1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 46;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s32,
47 GILLT_s64,
48 GILLT_v4s8,
49 GILLT_v16s8,
50 GILLT_v2s16,
51 GILLT_v8s16,
52 GILLT_v4s32,
53 GILLT_v2s64,
54};
55const static size_t NumTypeObjects = 8;
56const static LLT TypeObjects[] = {
57 LLT::scalar(32),
58 LLT::scalar(64),
59 LLT::vector(ElementCount::getFixed(4), LLT::scalar(8)),
60 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
61 LLT::vector(ElementCount::getFixed(2), LLT::scalar(16)),
62 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
63 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
64 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
65};
66
67// Bits for subtarget features that participate in instruction matching.
68enum SubtargetFeatureBits : uint8_t {
69 Feature_IsPTR64bitBit = 23,
70 Feature_UseCompactBranchesBit = 41,
71 Feature_HasMips2Bit = 7,
72 Feature_HasMips3Bit = 18,
73 Feature_HasMips4_32Bit = 26,
74 Feature_NotMips4_32Bit = 27,
75 Feature_HasMips4_32r2Bit = 19,
76 Feature_HasMips32Bit = 3,
77 Feature_HasMips32r2Bit = 6,
78 Feature_HasMips32r6Bit = 28,
79 Feature_NotMips32r6Bit = 4,
80 Feature_IsGP64bitBit = 21,
81 Feature_HasMips64Bit = 24,
82 Feature_HasMips64r2Bit = 22,
83 Feature_HasMips64r6Bit = 29,
84 Feature_NotMips64r6Bit = 5,
85 Feature_InMips16ModeBit = 30,
86 Feature_NotInMips16ModeBit = 0,
87 Feature_HasCnMipsBit = 25,
88 Feature_NotCnMipsBit = 8,
89 Feature_IsSym32Bit = 38,
90 Feature_IsSym64Bit = 39,
91 Feature_IsN64Bit = 40,
92 Feature_RelocNotPICBit = 10,
93 Feature_RelocPICBit = 36,
94 Feature_HasStdEncBit = 1,
95 Feature_NotDSPBit = 12,
96 Feature_InMicroMipsBit = 34,
97 Feature_NotInMicroMipsBit = 2,
98 Feature_IsLEBit = 42,
99 Feature_IsBEBit = 43,
100 Feature_HasEVABit = 35,
101 Feature_HasMSABit = 33,
102 Feature_HasMadd4Bit = 20,
103 Feature_UseIndirectJumpsHazardBit = 13,
104 Feature_NoIndirectJumpGuardsBit = 11,
105 Feature_IsR5900Bit = 37,
106 Feature_NotR5900Bit = 9,
107 Feature_IsFP64bitBit = 17,
108 Feature_NotFP64bitBit = 16,
109 Feature_IsNotSingleFloatBit = 15,
110 Feature_IsNotSoftFloatBit = 14,
111 Feature_HasDSPBit = 31,
112 Feature_HasDSPR2Bit = 32,
113 Feature_HwMode1Bit = 45,
114 Feature_HwMode0Bit = 44,
115};
116
117PredicateBitset MipsInstructionSelector::
118computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
119 PredicateBitset Features{};
120 if (Subtarget->isABI_N64())
121 Features.set(Feature_IsPTR64bitBit);
122 if (Subtarget->useCompactBranches())
123 Features.set(Feature_UseCompactBranchesBit);
124 if (Subtarget->hasMips2())
125 Features.set(Feature_HasMips2Bit);
126 if (Subtarget->hasMips3())
127 Features.set(Feature_HasMips3Bit);
128 if (Subtarget->hasMips4_32())
129 Features.set(Feature_HasMips4_32Bit);
130 if (!Subtarget->hasMips4_32())
131 Features.set(Feature_NotMips4_32Bit);
132 if (Subtarget->hasMips4_32r2())
133 Features.set(Feature_HasMips4_32r2Bit);
134 if (Subtarget->hasMips32())
135 Features.set(Feature_HasMips32Bit);
136 if (Subtarget->hasMips32r2())
137 Features.set(Feature_HasMips32r2Bit);
138 if (Subtarget->hasMips32r6())
139 Features.set(Feature_HasMips32r6Bit);
140 if (!Subtarget->hasMips32r6())
141 Features.set(Feature_NotMips32r6Bit);
142 if (Subtarget->isGP64bit())
143 Features.set(Feature_IsGP64bitBit);
144 if (Subtarget->hasMips64())
145 Features.set(Feature_HasMips64Bit);
146 if (Subtarget->hasMips64r2())
147 Features.set(Feature_HasMips64r2Bit);
148 if (Subtarget->hasMips64r6())
149 Features.set(Feature_HasMips64r6Bit);
150 if (!Subtarget->hasMips64r6())
151 Features.set(Feature_NotMips64r6Bit);
152 if (Subtarget->inMips16Mode())
153 Features.set(Feature_InMips16ModeBit);
154 if (!Subtarget->inMips16Mode())
155 Features.set(Feature_NotInMips16ModeBit);
156 if (Subtarget->hasCnMips())
157 Features.set(Feature_HasCnMipsBit);
158 if (!Subtarget->hasCnMips())
159 Features.set(Feature_NotCnMipsBit);
160 if (Subtarget->hasSym32())
161 Features.set(Feature_IsSym32Bit);
162 if (!Subtarget->hasSym32())
163 Features.set(Feature_IsSym64Bit);
164 if (Subtarget->isABI_N64())
165 Features.set(Feature_IsN64Bit);
166 if (!TM.isPositionIndependent())
167 Features.set(Feature_RelocNotPICBit);
168 if (TM.isPositionIndependent())
169 Features.set(Feature_RelocPICBit);
170 if (Subtarget->hasStandardEncoding())
171 Features.set(Feature_HasStdEncBit);
172 if (!Subtarget->hasDSP())
173 Features.set(Feature_NotDSPBit);
174 if (Subtarget->inMicroMipsMode())
175 Features.set(Feature_InMicroMipsBit);
176 if (!Subtarget->inMicroMipsMode())
177 Features.set(Feature_NotInMicroMipsBit);
178 if (Subtarget->isLittle())
179 Features.set(Feature_IsLEBit);
180 if (!Subtarget->isLittle())
181 Features.set(Feature_IsBEBit);
182 if (Subtarget->hasEVA())
183 Features.set(Feature_HasEVABit);
184 if (Subtarget->hasMSA())
185 Features.set(Feature_HasMSABit);
186 if (!Subtarget->disableMadd4())
187 Features.set(Feature_HasMadd4Bit);
188 if (Subtarget->useIndirectJumpsHazard())
189 Features.set(Feature_UseIndirectJumpsHazardBit);
190 if (!Subtarget->useIndirectJumpsHazard())
191 Features.set(Feature_NoIndirectJumpGuardsBit);
192 if (Subtarget->isR5900())
193 Features.set(Feature_IsR5900Bit);
194 if (!Subtarget->isR5900())
195 Features.set(Feature_NotR5900Bit);
196 if (Subtarget->isFP64bit())
197 Features.set(Feature_IsFP64bitBit);
198 if (!Subtarget->isFP64bit())
199 Features.set(Feature_NotFP64bitBit);
200 if (!Subtarget->isSingleFloat())
201 Features.set(Feature_IsNotSingleFloatBit);
202 if (!Subtarget->useSoftFloat())
203 Features.set(Feature_IsNotSoftFloatBit);
204 if (Subtarget->hasDSP())
205 Features.set(Feature_HasDSPBit);
206 if (Subtarget->hasDSPR2())
207 Features.set(Feature_HasDSPR2Bit);
208 if (!((Subtarget->isABI_N64())))
209 Features.set(Feature_HwMode1Bit);
210 if ((Subtarget->isABI_N64()))
211 Features.set(Feature_HwMode0Bit);
212 return Features;
213}
214
215void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
216 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
217}
218PredicateBitset MipsInstructionSelector::
219computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
220 PredicateBitset Features{};
221 return Features;
222}
223
224// Feature bitsets.
225enum {
226 GIFBS_Invalid,
227 GIFBS_HasCnMips,
228 GIFBS_HasDSP,
229 GIFBS_HasDSPR2,
230 GIFBS_HasMSA,
231 GIFBS_InMicroMips,
232 GIFBS_InMips16Mode,
233 GIFBS_NotInMips16Mode,
234 GIFBS_HasDSP_InMicroMips,
235 GIFBS_HasDSP_NotInMicroMips,
236 GIFBS_HasDSPR2_InMicroMips,
237 GIFBS_HasMSA_HasStdEnc,
238 GIFBS_HasMSA_IsBE,
239 GIFBS_HasMSA_IsLE,
240 GIFBS_HasMips32r6_HasStdEnc,
241 GIFBS_HasMips32r6_InMicroMips,
242 GIFBS_HasMips64r2_HasStdEnc,
243 GIFBS_HasMips64r6_HasStdEnc,
244 GIFBS_HasStdEnc_IsNotSoftFloat,
245 GIFBS_HasStdEnc_NotInMicroMips,
246 GIFBS_HasStdEnc_NotMips4_32,
247 GIFBS_InMicroMips_IsNotSoftFloat,
248 GIFBS_InMicroMips_NotMips32r6,
249 GIFBS_IsFP64bit_IsNotSingleFloat,
250 GIFBS_IsGP64bit_NotInMips16Mode,
251 GIFBS_IsNotSingleFloat_NotFP64bit,
252 GIFBS_HasMSA_HasMips64_HasStdEnc,
253 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
254 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
255 GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
256 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
257 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
258 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
259 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
260 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
261 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
262 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
263 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat,
264 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit,
265 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
266 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
267 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
268 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
269 GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat,
270 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
271 GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat,
272 GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit,
273 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
274 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
275 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
276 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
277 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
278 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips,
279 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32,
280 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips,
281 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32,
282 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
283 GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit,
284 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6,
285 GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode,
286 GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
287 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
288 GIFBS_HasMips32r6_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode,
289 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_NotInMips16Mode_UseIndirectJumpsHazard,
290 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
291 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
292 GIFBS_HasMips64r6_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode,
293 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_NotInMips16Mode_UseIndirectJumpsHazard,
294 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
295 GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
296 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
297 GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
298 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
299 GIFBS_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6,
300 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
301 GIFBS_HasMips3_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6,
302 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6_UseIndirectJumpsHazard,
303 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
304 GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
305 GIFBS_HasMips32r2_HasStdEnc_IsPTR64bit_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6_UseIndirectJumpsHazard,
306 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
307 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
308};
309constexpr static PredicateBitset FeatureBitsets[] {
310 {}, // GIFBS_Invalid
311 {Feature_HasCnMipsBit, },
312 {Feature_HasDSPBit, },
313 {Feature_HasDSPR2Bit, },
314 {Feature_HasMSABit, },
315 {Feature_InMicroMipsBit, },
316 {Feature_InMips16ModeBit, },
317 {Feature_NotInMips16ModeBit, },
318 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
319 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
320 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
321 {Feature_HasMSABit, Feature_HasStdEncBit, },
322 {Feature_HasMSABit, Feature_IsBEBit, },
323 {Feature_HasMSABit, Feature_IsLEBit, },
324 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
325 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
326 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
327 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
328 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
329 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
330 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
331 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
332 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
333 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
334 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
335 {Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
336 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
337 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
338 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
339 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
340 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
341 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
342 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
343 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
344 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
345 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
346 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
347 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
348 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
349 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
350 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
351 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
352 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
353 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
354 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
355 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
356 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
357 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
358 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
359 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
360 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
361 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
362 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, },
363 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, },
364 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
365 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
366 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
367 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
368 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
369 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
370 {Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
371 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
372 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NoIndirectJumpGuardsBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, },
373 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_UseIndirectJumpsHazardBit, },
374 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
375 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
376 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NoIndirectJumpGuardsBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, },
377 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_UseIndirectJumpsHazardBit, },
378 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
379 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
380 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
381 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
382 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
383 {Feature_HasStdEncBit, Feature_NoIndirectJumpGuardsBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
384 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
385 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NoIndirectJumpGuardsBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
386 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_UseIndirectJumpsHazardBit, },
387 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
388 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
389 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, Feature_NotInMips16ModeBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_UseIndirectJumpsHazardBit, },
390 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
391 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
392};
393
394// ComplexPattern predicates.
395enum {
396 GICP_Invalid,
397};
398// See constructor for table contents
399
400MipsInstructionSelector::ComplexMatcherMemFn
401MipsInstructionSelector::ComplexPredicateFns[] = {
402 nullptr, // GICP_Invalid
403};
404
405// PatFrag predicates.
406enum {
407 GICXXPred_MI_Predicate_fadd_contract = GICXXPred_Invalid + 1,
408 GICXXPred_MI_Predicate_ffloor_nnan,
409 GICXXPred_MI_Predicate_fmul_contract,
410 GICXXPred_MI_Predicate_fsub_contract,
411 GICXXPred_MI_Predicate_or_disjoint,
412};
413bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
414 const MachineFunction &MF = *MI.getParent()->getParent();
415 const MachineRegisterInfo &MRI = MF.getRegInfo();
416 const auto &Operands = State.RecordedOperands;
417 (void)Operands;
418 (void)MRI;
419 switch (PredicateID) {
420 case GICXXPred_MI_Predicate_fadd_contract: {
421
422 return MI.getFlag(MachineInstr::FmContract);
423
424 }
425 case GICXXPred_MI_Predicate_ffloor_nnan: {
426
427 return MI.getFlag(MachineInstr::FmNoNans);
428
429 }
430 case GICXXPred_MI_Predicate_fmul_contract: {
431
432 return MI.getFlag(MachineInstr::FmContract);
433
434 }
435 case GICXXPred_MI_Predicate_fsub_contract: {
436
437 return MI.getFlag(MachineInstr::FmContract);
438
439 }
440 case GICXXPred_MI_Predicate_or_disjoint: {
441
442 return MI.getFlag(MachineInstr::Disjoint);
443
444 }
445 }
446 llvm_unreachable("Unknown predicate");
447 return false;
448}
449// PatFrag predicates.
450bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
451 const auto &Operands = State.RecordedOperands;
452 Register Reg = MO.getReg();
453 (void)Operands;
454 (void)Reg;
455 llvm_unreachable("Unknown predicate");
456 return false;
457}
458// PatFrag predicates.
459enum {
460 GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1,
461 GICXXPred_I64_Predicate_Float8E4M3FN,
462 GICXXPred_I64_Predicate_Float8E5M2,
463 GICXXPred_I64_Predicate_NearestTiesToEven,
464 GICXXPred_I64_Predicate_immLi16,
465 GICXXPred_I64_Predicate_immSExt6,
466 GICXXPred_I64_Predicate_immSExt10,
467 GICXXPred_I64_Predicate_immSExtAddiur2,
468 GICXXPred_I64_Predicate_immSExtAddius5,
469 GICXXPred_I64_Predicate_immZExt1,
470 GICXXPred_I64_Predicate_immZExt1Ptr,
471 GICXXPred_I64_Predicate_immZExt2,
472 GICXXPred_I64_Predicate_immZExt2Lsa,
473 GICXXPred_I64_Predicate_immZExt2Ptr,
474 GICXXPred_I64_Predicate_immZExt2Shift,
475 GICXXPred_I64_Predicate_immZExt3,
476 GICXXPred_I64_Predicate_immZExt3Ptr,
477 GICXXPred_I64_Predicate_immZExt4,
478 GICXXPred_I64_Predicate_immZExt4Ptr,
479 GICXXPred_I64_Predicate_immZExt5,
480 GICXXPred_I64_Predicate_immZExt5_64,
481 GICXXPred_I64_Predicate_immZExt6,
482 GICXXPred_I64_Predicate_immZExt8,
483 GICXXPred_I64_Predicate_immZExt10,
484 GICXXPred_I64_Predicate_immZExtAndi16,
485 GICXXPred_I64_Predicate_immi32Cst7,
486 GICXXPred_I64_Predicate_immi32Cst15,
487 GICXXPred_I64_Predicate_immi32Cst31,
488 GICXXPred_I64_Predicate_timmSExt6,
489 GICXXPred_I64_Predicate_timmZExt1,
490 GICXXPred_I64_Predicate_timmZExt1Ptr,
491 GICXXPred_I64_Predicate_timmZExt2,
492 GICXXPred_I64_Predicate_timmZExt2Ptr,
493 GICXXPred_I64_Predicate_timmZExt3,
494 GICXXPred_I64_Predicate_timmZExt3Ptr,
495 GICXXPred_I64_Predicate_timmZExt4,
496 GICXXPred_I64_Predicate_timmZExt4Ptr,
497 GICXXPred_I64_Predicate_timmZExt5,
498 GICXXPred_I64_Predicate_timmZExt6,
499 GICXXPred_I64_Predicate_timmZExt8,
500 GICXXPred_I64_Predicate_timmZExt10,
501};
502bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
503 switch (PredicateID) {
504 case GICXXPred_I64_Predicate_FPNoSaturation: {
505 return Imm == 0;
506 }
507 case GICXXPred_I64_Predicate_Float8E4M3FN: {
508 return Imm == APFloatBase::S_Float8E4M3FN;
509 }
510 case GICXXPred_I64_Predicate_Float8E5M2: {
511 return Imm == APFloatBase::S_Float8E5M2;
512 }
513 case GICXXPred_I64_Predicate_NearestTiesToEven: {
514 return Imm == static_cast<int>(RoundingMode::NearestTiesToEven);
515 }
516 case GICXXPred_I64_Predicate_immLi16: {
517 return Imm >= -1 && Imm <= 126;
518 }
519 case GICXXPred_I64_Predicate_immSExt6: {
520 return isInt<6>(Imm);
521 }
522 case GICXXPred_I64_Predicate_immSExt10: {
523 return isInt<10>(Imm);
524 }
525 case GICXXPred_I64_Predicate_immSExtAddiur2: {
526 return Imm == 1 || Imm == -1 ||
527 ((Imm % 4 == 0) &&
528 Imm < 28 && Imm > 0);
529 }
530 case GICXXPred_I64_Predicate_immSExtAddius5: {
531 return Imm >= -8 && Imm <= 7;
532 }
533 case GICXXPred_I64_Predicate_immZExt1: {
534 return isUInt<1>(Imm);
535 }
536 case GICXXPred_I64_Predicate_immZExt1Ptr: {
537 return isUInt<1>(Imm);
538 }
539 case GICXXPred_I64_Predicate_immZExt2: {
540 return isUInt<2>(Imm);
541 }
542 case GICXXPred_I64_Predicate_immZExt2Lsa: {
543 return isUInt<2>(Imm - 1);
544 }
545 case GICXXPred_I64_Predicate_immZExt2Ptr: {
546 return isUInt<2>(Imm);
547 }
548 case GICXXPred_I64_Predicate_immZExt2Shift: {
549 return Imm >= 1 && Imm <= 8;
550 }
551 case GICXXPred_I64_Predicate_immZExt3: {
552 return isUInt<3>(Imm);
553 }
554 case GICXXPred_I64_Predicate_immZExt3Ptr: {
555 return isUInt<3>(Imm);
556 }
557 case GICXXPred_I64_Predicate_immZExt4: {
558 return isUInt<4>(Imm);
559 }
560 case GICXXPred_I64_Predicate_immZExt4Ptr: {
561 return isUInt<4>(Imm);
562 }
563 case GICXXPred_I64_Predicate_immZExt5: {
564 return Imm == (Imm & 0x1f);
565 }
566 case GICXXPred_I64_Predicate_immZExt5_64: {
567 return Imm == (Imm & 0x1f);
568 }
569 case GICXXPred_I64_Predicate_immZExt6: {
570 return Imm == (Imm & 0x3f);
571 }
572 case GICXXPred_I64_Predicate_immZExt8: {
573 return isUInt<8>(Imm);
574 }
575 case GICXXPred_I64_Predicate_immZExt10: {
576 return isUInt<10>(Imm);
577 }
578 case GICXXPred_I64_Predicate_immZExtAndi16: {
579 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
580 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
581 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
582 }
583 case GICXXPred_I64_Predicate_immi32Cst7: {
584 return isUInt<32>(Imm) && Imm == 7;
585 }
586 case GICXXPred_I64_Predicate_immi32Cst15: {
587 return isUInt<32>(Imm) && Imm == 15;
588 }
589 case GICXXPred_I64_Predicate_immi32Cst31: {
590 return isUInt<32>(Imm) && Imm == 31;
591 }
592 case GICXXPred_I64_Predicate_timmSExt6: {
593 return isInt<6>(Imm);
594 }
595 case GICXXPred_I64_Predicate_timmZExt1: {
596 return isUInt<1>(Imm);
597 }
598 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
599 return isUInt<1>(Imm);
600 }
601 case GICXXPred_I64_Predicate_timmZExt2: {
602 return isUInt<2>(Imm);
603 }
604 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
605 return isUInt<2>(Imm);
606 }
607 case GICXXPred_I64_Predicate_timmZExt3: {
608 return isUInt<3>(Imm);
609 }
610 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
611 return isUInt<3>(Imm);
612 }
613 case GICXXPred_I64_Predicate_timmZExt4: {
614 return isUInt<4>(Imm);
615 }
616 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
617 return isUInt<4>(Imm);
618 }
619 case GICXXPred_I64_Predicate_timmZExt5: {
620 return Imm == (Imm & 0x1f);
621 }
622 case GICXXPred_I64_Predicate_timmZExt6: {
623 return Imm == (Imm & 0x3f);
624 }
625 case GICXXPred_I64_Predicate_timmZExt8: {
626 return isUInt<8>(Imm);
627 }
628 case GICXXPred_I64_Predicate_timmZExt10: {
629 return isUInt<10>(Imm);
630 }
631 }
632 llvm_unreachable("Unknown predicate");
633 return false;
634}
635// PatFrag predicates.
636bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
637 llvm_unreachable("Unknown predicate");
638 return false;
639}
640// PatFrag predicates.
641enum {
642 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
643 GICXXPred_APInt_Predicate_imm32ZExt16,
644};
645bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
646 switch (PredicateID) {
647 case GICXXPred_APInt_Predicate_imm32SExt16: {
648 return isInt<16>(Imm.getSExtValue());
649 }
650 case GICXXPred_APInt_Predicate_imm32ZExt16: {
651
652 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
653
654 }
655 }
656 llvm_unreachable("Unknown predicate");
657 return false;
658}
659bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
660 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
661 return false;
662}
663// Custom renderers.
664enum {
665 GICR_Invalid,
666 GICR_renderFrameIndex,
667};
668MipsInstructionSelector::CustomRendererFn
669MipsInstructionSelector::CustomRenderers[] = {
670 nullptr, // GICR_Invalid
671 &MipsInstructionSelector::renderFrameIndex,
672};
673
674bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
675 const PredicateBitset AvailableFeatures = getAvailableFeatures();
676 MachineIRBuilder B(I);
677 State.MIs.clear();
678 State.MIs.push_back(&I);
679
680 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
681 return true;
682 }
683
684 return false;
685}
686
687bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
688 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
689}
690#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
691#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
692#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
693#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
694#else
695#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
696#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
697#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
698#endif
699const uint8_t *MipsInstructionSelector::getMatchTable() const {
700 constexpr static uint8_t MatchTable0[] = {
701 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(312), /*)*//*default:*//*Label 85*/ GIMT_Encode4(69079),
702 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1038),
703 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2319),
704 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2993),
705 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3432),
706 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3694),
707 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(3956),
708 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4218), GIMT_Encode4(0), GIMT_Encode4(0),
709 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4480),
710 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5014),
711 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5399), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
712 /* 118 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6236),
713 /* 122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6335), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
714 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6670), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
715 /* 186 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(10754),
716 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(10818),
717 /* 194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(10885), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
718 /* 230 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(10952),
719 /* 234 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11140),
720 /* 238 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11306),
721 /* 242 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11472),
722 /* 246 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(11638),
723 /* 250 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(11804),
724 /* 254 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(11970),
725 /* 258 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12136),
726 /* 262 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12302),
727 /* 266 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12468),
728 /* 270 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(12634),
729 /* 274 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(12800), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
730 /* 334 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(12966),
731 /* 338 */ /*TargetOpcode::G_BRINDIRECT*//*Label 29*/ GIMT_Encode4(19130), GIMT_Encode4(0),
732 /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 30*/ GIMT_Encode4(19365),
733 /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 31*/ GIMT_Encode4(33307), GIMT_Encode4(0), GIMT_Encode4(0),
734 /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 32*/ GIMT_Encode4(38267),
735 /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 33*/ GIMT_Encode4(38332), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
736 /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 34*/ GIMT_Encode4(38395), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
737 /* 398 */ /*TargetOpcode::G_SEXT*//*Label 35*/ GIMT_Encode4(38454),
738 /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 36*/ GIMT_Encode4(39911),
739 /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 37*/ GIMT_Encode4(40230),
740 /* 410 */ /*TargetOpcode::G_SHL*//*Label 38*/ GIMT_Encode4(40427),
741 /* 414 */ /*TargetOpcode::G_LSHR*//*Label 39*/ GIMT_Encode4(42202),
742 /* 418 */ /*TargetOpcode::G_ASHR*//*Label 40*/ GIMT_Encode4(43977), GIMT_Encode4(0), GIMT_Encode4(0),
743 /* 430 */ /*TargetOpcode::G_ROTR*//*Label 41*/ GIMT_Encode4(45711), GIMT_Encode4(0),
744 /* 438 */ /*TargetOpcode::G_ICMP*//*Label 42*/ GIMT_Encode4(45994),
745 /* 442 */ /*TargetOpcode::G_FCMP*//*Label 43*/ GIMT_Encode4(48488), GIMT_Encode4(0), GIMT_Encode4(0),
746 /* 454 */ /*TargetOpcode::G_SELECT*//*Label 44*/ GIMT_Encode4(50015), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
747 /* 498 */ /*TargetOpcode::G_UMULH*//*Label 45*/ GIMT_Encode4(59725),
748 /* 502 */ /*TargetOpcode::G_SMULH*//*Label 46*/ GIMT_Encode4(59831), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
749 /* 562 */ /*TargetOpcode::G_FADD*//*Label 47*/ GIMT_Encode4(59937),
750 /* 566 */ /*TargetOpcode::G_FSUB*//*Label 48*/ GIMT_Encode4(61249),
751 /* 570 */ /*TargetOpcode::G_FMUL*//*Label 49*/ GIMT_Encode4(62079),
752 /* 574 */ /*TargetOpcode::G_FMA*//*Label 50*/ GIMT_Encode4(62589), GIMT_Encode4(0),
753 /* 582 */ /*TargetOpcode::G_FDIV*//*Label 51*/ GIMT_Encode4(62689), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
754 /* 606 */ /*TargetOpcode::G_FEXP2*//*Label 52*/ GIMT_Encode4(63011), GIMT_Encode4(0), GIMT_Encode4(0),
755 /* 618 */ /*TargetOpcode::G_FLOG2*//*Label 53*/ GIMT_Encode4(63083), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
756 /* 634 */ /*TargetOpcode::G_FNEG*//*Label 54*/ GIMT_Encode4(63155),
757 /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 55*/ GIMT_Encode4(63333),
758 /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 56*/ GIMT_Encode4(63448),
759 /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 57*/ GIMT_Encode4(63555),
760 /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 58*/ GIMT_Encode4(63627),
761 /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 59*/ GIMT_Encode4(63699),
762 /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 60*/ GIMT_Encode4(63981), GIMT_Encode4(0), GIMT_Encode4(0),
763 /* 670 */ /*TargetOpcode::G_FABS*//*Label 61*/ GIMT_Encode4(64053), GIMT_Encode4(0), GIMT_Encode4(0),
764 /* 682 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 62*/ GIMT_Encode4(64293),
765 /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 63*/ GIMT_Encode4(64365),
766 /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 64*/ GIMT_Encode4(64435),
767 /* 694 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 65*/ GIMT_Encode4(64505),
768 /* 698 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 66*/ GIMT_Encode4(64575), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
769 /* 758 */ /*TargetOpcode::G_SMIN*//*Label 67*/ GIMT_Encode4(64645),
770 /* 762 */ /*TargetOpcode::G_SMAX*//*Label 68*/ GIMT_Encode4(64809),
771 /* 766 */ /*TargetOpcode::G_UMIN*//*Label 69*/ GIMT_Encode4(64973),
772 /* 770 */ /*TargetOpcode::G_UMAX*//*Label 70*/ GIMT_Encode4(65137), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
773 /* 786 */ /*TargetOpcode::G_BR*//*Label 71*/ GIMT_Encode4(65301), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
774 /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(65419),
775 /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 73*/ GIMT_Encode4(66011), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
776 /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 74*/ GIMT_Encode4(66062), GIMT_Encode4(0), GIMT_Encode4(0),
777 /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 75*/ GIMT_Encode4(66553),
778 /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 76*/ GIMT_Encode4(66753), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
779 /* 922 */ /*TargetOpcode::G_FSQRT*//*Label 77*/ GIMT_Encode4(66914), GIMT_Encode4(0),
780 /* 930 */ /*TargetOpcode::G_FRINT*//*Label 78*/ GIMT_Encode4(67178), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
781 /* 962 */ /*TargetOpcode::G_STRICT_FADD*//*Label 79*/ GIMT_Encode4(67334),
782 /* 966 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 80*/ GIMT_Encode4(68174),
783 /* 970 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 81*/ GIMT_Encode4(68664),
784 /* 974 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 82*/ GIMT_Encode4(68794), GIMT_Encode4(0), GIMT_Encode4(0),
785 /* 986 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 83*/ GIMT_Encode4(68924), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
786 /* 1034 */ /*TargetOpcode::G_TRAP*//*Label 84*/ GIMT_Encode4(69036),
787 /* 1038 */ // Label 0: @1038
788 /* 1038 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 94*/ GIMT_Encode4(2318),
789 /* 1049 */ /*GILLT_s32*//*Label 86*/ GIMT_Encode4(1081),
790 /* 1053 */ /*GILLT_s64*//*Label 87*/ GIMT_Encode4(1479),
791 /* 1057 */ /*GILLT_v4s8*//*Label 88*/ GIMT_Encode4(1644),
792 /* 1061 */ /*GILLT_v16s8*//*Label 89*/ GIMT_Encode4(1675),
793 /* 1065 */ /*GILLT_v2s16*//*Label 90*/ GIMT_Encode4(1828),
794 /* 1069 */ /*GILLT_v8s16*//*Label 91*/ GIMT_Encode4(1859),
795 /* 1073 */ /*GILLT_v4s32*//*Label 92*/ GIMT_Encode4(2012),
796 /* 1077 */ /*GILLT_v2s64*//*Label 93*/ GIMT_Encode4(2165),
797 /* 1081 */ // Label 86: @1081
798 /* 1081 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1478),
799 /* 1086 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
800 /* 1089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
801 /* 1092 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1265),
802 /* 1097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
803 /* 1101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 97*/ GIMT_Encode4(1163), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2707 //
804 /* 1108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
805 /* 1112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
806 /* 1116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
807 /* 1120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
808 /* 1124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
809 /* 1129 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
810 /* 1133 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
811 /* 1137 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
812 /* 1141 */ // MIs[2] Operand 1
813 /* 1141 */ // No operand predicates
814 /* 1141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
815 /* 1145 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
816 /* 1147 */ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
817 /* 1147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
818 /* 1150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
819 /* 1152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
820 /* 1156 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
821 /* 1158 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
822 /* 1161 */ GIR_RootConstrainSelectedInstOperands,
823 /* 1162 */ // GIR_Coverage, 2707,
824 /* 1162 */ GIR_EraseRootFromParent_Done,
825 /* 1163 */ // Label 97: @1163
826 /* 1163 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1264),
827 /* 1168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
828 /* 1172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 99*/ GIMT_Encode4(1230), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 901 //
829 /* 1179 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
830 /* 1183 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
831 /* 1187 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
832 /* 1191 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
833 /* 1195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
834 /* 1200 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
835 /* 1204 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
836 /* 1208 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
837 /* 1212 */ // MIs[2] Operand 1
838 /* 1212 */ // No operand predicates
839 /* 1212 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
840 /* 1214 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
841 /* 1214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
842 /* 1217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
843 /* 1219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
844 /* 1223 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
845 /* 1225 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
846 /* 1228 */ GIR_RootConstrainSelectedInstOperands,
847 /* 1229 */ // GIR_Coverage, 901,
848 /* 1229 */ GIR_EraseRootFromParent_Done,
849 /* 1230 */ // Label 99: @1230
850 /* 1230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 100*/ GIMT_Encode4(1263), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 40 //
851 /* 1237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
852 /* 1241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
853 /* 1245 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
854 /* 1249 */ // MIs[1] Operand 1
855 /* 1249 */ // No operand predicates
856 /* 1249 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
857 /* 1251 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
858 /* 1251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
859 /* 1254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
860 /* 1256 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
861 /* 1258 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
862 /* 1261 */ GIR_RootConstrainSelectedInstOperands,
863 /* 1262 */ // GIR_Coverage, 40,
864 /* 1262 */ GIR_EraseRootFromParent_Done,
865 /* 1263 */ // Label 100: @1263
866 /* 1263 */ GIM_Reject,
867 /* 1264 */ // Label 98: @1264
868 /* 1264 */ GIM_Reject,
869 /* 1265 */ // Label 96: @1265
870 /* 1265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 101*/ GIMT_Encode4(1306), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2431 //
871 /* 1272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
872 /* 1276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
873 /* 1280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
874 /* 1284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
875 /* 1288 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
876 /* 1292 */ // MIs[1] Operand 1
877 /* 1292 */ // No operand predicates
878 /* 1292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
879 /* 1294 */ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
880 /* 1294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
881 /* 1297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
882 /* 1299 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
883 /* 1301 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
884 /* 1304 */ GIR_RootConstrainSelectedInstOperands,
885 /* 1305 */ // GIR_Coverage, 2431,
886 /* 1305 */ GIR_EraseRootFromParent_Done,
887 /* 1306 */ // Label 101: @1306
888 /* 1306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 102*/ GIMT_Encode4(1347), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2432 //
889 /* 1313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
890 /* 1317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
891 /* 1321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
892 /* 1325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
893 /* 1329 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
894 /* 1333 */ // MIs[1] Operand 1
895 /* 1333 */ // No operand predicates
896 /* 1333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
897 /* 1335 */ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
898 /* 1335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
899 /* 1338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
900 /* 1340 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
901 /* 1342 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
902 /* 1345 */ GIR_RootConstrainSelectedInstOperands,
903 /* 1346 */ // GIR_Coverage, 2432,
904 /* 1346 */ GIR_EraseRootFromParent_Done,
905 /* 1347 */ // Label 102: @1347
906 /* 1347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 103*/ GIMT_Encode4(1373), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1282 //
907 /* 1354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
908 /* 1358 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
909 /* 1362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
910 /* 1366 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
911 /* 1366 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
912 /* 1371 */ GIR_RootConstrainSelectedInstOperands,
913 /* 1372 */ // GIR_Coverage, 1282,
914 /* 1372 */ GIR_Done,
915 /* 1373 */ // Label 103: @1373
916 /* 1373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 104*/ GIMT_Encode4(1399), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 46 //
917 /* 1380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
918 /* 1384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
919 /* 1388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
920 /* 1392 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
921 /* 1392 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
922 /* 1397 */ GIR_RootConstrainSelectedInstOperands,
923 /* 1398 */ // GIR_Coverage, 46,
924 /* 1398 */ GIR_Done,
925 /* 1399 */ // Label 104: @1399
926 /* 1399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 105*/ GIMT_Encode4(1425), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1125 //
927 /* 1406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
928 /* 1410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
929 /* 1414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
930 /* 1418 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
931 /* 1418 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
932 /* 1423 */ GIR_RootConstrainSelectedInstOperands,
933 /* 1424 */ // GIR_Coverage, 1125,
934 /* 1424 */ GIR_Done,
935 /* 1425 */ // Label 105: @1425
936 /* 1425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 106*/ GIMT_Encode4(1451), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1138 //
937 /* 1432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
938 /* 1436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
939 /* 1440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
940 /* 1444 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
941 /* 1444 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
942 /* 1449 */ GIR_RootConstrainSelectedInstOperands,
943 /* 1450 */ // GIR_Coverage, 1138,
944 /* 1450 */ GIR_Done,
945 /* 1451 */ // Label 106: @1451
946 /* 1451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 107*/ GIMT_Encode4(1477), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2074 //
947 /* 1458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
948 /* 1462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
949 /* 1466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
950 /* 1470 */ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
951 /* 1470 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
952 /* 1475 */ GIR_RootConstrainSelectedInstOperands,
953 /* 1476 */ // GIR_Coverage, 2074,
954 /* 1476 */ GIR_Done,
955 /* 1477 */ // Label 107: @1477
956 /* 1477 */ GIM_Reject,
957 /* 1478 */ // Label 95: @1478
958 /* 1478 */ GIM_Reject,
959 /* 1479 */ // Label 87: @1479
960 /* 1479 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1643),
961 /* 1484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
962 /* 1487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
963 /* 1490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
964 /* 1494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 109*/ GIMT_Encode4(1556), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 2708 //
965 /* 1501 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
966 /* 1505 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
967 /* 1509 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
968 /* 1513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
969 /* 1517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
970 /* 1522 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
971 /* 1526 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
972 /* 1530 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
973 /* 1534 */ // MIs[2] Operand 1
974 /* 1534 */ // No operand predicates
975 /* 1534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
976 /* 1538 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
977 /* 1540 */ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
978 /* 1540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
979 /* 1543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
980 /* 1545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
981 /* 1549 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
982 /* 1551 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
983 /* 1554 */ GIR_RootConstrainSelectedInstOperands,
984 /* 1555 */ // GIR_Coverage, 2708,
985 /* 1555 */ GIR_EraseRootFromParent_Done,
986 /* 1556 */ // Label 109: @1556
987 /* 1556 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1642),
988 /* 1561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
989 /* 1565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1623), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 902 //
990 /* 1572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
991 /* 1576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
992 /* 1580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
993 /* 1584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
994 /* 1588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
995 /* 1593 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
996 /* 1597 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
997 /* 1601 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
998 /* 1605 */ // MIs[2] Operand 1
999 /* 1605 */ // No operand predicates
1000 /* 1605 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1001 /* 1607 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
1002 /* 1607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
1003 /* 1610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
1004 /* 1612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
1005 /* 1616 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
1006 /* 1618 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
1007 /* 1621 */ GIR_RootConstrainSelectedInstOperands,
1008 /* 1622 */ // GIR_Coverage, 902,
1009 /* 1622 */ GIR_EraseRootFromParent_Done,
1010 /* 1623 */ // Label 111: @1623
1011 /* 1623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 112*/ GIMT_Encode4(1641), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 257 //
1012 /* 1630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1013 /* 1634 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1014 /* 1634 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
1015 /* 1639 */ GIR_RootConstrainSelectedInstOperands,
1016 /* 1640 */ // GIR_Coverage, 257,
1017 /* 1640 */ GIR_Done,
1018 /* 1641 */ // Label 112: @1641
1019 /* 1641 */ GIM_Reject,
1020 /* 1642 */ // Label 110: @1642
1021 /* 1642 */ GIM_Reject,
1022 /* 1643 */ // Label 108: @1643
1023 /* 1643 */ GIM_Reject,
1024 /* 1644 */ // Label 88: @1644
1025 /* 1644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 113*/ GIMT_Encode4(1674), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2183 //
1026 /* 1651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1027 /* 1654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1028 /* 1657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1029 /* 1661 */ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1030 /* 1661 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
1031 /* 1666 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1032 /* 1672 */ GIR_RootConstrainSelectedInstOperands,
1033 /* 1673 */ // GIR_Coverage, 2183,
1034 /* 1673 */ GIR_Done,
1035 /* 1674 */ // Label 113: @1674
1036 /* 1674 */ GIM_Reject,
1037 /* 1675 */ // Label 89: @1675
1038 /* 1675 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1827),
1039 /* 1680 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1040 /* 1683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1041 /* 1686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1042 /* 1690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 115*/ GIMT_Encode4(1746), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2709 //
1043 /* 1697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1044 /* 1701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1045 /* 1705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1046 /* 1709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1047 /* 1713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1048 /* 1718 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1049 /* 1723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1050 /* 1727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1051 /* 1729 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1052 /* 1729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1053 /* 1732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1054 /* 1734 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1055 /* 1736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1056 /* 1740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1057 /* 1744 */ GIR_RootConstrainSelectedInstOperands,
1058 /* 1745 */ // GIR_Coverage, 2709,
1059 /* 1745 */ GIR_EraseRootFromParent_Done,
1060 /* 1746 */ // Label 115: @1746
1061 /* 1746 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1826),
1062 /* 1751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1063 /* 1755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 117*/ GIMT_Encode4(1807), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 907 //
1064 /* 1762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1065 /* 1766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1066 /* 1770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1067 /* 1774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1068 /* 1778 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1069 /* 1783 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1070 /* 1788 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1071 /* 1790 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1072 /* 1790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1073 /* 1793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1074 /* 1795 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1075 /* 1797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076 /* 1801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077 /* 1805 */ GIR_RootConstrainSelectedInstOperands,
1078 /* 1806 */ // GIR_Coverage, 907,
1079 /* 1806 */ GIR_EraseRootFromParent_Done,
1080 /* 1807 */ // Label 117: @1807
1081 /* 1807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1825), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 570 //
1082 /* 1814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1083 /* 1818 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1084 /* 1818 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1085 /* 1823 */ GIR_RootConstrainSelectedInstOperands,
1086 /* 1824 */ // GIR_Coverage, 570,
1087 /* 1824 */ GIR_Done,
1088 /* 1825 */ // Label 118: @1825
1089 /* 1825 */ GIM_Reject,
1090 /* 1826 */ // Label 116: @1826
1091 /* 1826 */ GIM_Reject,
1092 /* 1827 */ // Label 114: @1827
1093 /* 1827 */ GIM_Reject,
1094 /* 1828 */ // Label 90: @1828
1095 /* 1828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 119*/ GIMT_Encode4(1858), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2177 //
1096 /* 1835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1097 /* 1838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1098 /* 1841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1099 /* 1845 */ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1100 /* 1845 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
1101 /* 1850 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1102 /* 1856 */ GIR_RootConstrainSelectedInstOperands,
1103 /* 1857 */ // GIR_Coverage, 2177,
1104 /* 1857 */ GIR_Done,
1105 /* 1858 */ // Label 119: @1858
1106 /* 1858 */ GIM_Reject,
1107 /* 1859 */ // Label 91: @1859
1108 /* 1859 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2011),
1109 /* 1864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1110 /* 1867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1111 /* 1870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1112 /* 1874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 121*/ GIMT_Encode4(1930), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2710 //
1113 /* 1881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1114 /* 1885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1115 /* 1889 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1116 /* 1893 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1117 /* 1897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1118 /* 1902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1119 /* 1907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1120 /* 1911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1121 /* 1913 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1122 /* 1913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1123 /* 1916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1124 /* 1918 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1125 /* 1920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1126 /* 1924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1127 /* 1928 */ GIR_RootConstrainSelectedInstOperands,
1128 /* 1929 */ // GIR_Coverage, 2710,
1129 /* 1929 */ GIR_EraseRootFromParent_Done,
1130 /* 1930 */ // Label 121: @1930
1131 /* 1930 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2010),
1132 /* 1935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1133 /* 1939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 123*/ GIMT_Encode4(1991), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 908 //
1134 /* 1946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1135 /* 1950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1136 /* 1954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1137 /* 1958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1138 /* 1962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1139 /* 1967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1140 /* 1972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1141 /* 1974 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1142 /* 1974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1143 /* 1977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1144 /* 1979 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1145 /* 1981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1146 /* 1985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1147 /* 1989 */ GIR_RootConstrainSelectedInstOperands,
1148 /* 1990 */ // GIR_Coverage, 908,
1149 /* 1990 */ GIR_EraseRootFromParent_Done,
1150 /* 1991 */ // Label 123: @1991
1151 /* 1991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 124*/ GIMT_Encode4(2009), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 571 //
1152 /* 1998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1153 /* 2002 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1154 /* 2002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1155 /* 2007 */ GIR_RootConstrainSelectedInstOperands,
1156 /* 2008 */ // GIR_Coverage, 571,
1157 /* 2008 */ GIR_Done,
1158 /* 2009 */ // Label 124: @2009
1159 /* 2009 */ GIM_Reject,
1160 /* 2010 */ // Label 122: @2010
1161 /* 2010 */ GIM_Reject,
1162 /* 2011 */ // Label 120: @2011
1163 /* 2011 */ GIM_Reject,
1164 /* 2012 */ // Label 92: @2012
1165 /* 2012 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2164),
1166 /* 2017 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1167 /* 2020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1168 /* 2023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1169 /* 2027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 126*/ GIMT_Encode4(2083), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2711 //
1170 /* 2034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1171 /* 2038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1172 /* 2042 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1173 /* 2046 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1174 /* 2050 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1175 /* 2055 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1176 /* 2060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1177 /* 2064 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1178 /* 2066 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1179 /* 2066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1180 /* 2069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1181 /* 2071 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1182 /* 2073 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1183 /* 2077 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1184 /* 2081 */ GIR_RootConstrainSelectedInstOperands,
1185 /* 2082 */ // GIR_Coverage, 2711,
1186 /* 2082 */ GIR_EraseRootFromParent_Done,
1187 /* 2083 */ // Label 126: @2083
1188 /* 2083 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(2163),
1189 /* 2088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1190 /* 2092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2144), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 909 //
1191 /* 2099 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1192 /* 2103 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1193 /* 2107 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1194 /* 2111 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1195 /* 2115 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1196 /* 2120 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1197 /* 2125 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1198 /* 2127 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1199 /* 2127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1200 /* 2130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1201 /* 2132 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1202 /* 2134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1203 /* 2138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1204 /* 2142 */ GIR_RootConstrainSelectedInstOperands,
1205 /* 2143 */ // GIR_Coverage, 909,
1206 /* 2143 */ GIR_EraseRootFromParent_Done,
1207 /* 2144 */ // Label 128: @2144
1208 /* 2144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 129*/ GIMT_Encode4(2162), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 572 //
1209 /* 2151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1210 /* 2155 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1211 /* 2155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1212 /* 2160 */ GIR_RootConstrainSelectedInstOperands,
1213 /* 2161 */ // GIR_Coverage, 572,
1214 /* 2161 */ GIR_Done,
1215 /* 2162 */ // Label 129: @2162
1216 /* 2162 */ GIM_Reject,
1217 /* 2163 */ // Label 127: @2163
1218 /* 2163 */ GIM_Reject,
1219 /* 2164 */ // Label 125: @2164
1220 /* 2164 */ GIM_Reject,
1221 /* 2165 */ // Label 93: @2165
1222 /* 2165 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(2317),
1223 /* 2170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1224 /* 2173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1225 /* 2176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1226 /* 2180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 131*/ GIMT_Encode4(2236), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2712 //
1227 /* 2187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1228 /* 2191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1229 /* 2195 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1230 /* 2199 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1231 /* 2203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1232 /* 2208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1233 /* 2213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1234 /* 2217 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1235 /* 2219 */ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1236 /* 2219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1237 /* 2222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1238 /* 2224 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1239 /* 2226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1240 /* 2230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1241 /* 2234 */ GIR_RootConstrainSelectedInstOperands,
1242 /* 2235 */ // GIR_Coverage, 2712,
1243 /* 2235 */ GIR_EraseRootFromParent_Done,
1244 /* 2236 */ // Label 131: @2236
1245 /* 2236 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(2316),
1246 /* 2241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1247 /* 2245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(2297), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 910 //
1248 /* 2252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1249 /* 2256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1250 /* 2260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1251 /* 2264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1252 /* 2268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1253 /* 2273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1254 /* 2278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1255 /* 2280 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1256 /* 2280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1257 /* 2283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1258 /* 2285 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1259 /* 2287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1260 /* 2291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1261 /* 2295 */ GIR_RootConstrainSelectedInstOperands,
1262 /* 2296 */ // GIR_Coverage, 910,
1263 /* 2296 */ GIR_EraseRootFromParent_Done,
1264 /* 2297 */ // Label 133: @2297
1265 /* 2297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 134*/ GIMT_Encode4(2315), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 573 //
1266 /* 2304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1267 /* 2308 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1268 /* 2308 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
1269 /* 2313 */ GIR_RootConstrainSelectedInstOperands,
1270 /* 2314 */ // GIR_Coverage, 573,
1271 /* 2314 */ GIR_Done,
1272 /* 2315 */ // Label 134: @2315
1273 /* 2315 */ GIM_Reject,
1274 /* 2316 */ // Label 132: @2316
1275 /* 2316 */ GIM_Reject,
1276 /* 2317 */ // Label 130: @2317
1277 /* 2317 */ GIM_Reject,
1278 /* 2318 */ // Label 94: @2318
1279 /* 2318 */ GIM_Reject,
1280 /* 2319 */ // Label 1: @2319
1281 /* 2319 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 143*/ GIMT_Encode4(2992),
1282 /* 2330 */ /*GILLT_s32*//*Label 135*/ GIMT_Encode4(2362),
1283 /* 2334 */ /*GILLT_s64*//*Label 136*/ GIMT_Encode4(2533),
1284 /* 2338 */ /*GILLT_v4s8*//*Label 137*/ GIMT_Encode4(2566),
1285 /* 2342 */ /*GILLT_v16s8*//*Label 138*/ GIMT_Encode4(2597),
1286 /* 2346 */ /*GILLT_v2s16*//*Label 139*/ GIMT_Encode4(2688),
1287 /* 2350 */ /*GILLT_v8s16*//*Label 140*/ GIMT_Encode4(2719),
1288 /* 2354 */ /*GILLT_v4s32*//*Label 141*/ GIMT_Encode4(2810),
1289 /* 2358 */ /*GILLT_v2s64*//*Label 142*/ GIMT_Encode4(2901),
1290 /* 2362 */ // Label 135: @2362
1291 /* 2362 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2532),
1292 /* 2367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1293 /* 2370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1294 /* 2373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 145*/ GIMT_Encode4(2401), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2073 //
1295 /* 2380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1296 /* 2384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1297 /* 2388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1298 /* 2392 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1299 /* 2392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1300 /* 2395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1301 /* 2397 */ GIR_RootToRootCopy, /*OpIdx*/2, // r
1302 /* 2399 */ GIR_RootConstrainSelectedInstOperands,
1303 /* 2400 */ // GIR_Coverage, 2073,
1304 /* 2400 */ GIR_EraseRootFromParent_Done,
1305 /* 2401 */ // Label 145: @2401
1306 /* 2401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 146*/ GIMT_Encode4(2427), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1284 //
1307 /* 2408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1308 /* 2412 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1309 /* 2416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1310 /* 2420 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1311 /* 2420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1312 /* 2425 */ GIR_RootConstrainSelectedInstOperands,
1313 /* 2426 */ // GIR_Coverage, 1284,
1314 /* 2426 */ GIR_Done,
1315 /* 2427 */ // Label 146: @2427
1316 /* 2427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(2453), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 47 //
1317 /* 2434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1318 /* 2438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1319 /* 2442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1320 /* 2446 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1321 /* 2446 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1322 /* 2451 */ GIR_RootConstrainSelectedInstOperands,
1323 /* 2452 */ // GIR_Coverage, 47,
1324 /* 2452 */ GIR_Done,
1325 /* 2453 */ // Label 147: @2453
1326 /* 2453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(2479), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1129 //
1327 /* 2460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1328 /* 2464 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1329 /* 2468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1330 /* 2472 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1331 /* 2472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1332 /* 2477 */ GIR_RootConstrainSelectedInstOperands,
1333 /* 2478 */ // GIR_Coverage, 1129,
1334 /* 2478 */ GIR_Done,
1335 /* 2479 */ // Label 148: @2479
1336 /* 2479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 149*/ GIMT_Encode4(2505), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1139 //
1337 /* 2486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1338 /* 2490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1339 /* 2494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1340 /* 2498 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1341 /* 2498 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1342 /* 2503 */ GIR_RootConstrainSelectedInstOperands,
1343 /* 2504 */ // GIR_Coverage, 1139,
1344 /* 2504 */ GIR_Done,
1345 /* 2505 */ // Label 149: @2505
1346 /* 2505 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 150*/ GIMT_Encode4(2531), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2078 //
1347 /* 2512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1348 /* 2516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1349 /* 2520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1350 /* 2524 */ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1351 /* 2524 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1352 /* 2529 */ GIR_RootConstrainSelectedInstOperands,
1353 /* 2530 */ // GIR_Coverage, 2078,
1354 /* 2530 */ GIR_Done,
1355 /* 2531 */ // Label 150: @2531
1356 /* 2531 */ GIM_Reject,
1357 /* 2532 */ // Label 144: @2532
1358 /* 2532 */ GIM_Reject,
1359 /* 2533 */ // Label 136: @2533
1360 /* 2533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(2565), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 258 //
1361 /* 2540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1362 /* 2543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1363 /* 2546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1364 /* 2550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1365 /* 2554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1366 /* 2558 */ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1367 /* 2558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1368 /* 2563 */ GIR_RootConstrainSelectedInstOperands,
1369 /* 2564 */ // GIR_Coverage, 258,
1370 /* 2564 */ GIR_Done,
1371 /* 2565 */ // Label 151: @2565
1372 /* 2565 */ GIM_Reject,
1373 /* 2566 */ // Label 137: @2566
1374 /* 2566 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 152*/ GIMT_Encode4(2596), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2185 //
1375 /* 2573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1376 /* 2576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1377 /* 2579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1378 /* 2583 */ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1379 /* 2583 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1380 /* 2588 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1381 /* 2594 */ GIR_RootConstrainSelectedInstOperands,
1382 /* 2595 */ // GIR_Coverage, 2185,
1383 /* 2595 */ GIR_Done,
1384 /* 2596 */ // Label 152: @2596
1385 /* 2596 */ GIM_Reject,
1386 /* 2597 */ // Label 138: @2597
1387 /* 2597 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2687),
1388 /* 2602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1389 /* 2605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1390 /* 2608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1391 /* 2612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1392 /* 2616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 154*/ GIMT_Encode4(2668), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 963 //
1393 /* 2623 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1394 /* 2627 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1395 /* 2631 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1396 /* 2635 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1397 /* 2639 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1398 /* 2644 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1399 /* 2649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1400 /* 2651 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1401 /* 2651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1402 /* 2654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1403 /* 2656 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1404 /* 2658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1405 /* 2662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1406 /* 2666 */ GIR_RootConstrainSelectedInstOperands,
1407 /* 2667 */ // GIR_Coverage, 963,
1408 /* 2667 */ GIR_EraseRootFromParent_Done,
1409 /* 2668 */ // Label 154: @2668
1410 /* 2668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 155*/ GIMT_Encode4(2686), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1096 //
1411 /* 2675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1412 /* 2679 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1413 /* 2679 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1414 /* 2684 */ GIR_RootConstrainSelectedInstOperands,
1415 /* 2685 */ // GIR_Coverage, 1096,
1416 /* 2685 */ GIR_Done,
1417 /* 2686 */ // Label 155: @2686
1418 /* 2686 */ GIM_Reject,
1419 /* 2687 */ // Label 153: @2687
1420 /* 2687 */ GIM_Reject,
1421 /* 2688 */ // Label 139: @2688
1422 /* 2688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 156*/ GIMT_Encode4(2718), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2179 //
1423 /* 2695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1424 /* 2698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1425 /* 2701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1426 /* 2705 */ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1427 /* 2705 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1428 /* 2710 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1429 /* 2716 */ GIR_RootConstrainSelectedInstOperands,
1430 /* 2717 */ // GIR_Coverage, 2179,
1431 /* 2717 */ GIR_Done,
1432 /* 2718 */ // Label 156: @2718
1433 /* 2718 */ GIM_Reject,
1434 /* 2719 */ // Label 140: @2719
1435 /* 2719 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2809),
1436 /* 2724 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1437 /* 2727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1438 /* 2730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1439 /* 2734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1440 /* 2738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 158*/ GIMT_Encode4(2790), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 964 //
1441 /* 2745 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1442 /* 2749 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1443 /* 2753 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1444 /* 2757 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1445 /* 2761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1446 /* 2766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1447 /* 2771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1448 /* 2773 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1449 /* 2773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1450 /* 2776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1451 /* 2778 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1452 /* 2780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1453 /* 2784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1454 /* 2788 */ GIR_RootConstrainSelectedInstOperands,
1455 /* 2789 */ // GIR_Coverage, 964,
1456 /* 2789 */ GIR_EraseRootFromParent_Done,
1457 /* 2790 */ // Label 158: @2790
1458 /* 2790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 159*/ GIMT_Encode4(2808), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1097 //
1459 /* 2797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1460 /* 2801 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1461 /* 2801 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1462 /* 2806 */ GIR_RootConstrainSelectedInstOperands,
1463 /* 2807 */ // GIR_Coverage, 1097,
1464 /* 2807 */ GIR_Done,
1465 /* 2808 */ // Label 159: @2808
1466 /* 2808 */ GIM_Reject,
1467 /* 2809 */ // Label 157: @2809
1468 /* 2809 */ GIM_Reject,
1469 /* 2810 */ // Label 141: @2810
1470 /* 2810 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(2900),
1471 /* 2815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1472 /* 2818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1473 /* 2821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1474 /* 2825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1475 /* 2829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 161*/ GIMT_Encode4(2881), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 965 //
1476 /* 2836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1477 /* 2840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1478 /* 2844 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1479 /* 2848 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1480 /* 2852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1481 /* 2857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1482 /* 2862 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1483 /* 2864 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1484 /* 2864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1485 /* 2867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1486 /* 2869 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1487 /* 2871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1488 /* 2875 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1489 /* 2879 */ GIR_RootConstrainSelectedInstOperands,
1490 /* 2880 */ // GIR_Coverage, 965,
1491 /* 2880 */ GIR_EraseRootFromParent_Done,
1492 /* 2881 */ // Label 161: @2881
1493 /* 2881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 162*/ GIMT_Encode4(2899), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1098 //
1494 /* 2888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1495 /* 2892 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1496 /* 2892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1497 /* 2897 */ GIR_RootConstrainSelectedInstOperands,
1498 /* 2898 */ // GIR_Coverage, 1098,
1499 /* 2898 */ GIR_Done,
1500 /* 2899 */ // Label 162: @2899
1501 /* 2899 */ GIM_Reject,
1502 /* 2900 */ // Label 160: @2900
1503 /* 2900 */ GIM_Reject,
1504 /* 2901 */ // Label 142: @2901
1505 /* 2901 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(2991),
1506 /* 2906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1507 /* 2909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1508 /* 2912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1509 /* 2916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1510 /* 2920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 164*/ GIMT_Encode4(2972), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 966 //
1511 /* 2927 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1512 /* 2931 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1513 /* 2935 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1514 /* 2939 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1515 /* 2943 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1516 /* 2948 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1517 /* 2953 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1518 /* 2955 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1519 /* 2955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1520 /* 2958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1521 /* 2960 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1522 /* 2962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1523 /* 2966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1524 /* 2970 */ GIR_RootConstrainSelectedInstOperands,
1525 /* 2971 */ // GIR_Coverage, 966,
1526 /* 2971 */ GIR_EraseRootFromParent_Done,
1527 /* 2972 */ // Label 164: @2972
1528 /* 2972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 165*/ GIMT_Encode4(2990), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1099 //
1529 /* 2979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1530 /* 2983 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1531 /* 2983 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1532 /* 2988 */ GIR_RootConstrainSelectedInstOperands,
1533 /* 2989 */ // GIR_Coverage, 1099,
1534 /* 2989 */ GIR_Done,
1535 /* 2990 */ // Label 165: @2990
1536 /* 2990 */ GIM_Reject,
1537 /* 2991 */ // Label 163: @2991
1538 /* 2991 */ GIM_Reject,
1539 /* 2992 */ // Label 143: @2992
1540 /* 2992 */ GIM_Reject,
1541 /* 2993 */ // Label 2: @2993
1542 /* 2993 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 173*/ GIMT_Encode4(3431),
1543 /* 3004 */ /*GILLT_s32*//*Label 166*/ GIMT_Encode4(3036),
1544 /* 3008 */ /*GILLT_s64*//*Label 167*/ GIMT_Encode4(3185), GIMT_Encode4(0),
1545 /* 3016 */ /*GILLT_v16s8*//*Label 168*/ GIMT_Encode4(3268),
1546 /* 3020 */ /*GILLT_v2s16*//*Label 169*/ GIMT_Encode4(3301),
1547 /* 3024 */ /*GILLT_v8s16*//*Label 170*/ GIMT_Encode4(3332),
1548 /* 3028 */ /*GILLT_v4s32*//*Label 171*/ GIMT_Encode4(3365),
1549 /* 3032 */ /*GILLT_v2s64*//*Label 172*/ GIMT_Encode4(3398),
1550 /* 3036 */ // Label 166: @3036
1551 /* 3036 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3184),
1552 /* 3041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1553 /* 3044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1554 /* 3047 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(3145),
1555 /* 3052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1556 /* 3056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1557 /* 3060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1558 /* 3064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 176*/ GIMT_Encode4(3090), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 48 //
1559 /* 3071 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1560 /* 3071 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1561 /* 3076 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1562 /* 3082 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1563 /* 3088 */ GIR_RootConstrainSelectedInstOperands,
1564 /* 3089 */ // GIR_Coverage, 48,
1565 /* 3089 */ GIR_Done,
1566 /* 3090 */ // Label 176: @3090
1567 /* 3090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 177*/ GIMT_Encode4(3104), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 393 //
1568 /* 3097 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1569 /* 3097 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1570 /* 3102 */ GIR_RootConstrainSelectedInstOperands,
1571 /* 3103 */ // GIR_Coverage, 393,
1572 /* 3103 */ GIR_Done,
1573 /* 3104 */ // Label 177: @3104
1574 /* 3104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(3130), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1140 //
1575 /* 3111 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1576 /* 3111 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1577 /* 3116 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1578 /* 3122 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1579 /* 3128 */ GIR_RootConstrainSelectedInstOperands,
1580 /* 3129 */ // GIR_Coverage, 1140,
1581 /* 3129 */ GIR_Done,
1582 /* 3130 */ // Label 178: @3130
1583 /* 3130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(3144), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1266 //
1584 /* 3137 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1585 /* 3137 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1586 /* 3142 */ GIR_RootConstrainSelectedInstOperands,
1587 /* 3143 */ // GIR_Coverage, 1266,
1588 /* 3143 */ GIR_Done,
1589 /* 3144 */ // Label 179: @3144
1590 /* 3144 */ GIM_Reject,
1591 /* 3145 */ // Label 175: @3145
1592 /* 3145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 180*/ GIMT_Encode4(3183), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2076 //
1593 /* 3152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1594 /* 3156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1595 /* 3160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1596 /* 3164 */ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1597 /* 3164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1598 /* 3169 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1599 /* 3175 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1600 /* 3181 */ GIR_RootConstrainSelectedInstOperands,
1601 /* 3182 */ // GIR_Coverage, 2076,
1602 /* 3182 */ GIR_Done,
1603 /* 3183 */ // Label 180: @3183
1604 /* 3183 */ GIM_Reject,
1605 /* 3184 */ // Label 174: @3184
1606 /* 3184 */ GIM_Reject,
1607 /* 3185 */ // Label 167: @3185
1608 /* 3185 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(3267),
1609 /* 3190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1610 /* 3193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1611 /* 3196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1612 /* 3200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1613 /* 3204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1614 /* 3208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(3252), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 349 //
1615 /* 3215 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1616 /* 3215 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1617 /* 3220 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1618 /* 3226 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1619 /* 3232 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1620 /* 3238 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1621 /* 3244 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1622 /* 3250 */ GIR_RootConstrainSelectedInstOperands,
1623 /* 3251 */ // GIR_Coverage, 349,
1624 /* 3251 */ GIR_Done,
1625 /* 3252 */ // Label 182: @3252
1626 /* 3252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 183*/ GIMT_Encode4(3266), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 410 //
1627 /* 3259 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1628 /* 3259 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1629 /* 3264 */ GIR_RootConstrainSelectedInstOperands,
1630 /* 3265 */ // GIR_Coverage, 410,
1631 /* 3265 */ GIR_Done,
1632 /* 3266 */ // Label 183: @3266
1633 /* 3266 */ GIM_Reject,
1634 /* 3267 */ // Label 181: @3267
1635 /* 3267 */ GIM_Reject,
1636 /* 3268 */ // Label 168: @3268
1637 /* 3268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 184*/ GIMT_Encode4(3300), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 971 //
1638 /* 3275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1639 /* 3278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1640 /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1641 /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1642 /* 3289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1643 /* 3293 */ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1644 /* 3293 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1645 /* 3298 */ GIR_RootConstrainSelectedInstOperands,
1646 /* 3299 */ // GIR_Coverage, 971,
1647 /* 3299 */ GIR_Done,
1648 /* 3300 */ // Label 184: @3300
1649 /* 3300 */ GIM_Reject,
1650 /* 3301 */ // Label 169: @3301
1651 /* 3301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(3331), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2181 //
1652 /* 3308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1653 /* 3311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1654 /* 3314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1655 /* 3318 */ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1656 /* 3318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1657 /* 3323 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1658 /* 3329 */ GIR_RootConstrainSelectedInstOperands,
1659 /* 3330 */ // GIR_Coverage, 2181,
1660 /* 3330 */ GIR_Done,
1661 /* 3331 */ // Label 185: @3331
1662 /* 3331 */ GIM_Reject,
1663 /* 3332 */ // Label 170: @3332
1664 /* 3332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(3364), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 972 //
1665 /* 3339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1666 /* 3342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1667 /* 3345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1668 /* 3349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1669 /* 3353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1670 /* 3357 */ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1671 /* 3357 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1672 /* 3362 */ GIR_RootConstrainSelectedInstOperands,
1673 /* 3363 */ // GIR_Coverage, 972,
1674 /* 3363 */ GIR_Done,
1675 /* 3364 */ // Label 186: @3364
1676 /* 3364 */ GIM_Reject,
1677 /* 3365 */ // Label 171: @3365
1678 /* 3365 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(3397), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 973 //
1679 /* 3372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1680 /* 3375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1681 /* 3378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1682 /* 3382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1683 /* 3386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1684 /* 3390 */ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1685 /* 3390 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1686 /* 3395 */ GIR_RootConstrainSelectedInstOperands,
1687 /* 3396 */ // GIR_Coverage, 973,
1688 /* 3396 */ GIR_Done,
1689 /* 3397 */ // Label 187: @3397
1690 /* 3397 */ GIM_Reject,
1691 /* 3398 */ // Label 172: @3398
1692 /* 3398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 188*/ GIMT_Encode4(3430), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 974 //
1693 /* 3405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1694 /* 3408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1695 /* 3411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1696 /* 3415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1697 /* 3419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1698 /* 3423 */ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1699 /* 3423 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1700 /* 3428 */ GIR_RootConstrainSelectedInstOperands,
1701 /* 3429 */ // GIR_Coverage, 974,
1702 /* 3429 */ GIR_Done,
1703 /* 3430 */ // Label 188: @3430
1704 /* 3430 */ GIM_Reject,
1705 /* 3431 */ // Label 173: @3431
1706 /* 3431 */ GIM_Reject,
1707 /* 3432 */ // Label 3: @3432
1708 /* 3432 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 195*/ GIMT_Encode4(3693),
1709 /* 3443 */ /*GILLT_s32*//*Label 189*/ GIMT_Encode4(3475),
1710 /* 3447 */ /*GILLT_s64*//*Label 190*/ GIMT_Encode4(3528), GIMT_Encode4(0),
1711 /* 3455 */ /*GILLT_v16s8*//*Label 191*/ GIMT_Encode4(3561), GIMT_Encode4(0),
1712 /* 3463 */ /*GILLT_v8s16*//*Label 192*/ GIMT_Encode4(3594),
1713 /* 3467 */ /*GILLT_v4s32*//*Label 193*/ GIMT_Encode4(3627),
1714 /* 3471 */ /*GILLT_v2s64*//*Label 194*/ GIMT_Encode4(3660),
1715 /* 3475 */ // Label 189: @3475
1716 /* 3475 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(3527),
1717 /* 3480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1718 /* 3483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1719 /* 3486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1720 /* 3490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1721 /* 3494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1722 /* 3498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(3512), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 387 //
1723 /* 3505 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1724 /* 3505 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1725 /* 3510 */ GIR_RootConstrainSelectedInstOperands,
1726 /* 3511 */ // GIR_Coverage, 387,
1727 /* 3511 */ GIR_Done,
1728 /* 3512 */ // Label 197: @3512
1729 /* 3512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 198*/ GIMT_Encode4(3526), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1259 //
1730 /* 3519 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1731 /* 3519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1732 /* 3524 */ GIR_RootConstrainSelectedInstOperands,
1733 /* 3525 */ // GIR_Coverage, 1259,
1734 /* 3525 */ GIR_Done,
1735 /* 3526 */ // Label 198: @3526
1736 /* 3526 */ GIM_Reject,
1737 /* 3527 */ // Label 196: @3527
1738 /* 3527 */ GIM_Reject,
1739 /* 3528 */ // Label 190: @3528
1740 /* 3528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 199*/ GIMT_Encode4(3560), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 404 //
1741 /* 3535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1742 /* 3538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1743 /* 3541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1744 /* 3545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1745 /* 3549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1746 /* 3553 */ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1747 /* 3553 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1748 /* 3558 */ GIR_RootConstrainSelectedInstOperands,
1749 /* 3559 */ // GIR_Coverage, 404,
1750 /* 3559 */ GIR_Done,
1751 /* 3560 */ // Label 199: @3560
1752 /* 3560 */ GIM_Reject,
1753 /* 3561 */ // Label 191: @3561
1754 /* 3561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 200*/ GIMT_Encode4(3593), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 707 //
1755 /* 3568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1756 /* 3571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1757 /* 3574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1758 /* 3578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1759 /* 3582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1760 /* 3586 */ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1761 /* 3586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1762 /* 3591 */ GIR_RootConstrainSelectedInstOperands,
1763 /* 3592 */ // GIR_Coverage, 707,
1764 /* 3592 */ GIR_Done,
1765 /* 3593 */ // Label 200: @3593
1766 /* 3593 */ GIM_Reject,
1767 /* 3594 */ // Label 192: @3594
1768 /* 3594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(3626), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 708 //
1769 /* 3601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1770 /* 3604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1771 /* 3607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1772 /* 3611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1773 /* 3615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1774 /* 3619 */ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1775 /* 3619 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1776 /* 3624 */ GIR_RootConstrainSelectedInstOperands,
1777 /* 3625 */ // GIR_Coverage, 708,
1778 /* 3625 */ GIR_Done,
1779 /* 3626 */ // Label 201: @3626
1780 /* 3626 */ GIM_Reject,
1781 /* 3627 */ // Label 193: @3627
1782 /* 3627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(3659), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 709 //
1783 /* 3634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1784 /* 3637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1785 /* 3640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1786 /* 3644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1787 /* 3648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1788 /* 3652 */ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1789 /* 3652 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1790 /* 3657 */ GIR_RootConstrainSelectedInstOperands,
1791 /* 3658 */ // GIR_Coverage, 709,
1792 /* 3658 */ GIR_Done,
1793 /* 3659 */ // Label 202: @3659
1794 /* 3659 */ GIM_Reject,
1795 /* 3660 */ // Label 194: @3660
1796 /* 3660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 203*/ GIMT_Encode4(3692), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 710 //
1797 /* 3667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1798 /* 3670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1799 /* 3673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1800 /* 3677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1801 /* 3681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1802 /* 3685 */ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1803 /* 3685 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1804 /* 3690 */ GIR_RootConstrainSelectedInstOperands,
1805 /* 3691 */ // GIR_Coverage, 710,
1806 /* 3691 */ GIR_Done,
1807 /* 3692 */ // Label 203: @3692
1808 /* 3692 */ GIM_Reject,
1809 /* 3693 */ // Label 195: @3693
1810 /* 3693 */ GIM_Reject,
1811 /* 3694 */ // Label 4: @3694
1812 /* 3694 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 210*/ GIMT_Encode4(3955),
1813 /* 3705 */ /*GILLT_s32*//*Label 204*/ GIMT_Encode4(3737),
1814 /* 3709 */ /*GILLT_s64*//*Label 205*/ GIMT_Encode4(3790), GIMT_Encode4(0),
1815 /* 3717 */ /*GILLT_v16s8*//*Label 206*/ GIMT_Encode4(3823), GIMT_Encode4(0),
1816 /* 3725 */ /*GILLT_v8s16*//*Label 207*/ GIMT_Encode4(3856),
1817 /* 3729 */ /*GILLT_v4s32*//*Label 208*/ GIMT_Encode4(3889),
1818 /* 3733 */ /*GILLT_v2s64*//*Label 209*/ GIMT_Encode4(3922),
1819 /* 3737 */ // Label 204: @3737
1820 /* 3737 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(3789),
1821 /* 3742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1822 /* 3745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1823 /* 3748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1824 /* 3752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1825 /* 3756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1826 /* 3760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(3774), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 388 //
1827 /* 3767 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1828 /* 3767 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1829 /* 3772 */ GIR_RootConstrainSelectedInstOperands,
1830 /* 3773 */ // GIR_Coverage, 388,
1831 /* 3773 */ GIR_Done,
1832 /* 3774 */ // Label 212: @3774
1833 /* 3774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(3788), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1260 //
1834 /* 3781 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1835 /* 3781 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1836 /* 3786 */ GIR_RootConstrainSelectedInstOperands,
1837 /* 3787 */ // GIR_Coverage, 1260,
1838 /* 3787 */ GIR_Done,
1839 /* 3788 */ // Label 213: @3788
1840 /* 3788 */ GIM_Reject,
1841 /* 3789 */ // Label 211: @3789
1842 /* 3789 */ GIM_Reject,
1843 /* 3790 */ // Label 205: @3790
1844 /* 3790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 214*/ GIMT_Encode4(3822), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 405 //
1845 /* 3797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1846 /* 3800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1847 /* 3803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1848 /* 3807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1849 /* 3811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1850 /* 3815 */ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1851 /* 3815 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1852 /* 3820 */ GIR_RootConstrainSelectedInstOperands,
1853 /* 3821 */ // GIR_Coverage, 405,
1854 /* 3821 */ GIR_Done,
1855 /* 3822 */ // Label 214: @3822
1856 /* 3822 */ GIM_Reject,
1857 /* 3823 */ // Label 206: @3823
1858 /* 3823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 215*/ GIMT_Encode4(3855), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 711 //
1859 /* 3830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1860 /* 3833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1861 /* 3836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1862 /* 3840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1863 /* 3844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1864 /* 3848 */ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1865 /* 3848 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1866 /* 3853 */ GIR_RootConstrainSelectedInstOperands,
1867 /* 3854 */ // GIR_Coverage, 711,
1868 /* 3854 */ GIR_Done,
1869 /* 3855 */ // Label 215: @3855
1870 /* 3855 */ GIM_Reject,
1871 /* 3856 */ // Label 207: @3856
1872 /* 3856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(3888), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 712 //
1873 /* 3863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1874 /* 3866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1875 /* 3869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1876 /* 3873 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1877 /* 3877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1878 /* 3881 */ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1879 /* 3881 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1880 /* 3886 */ GIR_RootConstrainSelectedInstOperands,
1881 /* 3887 */ // GIR_Coverage, 712,
1882 /* 3887 */ GIR_Done,
1883 /* 3888 */ // Label 216: @3888
1884 /* 3888 */ GIM_Reject,
1885 /* 3889 */ // Label 208: @3889
1886 /* 3889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(3921), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 713 //
1887 /* 3896 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1888 /* 3899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1889 /* 3902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1890 /* 3906 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1891 /* 3910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1892 /* 3914 */ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1893 /* 3914 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1894 /* 3919 */ GIR_RootConstrainSelectedInstOperands,
1895 /* 3920 */ // GIR_Coverage, 713,
1896 /* 3920 */ GIR_Done,
1897 /* 3921 */ // Label 217: @3921
1898 /* 3921 */ GIM_Reject,
1899 /* 3922 */ // Label 209: @3922
1900 /* 3922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 218*/ GIMT_Encode4(3954), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 714 //
1901 /* 3929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1902 /* 3932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1903 /* 3935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1904 /* 3939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1905 /* 3943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1906 /* 3947 */ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1907 /* 3947 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1908 /* 3952 */ GIR_RootConstrainSelectedInstOperands,
1909 /* 3953 */ // GIR_Coverage, 714,
1910 /* 3953 */ GIR_Done,
1911 /* 3954 */ // Label 218: @3954
1912 /* 3954 */ GIM_Reject,
1913 /* 3955 */ // Label 210: @3955
1914 /* 3955 */ GIM_Reject,
1915 /* 3956 */ // Label 5: @3956
1916 /* 3956 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 225*/ GIMT_Encode4(4217),
1917 /* 3967 */ /*GILLT_s32*//*Label 219*/ GIMT_Encode4(3999),
1918 /* 3971 */ /*GILLT_s64*//*Label 220*/ GIMT_Encode4(4052), GIMT_Encode4(0),
1919 /* 3979 */ /*GILLT_v16s8*//*Label 221*/ GIMT_Encode4(4085), GIMT_Encode4(0),
1920 /* 3987 */ /*GILLT_v8s16*//*Label 222*/ GIMT_Encode4(4118),
1921 /* 3991 */ /*GILLT_v4s32*//*Label 223*/ GIMT_Encode4(4151),
1922 /* 3995 */ /*GILLT_v2s64*//*Label 224*/ GIMT_Encode4(4184),
1923 /* 3999 */ // Label 219: @3999
1924 /* 3999 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(4051),
1925 /* 4004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1926 /* 4007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1927 /* 4010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1928 /* 4014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1929 /* 4018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1930 /* 4022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(4036), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 389 //
1931 /* 4029 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1932 /* 4029 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1933 /* 4034 */ GIR_RootConstrainSelectedInstOperands,
1934 /* 4035 */ // GIR_Coverage, 389,
1935 /* 4035 */ GIR_Done,
1936 /* 4036 */ // Label 227: @4036
1937 /* 4036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(4050), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1264 //
1938 /* 4043 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1939 /* 4043 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1940 /* 4048 */ GIR_RootConstrainSelectedInstOperands,
1941 /* 4049 */ // GIR_Coverage, 1264,
1942 /* 4049 */ GIR_Done,
1943 /* 4050 */ // Label 228: @4050
1944 /* 4050 */ GIM_Reject,
1945 /* 4051 */ // Label 226: @4051
1946 /* 4051 */ GIM_Reject,
1947 /* 4052 */ // Label 220: @4052
1948 /* 4052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(4084), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 406 //
1949 /* 4059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1950 /* 4062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1951 /* 4065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1952 /* 4069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1953 /* 4073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1954 /* 4077 */ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1955 /* 4077 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1956 /* 4082 */ GIR_RootConstrainSelectedInstOperands,
1957 /* 4083 */ // GIR_Coverage, 406,
1958 /* 4083 */ GIR_Done,
1959 /* 4084 */ // Label 229: @4084
1960 /* 4084 */ GIM_Reject,
1961 /* 4085 */ // Label 221: @4085
1962 /* 4085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 230*/ GIMT_Encode4(4117), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 951 //
1963 /* 4092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1964 /* 4095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1965 /* 4098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1966 /* 4102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1967 /* 4106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1968 /* 4110 */ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1969 /* 4110 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
1970 /* 4115 */ GIR_RootConstrainSelectedInstOperands,
1971 /* 4116 */ // GIR_Coverage, 951,
1972 /* 4116 */ GIR_Done,
1973 /* 4117 */ // Label 230: @4117
1974 /* 4117 */ GIM_Reject,
1975 /* 4118 */ // Label 222: @4118
1976 /* 4118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 231*/ GIMT_Encode4(4150), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 952 //
1977 /* 4125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1978 /* 4128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1979 /* 4131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1980 /* 4135 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1981 /* 4139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1982 /* 4143 */ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1983 /* 4143 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
1984 /* 4148 */ GIR_RootConstrainSelectedInstOperands,
1985 /* 4149 */ // GIR_Coverage, 952,
1986 /* 4149 */ GIR_Done,
1987 /* 4150 */ // Label 231: @4150
1988 /* 4150 */ GIM_Reject,
1989 /* 4151 */ // Label 223: @4151
1990 /* 4151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 232*/ GIMT_Encode4(4183), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 953 //
1991 /* 4158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1992 /* 4161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1993 /* 4164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1994 /* 4168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1995 /* 4172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1996 /* 4176 */ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1997 /* 4176 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
1998 /* 4181 */ GIR_RootConstrainSelectedInstOperands,
1999 /* 4182 */ // GIR_Coverage, 953,
2000 /* 4182 */ GIR_Done,
2001 /* 4183 */ // Label 232: @4183
2002 /* 4183 */ GIM_Reject,
2003 /* 4184 */ // Label 224: @4184
2004 /* 4184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 233*/ GIMT_Encode4(4216), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 954 //
2005 /* 4191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2006 /* 4194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2007 /* 4197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2008 /* 4201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2009 /* 4205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2010 /* 4209 */ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2011 /* 4209 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
2012 /* 4214 */ GIR_RootConstrainSelectedInstOperands,
2013 /* 4215 */ // GIR_Coverage, 954,
2014 /* 4215 */ GIR_Done,
2015 /* 4216 */ // Label 233: @4216
2016 /* 4216 */ GIM_Reject,
2017 /* 4217 */ // Label 225: @4217
2018 /* 4217 */ GIM_Reject,
2019 /* 4218 */ // Label 6: @4218
2020 /* 4218 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 240*/ GIMT_Encode4(4479),
2021 /* 4229 */ /*GILLT_s32*//*Label 234*/ GIMT_Encode4(4261),
2022 /* 4233 */ /*GILLT_s64*//*Label 235*/ GIMT_Encode4(4314), GIMT_Encode4(0),
2023 /* 4241 */ /*GILLT_v16s8*//*Label 236*/ GIMT_Encode4(4347), GIMT_Encode4(0),
2024 /* 4249 */ /*GILLT_v8s16*//*Label 237*/ GIMT_Encode4(4380),
2025 /* 4253 */ /*GILLT_v4s32*//*Label 238*/ GIMT_Encode4(4413),
2026 /* 4257 */ /*GILLT_v2s64*//*Label 239*/ GIMT_Encode4(4446),
2027 /* 4261 */ // Label 234: @4261
2028 /* 4261 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(4313),
2029 /* 4266 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2030 /* 4269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2031 /* 4272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2032 /* 4276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2033 /* 4280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2034 /* 4284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(4298), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 390 //
2035 /* 4291 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2036 /* 4291 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2037 /* 4296 */ GIR_RootConstrainSelectedInstOperands,
2038 /* 4297 */ // GIR_Coverage, 390,
2039 /* 4297 */ GIR_Done,
2040 /* 4298 */ // Label 242: @4298
2041 /* 4298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 243*/ GIMT_Encode4(4312), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1265 //
2042 /* 4305 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2043 /* 4305 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2044 /* 4310 */ GIR_RootConstrainSelectedInstOperands,
2045 /* 4311 */ // GIR_Coverage, 1265,
2046 /* 4311 */ GIR_Done,
2047 /* 4312 */ // Label 243: @4312
2048 /* 4312 */ GIM_Reject,
2049 /* 4313 */ // Label 241: @4313
2050 /* 4313 */ GIM_Reject,
2051 /* 4314 */ // Label 235: @4314
2052 /* 4314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 244*/ GIMT_Encode4(4346), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 407 //
2053 /* 4321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2054 /* 4324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2055 /* 4327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2056 /* 4331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2057 /* 4335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2058 /* 4339 */ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2059 /* 4339 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2060 /* 4344 */ GIR_RootConstrainSelectedInstOperands,
2061 /* 4345 */ // GIR_Coverage, 407,
2062 /* 4345 */ GIR_Done,
2063 /* 4346 */ // Label 244: @4346
2064 /* 4346 */ GIM_Reject,
2065 /* 4347 */ // Label 236: @4347
2066 /* 4347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(4379), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 955 //
2067 /* 4354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2068 /* 4357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2069 /* 4360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2070 /* 4364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2071 /* 4368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2072 /* 4372 */ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2073 /* 4372 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2074 /* 4377 */ GIR_RootConstrainSelectedInstOperands,
2075 /* 4378 */ // GIR_Coverage, 955,
2076 /* 4378 */ GIR_Done,
2077 /* 4379 */ // Label 245: @4379
2078 /* 4379 */ GIM_Reject,
2079 /* 4380 */ // Label 237: @4380
2080 /* 4380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(4412), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 956 //
2081 /* 4387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2082 /* 4390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2083 /* 4393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2084 /* 4397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2085 /* 4401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2086 /* 4405 */ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2087 /* 4405 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2088 /* 4410 */ GIR_RootConstrainSelectedInstOperands,
2089 /* 4411 */ // GIR_Coverage, 956,
2090 /* 4411 */ GIR_Done,
2091 /* 4412 */ // Label 246: @4412
2092 /* 4412 */ GIM_Reject,
2093 /* 4413 */ // Label 238: @4413
2094 /* 4413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(4445), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 957 //
2095 /* 4420 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2096 /* 4423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2097 /* 4426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2098 /* 4430 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2099 /* 4434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2100 /* 4438 */ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2101 /* 4438 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2102 /* 4443 */ GIR_RootConstrainSelectedInstOperands,
2103 /* 4444 */ // GIR_Coverage, 957,
2104 /* 4444 */ GIR_Done,
2105 /* 4445 */ // Label 247: @4445
2106 /* 4445 */ GIM_Reject,
2107 /* 4446 */ // Label 239: @4446
2108 /* 4446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 248*/ GIMT_Encode4(4478), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 958 //
2109 /* 4453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2110 /* 4456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2111 /* 4459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2112 /* 4463 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2113 /* 4467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2114 /* 4471 */ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2115 /* 4471 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2116 /* 4476 */ GIR_RootConstrainSelectedInstOperands,
2117 /* 4477 */ // GIR_Coverage, 958,
2118 /* 4477 */ GIR_Done,
2119 /* 4478 */ // Label 248: @4478
2120 /* 4478 */ GIM_Reject,
2121 /* 4479 */ // Label 240: @4479
2122 /* 4479 */ GIM_Reject,
2123 /* 4480 */ // Label 7: @4480
2124 /* 4480 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 255*/ GIMT_Encode4(5013),
2125 /* 4491 */ /*GILLT_s32*//*Label 249*/ GIMT_Encode4(4523),
2126 /* 4495 */ /*GILLT_s64*//*Label 250*/ GIMT_Encode4(4781), GIMT_Encode4(0),
2127 /* 4503 */ /*GILLT_v16s8*//*Label 251*/ GIMT_Encode4(4881), GIMT_Encode4(0),
2128 /* 4511 */ /*GILLT_v8s16*//*Label 252*/ GIMT_Encode4(4914),
2129 /* 4515 */ /*GILLT_v4s32*//*Label 253*/ GIMT_Encode4(4947),
2130 /* 4519 */ /*GILLT_v2s64*//*Label 254*/ GIMT_Encode4(4980),
2131 /* 4523 */ // Label 249: @4523
2132 /* 4523 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4780),
2133 /* 4528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2134 /* 4531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2135 /* 4534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 257*/ GIMT_Encode4(4575), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 41 //
2136 /* 4541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2137 /* 4545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2138 /* 4549 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2139 /* 4553 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2140 /* 4557 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2141 /* 4561 */ // MIs[1] Operand 1
2142 /* 4561 */ // No operand predicates
2143 /* 4561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2144 /* 4563 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2145 /* 4563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2146 /* 4566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2147 /* 4568 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2148 /* 4570 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2149 /* 4573 */ GIR_RootConstrainSelectedInstOperands,
2150 /* 4574 */ // GIR_Coverage, 41,
2151 /* 4574 */ GIR_EraseRootFromParent_Done,
2152 /* 4575 */ // Label 257: @4575
2153 /* 4575 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4655),
2154 /* 4580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2155 /* 4584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2156 /* 4588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 259*/ GIMT_Encode4(4621), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2434 //
2157 /* 4595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2158 /* 4599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2159 /* 4603 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2160 /* 4607 */ // MIs[1] Operand 1
2161 /* 4607 */ // No operand predicates
2162 /* 4607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2163 /* 4609 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2164 /* 4609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2165 /* 4612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2166 /* 4614 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2167 /* 4616 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2168 /* 4619 */ GIR_RootConstrainSelectedInstOperands,
2169 /* 4620 */ // GIR_Coverage, 2434,
2170 /* 4620 */ GIR_EraseRootFromParent_Done,
2171 /* 4621 */ // Label 259: @4621
2172 /* 4621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 260*/ GIMT_Encode4(4654), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2630 //
2173 /* 4628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2174 /* 4632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2175 /* 4636 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2176 /* 4640 */ // MIs[1] Operand 1
2177 /* 4640 */ // No operand predicates
2178 /* 4640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2179 /* 4642 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2180 /* 4642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2181 /* 4645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2182 /* 4647 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2183 /* 4649 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2184 /* 4652 */ GIR_RootConstrainSelectedInstOperands,
2185 /* 4653 */ // GIR_Coverage, 2630,
2186 /* 4653 */ GIR_EraseRootFromParent_Done,
2187 /* 4654 */ // Label 260: @4654
2188 /* 4654 */ GIM_Reject,
2189 /* 4655 */ // Label 258: @4655
2190 /* 4655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 261*/ GIMT_Encode4(4681), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 51 //
2191 /* 4662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2192 /* 4666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2193 /* 4670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2194 /* 4674 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2195 /* 4674 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2196 /* 4679 */ GIR_RootConstrainSelectedInstOperands,
2197 /* 4680 */ // GIR_Coverage, 51,
2198 /* 4680 */ GIR_Done,
2199 /* 4681 */ // Label 261: @4681
2200 /* 4681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 262*/ GIMT_Encode4(4707), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1126 //
2201 /* 4688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2202 /* 4692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2203 /* 4696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2204 /* 4700 */ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2205 /* 4700 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2206 /* 4705 */ GIR_RootConstrainSelectedInstOperands,
2207 /* 4706 */ // GIR_Coverage, 1126,
2208 /* 4706 */ GIR_Done,
2209 /* 4707 */ // Label 262: @4707
2210 /* 4707 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(4753),
2211 /* 4712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2212 /* 4716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2213 /* 4720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2214 /* 4724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 264*/ GIMT_Encode4(4738), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1143 //
2215 /* 4731 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2216 /* 4731 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2217 /* 4736 */ GIR_RootConstrainSelectedInstOperands,
2218 /* 4737 */ // GIR_Coverage, 1143,
2219 /* 4737 */ GIR_Done,
2220 /* 4738 */ // Label 264: @4738
2221 /* 4738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 265*/ GIMT_Encode4(4752), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1257 //
2222 /* 4745 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2223 /* 4745 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2224 /* 4750 */ GIR_RootConstrainSelectedInstOperands,
2225 /* 4751 */ // GIR_Coverage, 1257,
2226 /* 4751 */ GIR_Done,
2227 /* 4752 */ // Label 265: @4752
2228 /* 4752 */ GIM_Reject,
2229 /* 4753 */ // Label 263: @4753
2230 /* 4753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 266*/ GIMT_Encode4(4779), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2075 //
2231 /* 4760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2232 /* 4764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2233 /* 4768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2234 /* 4772 */ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2235 /* 4772 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2236 /* 4777 */ GIR_RootConstrainSelectedInstOperands,
2237 /* 4778 */ // GIR_Coverage, 2075,
2238 /* 4778 */ GIR_Done,
2239 /* 4779 */ // Label 266: @4779
2240 /* 4779 */ GIM_Reject,
2241 /* 4780 */ // Label 256: @4780
2242 /* 4780 */ GIM_Reject,
2243 /* 4781 */ // Label 250: @4781
2244 /* 4781 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(4880),
2245 /* 4786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2246 /* 4789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2247 /* 4792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2248 /* 4796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(4857), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 344 //
2249 /* 4803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2250 /* 4807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2251 /* 4811 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2252 /* 4815 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2253 /* 4819 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2254 /* 4824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2255 /* 4829 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2256 /* 4840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2257 /* 4842 */ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2258 /* 4842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2259 /* 4845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2260 /* 4847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2261 /* 4851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2262 /* 4855 */ GIR_RootConstrainSelectedInstOperands,
2263 /* 4856 */ // GIR_Coverage, 344,
2264 /* 4856 */ GIR_EraseRootFromParent_Done,
2265 /* 4857 */ // Label 268: @4857
2266 /* 4857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 269*/ GIMT_Encode4(4879), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 261 //
2267 /* 4864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2268 /* 4868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2269 /* 4872 */ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2270 /* 4872 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2271 /* 4877 */ GIR_RootConstrainSelectedInstOperands,
2272 /* 4878 */ // GIR_Coverage, 261,
2273 /* 4878 */ GIR_Done,
2274 /* 4879 */ // Label 269: @4879
2275 /* 4879 */ GIM_Reject,
2276 /* 4880 */ // Label 267: @4880
2277 /* 4880 */ GIM_Reject,
2278 /* 4881 */ // Label 251: @4881
2279 /* 4881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 270*/ GIMT_Encode4(4913), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 578 //
2280 /* 4888 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2281 /* 4891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2282 /* 4894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2283 /* 4898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2284 /* 4902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2285 /* 4906 */ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2286 /* 4906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2287 /* 4911 */ GIR_RootConstrainSelectedInstOperands,
2288 /* 4912 */ // GIR_Coverage, 578,
2289 /* 4912 */ GIR_Done,
2290 /* 4913 */ // Label 270: @4913
2291 /* 4913 */ GIM_Reject,
2292 /* 4914 */ // Label 252: @4914
2293 /* 4914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 271*/ GIMT_Encode4(4946), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 579 //
2294 /* 4921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2295 /* 4924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2296 /* 4927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2297 /* 4931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2298 /* 4935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2299 /* 4939 */ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2300 /* 4939 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2301 /* 4944 */ GIR_RootConstrainSelectedInstOperands,
2302 /* 4945 */ // GIR_Coverage, 579,
2303 /* 4945 */ GIR_Done,
2304 /* 4946 */ // Label 271: @4946
2305 /* 4946 */ GIM_Reject,
2306 /* 4947 */ // Label 253: @4947
2307 /* 4947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(4979), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 580 //
2308 /* 4954 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2309 /* 4957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2310 /* 4960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2311 /* 4964 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2312 /* 4968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2313 /* 4972 */ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2314 /* 4972 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2315 /* 4977 */ GIR_RootConstrainSelectedInstOperands,
2316 /* 4978 */ // GIR_Coverage, 580,
2317 /* 4978 */ GIR_Done,
2318 /* 4979 */ // Label 272: @4979
2319 /* 4979 */ GIM_Reject,
2320 /* 4980 */ // Label 254: @4980
2321 /* 4980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 273*/ GIMT_Encode4(5012), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 581 //
2322 /* 4987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2323 /* 4990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2324 /* 4993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2325 /* 4997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2326 /* 5001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2327 /* 5005 */ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2328 /* 5005 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2329 /* 5010 */ GIR_RootConstrainSelectedInstOperands,
2330 /* 5011 */ // GIR_Coverage, 581,
2331 /* 5011 */ GIR_Done,
2332 /* 5012 */ // Label 273: @5012
2333 /* 5012 */ GIM_Reject,
2334 /* 5013 */ // Label 255: @5013
2335 /* 5013 */ GIM_Reject,
2336 /* 5014 */ // Label 8: @5014
2337 /* 5014 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 280*/ GIMT_Encode4(5398),
2338 /* 5025 */ /*GILLT_s32*//*Label 274*/ GIMT_Encode4(5057),
2339 /* 5029 */ /*GILLT_s64*//*Label 275*/ GIMT_Encode4(5233), GIMT_Encode4(0),
2340 /* 5037 */ /*GILLT_v16s8*//*Label 276*/ GIMT_Encode4(5266), GIMT_Encode4(0),
2341 /* 5045 */ /*GILLT_v8s16*//*Label 277*/ GIMT_Encode4(5299),
2342 /* 5049 */ /*GILLT_v4s32*//*Label 278*/ GIMT_Encode4(5332),
2343 /* 5053 */ /*GILLT_v2s64*//*Label 279*/ GIMT_Encode4(5365),
2344 /* 5057 */ // Label 274: @5057
2345 /* 5057 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5232),
2346 /* 5062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2347 /* 5065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2348 /* 5068 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(5133),
2349 /* 5073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2350 /* 5077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2351 /* 5081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 283*/ GIMT_Encode4(5114), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 42 //
2352 /* 5088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2353 /* 5092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2354 /* 5096 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2355 /* 5100 */ // MIs[1] Operand 1
2356 /* 5100 */ // No operand predicates
2357 /* 5100 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2358 /* 5102 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2359 /* 5102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2360 /* 5105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2361 /* 5107 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2362 /* 5109 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2363 /* 5112 */ GIR_RootConstrainSelectedInstOperands,
2364 /* 5113 */ // GIR_Coverage, 42,
2365 /* 5113 */ GIR_EraseRootFromParent_Done,
2366 /* 5114 */ // Label 283: @5114
2367 /* 5114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(5132), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 52 //
2368 /* 5121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2369 /* 5125 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2370 /* 5125 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2371 /* 5130 */ GIR_RootConstrainSelectedInstOperands,
2372 /* 5131 */ // GIR_Coverage, 52,
2373 /* 5131 */ GIR_Done,
2374 /* 5132 */ // Label 284: @5132
2375 /* 5132 */ GIM_Reject,
2376 /* 5133 */ // Label 282: @5133
2377 /* 5133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 285*/ GIMT_Encode4(5159), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1128 //
2378 /* 5140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2379 /* 5144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2380 /* 5148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2381 /* 5152 */ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2382 /* 5152 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2383 /* 5157 */ GIR_RootConstrainSelectedInstOperands,
2384 /* 5158 */ // GIR_Coverage, 1128,
2385 /* 5158 */ GIR_Done,
2386 /* 5159 */ // Label 285: @5159
2387 /* 5159 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(5205),
2388 /* 5164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2389 /* 5168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2390 /* 5172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2391 /* 5176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(5190), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1144 //
2392 /* 5183 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2393 /* 5183 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2394 /* 5188 */ GIR_RootConstrainSelectedInstOperands,
2395 /* 5189 */ // GIR_Coverage, 1144,
2396 /* 5189 */ GIR_Done,
2397 /* 5190 */ // Label 287: @5190
2398 /* 5190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(5204), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1270 //
2399 /* 5197 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2400 /* 5197 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2401 /* 5202 */ GIR_RootConstrainSelectedInstOperands,
2402 /* 5203 */ // GIR_Coverage, 1270,
2403 /* 5203 */ GIR_Done,
2404 /* 5204 */ // Label 288: @5204
2405 /* 5204 */ GIM_Reject,
2406 /* 5205 */ // Label 286: @5205
2407 /* 5205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 289*/ GIMT_Encode4(5231), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2077 //
2408 /* 5212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2409 /* 5216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2410 /* 5220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2411 /* 5224 */ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2412 /* 5224 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2413 /* 5229 */ GIR_RootConstrainSelectedInstOperands,
2414 /* 5230 */ // GIR_Coverage, 2077,
2415 /* 5230 */ GIR_Done,
2416 /* 5231 */ // Label 289: @5231
2417 /* 5231 */ GIM_Reject,
2418 /* 5232 */ // Label 281: @5232
2419 /* 5232 */ GIM_Reject,
2420 /* 5233 */ // Label 275: @5233
2421 /* 5233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 290*/ GIMT_Encode4(5265), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 262 //
2422 /* 5240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2423 /* 5243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2424 /* 5246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2425 /* 5250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2426 /* 5254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2427 /* 5258 */ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2428 /* 5258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2429 /* 5263 */ GIR_RootConstrainSelectedInstOperands,
2430 /* 5264 */ // GIR_Coverage, 262,
2431 /* 5264 */ GIR_Done,
2432 /* 5265 */ // Label 290: @5265
2433 /* 5265 */ GIM_Reject,
2434 /* 5266 */ // Label 276: @5266
2435 /* 5266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(5298), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 988 //
2436 /* 5273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2437 /* 5276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2438 /* 5279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2439 /* 5283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2440 /* 5287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2441 /* 5291 */ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2442 /* 5291 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2443 /* 5296 */ GIR_RootConstrainSelectedInstOperands,
2444 /* 5297 */ // GIR_Coverage, 988,
2445 /* 5297 */ GIR_Done,
2446 /* 5298 */ // Label 291: @5298
2447 /* 5298 */ GIM_Reject,
2448 /* 5299 */ // Label 277: @5299
2449 /* 5299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(5331), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 989 //
2450 /* 5306 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2451 /* 5309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2452 /* 5312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2453 /* 5316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2454 /* 5320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2455 /* 5324 */ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2456 /* 5324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2457 /* 5329 */ GIR_RootConstrainSelectedInstOperands,
2458 /* 5330 */ // GIR_Coverage, 989,
2459 /* 5330 */ GIR_Done,
2460 /* 5331 */ // Label 292: @5331
2461 /* 5331 */ GIM_Reject,
2462 /* 5332 */ // Label 278: @5332
2463 /* 5332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(5364), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 990 //
2464 /* 5339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2465 /* 5342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2466 /* 5345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2467 /* 5349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2468 /* 5353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2469 /* 5357 */ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2470 /* 5357 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2471 /* 5362 */ GIR_RootConstrainSelectedInstOperands,
2472 /* 5363 */ // GIR_Coverage, 990,
2473 /* 5363 */ GIR_Done,
2474 /* 5364 */ // Label 293: @5364
2475 /* 5364 */ GIM_Reject,
2476 /* 5365 */ // Label 279: @5365
2477 /* 5365 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 294*/ GIMT_Encode4(5397), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 991 //
2478 /* 5372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2479 /* 5375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2480 /* 5378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2481 /* 5382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2482 /* 5386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2483 /* 5390 */ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2484 /* 5390 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2485 /* 5395 */ GIR_RootConstrainSelectedInstOperands,
2486 /* 5396 */ // GIR_Coverage, 991,
2487 /* 5396 */ GIR_Done,
2488 /* 5397 */ // Label 294: @5397
2489 /* 5397 */ GIM_Reject,
2490 /* 5398 */ // Label 280: @5398
2491 /* 5398 */ GIM_Reject,
2492 /* 5399 */ // Label 9: @5399
2493 /* 5399 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 301*/ GIMT_Encode4(6235),
2494 /* 5410 */ /*GILLT_s32*//*Label 295*/ GIMT_Encode4(5442),
2495 /* 5414 */ /*GILLT_s64*//*Label 296*/ GIMT_Encode4(6010), GIMT_Encode4(0),
2496 /* 5422 */ /*GILLT_v16s8*//*Label 297*/ GIMT_Encode4(6103), GIMT_Encode4(0),
2497 /* 5430 */ /*GILLT_v8s16*//*Label 298*/ GIMT_Encode4(6136),
2498 /* 5434 */ /*GILLT_v4s32*//*Label 299*/ GIMT_Encode4(6169),
2499 /* 5438 */ /*GILLT_v2s64*//*Label 300*/ GIMT_Encode4(6202),
2500 /* 5442 */ // Label 295: @5442
2501 /* 5442 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6009),
2502 /* 5447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2503 /* 5450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2504 /* 5453 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(5617),
2505 /* 5458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2506 /* 5462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2507 /* 5466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(5516), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 54 //
2508 /* 5473 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2509 /* 5477 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2510 /* 5481 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2511 /* 5485 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2512 /* 5489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2513 /* 5494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2514 /* 5499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2515 /* 5501 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2516 /* 5501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2517 /* 5504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2518 /* 5506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2519 /* 5510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2520 /* 5514 */ GIR_RootConstrainSelectedInstOperands,
2521 /* 5515 */ // GIR_Coverage, 54,
2522 /* 5515 */ GIR_EraseRootFromParent_Done,
2523 /* 5516 */ // Label 304: @5516
2524 /* 5516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(5566), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1146 //
2525 /* 5523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2526 /* 5527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2527 /* 5531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2528 /* 5535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2529 /* 5539 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2530 /* 5544 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2531 /* 5549 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2532 /* 5551 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2533 /* 5551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2534 /* 5554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2535 /* 5556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2536 /* 5560 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2537 /* 5564 */ GIR_RootConstrainSelectedInstOperands,
2538 /* 5565 */ // GIR_Coverage, 1146,
2539 /* 5565 */ GIR_EraseRootFromParent_Done,
2540 /* 5566 */ // Label 305: @5566
2541 /* 5566 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 306*/ GIMT_Encode4(5616), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1269 //
2542 /* 5573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2543 /* 5577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2544 /* 5581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2545 /* 5585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2546 /* 5589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2547 /* 5594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2548 /* 5599 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2549 /* 5601 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2550 /* 5601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2551 /* 5604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2552 /* 5606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2553 /* 5610 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2554 /* 5614 */ GIR_RootConstrainSelectedInstOperands,
2555 /* 5615 */ // GIR_Coverage, 1269,
2556 /* 5615 */ GIR_EraseRootFromParent_Done,
2557 /* 5616 */ // Label 306: @5616
2558 /* 5616 */ GIM_Reject,
2559 /* 5617 */ // Label 303: @5617
2560 /* 5617 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(5667),
2561 /* 5622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2562 /* 5626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2563 /* 5630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2564 /* 5634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 308*/ GIMT_Encode4(5650), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1283 //
2565 /* 5641 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2566 /* 5641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2567 /* 5644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2568 /* 5646 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2569 /* 5648 */ GIR_RootConstrainSelectedInstOperands,
2570 /* 5649 */ // GIR_Coverage, 1283,
2571 /* 5649 */ GIR_EraseRootFromParent_Done,
2572 /* 5650 */ // Label 308: @5650
2573 /* 5650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(5666), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1127 //
2574 /* 5657 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2575 /* 5657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2576 /* 5660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2577 /* 5662 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2578 /* 5664 */ GIR_RootConstrainSelectedInstOperands,
2579 /* 5665 */ // GIR_Coverage, 1127,
2580 /* 5665 */ GIR_EraseRootFromParent_Done,
2581 /* 5666 */ // Label 309: @5666
2582 /* 5666 */ GIM_Reject,
2583 /* 5667 */ // Label 307: @5667
2584 /* 5667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 310*/ GIMT_Encode4(5701), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1478 //
2585 /* 5674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2586 /* 5678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2587 /* 5682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2588 /* 5686 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, R0:{ *:[i32] })
2589 /* 5686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2590 /* 5689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2591 /* 5691 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2592 /* 5693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2593 /* 5699 */ GIR_RootConstrainSelectedInstOperands,
2594 /* 5700 */ // GIR_Coverage, 1478,
2595 /* 5700 */ GIR_EraseRootFromParent_Done,
2596 /* 5701 */ // Label 310: @5701
2597 /* 5701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 311*/ GIMT_Encode4(5729), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2072 //
2598 /* 5708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2599 /* 5712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2600 /* 5716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2601 /* 5720 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2602 /* 5720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2603 /* 5723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2604 /* 5725 */ GIR_RootToRootCopy, /*OpIdx*/1, // r
2605 /* 5727 */ GIR_RootConstrainSelectedInstOperands,
2606 /* 5728 */ // GIR_Coverage, 2072,
2607 /* 5728 */ GIR_EraseRootFromParent_Done,
2608 /* 5729 */ // Label 311: @5729
2609 /* 5729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(5757), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2429 //
2610 /* 5736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2611 /* 5740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2612 /* 5744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2613 /* 5748 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2614 /* 5748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2615 /* 5751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2616 /* 5753 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2617 /* 5755 */ GIR_RootConstrainSelectedInstOperands,
2618 /* 5756 */ // GIR_Coverage, 2429,
2619 /* 5756 */ GIR_EraseRootFromParent_Done,
2620 /* 5757 */ // Label 312: @5757
2621 /* 5757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(5791), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2430 //
2622 /* 5764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2623 /* 5768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2624 /* 5772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2625 /* 5776 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, R0:{ *:[i32] })
2626 /* 5776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2627 /* 5779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2628 /* 5781 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2629 /* 5783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2630 /* 5789 */ GIR_RootConstrainSelectedInstOperands,
2631 /* 5790 */ // GIR_Coverage, 2430,
2632 /* 5790 */ GIR_EraseRootFromParent_Done,
2633 /* 5791 */ // Label 313: @5791
2634 /* 5791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 314*/ GIMT_Encode4(5819), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2633 //
2635 /* 5798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2636 /* 5802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2637 /* 5806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2638 /* 5810 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2639 /* 5810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2640 /* 5813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2641 /* 5815 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2642 /* 5817 */ GIR_RootConstrainSelectedInstOperands,
2643 /* 5818 */ // GIR_Coverage, 2633,
2644 /* 5818 */ GIR_EraseRootFromParent_Done,
2645 /* 5819 */ // Label 314: @5819
2646 /* 5819 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(5910),
2647 /* 5824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2648 /* 5828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2649 /* 5832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(5858), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2634 //
2650 /* 5839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2651 /* 5843 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, R0:{ *:[i32] })
2652 /* 5843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2653 /* 5846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2654 /* 5848 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2655 /* 5850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2656 /* 5856 */ GIR_RootConstrainSelectedInstOperands,
2657 /* 5857 */ // GIR_Coverage, 2634,
2658 /* 5857 */ GIR_EraseRootFromParent_Done,
2659 /* 5858 */ // Label 316: @5858
2660 /* 5858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(5891), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 43 //
2661 /* 5865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2662 /* 5869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2663 /* 5873 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2664 /* 5877 */ // MIs[1] Operand 1
2665 /* 5877 */ // No operand predicates
2666 /* 5877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2667 /* 5879 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2668 /* 5879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2669 /* 5882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2670 /* 5884 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2671 /* 5886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2672 /* 5889 */ GIR_RootConstrainSelectedInstOperands,
2673 /* 5890 */ // GIR_Coverage, 43,
2674 /* 5890 */ GIR_EraseRootFromParent_Done,
2675 /* 5891 */ // Label 317: @5891
2676 /* 5891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(5909), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 53 //
2677 /* 5898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2678 /* 5902 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2679 /* 5902 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2680 /* 5907 */ GIR_RootConstrainSelectedInstOperands,
2681 /* 5908 */ // GIR_Coverage, 53,
2682 /* 5908 */ GIR_Done,
2683 /* 5909 */ // Label 318: @5909
2684 /* 5909 */ GIM_Reject,
2685 /* 5910 */ // Label 315: @5910
2686 /* 5910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 319*/ GIMT_Encode4(5936), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1130 //
2687 /* 5917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2688 /* 5921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2689 /* 5925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2690 /* 5929 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2691 /* 5929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2692 /* 5934 */ GIR_RootConstrainSelectedInstOperands,
2693 /* 5935 */ // GIR_Coverage, 1130,
2694 /* 5935 */ GIR_Done,
2695 /* 5936 */ // Label 319: @5936
2696 /* 5936 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(5982),
2697 /* 5941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2698 /* 5945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2699 /* 5949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2700 /* 5953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 321*/ GIMT_Encode4(5967), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1145 //
2701 /* 5960 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2702 /* 5960 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2703 /* 5965 */ GIR_RootConstrainSelectedInstOperands,
2704 /* 5966 */ // GIR_Coverage, 1145,
2705 /* 5966 */ GIR_Done,
2706 /* 5967 */ // Label 321: @5967
2707 /* 5967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 322*/ GIMT_Encode4(5981), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1273 //
2708 /* 5974 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2709 /* 5974 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2710 /* 5979 */ GIR_RootConstrainSelectedInstOperands,
2711 /* 5980 */ // GIR_Coverage, 1273,
2712 /* 5980 */ GIR_Done,
2713 /* 5981 */ // Label 322: @5981
2714 /* 5981 */ GIM_Reject,
2715 /* 5982 */ // Label 320: @5982
2716 /* 5982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 323*/ GIMT_Encode4(6008), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2079 //
2717 /* 5989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2718 /* 5993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2719 /* 5997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2720 /* 6001 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2721 /* 6001 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2722 /* 6006 */ GIR_RootConstrainSelectedInstOperands,
2723 /* 6007 */ // GIR_Coverage, 2079,
2724 /* 6007 */ GIR_Done,
2725 /* 6008 */ // Label 323: @6008
2726 /* 6008 */ GIM_Reject,
2727 /* 6009 */ // Label 302: @6009
2728 /* 6009 */ GIM_Reject,
2729 /* 6010 */ // Label 296: @6010
2730 /* 6010 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6102),
2731 /* 6015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2732 /* 6018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2733 /* 6021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2734 /* 6025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 325*/ GIMT_Encode4(6079), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 264 //
2735 /* 6032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2736 /* 6036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2737 /* 6040 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2738 /* 6044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2739 /* 6048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2740 /* 6053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2741 /* 6058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2742 /* 6062 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2743 /* 6064 */ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2744 /* 6064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2745 /* 6067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2746 /* 6069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2747 /* 6073 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2748 /* 6077 */ GIR_RootConstrainSelectedInstOperands,
2749 /* 6078 */ // GIR_Coverage, 264,
2750 /* 6078 */ GIR_EraseRootFromParent_Done,
2751 /* 6079 */ // Label 325: @6079
2752 /* 6079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 326*/ GIMT_Encode4(6101), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 263 //
2753 /* 6086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2754 /* 6090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2755 /* 6094 */ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2756 /* 6094 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2757 /* 6099 */ GIR_RootConstrainSelectedInstOperands,
2758 /* 6100 */ // GIR_Coverage, 263,
2759 /* 6100 */ GIR_Done,
2760 /* 6101 */ // Label 326: @6101
2761 /* 6101 */ GIM_Reject,
2762 /* 6102 */ // Label 324: @6102
2763 /* 6102 */ GIM_Reject,
2764 /* 6103 */ // Label 297: @6103
2765 /* 6103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 327*/ GIMT_Encode4(6135), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1108 //
2766 /* 6110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2767 /* 6113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2768 /* 6116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2769 /* 6120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2770 /* 6124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2771 /* 6128 */ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2772 /* 6128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2773 /* 6133 */ GIR_RootConstrainSelectedInstOperands,
2774 /* 6134 */ // GIR_Coverage, 1108,
2775 /* 6134 */ GIR_Done,
2776 /* 6135 */ // Label 327: @6135
2777 /* 6135 */ GIM_Reject,
2778 /* 6136 */ // Label 298: @6136
2779 /* 6136 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 328*/ GIMT_Encode4(6168), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1109 //
2780 /* 6143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2781 /* 6146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2782 /* 6149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2783 /* 6153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2784 /* 6157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2785 /* 6161 */ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2786 /* 6161 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2787 /* 6166 */ GIR_RootConstrainSelectedInstOperands,
2788 /* 6167 */ // GIR_Coverage, 1109,
2789 /* 6167 */ GIR_Done,
2790 /* 6168 */ // Label 328: @6168
2791 /* 6168 */ GIM_Reject,
2792 /* 6169 */ // Label 299: @6169
2793 /* 6169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 329*/ GIMT_Encode4(6201), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1110 //
2794 /* 6176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2795 /* 6179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2796 /* 6182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2797 /* 6186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2798 /* 6190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2799 /* 6194 */ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2800 /* 6194 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2801 /* 6199 */ GIR_RootConstrainSelectedInstOperands,
2802 /* 6200 */ // GIR_Coverage, 1110,
2803 /* 6200 */ GIR_Done,
2804 /* 6201 */ // Label 329: @6201
2805 /* 6201 */ GIM_Reject,
2806 /* 6202 */ // Label 300: @6202
2807 /* 6202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 330*/ GIMT_Encode4(6234), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1111 //
2808 /* 6209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2809 /* 6212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2810 /* 6215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2811 /* 6219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2812 /* 6223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2813 /* 6227 */ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2814 /* 6227 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2815 /* 6232 */ GIR_RootConstrainSelectedInstOperands,
2816 /* 6233 */ // GIR_Coverage, 1111,
2817 /* 6233 */ GIR_Done,
2818 /* 6234 */ // Label 330: @6234
2819 /* 6234 */ GIM_Reject,
2820 /* 6235 */ // Label 301: @6235
2821 /* 6235 */ GIM_Reject,
2822 /* 6236 */ // Label 10: @6236
2823 /* 6236 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(6334),
2824 /* 6241 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2825 /* 6244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2826 /* 6247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2827 /* 6250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2828 /* 6253 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(6307),
2829 /* 6258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2830 /* 6262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(6284), GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode), // Rule ID 234 //
2831 /* 6269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2832 /* 6273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2833 /* 6277 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2834 /* 6277 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2835 /* 6282 */ GIR_RootConstrainSelectedInstOperands,
2836 /* 6283 */ // GIR_Coverage, 234,
2837 /* 6283 */ GIR_Done,
2838 /* 6284 */ // Label 333: @6284
2839 /* 6284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 334*/ GIMT_Encode4(6306), GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode), // Rule ID 235 //
2840 /* 6291 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2841 /* 6295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2842 /* 6299 */ // (MipsBuildPairF64_FPR:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$lo, FGR32Opnd:{ *:[f32] }:$hi) => (BuildPairF64_FPR:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$lo, FGR32Opnd:{ *:[f32] }:$hi)
2843 /* 6299 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_FPR),
2844 /* 6304 */ GIR_RootConstrainSelectedInstOperands,
2845 /* 6305 */ // GIR_Coverage, 235,
2846 /* 6305 */ GIR_Done,
2847 /* 6306 */ // Label 334: @6306
2848 /* 6306 */ GIM_Reject,
2849 /* 6307 */ // Label 332: @6307
2850 /* 6307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 335*/ GIMT_Encode4(6333), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode), // Rule ID 236 //
2851 /* 6314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2852 /* 6318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2853 /* 6322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2854 /* 6326 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2855 /* 6326 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2856 /* 6331 */ GIR_RootConstrainSelectedInstOperands,
2857 /* 6332 */ // GIR_Coverage, 236,
2858 /* 6332 */ GIR_Done,
2859 /* 6333 */ // Label 335: @6333
2860 /* 6333 */ GIM_Reject,
2861 /* 6334 */ // Label 331: @6334
2862 /* 6334 */ GIM_Reject,
2863 /* 6335 */ // Label 11: @6335
2864 /* 6335 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(6404),
2865 /* 6340 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2866 /* 6343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2867 /* 6346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2868 /* 6349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2869 /* 6353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(6378), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 782 //
2870 /* 6360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2871 /* 6364 */ // MIs[0] rs
2872 /* 6364 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2873 /* 6369 */ // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2874 /* 6369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2875 /* 6372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2876 /* 6374 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2877 /* 6376 */ GIR_RootConstrainSelectedInstOperands,
2878 /* 6377 */ // GIR_Coverage, 782,
2879 /* 6377 */ GIR_EraseRootFromParent_Done,
2880 /* 6378 */ // Label 337: @6378
2881 /* 6378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 338*/ GIMT_Encode4(6403), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 784 //
2882 /* 6385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2883 /* 6389 */ // MIs[0] fs
2884 /* 6389 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2885 /* 6394 */ // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2886 /* 6394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2887 /* 6397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2888 /* 6399 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2889 /* 6401 */ GIR_RootConstrainSelectedInstOperands,
2890 /* 6402 */ // GIR_Coverage, 784,
2891 /* 6402 */ GIR_EraseRootFromParent_Done,
2892 /* 6403 */ // Label 338: @6403
2893 /* 6403 */ GIM_Reject,
2894 /* 6404 */ // Label 336: @6404
2895 /* 6404 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(6493),
2896 /* 6409 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2897 /* 6412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2898 /* 6415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2899 /* 6418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2900 /* 6422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(6457), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 781 //
2901 /* 6429 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2902 /* 6433 */ // MIs[0] rs
2903 /* 6433 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2904 /* 6438 */ // MIs[0] rs
2905 /* 6438 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2906 /* 6443 */ // MIs[0] rs
2907 /* 6443 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2908 /* 6448 */ // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2909 /* 6448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2910 /* 6451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2911 /* 6453 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2912 /* 6455 */ GIR_RootConstrainSelectedInstOperands,
2913 /* 6456 */ // GIR_Coverage, 781,
2914 /* 6456 */ GIR_EraseRootFromParent_Done,
2915 /* 6457 */ // Label 340: @6457
2916 /* 6457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(6492), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 783 //
2917 /* 6464 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2918 /* 6468 */ // MIs[0] fs
2919 /* 6468 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2920 /* 6473 */ // MIs[0] fs
2921 /* 6473 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2922 /* 6478 */ // MIs[0] fs
2923 /* 6478 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2924 /* 6483 */ // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2925 /* 6483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2926 /* 6486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2927 /* 6488 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2928 /* 6490 */ GIR_RootConstrainSelectedInstOperands,
2929 /* 6491 */ // GIR_Coverage, 783,
2930 /* 6491 */ GIR_EraseRootFromParent_Done,
2931 /* 6492 */ // Label 341: @6492
2932 /* 6492 */ GIM_Reject,
2933 /* 6493 */ // Label 339: @6493
2934 /* 6493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(6561), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 780 //
2935 /* 6500 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
2936 /* 6503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
2937 /* 6506 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2938 /* 6509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2939 /* 6513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2940 /* 6517 */ // MIs[0] rs
2941 /* 6517 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2942 /* 6522 */ // MIs[0] rs
2943 /* 6522 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2944 /* 6527 */ // MIs[0] rs
2945 /* 6527 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2946 /* 6532 */ // MIs[0] rs
2947 /* 6532 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2948 /* 6537 */ // MIs[0] rs
2949 /* 6537 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2950 /* 6542 */ // MIs[0] rs
2951 /* 6542 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2952 /* 6547 */ // MIs[0] rs
2953 /* 6547 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
2954 /* 6552 */ // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
2955 /* 6552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
2956 /* 6555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2957 /* 6557 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2958 /* 6559 */ GIR_RootConstrainSelectedInstOperands,
2959 /* 6560 */ // GIR_Coverage, 780,
2960 /* 6560 */ GIR_EraseRootFromParent_Done,
2961 /* 6561 */ // Label 342: @6561
2962 /* 6561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 343*/ GIMT_Encode4(6669), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 779 //
2963 /* 6568 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
2964 /* 6571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
2965 /* 6574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2966 /* 6577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2967 /* 6581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2968 /* 6585 */ // MIs[0] rs
2969 /* 6585 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2970 /* 6590 */ // MIs[0] rs
2971 /* 6590 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2972 /* 6595 */ // MIs[0] rs
2973 /* 6595 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2974 /* 6600 */ // MIs[0] rs
2975 /* 6600 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2976 /* 6605 */ // MIs[0] rs
2977 /* 6605 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2978 /* 6610 */ // MIs[0] rs
2979 /* 6610 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2980 /* 6615 */ // MIs[0] rs
2981 /* 6615 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
2982 /* 6620 */ // MIs[0] rs
2983 /* 6620 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
2984 /* 6625 */ // MIs[0] rs
2985 /* 6625 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
2986 /* 6630 */ // MIs[0] rs
2987 /* 6630 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
2988 /* 6635 */ // MIs[0] rs
2989 /* 6635 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
2990 /* 6640 */ // MIs[0] rs
2991 /* 6640 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
2992 /* 6645 */ // MIs[0] rs
2993 /* 6645 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
2994 /* 6650 */ // MIs[0] rs
2995 /* 6650 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
2996 /* 6655 */ // MIs[0] rs
2997 /* 6655 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
2998 /* 6660 */ // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
2999 /* 6660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
3000 /* 6663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3001 /* 6665 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3002 /* 6667 */ GIR_RootConstrainSelectedInstOperands,
3003 /* 6668 */ // GIR_Coverage, 779,
3004 /* 6668 */ GIR_EraseRootFromParent_Done,
3005 /* 6669 */ // Label 343: @6669
3006 /* 6669 */ GIM_Reject,
3007 /* 6670 */ // Label 12: @6670
3008 /* 6670 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 352*/ GIMT_Encode4(10753),
3009 /* 6681 */ /*GILLT_s32*//*Label 344*/ GIMT_Encode4(6713),
3010 /* 6685 */ /*GILLT_s64*//*Label 345*/ GIMT_Encode4(6982),
3011 /* 6689 */ /*GILLT_v4s8*//*Label 346*/ GIMT_Encode4(7036),
3012 /* 6693 */ /*GILLT_v16s8*//*Label 347*/ GIMT_Encode4(7094),
3013 /* 6697 */ /*GILLT_v2s16*//*Label 348*/ GIMT_Encode4(7739),
3014 /* 6701 */ /*GILLT_v8s16*//*Label 349*/ GIMT_Encode4(7797),
3015 /* 6705 */ /*GILLT_v4s32*//*Label 350*/ GIMT_Encode4(8751),
3016 /* 6709 */ /*GILLT_v2s64*//*Label 351*/ GIMT_Encode4(9719),
3017 /* 6713 */ // Label 344: @6713
3018 /* 6713 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(5), /*)*//*default:*//*Label 356*/ GIMT_Encode4(6981),
3019 /* 6724 */ /*GILLT_s32*//*Label 353*/ GIMT_Encode4(6744), GIMT_Encode4(0),
3020 /* 6732 */ /*GILLT_v4s8*//*Label 354*/ GIMT_Encode4(6875), GIMT_Encode4(0),
3021 /* 6740 */ /*GILLT_v2s16*//*Label 355*/ GIMT_Encode4(6928),
3022 /* 6744 */ // Label 353: @6744
3023 /* 6744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(6766), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 159 //
3024 /* 6751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3025 /* 6755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3026 /* 6759 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3027 /* 6759 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3028 /* 6764 */ GIR_RootConstrainSelectedInstOperands,
3029 /* 6765 */ // GIR_Coverage, 159,
3030 /* 6765 */ GIR_Done,
3031 /* 6766 */ // Label 357: @6766
3032 /* 6766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(6788), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 160 //
3033 /* 6773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3034 /* 6777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3035 /* 6781 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3036 /* 6781 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3037 /* 6786 */ GIR_RootConstrainSelectedInstOperands,
3038 /* 6787 */ // GIR_Coverage, 160,
3039 /* 6787 */ GIR_Done,
3040 /* 6788 */ // Label 358: @6788
3041 /* 6788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 359*/ GIMT_Encode4(6810), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1241 //
3042 /* 6795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3043 /* 6799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3044 /* 6803 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3045 /* 6803 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3046 /* 6808 */ GIR_RootConstrainSelectedInstOperands,
3047 /* 6809 */ // GIR_Coverage, 1241,
3048 /* 6809 */ GIR_Done,
3049 /* 6810 */ // Label 359: @6810
3050 /* 6810 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(6852),
3051 /* 6815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3052 /* 6819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3053 /* 6823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 361*/ GIMT_Encode4(6837), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1242 //
3054 /* 6830 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3055 /* 6830 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3056 /* 6835 */ GIR_RootConstrainSelectedInstOperands,
3057 /* 6836 */ // GIR_Coverage, 1242,
3058 /* 6836 */ GIR_Done,
3059 /* 6837 */ // Label 361: @6837
3060 /* 6837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 362*/ GIMT_Encode4(6851), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1262 //
3061 /* 6844 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3062 /* 6844 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3063 /* 6849 */ GIR_RootConstrainSelectedInstOperands,
3064 /* 6850 */ // GIR_Coverage, 1262,
3065 /* 6850 */ GIR_Done,
3066 /* 6851 */ // Label 362: @6851
3067 /* 6851 */ GIM_Reject,
3068 /* 6852 */ // Label 360: @6852
3069 /* 6852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(6874), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1263 //
3070 /* 6859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3071 /* 6863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3072 /* 6867 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3073 /* 6867 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3074 /* 6872 */ GIR_RootConstrainSelectedInstOperands,
3075 /* 6873 */ // GIR_Coverage, 1263,
3076 /* 6873 */ GIR_Done,
3077 /* 6874 */ // Label 363: @6874
3078 /* 6874 */ GIM_Reject,
3079 /* 6875 */ // Label 354: @6875
3080 /* 6875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(6901), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2161 //
3081 /* 6882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3082 /* 6886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3083 /* 6890 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3084 /* 6890 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3085 /* 6895 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3086 /* 6900 */ // GIR_Coverage, 2161,
3087 /* 6900 */ GIR_Done,
3088 /* 6901 */ // Label 364: @6901
3089 /* 6901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(6927), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2165 //
3090 /* 6908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3091 /* 6912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3092 /* 6916 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3093 /* 6916 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3094 /* 6921 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3095 /* 6926 */ // GIR_Coverage, 2165,
3096 /* 6926 */ GIR_Done,
3097 /* 6927 */ // Label 365: @6927
3098 /* 6927 */ GIM_Reject,
3099 /* 6928 */ // Label 355: @6928
3100 /* 6928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(6954), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2160 //
3101 /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3102 /* 6939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3103 /* 6943 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3104 /* 6943 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3105 /* 6948 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3106 /* 6953 */ // GIR_Coverage, 2160,
3107 /* 6953 */ GIR_Done,
3108 /* 6954 */ // Label 366: @6954
3109 /* 6954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 367*/ GIMT_Encode4(6980), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2164 //
3110 /* 6961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3111 /* 6965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3112 /* 6969 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3113 /* 6969 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3114 /* 6974 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3115 /* 6979 */ // GIR_Coverage, 2164,
3116 /* 6979 */ GIR_Done,
3117 /* 6980 */ // Label 367: @6980
3118 /* 6980 */ GIM_Reject,
3119 /* 6981 */ // Label 356: @6981
3120 /* 6981 */ GIM_Reject,
3121 /* 6982 */ // Label 345: @6982
3122 /* 6982 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(7035),
3123 /* 6987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3124 /* 6990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 369*/ GIMT_Encode4(7012), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 161 //
3125 /* 6997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3126 /* 7001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3127 /* 7005 */ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3128 /* 7005 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3129 /* 7010 */ GIR_RootConstrainSelectedInstOperands,
3130 /* 7011 */ // GIR_Coverage, 161,
3131 /* 7011 */ GIR_Done,
3132 /* 7012 */ // Label 369: @7012
3133 /* 7012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 370*/ GIMT_Encode4(7034), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 162 //
3134 /* 7019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3135 /* 7023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3136 /* 7027 */ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3137 /* 7027 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3138 /* 7032 */ GIR_RootConstrainSelectedInstOperands,
3139 /* 7033 */ // GIR_Coverage, 162,
3140 /* 7033 */ GIR_Done,
3141 /* 7034 */ // Label 370: @7034
3142 /* 7034 */ GIM_Reject,
3143 /* 7035 */ // Label 368: @7035
3144 /* 7035 */ GIM_Reject,
3145 /* 7036 */ // Label 346: @7036
3146 /* 7036 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(7093),
3147 /* 7041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3148 /* 7044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3149 /* 7048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 372*/ GIMT_Encode4(7070), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2163 //
3150 /* 7055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3151 /* 7059 */ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3152 /* 7059 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3153 /* 7064 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3154 /* 7069 */ // GIR_Coverage, 2163,
3155 /* 7069 */ GIR_Done,
3156 /* 7070 */ // Label 372: @7070
3157 /* 7070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 373*/ GIMT_Encode4(7092), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2167 //
3158 /* 7077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3159 /* 7081 */ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3160 /* 7081 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3161 /* 7086 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3162 /* 7091 */ // GIR_Coverage, 2167,
3163 /* 7091 */ GIR_Done,
3164 /* 7092 */ // Label 373: @7092
3165 /* 7092 */ GIM_Reject,
3166 /* 7093 */ // Label 371: @7093
3167 /* 7093 */ GIM_Reject,
3168 /* 7094 */ // Label 347: @7094
3169 /* 7094 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 377*/ GIMT_Encode4(7738),
3170 /* 7105 */ /*GILLT_v8s16*//*Label 374*/ GIMT_Encode4(7117),
3171 /* 7109 */ /*GILLT_v4s32*//*Label 375*/ GIMT_Encode4(7302),
3172 /* 7113 */ /*GILLT_v2s64*//*Label 376*/ GIMT_Encode4(7473),
3173 /* 7117 */ // Label 374: @7117
3174 /* 7117 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(7301),
3175 /* 7122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3176 /* 7126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 379*/ GIMT_Encode4(7144), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2258 //
3177 /* 7133 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3178 /* 7133 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3179 /* 7138 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3180 /* 7143 */ // GIR_Coverage, 2258,
3181 /* 7143 */ GIR_Done,
3182 /* 7144 */ // Label 379: @7144
3183 /* 7144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(7162), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2261 //
3184 /* 7151 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
3185 /* 7151 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3186 /* 7156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3187 /* 7161 */ // GIR_Coverage, 2261,
3188 /* 7161 */ GIR_Done,
3189 /* 7162 */ // Label 380: @7162
3190 /* 7162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(7231), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2300 //
3191 /* 7169 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3192 /* 7169 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3193 /* 7172 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3194 /* 7176 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3195 /* 7181 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3196 /* 7185 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3197 /* 7190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3198 /* 7193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3199 /* 7197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3200 /* 7202 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3201 /* 7205 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3202 /* 7215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3203 /* 7217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3204 /* 7220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3205 /* 7222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3206 /* 7225 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3207 /* 7230 */ // GIR_Coverage, 2300,
3208 /* 7230 */ GIR_EraseRootFromParent_Done,
3209 /* 7231 */ // Label 381: @7231
3210 /* 7231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 382*/ GIMT_Encode4(7300), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2305 //
3211 /* 7238 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3212 /* 7238 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3213 /* 7241 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3214 /* 7245 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3215 /* 7250 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3216 /* 7254 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3217 /* 7259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3218 /* 7262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3219 /* 7266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3220 /* 7271 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3221 /* 7274 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3222 /* 7284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3223 /* 7286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3224 /* 7289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3225 /* 7291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3226 /* 7294 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3227 /* 7299 */ // GIR_Coverage, 2305,
3228 /* 7299 */ GIR_EraseRootFromParent_Done,
3229 /* 7300 */ // Label 382: @7300
3230 /* 7300 */ GIM_Reject,
3231 /* 7301 */ // Label 378: @7301
3232 /* 7301 */ GIM_Reject,
3233 /* 7302 */ // Label 375: @7302
3234 /* 7302 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(7472),
3235 /* 7307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3236 /* 7311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(7329), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2259 //
3237 /* 7318 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3238 /* 7318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3239 /* 7323 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3240 /* 7328 */ // GIR_Coverage, 2259,
3241 /* 7328 */ GIR_Done,
3242 /* 7329 */ // Label 384: @7329
3243 /* 7329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 385*/ GIMT_Encode4(7347), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2262 //
3244 /* 7336 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
3245 /* 7336 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3246 /* 7341 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3247 /* 7346 */ // GIR_Coverage, 2262,
3248 /* 7346 */ GIR_Done,
3249 /* 7347 */ // Label 385: @7347
3250 /* 7347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 386*/ GIMT_Encode4(7409), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2310 //
3251 /* 7354 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3252 /* 7354 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3253 /* 7357 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3254 /* 7361 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3255 /* 7366 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3256 /* 7370 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3257 /* 7375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3258 /* 7378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3259 /* 7382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3260 /* 7387 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3261 /* 7390 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3262 /* 7393 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3263 /* 7395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3264 /* 7398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3265 /* 7400 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3266 /* 7403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3267 /* 7408 */ // GIR_Coverage, 2310,
3268 /* 7408 */ GIR_EraseRootFromParent_Done,
3269 /* 7409 */ // Label 386: @7409
3270 /* 7409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 387*/ GIMT_Encode4(7471), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2315 //
3271 /* 7416 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3272 /* 7416 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3273 /* 7419 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3274 /* 7423 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3275 /* 7428 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3276 /* 7432 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3277 /* 7437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3278 /* 7440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3279 /* 7444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3280 /* 7449 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3281 /* 7452 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3282 /* 7455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3283 /* 7457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3284 /* 7460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3285 /* 7462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3286 /* 7465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3287 /* 7470 */ // GIR_Coverage, 2315,
3288 /* 7470 */ GIR_EraseRootFromParent_Done,
3289 /* 7471 */ // Label 387: @7471
3290 /* 7471 */ GIM_Reject,
3291 /* 7472 */ // Label 383: @7472
3292 /* 7472 */ GIM_Reject,
3293 /* 7473 */ // Label 376: @7473
3294 /* 7473 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(7737),
3295 /* 7478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3296 /* 7482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(7500), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2260 //
3297 /* 7489 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3298 /* 7489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3299 /* 7494 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3300 /* 7499 */ // GIR_Coverage, 2260,
3301 /* 7499 */ GIR_Done,
3302 /* 7500 */ // Label 389: @7500
3303 /* 7500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(7518), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2263 //
3304 /* 7507 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
3305 /* 7507 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3306 /* 7512 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3307 /* 7517 */ // GIR_Coverage, 2263,
3308 /* 7517 */ GIR_Done,
3309 /* 7518 */ // Label 390: @7518
3310 /* 7518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 391*/ GIMT_Encode4(7627), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2320 //
3311 /* 7525 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3312 /* 7525 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3313 /* 7528 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3314 /* 7532 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3315 /* 7537 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3316 /* 7541 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3317 /* 7546 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3318 /* 7549 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3319 /* 7553 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3320 /* 7558 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3321 /* 7561 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3322 /* 7564 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3323 /* 7566 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3324 /* 7569 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3325 /* 7573 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3326 /* 7578 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3327 /* 7581 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3328 /* 7586 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3329 /* 7589 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3330 /* 7593 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3331 /* 7598 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3332 /* 7601 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3333 /* 7611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3334 /* 7613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3335 /* 7616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3336 /* 7618 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3337 /* 7621 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3338 /* 7626 */ // GIR_Coverage, 2320,
3339 /* 7626 */ GIR_EraseRootFromParent_Done,
3340 /* 7627 */ // Label 391: @7627
3341 /* 7627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 392*/ GIMT_Encode4(7736), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2325 //
3342 /* 7634 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3343 /* 7634 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3344 /* 7637 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3345 /* 7641 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3346 /* 7646 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3347 /* 7650 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3348 /* 7655 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3349 /* 7658 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3350 /* 7662 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3351 /* 7667 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3352 /* 7670 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3353 /* 7673 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3354 /* 7675 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3355 /* 7678 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3356 /* 7682 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3357 /* 7687 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3358 /* 7690 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3359 /* 7695 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3360 /* 7698 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3361 /* 7702 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3362 /* 7707 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3363 /* 7710 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3364 /* 7720 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3365 /* 7722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3366 /* 7725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3367 /* 7727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3368 /* 7730 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3369 /* 7735 */ // GIR_Coverage, 2325,
3370 /* 7735 */ GIR_EraseRootFromParent_Done,
3371 /* 7736 */ // Label 392: @7736
3372 /* 7736 */ GIM_Reject,
3373 /* 7737 */ // Label 388: @7737
3374 /* 7737 */ GIM_Reject,
3375 /* 7738 */ // Label 377: @7738
3376 /* 7738 */ GIM_Reject,
3377 /* 7739 */ // Label 348: @7739
3378 /* 7739 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(7796),
3379 /* 7744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3380 /* 7747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3381 /* 7751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(7773), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2162 //
3382 /* 7758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3383 /* 7762 */ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3384 /* 7762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3385 /* 7767 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3386 /* 7772 */ // GIR_Coverage, 2162,
3387 /* 7772 */ GIR_Done,
3388 /* 7773 */ // Label 394: @7773
3389 /* 7773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 395*/ GIMT_Encode4(7795), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2166 //
3390 /* 7780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3391 /* 7784 */ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3392 /* 7784 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3393 /* 7789 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3394 /* 7794 */ // GIR_Coverage, 2166,
3395 /* 7794 */ GIR_Done,
3396 /* 7795 */ // Label 395: @7795
3397 /* 7795 */ GIM_Reject,
3398 /* 7796 */ // Label 393: @7796
3399 /* 7796 */ GIM_Reject,
3400 /* 7797 */ // Label 349: @7797
3401 /* 7797 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 400*/ GIMT_Encode4(8750),
3402 /* 7808 */ /*GILLT_v16s8*//*Label 396*/ GIMT_Encode4(7828), GIMT_Encode4(0),
3403 /* 7816 */ /*GILLT_v8s16*//*Label 397*/ GIMT_Encode4(8013),
3404 /* 7820 */ /*GILLT_v4s32*//*Label 398*/ GIMT_Encode4(8060),
3405 /* 7824 */ /*GILLT_v2s64*//*Label 399*/ GIMT_Encode4(8419),
3406 /* 7828 */ // Label 396: @7828
3407 /* 7828 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(8012),
3408 /* 7833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3409 /* 7837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 402*/ GIMT_Encode4(7855), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2264 //
3410 /* 7844 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3411 /* 7844 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3412 /* 7849 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3413 /* 7854 */ // GIR_Coverage, 2264,
3414 /* 7854 */ GIR_Done,
3415 /* 7855 */ // Label 402: @7855
3416 /* 7855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 403*/ GIMT_Encode4(7873), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2279 //
3417 /* 7862 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3418 /* 7862 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3419 /* 7867 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3420 /* 7872 */ // GIR_Coverage, 2279,
3421 /* 7872 */ GIR_Done,
3422 /* 7873 */ // Label 403: @7873
3423 /* 7873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 404*/ GIMT_Encode4(7942), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2294 //
3424 /* 7880 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3425 /* 7880 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3426 /* 7883 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3427 /* 7887 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3428 /* 7892 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3429 /* 7896 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3430 /* 7901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3431 /* 7904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3432 /* 7908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3433 /* 7913 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3434 /* 7916 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3435 /* 7926 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3436 /* 7928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3437 /* 7931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3438 /* 7933 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3439 /* 7936 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3440 /* 7941 */ // GIR_Coverage, 2294,
3441 /* 7941 */ GIR_EraseRootFromParent_Done,
3442 /* 7942 */ // Label 404: @7942
3443 /* 7942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 405*/ GIMT_Encode4(8011), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2295 //
3444 /* 7949 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3445 /* 7949 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3446 /* 7952 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3447 /* 7956 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3448 /* 7961 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3449 /* 7965 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3450 /* 7970 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3451 /* 7973 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3452 /* 7977 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3453 /* 7982 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3454 /* 7985 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3455 /* 7995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3456 /* 7997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3457 /* 8000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3458 /* 8002 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3459 /* 8005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3460 /* 8010 */ // GIR_Coverage, 2295,
3461 /* 8010 */ GIR_EraseRootFromParent_Done,
3462 /* 8011 */ // Label 405: @8011
3463 /* 8011 */ GIM_Reject,
3464 /* 8012 */ // Label 401: @8012
3465 /* 8012 */ GIM_Reject,
3466 /* 8013 */ // Label 397: @8013
3467 /* 8013 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(8059),
3468 /* 8018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3469 /* 8022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 407*/ GIMT_Encode4(8040), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2252 //
3470 /* 8029 */ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3471 /* 8029 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3472 /* 8034 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3473 /* 8039 */ // GIR_Coverage, 2252,
3474 /* 8039 */ GIR_Done,
3475 /* 8040 */ // Label 407: @8040
3476 /* 8040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(8058), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2255 //
3477 /* 8047 */ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3478 /* 8047 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3479 /* 8052 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3480 /* 8057 */ // GIR_Coverage, 2255,
3481 /* 8057 */ GIR_Done,
3482 /* 8058 */ // Label 408: @8058
3483 /* 8058 */ GIM_Reject,
3484 /* 8059 */ // Label 406: @8059
3485 /* 8059 */ GIM_Reject,
3486 /* 8060 */ // Label 398: @8060
3487 /* 8060 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(8418),
3488 /* 8065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3489 /* 8069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(8087), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2265 //
3490 /* 8076 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3491 /* 8076 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3492 /* 8081 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3493 /* 8086 */ // GIR_Coverage, 2265,
3494 /* 8086 */ GIR_Done,
3495 /* 8087 */ // Label 410: @8087
3496 /* 8087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(8105), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2267 //
3497 /* 8094 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3498 /* 8094 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3499 /* 8099 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3500 /* 8104 */ // GIR_Coverage, 2267,
3501 /* 8104 */ GIR_Done,
3502 /* 8105 */ // Label 411: @8105
3503 /* 8105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(8123), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2280 //
3504 /* 8112 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3505 /* 8112 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3506 /* 8117 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3507 /* 8122 */ // GIR_Coverage, 2280,
3508 /* 8122 */ GIR_Done,
3509 /* 8123 */ // Label 412: @8123
3510 /* 8123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 413*/ GIMT_Encode4(8141), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2282 //
3511 /* 8130 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3512 /* 8130 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3513 /* 8135 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3514 /* 8140 */ // GIR_Coverage, 2282,
3515 /* 8140 */ GIR_Done,
3516 /* 8141 */ // Label 413: @8141
3517 /* 8141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 414*/ GIMT_Encode4(8210), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2311 //
3518 /* 8148 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3519 /* 8148 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3520 /* 8151 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3521 /* 8155 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3522 /* 8160 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3523 /* 8164 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3524 /* 8169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3525 /* 8172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3526 /* 8176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3527 /* 8181 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3528 /* 8184 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3529 /* 8194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3530 /* 8196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3531 /* 8199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3532 /* 8201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3533 /* 8204 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3534 /* 8209 */ // GIR_Coverage, 2311,
3535 /* 8209 */ GIR_EraseRootFromParent_Done,
3536 /* 8210 */ // Label 414: @8210
3537 /* 8210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(8279), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2312 //
3538 /* 8217 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3539 /* 8217 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3540 /* 8220 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3541 /* 8224 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3542 /* 8229 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3543 /* 8233 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3544 /* 8238 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3545 /* 8241 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3546 /* 8245 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3547 /* 8250 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3548 /* 8253 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3549 /* 8263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3550 /* 8265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3551 /* 8268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3552 /* 8270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3553 /* 8273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3554 /* 8278 */ // GIR_Coverage, 2312,
3555 /* 8278 */ GIR_EraseRootFromParent_Done,
3556 /* 8279 */ // Label 415: @8279
3557 /* 8279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(8348), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2316 //
3558 /* 8286 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3559 /* 8286 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3560 /* 8289 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3561 /* 8293 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3562 /* 8298 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3563 /* 8302 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3564 /* 8307 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3565 /* 8310 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3566 /* 8314 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3567 /* 8319 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3568 /* 8322 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3569 /* 8332 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3570 /* 8334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3571 /* 8337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3572 /* 8339 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3573 /* 8342 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3574 /* 8347 */ // GIR_Coverage, 2316,
3575 /* 8347 */ GIR_EraseRootFromParent_Done,
3576 /* 8348 */ // Label 416: @8348
3577 /* 8348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(8417), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2317 //
3578 /* 8355 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3579 /* 8355 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3580 /* 8358 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3581 /* 8362 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3582 /* 8367 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3583 /* 8371 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3584 /* 8376 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3585 /* 8379 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3586 /* 8383 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3587 /* 8388 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3588 /* 8391 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3589 /* 8401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3590 /* 8403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3591 /* 8406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3592 /* 8408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3593 /* 8411 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3594 /* 8416 */ // GIR_Coverage, 2317,
3595 /* 8416 */ GIR_EraseRootFromParent_Done,
3596 /* 8417 */ // Label 417: @8417
3597 /* 8417 */ GIM_Reject,
3598 /* 8418 */ // Label 409: @8418
3599 /* 8418 */ GIM_Reject,
3600 /* 8419 */ // Label 399: @8419
3601 /* 8419 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(8749),
3602 /* 8424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3603 /* 8428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 419*/ GIMT_Encode4(8446), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2266 //
3604 /* 8435 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3605 /* 8435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3606 /* 8440 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3607 /* 8445 */ // GIR_Coverage, 2266,
3608 /* 8445 */ GIR_Done,
3609 /* 8446 */ // Label 419: @8446
3610 /* 8446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 420*/ GIMT_Encode4(8464), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2268 //
3611 /* 8453 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3612 /* 8453 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3613 /* 8458 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3614 /* 8463 */ // GIR_Coverage, 2268,
3615 /* 8463 */ GIR_Done,
3616 /* 8464 */ // Label 420: @8464
3617 /* 8464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 421*/ GIMT_Encode4(8482), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2281 //
3618 /* 8471 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3619 /* 8471 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3620 /* 8476 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3621 /* 8481 */ // GIR_Coverage, 2281,
3622 /* 8481 */ GIR_Done,
3623 /* 8482 */ // Label 421: @8482
3624 /* 8482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 422*/ GIMT_Encode4(8500), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2283 //
3625 /* 8489 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3626 /* 8489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3627 /* 8494 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3628 /* 8499 */ // GIR_Coverage, 2283,
3629 /* 8499 */ GIR_Done,
3630 /* 8500 */ // Label 422: @8500
3631 /* 8500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 423*/ GIMT_Encode4(8562), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2321 //
3632 /* 8507 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3633 /* 8507 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3634 /* 8510 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3635 /* 8514 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3636 /* 8519 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3637 /* 8523 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3638 /* 8528 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3639 /* 8531 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3640 /* 8535 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3641 /* 8540 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3642 /* 8543 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3643 /* 8546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3644 /* 8548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3645 /* 8551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3646 /* 8553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3647 /* 8556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3648 /* 8561 */ // GIR_Coverage, 2321,
3649 /* 8561 */ GIR_EraseRootFromParent_Done,
3650 /* 8562 */ // Label 423: @8562
3651 /* 8562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 424*/ GIMT_Encode4(8624), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2322 //
3652 /* 8569 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3653 /* 8569 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3654 /* 8572 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3655 /* 8576 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3656 /* 8581 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3657 /* 8585 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3658 /* 8590 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3659 /* 8593 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3660 /* 8597 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3661 /* 8602 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3662 /* 8605 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3663 /* 8608 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3664 /* 8610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3665 /* 8613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3666 /* 8615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3667 /* 8618 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3668 /* 8623 */ // GIR_Coverage, 2322,
3669 /* 8623 */ GIR_EraseRootFromParent_Done,
3670 /* 8624 */ // Label 424: @8624
3671 /* 8624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 425*/ GIMT_Encode4(8686), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2326 //
3672 /* 8631 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3673 /* 8631 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3674 /* 8634 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3675 /* 8638 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3676 /* 8643 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3677 /* 8647 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3678 /* 8652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3679 /* 8655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3680 /* 8659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3681 /* 8664 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3682 /* 8667 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3683 /* 8670 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3684 /* 8672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3685 /* 8675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3686 /* 8677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3687 /* 8680 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3688 /* 8685 */ // GIR_Coverage, 2326,
3689 /* 8685 */ GIR_EraseRootFromParent_Done,
3690 /* 8686 */ // Label 425: @8686
3691 /* 8686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 426*/ GIMT_Encode4(8748), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2327 //
3692 /* 8693 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3693 /* 8693 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3694 /* 8696 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3695 /* 8700 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3696 /* 8705 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3697 /* 8709 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3698 /* 8714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3699 /* 8717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3700 /* 8721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3701 /* 8726 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3702 /* 8729 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3703 /* 8732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3704 /* 8734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3705 /* 8737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3706 /* 8739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3707 /* 8742 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3708 /* 8747 */ // GIR_Coverage, 2327,
3709 /* 8747 */ GIR_EraseRootFromParent_Done,
3710 /* 8748 */ // Label 426: @8748
3711 /* 8748 */ GIM_Reject,
3712 /* 8749 */ // Label 418: @8749
3713 /* 8749 */ GIM_Reject,
3714 /* 8750 */ // Label 400: @8750
3715 /* 8750 */ GIM_Reject,
3716 /* 8751 */ // Label 350: @8751
3717 /* 8751 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 431*/ GIMT_Encode4(9718),
3718 /* 8762 */ /*GILLT_v16s8*//*Label 427*/ GIMT_Encode4(8782), GIMT_Encode4(0),
3719 /* 8770 */ /*GILLT_v8s16*//*Label 428*/ GIMT_Encode4(8953),
3720 /* 8774 */ /*GILLT_v4s32*//*Label 429*/ GIMT_Encode4(9312),
3721 /* 8778 */ /*GILLT_v2s64*//*Label 430*/ GIMT_Encode4(9359),
3722 /* 8782 */ // Label 427: @8782
3723 /* 8782 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(8952),
3724 /* 8787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3725 /* 8791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 433*/ GIMT_Encode4(8809), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2269 //
3726 /* 8798 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3727 /* 8798 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3728 /* 8803 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3729 /* 8808 */ // GIR_Coverage, 2269,
3730 /* 8808 */ GIR_Done,
3731 /* 8809 */ // Label 433: @8809
3732 /* 8809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(8827), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2284 //
3733 /* 8816 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3734 /* 8816 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3735 /* 8821 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3736 /* 8826 */ // GIR_Coverage, 2284,
3737 /* 8826 */ GIR_Done,
3738 /* 8827 */ // Label 434: @8827
3739 /* 8827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 435*/ GIMT_Encode4(8889), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2296 //
3740 /* 8834 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3741 /* 8834 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3742 /* 8837 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3743 /* 8841 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3744 /* 8846 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3745 /* 8850 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3746 /* 8855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3747 /* 8858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3748 /* 8862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3749 /* 8867 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3750 /* 8870 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3751 /* 8873 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3752 /* 8875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3753 /* 8878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3754 /* 8880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3755 /* 8883 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3756 /* 8888 */ // GIR_Coverage, 2296,
3757 /* 8888 */ GIR_EraseRootFromParent_Done,
3758 /* 8889 */ // Label 435: @8889
3759 /* 8889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 436*/ GIMT_Encode4(8951), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2297 //
3760 /* 8896 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3761 /* 8896 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3762 /* 8899 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3763 /* 8903 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3764 /* 8908 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3765 /* 8912 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3766 /* 8917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3767 /* 8920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3768 /* 8924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3769 /* 8929 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3770 /* 8932 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3771 /* 8935 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3772 /* 8937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3773 /* 8940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3774 /* 8942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3775 /* 8945 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3776 /* 8950 */ // GIR_Coverage, 2297,
3777 /* 8950 */ GIR_EraseRootFromParent_Done,
3778 /* 8951 */ // Label 436: @8951
3779 /* 8951 */ GIM_Reject,
3780 /* 8952 */ // Label 432: @8952
3781 /* 8952 */ GIM_Reject,
3782 /* 8953 */ // Label 428: @8953
3783 /* 8953 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(9311),
3784 /* 8958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3785 /* 8962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 438*/ GIMT_Encode4(8980), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2270 //
3786 /* 8969 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3787 /* 8969 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3788 /* 8974 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3789 /* 8979 */ // GIR_Coverage, 2270,
3790 /* 8979 */ GIR_Done,
3791 /* 8980 */ // Label 438: @8980
3792 /* 8980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 439*/ GIMT_Encode4(8998), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2272 //
3793 /* 8987 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3794 /* 8987 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3795 /* 8992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3796 /* 8997 */ // GIR_Coverage, 2272,
3797 /* 8997 */ GIR_Done,
3798 /* 8998 */ // Label 439: @8998
3799 /* 8998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 440*/ GIMT_Encode4(9016), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2285 //
3800 /* 9005 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3801 /* 9005 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3802 /* 9010 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3803 /* 9015 */ // GIR_Coverage, 2285,
3804 /* 9015 */ GIR_Done,
3805 /* 9016 */ // Label 440: @9016
3806 /* 9016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 441*/ GIMT_Encode4(9034), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2287 //
3807 /* 9023 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3808 /* 9023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3809 /* 9028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3810 /* 9033 */ // GIR_Coverage, 2287,
3811 /* 9033 */ GIR_Done,
3812 /* 9034 */ // Label 441: @9034
3813 /* 9034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 442*/ GIMT_Encode4(9103), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2301 //
3814 /* 9041 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3815 /* 9041 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3816 /* 9044 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3817 /* 9048 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3818 /* 9053 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3819 /* 9057 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3820 /* 9062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3821 /* 9065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3822 /* 9069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3823 /* 9074 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3824 /* 9077 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3825 /* 9087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3826 /* 9089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3827 /* 9092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3828 /* 9094 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3829 /* 9097 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3830 /* 9102 */ // GIR_Coverage, 2301,
3831 /* 9102 */ GIR_EraseRootFromParent_Done,
3832 /* 9103 */ // Label 442: @9103
3833 /* 9103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 443*/ GIMT_Encode4(9172), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2302 //
3834 /* 9110 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3835 /* 9110 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3836 /* 9113 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3837 /* 9117 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3838 /* 9122 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3839 /* 9126 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3840 /* 9131 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3841 /* 9134 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3842 /* 9138 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3843 /* 9143 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3844 /* 9146 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3845 /* 9156 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3846 /* 9158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3847 /* 9161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3848 /* 9163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3849 /* 9166 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3850 /* 9171 */ // GIR_Coverage, 2302,
3851 /* 9171 */ GIR_EraseRootFromParent_Done,
3852 /* 9172 */ // Label 443: @9172
3853 /* 9172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 444*/ GIMT_Encode4(9241), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2306 //
3854 /* 9179 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3855 /* 9179 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3856 /* 9182 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3857 /* 9186 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3858 /* 9191 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3859 /* 9195 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3860 /* 9200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3861 /* 9203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3862 /* 9207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3863 /* 9212 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3864 /* 9215 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3865 /* 9225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3866 /* 9227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3867 /* 9230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3868 /* 9232 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3869 /* 9235 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3870 /* 9240 */ // GIR_Coverage, 2306,
3871 /* 9240 */ GIR_EraseRootFromParent_Done,
3872 /* 9241 */ // Label 444: @9241
3873 /* 9241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 445*/ GIMT_Encode4(9310), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2307 //
3874 /* 9248 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3875 /* 9248 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3876 /* 9251 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3877 /* 9255 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3878 /* 9260 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3879 /* 9264 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3880 /* 9269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3881 /* 9272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3882 /* 9276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3883 /* 9281 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3884 /* 9284 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3885 /* 9294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3886 /* 9296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3887 /* 9299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3888 /* 9301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3889 /* 9304 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3890 /* 9309 */ // GIR_Coverage, 2307,
3891 /* 9309 */ GIR_EraseRootFromParent_Done,
3892 /* 9310 */ // Label 445: @9310
3893 /* 9310 */ GIM_Reject,
3894 /* 9311 */ // Label 437: @9311
3895 /* 9311 */ GIM_Reject,
3896 /* 9312 */ // Label 429: @9312
3897 /* 9312 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(9358),
3898 /* 9317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3899 /* 9321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 447*/ GIMT_Encode4(9339), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2253 //
3900 /* 9328 */ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3901 /* 9328 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3902 /* 9333 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3903 /* 9338 */ // GIR_Coverage, 2253,
3904 /* 9338 */ GIR_Done,
3905 /* 9339 */ // Label 447: @9339
3906 /* 9339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 448*/ GIMT_Encode4(9357), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2256 //
3907 /* 9346 */ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3908 /* 9346 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3909 /* 9351 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3910 /* 9356 */ // GIR_Coverage, 2256,
3911 /* 9356 */ GIR_Done,
3912 /* 9357 */ // Label 448: @9357
3913 /* 9357 */ GIM_Reject,
3914 /* 9358 */ // Label 446: @9358
3915 /* 9358 */ GIM_Reject,
3916 /* 9359 */ // Label 430: @9359
3917 /* 9359 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(9717),
3918 /* 9364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3919 /* 9368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 450*/ GIMT_Encode4(9386), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2271 //
3920 /* 9375 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3921 /* 9375 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3922 /* 9380 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3923 /* 9385 */ // GIR_Coverage, 2271,
3924 /* 9385 */ GIR_Done,
3925 /* 9386 */ // Label 450: @9386
3926 /* 9386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 451*/ GIMT_Encode4(9404), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2273 //
3927 /* 9393 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3928 /* 9393 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3929 /* 9398 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3930 /* 9403 */ // GIR_Coverage, 2273,
3931 /* 9403 */ GIR_Done,
3932 /* 9404 */ // Label 451: @9404
3933 /* 9404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 452*/ GIMT_Encode4(9422), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2286 //
3934 /* 9411 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3935 /* 9411 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3936 /* 9416 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3937 /* 9421 */ // GIR_Coverage, 2286,
3938 /* 9421 */ GIR_Done,
3939 /* 9422 */ // Label 452: @9422
3940 /* 9422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 453*/ GIMT_Encode4(9440), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2288 //
3941 /* 9429 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3942 /* 9429 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3943 /* 9434 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3944 /* 9439 */ // GIR_Coverage, 2288,
3945 /* 9439 */ GIR_Done,
3946 /* 9440 */ // Label 453: @9440
3947 /* 9440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 454*/ GIMT_Encode4(9509), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2323 //
3948 /* 9447 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3949 /* 9447 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3950 /* 9450 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3951 /* 9454 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3952 /* 9459 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3953 /* 9463 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3954 /* 9468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3955 /* 9471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3956 /* 9475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3957 /* 9480 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3958 /* 9483 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3959 /* 9493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3960 /* 9495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3961 /* 9498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3962 /* 9500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3963 /* 9503 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3964 /* 9508 */ // GIR_Coverage, 2323,
3965 /* 9508 */ GIR_EraseRootFromParent_Done,
3966 /* 9509 */ // Label 454: @9509
3967 /* 9509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 455*/ GIMT_Encode4(9578), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2324 //
3968 /* 9516 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3969 /* 9516 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3970 /* 9519 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3971 /* 9523 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3972 /* 9528 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3973 /* 9532 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3974 /* 9537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3975 /* 9540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3976 /* 9544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3977 /* 9549 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3978 /* 9552 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3979 /* 9562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3980 /* 9564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3981 /* 9567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3982 /* 9569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3983 /* 9572 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3984 /* 9577 */ // GIR_Coverage, 2324,
3985 /* 9577 */ GIR_EraseRootFromParent_Done,
3986 /* 9578 */ // Label 455: @9578
3987 /* 9578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 456*/ GIMT_Encode4(9647), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2328 //
3988 /* 9585 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3989 /* 9585 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3990 /* 9588 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3991 /* 9592 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3992 /* 9597 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3993 /* 9601 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3994 /* 9606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3995 /* 9609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3996 /* 9613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3997 /* 9618 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3998 /* 9621 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3999 /* 9631 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4000 /* 9633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4001 /* 9636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4002 /* 9638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4003 /* 9641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4004 /* 9646 */ // GIR_Coverage, 2328,
4005 /* 9646 */ GIR_EraseRootFromParent_Done,
4006 /* 9647 */ // Label 456: @9647
4007 /* 9647 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 457*/ GIMT_Encode4(9716), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2329 //
4008 /* 9654 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4009 /* 9654 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4010 /* 9657 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4011 /* 9661 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4012 /* 9666 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4013 /* 9670 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4014 /* 9675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4015 /* 9678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4016 /* 9682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4017 /* 9687 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4018 /* 9690 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4019 /* 9700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4020 /* 9702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4021 /* 9705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4022 /* 9707 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4023 /* 9710 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4024 /* 9715 */ // GIR_Coverage, 2329,
4025 /* 9715 */ GIR_EraseRootFromParent_Done,
4026 /* 9716 */ // Label 457: @9716
4027 /* 9716 */ GIM_Reject,
4028 /* 9717 */ // Label 449: @9717
4029 /* 9717 */ GIM_Reject,
4030 /* 9718 */ // Label 431: @9718
4031 /* 9718 */ GIM_Reject,
4032 /* 9719 */ // Label 351: @9719
4033 /* 9719 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 462*/ GIMT_Encode4(10752),
4034 /* 9730 */ /*GILLT_v16s8*//*Label 458*/ GIMT_Encode4(9750), GIMT_Encode4(0),
4035 /* 9738 */ /*GILLT_v8s16*//*Label 459*/ GIMT_Encode4(10015),
4036 /* 9742 */ /*GILLT_v4s32*//*Label 460*/ GIMT_Encode4(10346),
4037 /* 9746 */ /*GILLT_v2s64*//*Label 461*/ GIMT_Encode4(10705),
4038 /* 9750 */ // Label 458: @9750
4039 /* 9750 */ GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(10014),
4040 /* 9755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4041 /* 9759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(9777), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2274 //
4042 /* 9766 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
4043 /* 9766 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4044 /* 9771 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4045 /* 9776 */ // GIR_Coverage, 2274,
4046 /* 9776 */ GIR_Done,
4047 /* 9777 */ // Label 464: @9777
4048 /* 9777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(9795), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2289 //
4049 /* 9784 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
4050 /* 9784 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4051 /* 9789 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4052 /* 9794 */ // GIR_Coverage, 2289,
4053 /* 9794 */ GIR_Done,
4054 /* 9795 */ // Label 465: @9795
4055 /* 9795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(9904), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2298 //
4056 /* 9802 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4057 /* 9802 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4058 /* 9805 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4059 /* 9809 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4060 /* 9814 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4061 /* 9818 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4062 /* 9823 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4063 /* 9826 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4064 /* 9830 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4065 /* 9835 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4066 /* 9838 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4067 /* 9841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4068 /* 9843 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4069 /* 9846 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4070 /* 9850 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4071 /* 9855 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4072 /* 9858 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4073 /* 9863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4074 /* 9866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4075 /* 9870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4076 /* 9875 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4077 /* 9878 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4078 /* 9888 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4079 /* 9890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4080 /* 9893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4081 /* 9895 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4082 /* 9898 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4083 /* 9903 */ // GIR_Coverage, 2298,
4084 /* 9903 */ GIR_EraseRootFromParent_Done,
4085 /* 9904 */ // Label 466: @9904
4086 /* 9904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(10013), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2299 //
4087 /* 9911 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4088 /* 9911 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4089 /* 9914 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4090 /* 9918 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4091 /* 9923 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4092 /* 9927 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4093 /* 9932 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4094 /* 9935 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4095 /* 9939 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4096 /* 9944 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4097 /* 9947 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4098 /* 9950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4099 /* 9952 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4100 /* 9955 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4101 /* 9959 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4102 /* 9964 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4103 /* 9967 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4104 /* 9972 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4105 /* 9975 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4106 /* 9979 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4107 /* 9984 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4108 /* 9987 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4109 /* 9997 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4110 /* 9999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4111 /* 10002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4112 /* 10004 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4113 /* 10007 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4114 /* 10012 */ // GIR_Coverage, 2299,
4115 /* 10012 */ GIR_EraseRootFromParent_Done,
4116 /* 10013 */ // Label 467: @10013
4117 /* 10013 */ GIM_Reject,
4118 /* 10014 */ // Label 463: @10014
4119 /* 10014 */ GIM_Reject,
4120 /* 10015 */ // Label 459: @10015
4121 /* 10015 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(10345),
4122 /* 10020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4123 /* 10024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(10042), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2275 //
4124 /* 10031 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4125 /* 10031 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4126 /* 10036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4127 /* 10041 */ // GIR_Coverage, 2275,
4128 /* 10041 */ GIR_Done,
4129 /* 10042 */ // Label 469: @10042
4130 /* 10042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(10060), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2277 //
4131 /* 10049 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4132 /* 10049 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4133 /* 10054 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4134 /* 10059 */ // GIR_Coverage, 2277,
4135 /* 10059 */ GIR_Done,
4136 /* 10060 */ // Label 470: @10060
4137 /* 10060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 471*/ GIMT_Encode4(10078), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2290 //
4138 /* 10067 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4139 /* 10067 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4140 /* 10072 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4141 /* 10077 */ // GIR_Coverage, 2290,
4142 /* 10077 */ GIR_Done,
4143 /* 10078 */ // Label 471: @10078
4144 /* 10078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(10096), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2292 //
4145 /* 10085 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4146 /* 10085 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4147 /* 10090 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4148 /* 10095 */ // GIR_Coverage, 2292,
4149 /* 10095 */ GIR_Done,
4150 /* 10096 */ // Label 472: @10096
4151 /* 10096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(10158), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2303 //
4152 /* 10103 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4153 /* 10103 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4154 /* 10106 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4155 /* 10110 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4156 /* 10115 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4157 /* 10119 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4158 /* 10124 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4159 /* 10127 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4160 /* 10131 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4161 /* 10136 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4162 /* 10139 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4163 /* 10142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4164 /* 10144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4165 /* 10147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4166 /* 10149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4167 /* 10152 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4168 /* 10157 */ // GIR_Coverage, 2303,
4169 /* 10157 */ GIR_EraseRootFromParent_Done,
4170 /* 10158 */ // Label 473: @10158
4171 /* 10158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(10220), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2304 //
4172 /* 10165 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4173 /* 10165 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4174 /* 10168 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4175 /* 10172 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4176 /* 10177 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4177 /* 10181 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4178 /* 10186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4179 /* 10189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4180 /* 10193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4181 /* 10198 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4182 /* 10201 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4183 /* 10204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4184 /* 10206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4185 /* 10209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4186 /* 10211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4187 /* 10214 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4188 /* 10219 */ // GIR_Coverage, 2304,
4189 /* 10219 */ GIR_EraseRootFromParent_Done,
4190 /* 10220 */ // Label 474: @10220
4191 /* 10220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(10282), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2308 //
4192 /* 10227 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4193 /* 10227 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4194 /* 10230 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4195 /* 10234 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4196 /* 10239 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4197 /* 10243 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4198 /* 10248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4199 /* 10251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4200 /* 10255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4201 /* 10260 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4202 /* 10263 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4203 /* 10266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4204 /* 10268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4205 /* 10271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4206 /* 10273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4207 /* 10276 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4208 /* 10281 */ // GIR_Coverage, 2308,
4209 /* 10281 */ GIR_EraseRootFromParent_Done,
4210 /* 10282 */ // Label 475: @10282
4211 /* 10282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(10344), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2309 //
4212 /* 10289 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4213 /* 10289 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4214 /* 10292 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4215 /* 10296 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4216 /* 10301 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4217 /* 10305 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4218 /* 10310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4219 /* 10313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4220 /* 10317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4221 /* 10322 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4222 /* 10325 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4223 /* 10328 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4224 /* 10330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4225 /* 10333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4226 /* 10335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4227 /* 10338 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4228 /* 10343 */ // GIR_Coverage, 2309,
4229 /* 10343 */ GIR_EraseRootFromParent_Done,
4230 /* 10344 */ // Label 476: @10344
4231 /* 10344 */ GIM_Reject,
4232 /* 10345 */ // Label 468: @10345
4233 /* 10345 */ GIM_Reject,
4234 /* 10346 */ // Label 460: @10346
4235 /* 10346 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(10704),
4236 /* 10351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4237 /* 10355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 478*/ GIMT_Encode4(10373), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2276 //
4238 /* 10362 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4239 /* 10362 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4240 /* 10367 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4241 /* 10372 */ // GIR_Coverage, 2276,
4242 /* 10372 */ GIR_Done,
4243 /* 10373 */ // Label 478: @10373
4244 /* 10373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(10391), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2278 //
4245 /* 10380 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4246 /* 10380 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4247 /* 10385 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4248 /* 10390 */ // GIR_Coverage, 2278,
4249 /* 10390 */ GIR_Done,
4250 /* 10391 */ // Label 479: @10391
4251 /* 10391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 480*/ GIMT_Encode4(10409), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2291 //
4252 /* 10398 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4253 /* 10398 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4254 /* 10403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4255 /* 10408 */ // GIR_Coverage, 2291,
4256 /* 10408 */ GIR_Done,
4257 /* 10409 */ // Label 480: @10409
4258 /* 10409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 481*/ GIMT_Encode4(10427), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2293 //
4259 /* 10416 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4260 /* 10416 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4261 /* 10421 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4262 /* 10426 */ // GIR_Coverage, 2293,
4263 /* 10426 */ GIR_Done,
4264 /* 10427 */ // Label 481: @10427
4265 /* 10427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(10496), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2313 //
4266 /* 10434 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4267 /* 10434 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4268 /* 10437 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4269 /* 10441 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4270 /* 10446 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4271 /* 10450 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4272 /* 10455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4273 /* 10458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4274 /* 10462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4275 /* 10467 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4276 /* 10470 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4277 /* 10480 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4278 /* 10482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4279 /* 10485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4280 /* 10487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4281 /* 10490 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4282 /* 10495 */ // GIR_Coverage, 2313,
4283 /* 10495 */ GIR_EraseRootFromParent_Done,
4284 /* 10496 */ // Label 482: @10496
4285 /* 10496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(10565), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2314 //
4286 /* 10503 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4287 /* 10503 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4288 /* 10506 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4289 /* 10510 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4290 /* 10515 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4291 /* 10519 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4292 /* 10524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4293 /* 10527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4294 /* 10531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4295 /* 10536 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4296 /* 10539 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4297 /* 10549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4298 /* 10551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4299 /* 10554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4300 /* 10556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4301 /* 10559 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4302 /* 10564 */ // GIR_Coverage, 2314,
4303 /* 10564 */ GIR_EraseRootFromParent_Done,
4304 /* 10565 */ // Label 483: @10565
4305 /* 10565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(10634), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2318 //
4306 /* 10572 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4307 /* 10572 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4308 /* 10575 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4309 /* 10579 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4310 /* 10584 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4311 /* 10588 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4312 /* 10593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4313 /* 10596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4314 /* 10600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4315 /* 10605 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4316 /* 10608 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4317 /* 10618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4318 /* 10620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4319 /* 10623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4320 /* 10625 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4321 /* 10628 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4322 /* 10633 */ // GIR_Coverage, 2318,
4323 /* 10633 */ GIR_EraseRootFromParent_Done,
4324 /* 10634 */ // Label 484: @10634
4325 /* 10634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(10703), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2319 //
4326 /* 10641 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4327 /* 10641 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4328 /* 10644 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4329 /* 10648 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4330 /* 10653 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4331 /* 10657 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4332 /* 10662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4333 /* 10665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4334 /* 10669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4335 /* 10674 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4336 /* 10677 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4337 /* 10687 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4338 /* 10689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4339 /* 10692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4340 /* 10694 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4341 /* 10697 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4342 /* 10702 */ // GIR_Coverage, 2319,
4343 /* 10702 */ GIR_EraseRootFromParent_Done,
4344 /* 10703 */ // Label 485: @10703
4345 /* 10703 */ GIM_Reject,
4346 /* 10704 */ // Label 477: @10704
4347 /* 10704 */ GIM_Reject,
4348 /* 10705 */ // Label 461: @10705
4349 /* 10705 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(10751),
4350 /* 10710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4351 /* 10714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 487*/ GIMT_Encode4(10732), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2254 //
4352 /* 10721 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
4353 /* 10721 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4354 /* 10726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4355 /* 10731 */ // GIR_Coverage, 2254,
4356 /* 10731 */ GIR_Done,
4357 /* 10732 */ // Label 487: @10732
4358 /* 10732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 488*/ GIMT_Encode4(10750), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2257 //
4359 /* 10739 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
4360 /* 10739 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4361 /* 10744 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4362 /* 10749 */ // GIR_Coverage, 2257,
4363 /* 10749 */ GIR_Done,
4364 /* 10750 */ // Label 488: @10750
4365 /* 10750 */ GIM_Reject,
4366 /* 10751 */ // Label 486: @10751
4367 /* 10751 */ GIM_Reject,
4368 /* 10752 */ // Label 462: @10752
4369 /* 10752 */ GIM_Reject,
4370 /* 10753 */ // Label 352: @10753
4371 /* 10753 */ GIM_Reject,
4372 /* 10754 */ // Label 13: @10754
4373 /* 10754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 489*/ GIMT_Encode4(10817), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2240 //
4374 /* 10761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4375 /* 10764 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4376 /* 10767 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4377 /* 10771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4378 /* 10775 */ // MIs[0] Operand 1
4379 /* 10775 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4380 /* 10779 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4381 /* 10783 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4382 /* 10787 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4383 /* 10791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4384 /* 10795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4385 /* 10797 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4386 /* 10797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4387 /* 10800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4388 /* 10802 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4389 /* 10806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4390 /* 10810 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4391 /* 10815 */ GIR_RootConstrainSelectedInstOperands,
4392 /* 10816 */ // GIR_Coverage, 2240,
4393 /* 10816 */ GIR_EraseRootFromParent_Done,
4394 /* 10817 */ // Label 489: @10817
4395 /* 10817 */ GIM_Reject,
4396 /* 10818 */ // Label 14: @10818
4397 /* 10818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(10884), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2239 //
4398 /* 10825 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4399 /* 10828 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4400 /* 10831 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4401 /* 10838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4402 /* 10842 */ // MIs[0] Operand 1
4403 /* 10842 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4404 /* 10846 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4405 /* 10850 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4406 /* 10854 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4407 /* 10858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4408 /* 10862 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4409 /* 10864 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4410 /* 10864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4411 /* 10867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4412 /* 10869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4413 /* 10873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4414 /* 10877 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4415 /* 10882 */ GIR_RootConstrainSelectedInstOperands,
4416 /* 10883 */ // GIR_Coverage, 2239,
4417 /* 10883 */ GIR_EraseRootFromParent_Done,
4418 /* 10884 */ // Label 490: @10884
4419 /* 10884 */ GIM_Reject,
4420 /* 10885 */ // Label 15: @10885
4421 /* 10885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(10951), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2238 //
4422 /* 10892 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4423 /* 10895 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4424 /* 10898 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4425 /* 10905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4426 /* 10909 */ // MIs[0] Operand 1
4427 /* 10909 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4428 /* 10913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4429 /* 10917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4430 /* 10921 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4431 /* 10925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4432 /* 10929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4433 /* 10931 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4434 /* 10931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4435 /* 10934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4436 /* 10936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4437 /* 10940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4438 /* 10944 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4439 /* 10949 */ GIR_RootConstrainSelectedInstOperands,
4440 /* 10950 */ // GIR_Coverage, 2238,
4441 /* 10950 */ GIR_EraseRootFromParent_Done,
4442 /* 10951 */ // Label 491: @10951
4443 /* 10951 */ GIM_Reject,
4444 /* 10952 */ // Label 16: @10952
4445 /* 10952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 494*/ GIMT_Encode4(11139),
4446 /* 10963 */ /*GILLT_s32*//*Label 492*/ GIMT_Encode4(10971),
4447 /* 10967 */ /*GILLT_s64*//*Label 493*/ GIMT_Encode4(11095),
4448 /* 10971 */ // Label 492: @10971
4449 /* 10971 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(11094),
4450 /* 10976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4451 /* 10979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
4452 /* 10982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 496*/ GIMT_Encode4(11019), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 25 //
4453 /* 10989 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4454 /* 10996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4455 /* 11000 */ // MIs[0] ptr
4456 /* 11000 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4457 /* 11004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4458 /* 11008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4459 /* 11012 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4460 /* 11012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4461 /* 11017 */ GIR_RootConstrainSelectedInstOperands,
4462 /* 11018 */ // GIR_Coverage, 25,
4463 /* 11018 */ GIR_Done,
4464 /* 11019 */ // Label 496: @11019
4465 /* 11019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 497*/ GIMT_Encode4(11056), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 26 //
4466 /* 11026 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4467 /* 11033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4468 /* 11037 */ // MIs[0] ptr
4469 /* 11037 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4470 /* 11041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4471 /* 11045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4472 /* 11049 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4473 /* 11049 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4474 /* 11054 */ GIR_RootConstrainSelectedInstOperands,
4475 /* 11055 */ // GIR_Coverage, 26,
4476 /* 11055 */ GIR_Done,
4477 /* 11056 */ // Label 497: @11056
4478 /* 11056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(11093), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 27 //
4479 /* 11063 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4480 /* 11070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4481 /* 11074 */ // MIs[0] ptr
4482 /* 11074 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4483 /* 11078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4484 /* 11082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4485 /* 11086 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4486 /* 11086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4487 /* 11091 */ GIR_RootConstrainSelectedInstOperands,
4488 /* 11092 */ // GIR_Coverage, 27,
4489 /* 11092 */ GIR_Done,
4490 /* 11093 */ // Label 498: @11093
4491 /* 11093 */ GIM_Reject,
4492 /* 11094 */ // Label 495: @11094
4493 /* 11094 */ GIM_Reject,
4494 /* 11095 */ // Label 493: @11095
4495 /* 11095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 499*/ GIMT_Encode4(11138), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 246 //
4496 /* 11102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4497 /* 11105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
4498 /* 11108 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4499 /* 11115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4500 /* 11119 */ // MIs[0] ptr
4501 /* 11119 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4502 /* 11123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4503 /* 11127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4504 /* 11131 */ // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4505 /* 11131 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4506 /* 11136 */ GIR_RootConstrainSelectedInstOperands,
4507 /* 11137 */ // GIR_Coverage, 246,
4508 /* 11137 */ GIR_Done,
4509 /* 11138 */ // Label 499: @11138
4510 /* 11138 */ GIM_Reject,
4511 /* 11139 */ // Label 494: @11139
4512 /* 11139 */ GIM_Reject,
4513 /* 11140 */ // Label 17: @11140
4514 /* 11140 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 502*/ GIMT_Encode4(11305),
4515 /* 11151 */ /*GILLT_s32*//*Label 500*/ GIMT_Encode4(11159),
4516 /* 11155 */ /*GILLT_s64*//*Label 501*/ GIMT_Encode4(11268),
4517 /* 11159 */ // Label 500: @11159
4518 /* 11159 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(11267),
4519 /* 11164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4520 /* 11167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 504*/ GIMT_Encode4(11200), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 22 //
4521 /* 11174 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4522 /* 11181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4523 /* 11185 */ // MIs[0] ptr
4524 /* 11185 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4525 /* 11189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4526 /* 11193 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4527 /* 11193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4528 /* 11198 */ GIR_RootConstrainSelectedInstOperands,
4529 /* 11199 */ // GIR_Coverage, 22,
4530 /* 11199 */ GIR_Done,
4531 /* 11200 */ // Label 504: @11200
4532 /* 11200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 505*/ GIMT_Encode4(11233), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 23 //
4533 /* 11207 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4534 /* 11214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4535 /* 11218 */ // MIs[0] ptr
4536 /* 11218 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4537 /* 11222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4538 /* 11226 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4539 /* 11226 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4540 /* 11231 */ GIR_RootConstrainSelectedInstOperands,
4541 /* 11232 */ // GIR_Coverage, 23,
4542 /* 11232 */ GIR_Done,
4543 /* 11233 */ // Label 505: @11233
4544 /* 11233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 506*/ GIMT_Encode4(11266), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 24 //
4545 /* 11240 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4546 /* 11247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4547 /* 11251 */ // MIs[0] ptr
4548 /* 11251 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4549 /* 11255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4550 /* 11259 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4551 /* 11259 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4552 /* 11264 */ GIR_RootConstrainSelectedInstOperands,
4553 /* 11265 */ // GIR_Coverage, 24,
4554 /* 11265 */ GIR_Done,
4555 /* 11266 */ // Label 506: @11266
4556 /* 11266 */ GIM_Reject,
4557 /* 11267 */ // Label 503: @11267
4558 /* 11267 */ GIM_Reject,
4559 /* 11268 */ // Label 501: @11268
4560 /* 11268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 507*/ GIMT_Encode4(11304), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 245 //
4561 /* 11275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4562 /* 11278 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4563 /* 11285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4564 /* 11289 */ // MIs[0] ptr
4565 /* 11289 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4566 /* 11293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4567 /* 11297 */ // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4568 /* 11297 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4569 /* 11302 */ GIR_RootConstrainSelectedInstOperands,
4570 /* 11303 */ // GIR_Coverage, 245,
4571 /* 11303 */ GIR_Done,
4572 /* 11304 */ // Label 507: @11304
4573 /* 11304 */ GIM_Reject,
4574 /* 11305 */ // Label 502: @11305
4575 /* 11305 */ GIM_Reject,
4576 /* 11306 */ // Label 18: @11306
4577 /* 11306 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 510*/ GIMT_Encode4(11471),
4578 /* 11317 */ /*GILLT_s32*//*Label 508*/ GIMT_Encode4(11325),
4579 /* 11321 */ /*GILLT_s64*//*Label 509*/ GIMT_Encode4(11434),
4580 /* 11325 */ // Label 508: @11325
4581 /* 11325 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(11433),
4582 /* 11330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4583 /* 11333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 512*/ GIMT_Encode4(11366), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 4 //
4584 /* 11340 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4585 /* 11347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4586 /* 11351 */ // MIs[0] ptr
4587 /* 11351 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4588 /* 11355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4589 /* 11359 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4590 /* 11359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4591 /* 11364 */ GIR_RootConstrainSelectedInstOperands,
4592 /* 11365 */ // GIR_Coverage, 4,
4593 /* 11365 */ GIR_Done,
4594 /* 11366 */ // Label 512: @11366
4595 /* 11366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 513*/ GIMT_Encode4(11399), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 5 //
4596 /* 11373 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4597 /* 11380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4598 /* 11384 */ // MIs[0] ptr
4599 /* 11384 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4600 /* 11388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4601 /* 11392 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4602 /* 11392 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4603 /* 11397 */ GIR_RootConstrainSelectedInstOperands,
4604 /* 11398 */ // GIR_Coverage, 5,
4605 /* 11398 */ GIR_Done,
4606 /* 11399 */ // Label 513: @11399
4607 /* 11399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 514*/ GIMT_Encode4(11432), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 6 //
4608 /* 11406 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4609 /* 11413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4610 /* 11417 */ // MIs[0] ptr
4611 /* 11417 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4612 /* 11421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4613 /* 11425 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4614 /* 11425 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4615 /* 11430 */ GIR_RootConstrainSelectedInstOperands,
4616 /* 11431 */ // GIR_Coverage, 6,
4617 /* 11431 */ GIR_Done,
4618 /* 11432 */ // Label 514: @11432
4619 /* 11432 */ GIM_Reject,
4620 /* 11433 */ // Label 511: @11433
4621 /* 11433 */ GIM_Reject,
4622 /* 11434 */ // Label 509: @11434
4623 /* 11434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 515*/ GIMT_Encode4(11470), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 239 //
4624 /* 11441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4625 /* 11444 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4626 /* 11451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4627 /* 11455 */ // MIs[0] ptr
4628 /* 11455 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4629 /* 11459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4630 /* 11463 */ // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4631 /* 11463 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4632 /* 11468 */ GIR_RootConstrainSelectedInstOperands,
4633 /* 11469 */ // GIR_Coverage, 239,
4634 /* 11469 */ GIR_Done,
4635 /* 11470 */ // Label 515: @11470
4636 /* 11470 */ GIM_Reject,
4637 /* 11471 */ // Label 510: @11471
4638 /* 11471 */ GIM_Reject,
4639 /* 11472 */ // Label 19: @11472
4640 /* 11472 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 518*/ GIMT_Encode4(11637),
4641 /* 11483 */ /*GILLT_s32*//*Label 516*/ GIMT_Encode4(11491),
4642 /* 11487 */ /*GILLT_s64*//*Label 517*/ GIMT_Encode4(11600),
4643 /* 11491 */ // Label 516: @11491
4644 /* 11491 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(11599),
4645 /* 11496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4646 /* 11499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 520*/ GIMT_Encode4(11532), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 7 //
4647 /* 11506 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4648 /* 11513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4649 /* 11517 */ // MIs[0] ptr
4650 /* 11517 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4651 /* 11521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4652 /* 11525 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4653 /* 11525 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4654 /* 11530 */ GIR_RootConstrainSelectedInstOperands,
4655 /* 11531 */ // GIR_Coverage, 7,
4656 /* 11531 */ GIR_Done,
4657 /* 11532 */ // Label 520: @11532
4658 /* 11532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 521*/ GIMT_Encode4(11565), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 8 //
4659 /* 11539 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4660 /* 11546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4661 /* 11550 */ // MIs[0] ptr
4662 /* 11550 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4663 /* 11554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4664 /* 11558 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4665 /* 11558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4666 /* 11563 */ GIR_RootConstrainSelectedInstOperands,
4667 /* 11564 */ // GIR_Coverage, 8,
4668 /* 11564 */ GIR_Done,
4669 /* 11565 */ // Label 521: @11565
4670 /* 11565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 522*/ GIMT_Encode4(11598), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 9 //
4671 /* 11572 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4672 /* 11579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4673 /* 11583 */ // MIs[0] ptr
4674 /* 11583 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4675 /* 11587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4676 /* 11591 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4677 /* 11591 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4678 /* 11596 */ GIR_RootConstrainSelectedInstOperands,
4679 /* 11597 */ // GIR_Coverage, 9,
4680 /* 11597 */ GIR_Done,
4681 /* 11598 */ // Label 522: @11598
4682 /* 11598 */ GIM_Reject,
4683 /* 11599 */ // Label 519: @11599
4684 /* 11599 */ GIM_Reject,
4685 /* 11600 */ // Label 517: @11600
4686 /* 11600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 523*/ GIMT_Encode4(11636), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 240 //
4687 /* 11607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4688 /* 11610 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4689 /* 11617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4690 /* 11621 */ // MIs[0] ptr
4691 /* 11621 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4692 /* 11625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4693 /* 11629 */ // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4694 /* 11629 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4695 /* 11634 */ GIR_RootConstrainSelectedInstOperands,
4696 /* 11635 */ // GIR_Coverage, 240,
4697 /* 11635 */ GIR_Done,
4698 /* 11636 */ // Label 523: @11636
4699 /* 11636 */ GIM_Reject,
4700 /* 11637 */ // Label 518: @11637
4701 /* 11637 */ GIM_Reject,
4702 /* 11638 */ // Label 20: @11638
4703 /* 11638 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 526*/ GIMT_Encode4(11803),
4704 /* 11649 */ /*GILLT_s32*//*Label 524*/ GIMT_Encode4(11657),
4705 /* 11653 */ /*GILLT_s64*//*Label 525*/ GIMT_Encode4(11766),
4706 /* 11657 */ // Label 524: @11657
4707 /* 11657 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(11765),
4708 /* 11662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4709 /* 11665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 528*/ GIMT_Encode4(11698), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 10 //
4710 /* 11672 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4711 /* 11679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4712 /* 11683 */ // MIs[0] ptr
4713 /* 11683 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4714 /* 11687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4715 /* 11691 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4716 /* 11691 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4717 /* 11696 */ GIR_RootConstrainSelectedInstOperands,
4718 /* 11697 */ // GIR_Coverage, 10,
4719 /* 11697 */ GIR_Done,
4720 /* 11698 */ // Label 528: @11698
4721 /* 11698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 529*/ GIMT_Encode4(11731), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 11 //
4722 /* 11705 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4723 /* 11712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4724 /* 11716 */ // MIs[0] ptr
4725 /* 11716 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4726 /* 11720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4727 /* 11724 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4728 /* 11724 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4729 /* 11729 */ GIR_RootConstrainSelectedInstOperands,
4730 /* 11730 */ // GIR_Coverage, 11,
4731 /* 11730 */ GIR_Done,
4732 /* 11731 */ // Label 529: @11731
4733 /* 11731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(11764), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 12 //
4734 /* 11738 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4735 /* 11745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4736 /* 11749 */ // MIs[0] ptr
4737 /* 11749 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4738 /* 11753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4739 /* 11757 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4740 /* 11757 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4741 /* 11762 */ GIR_RootConstrainSelectedInstOperands,
4742 /* 11763 */ // GIR_Coverage, 12,
4743 /* 11763 */ GIR_Done,
4744 /* 11764 */ // Label 530: @11764
4745 /* 11764 */ GIM_Reject,
4746 /* 11765 */ // Label 527: @11765
4747 /* 11765 */ GIM_Reject,
4748 /* 11766 */ // Label 525: @11766
4749 /* 11766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(11802), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 241 //
4750 /* 11773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4751 /* 11776 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4752 /* 11783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4753 /* 11787 */ // MIs[0] ptr
4754 /* 11787 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4755 /* 11791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4756 /* 11795 */ // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4757 /* 11795 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4758 /* 11800 */ GIR_RootConstrainSelectedInstOperands,
4759 /* 11801 */ // GIR_Coverage, 241,
4760 /* 11801 */ GIR_Done,
4761 /* 11802 */ // Label 531: @11802
4762 /* 11802 */ GIM_Reject,
4763 /* 11803 */ // Label 526: @11803
4764 /* 11803 */ GIM_Reject,
4765 /* 11804 */ // Label 21: @11804
4766 /* 11804 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 534*/ GIMT_Encode4(11969),
4767 /* 11815 */ /*GILLT_s32*//*Label 532*/ GIMT_Encode4(11823),
4768 /* 11819 */ /*GILLT_s64*//*Label 533*/ GIMT_Encode4(11932),
4769 /* 11823 */ // Label 532: @11823
4770 /* 11823 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(11931),
4771 /* 11828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4772 /* 11831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 536*/ GIMT_Encode4(11864), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 19 //
4773 /* 11838 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4774 /* 11845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4775 /* 11849 */ // MIs[0] ptr
4776 /* 11849 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4777 /* 11853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4778 /* 11857 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4779 /* 11857 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4780 /* 11862 */ GIR_RootConstrainSelectedInstOperands,
4781 /* 11863 */ // GIR_Coverage, 19,
4782 /* 11863 */ GIR_Done,
4783 /* 11864 */ // Label 536: @11864
4784 /* 11864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 537*/ GIMT_Encode4(11897), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 20 //
4785 /* 11871 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4786 /* 11878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4787 /* 11882 */ // MIs[0] ptr
4788 /* 11882 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4789 /* 11886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4790 /* 11890 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4791 /* 11890 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4792 /* 11895 */ GIR_RootConstrainSelectedInstOperands,
4793 /* 11896 */ // GIR_Coverage, 20,
4794 /* 11896 */ GIR_Done,
4795 /* 11897 */ // Label 537: @11897
4796 /* 11897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(11930), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 21 //
4797 /* 11904 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4798 /* 11911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4799 /* 11915 */ // MIs[0] ptr
4800 /* 11915 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4801 /* 11919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4802 /* 11923 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4803 /* 11923 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4804 /* 11928 */ GIR_RootConstrainSelectedInstOperands,
4805 /* 11929 */ // GIR_Coverage, 21,
4806 /* 11929 */ GIR_Done,
4807 /* 11930 */ // Label 538: @11930
4808 /* 11930 */ GIM_Reject,
4809 /* 11931 */ // Label 535: @11931
4810 /* 11931 */ GIM_Reject,
4811 /* 11932 */ // Label 533: @11932
4812 /* 11932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(11968), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 244 //
4813 /* 11939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4814 /* 11942 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4815 /* 11949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4816 /* 11953 */ // MIs[0] ptr
4817 /* 11953 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4818 /* 11957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4819 /* 11961 */ // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4820 /* 11961 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4821 /* 11966 */ GIR_RootConstrainSelectedInstOperands,
4822 /* 11967 */ // GIR_Coverage, 244,
4823 /* 11967 */ GIR_Done,
4824 /* 11968 */ // Label 539: @11968
4825 /* 11968 */ GIM_Reject,
4826 /* 11969 */ // Label 534: @11969
4827 /* 11969 */ GIM_Reject,
4828 /* 11970 */ // Label 22: @11970
4829 /* 11970 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 542*/ GIMT_Encode4(12135),
4830 /* 11981 */ /*GILLT_s32*//*Label 540*/ GIMT_Encode4(11989),
4831 /* 11985 */ /*GILLT_s64*//*Label 541*/ GIMT_Encode4(12098),
4832 /* 11989 */ // Label 540: @11989
4833 /* 11989 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(12097),
4834 /* 11994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4835 /* 11997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 544*/ GIMT_Encode4(12030), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 13 //
4836 /* 12004 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4837 /* 12011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4838 /* 12015 */ // MIs[0] ptr
4839 /* 12015 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4840 /* 12019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4841 /* 12023 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4842 /* 12023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
4843 /* 12028 */ GIR_RootConstrainSelectedInstOperands,
4844 /* 12029 */ // GIR_Coverage, 13,
4845 /* 12029 */ GIR_Done,
4846 /* 12030 */ // Label 544: @12030
4847 /* 12030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 545*/ GIMT_Encode4(12063), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 14 //
4848 /* 12037 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4849 /* 12044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4850 /* 12048 */ // MIs[0] ptr
4851 /* 12048 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4852 /* 12052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4853 /* 12056 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4854 /* 12056 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
4855 /* 12061 */ GIR_RootConstrainSelectedInstOperands,
4856 /* 12062 */ // GIR_Coverage, 14,
4857 /* 12062 */ GIR_Done,
4858 /* 12063 */ // Label 545: @12063
4859 /* 12063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(12096), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 15 //
4860 /* 12070 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4861 /* 12077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4862 /* 12081 */ // MIs[0] ptr
4863 /* 12081 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4864 /* 12085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4865 /* 12089 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4866 /* 12089 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
4867 /* 12094 */ GIR_RootConstrainSelectedInstOperands,
4868 /* 12095 */ // GIR_Coverage, 15,
4869 /* 12095 */ GIR_Done,
4870 /* 12096 */ // Label 546: @12096
4871 /* 12096 */ GIM_Reject,
4872 /* 12097 */ // Label 543: @12097
4873 /* 12097 */ GIM_Reject,
4874 /* 12098 */ // Label 541: @12098
4875 /* 12098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(12134), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 242 //
4876 /* 12105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4877 /* 12108 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4878 /* 12115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4879 /* 12119 */ // MIs[0] ptr
4880 /* 12119 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4881 /* 12123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4882 /* 12127 */ // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4883 /* 12127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
4884 /* 12132 */ GIR_RootConstrainSelectedInstOperands,
4885 /* 12133 */ // GIR_Coverage, 242,
4886 /* 12133 */ GIR_Done,
4887 /* 12134 */ // Label 547: @12134
4888 /* 12134 */ GIM_Reject,
4889 /* 12135 */ // Label 542: @12135
4890 /* 12135 */ GIM_Reject,
4891 /* 12136 */ // Label 23: @12136
4892 /* 12136 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 550*/ GIMT_Encode4(12301),
4893 /* 12147 */ /*GILLT_s32*//*Label 548*/ GIMT_Encode4(12155),
4894 /* 12151 */ /*GILLT_s64*//*Label 549*/ GIMT_Encode4(12264),
4895 /* 12155 */ // Label 548: @12155
4896 /* 12155 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(12263),
4897 /* 12160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4898 /* 12163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 552*/ GIMT_Encode4(12196), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 16 //
4899 /* 12170 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4900 /* 12177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4901 /* 12181 */ // MIs[0] ptr
4902 /* 12181 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4903 /* 12185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4904 /* 12189 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4905 /* 12189 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
4906 /* 12194 */ GIR_RootConstrainSelectedInstOperands,
4907 /* 12195 */ // GIR_Coverage, 16,
4908 /* 12195 */ GIR_Done,
4909 /* 12196 */ // Label 552: @12196
4910 /* 12196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 553*/ GIMT_Encode4(12229), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 17 //
4911 /* 12203 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4912 /* 12210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4913 /* 12214 */ // MIs[0] ptr
4914 /* 12214 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4915 /* 12218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4916 /* 12222 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4917 /* 12222 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
4918 /* 12227 */ GIR_RootConstrainSelectedInstOperands,
4919 /* 12228 */ // GIR_Coverage, 17,
4920 /* 12228 */ GIR_Done,
4921 /* 12229 */ // Label 553: @12229
4922 /* 12229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(12262), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 18 //
4923 /* 12236 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4924 /* 12243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4925 /* 12247 */ // MIs[0] ptr
4926 /* 12247 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4927 /* 12251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4928 /* 12255 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4929 /* 12255 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
4930 /* 12260 */ GIR_RootConstrainSelectedInstOperands,
4931 /* 12261 */ // GIR_Coverage, 18,
4932 /* 12261 */ GIR_Done,
4933 /* 12262 */ // Label 554: @12262
4934 /* 12262 */ GIM_Reject,
4935 /* 12263 */ // Label 551: @12263
4936 /* 12263 */ GIM_Reject,
4937 /* 12264 */ // Label 549: @12264
4938 /* 12264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 555*/ GIMT_Encode4(12300), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 243 //
4939 /* 12271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4940 /* 12274 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4941 /* 12281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4942 /* 12285 */ // MIs[0] ptr
4943 /* 12285 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4944 /* 12289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4945 /* 12293 */ // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4946 /* 12293 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
4947 /* 12298 */ GIR_RootConstrainSelectedInstOperands,
4948 /* 12299 */ // GIR_Coverage, 243,
4949 /* 12299 */ GIR_Done,
4950 /* 12300 */ // Label 555: @12300
4951 /* 12300 */ GIM_Reject,
4952 /* 12301 */ // Label 550: @12301
4953 /* 12301 */ GIM_Reject,
4954 /* 12302 */ // Label 24: @12302
4955 /* 12302 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 558*/ GIMT_Encode4(12467),
4956 /* 12313 */ /*GILLT_s32*//*Label 556*/ GIMT_Encode4(12321),
4957 /* 12317 */ /*GILLT_s64*//*Label 557*/ GIMT_Encode4(12430),
4958 /* 12321 */ // Label 556: @12321
4959 /* 12321 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(12429),
4960 /* 12326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4961 /* 12329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 560*/ GIMT_Encode4(12362), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 31 //
4962 /* 12336 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4963 /* 12343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4964 /* 12347 */ // MIs[0] ptr
4965 /* 12347 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4966 /* 12351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4967 /* 12355 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4968 /* 12355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
4969 /* 12360 */ GIR_RootConstrainSelectedInstOperands,
4970 /* 12361 */ // GIR_Coverage, 31,
4971 /* 12361 */ GIR_Done,
4972 /* 12362 */ // Label 560: @12362
4973 /* 12362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 561*/ GIMT_Encode4(12395), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 32 //
4974 /* 12369 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4975 /* 12376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4976 /* 12380 */ // MIs[0] ptr
4977 /* 12380 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4978 /* 12384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4979 /* 12388 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4980 /* 12388 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
4981 /* 12393 */ GIR_RootConstrainSelectedInstOperands,
4982 /* 12394 */ // GIR_Coverage, 32,
4983 /* 12394 */ GIR_Done,
4984 /* 12395 */ // Label 561: @12395
4985 /* 12395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(12428), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 33 //
4986 /* 12402 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4987 /* 12409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4988 /* 12413 */ // MIs[0] ptr
4989 /* 12413 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4990 /* 12417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4991 /* 12421 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4992 /* 12421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
4993 /* 12426 */ GIR_RootConstrainSelectedInstOperands,
4994 /* 12427 */ // GIR_Coverage, 33,
4995 /* 12427 */ GIR_Done,
4996 /* 12428 */ // Label 562: @12428
4997 /* 12428 */ GIM_Reject,
4998 /* 12429 */ // Label 559: @12429
4999 /* 12429 */ GIM_Reject,
5000 /* 12430 */ // Label 557: @12430
5001 /* 12430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(12466), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 248 //
5002 /* 12437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5003 /* 12440 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5004 /* 12447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5005 /* 12451 */ // MIs[0] ptr
5006 /* 12451 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5007 /* 12455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5008 /* 12459 */ // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5009 /* 12459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
5010 /* 12464 */ GIR_RootConstrainSelectedInstOperands,
5011 /* 12465 */ // GIR_Coverage, 248,
5012 /* 12465 */ GIR_Done,
5013 /* 12466 */ // Label 563: @12466
5014 /* 12466 */ GIM_Reject,
5015 /* 12467 */ // Label 558: @12467
5016 /* 12467 */ GIM_Reject,
5017 /* 12468 */ // Label 25: @12468
5018 /* 12468 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 566*/ GIMT_Encode4(12633),
5019 /* 12479 */ /*GILLT_s32*//*Label 564*/ GIMT_Encode4(12487),
5020 /* 12483 */ /*GILLT_s64*//*Label 565*/ GIMT_Encode4(12596),
5021 /* 12487 */ // Label 564: @12487
5022 /* 12487 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(12595),
5023 /* 12492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5024 /* 12495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 568*/ GIMT_Encode4(12528), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 28 //
5025 /* 12502 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5026 /* 12509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5027 /* 12513 */ // MIs[0] ptr
5028 /* 12513 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5029 /* 12517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5030 /* 12521 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5031 /* 12521 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
5032 /* 12526 */ GIR_RootConstrainSelectedInstOperands,
5033 /* 12527 */ // GIR_Coverage, 28,
5034 /* 12527 */ GIR_Done,
5035 /* 12528 */ // Label 568: @12528
5036 /* 12528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 569*/ GIMT_Encode4(12561), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 29 //
5037 /* 12535 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5038 /* 12542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5039 /* 12546 */ // MIs[0] ptr
5040 /* 12546 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5041 /* 12550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5042 /* 12554 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5043 /* 12554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
5044 /* 12559 */ GIR_RootConstrainSelectedInstOperands,
5045 /* 12560 */ // GIR_Coverage, 29,
5046 /* 12560 */ GIR_Done,
5047 /* 12561 */ // Label 569: @12561
5048 /* 12561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(12594), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 30 //
5049 /* 12568 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5050 /* 12575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5051 /* 12579 */ // MIs[0] ptr
5052 /* 12579 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5053 /* 12583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5054 /* 12587 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5055 /* 12587 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
5056 /* 12592 */ GIR_RootConstrainSelectedInstOperands,
5057 /* 12593 */ // GIR_Coverage, 30,
5058 /* 12593 */ GIR_Done,
5059 /* 12594 */ // Label 570: @12594
5060 /* 12594 */ GIM_Reject,
5061 /* 12595 */ // Label 567: @12595
5062 /* 12595 */ GIM_Reject,
5063 /* 12596 */ // Label 565: @12596
5064 /* 12596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(12632), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 247 //
5065 /* 12603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5066 /* 12606 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5067 /* 12613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5068 /* 12617 */ // MIs[0] ptr
5069 /* 12617 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5070 /* 12621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5071 /* 12625 */ // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5072 /* 12625 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
5073 /* 12630 */ GIR_RootConstrainSelectedInstOperands,
5074 /* 12631 */ // GIR_Coverage, 247,
5075 /* 12631 */ GIR_Done,
5076 /* 12632 */ // Label 571: @12632
5077 /* 12632 */ GIM_Reject,
5078 /* 12633 */ // Label 566: @12633
5079 /* 12633 */ GIM_Reject,
5080 /* 12634 */ // Label 26: @12634
5081 /* 12634 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 574*/ GIMT_Encode4(12799),
5082 /* 12645 */ /*GILLT_s32*//*Label 572*/ GIMT_Encode4(12653),
5083 /* 12649 */ /*GILLT_s64*//*Label 573*/ GIMT_Encode4(12762),
5084 /* 12653 */ // Label 572: @12653
5085 /* 12653 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(12761),
5086 /* 12658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5087 /* 12661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 576*/ GIMT_Encode4(12694), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 37 //
5088 /* 12668 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5089 /* 12675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5090 /* 12679 */ // MIs[0] ptr
5091 /* 12679 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5092 /* 12683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5093 /* 12687 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5094 /* 12687 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
5095 /* 12692 */ GIR_RootConstrainSelectedInstOperands,
5096 /* 12693 */ // GIR_Coverage, 37,
5097 /* 12693 */ GIR_Done,
5098 /* 12694 */ // Label 576: @12694
5099 /* 12694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 577*/ GIMT_Encode4(12727), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 38 //
5100 /* 12701 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5101 /* 12708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5102 /* 12712 */ // MIs[0] ptr
5103 /* 12712 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5104 /* 12716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5105 /* 12720 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5106 /* 12720 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5107 /* 12725 */ GIR_RootConstrainSelectedInstOperands,
5108 /* 12726 */ // GIR_Coverage, 38,
5109 /* 12726 */ GIR_Done,
5110 /* 12727 */ // Label 577: @12727
5111 /* 12727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 578*/ GIMT_Encode4(12760), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 39 //
5112 /* 12734 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5113 /* 12741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5114 /* 12745 */ // MIs[0] ptr
5115 /* 12745 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5116 /* 12749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5117 /* 12753 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5118 /* 12753 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5119 /* 12758 */ GIR_RootConstrainSelectedInstOperands,
5120 /* 12759 */ // GIR_Coverage, 39,
5121 /* 12759 */ GIR_Done,
5122 /* 12760 */ // Label 578: @12760
5123 /* 12760 */ GIM_Reject,
5124 /* 12761 */ // Label 575: @12761
5125 /* 12761 */ GIM_Reject,
5126 /* 12762 */ // Label 573: @12762
5127 /* 12762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 579*/ GIMT_Encode4(12798), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 250 //
5128 /* 12769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5129 /* 12772 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5130 /* 12779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5131 /* 12783 */ // MIs[0] ptr
5132 /* 12783 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5133 /* 12787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5134 /* 12791 */ // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5135 /* 12791 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5136 /* 12796 */ GIR_RootConstrainSelectedInstOperands,
5137 /* 12797 */ // GIR_Coverage, 250,
5138 /* 12797 */ GIR_Done,
5139 /* 12798 */ // Label 579: @12798
5140 /* 12798 */ GIM_Reject,
5141 /* 12799 */ // Label 574: @12799
5142 /* 12799 */ GIM_Reject,
5143 /* 12800 */ // Label 27: @12800
5144 /* 12800 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 582*/ GIMT_Encode4(12965),
5145 /* 12811 */ /*GILLT_s32*//*Label 580*/ GIMT_Encode4(12819),
5146 /* 12815 */ /*GILLT_s64*//*Label 581*/ GIMT_Encode4(12928),
5147 /* 12819 */ // Label 580: @12819
5148 /* 12819 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(12927),
5149 /* 12824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5150 /* 12827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 584*/ GIMT_Encode4(12860), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 34 //
5151 /* 12834 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5152 /* 12841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5153 /* 12845 */ // MIs[0] ptr
5154 /* 12845 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5155 /* 12849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5156 /* 12853 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5157 /* 12853 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5158 /* 12858 */ GIR_RootConstrainSelectedInstOperands,
5159 /* 12859 */ // GIR_Coverage, 34,
5160 /* 12859 */ GIR_Done,
5161 /* 12860 */ // Label 584: @12860
5162 /* 12860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 585*/ GIMT_Encode4(12893), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 35 //
5163 /* 12867 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5164 /* 12874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5165 /* 12878 */ // MIs[0] ptr
5166 /* 12878 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5167 /* 12882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5168 /* 12886 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5169 /* 12886 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5170 /* 12891 */ GIR_RootConstrainSelectedInstOperands,
5171 /* 12892 */ // GIR_Coverage, 35,
5172 /* 12892 */ GIR_Done,
5173 /* 12893 */ // Label 585: @12893
5174 /* 12893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 586*/ GIMT_Encode4(12926), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 36 //
5175 /* 12900 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5176 /* 12907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5177 /* 12911 */ // MIs[0] ptr
5178 /* 12911 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5179 /* 12915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5180 /* 12919 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5181 /* 12919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5182 /* 12924 */ GIR_RootConstrainSelectedInstOperands,
5183 /* 12925 */ // GIR_Coverage, 36,
5184 /* 12925 */ GIR_Done,
5185 /* 12926 */ // Label 586: @12926
5186 /* 12926 */ GIM_Reject,
5187 /* 12927 */ // Label 583: @12927
5188 /* 12927 */ GIM_Reject,
5189 /* 12928 */ // Label 581: @12928
5190 /* 12928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 587*/ GIMT_Encode4(12964), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 249 //
5191 /* 12935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5192 /* 12938 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5193 /* 12945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5194 /* 12949 */ // MIs[0] ptr
5195 /* 12949 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5196 /* 12953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5197 /* 12957 */ // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5198 /* 12957 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5199 /* 12962 */ GIR_RootConstrainSelectedInstOperands,
5200 /* 12963 */ // GIR_Coverage, 249,
5201 /* 12963 */ GIR_Done,
5202 /* 12964 */ // Label 587: @12964
5203 /* 12964 */ GIM_Reject,
5204 /* 12965 */ // Label 582: @12965
5205 /* 12965 */ GIM_Reject,
5206 /* 12966 */ // Label 28: @12966
5207 /* 12966 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 590*/ GIMT_Encode4(19129),
5208 /* 12977 */ /*GILLT_s32*//*Label 588*/ GIMT_Encode4(12985),
5209 /* 12981 */ /*GILLT_s64*//*Label 589*/ GIMT_Encode4(19096),
5210 /* 12985 */ // Label 588: @12985
5211 /* 12985 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(18984),
5212 /* 12990 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5213 /* 12993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 592*/ GIMT_Encode4(13097), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2672 //
5214 /* 13000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5215 /* 13004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5216 /* 13008 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5217 /* 13012 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5218 /* 13016 */ // MIs[1] Operand 1
5219 /* 13016 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5220 /* 13021 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5221 /* 13025 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5222 /* 13029 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5223 /* 13033 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5224 /* 13037 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5225 /* 13041 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5226 /* 13045 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5227 /* 13049 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5228 /* 13053 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5229 /* 13057 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5230 /* 13061 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5231 /* 13065 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5232 /* 13069 */ // MIs[4] Operand 1
5233 /* 13069 */ // No operand predicates
5234 /* 13069 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5235 /* 13074 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5236 /* 13078 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5237 /* 13080 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5238 /* 13080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5239 /* 13083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5240 /* 13087 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5241 /* 13090 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5242 /* 13092 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5243 /* 13095 */ GIR_RootConstrainSelectedInstOperands,
5244 /* 13096 */ // GIR_Coverage, 2672,
5245 /* 13096 */ GIR_EraseRootFromParent_Done,
5246 /* 13097 */ // Label 592: @13097
5247 /* 13097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 593*/ GIMT_Encode4(13208), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2673 //
5248 /* 13104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5249 /* 13108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5250 /* 13112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5251 /* 13116 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5252 /* 13120 */ // MIs[1] Operand 1
5253 /* 13120 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5254 /* 13125 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5255 /* 13129 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5256 /* 13133 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5257 /* 13137 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5258 /* 13141 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5259 /* 13145 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5260 /* 13149 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5261 /* 13153 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5262 /* 13157 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5263 /* 13168 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5264 /* 13172 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5265 /* 13176 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5266 /* 13180 */ // MIs[4] Operand 1
5267 /* 13180 */ // No operand predicates
5268 /* 13180 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5269 /* 13185 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5270 /* 13189 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5271 /* 13191 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5272 /* 13191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5273 /* 13194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5274 /* 13198 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5275 /* 13201 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5276 /* 13203 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5277 /* 13206 */ GIR_RootConstrainSelectedInstOperands,
5278 /* 13207 */ // GIR_Coverage, 2673,
5279 /* 13207 */ GIR_EraseRootFromParent_Done,
5280 /* 13208 */ // Label 593: @13208
5281 /* 13208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 594*/ GIMT_Encode4(13312), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2674 //
5282 /* 13215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5283 /* 13219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5284 /* 13223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5285 /* 13227 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5286 /* 13231 */ // MIs[1] Operand 1
5287 /* 13231 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5288 /* 13236 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5289 /* 13240 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5290 /* 13244 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5291 /* 13248 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5292 /* 13252 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5293 /* 13256 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5294 /* 13260 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5295 /* 13264 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5296 /* 13268 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5297 /* 13272 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5298 /* 13276 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5299 /* 13280 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5300 /* 13284 */ // MIs[4] Operand 1
5301 /* 13284 */ // No operand predicates
5302 /* 13284 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5303 /* 13289 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5304 /* 13293 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5305 /* 13295 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5306 /* 13295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5307 /* 13298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5308 /* 13302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5309 /* 13305 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5310 /* 13307 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5311 /* 13310 */ GIR_RootConstrainSelectedInstOperands,
5312 /* 13311 */ // GIR_Coverage, 2674,
5313 /* 13311 */ GIR_EraseRootFromParent_Done,
5314 /* 13312 */ // Label 594: @13312
5315 /* 13312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 595*/ GIMT_Encode4(13423), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2675 //
5316 /* 13319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5317 /* 13323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5318 /* 13327 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5319 /* 13331 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5320 /* 13335 */ // MIs[1] Operand 1
5321 /* 13335 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5322 /* 13340 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5323 /* 13344 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5324 /* 13348 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5325 /* 13352 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5326 /* 13356 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5327 /* 13360 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5328 /* 13364 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5329 /* 13368 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5330 /* 13372 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5331 /* 13383 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5332 /* 13387 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5333 /* 13391 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5334 /* 13395 */ // MIs[4] Operand 1
5335 /* 13395 */ // No operand predicates
5336 /* 13395 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5337 /* 13400 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5338 /* 13404 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5339 /* 13406 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5340 /* 13406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5341 /* 13409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5342 /* 13413 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5343 /* 13416 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5344 /* 13418 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5345 /* 13421 */ GIR_RootConstrainSelectedInstOperands,
5346 /* 13422 */ // GIR_Coverage, 2675,
5347 /* 13422 */ GIR_EraseRootFromParent_Done,
5348 /* 13423 */ // Label 595: @13423
5349 /* 13423 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 596*/ GIMT_Encode4(13527), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 345 //
5350 /* 13430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5351 /* 13434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5352 /* 13438 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5353 /* 13442 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5354 /* 13446 */ // MIs[1] Operand 1
5355 /* 13446 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5356 /* 13451 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5357 /* 13455 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5358 /* 13459 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5359 /* 13463 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5360 /* 13467 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5361 /* 13472 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5362 /* 13476 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5363 /* 13480 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5364 /* 13484 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5365 /* 13488 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5366 /* 13492 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5367 /* 13496 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5368 /* 13500 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5369 /* 13504 */ // MIs[4] Operand 1
5370 /* 13504 */ // No operand predicates
5371 /* 13504 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5372 /* 13508 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5373 /* 13510 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5374 /* 13510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5375 /* 13513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5376 /* 13517 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5377 /* 13520 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5378 /* 13522 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5379 /* 13525 */ GIR_RootConstrainSelectedInstOperands,
5380 /* 13526 */ // GIR_Coverage, 345,
5381 /* 13526 */ GIR_EraseRootFromParent_Done,
5382 /* 13527 */ // Label 596: @13527
5383 /* 13527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 597*/ GIMT_Encode4(13638), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 346 //
5384 /* 13534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5385 /* 13538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5386 /* 13542 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5387 /* 13546 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5388 /* 13550 */ // MIs[1] Operand 1
5389 /* 13550 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5390 /* 13555 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5391 /* 13559 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5392 /* 13563 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5393 /* 13567 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5394 /* 13571 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5395 /* 13576 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5396 /* 13580 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5397 /* 13584 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5398 /* 13588 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5399 /* 13592 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5400 /* 13603 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5401 /* 13607 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5402 /* 13611 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5403 /* 13615 */ // MIs[4] Operand 1
5404 /* 13615 */ // No operand predicates
5405 /* 13615 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5406 /* 13619 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5407 /* 13621 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5408 /* 13621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5409 /* 13624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5410 /* 13628 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5411 /* 13631 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5412 /* 13633 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5413 /* 13636 */ GIR_RootConstrainSelectedInstOperands,
5414 /* 13637 */ // GIR_Coverage, 346,
5415 /* 13637 */ GIR_EraseRootFromParent_Done,
5416 /* 13638 */ // Label 597: @13638
5417 /* 13638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 598*/ GIMT_Encode4(13742), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 347 //
5418 /* 13645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5419 /* 13649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5420 /* 13653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5421 /* 13657 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5422 /* 13661 */ // MIs[1] Operand 1
5423 /* 13661 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5424 /* 13666 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5425 /* 13670 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5426 /* 13674 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5427 /* 13678 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5428 /* 13682 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5429 /* 13687 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5430 /* 13691 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5431 /* 13695 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5432 /* 13699 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5433 /* 13703 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5434 /* 13707 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5435 /* 13711 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5436 /* 13715 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5437 /* 13719 */ // MIs[4] Operand 1
5438 /* 13719 */ // No operand predicates
5439 /* 13719 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5440 /* 13723 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5441 /* 13725 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5442 /* 13725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5443 /* 13728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5444 /* 13732 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5445 /* 13735 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5446 /* 13737 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5447 /* 13740 */ GIR_RootConstrainSelectedInstOperands,
5448 /* 13741 */ // GIR_Coverage, 347,
5449 /* 13741 */ GIR_EraseRootFromParent_Done,
5450 /* 13742 */ // Label 598: @13742
5451 /* 13742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 599*/ GIMT_Encode4(13853), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 348 //
5452 /* 13749 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5453 /* 13753 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5454 /* 13757 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5455 /* 13761 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5456 /* 13765 */ // MIs[1] Operand 1
5457 /* 13765 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5458 /* 13770 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5459 /* 13774 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5460 /* 13778 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5461 /* 13782 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5462 /* 13786 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5463 /* 13791 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5464 /* 13795 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5465 /* 13799 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5466 /* 13803 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5467 /* 13807 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5468 /* 13818 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5469 /* 13822 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5470 /* 13826 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5471 /* 13830 */ // MIs[4] Operand 1
5472 /* 13830 */ // No operand predicates
5473 /* 13830 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5474 /* 13834 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5475 /* 13836 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5476 /* 13836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5477 /* 13839 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5478 /* 13843 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5479 /* 13846 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5480 /* 13848 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5481 /* 13851 */ GIR_RootConstrainSelectedInstOperands,
5482 /* 13852 */ // GIR_Coverage, 348,
5483 /* 13852 */ GIR_EraseRootFromParent_Done,
5484 /* 13853 */ // Label 599: @13853
5485 /* 13853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 600*/ GIMT_Encode4(13906), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 114 //
5486 /* 13860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5487 /* 13864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5488 /* 13868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5489 /* 13872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5490 /* 13876 */ // MIs[1] Operand 1
5491 /* 13876 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5492 /* 13881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5493 /* 13886 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5494 /* 13890 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5495 /* 13892 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5496 /* 13892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5497 /* 13895 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5498 /* 13899 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5499 /* 13901 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5500 /* 13904 */ GIR_RootConstrainSelectedInstOperands,
5501 /* 13905 */ // GIR_Coverage, 114,
5502 /* 13905 */ GIR_EraseRootFromParent_Done,
5503 /* 13906 */ // Label 600: @13906
5504 /* 13906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 601*/ GIMT_Encode4(13959), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 115 //
5505 /* 13913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5506 /* 13917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5507 /* 13921 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5508 /* 13925 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5509 /* 13929 */ // MIs[1] Operand 1
5510 /* 13929 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5511 /* 13934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5512 /* 13939 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5513 /* 13943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5514 /* 13945 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5515 /* 13945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
5516 /* 13948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5517 /* 13952 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5518 /* 13954 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5519 /* 13957 */ GIR_RootConstrainSelectedInstOperands,
5520 /* 13958 */ // GIR_Coverage, 115,
5521 /* 13958 */ GIR_EraseRootFromParent_Done,
5522 /* 13959 */ // Label 601: @13959
5523 /* 13959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 602*/ GIMT_Encode4(14012), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 116 //
5524 /* 13966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5525 /* 13970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5526 /* 13974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5527 /* 13978 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5528 /* 13982 */ // MIs[1] Operand 1
5529 /* 13982 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5530 /* 13987 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5531 /* 13992 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5532 /* 13996 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5533 /* 13998 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5534 /* 13998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5535 /* 14001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5536 /* 14005 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5537 /* 14007 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5538 /* 14010 */ GIR_RootConstrainSelectedInstOperands,
5539 /* 14011 */ // GIR_Coverage, 116,
5540 /* 14011 */ GIR_EraseRootFromParent_Done,
5541 /* 14012 */ // Label 602: @14012
5542 /* 14012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 603*/ GIMT_Encode4(14065), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 117 //
5543 /* 14019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5544 /* 14023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5545 /* 14027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5546 /* 14031 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5547 /* 14035 */ // MIs[1] Operand 1
5548 /* 14035 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5549 /* 14040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5550 /* 14045 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5551 /* 14049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5552 /* 14051 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5553 /* 14051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
5554 /* 14054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5555 /* 14058 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5556 /* 14060 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5557 /* 14063 */ GIR_RootConstrainSelectedInstOperands,
5558 /* 14064 */ // GIR_Coverage, 117,
5559 /* 14064 */ GIR_EraseRootFromParent_Done,
5560 /* 14065 */ // Label 603: @14065
5561 /* 14065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 604*/ GIMT_Encode4(14118), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 319 //
5562 /* 14072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5563 /* 14076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5564 /* 14080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5565 /* 14084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5566 /* 14088 */ // MIs[1] Operand 1
5567 /* 14088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5568 /* 14093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5569 /* 14098 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5570 /* 14102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5571 /* 14104 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5572 /* 14104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5573 /* 14107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5574 /* 14111 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5575 /* 14113 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5576 /* 14116 */ GIR_RootConstrainSelectedInstOperands,
5577 /* 14117 */ // GIR_Coverage, 319,
5578 /* 14117 */ GIR_EraseRootFromParent_Done,
5579 /* 14118 */ // Label 604: @14118
5580 /* 14118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 605*/ GIMT_Encode4(14171), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 320 //
5581 /* 14125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5582 /* 14129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5583 /* 14133 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5584 /* 14137 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5585 /* 14141 */ // MIs[1] Operand 1
5586 /* 14141 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5587 /* 14146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5588 /* 14151 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5589 /* 14155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5590 /* 14157 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5591 /* 14157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
5592 /* 14160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5593 /* 14164 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5594 /* 14166 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5595 /* 14169 */ GIR_RootConstrainSelectedInstOperands,
5596 /* 14170 */ // GIR_Coverage, 320,
5597 /* 14170 */ GIR_EraseRootFromParent_Done,
5598 /* 14171 */ // Label 605: @14171
5599 /* 14171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 606*/ GIMT_Encode4(14224), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 321 //
5600 /* 14178 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5601 /* 14182 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5602 /* 14186 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5603 /* 14190 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5604 /* 14194 */ // MIs[1] Operand 1
5605 /* 14194 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5606 /* 14199 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5607 /* 14204 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5608 /* 14208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5609 /* 14210 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5610 /* 14210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5611 /* 14213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5612 /* 14217 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5613 /* 14219 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5614 /* 14222 */ GIR_RootConstrainSelectedInstOperands,
5615 /* 14223 */ // GIR_Coverage, 321,
5616 /* 14223 */ GIR_EraseRootFromParent_Done,
5617 /* 14224 */ // Label 606: @14224
5618 /* 14224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 607*/ GIMT_Encode4(14277), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 322 //
5619 /* 14231 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5620 /* 14235 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5621 /* 14239 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5622 /* 14243 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5623 /* 14247 */ // MIs[1] Operand 1
5624 /* 14247 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5625 /* 14252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5626 /* 14257 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5627 /* 14261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5628 /* 14263 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5629 /* 14263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5630 /* 14266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5631 /* 14270 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5632 /* 14272 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5633 /* 14275 */ GIR_RootConstrainSelectedInstOperands,
5634 /* 14276 */ // GIR_Coverage, 322,
5635 /* 14276 */ GIR_EraseRootFromParent_Done,
5636 /* 14277 */ // Label 607: @14277
5637 /* 14277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 608*/ GIMT_Encode4(14330), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1189 //
5638 /* 14284 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5639 /* 14288 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5640 /* 14292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5641 /* 14296 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5642 /* 14300 */ // MIs[1] Operand 1
5643 /* 14300 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5644 /* 14305 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5645 /* 14310 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5646 /* 14314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5647 /* 14316 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5648 /* 14316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5649 /* 14319 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5650 /* 14323 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5651 /* 14325 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5652 /* 14328 */ GIR_RootConstrainSelectedInstOperands,
5653 /* 14329 */ // GIR_Coverage, 1189,
5654 /* 14329 */ GIR_EraseRootFromParent_Done,
5655 /* 14330 */ // Label 608: @14330
5656 /* 14330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(14383), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1190 //
5657 /* 14337 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5658 /* 14341 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5659 /* 14345 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5660 /* 14349 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5661 /* 14353 */ // MIs[1] Operand 1
5662 /* 14353 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5663 /* 14358 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5664 /* 14363 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5665 /* 14367 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5666 /* 14369 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5667 /* 14369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5668 /* 14372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5669 /* 14376 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5670 /* 14378 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5671 /* 14381 */ GIR_RootConstrainSelectedInstOperands,
5672 /* 14382 */ // GIR_Coverage, 1190,
5673 /* 14382 */ GIR_EraseRootFromParent_Done,
5674 /* 14383 */ // Label 609: @14383
5675 /* 14383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(14436), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1191 //
5676 /* 14390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5677 /* 14394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5678 /* 14398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5679 /* 14402 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5680 /* 14406 */ // MIs[1] Operand 1
5681 /* 14406 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5682 /* 14411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5683 /* 14416 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5684 /* 14420 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5685 /* 14422 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5686 /* 14422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5687 /* 14425 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5688 /* 14429 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5689 /* 14431 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5690 /* 14434 */ GIR_RootConstrainSelectedInstOperands,
5691 /* 14435 */ // GIR_Coverage, 1191,
5692 /* 14435 */ GIR_EraseRootFromParent_Done,
5693 /* 14436 */ // Label 610: @14436
5694 /* 14436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(14489), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1192 //
5695 /* 14443 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5696 /* 14447 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5697 /* 14451 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5698 /* 14455 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5699 /* 14459 */ // MIs[1] Operand 1
5700 /* 14459 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5701 /* 14464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5702 /* 14469 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5703 /* 14473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5704 /* 14475 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5705 /* 14475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5706 /* 14478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5707 /* 14482 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5708 /* 14484 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5709 /* 14487 */ GIR_RootConstrainSelectedInstOperands,
5710 /* 14488 */ // GIR_Coverage, 1192,
5711 /* 14488 */ GIR_EraseRootFromParent_Done,
5712 /* 14489 */ // Label 611: @14489
5713 /* 14489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(14548), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1487 //
5714 /* 14496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5715 /* 14500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5716 /* 14504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5717 /* 14508 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5718 /* 14512 */ // MIs[1] Operand 1
5719 /* 14512 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5720 /* 14517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5721 /* 14522 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5722 /* 14526 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5723 /* 14528 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5724 /* 14528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5725 /* 14531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5726 /* 14535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5727 /* 14541 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5728 /* 14543 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5729 /* 14546 */ GIR_RootConstrainSelectedInstOperands,
5730 /* 14547 */ // GIR_Coverage, 1487,
5731 /* 14547 */ GIR_EraseRootFromParent_Done,
5732 /* 14548 */ // Label 612: @14548
5733 /* 14548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(14607), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1488 //
5734 /* 14555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5735 /* 14559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5736 /* 14563 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5737 /* 14567 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5738 /* 14571 */ // MIs[1] Operand 1
5739 /* 14571 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5740 /* 14576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5741 /* 14581 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5742 /* 14585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5743 /* 14587 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5744 /* 14587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5745 /* 14590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5746 /* 14594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5747 /* 14600 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5748 /* 14602 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5749 /* 14605 */ GIR_RootConstrainSelectedInstOperands,
5750 /* 14606 */ // GIR_Coverage, 1488,
5751 /* 14606 */ GIR_EraseRootFromParent_Done,
5752 /* 14607 */ // Label 613: @14607
5753 /* 14607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(14666), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1740 //
5754 /* 14614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5755 /* 14618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5756 /* 14622 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5757 /* 14626 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5758 /* 14630 */ // MIs[1] Operand 1
5759 /* 14630 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5760 /* 14635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5761 /* 14640 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5762 /* 14644 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5763 /* 14646 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, R0_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5764 /* 14646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
5765 /* 14649 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5766 /* 14653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5767 /* 14659 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5768 /* 14661 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5769 /* 14664 */ GIR_RootConstrainSelectedInstOperands,
5770 /* 14665 */ // GIR_Coverage, 1740,
5771 /* 14665 */ GIR_EraseRootFromParent_Done,
5772 /* 14666 */ // Label 614: @14666
5773 /* 14666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(14725), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1741 //
5774 /* 14673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5775 /* 14677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5776 /* 14681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5777 /* 14685 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5778 /* 14689 */ // MIs[1] Operand 1
5779 /* 14689 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5780 /* 14694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5781 /* 14699 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5782 /* 14703 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5783 /* 14705 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, R0_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5784 /* 14705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
5785 /* 14708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5786 /* 14712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5787 /* 14718 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5788 /* 14720 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5789 /* 14723 */ GIR_RootConstrainSelectedInstOperands,
5790 /* 14724 */ // GIR_Coverage, 1741,
5791 /* 14724 */ GIR_EraseRootFromParent_Done,
5792 /* 14725 */ // Label 615: @14725
5793 /* 14725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(14775), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2103 //
5794 /* 14732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5795 /* 14736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5796 /* 14740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5797 /* 14744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5798 /* 14748 */ // MIs[1] Operand 1
5799 /* 14748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5800 /* 14753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5801 /* 14758 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5802 /* 14762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5803 /* 14764 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5804 /* 14764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
5805 /* 14767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5806 /* 14771 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5807 /* 14773 */ GIR_RootConstrainSelectedInstOperands,
5808 /* 14774 */ // GIR_Coverage, 2103,
5809 /* 14774 */ GIR_EraseRootFromParent_Done,
5810 /* 14775 */ // Label 616: @14775
5811 /* 14775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(14825), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2112 //
5812 /* 14782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5813 /* 14786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5814 /* 14790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5815 /* 14794 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5816 /* 14798 */ // MIs[1] Operand 1
5817 /* 14798 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5818 /* 14803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5819 /* 14808 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5820 /* 14812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5821 /* 14814 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5822 /* 14814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
5823 /* 14817 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5824 /* 14821 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5825 /* 14823 */ GIR_RootConstrainSelectedInstOperands,
5826 /* 14824 */ // GIR_Coverage, 2112,
5827 /* 14824 */ GIR_EraseRootFromParent_Done,
5828 /* 14825 */ // Label 617: @14825
5829 /* 14825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(14884), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2463 //
5830 /* 14832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5831 /* 14836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5832 /* 14840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5833 /* 14844 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5834 /* 14848 */ // MIs[1] Operand 1
5835 /* 14848 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5836 /* 14853 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5837 /* 14858 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5838 /* 14862 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5839 /* 14864 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5840 /* 14864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
5841 /* 14867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5842 /* 14871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5843 /* 14877 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5844 /* 14879 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5845 /* 14882 */ GIR_RootConstrainSelectedInstOperands,
5846 /* 14883 */ // GIR_Coverage, 2463,
5847 /* 14883 */ GIR_EraseRootFromParent_Done,
5848 /* 14884 */ // Label 618: @14884
5849 /* 14884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(14943), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2464 //
5850 /* 14891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5851 /* 14895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5852 /* 14899 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5853 /* 14903 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5854 /* 14907 */ // MIs[1] Operand 1
5855 /* 14907 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5856 /* 14912 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5857 /* 14917 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5858 /* 14921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5859 /* 14923 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5860 /* 14923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
5861 /* 14926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5862 /* 14930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5863 /* 14936 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5864 /* 14938 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5865 /* 14941 */ GIR_RootConstrainSelectedInstOperands,
5866 /* 14942 */ // GIR_Coverage, 2464,
5867 /* 14942 */ GIR_EraseRootFromParent_Done,
5868 /* 14943 */ // Label 619: @14943
5869 /* 14943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(14996), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2643 //
5870 /* 14950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5871 /* 14954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5872 /* 14958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5873 /* 14962 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5874 /* 14966 */ // MIs[1] Operand 1
5875 /* 14966 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5876 /* 14971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5877 /* 14976 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5878 /* 14980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5879 /* 14982 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5880 /* 14982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
5881 /* 14985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5882 /* 14989 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5883 /* 14991 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5884 /* 14994 */ GIR_RootConstrainSelectedInstOperands,
5885 /* 14995 */ // GIR_Coverage, 2643,
5886 /* 14995 */ GIR_EraseRootFromParent_Done,
5887 /* 14996 */ // Label 620: @14996
5888 /* 14996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(15049), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2644 //
5889 /* 15003 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5890 /* 15007 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5891 /* 15011 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5892 /* 15015 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5893 /* 15019 */ // MIs[1] Operand 1
5894 /* 15019 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5895 /* 15024 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5896 /* 15029 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5897 /* 15033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5898 /* 15035 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5899 /* 15035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
5900 /* 15038 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5901 /* 15042 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5902 /* 15044 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5903 /* 15047 */ GIR_RootConstrainSelectedInstOperands,
5904 /* 15048 */ // GIR_Coverage, 2644,
5905 /* 15048 */ GIR_EraseRootFromParent_Done,
5906 /* 15049 */ // Label 621: @15049
5907 /* 15049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(15097), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1498 //
5908 /* 15056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5909 /* 15060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5910 /* 15064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5911 /* 15068 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5912 /* 15072 */ // MIs[1] Operand 1
5913 /* 15072 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5914 /* 15077 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5915 /* 15081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5916 /* 15083 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5917 /* 15083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5918 /* 15086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5919 /* 15090 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5920 /* 15092 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5921 /* 15095 */ GIR_RootConstrainSelectedInstOperands,
5922 /* 15096 */ // GIR_Coverage, 1498,
5923 /* 15096 */ GIR_EraseRootFromParent_Done,
5924 /* 15097 */ // Label 622: @15097
5925 /* 15097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(15145), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1499 //
5926 /* 15104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5927 /* 15108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5928 /* 15112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5929 /* 15116 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5930 /* 15120 */ // MIs[1] Operand 1
5931 /* 15120 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5932 /* 15125 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
5933 /* 15129 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5934 /* 15131 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5935 /* 15131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5936 /* 15134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5937 /* 15138 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5938 /* 15140 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5939 /* 15143 */ GIR_RootConstrainSelectedInstOperands,
5940 /* 15144 */ // GIR_Coverage, 1499,
5941 /* 15144 */ GIR_EraseRootFromParent_Done,
5942 /* 15145 */ // Label 623: @15145
5943 /* 15145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 624*/ GIMT_Encode4(15193), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1751 //
5944 /* 15152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5945 /* 15156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5946 /* 15160 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5947 /* 15164 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5948 /* 15168 */ // MIs[1] Operand 1
5949 /* 15168 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5950 /* 15173 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5951 /* 15177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5952 /* 15179 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5953 /* 15179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5954 /* 15182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5955 /* 15186 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5956 /* 15188 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5957 /* 15191 */ GIR_RootConstrainSelectedInstOperands,
5958 /* 15192 */ // GIR_Coverage, 1751,
5959 /* 15192 */ GIR_EraseRootFromParent_Done,
5960 /* 15193 */ // Label 624: @15193
5961 /* 15193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 625*/ GIMT_Encode4(15241), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1752 //
5962 /* 15200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5963 /* 15204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5964 /* 15208 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5965 /* 15212 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5966 /* 15216 */ // MIs[1] Operand 1
5967 /* 15216 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5968 /* 15221 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
5969 /* 15225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5970 /* 15227 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5971 /* 15227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5972 /* 15230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5973 /* 15234 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5974 /* 15236 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5975 /* 15239 */ GIR_RootConstrainSelectedInstOperands,
5976 /* 15240 */ // GIR_Coverage, 1752,
5977 /* 15240 */ GIR_EraseRootFromParent_Done,
5978 /* 15241 */ // Label 625: @15241
5979 /* 15241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(15289), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2013 //
5980 /* 15248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5981 /* 15252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5982 /* 15256 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5983 /* 15260 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5984 /* 15264 */ // MIs[1] Operand 1
5985 /* 15264 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5986 /* 15269 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5987 /* 15273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5988 /* 15275 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5989 /* 15275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
5990 /* 15278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5991 /* 15282 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5992 /* 15284 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
5993 /* 15287 */ GIR_RootConstrainSelectedInstOperands,
5994 /* 15288 */ // GIR_Coverage, 2013,
5995 /* 15288 */ GIR_EraseRootFromParent_Done,
5996 /* 15289 */ // Label 626: @15289
5997 /* 15289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(15337), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2014 //
5998 /* 15296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5999 /* 15300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6000 /* 15304 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6001 /* 15308 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6002 /* 15312 */ // MIs[1] Operand 1
6003 /* 15312 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6004 /* 15317 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6005 /* 15321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6006 /* 15323 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6007 /* 15323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6008 /* 15326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6009 /* 15330 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6010 /* 15332 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6011 /* 15335 */ GIR_RootConstrainSelectedInstOperands,
6012 /* 15336 */ // GIR_Coverage, 2014,
6013 /* 15336 */ GIR_EraseRootFromParent_Done,
6014 /* 15337 */ // Label 627: @15337
6015 /* 15337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 628*/ GIMT_Encode4(15385), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2015 //
6016 /* 15344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6017 /* 15348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6018 /* 15352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6019 /* 15356 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6020 /* 15360 */ // MIs[1] Operand 1
6021 /* 15360 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6022 /* 15365 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6023 /* 15369 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6024 /* 15371 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6025 /* 15371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6026 /* 15374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6027 /* 15378 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6028 /* 15380 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6029 /* 15383 */ GIR_RootConstrainSelectedInstOperands,
6030 /* 15384 */ // GIR_Coverage, 2015,
6031 /* 15384 */ GIR_EraseRootFromParent_Done,
6032 /* 15385 */ // Label 628: @15385
6033 /* 15385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 629*/ GIMT_Encode4(15433), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2016 //
6034 /* 15392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6035 /* 15396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6036 /* 15400 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6037 /* 15404 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6038 /* 15408 */ // MIs[1] Operand 1
6039 /* 15408 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6040 /* 15413 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6041 /* 15417 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6042 /* 15419 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6043 /* 15419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6044 /* 15422 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6045 /* 15426 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6046 /* 15428 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6047 /* 15431 */ GIR_RootConstrainSelectedInstOperands,
6048 /* 15432 */ // GIR_Coverage, 2016,
6049 /* 15432 */ GIR_EraseRootFromParent_Done,
6050 /* 15433 */ // Label 629: @15433
6051 /* 15433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(15481), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2017 //
6052 /* 15440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6053 /* 15444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6054 /* 15448 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6055 /* 15452 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6056 /* 15456 */ // MIs[1] Operand 1
6057 /* 15456 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6058 /* 15461 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6059 /* 15465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6060 /* 15467 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6061 /* 15467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6062 /* 15470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6063 /* 15474 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6064 /* 15476 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6065 /* 15479 */ GIR_RootConstrainSelectedInstOperands,
6066 /* 15480 */ // GIR_Coverage, 2017,
6067 /* 15480 */ GIR_EraseRootFromParent_Done,
6068 /* 15481 */ // Label 630: @15481
6069 /* 15481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(15529), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2018 //
6070 /* 15488 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6071 /* 15492 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6072 /* 15496 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6073 /* 15500 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6074 /* 15504 */ // MIs[1] Operand 1
6075 /* 15504 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6076 /* 15509 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6077 /* 15513 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6078 /* 15515 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6079 /* 15515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6080 /* 15518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6081 /* 15522 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6082 /* 15524 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6083 /* 15527 */ GIR_RootConstrainSelectedInstOperands,
6084 /* 15528 */ // GIR_Coverage, 2018,
6085 /* 15528 */ GIR_EraseRootFromParent_Done,
6086 /* 15529 */ // Label 631: @15529
6087 /* 15529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 632*/ GIMT_Encode4(15577), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2019 //
6088 /* 15536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6089 /* 15540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6090 /* 15544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6091 /* 15548 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6092 /* 15552 */ // MIs[1] Operand 1
6093 /* 15552 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6094 /* 15557 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6095 /* 15561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6096 /* 15563 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6097 /* 15563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6098 /* 15566 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6099 /* 15570 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6100 /* 15572 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6101 /* 15575 */ GIR_RootConstrainSelectedInstOperands,
6102 /* 15576 */ // GIR_Coverage, 2019,
6103 /* 15576 */ GIR_EraseRootFromParent_Done,
6104 /* 15577 */ // Label 632: @15577
6105 /* 15577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 633*/ GIMT_Encode4(15625), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2020 //
6106 /* 15584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6107 /* 15588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6108 /* 15592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6109 /* 15596 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6110 /* 15600 */ // MIs[1] Operand 1
6111 /* 15600 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6112 /* 15605 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6113 /* 15609 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6114 /* 15611 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6115 /* 15611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6116 /* 15614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6117 /* 15618 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6118 /* 15620 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6119 /* 15623 */ GIR_RootConstrainSelectedInstOperands,
6120 /* 15624 */ // GIR_Coverage, 2020,
6121 /* 15624 */ GIR_EraseRootFromParent_Done,
6122 /* 15625 */ // Label 633: @15625
6123 /* 15625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(15673), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2056 //
6124 /* 15632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6125 /* 15636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6126 /* 15640 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6127 /* 15644 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6128 /* 15648 */ // MIs[1] Operand 1
6129 /* 15648 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6130 /* 15653 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6131 /* 15657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6132 /* 15659 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6133 /* 15659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6134 /* 15662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6135 /* 15666 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6136 /* 15668 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6137 /* 15671 */ GIR_RootConstrainSelectedInstOperands,
6138 /* 15672 */ // GIR_Coverage, 2056,
6139 /* 15672 */ GIR_EraseRootFromParent_Done,
6140 /* 15673 */ // Label 634: @15673
6141 /* 15673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 635*/ GIMT_Encode4(15721), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2057 //
6142 /* 15680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6143 /* 15684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6144 /* 15688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6145 /* 15692 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6146 /* 15696 */ // MIs[1] Operand 1
6147 /* 15696 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6148 /* 15701 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6149 /* 15705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6150 /* 15707 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6151 /* 15707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6152 /* 15710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6153 /* 15714 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6154 /* 15716 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6155 /* 15719 */ GIR_RootConstrainSelectedInstOperands,
6156 /* 15720 */ // GIR_Coverage, 2057,
6157 /* 15720 */ GIR_EraseRootFromParent_Done,
6158 /* 15721 */ // Label 635: @15721
6159 /* 15721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 636*/ GIMT_Encode4(15769), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2058 //
6160 /* 15728 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6161 /* 15732 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6162 /* 15736 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6163 /* 15740 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6164 /* 15744 */ // MIs[1] Operand 1
6165 /* 15744 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6166 /* 15749 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6167 /* 15753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6168 /* 15755 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6169 /* 15755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6170 /* 15758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6171 /* 15762 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6172 /* 15764 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6173 /* 15767 */ GIR_RootConstrainSelectedInstOperands,
6174 /* 15768 */ // GIR_Coverage, 2058,
6175 /* 15768 */ GIR_EraseRootFromParent_Done,
6176 /* 15769 */ // Label 636: @15769
6177 /* 15769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(15817), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2059 //
6178 /* 15776 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6179 /* 15780 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6180 /* 15784 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6181 /* 15788 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6182 /* 15792 */ // MIs[1] Operand 1
6183 /* 15792 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6184 /* 15797 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6185 /* 15801 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6186 /* 15803 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6187 /* 15803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6188 /* 15806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6189 /* 15810 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6190 /* 15812 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6191 /* 15815 */ GIR_RootConstrainSelectedInstOperands,
6192 /* 15816 */ // GIR_Coverage, 2059,
6193 /* 15816 */ GIR_EraseRootFromParent_Done,
6194 /* 15817 */ // Label 637: @15817
6195 /* 15817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 638*/ GIMT_Encode4(15865), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2060 //
6196 /* 15824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6197 /* 15828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6198 /* 15832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6199 /* 15836 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6200 /* 15840 */ // MIs[1] Operand 1
6201 /* 15840 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6202 /* 15845 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6203 /* 15849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6204 /* 15851 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6205 /* 15851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6206 /* 15854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6207 /* 15858 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6208 /* 15860 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6209 /* 15863 */ GIR_RootConstrainSelectedInstOperands,
6210 /* 15864 */ // GIR_Coverage, 2060,
6211 /* 15864 */ GIR_EraseRootFromParent_Done,
6212 /* 15865 */ // Label 638: @15865
6213 /* 15865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 639*/ GIMT_Encode4(15913), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2061 //
6214 /* 15872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6215 /* 15876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6216 /* 15880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6217 /* 15884 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6218 /* 15888 */ // MIs[1] Operand 1
6219 /* 15888 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6220 /* 15893 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6221 /* 15897 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6222 /* 15899 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6223 /* 15899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6224 /* 15902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6225 /* 15906 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6226 /* 15908 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6227 /* 15911 */ GIR_RootConstrainSelectedInstOperands,
6228 /* 15912 */ // GIR_Coverage, 2061,
6229 /* 15912 */ GIR_EraseRootFromParent_Done,
6230 /* 15913 */ // Label 639: @15913
6231 /* 15913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 640*/ GIMT_Encode4(15961), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2062 //
6232 /* 15920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6233 /* 15924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6234 /* 15928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6235 /* 15932 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6236 /* 15936 */ // MIs[1] Operand 1
6237 /* 15936 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6238 /* 15941 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6239 /* 15945 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6240 /* 15947 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6241 /* 15947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6242 /* 15950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6243 /* 15954 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6244 /* 15956 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6245 /* 15959 */ GIR_RootConstrainSelectedInstOperands,
6246 /* 15960 */ // GIR_Coverage, 2062,
6247 /* 15960 */ GIR_EraseRootFromParent_Done,
6248 /* 15961 */ // Label 640: @15961
6249 /* 15961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 641*/ GIMT_Encode4(16009), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2063 //
6250 /* 15968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6251 /* 15972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6252 /* 15976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6253 /* 15980 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6254 /* 15984 */ // MIs[1] Operand 1
6255 /* 15984 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6256 /* 15989 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6257 /* 15993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6258 /* 15995 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6259 /* 15995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6260 /* 15998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6261 /* 16002 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6262 /* 16004 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6263 /* 16007 */ GIR_RootConstrainSelectedInstOperands,
6264 /* 16008 */ // GIR_Coverage, 2063,
6265 /* 16008 */ GIR_EraseRootFromParent_Done,
6266 /* 16009 */ // Label 641: @16009
6267 /* 16009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 642*/ GIMT_Encode4(16057), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2474 //
6268 /* 16016 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6269 /* 16020 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6270 /* 16024 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6271 /* 16028 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6272 /* 16032 */ // MIs[1] Operand 1
6273 /* 16032 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6274 /* 16037 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6275 /* 16041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6276 /* 16043 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6277 /* 16043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
6278 /* 16046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6279 /* 16050 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6280 /* 16052 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6281 /* 16055 */ GIR_RootConstrainSelectedInstOperands,
6282 /* 16056 */ // GIR_Coverage, 2474,
6283 /* 16056 */ GIR_EraseRootFromParent_Done,
6284 /* 16057 */ // Label 642: @16057
6285 /* 16057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 643*/ GIMT_Encode4(16105), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2475 //
6286 /* 16064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6287 /* 16068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6288 /* 16072 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6289 /* 16076 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6290 /* 16080 */ // MIs[1] Operand 1
6291 /* 16080 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6292 /* 16085 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6293 /* 16089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6294 /* 16091 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6295 /* 16091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
6296 /* 16094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6297 /* 16098 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6298 /* 16100 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6299 /* 16103 */ GIR_RootConstrainSelectedInstOperands,
6300 /* 16104 */ // GIR_Coverage, 2475,
6301 /* 16104 */ GIR_EraseRootFromParent_Done,
6302 /* 16105 */ // Label 643: @16105
6303 /* 16105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 644*/ GIMT_Encode4(16163), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 112 //
6304 /* 16112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6305 /* 16116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6306 /* 16120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6307 /* 16124 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6308 /* 16128 */ // MIs[1] Operand 1
6309 /* 16128 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6310 /* 16133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6311 /* 16138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6312 /* 16143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6313 /* 16145 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6314 /* 16145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6315 /* 16148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6316 /* 16152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6317 /* 16156 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6318 /* 16158 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6319 /* 16161 */ GIR_RootConstrainSelectedInstOperands,
6320 /* 16162 */ // GIR_Coverage, 112,
6321 /* 16162 */ GIR_EraseRootFromParent_Done,
6322 /* 16163 */ // Label 644: @16163
6323 /* 16163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 645*/ GIMT_Encode4(16221), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 113 //
6324 /* 16170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6325 /* 16174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6326 /* 16178 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6327 /* 16182 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6328 /* 16186 */ // MIs[1] Operand 1
6329 /* 16186 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6330 /* 16191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6331 /* 16196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6332 /* 16201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6333 /* 16203 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6334 /* 16203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6335 /* 16206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6336 /* 16210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6337 /* 16214 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6338 /* 16216 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6339 /* 16219 */ GIR_RootConstrainSelectedInstOperands,
6340 /* 16220 */ // GIR_Coverage, 113,
6341 /* 16220 */ GIR_EraseRootFromParent_Done,
6342 /* 16221 */ // Label 645: @16221
6343 /* 16221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 646*/ GIMT_Encode4(16279), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 317 //
6344 /* 16228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6345 /* 16232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6346 /* 16236 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6347 /* 16240 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6348 /* 16244 */ // MIs[1] Operand 1
6349 /* 16244 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6350 /* 16249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6351 /* 16254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6352 /* 16259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6353 /* 16261 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6354 /* 16261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6355 /* 16264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6356 /* 16268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6357 /* 16272 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6358 /* 16274 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6359 /* 16277 */ GIR_RootConstrainSelectedInstOperands,
6360 /* 16278 */ // GIR_Coverage, 317,
6361 /* 16278 */ GIR_EraseRootFromParent_Done,
6362 /* 16279 */ // Label 646: @16279
6363 /* 16279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 647*/ GIMT_Encode4(16337), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 318 //
6364 /* 16286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6365 /* 16290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6366 /* 16294 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6367 /* 16298 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6368 /* 16302 */ // MIs[1] Operand 1
6369 /* 16302 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6370 /* 16307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6371 /* 16312 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6372 /* 16317 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6373 /* 16319 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6374 /* 16319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6375 /* 16322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6376 /* 16326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6377 /* 16330 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6378 /* 16332 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6379 /* 16335 */ GIR_RootConstrainSelectedInstOperands,
6380 /* 16336 */ // GIR_Coverage, 318,
6381 /* 16336 */ GIR_EraseRootFromParent_Done,
6382 /* 16337 */ // Label 647: @16337
6383 /* 16337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(16395), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1187 //
6384 /* 16344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6385 /* 16348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6386 /* 16352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6387 /* 16356 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6388 /* 16360 */ // MIs[1] Operand 1
6389 /* 16360 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6390 /* 16365 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6391 /* 16370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6392 /* 16375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6393 /* 16377 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6394 /* 16377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6395 /* 16380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6396 /* 16384 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6397 /* 16388 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6398 /* 16390 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6399 /* 16393 */ GIR_RootConstrainSelectedInstOperands,
6400 /* 16394 */ // GIR_Coverage, 1187,
6401 /* 16394 */ GIR_EraseRootFromParent_Done,
6402 /* 16395 */ // Label 648: @16395
6403 /* 16395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(16453), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1188 //
6404 /* 16402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6405 /* 16406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6406 /* 16410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6407 /* 16414 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6408 /* 16418 */ // MIs[1] Operand 1
6409 /* 16418 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6410 /* 16423 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6411 /* 16428 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6412 /* 16433 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6413 /* 16435 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6414 /* 16435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6415 /* 16438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6416 /* 16442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6417 /* 16446 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6418 /* 16448 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6419 /* 16451 */ GIR_RootConstrainSelectedInstOperands,
6420 /* 16452 */ // GIR_Coverage, 1188,
6421 /* 16452 */ GIR_EraseRootFromParent_Done,
6422 /* 16453 */ // Label 649: @16453
6423 /* 16453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 650*/ GIMT_Encode4(16534), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1489 //
6424 /* 16460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6425 /* 16464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6426 /* 16468 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6427 /* 16472 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6428 /* 16476 */ // MIs[1] Operand 1
6429 /* 16476 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6430 /* 16481 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6431 /* 16486 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6432 /* 16491 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6433 /* 16493 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6434 /* 16493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6435 /* 16496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6436 /* 16500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6437 /* 16505 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6438 /* 16509 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6439 /* 16513 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6440 /* 16515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6441 /* 16518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6442 /* 16521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6443 /* 16527 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6444 /* 16529 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6445 /* 16532 */ GIR_RootConstrainSelectedInstOperands,
6446 /* 16533 */ // GIR_Coverage, 1489,
6447 /* 16533 */ GIR_EraseRootFromParent_Done,
6448 /* 16534 */ // Label 650: @16534
6449 /* 16534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 651*/ GIMT_Encode4(16615), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1490 //
6450 /* 16541 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6451 /* 16545 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6452 /* 16549 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6453 /* 16553 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6454 /* 16557 */ // MIs[1] Operand 1
6455 /* 16557 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6456 /* 16562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6457 /* 16567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6458 /* 16572 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6459 /* 16574 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6460 /* 16574 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6461 /* 16577 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6462 /* 16581 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6463 /* 16586 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6464 /* 16590 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6465 /* 16594 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6466 /* 16596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6467 /* 16599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6468 /* 16602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6469 /* 16608 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6470 /* 16610 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6471 /* 16613 */ GIR_RootConstrainSelectedInstOperands,
6472 /* 16614 */ // GIR_Coverage, 1490,
6473 /* 16614 */ GIR_EraseRootFromParent_Done,
6474 /* 16615 */ // Label 651: @16615
6475 /* 16615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(16696), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1495 //
6476 /* 16622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6477 /* 16626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6478 /* 16630 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6479 /* 16634 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6480 /* 16638 */ // MIs[1] Operand 1
6481 /* 16638 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6482 /* 16643 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6483 /* 16648 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6484 /* 16653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6485 /* 16655 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6486 /* 16655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6487 /* 16658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6488 /* 16662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6489 /* 16667 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6490 /* 16671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6491 /* 16675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6492 /* 16677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6493 /* 16680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6494 /* 16683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6495 /* 16689 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6496 /* 16691 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6497 /* 16694 */ GIR_RootConstrainSelectedInstOperands,
6498 /* 16695 */ // GIR_Coverage, 1495,
6499 /* 16695 */ GIR_EraseRootFromParent_Done,
6500 /* 16696 */ // Label 652: @16696
6501 /* 16696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(16777), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1496 //
6502 /* 16703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6503 /* 16707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6504 /* 16711 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6505 /* 16715 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6506 /* 16719 */ // MIs[1] Operand 1
6507 /* 16719 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6508 /* 16724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6509 /* 16729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6510 /* 16734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6511 /* 16736 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6512 /* 16736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6513 /* 16739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6514 /* 16743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6515 /* 16748 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6516 /* 16752 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6517 /* 16756 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6518 /* 16758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6519 /* 16761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6520 /* 16764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6521 /* 16770 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6522 /* 16772 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6523 /* 16775 */ GIR_RootConstrainSelectedInstOperands,
6524 /* 16776 */ // GIR_Coverage, 1496,
6525 /* 16776 */ GIR_EraseRootFromParent_Done,
6526 /* 16777 */ // Label 653: @16777
6527 /* 16777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 654*/ GIMT_Encode4(16858), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1742 //
6528 /* 16784 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6529 /* 16788 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6530 /* 16792 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6531 /* 16796 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6532 /* 16800 */ // MIs[1] Operand 1
6533 /* 16800 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6534 /* 16805 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6535 /* 16810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6536 /* 16815 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6537 /* 16817 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6538 /* 16817 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6539 /* 16820 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6540 /* 16824 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6541 /* 16829 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6542 /* 16833 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6543 /* 16837 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6544 /* 16839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6545 /* 16842 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6546 /* 16845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6547 /* 16851 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6548 /* 16853 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6549 /* 16856 */ GIR_RootConstrainSelectedInstOperands,
6550 /* 16857 */ // GIR_Coverage, 1742,
6551 /* 16857 */ GIR_EraseRootFromParent_Done,
6552 /* 16858 */ // Label 654: @16858
6553 /* 16858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 655*/ GIMT_Encode4(16939), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1743 //
6554 /* 16865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6555 /* 16869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6556 /* 16873 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6557 /* 16877 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6558 /* 16881 */ // MIs[1] Operand 1
6559 /* 16881 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6560 /* 16886 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6561 /* 16891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6562 /* 16896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6563 /* 16898 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6564 /* 16898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6565 /* 16901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6566 /* 16905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6567 /* 16910 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6568 /* 16914 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6569 /* 16918 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6570 /* 16920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6571 /* 16923 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6572 /* 16926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6573 /* 16932 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6574 /* 16934 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6575 /* 16937 */ GIR_RootConstrainSelectedInstOperands,
6576 /* 16938 */ // GIR_Coverage, 1743,
6577 /* 16938 */ GIR_EraseRootFromParent_Done,
6578 /* 16939 */ // Label 655: @16939
6579 /* 16939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(17020), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1748 //
6580 /* 16946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6581 /* 16950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6582 /* 16954 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6583 /* 16958 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6584 /* 16962 */ // MIs[1] Operand 1
6585 /* 16962 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6586 /* 16967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6587 /* 16972 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6588 /* 16977 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6589 /* 16979 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6590 /* 16979 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6591 /* 16982 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6592 /* 16986 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6593 /* 16991 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6594 /* 16995 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6595 /* 16999 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6596 /* 17001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6597 /* 17004 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6598 /* 17007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6599 /* 17013 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6600 /* 17015 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6601 /* 17018 */ GIR_RootConstrainSelectedInstOperands,
6602 /* 17019 */ // GIR_Coverage, 1748,
6603 /* 17019 */ GIR_EraseRootFromParent_Done,
6604 /* 17020 */ // Label 656: @17020
6605 /* 17020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 657*/ GIMT_Encode4(17101), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1749 //
6606 /* 17027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6607 /* 17031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6608 /* 17035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6609 /* 17039 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6610 /* 17043 */ // MIs[1] Operand 1
6611 /* 17043 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6612 /* 17048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6613 /* 17053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6614 /* 17058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6615 /* 17060 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6616 /* 17060 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6617 /* 17063 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6618 /* 17067 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6619 /* 17072 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6620 /* 17076 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6621 /* 17080 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6622 /* 17082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6623 /* 17085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6624 /* 17088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6625 /* 17094 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6626 /* 17096 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6627 /* 17099 */ GIR_RootConstrainSelectedInstOperands,
6628 /* 17100 */ // GIR_Coverage, 1749,
6629 /* 17100 */ GIR_EraseRootFromParent_Done,
6630 /* 17101 */ // Label 657: @17101
6631 /* 17101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 658*/ GIMT_Encode4(17159), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2021 //
6632 /* 17108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6633 /* 17112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6634 /* 17116 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6635 /* 17120 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6636 /* 17124 */ // MIs[1] Operand 1
6637 /* 17124 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6638 /* 17129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6639 /* 17134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6640 /* 17139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6641 /* 17141 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6642 /* 17141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
6643 /* 17144 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6644 /* 17148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6645 /* 17152 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6646 /* 17154 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6647 /* 17157 */ GIR_RootConstrainSelectedInstOperands,
6648 /* 17158 */ // GIR_Coverage, 2021,
6649 /* 17158 */ GIR_EraseRootFromParent_Done,
6650 /* 17159 */ // Label 658: @17159
6651 /* 17159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 659*/ GIMT_Encode4(17217), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2022 //
6652 /* 17166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6653 /* 17170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6654 /* 17174 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6655 /* 17178 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6656 /* 17182 */ // MIs[1] Operand 1
6657 /* 17182 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6658 /* 17187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6659 /* 17192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6660 /* 17197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6661 /* 17199 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6662 /* 17199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
6663 /* 17202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6664 /* 17206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6665 /* 17210 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6666 /* 17212 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6667 /* 17215 */ GIR_RootConstrainSelectedInstOperands,
6668 /* 17216 */ // GIR_Coverage, 2022,
6669 /* 17216 */ GIR_EraseRootFromParent_Done,
6670 /* 17217 */ // Label 659: @17217
6671 /* 17217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 660*/ GIMT_Encode4(17275), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2023 //
6672 /* 17224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6673 /* 17228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6674 /* 17232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6675 /* 17236 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6676 /* 17240 */ // MIs[1] Operand 1
6677 /* 17240 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6678 /* 17245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6679 /* 17250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6680 /* 17255 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6681 /* 17257 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6682 /* 17257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
6683 /* 17260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6684 /* 17264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6685 /* 17268 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6686 /* 17270 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6687 /* 17273 */ GIR_RootConstrainSelectedInstOperands,
6688 /* 17274 */ // GIR_Coverage, 2023,
6689 /* 17274 */ GIR_EraseRootFromParent_Done,
6690 /* 17275 */ // Label 660: @17275
6691 /* 17275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 661*/ GIMT_Encode4(17333), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2024 //
6692 /* 17282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6693 /* 17286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6694 /* 17290 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6695 /* 17294 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6696 /* 17298 */ // MIs[1] Operand 1
6697 /* 17298 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6698 /* 17303 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6699 /* 17308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6700 /* 17313 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6701 /* 17315 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6702 /* 17315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
6703 /* 17318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6704 /* 17322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6705 /* 17326 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6706 /* 17328 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6707 /* 17331 */ GIR_RootConstrainSelectedInstOperands,
6708 /* 17332 */ // GIR_Coverage, 2024,
6709 /* 17332 */ GIR_EraseRootFromParent_Done,
6710 /* 17333 */ // Label 661: @17333
6711 /* 17333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 662*/ GIMT_Encode4(17391), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2025 //
6712 /* 17340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6713 /* 17344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6714 /* 17348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6715 /* 17352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6716 /* 17356 */ // MIs[1] Operand 1
6717 /* 17356 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
6718 /* 17361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6719 /* 17366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6720 /* 17371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6721 /* 17373 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6722 /* 17373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
6723 /* 17376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6724 /* 17380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6725 /* 17384 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6726 /* 17386 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6727 /* 17389 */ GIR_RootConstrainSelectedInstOperands,
6728 /* 17390 */ // GIR_Coverage, 2025,
6729 /* 17390 */ GIR_EraseRootFromParent_Done,
6730 /* 17391 */ // Label 662: @17391
6731 /* 17391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 663*/ GIMT_Encode4(17449), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2026 //
6732 /* 17398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6733 /* 17402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6734 /* 17406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6735 /* 17410 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6736 /* 17414 */ // MIs[1] Operand 1
6737 /* 17414 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6738 /* 17419 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6739 /* 17424 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6740 /* 17429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6741 /* 17431 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6742 /* 17431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
6743 /* 17434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6744 /* 17438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6745 /* 17442 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6746 /* 17444 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6747 /* 17447 */ GIR_RootConstrainSelectedInstOperands,
6748 /* 17448 */ // GIR_Coverage, 2026,
6749 /* 17448 */ GIR_EraseRootFromParent_Done,
6750 /* 17449 */ // Label 663: @17449
6751 /* 17449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 664*/ GIMT_Encode4(17507), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2027 //
6752 /* 17456 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6753 /* 17460 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6754 /* 17464 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6755 /* 17468 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6756 /* 17472 */ // MIs[1] Operand 1
6757 /* 17472 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
6758 /* 17477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6759 /* 17482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6760 /* 17487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6761 /* 17489 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6762 /* 17489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
6763 /* 17492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6764 /* 17496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6765 /* 17500 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6766 /* 17502 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6767 /* 17505 */ GIR_RootConstrainSelectedInstOperands,
6768 /* 17506 */ // GIR_Coverage, 2027,
6769 /* 17506 */ GIR_EraseRootFromParent_Done,
6770 /* 17507 */ // Label 664: @17507
6771 /* 17507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 665*/ GIMT_Encode4(17565), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2028 //
6772 /* 17514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6773 /* 17518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6774 /* 17522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6775 /* 17526 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6776 /* 17530 */ // MIs[1] Operand 1
6777 /* 17530 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6778 /* 17535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6779 /* 17540 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6780 /* 17545 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6781 /* 17547 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6782 /* 17547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
6783 /* 17550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6784 /* 17554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6785 /* 17558 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6786 /* 17560 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6787 /* 17563 */ GIR_RootConstrainSelectedInstOperands,
6788 /* 17564 */ // GIR_Coverage, 2028,
6789 /* 17564 */ GIR_EraseRootFromParent_Done,
6790 /* 17565 */ // Label 665: @17565
6791 /* 17565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 666*/ GIMT_Encode4(17623), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2064 //
6792 /* 17572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6793 /* 17576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6794 /* 17580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6795 /* 17584 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6796 /* 17588 */ // MIs[1] Operand 1
6797 /* 17588 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6798 /* 17593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6799 /* 17598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6800 /* 17603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6801 /* 17605 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6802 /* 17605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
6803 /* 17608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6804 /* 17612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6805 /* 17616 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6806 /* 17618 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6807 /* 17621 */ GIR_RootConstrainSelectedInstOperands,
6808 /* 17622 */ // GIR_Coverage, 2064,
6809 /* 17622 */ GIR_EraseRootFromParent_Done,
6810 /* 17623 */ // Label 666: @17623
6811 /* 17623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(17681), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2065 //
6812 /* 17630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6813 /* 17634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6814 /* 17638 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6815 /* 17642 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6816 /* 17646 */ // MIs[1] Operand 1
6817 /* 17646 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6818 /* 17651 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6819 /* 17656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6820 /* 17661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6821 /* 17663 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6822 /* 17663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
6823 /* 17666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6824 /* 17670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6825 /* 17674 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6826 /* 17676 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6827 /* 17679 */ GIR_RootConstrainSelectedInstOperands,
6828 /* 17680 */ // GIR_Coverage, 2065,
6829 /* 17680 */ GIR_EraseRootFromParent_Done,
6830 /* 17681 */ // Label 667: @17681
6831 /* 17681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(17739), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2066 //
6832 /* 17688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6833 /* 17692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6834 /* 17696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6835 /* 17700 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6836 /* 17704 */ // MIs[1] Operand 1
6837 /* 17704 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6838 /* 17709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6839 /* 17714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6840 /* 17719 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6841 /* 17721 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6842 /* 17721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
6843 /* 17724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6844 /* 17728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6845 /* 17732 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6846 /* 17734 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6847 /* 17737 */ GIR_RootConstrainSelectedInstOperands,
6848 /* 17738 */ // GIR_Coverage, 2066,
6849 /* 17738 */ GIR_EraseRootFromParent_Done,
6850 /* 17739 */ // Label 668: @17739
6851 /* 17739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 669*/ GIMT_Encode4(17797), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2067 //
6852 /* 17746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6853 /* 17750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6854 /* 17754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6855 /* 17758 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6856 /* 17762 */ // MIs[1] Operand 1
6857 /* 17762 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6858 /* 17767 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6859 /* 17772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6860 /* 17777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6861 /* 17779 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6862 /* 17779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
6863 /* 17782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6864 /* 17786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6865 /* 17790 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6866 /* 17792 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6867 /* 17795 */ GIR_RootConstrainSelectedInstOperands,
6868 /* 17796 */ // GIR_Coverage, 2067,
6869 /* 17796 */ GIR_EraseRootFromParent_Done,
6870 /* 17797 */ // Label 669: @17797
6871 /* 17797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 670*/ GIMT_Encode4(17855), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2068 //
6872 /* 17804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6873 /* 17808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6874 /* 17812 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6875 /* 17816 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6876 /* 17820 */ // MIs[1] Operand 1
6877 /* 17820 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
6878 /* 17825 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6879 /* 17830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6880 /* 17835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6881 /* 17837 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6882 /* 17837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
6883 /* 17840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6884 /* 17844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6885 /* 17848 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6886 /* 17850 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6887 /* 17853 */ GIR_RootConstrainSelectedInstOperands,
6888 /* 17854 */ // GIR_Coverage, 2068,
6889 /* 17854 */ GIR_EraseRootFromParent_Done,
6890 /* 17855 */ // Label 670: @17855
6891 /* 17855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(17913), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2069 //
6892 /* 17862 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6893 /* 17866 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6894 /* 17870 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6895 /* 17874 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6896 /* 17878 */ // MIs[1] Operand 1
6897 /* 17878 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6898 /* 17883 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6899 /* 17888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6900 /* 17893 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6901 /* 17895 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6902 /* 17895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
6903 /* 17898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6904 /* 17902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6905 /* 17906 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6906 /* 17908 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6907 /* 17911 */ GIR_RootConstrainSelectedInstOperands,
6908 /* 17912 */ // GIR_Coverage, 2069,
6909 /* 17912 */ GIR_EraseRootFromParent_Done,
6910 /* 17913 */ // Label 671: @17913
6911 /* 17913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(17971), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2070 //
6912 /* 17920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6913 /* 17924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6914 /* 17928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6915 /* 17932 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6916 /* 17936 */ // MIs[1] Operand 1
6917 /* 17936 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
6918 /* 17941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6919 /* 17946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6920 /* 17951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6921 /* 17953 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6922 /* 17953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
6923 /* 17956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6924 /* 17960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6925 /* 17964 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6926 /* 17966 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6927 /* 17969 */ GIR_RootConstrainSelectedInstOperands,
6928 /* 17970 */ // GIR_Coverage, 2070,
6929 /* 17970 */ GIR_EraseRootFromParent_Done,
6930 /* 17971 */ // Label 672: @17971
6931 /* 17971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 673*/ GIMT_Encode4(18029), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 2071 //
6932 /* 17978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6933 /* 17982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6934 /* 17986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6935 /* 17990 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6936 /* 17994 */ // MIs[1] Operand 1
6937 /* 17994 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6938 /* 17999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6939 /* 18004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6940 /* 18009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6941 /* 18011 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6942 /* 18011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
6943 /* 18014 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6944 /* 18018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6945 /* 18022 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6946 /* 18024 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
6947 /* 18027 */ GIR_RootConstrainSelectedInstOperands,
6948 /* 18028 */ // GIR_Coverage, 2071,
6949 /* 18028 */ GIR_EraseRootFromParent_Done,
6950 /* 18029 */ // Label 673: @18029
6951 /* 18029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 674*/ GIMT_Encode4(18084), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2101 //
6952 /* 18036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6953 /* 18040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6954 /* 18044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6955 /* 18048 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6956 /* 18052 */ // MIs[1] Operand 1
6957 /* 18052 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6958 /* 18057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6959 /* 18062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6960 /* 18067 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6961 /* 18069 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6962 /* 18069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
6963 /* 18072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6964 /* 18076 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6965 /* 18080 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6966 /* 18082 */ GIR_RootConstrainSelectedInstOperands,
6967 /* 18083 */ // GIR_Coverage, 2101,
6968 /* 18083 */ GIR_EraseRootFromParent_Done,
6969 /* 18084 */ // Label 674: @18084
6970 /* 18084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(18139), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2104 //
6971 /* 18091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6972 /* 18095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6973 /* 18099 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6974 /* 18103 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6975 /* 18107 */ // MIs[1] Operand 1
6976 /* 18107 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6977 /* 18112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6978 /* 18117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6979 /* 18122 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6980 /* 18124 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6981 /* 18124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
6982 /* 18127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6983 /* 18131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6984 /* 18135 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6985 /* 18137 */ GIR_RootConstrainSelectedInstOperands,
6986 /* 18138 */ // GIR_Coverage, 2104,
6987 /* 18138 */ GIR_EraseRootFromParent_Done,
6988 /* 18139 */ // Label 675: @18139
6989 /* 18139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 676*/ GIMT_Encode4(18194), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2105 //
6990 /* 18146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6991 /* 18150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6992 /* 18154 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6993 /* 18158 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6994 /* 18162 */ // MIs[1] Operand 1
6995 /* 18162 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6996 /* 18167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6997 /* 18172 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6998 /* 18177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6999 /* 18179 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7000 /* 18179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7001 /* 18182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7002 /* 18186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7003 /* 18190 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7004 /* 18192 */ GIR_RootConstrainSelectedInstOperands,
7005 /* 18193 */ // GIR_Coverage, 2105,
7006 /* 18193 */ GIR_EraseRootFromParent_Done,
7007 /* 18194 */ // Label 676: @18194
7008 /* 18194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 677*/ GIMT_Encode4(18249), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2107 //
7009 /* 18201 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7010 /* 18205 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7011 /* 18209 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7012 /* 18213 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7013 /* 18217 */ // MIs[1] Operand 1
7014 /* 18217 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7015 /* 18222 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7016 /* 18227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7017 /* 18232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7018 /* 18234 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7019 /* 18234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
7020 /* 18237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7021 /* 18241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7022 /* 18245 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7023 /* 18247 */ GIR_RootConstrainSelectedInstOperands,
7024 /* 18248 */ // GIR_Coverage, 2107,
7025 /* 18248 */ GIR_EraseRootFromParent_Done,
7026 /* 18249 */ // Label 677: @18249
7027 /* 18249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 678*/ GIMT_Encode4(18304), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2109 //
7028 /* 18256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7029 /* 18260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7030 /* 18264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7031 /* 18268 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7032 /* 18272 */ // MIs[1] Operand 1
7033 /* 18272 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7034 /* 18277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7035 /* 18282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7036 /* 18287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7037 /* 18289 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
7038 /* 18289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7039 /* 18292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7040 /* 18296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7041 /* 18300 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7042 /* 18302 */ GIR_RootConstrainSelectedInstOperands,
7043 /* 18303 */ // GIR_Coverage, 2109,
7044 /* 18303 */ GIR_EraseRootFromParent_Done,
7045 /* 18304 */ // Label 678: @18304
7046 /* 18304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 679*/ GIMT_Encode4(18359), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2110 //
7047 /* 18311 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7048 /* 18315 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7049 /* 18319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7050 /* 18323 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7051 /* 18327 */ // MIs[1] Operand 1
7052 /* 18327 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
7053 /* 18332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7054 /* 18337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7055 /* 18342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7056 /* 18344 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7057 /* 18344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
7058 /* 18347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7059 /* 18351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7060 /* 18355 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7061 /* 18357 */ GIR_RootConstrainSelectedInstOperands,
7062 /* 18358 */ // GIR_Coverage, 2110,
7063 /* 18358 */ GIR_EraseRootFromParent_Done,
7064 /* 18359 */ // Label 679: @18359
7065 /* 18359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 680*/ GIMT_Encode4(18440), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2465 //
7066 /* 18366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7067 /* 18370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7068 /* 18374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7069 /* 18378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7070 /* 18382 */ // MIs[1] Operand 1
7071 /* 18382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7072 /* 18387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7073 /* 18392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7074 /* 18397 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7075 /* 18399 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7076 /* 18399 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7077 /* 18402 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7078 /* 18406 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7079 /* 18411 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7080 /* 18415 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7081 /* 18419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7082 /* 18421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7083 /* 18424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7084 /* 18427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7085 /* 18433 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7086 /* 18435 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7087 /* 18438 */ GIR_RootConstrainSelectedInstOperands,
7088 /* 18439 */ // GIR_Coverage, 2465,
7089 /* 18439 */ GIR_EraseRootFromParent_Done,
7090 /* 18440 */ // Label 680: @18440
7091 /* 18440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 681*/ GIMT_Encode4(18521), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2466 //
7092 /* 18447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7093 /* 18451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7094 /* 18455 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7095 /* 18459 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7096 /* 18463 */ // MIs[1] Operand 1
7097 /* 18463 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7098 /* 18468 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7099 /* 18473 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7100 /* 18478 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7101 /* 18480 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7102 /* 18480 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7103 /* 18483 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7104 /* 18487 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7105 /* 18492 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7106 /* 18496 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7107 /* 18500 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7108 /* 18502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7109 /* 18505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7110 /* 18508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7111 /* 18514 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7112 /* 18516 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7113 /* 18519 */ GIR_RootConstrainSelectedInstOperands,
7114 /* 18520 */ // GIR_Coverage, 2466,
7115 /* 18520 */ GIR_EraseRootFromParent_Done,
7116 /* 18521 */ // Label 681: @18521
7117 /* 18521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 682*/ GIMT_Encode4(18602), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2471 //
7118 /* 18528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7119 /* 18532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7120 /* 18536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7121 /* 18540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7122 /* 18544 */ // MIs[1] Operand 1
7123 /* 18544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7124 /* 18549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7125 /* 18554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7126 /* 18559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7127 /* 18561 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7128 /* 18561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7129 /* 18564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7130 /* 18568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7131 /* 18573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7132 /* 18577 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7133 /* 18581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7134 /* 18583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7135 /* 18586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7136 /* 18589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7137 /* 18595 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7138 /* 18597 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7139 /* 18600 */ GIR_RootConstrainSelectedInstOperands,
7140 /* 18601 */ // GIR_Coverage, 2471,
7141 /* 18601 */ GIR_EraseRootFromParent_Done,
7142 /* 18602 */ // Label 682: @18602
7143 /* 18602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 683*/ GIMT_Encode4(18683), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2472 //
7144 /* 18609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7145 /* 18613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7146 /* 18617 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7147 /* 18621 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7148 /* 18625 */ // MIs[1] Operand 1
7149 /* 18625 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7150 /* 18630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7151 /* 18635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7152 /* 18640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7153 /* 18642 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7154 /* 18642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7155 /* 18645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7156 /* 18649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7157 /* 18654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7158 /* 18658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7159 /* 18662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7160 /* 18664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7161 /* 18667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7162 /* 18670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7163 /* 18676 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7164 /* 18678 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7165 /* 18681 */ GIR_RootConstrainSelectedInstOperands,
7166 /* 18682 */ // GIR_Coverage, 2472,
7167 /* 18682 */ GIR_EraseRootFromParent_Done,
7168 /* 18683 */ // Label 683: @18683
7169 /* 18683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 684*/ GIMT_Encode4(18758), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2645 //
7170 /* 18690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7171 /* 18694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7172 /* 18698 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7173 /* 18702 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7174 /* 18706 */ // MIs[1] Operand 1
7175 /* 18706 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7176 /* 18711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7177 /* 18716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7178 /* 18721 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7179 /* 18723 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7180 /* 18723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7181 /* 18726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7182 /* 18730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7183 /* 18735 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7184 /* 18739 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7185 /* 18743 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7186 /* 18745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7187 /* 18748 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7188 /* 18751 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7189 /* 18753 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7190 /* 18756 */ GIR_RootConstrainSelectedInstOperands,
7191 /* 18757 */ // GIR_Coverage, 2645,
7192 /* 18757 */ GIR_EraseRootFromParent_Done,
7193 /* 18758 */ // Label 684: @18758
7194 /* 18758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 685*/ GIMT_Encode4(18833), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2646 //
7195 /* 18765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7196 /* 18769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7197 /* 18773 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7198 /* 18777 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7199 /* 18781 */ // MIs[1] Operand 1
7200 /* 18781 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7201 /* 18786 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7202 /* 18791 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7203 /* 18796 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7204 /* 18798 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7205 /* 18798 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7206 /* 18801 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7207 /* 18805 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7208 /* 18810 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7209 /* 18814 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7210 /* 18818 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7211 /* 18820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7212 /* 18823 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7213 /* 18826 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7214 /* 18828 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7215 /* 18831 */ GIR_RootConstrainSelectedInstOperands,
7216 /* 18832 */ // GIR_Coverage, 2646,
7217 /* 18832 */ GIR_EraseRootFromParent_Done,
7218 /* 18833 */ // Label 685: @18833
7219 /* 18833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 686*/ GIMT_Encode4(18908), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2651 //
7220 /* 18840 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7221 /* 18844 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7222 /* 18848 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7223 /* 18852 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7224 /* 18856 */ // MIs[1] Operand 1
7225 /* 18856 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7226 /* 18861 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7227 /* 18866 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7228 /* 18871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7229 /* 18873 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7230 /* 18873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7231 /* 18876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7232 /* 18880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7233 /* 18885 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7234 /* 18889 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7235 /* 18893 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7236 /* 18895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7237 /* 18898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7238 /* 18901 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7239 /* 18903 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7240 /* 18906 */ GIR_RootConstrainSelectedInstOperands,
7241 /* 18907 */ // GIR_Coverage, 2651,
7242 /* 18907 */ GIR_EraseRootFromParent_Done,
7243 /* 18908 */ // Label 686: @18908
7244 /* 18908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 687*/ GIMT_Encode4(18983), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2652 //
7245 /* 18915 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7246 /* 18919 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7247 /* 18923 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7248 /* 18927 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7249 /* 18931 */ // MIs[1] Operand 1
7250 /* 18931 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7251 /* 18936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7252 /* 18941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7253 /* 18946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7254 /* 18948 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7255 /* 18948 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7256 /* 18951 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7257 /* 18955 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7258 /* 18960 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7259 /* 18964 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7260 /* 18968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7261 /* 18970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7262 /* 18973 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7263 /* 18976 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7264 /* 18978 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7265 /* 18981 */ GIR_RootConstrainSelectedInstOperands,
7266 /* 18982 */ // GIR_Coverage, 2652,
7267 /* 18982 */ GIR_EraseRootFromParent_Done,
7268 /* 18983 */ // Label 687: @18983
7269 /* 18983 */ GIM_Reject,
7270 /* 18984 */ // Label 591: @18984
7271 /* 18984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 688*/ GIMT_Encode4(19016), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1497 //
7272 /* 18991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7273 /* 18995 */ // MIs[0] dst
7274 /* 18995 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7275 /* 18998 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7276 /* 18998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
7277 /* 19001 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7278 /* 19003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7279 /* 19009 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7280 /* 19011 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7281 /* 19014 */ GIR_RootConstrainSelectedInstOperands,
7282 /* 19015 */ // GIR_Coverage, 1497,
7283 /* 19015 */ GIR_EraseRootFromParent_Done,
7284 /* 19016 */ // Label 688: @19016
7285 /* 19016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 689*/ GIMT_Encode4(19037), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2113 //
7286 /* 19023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7287 /* 19027 */ // MIs[0] targ16
7288 /* 19027 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7289 /* 19030 */ // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
7290 /* 19030 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
7291 /* 19035 */ GIR_RootConstrainSelectedInstOperands,
7292 /* 19036 */ // GIR_Coverage, 2113,
7293 /* 19036 */ GIR_Done,
7294 /* 19037 */ // Label 689: @19037
7295 /* 19037 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(19095),
7296 /* 19042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7297 /* 19046 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7298 /* 19049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 691*/ GIMT_Encode4(19074), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2473 //
7299 /* 19056 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, R0:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7300 /* 19056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
7301 /* 19059 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7302 /* 19061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7303 /* 19067 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7304 /* 19069 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7305 /* 19072 */ GIR_RootConstrainSelectedInstOperands,
7306 /* 19073 */ // GIR_Coverage, 2473,
7307 /* 19073 */ GIR_EraseRootFromParent_Done,
7308 /* 19074 */ // Label 691: @19074
7309 /* 19074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 692*/ GIMT_Encode4(19094), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2653 //
7310 /* 19081 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
7311 /* 19081 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
7312 /* 19086 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::R1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
7313 /* 19092 */ GIR_RootConstrainSelectedInstOperands,
7314 /* 19093 */ // GIR_Coverage, 2653,
7315 /* 19093 */ GIR_Done,
7316 /* 19094 */ // Label 692: @19094
7317 /* 19094 */ GIM_Reject,
7318 /* 19095 */ // Label 690: @19095
7319 /* 19095 */ GIM_Reject,
7320 /* 19096 */ // Label 589: @19096
7321 /* 19096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 693*/ GIMT_Encode4(19128), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1750 //
7322 /* 19103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7323 /* 19107 */ // MIs[0] dst
7324 /* 19107 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7325 /* 19110 */ // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, R0_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
7326 /* 19110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
7327 /* 19113 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7328 /* 19115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7329 /* 19121 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7330 /* 19123 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::R1*/0,
7331 /* 19126 */ GIR_RootConstrainSelectedInstOperands,
7332 /* 19127 */ // GIR_Coverage, 1750,
7333 /* 19127 */ GIR_EraseRootFromParent_Done,
7334 /* 19128 */ // Label 693: @19128
7335 /* 19128 */ GIM_Reject,
7336 /* 19129 */ // Label 590: @19129
7337 /* 19129 */ GIM_Reject,
7338 /* 19130 */ // Label 29: @19130
7339 /* 19130 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(19196),
7340 /* 19135 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
7341 /* 19139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 695*/ GIMT_Encode4(19157), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2098 //
7342 /* 19146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7343 /* 19150 */ // (brind CPU16Regs:{ *:[i32] }:$rs) => (JrcRx16 CPU16Regs:{ *:[i32] }:$rs)
7344 /* 19150 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::JrcRx16),
7345 /* 19155 */ GIR_RootConstrainSelectedInstOperands,
7346 /* 19156 */ // GIR_Coverage, 2098,
7347 /* 19156 */ GIR_Done,
7348 /* 19157 */ // Label 695: @19157
7349 /* 19157 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(19195),
7350 /* 19162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7351 /* 19166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 697*/ GIMT_Encode4(19180), GIMT_Encode2(GIFBS_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6), // Rule ID 123 //
7352 /* 19173 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndirectBranch GPR32Opnd:{ *:[i32] }:$rs)
7353 /* 19173 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranch),
7354 /* 19178 */ GIR_RootConstrainSelectedInstOperands,
7355 /* 19179 */ // GIR_Coverage, 123,
7356 /* 19179 */ GIR_Done,
7357 /* 19180 */ // Label 697: @19180
7358 /* 19180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 698*/ GIMT_Encode4(19194), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6_UseIndirectJumpsHazard), // Rule ID 146 //
7359 /* 19187 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndirectHazardBranch GPR32Opnd:{ *:[i32] }:$rs)
7360 /* 19187 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectHazardBranch),
7361 /* 19192 */ GIR_RootConstrainSelectedInstOperands,
7362 /* 19193 */ // GIR_Coverage, 146,
7363 /* 19193 */ GIR_Done,
7364 /* 19194 */ // Label 698: @19194
7365 /* 19194 */ GIM_Reject,
7366 /* 19195 */ // Label 696: @19195
7367 /* 19195 */ GIM_Reject,
7368 /* 19196 */ // Label 694: @19196
7369 /* 19196 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(19238),
7370 /* 19201 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
7371 /* 19205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7372 /* 19209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 700*/ GIMT_Encode4(19223), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6), // Rule ID 325 //
7373 /* 19216 */ // (brind GPR64Opnd:{ *:[i64] }:$rs) => (PseudoIndirectBranch64 GPR64Opnd:{ *:[i64] }:$rs)
7374 /* 19216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranch64),
7375 /* 19221 */ GIR_RootConstrainSelectedInstOperands,
7376 /* 19222 */ // GIR_Coverage, 325,
7377 /* 19222 */ GIR_Done,
7378 /* 19223 */ // Label 700: @19223
7379 /* 19223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 701*/ GIMT_Encode4(19237), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsPTR64bit_NotInMicroMips_NotInMips16Mode_NotMips32r6_NotMips64r6_UseIndirectJumpsHazard), // Rule ID 327 //
7380 /* 19230 */ // (brind GPR64Opnd:{ *:[i64] }:$rs) => (PseudoIndirectHazardBranch64 GPR64Opnd:{ *:[i64] }:$rs)
7381 /* 19230 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectHazardBranch64),
7382 /* 19235 */ GIR_RootConstrainSelectedInstOperands,
7383 /* 19236 */ // GIR_Coverage, 327,
7384 /* 19236 */ GIR_Done,
7385 /* 19237 */ // Label 701: @19237
7386 /* 19237 */ GIM_Reject,
7387 /* 19238 */ // Label 699: @19238
7388 /* 19238 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(19280),
7389 /* 19243 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
7390 /* 19247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7391 /* 19251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 703*/ GIMT_Encode4(19265), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode), // Rule ID 399 //
7392 /* 19258 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndirectBranchR6 GPR32Opnd:{ *:[i32] }:$rs)
7393 /* 19258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranchR6),
7394 /* 19263 */ GIR_RootConstrainSelectedInstOperands,
7395 /* 19264 */ // GIR_Coverage, 399,
7396 /* 19264 */ GIR_Done,
7397 /* 19265 */ // Label 703: @19265
7398 /* 19265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 704*/ GIMT_Encode4(19279), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_NotInMips16Mode_UseIndirectJumpsHazard), // Rule ID 401 //
7399 /* 19272 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndrectHazardBranchR6 GPR32Opnd:{ *:[i32] }:$rs)
7400 /* 19272 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndrectHazardBranchR6),
7401 /* 19277 */ GIR_RootConstrainSelectedInstOperands,
7402 /* 19278 */ // GIR_Coverage, 401,
7403 /* 19278 */ GIR_Done,
7404 /* 19279 */ // Label 704: @19279
7405 /* 19279 */ GIM_Reject,
7406 /* 19280 */ // Label 702: @19280
7407 /* 19280 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(19322),
7408 /* 19285 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
7409 /* 19289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7410 /* 19293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 706*/ GIMT_Encode4(19307), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NoIndirectJumpGuards_NotInMicroMips_NotInMips16Mode), // Rule ID 412 //
7411 /* 19300 */ // (brind GPR64Opnd:{ *:[i64] }:$rs) => (PseudoIndirectBranch64R6 GPR64Opnd:{ *:[i64] }:$rs)
7412 /* 19300 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranch64R6),
7413 /* 19305 */ GIR_RootConstrainSelectedInstOperands,
7414 /* 19306 */ // GIR_Coverage, 412,
7415 /* 19306 */ GIR_Done,
7416 /* 19307 */ // Label 706: @19307
7417 /* 19307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 707*/ GIMT_Encode4(19321), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_NotInMips16Mode_UseIndirectJumpsHazard), // Rule ID 414 //
7418 /* 19314 */ // (brind GPR64Opnd:{ *:[i64] }:$rs) => (PseudoIndrectHazardBranch64R6 GPR64Opnd:{ *:[i64] }:$rs)
7419 /* 19314 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndrectHazardBranch64R6),
7420 /* 19319 */ GIR_RootConstrainSelectedInstOperands,
7421 /* 19320 */ // GIR_Coverage, 414,
7422 /* 19320 */ GIR_Done,
7423 /* 19321 */ // Label 707: @19321
7424 /* 19321 */ GIM_Reject,
7425 /* 19322 */ // Label 705: @19322
7426 /* 19322 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(19364),
7427 /* 19327 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
7428 /* 19331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7429 /* 19335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 709*/ GIMT_Encode4(19349), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1206 //
7430 /* 19342 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndirectBranch_MM GPR32Opnd:{ *:[i32] }:$rs)
7431 /* 19342 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranch_MM),
7432 /* 19347 */ GIR_RootConstrainSelectedInstOperands,
7433 /* 19348 */ // GIR_Coverage, 1206,
7434 /* 19348 */ GIR_Done,
7435 /* 19349 */ // Label 709: @19349
7436 /* 19349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 710*/ GIMT_Encode4(19363), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1300 //
7437 /* 19356 */ // (brind GPR32Opnd:{ *:[i32] }:$rs) => (PseudoIndirectBranch_MMR6 GPR32Opnd:{ *:[i32] }:$rs)
7438 /* 19356 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoIndirectBranch_MMR6),
7439 /* 19361 */ GIR_RootConstrainSelectedInstOperands,
7440 /* 19362 */ // GIR_Coverage, 1300,
7441 /* 19362 */ GIR_Done,
7442 /* 19363 */ // Label 710: @19363
7443 /* 19363 */ GIM_Reject,
7444 /* 19364 */ // Label 708: @19364
7445 /* 19364 */ GIM_Reject,
7446 /* 19365 */ // Label 30: @19365
7447 /* 19365 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(21299),
7448 /* 19370 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7449 /* 19373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 712*/ GIMT_Encode4(19419), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 491 //
7450 /* 19380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7451 /* 19385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7452 /* 19388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7453 /* 19391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7454 /* 19395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7455 /* 19399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7456 /* 19403 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7457 /* 19407 */ // MIs[1] Operand 1
7458 /* 19407 */ // No operand predicates
7459 /* 19407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7460 /* 19409 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8524:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7461 /* 19409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
7462 /* 19412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7463 /* 19414 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7464 /* 19417 */ GIR_RootConstrainSelectedInstOperands,
7465 /* 19418 */ // GIR_Coverage, 491,
7466 /* 19418 */ GIR_EraseRootFromParent_Done,
7467 /* 19419 */ // Label 712: @19419
7468 /* 19419 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(19502),
7469 /* 19424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7470 /* 19429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7471 /* 19432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7472 /* 19435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7473 /* 19439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 714*/ GIMT_Encode4(19470), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 492 //
7474 /* 19446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7475 /* 19450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7476 /* 19454 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7477 /* 19458 */ // MIs[1] Operand 1
7478 /* 19458 */ // No operand predicates
7479 /* 19458 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7480 /* 19460 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8523:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7481 /* 19460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
7482 /* 19463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7483 /* 19465 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7484 /* 19468 */ GIR_RootConstrainSelectedInstOperands,
7485 /* 19469 */ // GIR_Coverage, 492,
7486 /* 19469 */ GIR_EraseRootFromParent_Done,
7487 /* 19470 */ // Label 714: @19470
7488 /* 19470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 715*/ GIMT_Encode4(19501), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1366 //
7489 /* 19477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7490 /* 19481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7491 /* 19485 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7492 /* 19489 */ // MIs[1] Operand 1
7493 /* 19489 */ // No operand predicates
7494 /* 19489 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7495 /* 19491 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8523:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7496 /* 19491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
7497 /* 19494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7498 /* 19496 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7499 /* 19499 */ GIR_RootConstrainSelectedInstOperands,
7500 /* 19500 */ // GIR_Coverage, 1366,
7501 /* 19500 */ GIR_EraseRootFromParent_Done,
7502 /* 19501 */ // Label 715: @19501
7503 /* 19501 */ GIM_Reject,
7504 /* 19502 */ // Label 713: @19502
7505 /* 19502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(19548), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1367 //
7506 /* 19509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7507 /* 19514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7508 /* 19517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7509 /* 19520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7510 /* 19524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7511 /* 19528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7512 /* 19532 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7513 /* 19536 */ // MIs[1] Operand 1
7514 /* 19536 */ // No operand predicates
7515 /* 19536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7516 /* 19538 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8524:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7517 /* 19538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
7518 /* 19541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7519 /* 19543 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7520 /* 19546 */ GIR_RootConstrainSelectedInstOperands,
7521 /* 19547 */ // GIR_Coverage, 1367,
7522 /* 19547 */ GIR_EraseRootFromParent_Done,
7523 /* 19548 */ // Label 716: @19548
7524 /* 19548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(19583), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 425 //
7525 /* 19555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7526 /* 19560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7527 /* 19563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7528 /* 19566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7529 /* 19570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7530 /* 19574 */ // (intrinsic_wo_chain:{ *:[i32] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7531 /* 19574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
7532 /* 19577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7533 /* 19579 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7534 /* 19581 */ GIR_RootConstrainSelectedInstOperands,
7535 /* 19582 */ // GIR_Coverage, 425,
7536 /* 19582 */ GIR_EraseRootFromParent_Done,
7537 /* 19583 */ // Label 717: @19583
7538 /* 19583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 718*/ GIMT_Encode4(19618), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 432 //
7539 /* 19590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7540 /* 19595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7541 /* 19598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7542 /* 19601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7543 /* 19605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7544 /* 19609 */ // (intrinsic_wo_chain:{ *:[i32] } 8503:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7545 /* 19609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7546 /* 19612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7547 /* 19614 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7548 /* 19616 */ GIR_RootConstrainSelectedInstOperands,
7549 /* 19617 */ // GIR_Coverage, 432,
7550 /* 19617 */ GIR_EraseRootFromParent_Done,
7551 /* 19618 */ // Label 718: @19618
7552 /* 19618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 719*/ GIMT_Encode4(19653), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 433 //
7553 /* 19625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7554 /* 19630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7555 /* 19633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7556 /* 19636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7557 /* 19640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7558 /* 19644 */ // (intrinsic_wo_chain:{ *:[i32] } 8504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7559 /* 19644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7560 /* 19647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7561 /* 19649 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7562 /* 19651 */ GIR_RootConstrainSelectedInstOperands,
7563 /* 19652 */ // GIR_Coverage, 433,
7564 /* 19652 */ GIR_EraseRootFromParent_Done,
7565 /* 19653 */ // Label 719: @19653
7566 /* 19653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 720*/ GIMT_Encode4(19688), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 434 //
7567 /* 19660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7568 /* 19665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7569 /* 19668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7570 /* 19671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7571 /* 19675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7572 /* 19679 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8505:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7573 /* 19679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7574 /* 19682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7575 /* 19684 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7576 /* 19686 */ GIR_RootConstrainSelectedInstOperands,
7577 /* 19687 */ // GIR_Coverage, 434,
7578 /* 19687 */ GIR_EraseRootFromParent_Done,
7579 /* 19688 */ // Label 720: @19688
7580 /* 19688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 721*/ GIMT_Encode4(19723), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 435 //
7581 /* 19695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7582 /* 19700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7583 /* 19703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7584 /* 19706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7585 /* 19710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7586 /* 19714 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8507:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7587 /* 19714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7588 /* 19717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7589 /* 19719 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7590 /* 19721 */ GIR_RootConstrainSelectedInstOperands,
7591 /* 19722 */ // GIR_Coverage, 435,
7592 /* 19722 */ GIR_EraseRootFromParent_Done,
7593 /* 19723 */ // Label 721: @19723
7594 /* 19723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 722*/ GIMT_Encode4(19758), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 436 //
7595 /* 19730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7596 /* 19735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7597 /* 19738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7598 /* 19741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7599 /* 19745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7600 /* 19749 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7601 /* 19749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7602 /* 19752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7603 /* 19754 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7604 /* 19756 */ GIR_RootConstrainSelectedInstOperands,
7605 /* 19757 */ // GIR_Coverage, 436,
7606 /* 19757 */ GIR_EraseRootFromParent_Done,
7607 /* 19758 */ // Label 722: @19758
7608 /* 19758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 723*/ GIMT_Encode4(19793), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 437 //
7609 /* 19765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7610 /* 19770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7611 /* 19773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7612 /* 19776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7613 /* 19780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7614 /* 19784 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8508:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7615 /* 19784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
7616 /* 19787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7617 /* 19789 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7618 /* 19791 */ GIR_RootConstrainSelectedInstOperands,
7619 /* 19792 */ // GIR_Coverage, 437,
7620 /* 19792 */ GIR_EraseRootFromParent_Done,
7621 /* 19793 */ // Label 723: @19793
7622 /* 19793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 724*/ GIMT_Encode4(19828), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 438 //
7623 /* 19800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7624 /* 19805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7625 /* 19808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7626 /* 19811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7627 /* 19815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7628 /* 19819 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8509:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7629 /* 19819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
7630 /* 19822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7631 /* 19824 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7632 /* 19826 */ GIR_RootConstrainSelectedInstOperands,
7633 /* 19827 */ // GIR_Coverage, 438,
7634 /* 19827 */ GIR_EraseRootFromParent_Done,
7635 /* 19828 */ // Label 724: @19828
7636 /* 19828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 725*/ GIMT_Encode4(19863), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 439 //
7637 /* 19835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7638 /* 19840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7639 /* 19843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7640 /* 19846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7641 /* 19850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7642 /* 19854 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8511:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7643 /* 19854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
7644 /* 19857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7645 /* 19859 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7646 /* 19861 */ GIR_RootConstrainSelectedInstOperands,
7647 /* 19862 */ // GIR_Coverage, 439,
7648 /* 19862 */ GIR_EraseRootFromParent_Done,
7649 /* 19863 */ // Label 725: @19863
7650 /* 19863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 726*/ GIMT_Encode4(19898), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 440 //
7651 /* 19870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7652 /* 19875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7653 /* 19878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7654 /* 19881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7655 /* 19885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7656 /* 19889 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8510:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7657 /* 19889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
7658 /* 19892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7659 /* 19894 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7660 /* 19896 */ GIR_RootConstrainSelectedInstOperands,
7661 /* 19897 */ // GIR_Coverage, 440,
7662 /* 19897 */ GIR_EraseRootFromParent_Done,
7663 /* 19898 */ // Label 726: @19898
7664 /* 19898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 727*/ GIMT_Encode4(19933), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 441 //
7665 /* 19905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7666 /* 19910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7667 /* 19913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7668 /* 19916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7669 /* 19920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7670 /* 19924 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7671 /* 19924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
7672 /* 19927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7673 /* 19929 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7674 /* 19931 */ GIR_RootConstrainSelectedInstOperands,
7675 /* 19932 */ // GIR_Coverage, 441,
7676 /* 19932 */ GIR_EraseRootFromParent_Done,
7677 /* 19933 */ // Label 727: @19933
7678 /* 19933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 728*/ GIMT_Encode4(19968), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 489 //
7679 /* 19940 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
7680 /* 19945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7681 /* 19948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7682 /* 19951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7683 /* 19955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7684 /* 19959 */ // (intrinsic_wo_chain:{ *:[i32] } 8077:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
7685 /* 19959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
7686 /* 19962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7687 /* 19964 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7688 /* 19966 */ GIR_RootConstrainSelectedInstOperands,
7689 /* 19967 */ // GIR_Coverage, 489,
7690 /* 19967 */ GIR_EraseRootFromParent_Done,
7691 /* 19968 */ // Label 728: @19968
7692 /* 19968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 729*/ GIMT_Encode4(20003), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 493 //
7693 /* 19975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7694 /* 19980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7695 /* 19983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7696 /* 19986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7697 /* 19990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7698 /* 19994 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8524:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
7699 /* 19994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
7700 /* 19997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7701 /* 19999 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7702 /* 20001 */ GIR_RootConstrainSelectedInstOperands,
7703 /* 20002 */ // GIR_Coverage, 493,
7704 /* 20002 */ GIR_EraseRootFromParent_Done,
7705 /* 20003 */ // Label 729: @20003
7706 /* 20003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 730*/ GIMT_Encode4(20038), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 494 //
7707 /* 20010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7708 /* 20015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7709 /* 20018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7710 /* 20021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7711 /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7712 /* 20029 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
7713 /* 20029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
7714 /* 20032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7715 /* 20034 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7716 /* 20036 */ GIR_RootConstrainSelectedInstOperands,
7717 /* 20037 */ // GIR_Coverage, 494,
7718 /* 20037 */ GIR_EraseRootFromParent_Done,
7719 /* 20038 */ // Label 730: @20038
7720 /* 20038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 731*/ GIMT_Encode4(20073), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 743 //
7721 /* 20045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
7722 /* 20050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7723 /* 20053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7724 /* 20056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7725 /* 20060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7726 /* 20064 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8229:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7727 /* 20064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
7728 /* 20067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7729 /* 20069 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7730 /* 20071 */ GIR_RootConstrainSelectedInstOperands,
7731 /* 20072 */ // GIR_Coverage, 743,
7732 /* 20072 */ GIR_EraseRootFromParent_Done,
7733 /* 20073 */ // Label 731: @20073
7734 /* 20073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(20108), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 744 //
7735 /* 20080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
7736 /* 20085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7737 /* 20088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7738 /* 20091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7739 /* 20095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7740 /* 20099 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8228:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7741 /* 20099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
7742 /* 20102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7743 /* 20104 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7744 /* 20106 */ GIR_RootConstrainSelectedInstOperands,
7745 /* 20107 */ // GIR_Coverage, 744,
7746 /* 20107 */ GIR_EraseRootFromParent_Done,
7747 /* 20108 */ // Label 732: @20108
7748 /* 20108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 733*/ GIMT_Encode4(20143), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 767 //
7749 /* 20115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
7750 /* 20120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7751 /* 20123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7752 /* 20126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7753 /* 20130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7754 /* 20134 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8255:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7755 /* 20134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
7756 /* 20137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7757 /* 20139 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7758 /* 20141 */ GIR_RootConstrainSelectedInstOperands,
7759 /* 20142 */ // GIR_Coverage, 767,
7760 /* 20142 */ GIR_EraseRootFromParent_Done,
7761 /* 20143 */ // Label 733: @20143
7762 /* 20143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 734*/ GIMT_Encode4(20178), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 768 //
7763 /* 20150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
7764 /* 20155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7765 /* 20158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7766 /* 20161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7767 /* 20165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7768 /* 20169 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8254:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7769 /* 20169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
7770 /* 20172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7771 /* 20174 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7772 /* 20176 */ GIR_RootConstrainSelectedInstOperands,
7773 /* 20177 */ // GIR_Coverage, 768,
7774 /* 20177 */ GIR_EraseRootFromParent_Done,
7775 /* 20178 */ // Label 734: @20178
7776 /* 20178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 735*/ GIMT_Encode4(20213), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 769 //
7777 /* 20185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
7778 /* 20190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7779 /* 20193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7780 /* 20196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7781 /* 20200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7782 /* 20204 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8257:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7783 /* 20204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
7784 /* 20207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7785 /* 20209 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7786 /* 20211 */ GIR_RootConstrainSelectedInstOperands,
7787 /* 20212 */ // GIR_Coverage, 769,
7788 /* 20212 */ GIR_EraseRootFromParent_Done,
7789 /* 20213 */ // Label 735: @20213
7790 /* 20213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 736*/ GIMT_Encode4(20248), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 770 //
7791 /* 20220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
7792 /* 20225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7793 /* 20228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7794 /* 20231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7795 /* 20235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7796 /* 20239 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8256:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7797 /* 20239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
7798 /* 20242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7799 /* 20244 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7800 /* 20246 */ GIR_RootConstrainSelectedInstOperands,
7801 /* 20247 */ // GIR_Coverage, 770,
7802 /* 20247 */ GIR_EraseRootFromParent_Done,
7803 /* 20248 */ // Label 736: @20248
7804 /* 20248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 737*/ GIMT_Encode4(20283), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 775 //
7805 /* 20255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
7806 /* 20260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7807 /* 20263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7808 /* 20266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7809 /* 20270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7810 /* 20274 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8263:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7811 /* 20274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
7812 /* 20277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7813 /* 20279 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7814 /* 20281 */ GIR_RootConstrainSelectedInstOperands,
7815 /* 20282 */ // GIR_Coverage, 775,
7816 /* 20282 */ GIR_EraseRootFromParent_Done,
7817 /* 20283 */ // Label 737: @20283
7818 /* 20283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 738*/ GIMT_Encode4(20318), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 776 //
7819 /* 20290 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
7820 /* 20295 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7821 /* 20298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7822 /* 20301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7823 /* 20305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7824 /* 20309 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7825 /* 20309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
7826 /* 20312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7827 /* 20314 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7828 /* 20316 */ GIR_RootConstrainSelectedInstOperands,
7829 /* 20317 */ // GIR_Coverage, 776,
7830 /* 20317 */ GIR_EraseRootFromParent_Done,
7831 /* 20318 */ // Label 738: @20318
7832 /* 20318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 739*/ GIMT_Encode4(20353), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 777 //
7833 /* 20325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
7834 /* 20330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7835 /* 20333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7836 /* 20336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7837 /* 20340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7838 /* 20344 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8265:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7839 /* 20344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
7840 /* 20347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7841 /* 20349 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7842 /* 20351 */ GIR_RootConstrainSelectedInstOperands,
7843 /* 20352 */ // GIR_Coverage, 777,
7844 /* 20352 */ GIR_EraseRootFromParent_Done,
7845 /* 20353 */ // Label 739: @20353
7846 /* 20353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(20388), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 778 //
7847 /* 20360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
7848 /* 20365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7849 /* 20368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7850 /* 20371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7851 /* 20375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7852 /* 20379 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7853 /* 20379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
7854 /* 20382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7855 /* 20384 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7856 /* 20386 */ GIR_RootConstrainSelectedInstOperands,
7857 /* 20387 */ // GIR_Coverage, 778,
7858 /* 20387 */ GIR_EraseRootFromParent_Done,
7859 /* 20388 */ // Label 740: @20388
7860 /* 20388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 741*/ GIMT_Encode4(20423), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 803 //
7861 /* 20395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
7862 /* 20400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7863 /* 20403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7864 /* 20406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7865 /* 20410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7866 /* 20414 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8287:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7867 /* 20414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
7868 /* 20417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7869 /* 20419 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7870 /* 20421 */ GIR_RootConstrainSelectedInstOperands,
7871 /* 20422 */ // GIR_Coverage, 803,
7872 /* 20422 */ GIR_EraseRootFromParent_Done,
7873 /* 20423 */ // Label 741: @20423
7874 /* 20423 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 742*/ GIMT_Encode4(20458), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 804 //
7875 /* 20430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
7876 /* 20435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7877 /* 20438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7878 /* 20441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7879 /* 20445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7880 /* 20449 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7881 /* 20449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
7882 /* 20452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7883 /* 20454 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7884 /* 20456 */ GIR_RootConstrainSelectedInstOperands,
7885 /* 20457 */ // GIR_Coverage, 804,
7886 /* 20457 */ GIR_EraseRootFromParent_Done,
7887 /* 20458 */ // Label 742: @20458
7888 /* 20458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(20493), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 805 //
7889 /* 20465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
7890 /* 20470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7891 /* 20473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7892 /* 20476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7893 /* 20480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7894 /* 20484 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8291:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7895 /* 20484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
7896 /* 20487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7897 /* 20489 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7898 /* 20491 */ GIR_RootConstrainSelectedInstOperands,
7899 /* 20492 */ // GIR_Coverage, 805,
7900 /* 20492 */ GIR_EraseRootFromParent_Done,
7901 /* 20493 */ // Label 743: @20493
7902 /* 20493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 744*/ GIMT_Encode4(20528), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 806 //
7903 /* 20500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
7904 /* 20505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7905 /* 20508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7906 /* 20511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7907 /* 20515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7908 /* 20519 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8290:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7909 /* 20519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
7910 /* 20522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7911 /* 20524 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7912 /* 20526 */ GIR_RootConstrainSelectedInstOperands,
7913 /* 20527 */ // GIR_Coverage, 806,
7914 /* 20527 */ GIR_EraseRootFromParent_Done,
7915 /* 20528 */ // Label 744: @20528
7916 /* 20528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(20563), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 833 //
7917 /* 20535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
7918 /* 20540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7919 /* 20543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7920 /* 20546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7921 /* 20550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7922 /* 20554 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8319:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7923 /* 20554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
7924 /* 20557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7925 /* 20559 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7926 /* 20561 */ GIR_RootConstrainSelectedInstOperands,
7927 /* 20562 */ // GIR_Coverage, 833,
7928 /* 20562 */ GIR_EraseRootFromParent_Done,
7929 /* 20563 */ // Label 745: @20563
7930 /* 20563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 746*/ GIMT_Encode4(20598), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 834 //
7931 /* 20570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
7932 /* 20575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7933 /* 20578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7934 /* 20581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7935 /* 20585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7936 /* 20589 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8318:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7937 /* 20589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
7938 /* 20592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7939 /* 20594 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7940 /* 20596 */ GIR_RootConstrainSelectedInstOperands,
7941 /* 20597 */ // GIR_Coverage, 834,
7942 /* 20597 */ GIR_EraseRootFromParent_Done,
7943 /* 20598 */ // Label 746: @20598
7944 /* 20598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 747*/ GIMT_Encode4(20633), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 835 //
7945 /* 20605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
7946 /* 20610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7947 /* 20613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7948 /* 20616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7949 /* 20620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7950 /* 20624 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8321:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7951 /* 20624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
7952 /* 20627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7953 /* 20629 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7954 /* 20631 */ GIR_RootConstrainSelectedInstOperands,
7955 /* 20632 */ // GIR_Coverage, 835,
7956 /* 20632 */ GIR_EraseRootFromParent_Done,
7957 /* 20633 */ // Label 747: @20633
7958 /* 20633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(20668), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 836 //
7959 /* 20640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
7960 /* 20645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7961 /* 20648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7962 /* 20651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7963 /* 20655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7964 /* 20659 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8320:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7965 /* 20659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
7966 /* 20662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7967 /* 20664 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7968 /* 20666 */ GIR_RootConstrainSelectedInstOperands,
7969 /* 20667 */ // GIR_Coverage, 836,
7970 /* 20667 */ GIR_EraseRootFromParent_Done,
7971 /* 20668 */ // Label 748: @20668
7972 /* 20668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(20703), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 975 //
7973 /* 20675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
7974 /* 20680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7975 /* 20683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7976 /* 20686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7977 /* 20690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7978 /* 20694 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8476:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
7979 /* 20694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
7980 /* 20697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7981 /* 20699 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7982 /* 20701 */ GIR_RootConstrainSelectedInstOperands,
7983 /* 20702 */ // GIR_Coverage, 975,
7984 /* 20702 */ GIR_EraseRootFromParent_Done,
7985 /* 20703 */ // Label 749: @20703
7986 /* 20703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(20738), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 976 //
7987 /* 20710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
7988 /* 20715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7989 /* 20718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7990 /* 20721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7991 /* 20725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7992 /* 20729 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8478:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7993 /* 20729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
7994 /* 20732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7995 /* 20734 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7996 /* 20736 */ GIR_RootConstrainSelectedInstOperands,
7997 /* 20737 */ // GIR_Coverage, 976,
7998 /* 20737 */ GIR_EraseRootFromParent_Done,
7999 /* 20738 */ // Label 750: @20738
8000 /* 20738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(20773), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 977 //
8001 /* 20745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
8002 /* 20750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8003 /* 20753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8004 /* 20756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8005 /* 20760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8006 /* 20764 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8479:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8007 /* 20764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
8008 /* 20767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8009 /* 20769 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8010 /* 20771 */ GIR_RootConstrainSelectedInstOperands,
8011 /* 20772 */ // GIR_Coverage, 977,
8012 /* 20772 */ GIR_EraseRootFromParent_Done,
8013 /* 20773 */ // Label 751: @20773
8014 /* 20773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(20808), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 978 //
8015 /* 20780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
8016 /* 20785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8017 /* 20788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8018 /* 20791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8019 /* 20795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8020 /* 20799 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8477:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
8021 /* 20799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
8022 /* 20802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8023 /* 20804 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8024 /* 20806 */ GIR_RootConstrainSelectedInstOperands,
8025 /* 20807 */ // GIR_Coverage, 978,
8026 /* 20807 */ GIR_EraseRootFromParent_Done,
8027 /* 20808 */ // Label 752: @20808
8028 /* 20808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(20843), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1329 //
8029 /* 20815 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
8030 /* 20820 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8031 /* 20823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8032 /* 20826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8033 /* 20830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8034 /* 20834 */ // (intrinsic_wo_chain:{ *:[i32] } 8503:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8035 /* 20834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
8036 /* 20837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8037 /* 20839 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8038 /* 20841 */ GIR_RootConstrainSelectedInstOperands,
8039 /* 20842 */ // GIR_Coverage, 1329,
8040 /* 20842 */ GIR_EraseRootFromParent_Done,
8041 /* 20843 */ // Label 753: @20843
8042 /* 20843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(20878), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1330 //
8043 /* 20850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
8044 /* 20855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8045 /* 20858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8046 /* 20861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8047 /* 20865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8048 /* 20869 */ // (intrinsic_wo_chain:{ *:[i32] } 8504:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8049 /* 20869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
8050 /* 20872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8051 /* 20874 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8052 /* 20876 */ GIR_RootConstrainSelectedInstOperands,
8053 /* 20877 */ // GIR_Coverage, 1330,
8054 /* 20877 */ GIR_EraseRootFromParent_Done,
8055 /* 20878 */ // Label 754: @20878
8056 /* 20878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 755*/ GIMT_Encode4(20913), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1331 //
8057 /* 20885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
8058 /* 20890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8059 /* 20893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8060 /* 20896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8061 /* 20900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8062 /* 20904 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8505:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8063 /* 20904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
8064 /* 20907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8065 /* 20909 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8066 /* 20911 */ GIR_RootConstrainSelectedInstOperands,
8067 /* 20912 */ // GIR_Coverage, 1331,
8068 /* 20912 */ GIR_EraseRootFromParent_Done,
8069 /* 20913 */ // Label 755: @20913
8070 /* 20913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 756*/ GIMT_Encode4(20948), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1332 //
8071 /* 20920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
8072 /* 20925 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8073 /* 20928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8074 /* 20931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8075 /* 20935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8076 /* 20939 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8506:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8077 /* 20939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
8078 /* 20942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8079 /* 20944 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8080 /* 20946 */ GIR_RootConstrainSelectedInstOperands,
8081 /* 20947 */ // GIR_Coverage, 1332,
8082 /* 20947 */ GIR_EraseRootFromParent_Done,
8083 /* 20948 */ // Label 756: @20948
8084 /* 20948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(20983), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1333 //
8085 /* 20955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
8086 /* 20960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8087 /* 20963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8088 /* 20966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8089 /* 20970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8090 /* 20974 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8507:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8091 /* 20974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
8092 /* 20977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8093 /* 20979 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8094 /* 20981 */ GIR_RootConstrainSelectedInstOperands,
8095 /* 20982 */ // GIR_Coverage, 1333,
8096 /* 20982 */ GIR_EraseRootFromParent_Done,
8097 /* 20983 */ // Label 757: @20983
8098 /* 20983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(21018), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1334 //
8099 /* 20990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
8100 /* 20995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8101 /* 20998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8102 /* 21001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8103 /* 21005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8104 /* 21009 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8508:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8105 /* 21009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
8106 /* 21012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8107 /* 21014 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8108 /* 21016 */ GIR_RootConstrainSelectedInstOperands,
8109 /* 21017 */ // GIR_Coverage, 1334,
8110 /* 21017 */ GIR_EraseRootFromParent_Done,
8111 /* 21018 */ // Label 758: @21018
8112 /* 21018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(21053), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1335 //
8113 /* 21025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
8114 /* 21030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8115 /* 21033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8116 /* 21036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8117 /* 21040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8118 /* 21044 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8509:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8119 /* 21044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
8120 /* 21047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8121 /* 21049 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8122 /* 21051 */ GIR_RootConstrainSelectedInstOperands,
8123 /* 21052 */ // GIR_Coverage, 1335,
8124 /* 21052 */ GIR_EraseRootFromParent_Done,
8125 /* 21053 */ // Label 759: @21053
8126 /* 21053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(21088), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1336 //
8127 /* 21060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
8128 /* 21065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8129 /* 21068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8130 /* 21071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8131 /* 21075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8132 /* 21079 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8510:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8133 /* 21079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
8134 /* 21082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8135 /* 21084 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8136 /* 21086 */ GIR_RootConstrainSelectedInstOperands,
8137 /* 21087 */ // GIR_Coverage, 1336,
8138 /* 21087 */ GIR_EraseRootFromParent_Done,
8139 /* 21088 */ // Label 760: @21088
8140 /* 21088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(21123), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1337 //
8141 /* 21095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
8142 /* 21100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8143 /* 21103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8144 /* 21106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8145 /* 21110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8146 /* 21114 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8511:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8147 /* 21114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
8148 /* 21117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8149 /* 21119 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8150 /* 21121 */ GIR_RootConstrainSelectedInstOperands,
8151 /* 21122 */ // GIR_Coverage, 1337,
8152 /* 21122 */ GIR_EraseRootFromParent_Done,
8153 /* 21123 */ // Label 761: @21123
8154 /* 21123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(21158), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1338 //
8155 /* 21130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
8156 /* 21135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8157 /* 21138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8158 /* 21141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8159 /* 21145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8160 /* 21149 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8161 /* 21149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
8162 /* 21152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8163 /* 21154 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8164 /* 21156 */ GIR_RootConstrainSelectedInstOperands,
8165 /* 21157 */ // GIR_Coverage, 1338,
8166 /* 21157 */ GIR_EraseRootFromParent_Done,
8167 /* 21158 */ // Label 762: @21158
8168 /* 21158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(21193), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1364 //
8169 /* 21165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
8170 /* 21170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8171 /* 21173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8172 /* 21176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8173 /* 21180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8174 /* 21184 */ // (intrinsic_wo_chain:{ *:[i32] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
8175 /* 21184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
8176 /* 21187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8177 /* 21189 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8178 /* 21191 */ GIR_RootConstrainSelectedInstOperands,
8179 /* 21192 */ // GIR_Coverage, 1364,
8180 /* 21192 */ GIR_EraseRootFromParent_Done,
8181 /* 21193 */ // Label 763: @21193
8182 /* 21193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 764*/ GIMT_Encode4(21228), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1368 //
8183 /* 21200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8184 /* 21205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8185 /* 21208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8186 /* 21211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8187 /* 21215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8188 /* 21219 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
8189 /* 21219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
8190 /* 21222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8191 /* 21224 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8192 /* 21226 */ GIR_RootConstrainSelectedInstOperands,
8193 /* 21227 */ // GIR_Coverage, 1368,
8194 /* 21227 */ GIR_EraseRootFromParent_Done,
8195 /* 21228 */ // Label 764: @21228
8196 /* 21228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 765*/ GIMT_Encode4(21263), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1369 //
8197 /* 21235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8198 /* 21240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8199 /* 21243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8200 /* 21246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8201 /* 21250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8202 /* 21254 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8524:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
8203 /* 21254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
8204 /* 21257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8205 /* 21259 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8206 /* 21261 */ GIR_RootConstrainSelectedInstOperands,
8207 /* 21262 */ // GIR_Coverage, 1369,
8208 /* 21262 */ GIR_EraseRootFromParent_Done,
8209 /* 21263 */ // Label 765: @21263
8210 /* 21263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 766*/ GIMT_Encode4(21298), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1379 //
8211 /* 21270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8212 /* 21275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8213 /* 21278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8214 /* 21281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8215 /* 21285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8216 /* 21289 */ // (intrinsic_wo_chain:{ *:[i32] } 8077:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
8217 /* 21289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
8218 /* 21292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8219 /* 21294 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8220 /* 21296 */ GIR_RootConstrainSelectedInstOperands,
8221 /* 21297 */ // GIR_Coverage, 1379,
8222 /* 21297 */ GIR_EraseRootFromParent_Done,
8223 /* 21298 */ // Label 766: @21298
8224 /* 21298 */ GIM_Reject,
8225 /* 21299 */ // Label 711: @21299
8226 /* 21299 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(30838),
8227 /* 21304 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
8228 /* 21307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 768*/ GIMT_Encode4(21352), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1005 //
8229 /* 21314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
8230 /* 21319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8231 /* 21322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8232 /* 21325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8233 /* 21329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8234 /* 21333 */ // MIs[0] m
8235 /* 21333 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8236 /* 21336 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8237 /* 21341 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8525:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8238 /* 21341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
8239 /* 21344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8240 /* 21346 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8241 /* 21348 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8242 /* 21350 */ GIR_RootConstrainSelectedInstOperands,
8243 /* 21351 */ // GIR_Coverage, 1005,
8244 /* 21351 */ GIR_EraseRootFromParent_Done,
8245 /* 21352 */ // Label 768: @21352
8246 /* 21352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 769*/ GIMT_Encode4(21397), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1006 //
8247 /* 21359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
8248 /* 21364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8249 /* 21367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8250 /* 21370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8251 /* 21374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8252 /* 21378 */ // MIs[0] m
8253 /* 21378 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8254 /* 21381 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8255 /* 21386 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8527:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8256 /* 21386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
8257 /* 21389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8258 /* 21391 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8259 /* 21393 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8260 /* 21395 */ GIR_RootConstrainSelectedInstOperands,
8261 /* 21396 */ // GIR_Coverage, 1006,
8262 /* 21396 */ GIR_EraseRootFromParent_Done,
8263 /* 21397 */ // Label 769: @21397
8264 /* 21397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(21442), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1007 //
8265 /* 21404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
8266 /* 21409 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8267 /* 21412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8268 /* 21415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8269 /* 21419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8270 /* 21423 */ // MIs[0] m
8271 /* 21423 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8272 /* 21426 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8273 /* 21431 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8528:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8274 /* 21431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
8275 /* 21434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8276 /* 21436 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8277 /* 21438 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8278 /* 21440 */ GIR_RootConstrainSelectedInstOperands,
8279 /* 21441 */ // GIR_Coverage, 1007,
8280 /* 21441 */ GIR_EraseRootFromParent_Done,
8281 /* 21442 */ // Label 770: @21442
8282 /* 21442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(21487), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1008 //
8283 /* 21449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8284 /* 21454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8285 /* 21457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8286 /* 21460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8287 /* 21464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8288 /* 21468 */ // MIs[0] m
8289 /* 21468 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8290 /* 21471 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8291 /* 21476 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8526:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8292 /* 21476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
8293 /* 21479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8294 /* 21481 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8295 /* 21483 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8296 /* 21485 */ GIR_RootConstrainSelectedInstOperands,
8297 /* 21486 */ // GIR_Coverage, 1008,
8298 /* 21486 */ GIR_EraseRootFromParent_Done,
8299 /* 21487 */ // Label 771: @21487
8300 /* 21487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(21532), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1009 //
8301 /* 21494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8302 /* 21499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8303 /* 21502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8304 /* 21505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8305 /* 21509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8306 /* 21513 */ // MIs[0] m
8307 /* 21513 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8308 /* 21516 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8309 /* 21521 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8529:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8310 /* 21521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
8311 /* 21524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8312 /* 21526 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8313 /* 21528 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8314 /* 21530 */ GIR_RootConstrainSelectedInstOperands,
8315 /* 21531 */ // GIR_Coverage, 1009,
8316 /* 21531 */ GIR_EraseRootFromParent_Done,
8317 /* 21532 */ // Label 772: @21532
8318 /* 21532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 773*/ GIMT_Encode4(21577), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1010 //
8319 /* 21539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8320 /* 21544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8321 /* 21547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8322 /* 21550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8323 /* 21554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8324 /* 21558 */ // MIs[0] m
8325 /* 21558 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8326 /* 21561 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8327 /* 21566 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8531:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8328 /* 21566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
8329 /* 21569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8330 /* 21571 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8331 /* 21573 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8332 /* 21575 */ GIR_RootConstrainSelectedInstOperands,
8333 /* 21576 */ // GIR_Coverage, 1010,
8334 /* 21576 */ GIR_EraseRootFromParent_Done,
8335 /* 21577 */ // Label 773: @21577
8336 /* 21577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 774*/ GIMT_Encode4(21622), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1011 //
8337 /* 21584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8338 /* 21589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8339 /* 21592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8340 /* 21595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8341 /* 21599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8342 /* 21603 */ // MIs[0] m
8343 /* 21603 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8344 /* 21606 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8345 /* 21611 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8532:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8346 /* 21611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
8347 /* 21614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8348 /* 21616 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8349 /* 21618 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8350 /* 21620 */ GIR_RootConstrainSelectedInstOperands,
8351 /* 21621 */ // GIR_Coverage, 1011,
8352 /* 21621 */ GIR_EraseRootFromParent_Done,
8353 /* 21622 */ // Label 774: @21622
8354 /* 21622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(21667), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1012 //
8355 /* 21629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8356 /* 21634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8357 /* 21637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8358 /* 21640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8359 /* 21644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8360 /* 21648 */ // MIs[0] m
8361 /* 21648 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8362 /* 21651 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8363 /* 21656 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8530:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8364 /* 21656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
8365 /* 21659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8366 /* 21661 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8367 /* 21663 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8368 /* 21665 */ GIR_RootConstrainSelectedInstOperands,
8369 /* 21666 */ // GIR_Coverage, 1012,
8370 /* 21666 */ GIR_EraseRootFromParent_Done,
8371 /* 21667 */ // Label 775: @21667
8372 /* 21667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(21712), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1052 //
8373 /* 21674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
8374 /* 21679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8375 /* 21682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8376 /* 21685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8377 /* 21689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8378 /* 21693 */ // MIs[0] m
8379 /* 21693 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8380 /* 21696 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8381 /* 21701 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8584:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8382 /* 21701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
8383 /* 21704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8384 /* 21706 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8385 /* 21708 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8386 /* 21710 */ GIR_RootConstrainSelectedInstOperands,
8387 /* 21711 */ // GIR_Coverage, 1052,
8388 /* 21711 */ GIR_EraseRootFromParent_Done,
8389 /* 21712 */ // Label 776: @21712
8390 /* 21712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(21757), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1053 //
8391 /* 21719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
8392 /* 21724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8393 /* 21727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8394 /* 21730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8395 /* 21734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8396 /* 21738 */ // MIs[0] m
8397 /* 21738 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8398 /* 21741 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8399 /* 21746 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8586:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8400 /* 21746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
8401 /* 21749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8402 /* 21751 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8403 /* 21753 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8404 /* 21755 */ GIR_RootConstrainSelectedInstOperands,
8405 /* 21756 */ // GIR_Coverage, 1053,
8406 /* 21756 */ GIR_EraseRootFromParent_Done,
8407 /* 21757 */ // Label 777: @21757
8408 /* 21757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 778*/ GIMT_Encode4(21802), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1054 //
8409 /* 21764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
8410 /* 21769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8411 /* 21772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8412 /* 21775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8413 /* 21779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8414 /* 21783 */ // MIs[0] m
8415 /* 21783 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8416 /* 21786 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8417 /* 21791 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8587:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8418 /* 21791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
8419 /* 21794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8420 /* 21796 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8421 /* 21798 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8422 /* 21800 */ GIR_RootConstrainSelectedInstOperands,
8423 /* 21801 */ // GIR_Coverage, 1054,
8424 /* 21801 */ GIR_EraseRootFromParent_Done,
8425 /* 21802 */ // Label 778: @21802
8426 /* 21802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 779*/ GIMT_Encode4(21847), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1055 //
8427 /* 21809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
8428 /* 21814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8429 /* 21817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8430 /* 21820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8431 /* 21824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8432 /* 21828 */ // MIs[0] m
8433 /* 21828 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8434 /* 21831 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8435 /* 21836 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8585:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8436 /* 21836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
8437 /* 21839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8438 /* 21841 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8439 /* 21843 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8440 /* 21845 */ GIR_RootConstrainSelectedInstOperands,
8441 /* 21846 */ // GIR_Coverage, 1055,
8442 /* 21846 */ GIR_EraseRootFromParent_Done,
8443 /* 21847 */ // Label 779: @21847
8444 /* 21847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(21892), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1068 //
8445 /* 21854 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
8446 /* 21859 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8447 /* 21862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8448 /* 21865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8449 /* 21869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8450 /* 21873 */ // MIs[0] m
8451 /* 21873 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8452 /* 21876 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8453 /* 21881 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8600:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8454 /* 21881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
8455 /* 21884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8456 /* 21886 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8457 /* 21888 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8458 /* 21890 */ GIR_RootConstrainSelectedInstOperands,
8459 /* 21891 */ // GIR_Coverage, 1068,
8460 /* 21891 */ GIR_EraseRootFromParent_Done,
8461 /* 21892 */ // Label 780: @21892
8462 /* 21892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(21937), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1069 //
8463 /* 21899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
8464 /* 21904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8465 /* 21907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8466 /* 21910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8467 /* 21914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8468 /* 21918 */ // MIs[0] m
8469 /* 21918 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8470 /* 21921 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8471 /* 21926 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8602:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8472 /* 21926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
8473 /* 21929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8474 /* 21931 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8475 /* 21933 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8476 /* 21935 */ GIR_RootConstrainSelectedInstOperands,
8477 /* 21936 */ // GIR_Coverage, 1069,
8478 /* 21936 */ GIR_EraseRootFromParent_Done,
8479 /* 21937 */ // Label 781: @21937
8480 /* 21937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(21982), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1070 //
8481 /* 21944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
8482 /* 21949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8483 /* 21952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8484 /* 21955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8485 /* 21959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8486 /* 21963 */ // MIs[0] m
8487 /* 21963 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8488 /* 21966 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8489 /* 21971 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8603:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8490 /* 21971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
8491 /* 21974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8492 /* 21976 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8493 /* 21978 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8494 /* 21980 */ GIR_RootConstrainSelectedInstOperands,
8495 /* 21981 */ // GIR_Coverage, 1070,
8496 /* 21981 */ GIR_EraseRootFromParent_Done,
8497 /* 21982 */ // Label 782: @21982
8498 /* 21982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 783*/ GIMT_Encode4(22027), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1071 //
8499 /* 21989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
8500 /* 21994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8501 /* 21997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8502 /* 22000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8503 /* 22004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8504 /* 22008 */ // MIs[0] m
8505 /* 22008 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8506 /* 22011 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8507 /* 22016 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8601:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8508 /* 22016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
8509 /* 22019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8510 /* 22021 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8511 /* 22023 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8512 /* 22025 */ GIR_RootConstrainSelectedInstOperands,
8513 /* 22026 */ // GIR_Coverage, 1071,
8514 /* 22026 */ GIR_EraseRootFromParent_Done,
8515 /* 22027 */ // Label 783: @22027
8516 /* 22027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 784*/ GIMT_Encode4(22082), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 448 //
8517 /* 22034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8518 /* 22039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8519 /* 22042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8520 /* 22045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8521 /* 22048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8522 /* 22052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8523 /* 22056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8524 /* 22060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8525 /* 22064 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8526 /* 22068 */ // MIs[1] Operand 1
8527 /* 22068 */ // No operand predicates
8528 /* 22068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8529 /* 22070 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8543:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8530 /* 22070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
8531 /* 22073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8532 /* 22075 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8533 /* 22077 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8534 /* 22080 */ GIR_RootConstrainSelectedInstOperands,
8535 /* 22081 */ // GIR_Coverage, 448,
8536 /* 22081 */ GIR_EraseRootFromParent_Done,
8537 /* 22082 */ // Label 784: @22082
8538 /* 22082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 785*/ GIMT_Encode4(22137), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 452 //
8539 /* 22089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8540 /* 22094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8541 /* 22097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8542 /* 22100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8543 /* 22103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8544 /* 22107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8545 /* 22111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8546 /* 22115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8547 /* 22119 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8548 /* 22123 */ // MIs[1] Operand 1
8549 /* 22123 */ // No operand predicates
8550 /* 22123 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8551 /* 22125 */ // (intrinsic_wo_chain:{ *:[i32] } 8545:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8552 /* 22125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
8553 /* 22128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8554 /* 22130 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8555 /* 22132 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8556 /* 22135 */ GIR_RootConstrainSelectedInstOperands,
8557 /* 22136 */ // GIR_Coverage, 452,
8558 /* 22136 */ GIR_EraseRootFromParent_Done,
8559 /* 22137 */ // Label 785: @22137
8560 /* 22137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 786*/ GIMT_Encode4(22192), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 543 //
8561 /* 22144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8562 /* 22149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8563 /* 22152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8564 /* 22155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8565 /* 22158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8566 /* 22162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8567 /* 22166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8568 /* 22170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8569 /* 22174 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8570 /* 22178 */ // MIs[1] Operand 1
8571 /* 22178 */ // No operand predicates
8572 /* 22178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8573 /* 22180 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8544:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8574 /* 22180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
8575 /* 22183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8576 /* 22185 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8577 /* 22187 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8578 /* 22190 */ GIR_RootConstrainSelectedInstOperands,
8579 /* 22191 */ // GIR_Coverage, 543,
8580 /* 22191 */ GIR_EraseRootFromParent_Done,
8581 /* 22192 */ // Label 786: @22192
8582 /* 22192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 787*/ GIMT_Encode4(22247), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1323 //
8583 /* 22199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8584 /* 22204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8585 /* 22207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8586 /* 22210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8587 /* 22213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8588 /* 22217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8589 /* 22221 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8590 /* 22225 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8591 /* 22229 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8592 /* 22233 */ // MIs[1] Operand 1
8593 /* 22233 */ // No operand predicates
8594 /* 22233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8595 /* 22235 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8543:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
8596 /* 22235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
8597 /* 22238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8598 /* 22240 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8599 /* 22242 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8600 /* 22245 */ GIR_RootConstrainSelectedInstOperands,
8601 /* 22246 */ // GIR_Coverage, 1323,
8602 /* 22246 */ GIR_EraseRootFromParent_Done,
8603 /* 22247 */ // Label 787: @22247
8604 /* 22247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 788*/ GIMT_Encode4(22302), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1327 //
8605 /* 22254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8606 /* 22259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8607 /* 22262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8608 /* 22265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8609 /* 22268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8610 /* 22272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8611 /* 22276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8612 /* 22280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8613 /* 22284 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8614 /* 22288 */ // MIs[1] Operand 1
8615 /* 22288 */ // No operand predicates
8616 /* 22288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8617 /* 22290 */ // (intrinsic_wo_chain:{ *:[i32] } 8545:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
8618 /* 22290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
8619 /* 22293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8620 /* 22295 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8621 /* 22297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8622 /* 22300 */ GIR_RootConstrainSelectedInstOperands,
8623 /* 22301 */ // GIR_Coverage, 1327,
8624 /* 22301 */ GIR_EraseRootFromParent_Done,
8625 /* 22302 */ // Label 788: @22302
8626 /* 22302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(22357), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1402 //
8627 /* 22309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8628 /* 22314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8629 /* 22317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8630 /* 22320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8631 /* 22323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8632 /* 22327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8633 /* 22331 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8634 /* 22335 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8635 /* 22339 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8636 /* 22343 */ // MIs[1] Operand 1
8637 /* 22343 */ // No operand predicates
8638 /* 22343 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8639 /* 22345 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8544:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
8640 /* 22345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
8641 /* 22348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8642 /* 22350 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8643 /* 22352 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8644 /* 22355 */ GIR_RootConstrainSelectedInstOperands,
8645 /* 22356 */ // GIR_Coverage, 1402,
8646 /* 22356 */ GIR_EraseRootFromParent_Done,
8647 /* 22357 */ // Label 789: @22357
8648 /* 22357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(22408), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2194 //
8649 /* 22364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8650 /* 22369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8651 /* 22372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8652 /* 22375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8653 /* 22378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8654 /* 22382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8655 /* 22386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8656 /* 22390 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8657 /* 22394 */ // MIs[1] Operand 1
8658 /* 22394 */ // No operand predicates
8659 /* 22394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8660 /* 22396 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8541:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8661 /* 22396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
8662 /* 22399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8663 /* 22401 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8664 /* 22403 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8665 /* 22406 */ GIR_RootConstrainSelectedInstOperands,
8666 /* 22407 */ // GIR_Coverage, 2194,
8667 /* 22407 */ GIR_EraseRootFromParent_Done,
8668 /* 22408 */ // Label 790: @22408
8669 /* 22408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(22459), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2195 //
8670 /* 22415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8671 /* 22420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8672 /* 22423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8673 /* 22426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8674 /* 22429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8675 /* 22433 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8676 /* 22437 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8677 /* 22441 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8678 /* 22445 */ // MIs[1] Operand 1
8679 /* 22445 */ // No operand predicates
8680 /* 22445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8681 /* 22447 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8546:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8682 /* 22447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
8683 /* 22450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8684 /* 22452 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8685 /* 22454 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8686 /* 22457 */ GIR_RootConstrainSelectedInstOperands,
8687 /* 22458 */ // GIR_Coverage, 2195,
8688 /* 22458 */ GIR_EraseRootFromParent_Done,
8689 /* 22459 */ // Label 791: @22459
8690 /* 22459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 792*/ GIMT_Encode4(22510), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2200 //
8691 /* 22466 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8692 /* 22471 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8693 /* 22474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8694 /* 22477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8695 /* 22480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8696 /* 22484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8697 /* 22488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8698 /* 22492 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8699 /* 22496 */ // MIs[1] Operand 1
8700 /* 22496 */ // No operand predicates
8701 /* 22496 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8702 /* 22498 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8542:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8703 /* 22498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
8704 /* 22501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8705 /* 22503 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8706 /* 22505 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8707 /* 22508 */ GIR_RootConstrainSelectedInstOperands,
8708 /* 22509 */ // GIR_Coverage, 2200,
8709 /* 22509 */ GIR_EraseRootFromParent_Done,
8710 /* 22510 */ // Label 792: @22510
8711 /* 22510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 793*/ GIMT_Encode4(22561), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2201 //
8712 /* 22517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8713 /* 22522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8714 /* 22525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8715 /* 22528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8716 /* 22531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8717 /* 22535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8718 /* 22539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8719 /* 22543 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8720 /* 22547 */ // MIs[1] Operand 1
8721 /* 22547 */ // No operand predicates
8722 /* 22547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8723 /* 22549 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8547:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8724 /* 22549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
8725 /* 22552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8726 /* 22554 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8727 /* 22556 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8728 /* 22559 */ GIR_RootConstrainSelectedInstOperands,
8729 /* 22560 */ // GIR_Coverage, 2201,
8730 /* 22560 */ GIR_EraseRootFromParent_Done,
8731 /* 22561 */ // Label 793: @22561
8732 /* 22561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(22608), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 418 //
8733 /* 22568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
8734 /* 22573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8735 /* 22576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8736 /* 22579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8737 /* 22582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8738 /* 22586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8739 /* 22590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8740 /* 22594 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8013:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8741 /* 22594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
8742 /* 22597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8743 /* 22599 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8744 /* 22601 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8745 /* 22603 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8746 /* 22606 */ GIR_RootConstrainSelectedInstOperands,
8747 /* 22607 */ // GIR_Coverage, 418,
8748 /* 22607 */ GIR_EraseRootFromParent_Done,
8749 /* 22608 */ // Label 794: @22608
8750 /* 22608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(22655), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 419 //
8751 /* 22615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
8752 /* 22620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8753 /* 22623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8754 /* 22626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8755 /* 22629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8756 /* 22633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8757 /* 22637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8758 /* 22641 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8636:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8759 /* 22641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
8760 /* 22644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8761 /* 22646 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8762 /* 22648 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8763 /* 22650 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8764 /* 22653 */ GIR_RootConstrainSelectedInstOperands,
8765 /* 22654 */ // GIR_Coverage, 419,
8766 /* 22654 */ GIR_EraseRootFromParent_Done,
8767 /* 22655 */ // Label 795: @22655
8768 /* 22655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(22702), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 420 //
8769 /* 22662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
8770 /* 22667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8771 /* 22670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8772 /* 22673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8773 /* 22676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8774 /* 22680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8775 /* 22684 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8776 /* 22688 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8777 /* 22688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
8778 /* 22691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8779 /* 22693 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8780 /* 22695 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8781 /* 22697 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8782 /* 22700 */ GIR_RootConstrainSelectedInstOperands,
8783 /* 22701 */ // GIR_Coverage, 420,
8784 /* 22701 */ GIR_EraseRootFromParent_Done,
8785 /* 22702 */ // Label 796: @22702
8786 /* 22702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 797*/ GIMT_Encode4(22749), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 421 //
8787 /* 22709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
8788 /* 22714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8789 /* 22717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8790 /* 22720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8791 /* 22723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8792 /* 22727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8793 /* 22731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8794 /* 22735 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8795 /* 22735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
8796 /* 22738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8797 /* 22740 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8798 /* 22742 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8799 /* 22744 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8800 /* 22747 */ GIR_RootConstrainSelectedInstOperands,
8801 /* 22748 */ // GIR_Coverage, 421,
8802 /* 22748 */ GIR_EraseRootFromParent_Done,
8803 /* 22749 */ // Label 797: @22749
8804 /* 22749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 798*/ GIMT_Encode4(22793), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 424 //
8805 /* 22756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
8806 /* 22761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8807 /* 22764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8808 /* 22767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8809 /* 22770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8810 /* 22774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8811 /* 22778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8812 /* 22782 */ // (intrinsic_wo_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8813 /* 22782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
8814 /* 22785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8815 /* 22787 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8816 /* 22789 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8817 /* 22791 */ GIR_RootConstrainSelectedInstOperands,
8818 /* 22792 */ // GIR_Coverage, 424,
8819 /* 22792 */ GIR_EraseRootFromParent_Done,
8820 /* 22793 */ // Label 798: @22793
8821 /* 22793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(22837), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 428 //
8822 /* 22800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
8823 /* 22805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8824 /* 22808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8825 /* 22811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8826 /* 22814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8827 /* 22818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8828 /* 22822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8829 /* 22826 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8830 /* 22826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
8831 /* 22829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8832 /* 22831 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8833 /* 22833 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8834 /* 22835 */ GIR_RootConstrainSelectedInstOperands,
8835 /* 22836 */ // GIR_Coverage, 428,
8836 /* 22836 */ GIR_EraseRootFromParent_Done,
8837 /* 22837 */ // Label 799: @22837
8838 /* 22837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(22881), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 429 //
8839 /* 22844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
8840 /* 22849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8841 /* 22852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8842 /* 22855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8843 /* 22858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8844 /* 22862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8845 /* 22866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8846 /* 22870 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8516:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8847 /* 22870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
8848 /* 22873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8849 /* 22875 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8850 /* 22877 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8851 /* 22879 */ GIR_RootConstrainSelectedInstOperands,
8852 /* 22880 */ // GIR_Coverage, 429,
8853 /* 22880 */ GIR_EraseRootFromParent_Done,
8854 /* 22881 */ // Label 800: @22881
8855 /* 22881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(22925), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 443 //
8856 /* 22888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8857 /* 22893 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8858 /* 22896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8859 /* 22899 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8860 /* 22902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8861 /* 22906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8862 /* 22910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8863 /* 22914 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8547:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8864 /* 22914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
8865 /* 22917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8866 /* 22919 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8867 /* 22921 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8868 /* 22923 */ GIR_RootConstrainSelectedInstOperands,
8869 /* 22924 */ // GIR_Coverage, 443,
8870 /* 22924 */ GIR_EraseRootFromParent_Done,
8871 /* 22925 */ // Label 801: @22925
8872 /* 22925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 802*/ GIMT_Encode4(22969), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 447 //
8873 /* 22932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8874 /* 22937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8875 /* 22940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8876 /* 22943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8877 /* 22946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8878 /* 22950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8879 /* 22954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8880 /* 22958 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8541:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8881 /* 22958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
8882 /* 22961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8883 /* 22963 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8884 /* 22965 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8885 /* 22967 */ GIR_RootConstrainSelectedInstOperands,
8886 /* 22968 */ // GIR_Coverage, 447,
8887 /* 22968 */ GIR_EraseRootFromParent_Done,
8888 /* 22969 */ // Label 802: @22969
8889 /* 22969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 803*/ GIMT_Encode4(23013), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 449 //
8890 /* 22976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8891 /* 22981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8892 /* 22984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8893 /* 22987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8894 /* 22990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8895 /* 22994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8896 /* 22998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8897 /* 23002 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8543:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8898 /* 23002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
8899 /* 23005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8900 /* 23007 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8901 /* 23009 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8902 /* 23011 */ GIR_RootConstrainSelectedInstOperands,
8903 /* 23012 */ // GIR_Coverage, 449,
8904 /* 23012 */ GIR_EraseRootFromParent_Done,
8905 /* 23013 */ // Label 803: @23013
8906 /* 23013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(23057), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 453 //
8907 /* 23020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8908 /* 23025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8909 /* 23028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8910 /* 23031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8911 /* 23034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8912 /* 23038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8913 /* 23042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8914 /* 23046 */ // (intrinsic_wo_chain:{ *:[i32] } 8545:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8915 /* 23046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
8916 /* 23049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8917 /* 23051 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8918 /* 23053 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8919 /* 23055 */ GIR_RootConstrainSelectedInstOperands,
8920 /* 23056 */ // GIR_Coverage, 453,
8921 /* 23056 */ GIR_EraseRootFromParent_Done,
8922 /* 23057 */ // Label 804: @23057
8923 /* 23057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(23101), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 490 //
8924 /* 23064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
8925 /* 23069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8926 /* 23072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8927 /* 23075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8928 /* 23078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8929 /* 23082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8930 /* 23086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8931 /* 23090 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8932 /* 23090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
8933 /* 23093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8934 /* 23095 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8935 /* 23097 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8936 /* 23099 */ GIR_RootConstrainSelectedInstOperands,
8937 /* 23100 */ // GIR_Coverage, 490,
8938 /* 23100 */ GIR_EraseRootFromParent_Done,
8939 /* 23101 */ // Label 805: @23101
8940 /* 23101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(23145), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 514 //
8941 /* 23108 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
8942 /* 23113 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8943 /* 23116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8944 /* 23119 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8945 /* 23122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8946 /* 23126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8947 /* 23130 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8948 /* 23134 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8014:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8949 /* 23134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
8950 /* 23137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8951 /* 23139 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8952 /* 23141 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8953 /* 23143 */ GIR_RootConstrainSelectedInstOperands,
8954 /* 23144 */ // GIR_Coverage, 514,
8955 /* 23144 */ GIR_EraseRootFromParent_Done,
8956 /* 23145 */ // Label 806: @23145
8957 /* 23145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 807*/ GIMT_Encode4(23189), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 515 //
8958 /* 23152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
8959 /* 23157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8960 /* 23160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8961 /* 23163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8962 /* 23166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8963 /* 23170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8964 /* 23174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8965 /* 23178 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8015:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8966 /* 23178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
8967 /* 23181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8968 /* 23183 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8969 /* 23185 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8970 /* 23187 */ GIR_RootConstrainSelectedInstOperands,
8971 /* 23188 */ // GIR_Coverage, 515,
8972 /* 23188 */ GIR_EraseRootFromParent_Done,
8973 /* 23189 */ // Label 807: @23189
8974 /* 23189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 808*/ GIMT_Encode4(23233), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 516 //
8975 /* 23196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
8976 /* 23201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8977 /* 23204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8978 /* 23207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8979 /* 23210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8980 /* 23214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8981 /* 23218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8982 /* 23222 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8637:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8983 /* 23222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
8984 /* 23225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8985 /* 23227 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8986 /* 23229 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8987 /* 23231 */ GIR_RootConstrainSelectedInstOperands,
8988 /* 23232 */ // GIR_Coverage, 516,
8989 /* 23232 */ GIR_EraseRootFromParent_Done,
8990 /* 23233 */ // Label 808: @23233
8991 /* 23233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(23277), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 517 //
8992 /* 23240 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
8993 /* 23245 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8994 /* 23248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8995 /* 23251 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8996 /* 23254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8997 /* 23258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8998 /* 23262 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8999 /* 23266 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8638:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9000 /* 23266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
9001 /* 23269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9002 /* 23271 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9003 /* 23273 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9004 /* 23275 */ GIR_RootConstrainSelectedInstOperands,
9005 /* 23276 */ // GIR_Coverage, 517,
9006 /* 23276 */ GIR_EraseRootFromParent_Done,
9007 /* 23277 */ // Label 809: @23277
9008 /* 23277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(23321), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 518 //
9009 /* 23284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
9010 /* 23289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9011 /* 23292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9012 /* 23295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9013 /* 23298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9014 /* 23302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9015 /* 23306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9016 /* 23310 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9017 /* 23310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
9018 /* 23313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9019 /* 23315 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9020 /* 23317 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9021 /* 23319 */ GIR_RootConstrainSelectedInstOperands,
9022 /* 23320 */ // GIR_Coverage, 518,
9023 /* 23320 */ GIR_EraseRootFromParent_Done,
9024 /* 23321 */ // Label 810: @23321
9025 /* 23321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(23365), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 519 //
9026 /* 23328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
9027 /* 23333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9028 /* 23336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9029 /* 23339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9030 /* 23342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9031 /* 23346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9032 /* 23350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9033 /* 23354 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7994:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9034 /* 23354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
9035 /* 23357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9036 /* 23359 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9037 /* 23361 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9038 /* 23363 */ GIR_RootConstrainSelectedInstOperands,
9039 /* 23364 */ // GIR_Coverage, 519,
9040 /* 23364 */ GIR_EraseRootFromParent_Done,
9041 /* 23365 */ // Label 811: @23365
9042 /* 23365 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 812*/ GIMT_Encode4(23409), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 520 //
9043 /* 23372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
9044 /* 23377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9045 /* 23380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9046 /* 23383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9047 /* 23386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9048 /* 23390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9049 /* 23394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9050 /* 23398 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9051 /* 23398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
9052 /* 23401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9053 /* 23403 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9054 /* 23405 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9055 /* 23407 */ GIR_RootConstrainSelectedInstOperands,
9056 /* 23408 */ // GIR_Coverage, 520,
9057 /* 23408 */ GIR_EraseRootFromParent_Done,
9058 /* 23409 */ // Label 812: @23409
9059 /* 23409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 813*/ GIMT_Encode4(23453), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 521 //
9060 /* 23416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
9061 /* 23421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9062 /* 23424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9063 /* 23427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9064 /* 23430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9065 /* 23434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9066 /* 23438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9067 /* 23442 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9068 /* 23442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
9069 /* 23445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9070 /* 23447 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9071 /* 23449 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9072 /* 23451 */ GIR_RootConstrainSelectedInstOperands,
9073 /* 23452 */ // GIR_Coverage, 521,
9074 /* 23452 */ GIR_EraseRootFromParent_Done,
9075 /* 23453 */ // Label 813: @23453
9076 /* 23453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(23497), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 522 //
9077 /* 23460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
9078 /* 23465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9079 /* 23468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9080 /* 23471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9081 /* 23474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9082 /* 23478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9083 /* 23482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9084 /* 23486 */ // (intrinsic_wo_chain:{ *:[i32] } 7996:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9085 /* 23486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
9086 /* 23489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9087 /* 23491 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9088 /* 23493 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9089 /* 23495 */ GIR_RootConstrainSelectedInstOperands,
9090 /* 23496 */ // GIR_Coverage, 522,
9091 /* 23496 */ GIR_EraseRootFromParent_Done,
9092 /* 23497 */ // Label 814: @23497
9093 /* 23497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(23541), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 523 //
9094 /* 23504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
9095 /* 23509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9096 /* 23512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9097 /* 23515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9098 /* 23518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9099 /* 23522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9100 /* 23526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9101 /* 23530 */ // (intrinsic_wo_chain:{ *:[i32] } 7995:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9102 /* 23530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
9103 /* 23533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9104 /* 23535 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9105 /* 23537 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9106 /* 23539 */ GIR_RootConstrainSelectedInstOperands,
9107 /* 23540 */ // GIR_Coverage, 523,
9108 /* 23540 */ GIR_EraseRootFromParent_Done,
9109 /* 23541 */ // Label 815: @23541
9110 /* 23541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(23585), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 524 //
9111 /* 23548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
9112 /* 23553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9113 /* 23556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9114 /* 23559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9115 /* 23562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9116 /* 23566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9117 /* 23570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9118 /* 23574 */ // (intrinsic_wo_chain:{ *:[i32] } 8616:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9119 /* 23574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
9120 /* 23577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9121 /* 23579 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9122 /* 23581 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9123 /* 23583 */ GIR_RootConstrainSelectedInstOperands,
9124 /* 23584 */ // GIR_Coverage, 524,
9125 /* 23584 */ GIR_EraseRootFromParent_Done,
9126 /* 23585 */ // Label 816: @23585
9127 /* 23585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 817*/ GIMT_Encode4(23629), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 525 //
9128 /* 23592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
9129 /* 23597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9130 /* 23600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9131 /* 23603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9132 /* 23606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9133 /* 23610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9134 /* 23614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9135 /* 23618 */ // (intrinsic_wo_chain:{ *:[i32] } 8615:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9136 /* 23618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
9137 /* 23621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9138 /* 23623 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9139 /* 23625 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9140 /* 23627 */ GIR_RootConstrainSelectedInstOperands,
9141 /* 23628 */ // GIR_Coverage, 525,
9142 /* 23628 */ GIR_EraseRootFromParent_Done,
9143 /* 23629 */ // Label 817: @23629
9144 /* 23629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 818*/ GIMT_Encode4(23673), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 542 //
9145 /* 23636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
9146 /* 23641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9147 /* 23644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9148 /* 23647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9149 /* 23650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9150 /* 23654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9151 /* 23658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9152 /* 23662 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8542:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9153 /* 23662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
9154 /* 23665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9155 /* 23667 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9156 /* 23669 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9157 /* 23671 */ GIR_RootConstrainSelectedInstOperands,
9158 /* 23672 */ // GIR_Coverage, 542,
9159 /* 23672 */ GIR_EraseRootFromParent_Done,
9160 /* 23673 */ // Label 818: @23673
9161 /* 23673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 819*/ GIMT_Encode4(23717), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 544 //
9162 /* 23680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9163 /* 23685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9164 /* 23688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9165 /* 23691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9166 /* 23694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9167 /* 23698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9168 /* 23702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9169 /* 23706 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8544:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9170 /* 23706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
9171 /* 23709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9172 /* 23711 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9173 /* 23713 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9174 /* 23715 */ GIR_RootConstrainSelectedInstOperands,
9175 /* 23716 */ // GIR_Coverage, 544,
9176 /* 23716 */ GIR_EraseRootFromParent_Done,
9177 /* 23717 */ // Label 819: @23717
9178 /* 23717 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 820*/ GIMT_Encode4(23761), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 545 //
9179 /* 23724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9180 /* 23729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9181 /* 23732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9182 /* 23735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9183 /* 23738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9184 /* 23742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9185 /* 23746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9186 /* 23750 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8546:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9187 /* 23750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
9188 /* 23753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9189 /* 23755 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9190 /* 23757 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9191 /* 23759 */ GIR_RootConstrainSelectedInstOperands,
9192 /* 23760 */ // GIR_Coverage, 545,
9193 /* 23760 */ GIR_EraseRootFromParent_Done,
9194 /* 23761 */ // Label 820: @23761
9195 /* 23761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 821*/ GIMT_Encode4(23805), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 554 //
9196 /* 23768 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
9197 /* 23773 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9198 /* 23776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9199 /* 23779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9200 /* 23782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9201 /* 23786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9202 /* 23790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9203 /* 23794 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7986:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9204 /* 23794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
9205 /* 23797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9206 /* 23799 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9207 /* 23801 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9208 /* 23803 */ GIR_RootConstrainSelectedInstOperands,
9209 /* 23804 */ // GIR_Coverage, 554,
9210 /* 23804 */ GIR_EraseRootFromParent_Done,
9211 /* 23805 */ // Label 821: @23805
9212 /* 23805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 822*/ GIMT_Encode4(23849), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 555 //
9213 /* 23812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
9214 /* 23817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9215 /* 23820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9216 /* 23823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9217 /* 23826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9218 /* 23830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9219 /* 23834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9220 /* 23838 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7988:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9221 /* 23838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
9222 /* 23841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9223 /* 23843 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9224 /* 23845 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9225 /* 23847 */ GIR_RootConstrainSelectedInstOperands,
9226 /* 23848 */ // GIR_Coverage, 555,
9227 /* 23848 */ GIR_EraseRootFromParent_Done,
9228 /* 23849 */ // Label 822: @23849
9229 /* 23849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 823*/ GIMT_Encode4(23893), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 556 //
9230 /* 23856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
9231 /* 23861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9232 /* 23864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9233 /* 23867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9234 /* 23870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9235 /* 23874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9236 /* 23878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9237 /* 23882 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7989:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9238 /* 23882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
9239 /* 23885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9240 /* 23887 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9241 /* 23889 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9242 /* 23891 */ GIR_RootConstrainSelectedInstOperands,
9243 /* 23892 */ // GIR_Coverage, 556,
9244 /* 23892 */ GIR_EraseRootFromParent_Done,
9245 /* 23893 */ // Label 823: @23893
9246 /* 23893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(23937), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 557 //
9247 /* 23900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
9248 /* 23905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9249 /* 23908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9250 /* 23911 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9251 /* 23914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9252 /* 23918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9253 /* 23922 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9254 /* 23926 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7987:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9255 /* 23926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
9256 /* 23929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9257 /* 23931 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9258 /* 23933 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9259 /* 23935 */ GIR_RootConstrainSelectedInstOperands,
9260 /* 23936 */ // GIR_Coverage, 557,
9261 /* 23936 */ GIR_EraseRootFromParent_Done,
9262 /* 23937 */ // Label 824: @23937
9263 /* 23937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(23981), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 558 //
9264 /* 23944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9265 /* 23949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9266 /* 23952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9267 /* 23955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9268 /* 23958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9269 /* 23962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9270 /* 23966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9271 /* 23970 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7997:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9272 /* 23970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
9273 /* 23973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9274 /* 23975 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9275 /* 23977 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9276 /* 23979 */ GIR_RootConstrainSelectedInstOperands,
9277 /* 23980 */ // GIR_Coverage, 558,
9278 /* 23980 */ GIR_EraseRootFromParent_Done,
9279 /* 23981 */ // Label 825: @23981
9280 /* 23981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(24025), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 559 //
9281 /* 23988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9282 /* 23993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9283 /* 23996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9284 /* 23999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9285 /* 24002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9286 /* 24006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9287 /* 24010 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9288 /* 24014 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7999:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9289 /* 24014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
9290 /* 24017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9291 /* 24019 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9292 /* 24021 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9293 /* 24023 */ GIR_RootConstrainSelectedInstOperands,
9294 /* 24024 */ // GIR_Coverage, 559,
9295 /* 24024 */ GIR_EraseRootFromParent_Done,
9296 /* 24025 */ // Label 826: @24025
9297 /* 24025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(24069), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 560 //
9298 /* 24032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9299 /* 24037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9300 /* 24040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9301 /* 24043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9302 /* 24046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9303 /* 24050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9304 /* 24054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9305 /* 24058 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8000:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9306 /* 24058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
9307 /* 24061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9308 /* 24063 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9309 /* 24065 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9310 /* 24067 */ GIR_RootConstrainSelectedInstOperands,
9311 /* 24068 */ // GIR_Coverage, 560,
9312 /* 24068 */ GIR_EraseRootFromParent_Done,
9313 /* 24069 */ // Label 827: @24069
9314 /* 24069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(24113), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 561 //
9315 /* 24076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9316 /* 24081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9317 /* 24084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9318 /* 24087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9319 /* 24090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9320 /* 24094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9321 /* 24098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9322 /* 24102 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7998:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9323 /* 24102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
9324 /* 24105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9325 /* 24107 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9326 /* 24109 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9327 /* 24111 */ GIR_RootConstrainSelectedInstOperands,
9328 /* 24112 */ // GIR_Coverage, 561,
9329 /* 24112 */ GIR_EraseRootFromParent_Done,
9330 /* 24113 */ // Label 828: @24113
9331 /* 24113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(24157), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 562 //
9332 /* 24120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9333 /* 24125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9334 /* 24128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9335 /* 24131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9336 /* 24134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9337 /* 24138 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9338 /* 24142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9339 /* 24146 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8001:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9340 /* 24146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
9341 /* 24149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9342 /* 24151 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9343 /* 24153 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9344 /* 24155 */ GIR_RootConstrainSelectedInstOperands,
9345 /* 24156 */ // GIR_Coverage, 562,
9346 /* 24156 */ GIR_EraseRootFromParent_Done,
9347 /* 24157 */ // Label 829: @24157
9348 /* 24157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(24201), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 563 //
9349 /* 24164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9350 /* 24169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9351 /* 24172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9352 /* 24175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9353 /* 24178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9354 /* 24182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9355 /* 24186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9356 /* 24190 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8003:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9357 /* 24190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
9358 /* 24193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9359 /* 24195 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9360 /* 24197 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9361 /* 24199 */ GIR_RootConstrainSelectedInstOperands,
9362 /* 24200 */ // GIR_Coverage, 563,
9363 /* 24200 */ GIR_EraseRootFromParent_Done,
9364 /* 24201 */ // Label 830: @24201
9365 /* 24201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 831*/ GIMT_Encode4(24245), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 564 //
9366 /* 24208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9367 /* 24213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9368 /* 24216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9369 /* 24219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9370 /* 24222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9371 /* 24226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9372 /* 24230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9373 /* 24234 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8004:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9374 /* 24234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
9375 /* 24237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9376 /* 24239 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9377 /* 24241 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9378 /* 24243 */ GIR_RootConstrainSelectedInstOperands,
9379 /* 24244 */ // GIR_Coverage, 564,
9380 /* 24244 */ GIR_EraseRootFromParent_Done,
9381 /* 24245 */ // Label 831: @24245
9382 /* 24245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 832*/ GIMT_Encode4(24289), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 565 //
9383 /* 24252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9384 /* 24257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9385 /* 24260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9386 /* 24263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9387 /* 24266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9388 /* 24270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9389 /* 24274 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9390 /* 24278 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8002:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9391 /* 24278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
9392 /* 24281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9393 /* 24283 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9394 /* 24285 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9395 /* 24287 */ GIR_RootConstrainSelectedInstOperands,
9396 /* 24288 */ // GIR_Coverage, 565,
9397 /* 24288 */ GIR_EraseRootFromParent_Done,
9398 /* 24289 */ // Label 832: @24289
9399 /* 24289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(24333), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 566 //
9400 /* 24296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9401 /* 24301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9402 /* 24304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9403 /* 24307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9404 /* 24310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9405 /* 24314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9406 /* 24318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9407 /* 24322 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8005:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9408 /* 24322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
9409 /* 24325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9410 /* 24327 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9411 /* 24329 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9412 /* 24331 */ GIR_RootConstrainSelectedInstOperands,
9413 /* 24332 */ // GIR_Coverage, 566,
9414 /* 24332 */ GIR_EraseRootFromParent_Done,
9415 /* 24333 */ // Label 833: @24333
9416 /* 24333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(24377), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 567 //
9417 /* 24340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9418 /* 24345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9419 /* 24348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9420 /* 24351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9421 /* 24354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9422 /* 24358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9423 /* 24362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9424 /* 24366 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8007:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9425 /* 24366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
9426 /* 24369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9427 /* 24371 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9428 /* 24373 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9429 /* 24375 */ GIR_RootConstrainSelectedInstOperands,
9430 /* 24376 */ // GIR_Coverage, 567,
9431 /* 24376 */ GIR_EraseRootFromParent_Done,
9432 /* 24377 */ // Label 834: @24377
9433 /* 24377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(24421), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 568 //
9434 /* 24384 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9435 /* 24389 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9436 /* 24392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9437 /* 24395 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9438 /* 24398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9439 /* 24402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9440 /* 24406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9441 /* 24410 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8008:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9442 /* 24410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
9443 /* 24413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9444 /* 24415 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9445 /* 24417 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9446 /* 24419 */ GIR_RootConstrainSelectedInstOperands,
9447 /* 24420 */ // GIR_Coverage, 568,
9448 /* 24420 */ GIR_EraseRootFromParent_Done,
9449 /* 24421 */ // Label 835: @24421
9450 /* 24421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 836*/ GIMT_Encode4(24465), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 569 //
9451 /* 24428 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9452 /* 24433 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9453 /* 24436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9454 /* 24439 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9455 /* 24442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9456 /* 24446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9457 /* 24450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9458 /* 24454 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8006:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9459 /* 24454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
9460 /* 24457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9461 /* 24459 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9462 /* 24461 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9463 /* 24463 */ GIR_RootConstrainSelectedInstOperands,
9464 /* 24464 */ // GIR_Coverage, 569,
9465 /* 24464 */ GIR_EraseRootFromParent_Done,
9466 /* 24465 */ // Label 836: @24465
9467 /* 24465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 837*/ GIMT_Encode4(24509), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 583 //
9468 /* 24472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9469 /* 24477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9470 /* 24480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9471 /* 24483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9472 /* 24486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9473 /* 24490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9474 /* 24494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9475 /* 24498 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8028:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9476 /* 24498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
9477 /* 24501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9478 /* 24503 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9479 /* 24505 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9480 /* 24507 */ GIR_RootConstrainSelectedInstOperands,
9481 /* 24508 */ // GIR_Coverage, 583,
9482 /* 24508 */ GIR_EraseRootFromParent_Done,
9483 /* 24509 */ // Label 837: @24509
9484 /* 24509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(24553), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 584 //
9485 /* 24516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9486 /* 24521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9487 /* 24524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9488 /* 24527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9489 /* 24530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9490 /* 24534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9491 /* 24538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9492 /* 24542 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8030:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9493 /* 24542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
9494 /* 24545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9495 /* 24547 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9496 /* 24549 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9497 /* 24551 */ GIR_RootConstrainSelectedInstOperands,
9498 /* 24552 */ // GIR_Coverage, 584,
9499 /* 24552 */ GIR_EraseRootFromParent_Done,
9500 /* 24553 */ // Label 838: @24553
9501 /* 24553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 839*/ GIMT_Encode4(24597), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 585 //
9502 /* 24560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
9503 /* 24565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9504 /* 24568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9505 /* 24571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9506 /* 24574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9507 /* 24578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9508 /* 24582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9509 /* 24586 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8031:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9510 /* 24586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
9511 /* 24589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9512 /* 24591 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9513 /* 24593 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9514 /* 24595 */ GIR_RootConstrainSelectedInstOperands,
9515 /* 24596 */ // GIR_Coverage, 585,
9516 /* 24596 */ GIR_EraseRootFromParent_Done,
9517 /* 24597 */ // Label 839: @24597
9518 /* 24597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 840*/ GIMT_Encode4(24641), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 586 //
9519 /* 24604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
9520 /* 24609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9521 /* 24612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9522 /* 24615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9523 /* 24618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9524 /* 24622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9525 /* 24626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9526 /* 24630 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8029:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9527 /* 24630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
9528 /* 24633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9529 /* 24635 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9530 /* 24637 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9531 /* 24639 */ GIR_RootConstrainSelectedInstOperands,
9532 /* 24640 */ // GIR_Coverage, 586,
9533 /* 24640 */ GIR_EraseRootFromParent_Done,
9534 /* 24641 */ // Label 840: @24641
9535 /* 24641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(24685), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 587 //
9536 /* 24648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
9537 /* 24653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9538 /* 24656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9539 /* 24659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9540 /* 24662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9541 /* 24666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9542 /* 24670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9543 /* 24674 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8032:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9544 /* 24674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
9545 /* 24677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9546 /* 24679 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9547 /* 24681 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9548 /* 24683 */ GIR_RootConstrainSelectedInstOperands,
9549 /* 24684 */ // GIR_Coverage, 587,
9550 /* 24684 */ GIR_EraseRootFromParent_Done,
9551 /* 24685 */ // Label 841: @24685
9552 /* 24685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(24729), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 588 //
9553 /* 24692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
9554 /* 24697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9555 /* 24700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9556 /* 24703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9557 /* 24706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9558 /* 24710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9559 /* 24714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9560 /* 24718 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8034:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9561 /* 24718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
9562 /* 24721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9563 /* 24723 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9564 /* 24725 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9565 /* 24727 */ GIR_RootConstrainSelectedInstOperands,
9566 /* 24728 */ // GIR_Coverage, 588,
9567 /* 24728 */ GIR_EraseRootFromParent_Done,
9568 /* 24729 */ // Label 842: @24729
9569 /* 24729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(24773), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 589 //
9570 /* 24736 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
9571 /* 24741 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9572 /* 24744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9573 /* 24747 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9574 /* 24750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9575 /* 24754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9576 /* 24758 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9577 /* 24762 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8035:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9578 /* 24762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
9579 /* 24765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9580 /* 24767 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9581 /* 24769 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9582 /* 24771 */ GIR_RootConstrainSelectedInstOperands,
9583 /* 24772 */ // GIR_Coverage, 589,
9584 /* 24772 */ GIR_EraseRootFromParent_Done,
9585 /* 24773 */ // Label 843: @24773
9586 /* 24773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(24817), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 590 //
9587 /* 24780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
9588 /* 24785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9589 /* 24788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9590 /* 24791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9591 /* 24794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9592 /* 24798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9593 /* 24802 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9594 /* 24806 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8033:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9595 /* 24806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
9596 /* 24809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9597 /* 24811 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9598 /* 24813 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9599 /* 24815 */ GIR_RootConstrainSelectedInstOperands,
9600 /* 24816 */ // GIR_Coverage, 590,
9601 /* 24816 */ GIR_EraseRootFromParent_Done,
9602 /* 24817 */ // Label 844: @24817
9603 /* 24817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(24861), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 591 //
9604 /* 24824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
9605 /* 24829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9606 /* 24832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9607 /* 24835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9608 /* 24838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9609 /* 24842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9610 /* 24846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9611 /* 24850 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8036:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9612 /* 24850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
9613 /* 24853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9614 /* 24855 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9615 /* 24857 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9616 /* 24859 */ GIR_RootConstrainSelectedInstOperands,
9617 /* 24860 */ // GIR_Coverage, 591,
9618 /* 24860 */ GIR_EraseRootFromParent_Done,
9619 /* 24861 */ // Label 845: @24861
9620 /* 24861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(24905), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 592 //
9621 /* 24868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
9622 /* 24873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9623 /* 24876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9624 /* 24879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9625 /* 24882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9626 /* 24886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9627 /* 24890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9628 /* 24894 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8038:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9629 /* 24894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
9630 /* 24897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9631 /* 24899 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9632 /* 24901 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9633 /* 24903 */ GIR_RootConstrainSelectedInstOperands,
9634 /* 24904 */ // GIR_Coverage, 592,
9635 /* 24904 */ GIR_EraseRootFromParent_Done,
9636 /* 24905 */ // Label 846: @24905
9637 /* 24905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(24949), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 593 //
9638 /* 24912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
9639 /* 24917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9640 /* 24920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9641 /* 24923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9642 /* 24926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9643 /* 24930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9644 /* 24934 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9645 /* 24938 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8039:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9646 /* 24938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
9647 /* 24941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9648 /* 24943 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9649 /* 24945 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9650 /* 24947 */ GIR_RootConstrainSelectedInstOperands,
9651 /* 24948 */ // GIR_Coverage, 593,
9652 /* 24948 */ GIR_EraseRootFromParent_Done,
9653 /* 24949 */ // Label 847: @24949
9654 /* 24949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 848*/ GIMT_Encode4(24993), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 594 //
9655 /* 24956 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
9656 /* 24961 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9657 /* 24964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9658 /* 24967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9659 /* 24970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9660 /* 24974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9661 /* 24978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9662 /* 24982 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8037:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9663 /* 24982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
9664 /* 24985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9665 /* 24987 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9666 /* 24989 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9667 /* 24991 */ GIR_RootConstrainSelectedInstOperands,
9668 /* 24992 */ // GIR_Coverage, 594,
9669 /* 24992 */ GIR_EraseRootFromParent_Done,
9670 /* 24993 */ // Label 848: @24993
9671 /* 24993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 849*/ GIMT_Encode4(25037), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 595 //
9672 /* 25000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
9673 /* 25005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9674 /* 25008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9675 /* 25011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9676 /* 25014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9677 /* 25018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9678 /* 25022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9679 /* 25026 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8040:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9680 /* 25026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
9681 /* 25029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9682 /* 25031 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9683 /* 25033 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9684 /* 25035 */ GIR_RootConstrainSelectedInstOperands,
9685 /* 25036 */ // GIR_Coverage, 595,
9686 /* 25036 */ GIR_EraseRootFromParent_Done,
9687 /* 25037 */ // Label 849: @25037
9688 /* 25037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 850*/ GIMT_Encode4(25081), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 596 //
9689 /* 25044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
9690 /* 25049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9691 /* 25052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9692 /* 25055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9693 /* 25058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9694 /* 25062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9695 /* 25066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9696 /* 25070 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8042:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9697 /* 25070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
9698 /* 25073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9699 /* 25075 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9700 /* 25077 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9701 /* 25079 */ GIR_RootConstrainSelectedInstOperands,
9702 /* 25080 */ // GIR_Coverage, 596,
9703 /* 25080 */ GIR_EraseRootFromParent_Done,
9704 /* 25081 */ // Label 850: @25081
9705 /* 25081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 851*/ GIMT_Encode4(25125), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 597 //
9706 /* 25088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
9707 /* 25093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9708 /* 25096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9709 /* 25099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9710 /* 25102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9711 /* 25106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9712 /* 25110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9713 /* 25114 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8043:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9714 /* 25114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
9715 /* 25117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9716 /* 25119 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9717 /* 25121 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9718 /* 25123 */ GIR_RootConstrainSelectedInstOperands,
9719 /* 25124 */ // GIR_Coverage, 597,
9720 /* 25124 */ GIR_EraseRootFromParent_Done,
9721 /* 25125 */ // Label 851: @25125
9722 /* 25125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 852*/ GIMT_Encode4(25169), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 598 //
9723 /* 25132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
9724 /* 25137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9725 /* 25140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9726 /* 25143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9727 /* 25146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9728 /* 25150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9729 /* 25154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9730 /* 25158 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8041:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9731 /* 25158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
9732 /* 25161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9733 /* 25163 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9734 /* 25165 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9735 /* 25167 */ GIR_RootConstrainSelectedInstOperands,
9736 /* 25168 */ // GIR_Coverage, 598,
9737 /* 25168 */ GIR_EraseRootFromParent_Done,
9738 /* 25169 */ // Label 852: @25169
9739 /* 25169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 853*/ GIMT_Encode4(25213), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 599 //
9740 /* 25176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
9741 /* 25181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9742 /* 25184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9743 /* 25187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9744 /* 25190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9745 /* 25194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9746 /* 25198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9747 /* 25202 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8044:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9748 /* 25202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
9749 /* 25205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9750 /* 25207 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9751 /* 25209 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9752 /* 25211 */ GIR_RootConstrainSelectedInstOperands,
9753 /* 25212 */ // GIR_Coverage, 599,
9754 /* 25212 */ GIR_EraseRootFromParent_Done,
9755 /* 25213 */ // Label 853: @25213
9756 /* 25213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 854*/ GIMT_Encode4(25257), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 600 //
9757 /* 25220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
9758 /* 25225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9759 /* 25228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9760 /* 25231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9761 /* 25234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9762 /* 25238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9763 /* 25242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9764 /* 25246 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8046:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9765 /* 25246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
9766 /* 25249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9767 /* 25251 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9768 /* 25253 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9769 /* 25255 */ GIR_RootConstrainSelectedInstOperands,
9770 /* 25256 */ // GIR_Coverage, 600,
9771 /* 25256 */ GIR_EraseRootFromParent_Done,
9772 /* 25257 */ // Label 854: @25257
9773 /* 25257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(25301), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 601 //
9774 /* 25264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
9775 /* 25269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9776 /* 25272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9777 /* 25275 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9778 /* 25278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9779 /* 25282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9780 /* 25286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9781 /* 25290 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8047:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9782 /* 25290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
9783 /* 25293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9784 /* 25295 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9785 /* 25297 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9786 /* 25299 */ GIR_RootConstrainSelectedInstOperands,
9787 /* 25300 */ // GIR_Coverage, 601,
9788 /* 25300 */ GIR_EraseRootFromParent_Done,
9789 /* 25301 */ // Label 855: @25301
9790 /* 25301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(25345), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 602 //
9791 /* 25308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
9792 /* 25313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9793 /* 25316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9794 /* 25319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9795 /* 25322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9796 /* 25326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9797 /* 25330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9798 /* 25334 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8045:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9799 /* 25334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
9800 /* 25337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9801 /* 25339 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9802 /* 25341 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9803 /* 25343 */ GIR_RootConstrainSelectedInstOperands,
9804 /* 25344 */ // GIR_Coverage, 602,
9805 /* 25344 */ GIR_EraseRootFromParent_Done,
9806 /* 25345 */ // Label 856: @25345
9807 /* 25345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(25389), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 603 //
9808 /* 25352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
9809 /* 25357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9810 /* 25360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9811 /* 25363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9812 /* 25366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9813 /* 25370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9814 /* 25374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9815 /* 25378 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8048:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9816 /* 25378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
9817 /* 25381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9818 /* 25383 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9819 /* 25385 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9820 /* 25387 */ GIR_RootConstrainSelectedInstOperands,
9821 /* 25388 */ // GIR_Coverage, 603,
9822 /* 25388 */ GIR_EraseRootFromParent_Done,
9823 /* 25389 */ // Label 857: @25389
9824 /* 25389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 858*/ GIMT_Encode4(25433), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 604 //
9825 /* 25396 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
9826 /* 25401 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9827 /* 25404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9828 /* 25407 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9829 /* 25410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9830 /* 25414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9831 /* 25418 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9832 /* 25422 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8050:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9833 /* 25422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
9834 /* 25425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9835 /* 25427 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9836 /* 25429 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9837 /* 25431 */ GIR_RootConstrainSelectedInstOperands,
9838 /* 25432 */ // GIR_Coverage, 604,
9839 /* 25432 */ GIR_EraseRootFromParent_Done,
9840 /* 25433 */ // Label 858: @25433
9841 /* 25433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 859*/ GIMT_Encode4(25477), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 605 //
9842 /* 25440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
9843 /* 25445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9844 /* 25448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9845 /* 25451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9846 /* 25454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9847 /* 25458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9848 /* 25462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9849 /* 25466 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8051:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9850 /* 25466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
9851 /* 25469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9852 /* 25471 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9853 /* 25473 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9854 /* 25475 */ GIR_RootConstrainSelectedInstOperands,
9855 /* 25476 */ // GIR_Coverage, 605,
9856 /* 25476 */ GIR_EraseRootFromParent_Done,
9857 /* 25477 */ // Label 859: @25477
9858 /* 25477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(25521), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 606 //
9859 /* 25484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
9860 /* 25489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9861 /* 25492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9862 /* 25495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9863 /* 25498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9864 /* 25502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9865 /* 25506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9866 /* 25510 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8049:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9867 /* 25510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
9868 /* 25513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9869 /* 25515 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9870 /* 25517 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9871 /* 25519 */ GIR_RootConstrainSelectedInstOperands,
9872 /* 25520 */ // GIR_Coverage, 606,
9873 /* 25520 */ GIR_EraseRootFromParent_Done,
9874 /* 25521 */ // Label 860: @25521
9875 /* 25521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(25565), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 715 //
9876 /* 25528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
9877 /* 25533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9878 /* 25536 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9879 /* 25539 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9880 /* 25542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9881 /* 25546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9882 /* 25550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9883 /* 25554 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8183:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9884 /* 25554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
9885 /* 25557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9886 /* 25559 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9887 /* 25561 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9888 /* 25563 */ GIR_RootConstrainSelectedInstOperands,
9889 /* 25564 */ // GIR_Coverage, 715,
9890 /* 25564 */ GIR_EraseRootFromParent_Done,
9891 /* 25565 */ // Label 861: @25565
9892 /* 25565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(25609), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 716 //
9893 /* 25572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
9894 /* 25577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9895 /* 25580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9896 /* 25583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9897 /* 25586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9898 /* 25590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9899 /* 25594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9900 /* 25598 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8184:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9901 /* 25598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
9902 /* 25601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9903 /* 25603 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9904 /* 25605 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9905 /* 25607 */ GIR_RootConstrainSelectedInstOperands,
9906 /* 25608 */ // GIR_Coverage, 716,
9907 /* 25608 */ GIR_EraseRootFromParent_Done,
9908 /* 25609 */ // Label 862: @25609
9909 /* 25609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 863*/ GIMT_Encode4(25653), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 717 //
9910 /* 25616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
9911 /* 25621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9912 /* 25624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9913 /* 25627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9914 /* 25630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9915 /* 25634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9916 /* 25638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9917 /* 25642 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8182:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9918 /* 25642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
9919 /* 25645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9920 /* 25647 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9921 /* 25649 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9922 /* 25651 */ GIR_RootConstrainSelectedInstOperands,
9923 /* 25652 */ // GIR_Coverage, 717,
9924 /* 25652 */ GIR_EraseRootFromParent_Done,
9925 /* 25653 */ // Label 863: @25653
9926 /* 25653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 864*/ GIMT_Encode4(25697), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 718 //
9927 /* 25660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
9928 /* 25665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9929 /* 25668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9930 /* 25671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9931 /* 25674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9932 /* 25678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9933 /* 25682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9934 /* 25686 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8186:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9935 /* 25686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
9936 /* 25689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9937 /* 25691 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9938 /* 25693 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9939 /* 25695 */ GIR_RootConstrainSelectedInstOperands,
9940 /* 25696 */ // GIR_Coverage, 718,
9941 /* 25696 */ GIR_EraseRootFromParent_Done,
9942 /* 25697 */ // Label 864: @25697
9943 /* 25697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(25741), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 719 //
9944 /* 25704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
9945 /* 25709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9946 /* 25712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9947 /* 25715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9948 /* 25718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9949 /* 25722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9950 /* 25726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9951 /* 25730 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8187:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9952 /* 25730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
9953 /* 25733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9954 /* 25735 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9955 /* 25737 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9956 /* 25739 */ GIR_RootConstrainSelectedInstOperands,
9957 /* 25740 */ // GIR_Coverage, 719,
9958 /* 25740 */ GIR_EraseRootFromParent_Done,
9959 /* 25741 */ // Label 865: @25741
9960 /* 25741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 866*/ GIMT_Encode4(25785), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 720 //
9961 /* 25748 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
9962 /* 25753 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9963 /* 25756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9964 /* 25759 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9965 /* 25762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9966 /* 25766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9967 /* 25770 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9968 /* 25774 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8185:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9969 /* 25774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
9970 /* 25777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9971 /* 25779 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9972 /* 25781 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9973 /* 25783 */ GIR_RootConstrainSelectedInstOperands,
9974 /* 25784 */ // GIR_Coverage, 720,
9975 /* 25784 */ GIR_EraseRootFromParent_Done,
9976 /* 25785 */ // Label 866: @25785
9977 /* 25785 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 867*/ GIMT_Encode4(25829), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 735 //
9978 /* 25792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
9979 /* 25797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9980 /* 25800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9981 /* 25803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9982 /* 25806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9983 /* 25810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9984 /* 25814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9985 /* 25818 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8225:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9986 /* 25818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
9987 /* 25821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9988 /* 25823 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9989 /* 25825 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9990 /* 25827 */ GIR_RootConstrainSelectedInstOperands,
9991 /* 25828 */ // GIR_Coverage, 735,
9992 /* 25828 */ GIR_EraseRootFromParent_Done,
9993 /* 25829 */ // Label 867: @25829
9994 /* 25829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(25873), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 736 //
9995 /* 25836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
9996 /* 25841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9997 /* 25844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9998 /* 25847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9999 /* 25850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10000 /* 25854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10001 /* 25858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10002 /* 25862 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8224:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10003 /* 25862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
10004 /* 25865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10005 /* 25867 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10006 /* 25869 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10007 /* 25871 */ GIR_RootConstrainSelectedInstOperands,
10008 /* 25872 */ // GIR_Coverage, 736,
10009 /* 25872 */ GIR_EraseRootFromParent_Done,
10010 /* 25873 */ // Label 868: @25873
10011 /* 25873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 869*/ GIMT_Encode4(25917), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 761 //
10012 /* 25880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
10013 /* 25885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10014 /* 25888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10015 /* 25891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10016 /* 25894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10017 /* 25898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10018 /* 25902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10019 /* 25906 */ // (intrinsic_wo_chain:{ *:[v8f16] } 8250:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10020 /* 25906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
10021 /* 25909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10022 /* 25911 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10023 /* 25913 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10024 /* 25915 */ GIR_RootConstrainSelectedInstOperands,
10025 /* 25916 */ // GIR_Coverage, 761,
10026 /* 25916 */ GIR_EraseRootFromParent_Done,
10027 /* 25917 */ // Label 869: @25917
10028 /* 25917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 870*/ GIMT_Encode4(25961), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 762 //
10029 /* 25924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
10030 /* 25929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10031 /* 25932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10032 /* 25935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10033 /* 25938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10034 /* 25942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10035 /* 25946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10036 /* 25950 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10037 /* 25950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
10038 /* 25953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10039 /* 25955 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10040 /* 25957 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10041 /* 25959 */ GIR_RootConstrainSelectedInstOperands,
10042 /* 25960 */ // GIR_Coverage, 762,
10043 /* 25960 */ GIR_EraseRootFromParent_Done,
10044 /* 25961 */ // Label 870: @25961
10045 /* 25961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(26005), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 789 //
10046 /* 25968 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
10047 /* 25973 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10048 /* 25976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10049 /* 25979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10050 /* 25982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10051 /* 25986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10052 /* 25990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10053 /* 25994 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10054 /* 25994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
10055 /* 25997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10056 /* 25999 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10057 /* 26001 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10058 /* 26003 */ GIR_RootConstrainSelectedInstOperands,
10059 /* 26004 */ // GIR_Coverage, 789,
10060 /* 26004 */ GIR_EraseRootFromParent_Done,
10061 /* 26005 */ // Label 871: @26005
10062 /* 26005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(26049), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 790 //
10063 /* 26012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
10064 /* 26017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10065 /* 26020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10066 /* 26023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10067 /* 26026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10068 /* 26030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10069 /* 26034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10070 /* 26038 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8276:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10071 /* 26038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
10072 /* 26041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10073 /* 26043 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10074 /* 26045 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10075 /* 26047 */ GIR_RootConstrainSelectedInstOperands,
10076 /* 26048 */ // GIR_Coverage, 790,
10077 /* 26048 */ GIR_EraseRootFromParent_Done,
10078 /* 26049 */ // Label 872: @26049
10079 /* 26049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(26093), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 791 //
10080 /* 26056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
10081 /* 26061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10082 /* 26064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10083 /* 26067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10084 /* 26070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10085 /* 26074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10086 /* 26078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10087 /* 26082 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8275:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10088 /* 26082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
10089 /* 26085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10090 /* 26087 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10091 /* 26089 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10092 /* 26091 */ GIR_RootConstrainSelectedInstOperands,
10093 /* 26092 */ // GIR_Coverage, 791,
10094 /* 26092 */ GIR_EraseRootFromParent_Done,
10095 /* 26093 */ // Label 873: @26093
10096 /* 26093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(26137), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 792 //
10097 /* 26100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
10098 /* 26105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10099 /* 26108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10100 /* 26111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10101 /* 26114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10102 /* 26118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10103 /* 26122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10104 /* 26126 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10105 /* 26126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
10106 /* 26129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10107 /* 26131 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10108 /* 26133 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10109 /* 26135 */ GIR_RootConstrainSelectedInstOperands,
10110 /* 26136 */ // GIR_Coverage, 792,
10111 /* 26136 */ GIR_EraseRootFromParent_Done,
10112 /* 26137 */ // Label 874: @26137
10113 /* 26137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(26181), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 793 //
10114 /* 26144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
10115 /* 26149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10116 /* 26152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10117 /* 26155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10118 /* 26158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10119 /* 26162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10120 /* 26166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10121 /* 26170 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8281:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10122 /* 26170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
10123 /* 26173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10124 /* 26175 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10125 /* 26177 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10126 /* 26179 */ GIR_RootConstrainSelectedInstOperands,
10127 /* 26180 */ // GIR_Coverage, 793,
10128 /* 26180 */ GIR_EraseRootFromParent_Done,
10129 /* 26181 */ // Label 875: @26181
10130 /* 26181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(26225), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 794 //
10131 /* 26188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
10132 /* 26193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10133 /* 26196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10134 /* 26199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10135 /* 26202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10136 /* 26206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10137 /* 26210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10138 /* 26214 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8280:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10139 /* 26214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
10140 /* 26217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10141 /* 26219 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10142 /* 26221 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10143 /* 26223 */ GIR_RootConstrainSelectedInstOperands,
10144 /* 26224 */ // GIR_Coverage, 794,
10145 /* 26224 */ GIR_EraseRootFromParent_Done,
10146 /* 26225 */ // Label 876: @26225
10147 /* 26225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(26269), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 795 //
10148 /* 26232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
10149 /* 26237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10150 /* 26240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10151 /* 26243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10152 /* 26246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10153 /* 26250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10154 /* 26254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10155 /* 26258 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8279:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10156 /* 26258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
10157 /* 26261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10158 /* 26263 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10159 /* 26265 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10160 /* 26267 */ GIR_RootConstrainSelectedInstOperands,
10161 /* 26268 */ // GIR_Coverage, 795,
10162 /* 26268 */ GIR_EraseRootFromParent_Done,
10163 /* 26269 */ // Label 877: @26269
10164 /* 26269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 878*/ GIMT_Encode4(26313), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 796 //
10165 /* 26276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
10166 /* 26281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10167 /* 26284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10168 /* 26287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10169 /* 26290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10170 /* 26294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10171 /* 26298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10172 /* 26302 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10173 /* 26302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
10174 /* 26305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10175 /* 26307 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10176 /* 26309 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10177 /* 26311 */ GIR_RootConstrainSelectedInstOperands,
10178 /* 26312 */ // GIR_Coverage, 796,
10179 /* 26312 */ GIR_EraseRootFromParent_Done,
10180 /* 26313 */ // Label 878: @26313
10181 /* 26313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 879*/ GIMT_Encode4(26357), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 807 //
10182 /* 26320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
10183 /* 26325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10184 /* 26328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10185 /* 26331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10186 /* 26334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10187 /* 26338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10188 /* 26342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10189 /* 26346 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8293:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10190 /* 26346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
10191 /* 26349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10192 /* 26351 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10193 /* 26353 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10194 /* 26355 */ GIR_RootConstrainSelectedInstOperands,
10195 /* 26356 */ // GIR_Coverage, 807,
10196 /* 26356 */ GIR_EraseRootFromParent_Done,
10197 /* 26357 */ // Label 879: @26357
10198 /* 26357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(26401), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 808 //
10199 /* 26364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
10200 /* 26369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10201 /* 26372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10202 /* 26375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10203 /* 26378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10204 /* 26382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10205 /* 26386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10206 /* 26390 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8292:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10207 /* 26390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
10208 /* 26393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10209 /* 26395 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10210 /* 26397 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10211 /* 26399 */ GIR_RootConstrainSelectedInstOperands,
10212 /* 26400 */ // GIR_Coverage, 808,
10213 /* 26400 */ GIR_EraseRootFromParent_Done,
10214 /* 26401 */ // Label 880: @26401
10215 /* 26401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(26445), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 809 //
10216 /* 26408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
10217 /* 26413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10218 /* 26416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10219 /* 26419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10220 /* 26422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10221 /* 26426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10222 /* 26430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10223 /* 26434 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8295:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10224 /* 26434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
10225 /* 26437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10226 /* 26439 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10227 /* 26441 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10228 /* 26443 */ GIR_RootConstrainSelectedInstOperands,
10229 /* 26444 */ // GIR_Coverage, 809,
10230 /* 26444 */ GIR_EraseRootFromParent_Done,
10231 /* 26445 */ // Label 881: @26445
10232 /* 26445 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(26489), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 810 //
10233 /* 26452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
10234 /* 26457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10235 /* 26460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10236 /* 26463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10237 /* 26466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10238 /* 26470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10239 /* 26474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10240 /* 26478 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10241 /* 26478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
10242 /* 26481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10243 /* 26483 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10244 /* 26485 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10245 /* 26487 */ GIR_RootConstrainSelectedInstOperands,
10246 /* 26488 */ // GIR_Coverage, 810,
10247 /* 26488 */ GIR_EraseRootFromParent_Done,
10248 /* 26489 */ // Label 882: @26489
10249 /* 26489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(26533), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 811 //
10250 /* 26496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
10251 /* 26501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10252 /* 26504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10253 /* 26507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10254 /* 26510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10255 /* 26514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10256 /* 26518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10257 /* 26522 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8297:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10258 /* 26522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
10259 /* 26525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10260 /* 26527 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10261 /* 26529 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10262 /* 26531 */ GIR_RootConstrainSelectedInstOperands,
10263 /* 26532 */ // GIR_Coverage, 811,
10264 /* 26532 */ GIR_EraseRootFromParent_Done,
10265 /* 26533 */ // Label 883: @26533
10266 /* 26533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(26577), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 812 //
10267 /* 26540 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
10268 /* 26545 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10269 /* 26548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10270 /* 26551 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10271 /* 26554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10272 /* 26558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10273 /* 26562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10274 /* 26566 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8296:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10275 /* 26566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
10276 /* 26569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10277 /* 26571 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10278 /* 26573 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10279 /* 26575 */ GIR_RootConstrainSelectedInstOperands,
10280 /* 26576 */ // GIR_Coverage, 812,
10281 /* 26576 */ GIR_EraseRootFromParent_Done,
10282 /* 26577 */ // Label 884: @26577
10283 /* 26577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(26621), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 813 //
10284 /* 26584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
10285 /* 26589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10286 /* 26592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10287 /* 26595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10288 /* 26598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10289 /* 26602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10290 /* 26606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10291 /* 26610 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8299:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10292 /* 26610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
10293 /* 26613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10294 /* 26615 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10295 /* 26617 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10296 /* 26619 */ GIR_RootConstrainSelectedInstOperands,
10297 /* 26620 */ // GIR_Coverage, 813,
10298 /* 26620 */ GIR_EraseRootFromParent_Done,
10299 /* 26621 */ // Label 885: @26621
10300 /* 26621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(26665), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 814 //
10301 /* 26628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
10302 /* 26633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10303 /* 26636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10304 /* 26639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10305 /* 26642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10306 /* 26646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10307 /* 26650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10308 /* 26654 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8298:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10309 /* 26654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
10310 /* 26657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10311 /* 26659 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10312 /* 26661 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10313 /* 26663 */ GIR_RootConstrainSelectedInstOperands,
10314 /* 26664 */ // GIR_Coverage, 814,
10315 /* 26664 */ GIR_EraseRootFromParent_Done,
10316 /* 26665 */ // Label 886: @26665
10317 /* 26665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 887*/ GIMT_Encode4(26709), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 815 //
10318 /* 26672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
10319 /* 26677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10320 /* 26680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10321 /* 26683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10322 /* 26686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10323 /* 26690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10324 /* 26694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10325 /* 26698 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8301:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10326 /* 26698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
10327 /* 26701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10328 /* 26703 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10329 /* 26705 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10330 /* 26707 */ GIR_RootConstrainSelectedInstOperands,
10331 /* 26708 */ // GIR_Coverage, 815,
10332 /* 26708 */ GIR_EraseRootFromParent_Done,
10333 /* 26709 */ // Label 887: @26709
10334 /* 26709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 888*/ GIMT_Encode4(26753), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 816 //
10335 /* 26716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
10336 /* 26721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10337 /* 26724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10338 /* 26727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10339 /* 26730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10340 /* 26734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10341 /* 26738 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10342 /* 26742 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8300:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10343 /* 26742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
10344 /* 26745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10345 /* 26747 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10346 /* 26749 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10347 /* 26751 */ GIR_RootConstrainSelectedInstOperands,
10348 /* 26752 */ // GIR_Coverage, 816,
10349 /* 26752 */ GIR_EraseRootFromParent_Done,
10350 /* 26753 */ // Label 888: @26753
10351 /* 26753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(26797), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 817 //
10352 /* 26760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
10353 /* 26765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10354 /* 26768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10355 /* 26771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10356 /* 26774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10357 /* 26778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10358 /* 26782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10359 /* 26786 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8303:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10360 /* 26786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
10361 /* 26789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10362 /* 26791 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10363 /* 26793 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10364 /* 26795 */ GIR_RootConstrainSelectedInstOperands,
10365 /* 26796 */ // GIR_Coverage, 817,
10366 /* 26796 */ GIR_EraseRootFromParent_Done,
10367 /* 26797 */ // Label 889: @26797
10368 /* 26797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(26841), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 818 //
10369 /* 26804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
10370 /* 26809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10371 /* 26812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10372 /* 26815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10373 /* 26818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10374 /* 26822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10375 /* 26826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10376 /* 26830 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8302:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10377 /* 26830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
10378 /* 26833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10379 /* 26835 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10380 /* 26837 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10381 /* 26839 */ GIR_RootConstrainSelectedInstOperands,
10382 /* 26840 */ // GIR_Coverage, 818,
10383 /* 26840 */ GIR_EraseRootFromParent_Done,
10384 /* 26841 */ // Label 890: @26841
10385 /* 26841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(26885), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 823 //
10386 /* 26848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10387 /* 26853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10388 /* 26856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10389 /* 26859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10390 /* 26862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10391 /* 26866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10392 /* 26870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10393 /* 26874 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10394 /* 26874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
10395 /* 26877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10396 /* 26879 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10397 /* 26881 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10398 /* 26883 */ GIR_RootConstrainSelectedInstOperands,
10399 /* 26884 */ // GIR_Coverage, 823,
10400 /* 26884 */ GIR_EraseRootFromParent_Done,
10401 /* 26885 */ // Label 891: @26885
10402 /* 26885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(26929), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 824 //
10403 /* 26892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10404 /* 26897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10405 /* 26900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10406 /* 26903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10407 /* 26906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10408 /* 26910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10409 /* 26914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10410 /* 26918 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8308:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10411 /* 26918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
10412 /* 26921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10413 /* 26923 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10414 /* 26925 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10415 /* 26927 */ GIR_RootConstrainSelectedInstOperands,
10416 /* 26928 */ // GIR_Coverage, 824,
10417 /* 26928 */ GIR_EraseRootFromParent_Done,
10418 /* 26929 */ // Label 892: @26929
10419 /* 26929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(26973), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 825 //
10420 /* 26936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
10421 /* 26941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10422 /* 26944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10423 /* 26947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10424 /* 26950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10425 /* 26954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10426 /* 26958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10427 /* 26962 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8311:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10428 /* 26962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
10429 /* 26965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10430 /* 26967 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10431 /* 26969 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10432 /* 26971 */ GIR_RootConstrainSelectedInstOperands,
10433 /* 26972 */ // GIR_Coverage, 825,
10434 /* 26972 */ GIR_EraseRootFromParent_Done,
10435 /* 26973 */ // Label 893: @26973
10436 /* 26973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(27017), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 826 //
10437 /* 26980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
10438 /* 26985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10439 /* 26988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10440 /* 26991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10441 /* 26994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10442 /* 26998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10443 /* 27002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10444 /* 27006 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8310:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10445 /* 27006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
10446 /* 27009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10447 /* 27011 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10448 /* 27013 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10449 /* 27015 */ GIR_RootConstrainSelectedInstOperands,
10450 /* 27016 */ // GIR_Coverage, 826,
10451 /* 27016 */ GIR_EraseRootFromParent_Done,
10452 /* 27017 */ // Label 894: @27017
10453 /* 27017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(27061), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 827 //
10454 /* 27024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
10455 /* 27029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10456 /* 27032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10457 /* 27035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10458 /* 27038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10459 /* 27042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10460 /* 27046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10461 /* 27050 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8313:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10462 /* 27050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
10463 /* 27053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10464 /* 27055 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10465 /* 27057 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10466 /* 27059 */ GIR_RootConstrainSelectedInstOperands,
10467 /* 27060 */ // GIR_Coverage, 827,
10468 /* 27060 */ GIR_EraseRootFromParent_Done,
10469 /* 27061 */ // Label 895: @27061
10470 /* 27061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 896*/ GIMT_Encode4(27105), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 828 //
10471 /* 27068 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
10472 /* 27073 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10473 /* 27076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10474 /* 27079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10475 /* 27082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10476 /* 27086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10477 /* 27090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10478 /* 27094 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8312:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10479 /* 27094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
10480 /* 27097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10481 /* 27099 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10482 /* 27101 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10483 /* 27103 */ GIR_RootConstrainSelectedInstOperands,
10484 /* 27104 */ // GIR_Coverage, 828,
10485 /* 27104 */ GIR_EraseRootFromParent_Done,
10486 /* 27105 */ // Label 896: @27105
10487 /* 27105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 897*/ GIMT_Encode4(27149), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 829 //
10488 /* 27112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
10489 /* 27117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10490 /* 27120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10491 /* 27123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10492 /* 27126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10493 /* 27130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10494 /* 27134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10495 /* 27138 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8315:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10496 /* 27138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
10497 /* 27141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10498 /* 27143 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10499 /* 27145 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10500 /* 27147 */ GIR_RootConstrainSelectedInstOperands,
10501 /* 27148 */ // GIR_Coverage, 829,
10502 /* 27148 */ GIR_EraseRootFromParent_Done,
10503 /* 27149 */ // Label 897: @27149
10504 /* 27149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(27193), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 830 //
10505 /* 27156 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
10506 /* 27161 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10507 /* 27164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10508 /* 27167 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10509 /* 27170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10510 /* 27174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10511 /* 27178 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10512 /* 27182 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8314:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10513 /* 27182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
10514 /* 27185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10515 /* 27187 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10516 /* 27189 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10517 /* 27191 */ GIR_RootConstrainSelectedInstOperands,
10518 /* 27192 */ // GIR_Coverage, 830,
10519 /* 27192 */ GIR_EraseRootFromParent_Done,
10520 /* 27193 */ // Label 898: @27193
10521 /* 27193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(27237), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 831 //
10522 /* 27200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
10523 /* 27205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10524 /* 27208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10525 /* 27211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10526 /* 27214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10527 /* 27218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10528 /* 27222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10529 /* 27226 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8317:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10530 /* 27226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
10531 /* 27229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10532 /* 27231 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10533 /* 27233 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10534 /* 27235 */ GIR_RootConstrainSelectedInstOperands,
10535 /* 27236 */ // GIR_Coverage, 831,
10536 /* 27236 */ GIR_EraseRootFromParent_Done,
10537 /* 27237 */ // Label 899: @27237
10538 /* 27237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(27281), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 832 //
10539 /* 27244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
10540 /* 27249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10541 /* 27252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10542 /* 27255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10543 /* 27258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10544 /* 27262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10545 /* 27266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10546 /* 27270 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8316:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10547 /* 27270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
10548 /* 27273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10549 /* 27275 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10550 /* 27277 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10551 /* 27279 */ GIR_RootConstrainSelectedInstOperands,
10552 /* 27280 */ // GIR_Coverage, 832,
10553 /* 27280 */ GIR_EraseRootFromParent_Done,
10554 /* 27281 */ // Label 900: @27281
10555 /* 27281 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(27325), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 837 //
10556 /* 27288 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
10557 /* 27293 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10558 /* 27296 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10559 /* 27299 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10560 /* 27302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10561 /* 27306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10562 /* 27310 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10563 /* 27314 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8322:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10564 /* 27314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
10565 /* 27317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10566 /* 27319 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10567 /* 27321 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10568 /* 27323 */ GIR_RootConstrainSelectedInstOperands,
10569 /* 27324 */ // GIR_Coverage, 837,
10570 /* 27324 */ GIR_EraseRootFromParent_Done,
10571 /* 27325 */ // Label 901: @27325
10572 /* 27325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(27369), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 838 //
10573 /* 27332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
10574 /* 27337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10575 /* 27340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10576 /* 27343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10577 /* 27346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10578 /* 27350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10579 /* 27354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10580 /* 27358 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8323:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10581 /* 27358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
10582 /* 27361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10583 /* 27363 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10584 /* 27365 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10585 /* 27367 */ GIR_RootConstrainSelectedInstOperands,
10586 /* 27368 */ // GIR_Coverage, 838,
10587 /* 27368 */ GIR_EraseRootFromParent_Done,
10588 /* 27369 */ // Label 902: @27369
10589 /* 27369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(27413), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 843 //
10590 /* 27376 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
10591 /* 27381 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10592 /* 27384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10593 /* 27387 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10594 /* 27390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10595 /* 27394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10596 /* 27398 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10597 /* 27402 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8329:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10598 /* 27402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
10599 /* 27405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10600 /* 27407 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10601 /* 27409 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10602 /* 27411 */ GIR_RootConstrainSelectedInstOperands,
10603 /* 27412 */ // GIR_Coverage, 843,
10604 /* 27412 */ GIR_EraseRootFromParent_Done,
10605 /* 27413 */ // Label 903: @27413
10606 /* 27413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(27457), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 844 //
10607 /* 27420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
10608 /* 27425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10609 /* 27428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10610 /* 27431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10611 /* 27434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10612 /* 27438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10613 /* 27442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10614 /* 27446 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8330:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10615 /* 27446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
10616 /* 27449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10617 /* 27451 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10618 /* 27453 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10619 /* 27455 */ GIR_RootConstrainSelectedInstOperands,
10620 /* 27456 */ // GIR_Coverage, 844,
10621 /* 27456 */ GIR_EraseRootFromParent_Done,
10622 /* 27457 */ // Label 904: @27457
10623 /* 27457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 905*/ GIMT_Encode4(27501), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 845 //
10624 /* 27464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
10625 /* 27469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10626 /* 27472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10627 /* 27475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10628 /* 27478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10629 /* 27482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10630 /* 27486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10631 /* 27490 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8328:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10632 /* 27490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
10633 /* 27493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10634 /* 27495 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10635 /* 27497 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10636 /* 27499 */ GIR_RootConstrainSelectedInstOperands,
10637 /* 27500 */ // GIR_Coverage, 845,
10638 /* 27500 */ GIR_EraseRootFromParent_Done,
10639 /* 27501 */ // Label 905: @27501
10640 /* 27501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 906*/ GIMT_Encode4(27545), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 846 //
10641 /* 27508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
10642 /* 27513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10643 /* 27516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10644 /* 27519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10645 /* 27522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10646 /* 27526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10647 /* 27530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10648 /* 27534 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8332:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10649 /* 27534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
10650 /* 27537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10651 /* 27539 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10652 /* 27541 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10653 /* 27543 */ GIR_RootConstrainSelectedInstOperands,
10654 /* 27544 */ // GIR_Coverage, 846,
10655 /* 27544 */ GIR_EraseRootFromParent_Done,
10656 /* 27545 */ // Label 906: @27545
10657 /* 27545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 907*/ GIMT_Encode4(27589), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 847 //
10658 /* 27552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
10659 /* 27557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10660 /* 27560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10661 /* 27563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10662 /* 27566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10663 /* 27570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10664 /* 27574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10665 /* 27578 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8333:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10666 /* 27578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
10667 /* 27581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10668 /* 27583 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10669 /* 27585 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10670 /* 27587 */ GIR_RootConstrainSelectedInstOperands,
10671 /* 27588 */ // GIR_Coverage, 847,
10672 /* 27588 */ GIR_EraseRootFromParent_Done,
10673 /* 27589 */ // Label 907: @27589
10674 /* 27589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 908*/ GIMT_Encode4(27633), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 848 //
10675 /* 27596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
10676 /* 27601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10677 /* 27604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10678 /* 27607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10679 /* 27610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10680 /* 27614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10681 /* 27618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10682 /* 27622 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8331:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10683 /* 27622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
10684 /* 27625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10685 /* 27627 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10686 /* 27629 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10687 /* 27631 */ GIR_RootConstrainSelectedInstOperands,
10688 /* 27632 */ // GIR_Coverage, 848,
10689 /* 27632 */ GIR_EraseRootFromParent_Done,
10690 /* 27633 */ // Label 908: @27633
10691 /* 27633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 909*/ GIMT_Encode4(27677), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 849 //
10692 /* 27640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
10693 /* 27645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10694 /* 27648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10695 /* 27651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10696 /* 27654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10697 /* 27658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10698 /* 27662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10699 /* 27666 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8335:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10700 /* 27666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
10701 /* 27669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10702 /* 27671 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10703 /* 27673 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10704 /* 27675 */ GIR_RootConstrainSelectedInstOperands,
10705 /* 27676 */ // GIR_Coverage, 849,
10706 /* 27676 */ GIR_EraseRootFromParent_Done,
10707 /* 27677 */ // Label 909: @27677
10708 /* 27677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 910*/ GIMT_Encode4(27721), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 850 //
10709 /* 27684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
10710 /* 27689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10711 /* 27692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10712 /* 27695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10713 /* 27698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10714 /* 27702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10715 /* 27706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10716 /* 27710 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8336:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10717 /* 27710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
10718 /* 27713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10719 /* 27715 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10720 /* 27717 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10721 /* 27719 */ GIR_RootConstrainSelectedInstOperands,
10722 /* 27720 */ // GIR_Coverage, 850,
10723 /* 27720 */ GIR_EraseRootFromParent_Done,
10724 /* 27721 */ // Label 910: @27721
10725 /* 27721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 911*/ GIMT_Encode4(27765), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 851 //
10726 /* 27728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
10727 /* 27733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10728 /* 27736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10729 /* 27739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10730 /* 27742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10731 /* 27746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10732 /* 27750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10733 /* 27754 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8334:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10734 /* 27754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
10735 /* 27757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10736 /* 27759 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10737 /* 27761 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10738 /* 27763 */ GIR_RootConstrainSelectedInstOperands,
10739 /* 27764 */ // GIR_Coverage, 851,
10740 /* 27764 */ GIR_EraseRootFromParent_Done,
10741 /* 27765 */ // Label 911: @27765
10742 /* 27765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(27809), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 852 //
10743 /* 27772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
10744 /* 27777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10745 /* 27780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10746 /* 27783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10747 /* 27786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10748 /* 27790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10749 /* 27794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10750 /* 27798 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8338:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10751 /* 27798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
10752 /* 27801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10753 /* 27803 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10754 /* 27805 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10755 /* 27807 */ GIR_RootConstrainSelectedInstOperands,
10756 /* 27808 */ // GIR_Coverage, 852,
10757 /* 27808 */ GIR_EraseRootFromParent_Done,
10758 /* 27809 */ // Label 912: @27809
10759 /* 27809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(27853), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 853 //
10760 /* 27816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
10761 /* 27821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10762 /* 27824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10763 /* 27827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10764 /* 27830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10765 /* 27834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10766 /* 27838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10767 /* 27842 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8339:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10768 /* 27842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
10769 /* 27845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10770 /* 27847 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10771 /* 27849 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10772 /* 27851 */ GIR_RootConstrainSelectedInstOperands,
10773 /* 27852 */ // GIR_Coverage, 853,
10774 /* 27852 */ GIR_EraseRootFromParent_Done,
10775 /* 27853 */ // Label 913: @27853
10776 /* 27853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(27897), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 854 //
10777 /* 27860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
10778 /* 27865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10779 /* 27868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10780 /* 27871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10781 /* 27874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10782 /* 27878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10783 /* 27882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10784 /* 27886 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8337:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10785 /* 27886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
10786 /* 27889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10787 /* 27891 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10788 /* 27893 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10789 /* 27895 */ GIR_RootConstrainSelectedInstOperands,
10790 /* 27896 */ // GIR_Coverage, 854,
10791 /* 27896 */ GIR_EraseRootFromParent_Done,
10792 /* 27897 */ // Label 914: @27897
10793 /* 27897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(27941), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 911 //
10794 /* 27904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
10795 /* 27909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10796 /* 27912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10797 /* 27915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10798 /* 27918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10799 /* 27922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10800 /* 27926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10801 /* 27930 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8393:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10802 /* 27930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
10803 /* 27933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10804 /* 27935 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10805 /* 27937 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10806 /* 27939 */ GIR_RootConstrainSelectedInstOperands,
10807 /* 27940 */ // GIR_Coverage, 911,
10808 /* 27940 */ GIR_EraseRootFromParent_Done,
10809 /* 27941 */ // Label 915: @27941
10810 /* 27941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(27985), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 912 //
10811 /* 27948 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
10812 /* 27953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10813 /* 27956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10814 /* 27959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10815 /* 27962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10816 /* 27966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10817 /* 27970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10818 /* 27974 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8395:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10819 /* 27974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
10820 /* 27977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10821 /* 27979 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10822 /* 27981 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10823 /* 27983 */ GIR_RootConstrainSelectedInstOperands,
10824 /* 27984 */ // GIR_Coverage, 912,
10825 /* 27984 */ GIR_EraseRootFromParent_Done,
10826 /* 27985 */ // Label 916: @27985
10827 /* 27985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(28029), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 913 //
10828 /* 27992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
10829 /* 27997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10830 /* 28000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10831 /* 28003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10832 /* 28006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10833 /* 28010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10834 /* 28014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10835 /* 28018 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8396:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10836 /* 28018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
10837 /* 28021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10838 /* 28023 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10839 /* 28025 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10840 /* 28027 */ GIR_RootConstrainSelectedInstOperands,
10841 /* 28028 */ // GIR_Coverage, 913,
10842 /* 28028 */ GIR_EraseRootFromParent_Done,
10843 /* 28029 */ // Label 917: @28029
10844 /* 28029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(28073), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 914 //
10845 /* 28036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
10846 /* 28041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10847 /* 28044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10848 /* 28047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10849 /* 28050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10850 /* 28054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10851 /* 28058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10852 /* 28062 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8394:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10853 /* 28062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
10854 /* 28065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10855 /* 28067 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10856 /* 28069 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10857 /* 28071 */ GIR_RootConstrainSelectedInstOperands,
10858 /* 28072 */ // GIR_Coverage, 914,
10859 /* 28072 */ GIR_EraseRootFromParent_Done,
10860 /* 28073 */ // Label 918: @28073
10861 /* 28073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 919*/ GIMT_Encode4(28117), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 931 //
10862 /* 28080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
10863 /* 28085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10864 /* 28088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10865 /* 28091 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10866 /* 28094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10867 /* 28098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10868 /* 28102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10869 /* 28106 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8413:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10870 /* 28106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
10871 /* 28109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10872 /* 28111 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10873 /* 28113 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10874 /* 28115 */ GIR_RootConstrainSelectedInstOperands,
10875 /* 28116 */ // GIR_Coverage, 931,
10876 /* 28116 */ GIR_EraseRootFromParent_Done,
10877 /* 28117 */ // Label 919: @28117
10878 /* 28117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 920*/ GIMT_Encode4(28161), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 932 //
10879 /* 28124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
10880 /* 28129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10881 /* 28132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10882 /* 28135 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10883 /* 28138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10884 /* 28142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10885 /* 28146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10886 /* 28150 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8415:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10887 /* 28150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
10888 /* 28153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10889 /* 28155 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10890 /* 28157 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10891 /* 28159 */ GIR_RootConstrainSelectedInstOperands,
10892 /* 28160 */ // GIR_Coverage, 932,
10893 /* 28160 */ GIR_EraseRootFromParent_Done,
10894 /* 28161 */ // Label 920: @28161
10895 /* 28161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(28205), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 933 //
10896 /* 28168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
10897 /* 28173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10898 /* 28176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10899 /* 28179 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10900 /* 28182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10901 /* 28186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10902 /* 28190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10903 /* 28194 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8416:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10904 /* 28194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
10905 /* 28197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10906 /* 28199 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10907 /* 28201 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10908 /* 28203 */ GIR_RootConstrainSelectedInstOperands,
10909 /* 28204 */ // GIR_Coverage, 933,
10910 /* 28204 */ GIR_EraseRootFromParent_Done,
10911 /* 28205 */ // Label 921: @28205
10912 /* 28205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(28249), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 934 //
10913 /* 28212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
10914 /* 28217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10915 /* 28220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10916 /* 28223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10917 /* 28226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10918 /* 28230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10919 /* 28234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10920 /* 28238 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8414:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10921 /* 28238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
10922 /* 28241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10923 /* 28243 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10924 /* 28245 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10925 /* 28247 */ GIR_RootConstrainSelectedInstOperands,
10926 /* 28248 */ // GIR_Coverage, 934,
10927 /* 28248 */ GIR_EraseRootFromParent_Done,
10928 /* 28249 */ // Label 922: @28249
10929 /* 28249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(28293), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 967 //
10930 /* 28256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
10931 /* 28261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10932 /* 28264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10933 /* 28267 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10934 /* 28270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10935 /* 28274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10936 /* 28278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10937 /* 28282 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8455:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10938 /* 28282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
10939 /* 28285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10940 /* 28287 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10941 /* 28289 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10942 /* 28291 */ GIR_RootConstrainSelectedInstOperands,
10943 /* 28292 */ // GIR_Coverage, 967,
10944 /* 28292 */ GIR_EraseRootFromParent_Done,
10945 /* 28293 */ // Label 923: @28293
10946 /* 28293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 924*/ GIMT_Encode4(28337), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 968 //
10947 /* 28300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
10948 /* 28305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10949 /* 28308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10950 /* 28311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10951 /* 28314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10952 /* 28318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10953 /* 28322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10954 /* 28326 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8456:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10955 /* 28326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
10956 /* 28329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10957 /* 28331 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10958 /* 28333 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10959 /* 28335 */ GIR_RootConstrainSelectedInstOperands,
10960 /* 28336 */ // GIR_Coverage, 968,
10961 /* 28336 */ GIR_EraseRootFromParent_Done,
10962 /* 28337 */ // Label 924: @28337
10963 /* 28337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 925*/ GIMT_Encode4(28381), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 969 //
10964 /* 28344 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
10965 /* 28349 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10966 /* 28352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10967 /* 28355 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10968 /* 28358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10969 /* 28362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10970 /* 28366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10971 /* 28370 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8466:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10972 /* 28370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
10973 /* 28373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10974 /* 28375 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10975 /* 28377 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10976 /* 28379 */ GIR_RootConstrainSelectedInstOperands,
10977 /* 28380 */ // GIR_Coverage, 969,
10978 /* 28380 */ GIR_EraseRootFromParent_Done,
10979 /* 28381 */ // Label 925: @28381
10980 /* 28381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(28425), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 970 //
10981 /* 28388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
10982 /* 28393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10983 /* 28396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10984 /* 28399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10985 /* 28402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10986 /* 28406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10987 /* 28410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10988 /* 28414 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8467:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10989 /* 28414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
10990 /* 28417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10991 /* 28419 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10992 /* 28421 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10993 /* 28423 */ GIR_RootConstrainSelectedInstOperands,
10994 /* 28424 */ // GIR_Coverage, 970,
10995 /* 28424 */ GIR_EraseRootFromParent_Done,
10996 /* 28425 */ // Label 926: @28425
10997 /* 28425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(28469), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1048 //
10998 /* 28432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
10999 /* 28437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11000 /* 28440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11001 /* 28443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11002 /* 28446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11003 /* 28450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11004 /* 28454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11005 /* 28458 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8580:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11006 /* 28458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
11007 /* 28461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11008 /* 28463 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11009 /* 28465 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11010 /* 28467 */ GIR_RootConstrainSelectedInstOperands,
11011 /* 28468 */ // GIR_Coverage, 1048,
11012 /* 28468 */ GIR_EraseRootFromParent_Done,
11013 /* 28469 */ // Label 927: @28469
11014 /* 28469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(28513), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1049 //
11015 /* 28476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
11016 /* 28481 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11017 /* 28484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11018 /* 28487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11019 /* 28490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11020 /* 28494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11021 /* 28498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11022 /* 28502 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8582:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11023 /* 28502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
11024 /* 28505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11025 /* 28507 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11026 /* 28509 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11027 /* 28511 */ GIR_RootConstrainSelectedInstOperands,
11028 /* 28512 */ // GIR_Coverage, 1049,
11029 /* 28512 */ GIR_EraseRootFromParent_Done,
11030 /* 28513 */ // Label 928: @28513
11031 /* 28513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(28557), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1050 //
11032 /* 28520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
11033 /* 28525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11034 /* 28528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11035 /* 28531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11036 /* 28534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11037 /* 28538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11038 /* 28542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11039 /* 28546 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8583:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11040 /* 28546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
11041 /* 28549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11042 /* 28551 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11043 /* 28553 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11044 /* 28555 */ GIR_RootConstrainSelectedInstOperands,
11045 /* 28556 */ // GIR_Coverage, 1050,
11046 /* 28556 */ GIR_EraseRootFromParent_Done,
11047 /* 28557 */ // Label 929: @28557
11048 /* 28557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(28601), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1051 //
11049 /* 28564 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
11050 /* 28569 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11051 /* 28572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11052 /* 28575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11053 /* 28578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11054 /* 28582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11055 /* 28586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11056 /* 28590 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8581:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11057 /* 28590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
11058 /* 28593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11059 /* 28595 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11060 /* 28597 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11061 /* 28599 */ GIR_RootConstrainSelectedInstOperands,
11062 /* 28600 */ // GIR_Coverage, 1051,
11063 /* 28600 */ GIR_EraseRootFromParent_Done,
11064 /* 28601 */ // Label 930: @28601
11065 /* 28601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(28645), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1064 //
11066 /* 28608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
11067 /* 28613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11068 /* 28616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11069 /* 28619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11070 /* 28622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11071 /* 28626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11072 /* 28630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11073 /* 28634 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8596:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11074 /* 28634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
11075 /* 28637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11076 /* 28639 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11077 /* 28641 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11078 /* 28643 */ GIR_RootConstrainSelectedInstOperands,
11079 /* 28644 */ // GIR_Coverage, 1064,
11080 /* 28644 */ GIR_EraseRootFromParent_Done,
11081 /* 28645 */ // Label 931: @28645
11082 /* 28645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(28689), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1065 //
11083 /* 28652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
11084 /* 28657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11085 /* 28660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11086 /* 28663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11087 /* 28666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11088 /* 28670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11089 /* 28674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11090 /* 28678 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8598:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11091 /* 28678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
11092 /* 28681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11093 /* 28683 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11094 /* 28685 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11095 /* 28687 */ GIR_RootConstrainSelectedInstOperands,
11096 /* 28688 */ // GIR_Coverage, 1065,
11097 /* 28688 */ GIR_EraseRootFromParent_Done,
11098 /* 28689 */ // Label 932: @28689
11099 /* 28689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 933*/ GIMT_Encode4(28733), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1066 //
11100 /* 28696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
11101 /* 28701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11102 /* 28704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11103 /* 28707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11104 /* 28710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11105 /* 28714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11106 /* 28718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11107 /* 28722 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8599:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11108 /* 28722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
11109 /* 28725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11110 /* 28727 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11111 /* 28729 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11112 /* 28731 */ GIR_RootConstrainSelectedInstOperands,
11113 /* 28732 */ // GIR_Coverage, 1066,
11114 /* 28732 */ GIR_EraseRootFromParent_Done,
11115 /* 28733 */ // Label 933: @28733
11116 /* 28733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 934*/ GIMT_Encode4(28777), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1067 //
11117 /* 28740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
11118 /* 28745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11119 /* 28748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11120 /* 28751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11121 /* 28754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11122 /* 28758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11123 /* 28762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11124 /* 28766 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8597:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11125 /* 28766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
11126 /* 28769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11127 /* 28771 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11128 /* 28773 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11129 /* 28775 */ GIR_RootConstrainSelectedInstOperands,
11130 /* 28776 */ // GIR_Coverage, 1067,
11131 /* 28776 */ GIR_EraseRootFromParent_Done,
11132 /* 28777 */ // Label 934: @28777
11133 /* 28777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(28821), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1080 //
11134 /* 28784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
11135 /* 28789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11136 /* 28792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11137 /* 28795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11138 /* 28798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11139 /* 28802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11140 /* 28806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11141 /* 28810 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8617:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11142 /* 28810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
11143 /* 28813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11144 /* 28815 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11145 /* 28817 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11146 /* 28819 */ GIR_RootConstrainSelectedInstOperands,
11147 /* 28820 */ // GIR_Coverage, 1080,
11148 /* 28820 */ GIR_EraseRootFromParent_Done,
11149 /* 28821 */ // Label 935: @28821
11150 /* 28821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 936*/ GIMT_Encode4(28865), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1081 //
11151 /* 28828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
11152 /* 28833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11153 /* 28836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11154 /* 28839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11155 /* 28842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11156 /* 28846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11157 /* 28850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11158 /* 28854 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8619:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11159 /* 28854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
11160 /* 28857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11161 /* 28859 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11162 /* 28861 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11163 /* 28863 */ GIR_RootConstrainSelectedInstOperands,
11164 /* 28864 */ // GIR_Coverage, 1081,
11165 /* 28864 */ GIR_EraseRootFromParent_Done,
11166 /* 28865 */ // Label 936: @28865
11167 /* 28865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 937*/ GIMT_Encode4(28909), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1082 //
11168 /* 28872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
11169 /* 28877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11170 /* 28880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11171 /* 28883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11172 /* 28886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11173 /* 28890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11174 /* 28894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11175 /* 28898 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8620:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11176 /* 28898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
11177 /* 28901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11178 /* 28903 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11179 /* 28905 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11180 /* 28907 */ GIR_RootConstrainSelectedInstOperands,
11181 /* 28908 */ // GIR_Coverage, 1082,
11182 /* 28908 */ GIR_EraseRootFromParent_Done,
11183 /* 28909 */ // Label 937: @28909
11184 /* 28909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 938*/ GIMT_Encode4(28953), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1083 //
11185 /* 28916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
11186 /* 28921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11187 /* 28924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11188 /* 28927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11189 /* 28930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11190 /* 28934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11191 /* 28938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11192 /* 28942 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8618:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11193 /* 28942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
11194 /* 28945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11195 /* 28947 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11196 /* 28949 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11197 /* 28951 */ GIR_RootConstrainSelectedInstOperands,
11198 /* 28952 */ // GIR_Coverage, 1083,
11199 /* 28952 */ GIR_EraseRootFromParent_Done,
11200 /* 28953 */ // Label 938: @28953
11201 /* 28953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 939*/ GIMT_Encode4(28997), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1084 //
11202 /* 28960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
11203 /* 28965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11204 /* 28968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11205 /* 28971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11206 /* 28974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11207 /* 28978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11208 /* 28982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11209 /* 28986 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8621:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11210 /* 28986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
11211 /* 28989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11212 /* 28991 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11213 /* 28993 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11214 /* 28995 */ GIR_RootConstrainSelectedInstOperands,
11215 /* 28996 */ // GIR_Coverage, 1084,
11216 /* 28996 */ GIR_EraseRootFromParent_Done,
11217 /* 28997 */ // Label 939: @28997
11218 /* 28997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 940*/ GIMT_Encode4(29041), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1085 //
11219 /* 29004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11220 /* 29009 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11221 /* 29012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11222 /* 29015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11223 /* 29018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11224 /* 29022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11225 /* 29026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11226 /* 29030 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8623:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11227 /* 29030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
11228 /* 29033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11229 /* 29035 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11230 /* 29037 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11231 /* 29039 */ GIR_RootConstrainSelectedInstOperands,
11232 /* 29040 */ // GIR_Coverage, 1085,
11233 /* 29040 */ GIR_EraseRootFromParent_Done,
11234 /* 29041 */ // Label 940: @29041
11235 /* 29041 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 941*/ GIMT_Encode4(29085), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1086 //
11236 /* 29048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11237 /* 29053 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11238 /* 29056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11239 /* 29059 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11240 /* 29062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11241 /* 29066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11242 /* 29070 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11243 /* 29074 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8624:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11244 /* 29074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
11245 /* 29077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11246 /* 29079 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11247 /* 29081 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11248 /* 29083 */ GIR_RootConstrainSelectedInstOperands,
11249 /* 29084 */ // GIR_Coverage, 1086,
11250 /* 29084 */ GIR_EraseRootFromParent_Done,
11251 /* 29085 */ // Label 941: @29085
11252 /* 29085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 942*/ GIMT_Encode4(29129), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1087 //
11253 /* 29092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11254 /* 29097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11255 /* 29100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11256 /* 29103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11257 /* 29106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11258 /* 29110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11259 /* 29114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11260 /* 29118 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8622:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11261 /* 29118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
11262 /* 29121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11263 /* 29123 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11264 /* 29125 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11265 /* 29127 */ GIR_RootConstrainSelectedInstOperands,
11266 /* 29128 */ // GIR_Coverage, 1087,
11267 /* 29128 */ GIR_EraseRootFromParent_Done,
11268 /* 29129 */ // Label 942: @29129
11269 /* 29129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(29173), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1088 //
11270 /* 29136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11271 /* 29141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11272 /* 29144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11273 /* 29147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11274 /* 29150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11275 /* 29154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11276 /* 29158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11277 /* 29162 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8625:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11278 /* 29162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
11279 /* 29165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11280 /* 29167 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11281 /* 29169 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11282 /* 29171 */ GIR_RootConstrainSelectedInstOperands,
11283 /* 29172 */ // GIR_Coverage, 1088,
11284 /* 29172 */ GIR_EraseRootFromParent_Done,
11285 /* 29173 */ // Label 943: @29173
11286 /* 29173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(29217), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1089 //
11287 /* 29180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11288 /* 29185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11289 /* 29188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11290 /* 29191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11291 /* 29194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11292 /* 29198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11293 /* 29202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11294 /* 29206 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8627:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11295 /* 29206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
11296 /* 29209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11297 /* 29211 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11298 /* 29213 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11299 /* 29215 */ GIR_RootConstrainSelectedInstOperands,
11300 /* 29216 */ // GIR_Coverage, 1089,
11301 /* 29216 */ GIR_EraseRootFromParent_Done,
11302 /* 29217 */ // Label 944: @29217
11303 /* 29217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(29261), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1090 //
11304 /* 29224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11305 /* 29229 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11306 /* 29232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11307 /* 29235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11308 /* 29238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11309 /* 29242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11310 /* 29246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11311 /* 29250 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8628:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11312 /* 29250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
11313 /* 29253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11314 /* 29255 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11315 /* 29257 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11316 /* 29259 */ GIR_RootConstrainSelectedInstOperands,
11317 /* 29260 */ // GIR_Coverage, 1090,
11318 /* 29260 */ GIR_EraseRootFromParent_Done,
11319 /* 29261 */ // Label 945: @29261
11320 /* 29261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 946*/ GIMT_Encode4(29305), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1091 //
11321 /* 29268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11322 /* 29273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11323 /* 29276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11324 /* 29279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11325 /* 29282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11326 /* 29286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11327 /* 29290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11328 /* 29294 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8626:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11329 /* 29294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
11330 /* 29297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11331 /* 29299 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11332 /* 29301 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11333 /* 29303 */ GIR_RootConstrainSelectedInstOperands,
11334 /* 29304 */ // GIR_Coverage, 1091,
11335 /* 29304 */ GIR_EraseRootFromParent_Done,
11336 /* 29305 */ // Label 946: @29305
11337 /* 29305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 947*/ GIMT_Encode4(29349), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1092 //
11338 /* 29312 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11339 /* 29317 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11340 /* 29320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11341 /* 29323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11342 /* 29326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11343 /* 29330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11344 /* 29334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11345 /* 29338 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8629:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11346 /* 29338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
11347 /* 29341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11348 /* 29343 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11349 /* 29345 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11350 /* 29347 */ GIR_RootConstrainSelectedInstOperands,
11351 /* 29348 */ // GIR_Coverage, 1092,
11352 /* 29348 */ GIR_EraseRootFromParent_Done,
11353 /* 29349 */ // Label 947: @29349
11354 /* 29349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(29393), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1093 //
11355 /* 29356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11356 /* 29361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11357 /* 29364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11358 /* 29367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11359 /* 29370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11360 /* 29374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11361 /* 29378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11362 /* 29382 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8631:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11363 /* 29382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
11364 /* 29385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11365 /* 29387 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11366 /* 29389 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11367 /* 29391 */ GIR_RootConstrainSelectedInstOperands,
11368 /* 29392 */ // GIR_Coverage, 1093,
11369 /* 29392 */ GIR_EraseRootFromParent_Done,
11370 /* 29393 */ // Label 948: @29393
11371 /* 29393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(29437), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1094 //
11372 /* 29400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11373 /* 29405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11374 /* 29408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11375 /* 29411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11376 /* 29414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11377 /* 29418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11378 /* 29422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11379 /* 29426 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8632:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11380 /* 29426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
11381 /* 29429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11382 /* 29431 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11383 /* 29433 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11384 /* 29435 */ GIR_RootConstrainSelectedInstOperands,
11385 /* 29436 */ // GIR_Coverage, 1094,
11386 /* 29436 */ GIR_EraseRootFromParent_Done,
11387 /* 29437 */ // Label 949: @29437
11388 /* 29437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(29481), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1095 //
11389 /* 29444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
11390 /* 29449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11391 /* 29452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11392 /* 29455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11393 /* 29458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11394 /* 29462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11395 /* 29466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11396 /* 29470 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8630:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11397 /* 29470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
11398 /* 29473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11399 /* 29475 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11400 /* 29477 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11401 /* 29479 */ GIR_RootConstrainSelectedInstOperands,
11402 /* 29480 */ // GIR_Coverage, 1095,
11403 /* 29480 */ GIR_EraseRootFromParent_Done,
11404 /* 29481 */ // Label 950: @29481
11405 /* 29481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 951*/ GIMT_Encode4(29528), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1301 //
11406 /* 29488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
11407 /* 29493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11408 /* 29496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11409 /* 29499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11410 /* 29502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11411 /* 29506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11412 /* 29510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11413 /* 29514 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11414 /* 29514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
11415 /* 29517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11416 /* 29519 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11417 /* 29521 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11418 /* 29523 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11419 /* 29526 */ GIR_RootConstrainSelectedInstOperands,
11420 /* 29527 */ // GIR_Coverage, 1301,
11421 /* 29527 */ GIR_EraseRootFromParent_Done,
11422 /* 29528 */ // Label 951: @29528
11423 /* 29528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 952*/ GIMT_Encode4(29575), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1303 //
11424 /* 29535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
11425 /* 29540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11426 /* 29543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11427 /* 29546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11428 /* 29549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11429 /* 29553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11430 /* 29557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11431 /* 29561 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8013:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11432 /* 29561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
11433 /* 29564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11434 /* 29566 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11435 /* 29568 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11436 /* 29570 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11437 /* 29573 */ GIR_RootConstrainSelectedInstOperands,
11438 /* 29574 */ // GIR_Coverage, 1303,
11439 /* 29574 */ GIR_EraseRootFromParent_Done,
11440 /* 29575 */ // Label 952: @29575
11441 /* 29575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(29619), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1324 //
11442 /* 29582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
11443 /* 29587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11444 /* 29590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11445 /* 29593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11446 /* 29596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11447 /* 29600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11448 /* 29604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11449 /* 29608 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8541:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11450 /* 29608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
11451 /* 29611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11452 /* 29613 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11453 /* 29615 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11454 /* 29617 */ GIR_RootConstrainSelectedInstOperands,
11455 /* 29618 */ // GIR_Coverage, 1324,
11456 /* 29618 */ GIR_EraseRootFromParent_Done,
11457 /* 29619 */ // Label 953: @29619
11458 /* 29619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(29663), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1325 //
11459 /* 29626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
11460 /* 29631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11461 /* 29634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11462 /* 29637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11463 /* 29640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11464 /* 29644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11465 /* 29648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11466 /* 29652 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8543:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11467 /* 29652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
11468 /* 29655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11469 /* 29657 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11470 /* 29659 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11471 /* 29661 */ GIR_RootConstrainSelectedInstOperands,
11472 /* 29662 */ // GIR_Coverage, 1325,
11473 /* 29662 */ GIR_EraseRootFromParent_Done,
11474 /* 29663 */ // Label 954: @29663
11475 /* 29663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(29707), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1326 //
11476 /* 29670 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
11477 /* 29675 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11478 /* 29678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11479 /* 29681 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11480 /* 29684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11481 /* 29688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11482 /* 29692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11483 /* 29696 */ // (intrinsic_wo_chain:{ *:[i32] } 8545:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11484 /* 29696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
11485 /* 29699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11486 /* 29701 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11487 /* 29703 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11488 /* 29705 */ GIR_RootConstrainSelectedInstOperands,
11489 /* 29706 */ // GIR_Coverage, 1326,
11490 /* 29706 */ GIR_EraseRootFromParent_Done,
11491 /* 29707 */ // Label 955: @29707
11492 /* 29707 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(29751), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1328 //
11493 /* 29714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
11494 /* 29719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11495 /* 29722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11496 /* 29725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11497 /* 29728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11498 /* 29732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11499 /* 29736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11500 /* 29740 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8547:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11501 /* 29740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
11502 /* 29743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11503 /* 29745 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11504 /* 29747 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11505 /* 29749 */ GIR_RootConstrainSelectedInstOperands,
11506 /* 29750 */ // GIR_Coverage, 1328,
11507 /* 29750 */ GIR_EraseRootFromParent_Done,
11508 /* 29751 */ // Label 956: @29751
11509 /* 29751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(29798), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1339 //
11510 /* 29758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
11511 /* 29763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11512 /* 29766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11513 /* 29769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11514 /* 29772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11515 /* 29776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11516 /* 29780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11517 /* 29784 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11518 /* 29784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
11519 /* 29787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11520 /* 29789 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11521 /* 29791 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11522 /* 29793 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11523 /* 29796 */ GIR_RootConstrainSelectedInstOperands,
11524 /* 29797 */ // GIR_Coverage, 1339,
11525 /* 29797 */ GIR_EraseRootFromParent_Done,
11526 /* 29798 */ // Label 957: @29798
11527 /* 29798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(29845), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1341 //
11528 /* 29805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
11529 /* 29810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11530 /* 29813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11531 /* 29816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11532 /* 29819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11533 /* 29823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11534 /* 29827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11535 /* 29831 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8636:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11536 /* 29831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
11537 /* 29834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11538 /* 29836 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11539 /* 29838 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11540 /* 29840 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11541 /* 29843 */ GIR_RootConstrainSelectedInstOperands,
11542 /* 29844 */ // GIR_Coverage, 1341,
11543 /* 29844 */ GIR_EraseRootFromParent_Done,
11544 /* 29845 */ // Label 958: @29845
11545 /* 29845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 959*/ GIMT_Encode4(29889), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1351 //
11546 /* 29852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
11547 /* 29857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11548 /* 29860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11549 /* 29863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11550 /* 29866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11551 /* 29870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11552 /* 29874 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11553 /* 29878 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8516:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11554 /* 29878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
11555 /* 29881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11556 /* 29883 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11557 /* 29885 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11558 /* 29887 */ GIR_RootConstrainSelectedInstOperands,
11559 /* 29888 */ // GIR_Coverage, 1351,
11560 /* 29888 */ GIR_EraseRootFromParent_Done,
11561 /* 29889 */ // Label 959: @29889
11562 /* 29889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 960*/ GIMT_Encode4(29933), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1352 //
11563 /* 29896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
11564 /* 29901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11565 /* 29904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11566 /* 29907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11567 /* 29910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11568 /* 29914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11569 /* 29918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11570 /* 29922 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11571 /* 29922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
11572 /* 29925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11573 /* 29927 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11574 /* 29929 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11575 /* 29931 */ GIR_RootConstrainSelectedInstOperands,
11576 /* 29932 */ // GIR_Coverage, 1352,
11577 /* 29932 */ GIR_EraseRootFromParent_Done,
11578 /* 29933 */ // Label 960: @29933
11579 /* 29933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 961*/ GIMT_Encode4(29977), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1371 //
11580 /* 29940 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
11581 /* 29945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11582 /* 29948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11583 /* 29951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11584 /* 29954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11585 /* 29958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11586 /* 29962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11587 /* 29966 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11588 /* 29966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
11589 /* 29969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11590 /* 29971 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11591 /* 29973 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11592 /* 29975 */ GIR_RootConstrainSelectedInstOperands,
11593 /* 29976 */ // GIR_Coverage, 1371,
11594 /* 29976 */ GIR_EraseRootFromParent_Done,
11595 /* 29977 */ // Label 961: @29977
11596 /* 29977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(30021), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1377 //
11597 /* 29984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
11598 /* 29989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11599 /* 29992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11600 /* 29995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11601 /* 29998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11602 /* 30002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11603 /* 30006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11604 /* 30010 */ // (intrinsic_wo_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11605 /* 30010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
11606 /* 30013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11607 /* 30015 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11608 /* 30017 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11609 /* 30019 */ GIR_RootConstrainSelectedInstOperands,
11610 /* 30020 */ // GIR_Coverage, 1377,
11611 /* 30020 */ GIR_EraseRootFromParent_Done,
11612 /* 30021 */ // Label 962: @30021
11613 /* 30021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(30065), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1390 //
11614 /* 30028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
11615 /* 30033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11616 /* 30036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11617 /* 30039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11618 /* 30042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11619 /* 30046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11620 /* 30050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11621 /* 30054 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11622 /* 30054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
11623 /* 30057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11624 /* 30059 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11625 /* 30061 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11626 /* 30063 */ GIR_RootConstrainSelectedInstOperands,
11627 /* 30064 */ // GIR_Coverage, 1390,
11628 /* 30064 */ GIR_EraseRootFromParent_Done,
11629 /* 30065 */ // Label 963: @30065
11630 /* 30065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(30109), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1391 //
11631 /* 30072 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
11632 /* 30077 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11633 /* 30080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11634 /* 30083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11635 /* 30086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11636 /* 30090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11637 /* 30094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11638 /* 30098 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7994:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11639 /* 30098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
11640 /* 30101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11641 /* 30103 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11642 /* 30105 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11643 /* 30107 */ GIR_RootConstrainSelectedInstOperands,
11644 /* 30108 */ // GIR_Coverage, 1391,
11645 /* 30108 */ GIR_EraseRootFromParent_Done,
11646 /* 30109 */ // Label 964: @30109
11647 /* 30109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(30153), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1392 //
11648 /* 30116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
11649 /* 30121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11650 /* 30124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11651 /* 30127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11652 /* 30130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11653 /* 30134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11654 /* 30138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11655 /* 30142 */ // (intrinsic_wo_chain:{ *:[i32] } 7996:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11656 /* 30142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
11657 /* 30145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11658 /* 30147 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11659 /* 30149 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11660 /* 30151 */ GIR_RootConstrainSelectedInstOperands,
11661 /* 30152 */ // GIR_Coverage, 1392,
11662 /* 30152 */ GIR_EraseRootFromParent_Done,
11663 /* 30153 */ // Label 965: @30153
11664 /* 30153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(30197), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1393 //
11665 /* 30160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
11666 /* 30165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11667 /* 30168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11668 /* 30171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11669 /* 30174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11670 /* 30178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11671 /* 30182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11672 /* 30186 */ // (intrinsic_wo_chain:{ *:[i32] } 7995:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11673 /* 30186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
11674 /* 30189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11675 /* 30191 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11676 /* 30193 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11677 /* 30195 */ GIR_RootConstrainSelectedInstOperands,
11678 /* 30196 */ // GIR_Coverage, 1393,
11679 /* 30196 */ GIR_EraseRootFromParent_Done,
11680 /* 30197 */ // Label 966: @30197
11681 /* 30197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(30241), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1396 //
11682 /* 30204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
11683 /* 30209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11684 /* 30212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11685 /* 30215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11686 /* 30218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11687 /* 30222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11688 /* 30226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11689 /* 30230 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8014:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11690 /* 30230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
11691 /* 30233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11692 /* 30235 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11693 /* 30237 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11694 /* 30239 */ GIR_RootConstrainSelectedInstOperands,
11695 /* 30240 */ // GIR_Coverage, 1396,
11696 /* 30240 */ GIR_EraseRootFromParent_Done,
11697 /* 30241 */ // Label 967: @30241
11698 /* 30241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(30285), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1397 //
11699 /* 30248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
11700 /* 30253 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11701 /* 30256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11702 /* 30259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11703 /* 30262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11704 /* 30266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11705 /* 30270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11706 /* 30274 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8015:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11707 /* 30274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
11708 /* 30277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11709 /* 30279 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11710 /* 30281 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11711 /* 30283 */ GIR_RootConstrainSelectedInstOperands,
11712 /* 30284 */ // GIR_Coverage, 1397,
11713 /* 30284 */ GIR_EraseRootFromParent_Done,
11714 /* 30285 */ // Label 968: @30285
11715 /* 30285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 969*/ GIMT_Encode4(30329), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1403 //
11716 /* 30292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
11717 /* 30297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11718 /* 30300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11719 /* 30303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11720 /* 30306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11721 /* 30310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11722 /* 30314 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11723 /* 30318 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8542:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11724 /* 30318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
11725 /* 30321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11726 /* 30323 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11727 /* 30325 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11728 /* 30327 */ GIR_RootConstrainSelectedInstOperands,
11729 /* 30328 */ // GIR_Coverage, 1403,
11730 /* 30328 */ GIR_EraseRootFromParent_Done,
11731 /* 30329 */ // Label 969: @30329
11732 /* 30329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 970*/ GIMT_Encode4(30373), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1404 //
11733 /* 30336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
11734 /* 30341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11735 /* 30344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11736 /* 30347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11737 /* 30350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11738 /* 30354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11739 /* 30358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11740 /* 30362 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8544:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11741 /* 30362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
11742 /* 30365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11743 /* 30367 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11744 /* 30369 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11745 /* 30371 */ GIR_RootConstrainSelectedInstOperands,
11746 /* 30372 */ // GIR_Coverage, 1404,
11747 /* 30372 */ GIR_EraseRootFromParent_Done,
11748 /* 30373 */ // Label 970: @30373
11749 /* 30373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(30417), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1409 //
11750 /* 30380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
11751 /* 30385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11752 /* 30388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11753 /* 30391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11754 /* 30394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11755 /* 30398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11756 /* 30402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11757 /* 30406 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8546:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11758 /* 30406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
11759 /* 30409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11760 /* 30411 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11761 /* 30413 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11762 /* 30415 */ GIR_RootConstrainSelectedInstOperands,
11763 /* 30416 */ // GIR_Coverage, 1409,
11764 /* 30416 */ GIR_EraseRootFromParent_Done,
11765 /* 30417 */ // Label 971: @30417
11766 /* 30417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 972*/ GIMT_Encode4(30461), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1410 //
11767 /* 30424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
11768 /* 30429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11769 /* 30432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11770 /* 30435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11771 /* 30438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11772 /* 30442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11773 /* 30446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11774 /* 30450 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11775 /* 30450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
11776 /* 30453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11777 /* 30455 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11778 /* 30457 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11779 /* 30459 */ GIR_RootConstrainSelectedInstOperands,
11780 /* 30460 */ // GIR_Coverage, 1410,
11781 /* 30460 */ GIR_EraseRootFromParent_Done,
11782 /* 30461 */ // Label 972: @30461
11783 /* 30461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 973*/ GIMT_Encode4(30505), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1411 //
11784 /* 30468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
11785 /* 30473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11786 /* 30476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11787 /* 30479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11788 /* 30482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11789 /* 30486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11790 /* 30490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11791 /* 30494 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11792 /* 30494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
11793 /* 30497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11794 /* 30499 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11795 /* 30501 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11796 /* 30503 */ GIR_RootConstrainSelectedInstOperands,
11797 /* 30504 */ // GIR_Coverage, 1411,
11798 /* 30504 */ GIR_EraseRootFromParent_Done,
11799 /* 30505 */ // Label 973: @30505
11800 /* 30505 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(30549), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1412 //
11801 /* 30512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
11802 /* 30517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11803 /* 30520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11804 /* 30523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11805 /* 30526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11806 /* 30530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11807 /* 30534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11808 /* 30538 */ // (intrinsic_wo_chain:{ *:[i32] } 8616:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11809 /* 30538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
11810 /* 30541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11811 /* 30543 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11812 /* 30545 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11813 /* 30547 */ GIR_RootConstrainSelectedInstOperands,
11814 /* 30548 */ // GIR_Coverage, 1412,
11815 /* 30548 */ GIR_EraseRootFromParent_Done,
11816 /* 30549 */ // Label 974: @30549
11817 /* 30549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 975*/ GIMT_Encode4(30593), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1413 //
11818 /* 30556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
11819 /* 30561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11820 /* 30564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11821 /* 30567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11822 /* 30570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11823 /* 30574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11824 /* 30578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11825 /* 30582 */ // (intrinsic_wo_chain:{ *:[i32] } 8615:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11826 /* 30582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
11827 /* 30585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11828 /* 30587 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11829 /* 30589 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11830 /* 30591 */ GIR_RootConstrainSelectedInstOperands,
11831 /* 30592 */ // GIR_Coverage, 1413,
11832 /* 30592 */ GIR_EraseRootFromParent_Done,
11833 /* 30593 */ // Label 975: @30593
11834 /* 30593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 976*/ GIMT_Encode4(30637), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1416 //
11835 /* 30600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
11836 /* 30605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11837 /* 30608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11838 /* 30611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11839 /* 30614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11840 /* 30618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11841 /* 30622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11842 /* 30626 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8637:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11843 /* 30626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
11844 /* 30629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11845 /* 30631 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11846 /* 30633 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11847 /* 30635 */ GIR_RootConstrainSelectedInstOperands,
11848 /* 30636 */ // GIR_Coverage, 1416,
11849 /* 30636 */ GIR_EraseRootFromParent_Done,
11850 /* 30637 */ // Label 976: @30637
11851 /* 30637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(30681), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1417 //
11852 /* 30644 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
11853 /* 30649 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11854 /* 30652 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11855 /* 30655 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11856 /* 30658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11857 /* 30662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11858 /* 30666 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11859 /* 30670 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8638:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11860 /* 30670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
11861 /* 30673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11862 /* 30675 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11863 /* 30677 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11864 /* 30679 */ GIR_RootConstrainSelectedInstOperands,
11865 /* 30680 */ // GIR_Coverage, 1417,
11866 /* 30680 */ GIR_EraseRootFromParent_Done,
11867 /* 30681 */ // Label 977: @30681
11868 /* 30681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(30720), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2176 //
11869 /* 30688 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
11870 /* 30693 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11871 /* 30696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11872 /* 30699 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11873 /* 30702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11874 /* 30706 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7990:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11875 /* 30706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
11876 /* 30709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11877 /* 30711 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11878 /* 30713 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11879 /* 30715 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11880 /* 30718 */ GIR_RootConstrainSelectedInstOperands,
11881 /* 30719 */ // GIR_Coverage, 2176,
11882 /* 30719 */ GIR_EraseRootFromParent_Done,
11883 /* 30720 */ // Label 978: @30720
11884 /* 30720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(30759), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2178 //
11885 /* 30727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
11886 /* 30732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11887 /* 30735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11888 /* 30738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11889 /* 30741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11890 /* 30745 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8610:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11891 /* 30745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
11892 /* 30748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11893 /* 30750 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11894 /* 30752 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11895 /* 30754 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11896 /* 30757 */ GIR_RootConstrainSelectedInstOperands,
11897 /* 30758 */ // GIR_Coverage, 2178,
11898 /* 30758 */ GIR_EraseRootFromParent_Done,
11899 /* 30759 */ // Label 979: @30759
11900 /* 30759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(30798), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2182 //
11901 /* 30766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
11902 /* 30771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11903 /* 30774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11904 /* 30777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11905 /* 30780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11906 /* 30784 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8011:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11907 /* 30784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
11908 /* 30787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11909 /* 30789 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11910 /* 30791 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11911 /* 30793 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11912 /* 30796 */ GIR_RootConstrainSelectedInstOperands,
11913 /* 30797 */ // GIR_Coverage, 2182,
11914 /* 30797 */ GIR_EraseRootFromParent_Done,
11915 /* 30798 */ // Label 980: @30798
11916 /* 30798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(30837), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2184 //
11917 /* 30805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
11918 /* 30810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11919 /* 30813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11920 /* 30816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11921 /* 30819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11922 /* 30823 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8634:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11923 /* 30823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
11924 /* 30826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11925 /* 30828 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11926 /* 30830 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11927 /* 30832 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11928 /* 30835 */ GIR_RootConstrainSelectedInstOperands,
11929 /* 30836 */ // GIR_Coverage, 2184,
11930 /* 30836 */ GIR_EraseRootFromParent_Done,
11931 /* 30837 */ // Label 981: @30837
11932 /* 30837 */ GIM_Reject,
11933 /* 30838 */ // Label 767: @30838
11934 /* 30838 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(33306),
11935 /* 30843 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
11936 /* 30846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(30900), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 540 //
11937 /* 30853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11938 /* 30858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11939 /* 30861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11940 /* 30864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11941 /* 30867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11942 /* 30871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11943 /* 30875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11944 /* 30879 */ // MIs[0] sa
11945 /* 30879 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11946 /* 30882 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11947 /* 30887 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8514:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11948 /* 30887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
11949 /* 30890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11950 /* 30892 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11951 /* 30894 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11952 /* 30896 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11953 /* 30898 */ GIR_RootConstrainSelectedInstOperands,
11954 /* 30899 */ // GIR_Coverage, 540,
11955 /* 30899 */ GIR_EraseRootFromParent_Done,
11956 /* 30900 */ // Label 983: @30900
11957 /* 30900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 984*/ GIMT_Encode4(30954), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 541 //
11958 /* 30907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11959 /* 30912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11960 /* 30915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11961 /* 30918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11962 /* 30921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11963 /* 30925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11964 /* 30929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11965 /* 30933 */ // MIs[0] sa
11966 /* 30933 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11967 /* 30936 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11968 /* 30941 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11969 /* 30941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
11970 /* 30944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11971 /* 30946 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11972 /* 30948 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11973 /* 30950 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11974 /* 30952 */ GIR_RootConstrainSelectedInstOperands,
11975 /* 30953 */ // GIR_Coverage, 541,
11976 /* 30953 */ GIR_EraseRootFromParent_Done,
11977 /* 30954 */ // Label 984: @30954
11978 /* 30954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 985*/ GIMT_Encode4(31008), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 546 //
11979 /* 30961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
11980 /* 30966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11981 /* 30969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11982 /* 30972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11983 /* 30975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11984 /* 30979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11985 /* 30983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11986 /* 30987 */ // MIs[0] sa
11987 /* 30987 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11988 /* 30990 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11989 /* 30995 */ // (intrinsic_wo_chain:{ *:[i32] } 8027:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11990 /* 30995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
11991 /* 30998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11992 /* 31000 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11993 /* 31002 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11994 /* 31004 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11995 /* 31006 */ GIR_RootConstrainSelectedInstOperands,
11996 /* 31007 */ // GIR_Coverage, 546,
11997 /* 31007 */ GIR_EraseRootFromParent_Done,
11998 /* 31008 */ // Label 985: @31008
11999 /* 31008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(31062), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 547 //
12000 /* 31015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12001 /* 31020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12002 /* 31023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12003 /* 31026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12004 /* 31029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12005 /* 31033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12006 /* 31037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12007 /* 31041 */ // MIs[0] sa
12008 /* 31041 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12009 /* 31044 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12010 /* 31049 */ // (intrinsic_wo_chain:{ *:[i32] } 8052:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12011 /* 31049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
12012 /* 31052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12013 /* 31054 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12014 /* 31056 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12015 /* 31058 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12016 /* 31060 */ GIR_RootConstrainSelectedInstOperands,
12017 /* 31061 */ // GIR_Coverage, 547,
12018 /* 31061 */ GIR_EraseRootFromParent_Done,
12019 /* 31062 */ // Label 986: @31062
12020 /* 31062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(31116), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 548 //
12021 /* 31069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12022 /* 31074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12023 /* 31077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12024 /* 31080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12025 /* 31083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12026 /* 31087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12027 /* 31091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12028 /* 31095 */ // MIs[0] sa
12029 /* 31095 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12030 /* 31098 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12031 /* 31103 */ // (intrinsic_wo_chain:{ *:[i32] } 8520:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12032 /* 31103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
12033 /* 31106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12034 /* 31108 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12035 /* 31110 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12036 /* 31112 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12037 /* 31114 */ GIR_RootConstrainSelectedInstOperands,
12038 /* 31115 */ // GIR_Coverage, 548,
12039 /* 31115 */ GIR_EraseRootFromParent_Done,
12040 /* 31116 */ // Label 987: @31116
12041 /* 31116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(31170), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1020 //
12042 /* 31123 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
12043 /* 31128 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12044 /* 31131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12045 /* 31134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12046 /* 31137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12047 /* 31141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12048 /* 31145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12049 /* 31149 */ // MIs[0] n
12050 /* 31149 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12051 /* 31152 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
12052 /* 31157 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8552:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
12053 /* 31157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
12054 /* 31160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12055 /* 31162 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12056 /* 31164 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12057 /* 31166 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12058 /* 31168 */ GIR_RootConstrainSelectedInstOperands,
12059 /* 31169 */ // GIR_Coverage, 1020,
12060 /* 31169 */ GIR_EraseRootFromParent_Done,
12061 /* 31170 */ // Label 988: @31170
12062 /* 31170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(31224), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1021 //
12063 /* 31177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
12064 /* 31182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12065 /* 31185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12066 /* 31188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12067 /* 31191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12068 /* 31195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12069 /* 31199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12070 /* 31203 */ // MIs[0] n
12071 /* 31203 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12072 /* 31206 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
12073 /* 31211 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8554:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
12074 /* 31211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
12075 /* 31214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12076 /* 31216 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12077 /* 31218 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12078 /* 31220 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12079 /* 31222 */ GIR_RootConstrainSelectedInstOperands,
12080 /* 31223 */ // GIR_Coverage, 1021,
12081 /* 31223 */ GIR_EraseRootFromParent_Done,
12082 /* 31224 */ // Label 989: @31224
12083 /* 31224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(31278), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1022 //
12084 /* 31231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
12085 /* 31236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12086 /* 31239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12087 /* 31242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12088 /* 31245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12089 /* 31249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12090 /* 31253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12091 /* 31257 */ // MIs[0] n
12092 /* 31257 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12093 /* 31260 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12094 /* 31265 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8555:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
12095 /* 31265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
12096 /* 31268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12097 /* 31270 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12098 /* 31272 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12099 /* 31274 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12100 /* 31276 */ GIR_RootConstrainSelectedInstOperands,
12101 /* 31277 */ // GIR_Coverage, 1022,
12102 /* 31277 */ GIR_EraseRootFromParent_Done,
12103 /* 31278 */ // Label 990: @31278
12104 /* 31278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(31332), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1023 //
12105 /* 31285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
12106 /* 31290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12107 /* 31293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12108 /* 31296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12109 /* 31299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12110 /* 31303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12111 /* 31307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12112 /* 31311 */ // MIs[0] n
12113 /* 31311 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12114 /* 31314 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
12115 /* 31319 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8553:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
12116 /* 31319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
12117 /* 31322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12118 /* 31324 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12119 /* 31326 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12120 /* 31328 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12121 /* 31330 */ GIR_RootConstrainSelectedInstOperands,
12122 /* 31331 */ // GIR_Coverage, 1023,
12123 /* 31331 */ GIR_EraseRootFromParent_Done,
12124 /* 31332 */ // Label 991: @31332
12125 /* 31332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(31386), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1427 //
12126 /* 31339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12127 /* 31344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12128 /* 31347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12129 /* 31350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12130 /* 31353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12131 /* 31357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12132 /* 31361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12133 /* 31365 */ // MIs[0] sa
12134 /* 31365 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12135 /* 31368 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12136 /* 31373 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8514:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12137 /* 31373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
12138 /* 31376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12139 /* 31378 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12140 /* 31380 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12141 /* 31382 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12142 /* 31384 */ GIR_RootConstrainSelectedInstOperands,
12143 /* 31385 */ // GIR_Coverage, 1427,
12144 /* 31385 */ GIR_EraseRootFromParent_Done,
12145 /* 31386 */ // Label 992: @31386
12146 /* 31386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 993*/ GIMT_Encode4(31440), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1428 //
12147 /* 31393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12148 /* 31398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12149 /* 31401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12150 /* 31404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12151 /* 31407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12152 /* 31411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12153 /* 31415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12154 /* 31419 */ // MIs[0] sa
12155 /* 31419 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12156 /* 31422 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12157 /* 31427 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12158 /* 31427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
12159 /* 31430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12160 /* 31432 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12161 /* 31434 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12162 /* 31436 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12163 /* 31438 */ GIR_RootConstrainSelectedInstOperands,
12164 /* 31439 */ // GIR_Coverage, 1428,
12165 /* 31439 */ GIR_EraseRootFromParent_Done,
12166 /* 31440 */ // Label 993: @31440
12167 /* 31440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 994*/ GIMT_Encode4(31494), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1429 //
12168 /* 31447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12169 /* 31452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12170 /* 31455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12171 /* 31458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12172 /* 31461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12173 /* 31465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12174 /* 31469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12175 /* 31473 */ // MIs[0] sa
12176 /* 31473 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12177 /* 31476 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12178 /* 31481 */ // (intrinsic_wo_chain:{ *:[i32] } 8520:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12179 /* 31481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
12180 /* 31484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12181 /* 31486 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12182 /* 31488 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12183 /* 31490 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12184 /* 31492 */ GIR_RootConstrainSelectedInstOperands,
12185 /* 31493 */ // GIR_Coverage, 1429,
12186 /* 31493 */ GIR_EraseRootFromParent_Done,
12187 /* 31494 */ // Label 994: @31494
12188 /* 31494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 995*/ GIMT_Encode4(31548), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1430 //
12189 /* 31501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12190 /* 31506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12191 /* 31509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12192 /* 31512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12193 /* 31515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12194 /* 31519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12195 /* 31523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12196 /* 31527 */ // MIs[0] sa
12197 /* 31527 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12198 /* 31530 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12199 /* 31535 */ // (intrinsic_wo_chain:{ *:[i32] } 8027:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12200 /* 31535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
12201 /* 31538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12202 /* 31540 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12203 /* 31542 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12204 /* 31544 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12205 /* 31546 */ GIR_RootConstrainSelectedInstOperands,
12206 /* 31547 */ // GIR_Coverage, 1430,
12207 /* 31547 */ GIR_EraseRootFromParent_Done,
12208 /* 31548 */ // Label 995: @31548
12209 /* 31548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 996*/ GIMT_Encode4(31609), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1405 //
12210 /* 31555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12211 /* 31560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12212 /* 31563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12213 /* 31566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12214 /* 31569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12215 /* 31573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12216 /* 31577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12217 /* 31581 */ // MIs[0] bp
12218 /* 31581 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
12219 /* 31585 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12220 /* 31589 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12221 /* 31593 */ // MIs[1] Operand 1
12222 /* 31593 */ // No operand predicates
12223 /* 31593 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
12224 /* 31595 */ // (intrinsic_wo_chain:{ *:[i32] } 8052:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
12225 /* 31595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
12226 /* 31598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12227 /* 31600 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12228 /* 31602 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
12229 /* 31605 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12230 /* 31607 */ GIR_RootConstrainSelectedInstOperands,
12231 /* 31608 */ // GIR_Coverage, 1405,
12232 /* 31608 */ GIR_EraseRootFromParent_Done,
12233 /* 31609 */ // Label 996: @31609
12234 /* 31609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 997*/ GIMT_Encode4(31662), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 615 //
12235 /* 31616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
12236 /* 31621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12237 /* 31624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12238 /* 31627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12239 /* 31630 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12240 /* 31633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12241 /* 31637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12242 /* 31641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12243 /* 31645 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12244 /* 31649 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8061:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12245 /* 31649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
12246 /* 31652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12247 /* 31654 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12248 /* 31656 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12249 /* 31658 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12250 /* 31660 */ GIR_RootConstrainSelectedInstOperands,
12251 /* 31661 */ // GIR_Coverage, 615,
12252 /* 31661 */ GIR_EraseRootFromParent_Done,
12253 /* 31662 */ // Label 997: @31662
12254 /* 31662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 998*/ GIMT_Encode4(31715), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 616 //
12255 /* 31669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
12256 /* 31674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12257 /* 31677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12258 /* 31680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12259 /* 31683 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12260 /* 31686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12261 /* 31690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12262 /* 31694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12263 /* 31698 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12264 /* 31702 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8063:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12265 /* 31702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
12266 /* 31705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12267 /* 31707 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12268 /* 31709 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12269 /* 31711 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12270 /* 31713 */ GIR_RootConstrainSelectedInstOperands,
12271 /* 31714 */ // GIR_Coverage, 616,
12272 /* 31714 */ GIR_EraseRootFromParent_Done,
12273 /* 31715 */ // Label 998: @31715
12274 /* 31715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 999*/ GIMT_Encode4(31768), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 617 //
12275 /* 31722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
12276 /* 31727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12277 /* 31730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12278 /* 31733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12279 /* 31736 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12280 /* 31739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12281 /* 31743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12282 /* 31747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12283 /* 31751 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12284 /* 31755 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8064:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12285 /* 31755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
12286 /* 31758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12287 /* 31760 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12288 /* 31762 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12289 /* 31764 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12290 /* 31766 */ GIR_RootConstrainSelectedInstOperands,
12291 /* 31767 */ // GIR_Coverage, 617,
12292 /* 31767 */ GIR_EraseRootFromParent_Done,
12293 /* 31768 */ // Label 999: @31768
12294 /* 31768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(31821), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 618 //
12295 /* 31775 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
12296 /* 31780 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12297 /* 31783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12298 /* 31786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12299 /* 31789 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12300 /* 31792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12301 /* 31796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12302 /* 31800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12303 /* 31804 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12304 /* 31808 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8062:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12305 /* 31808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
12306 /* 31811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12307 /* 31813 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12308 /* 31815 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12309 /* 31817 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12310 /* 31819 */ GIR_RootConstrainSelectedInstOperands,
12311 /* 31820 */ // GIR_Coverage, 618,
12312 /* 31820 */ GIR_EraseRootFromParent_Done,
12313 /* 31821 */ // Label 1000: @31821
12314 /* 31821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(31874), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 623 //
12315 /* 31828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
12316 /* 31833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12317 /* 31836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12318 /* 31839 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12319 /* 31842 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12320 /* 31845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12321 /* 31849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12322 /* 31853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12323 /* 31857 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12324 /* 31861 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8069:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12325 /* 31861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
12326 /* 31864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12327 /* 31866 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12328 /* 31868 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12329 /* 31870 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12330 /* 31872 */ GIR_RootConstrainSelectedInstOperands,
12331 /* 31873 */ // GIR_Coverage, 623,
12332 /* 31873 */ GIR_EraseRootFromParent_Done,
12333 /* 31874 */ // Label 1001: @31874
12334 /* 31874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(31927), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 624 //
12335 /* 31881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
12336 /* 31886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12337 /* 31889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12338 /* 31892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12339 /* 31895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12340 /* 31898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12341 /* 31902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12342 /* 31906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12343 /* 31910 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12344 /* 31914 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8071:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12345 /* 31914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
12346 /* 31917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12347 /* 31919 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12348 /* 31921 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12349 /* 31923 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12350 /* 31925 */ GIR_RootConstrainSelectedInstOperands,
12351 /* 31926 */ // GIR_Coverage, 624,
12352 /* 31926 */ GIR_EraseRootFromParent_Done,
12353 /* 31927 */ // Label 1002: @31927
12354 /* 31927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1003*/ GIMT_Encode4(31980), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 625 //
12355 /* 31934 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
12356 /* 31939 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12357 /* 31942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12358 /* 31945 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12359 /* 31948 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12360 /* 31951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12361 /* 31955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12362 /* 31959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12363 /* 31963 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12364 /* 31967 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8072:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12365 /* 31967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
12366 /* 31970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12367 /* 31972 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12368 /* 31974 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12369 /* 31976 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12370 /* 31978 */ GIR_RootConstrainSelectedInstOperands,
12371 /* 31979 */ // GIR_Coverage, 625,
12372 /* 31979 */ GIR_EraseRootFromParent_Done,
12373 /* 31980 */ // Label 1003: @31980
12374 /* 31980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1004*/ GIMT_Encode4(32033), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 626 //
12375 /* 31987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
12376 /* 31992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12377 /* 31995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12378 /* 31998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12379 /* 32001 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12380 /* 32004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12381 /* 32008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12382 /* 32012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12383 /* 32016 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12384 /* 32020 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8070:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12385 /* 32020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
12386 /* 32023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12387 /* 32025 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12388 /* 32027 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12389 /* 32029 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12390 /* 32031 */ GIR_RootConstrainSelectedInstOperands,
12391 /* 32032 */ // GIR_Coverage, 626,
12392 /* 32032 */ GIR_EraseRootFromParent_Done,
12393 /* 32033 */ // Label 1004: @32033
12394 /* 32033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(32086), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 721 //
12395 /* 32040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
12396 /* 32045 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12397 /* 32048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12398 /* 32051 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12399 /* 32054 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12400 /* 32057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12401 /* 32061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12402 /* 32065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12403 /* 32069 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12404 /* 32073 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8190:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12405 /* 32073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
12406 /* 32076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12407 /* 32078 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12408 /* 32080 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12409 /* 32082 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12410 /* 32084 */ GIR_RootConstrainSelectedInstOperands,
12411 /* 32085 */ // GIR_Coverage, 721,
12412 /* 32085 */ GIR_EraseRootFromParent_Done,
12413 /* 32086 */ // Label 1005: @32086
12414 /* 32086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1006*/ GIMT_Encode4(32139), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 722 //
12415 /* 32093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
12416 /* 32098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12417 /* 32101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12418 /* 32104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12419 /* 32107 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12420 /* 32110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12421 /* 32114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12422 /* 32118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12423 /* 32122 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12424 /* 32126 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8191:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12425 /* 32126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
12426 /* 32129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12427 /* 32131 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12428 /* 32133 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12429 /* 32135 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12430 /* 32137 */ GIR_RootConstrainSelectedInstOperands,
12431 /* 32138 */ // GIR_Coverage, 722,
12432 /* 32138 */ GIR_EraseRootFromParent_Done,
12433 /* 32139 */ // Label 1006: @32139
12434 /* 32139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1007*/ GIMT_Encode4(32192), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 723 //
12435 /* 32146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
12436 /* 32151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12437 /* 32154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12438 /* 32157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12439 /* 32160 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12440 /* 32163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12441 /* 32167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12442 /* 32171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12443 /* 32175 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12444 /* 32179 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8189:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12445 /* 32179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
12446 /* 32182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12447 /* 32184 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12448 /* 32186 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12449 /* 32188 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12450 /* 32190 */ GIR_RootConstrainSelectedInstOperands,
12451 /* 32191 */ // GIR_Coverage, 723,
12452 /* 32191 */ GIR_EraseRootFromParent_Done,
12453 /* 32192 */ // Label 1007: @32192
12454 /* 32192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1008*/ GIMT_Encode4(32245), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 724 //
12455 /* 32199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
12456 /* 32204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12457 /* 32207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12458 /* 32210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12459 /* 32213 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12460 /* 32216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12461 /* 32220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12462 /* 32224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12463 /* 32228 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12464 /* 32232 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8193:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12465 /* 32232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
12466 /* 32235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12467 /* 32237 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12468 /* 32239 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12469 /* 32241 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12470 /* 32243 */ GIR_RootConstrainSelectedInstOperands,
12471 /* 32244 */ // GIR_Coverage, 724,
12472 /* 32244 */ GIR_EraseRootFromParent_Done,
12473 /* 32245 */ // Label 1008: @32245
12474 /* 32245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1009*/ GIMT_Encode4(32298), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 725 //
12475 /* 32252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
12476 /* 32257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12477 /* 32260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12478 /* 32263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12479 /* 32266 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12480 /* 32269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12481 /* 32273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12482 /* 32277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12483 /* 32281 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12484 /* 32285 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8194:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12485 /* 32285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
12486 /* 32288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12487 /* 32290 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12488 /* 32292 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12489 /* 32294 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12490 /* 32296 */ GIR_RootConstrainSelectedInstOperands,
12491 /* 32297 */ // GIR_Coverage, 725,
12492 /* 32297 */ GIR_EraseRootFromParent_Done,
12493 /* 32298 */ // Label 1009: @32298
12494 /* 32298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(32351), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 726 //
12495 /* 32305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
12496 /* 32310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12497 /* 32313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12498 /* 32316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12499 /* 32319 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12500 /* 32322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12501 /* 32326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12502 /* 32330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12503 /* 32334 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12504 /* 32338 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8192:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12505 /* 32338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
12506 /* 32341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12507 /* 32343 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12508 /* 32345 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12509 /* 32347 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12510 /* 32349 */ GIR_RootConstrainSelectedInstOperands,
12511 /* 32350 */ // GIR_Coverage, 726,
12512 /* 32350 */ GIR_EraseRootFromParent_Done,
12513 /* 32351 */ // Label 1010: @32351
12514 /* 32351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1011*/ GIMT_Encode4(32404), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 727 //
12515 /* 32358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
12516 /* 32363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12517 /* 32366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12518 /* 32369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12519 /* 32372 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12520 /* 32375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12521 /* 32379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12522 /* 32383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12523 /* 32387 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12524 /* 32391 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8210:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12525 /* 32391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
12526 /* 32394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12527 /* 32396 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12528 /* 32398 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12529 /* 32400 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12530 /* 32402 */ GIR_RootConstrainSelectedInstOperands,
12531 /* 32403 */ // GIR_Coverage, 727,
12532 /* 32403 */ GIR_EraseRootFromParent_Done,
12533 /* 32404 */ // Label 1011: @32404
12534 /* 32404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(32457), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 728 //
12535 /* 32411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
12536 /* 32416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12537 /* 32419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12538 /* 32422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12539 /* 32425 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12540 /* 32428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12541 /* 32432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12542 /* 32436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12543 /* 32440 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12544 /* 32444 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8211:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12545 /* 32444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
12546 /* 32447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12547 /* 32449 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12548 /* 32451 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12549 /* 32453 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12550 /* 32455 */ GIR_RootConstrainSelectedInstOperands,
12551 /* 32456 */ // GIR_Coverage, 728,
12552 /* 32456 */ GIR_EraseRootFromParent_Done,
12553 /* 32457 */ // Label 1012: @32457
12554 /* 32457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(32510), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 729 //
12555 /* 32464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
12556 /* 32469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12557 /* 32472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12558 /* 32475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12559 /* 32478 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12560 /* 32481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12561 /* 32485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12562 /* 32489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12563 /* 32493 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12564 /* 32497 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8209:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12565 /* 32497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
12566 /* 32500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12567 /* 32502 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12568 /* 32504 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12569 /* 32506 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12570 /* 32508 */ GIR_RootConstrainSelectedInstOperands,
12571 /* 32509 */ // GIR_Coverage, 729,
12572 /* 32509 */ GIR_EraseRootFromParent_Done,
12573 /* 32510 */ // Label 1013: @32510
12574 /* 32510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(32563), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 730 //
12575 /* 32517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
12576 /* 32522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12577 /* 32525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12578 /* 32528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12579 /* 32531 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12580 /* 32534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12581 /* 32538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12582 /* 32542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12583 /* 32546 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12584 /* 32550 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8213:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12585 /* 32550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
12586 /* 32553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12587 /* 32555 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12588 /* 32557 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12589 /* 32559 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12590 /* 32561 */ GIR_RootConstrainSelectedInstOperands,
12591 /* 32562 */ // GIR_Coverage, 730,
12592 /* 32562 */ GIR_EraseRootFromParent_Done,
12593 /* 32563 */ // Label 1014: @32563
12594 /* 32563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(32616), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 731 //
12595 /* 32570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
12596 /* 32575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12597 /* 32578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12598 /* 32581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12599 /* 32584 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12600 /* 32587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12601 /* 32591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12602 /* 32595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12603 /* 32599 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12604 /* 32603 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8214:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12605 /* 32603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
12606 /* 32606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12607 /* 32608 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12608 /* 32610 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12609 /* 32612 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12610 /* 32614 */ GIR_RootConstrainSelectedInstOperands,
12611 /* 32615 */ // GIR_Coverage, 731,
12612 /* 32615 */ GIR_EraseRootFromParent_Done,
12613 /* 32616 */ // Label 1015: @32616
12614 /* 32616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(32669), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 732 //
12615 /* 32623 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
12616 /* 32628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12617 /* 32631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12618 /* 32634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12619 /* 32637 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12620 /* 32640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12621 /* 32644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12622 /* 32648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12623 /* 32652 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12624 /* 32656 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8212:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12625 /* 32656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
12626 /* 32659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12627 /* 32661 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12628 /* 32663 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12629 /* 32665 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12630 /* 32667 */ GIR_RootConstrainSelectedInstOperands,
12631 /* 32668 */ // GIR_Coverage, 732,
12632 /* 32668 */ GIR_EraseRootFromParent_Done,
12633 /* 32669 */ // Label 1016: @32669
12634 /* 32669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1017*/ GIMT_Encode4(32722), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 903 //
12635 /* 32676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
12636 /* 32681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12637 /* 32684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12638 /* 32687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12639 /* 32690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12640 /* 32693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12641 /* 32697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12642 /* 32701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12643 /* 32705 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12644 /* 32709 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8380:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12645 /* 32709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
12646 /* 32712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12647 /* 32714 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12648 /* 32716 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12649 /* 32718 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12650 /* 32720 */ GIR_RootConstrainSelectedInstOperands,
12651 /* 32721 */ // GIR_Coverage, 903,
12652 /* 32721 */ GIR_EraseRootFromParent_Done,
12653 /* 32722 */ // Label 1017: @32722
12654 /* 32722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1018*/ GIMT_Encode4(32775), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 904 //
12655 /* 32729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
12656 /* 32734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12657 /* 32737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12658 /* 32740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12659 /* 32743 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12660 /* 32746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12661 /* 32750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12662 /* 32754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12663 /* 32758 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12664 /* 32762 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8381:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12665 /* 32762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
12666 /* 32765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12667 /* 32767 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12668 /* 32769 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12669 /* 32771 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12670 /* 32773 */ GIR_RootConstrainSelectedInstOperands,
12671 /* 32774 */ // GIR_Coverage, 904,
12672 /* 32774 */ GIR_EraseRootFromParent_Done,
12673 /* 32775 */ // Label 1018: @32775
12674 /* 32775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(32828), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 905 //
12675 /* 32782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
12676 /* 32787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12677 /* 32790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12678 /* 32793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12679 /* 32796 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12680 /* 32799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12681 /* 32803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12682 /* 32807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12683 /* 32811 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12684 /* 32815 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8382:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12685 /* 32815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
12686 /* 32818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12687 /* 32820 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12688 /* 32822 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12689 /* 32824 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12690 /* 32826 */ GIR_RootConstrainSelectedInstOperands,
12691 /* 32827 */ // GIR_Coverage, 905,
12692 /* 32827 */ GIR_EraseRootFromParent_Done,
12693 /* 32828 */ // Label 1019: @32828
12694 /* 32828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(32881), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 906 //
12695 /* 32835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
12696 /* 32840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12697 /* 32843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12698 /* 32846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12699 /* 32849 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12700 /* 32852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12701 /* 32856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12702 /* 32860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12703 /* 32864 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12704 /* 32868 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8383:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12705 /* 32868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
12706 /* 32871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12707 /* 32873 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12708 /* 32875 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12709 /* 32877 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12710 /* 32879 */ GIR_RootConstrainSelectedInstOperands,
12711 /* 32880 */ // GIR_Coverage, 906,
12712 /* 32880 */ GIR_EraseRootFromParent_Done,
12713 /* 32881 */ // Label 1020: @32881
12714 /* 32881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(32934), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 959 //
12715 /* 32888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
12716 /* 32893 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12717 /* 32896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12718 /* 32899 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12719 /* 32902 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12720 /* 32905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12721 /* 32909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12722 /* 32913 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12723 /* 32917 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12724 /* 32921 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8444:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12725 /* 32921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
12726 /* 32924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12727 /* 32926 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12728 /* 32928 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12729 /* 32930 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12730 /* 32932 */ GIR_RootConstrainSelectedInstOperands,
12731 /* 32933 */ // GIR_Coverage, 959,
12732 /* 32933 */ GIR_EraseRootFromParent_Done,
12733 /* 32934 */ // Label 1021: @32934
12734 /* 32934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(32987), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 960 //
12735 /* 32941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
12736 /* 32946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12737 /* 32949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12738 /* 32952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12739 /* 32955 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12740 /* 32958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12741 /* 32962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12742 /* 32966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12743 /* 32970 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12744 /* 32974 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8445:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12745 /* 32974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
12746 /* 32977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12747 /* 32979 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12748 /* 32981 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12749 /* 32983 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12750 /* 32985 */ GIR_RootConstrainSelectedInstOperands,
12751 /* 32986 */ // GIR_Coverage, 960,
12752 /* 32986 */ GIR_EraseRootFromParent_Done,
12753 /* 32987 */ // Label 1022: @32987
12754 /* 32987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(33040), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 961 //
12755 /* 32994 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
12756 /* 32999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12757 /* 33002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12758 /* 33005 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12759 /* 33008 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12760 /* 33011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12761 /* 33015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12762 /* 33019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12763 /* 33023 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12764 /* 33027 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8446:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12765 /* 33027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
12766 /* 33030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12767 /* 33032 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12768 /* 33034 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12769 /* 33036 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12770 /* 33038 */ GIR_RootConstrainSelectedInstOperands,
12771 /* 33039 */ // GIR_Coverage, 961,
12772 /* 33039 */ GIR_EraseRootFromParent_Done,
12773 /* 33040 */ // Label 1023: @33040
12774 /* 33040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(33093), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 962 //
12775 /* 33047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
12776 /* 33052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12777 /* 33055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12778 /* 33058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12779 /* 33061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12780 /* 33064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12781 /* 33068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12782 /* 33072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12783 /* 33076 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12784 /* 33080 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8447:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12785 /* 33080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
12786 /* 33083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12787 /* 33085 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12788 /* 33087 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12789 /* 33089 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12790 /* 33091 */ GIR_RootConstrainSelectedInstOperands,
12791 /* 33092 */ // GIR_Coverage, 962,
12792 /* 33092 */ GIR_EraseRootFromParent_Done,
12793 /* 33093 */ // Label 1024: @33093
12794 /* 33093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(33146), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1016 //
12795 /* 33100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
12796 /* 33105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12797 /* 33108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12798 /* 33111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12799 /* 33114 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12800 /* 33117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12801 /* 33121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12802 /* 33125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12803 /* 33129 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12804 /* 33133 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8548:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12805 /* 33133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
12806 /* 33136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12807 /* 33138 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12808 /* 33140 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12809 /* 33142 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12810 /* 33144 */ GIR_RootConstrainSelectedInstOperands,
12811 /* 33145 */ // GIR_Coverage, 1016,
12812 /* 33145 */ GIR_EraseRootFromParent_Done,
12813 /* 33146 */ // Label 1025: @33146
12814 /* 33146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1026*/ GIMT_Encode4(33199), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1017 //
12815 /* 33153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
12816 /* 33158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12817 /* 33161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12818 /* 33164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12819 /* 33167 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12820 /* 33170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12821 /* 33174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12822 /* 33178 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12823 /* 33182 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12824 /* 33186 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8550:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12825 /* 33186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
12826 /* 33189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12827 /* 33191 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12828 /* 33193 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12829 /* 33195 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12830 /* 33197 */ GIR_RootConstrainSelectedInstOperands,
12831 /* 33198 */ // GIR_Coverage, 1017,
12832 /* 33198 */ GIR_EraseRootFromParent_Done,
12833 /* 33199 */ // Label 1026: @33199
12834 /* 33199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1027*/ GIMT_Encode4(33252), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1018 //
12835 /* 33206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
12836 /* 33211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12837 /* 33214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12838 /* 33217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12839 /* 33220 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12840 /* 33223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12841 /* 33227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12842 /* 33231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12843 /* 33235 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12844 /* 33239 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8551:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12845 /* 33239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
12846 /* 33242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12847 /* 33244 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12848 /* 33246 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12849 /* 33248 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12850 /* 33250 */ GIR_RootConstrainSelectedInstOperands,
12851 /* 33251 */ // GIR_Coverage, 1018,
12852 /* 33251 */ GIR_EraseRootFromParent_Done,
12853 /* 33252 */ // Label 1027: @33252
12854 /* 33252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(33305), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1019 //
12855 /* 33259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
12856 /* 33264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12857 /* 33267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12858 /* 33270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12859 /* 33273 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12860 /* 33276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12861 /* 33280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12862 /* 33284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12863 /* 33288 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12864 /* 33292 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8549:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12865 /* 33292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
12866 /* 33295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12867 /* 33297 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12868 /* 33299 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12869 /* 33301 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12870 /* 33303 */ GIR_RootConstrainSelectedInstOperands,
12871 /* 33304 */ // GIR_Coverage, 1019,
12872 /* 33304 */ GIR_EraseRootFromParent_Done,
12873 /* 33305 */ // Label 1028: @33305
12874 /* 33305 */ GIM_Reject,
12875 /* 33306 */ // Label 982: @33306
12876 /* 33306 */ GIM_Reject,
12877 /* 33307 */ // Label 31: @33307
12878 /* 33307 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(33338), // Rule ID 417 //
12879 /* 33312 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
12880 /* 33315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
12881 /* 33320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12882 /* 33323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12883 /* 33327 */ // (intrinsic_w_chain:{ *:[i32] } 8095:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
12884 /* 33327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
12885 /* 33330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12886 /* 33332 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12887 /* 33336 */ GIR_RootConstrainSelectedInstOperands,
12888 /* 33337 */ // GIR_Coverage, 417,
12889 /* 33337 */ GIR_EraseRootFromParent_Done,
12890 /* 33338 */ // Label 1029: @33338
12891 /* 33338 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(34235),
12892 /* 33343 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
12893 /* 33346 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(33412),
12894 /* 33351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12895 /* 33356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12896 /* 33359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12897 /* 33363 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12898 /* 33366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1032*/ GIMT_Encode4(33391), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 504 //
12899 /* 33373 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12900 /* 33378 */ // (intrinsic_w_chain:{ *:[i32] } 8522:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12901 /* 33378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
12902 /* 33381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12903 /* 33383 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12904 /* 33385 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12905 /* 33389 */ GIR_RootConstrainSelectedInstOperands,
12906 /* 33390 */ // GIR_Coverage, 504,
12907 /* 33390 */ GIR_EraseRootFromParent_Done,
12908 /* 33391 */ // Label 1032: @33391
12909 /* 33391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(33411), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1365 //
12910 /* 33398 */ // (intrinsic_w_chain:{ *:[i32] } 8522:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12911 /* 33398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
12912 /* 33401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12913 /* 33403 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12914 /* 33405 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12915 /* 33409 */ GIR_RootConstrainSelectedInstOperands,
12916 /* 33410 */ // GIR_Coverage, 1365,
12917 /* 33410 */ GIR_EraseRootFromParent_Done,
12918 /* 33411 */ // Label 1033: @33411
12919 /* 33411 */ GIM_Reject,
12920 /* 33412 */ // Label 1031: @33412
12921 /* 33412 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(33478),
12922 /* 33417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12923 /* 33422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12924 /* 33425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12925 /* 33429 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12926 /* 33432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1035*/ GIMT_Encode4(33457), GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips), // Rule ID 505 //
12927 /* 33439 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12928 /* 33444 */ // (intrinsic_void 8651:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
12929 /* 33444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
12930 /* 33447 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12931 /* 33449 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12932 /* 33451 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12933 /* 33455 */ GIR_RootConstrainSelectedInstOperands,
12934 /* 33456 */ // GIR_Coverage, 505,
12935 /* 33456 */ GIR_EraseRootFromParent_Done,
12936 /* 33457 */ // Label 1035: @33457
12937 /* 33457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1036*/ GIMT_Encode4(33477), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1376 //
12938 /* 33464 */ // (intrinsic_void 8651:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
12939 /* 33464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
12940 /* 33467 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
12941 /* 33469 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12942 /* 33471 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12943 /* 33475 */ GIR_RootConstrainSelectedInstOperands,
12944 /* 33476 */ // GIR_Coverage, 1376,
12945 /* 33476 */ GIR_EraseRootFromParent_Done,
12946 /* 33477 */ // Label 1036: @33477
12947 /* 33477 */ GIM_Reject,
12948 /* 33478 */ // Label 1034: @33478
12949 /* 33478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(33520), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 426 //
12950 /* 33485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12951 /* 33490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12952 /* 33493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12953 /* 33496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12954 /* 33500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12955 /* 33504 */ // (intrinsic_w_chain:{ *:[v2i16] } 7983:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
12956 /* 33504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
12957 /* 33507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12958 /* 33509 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12959 /* 33511 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12960 /* 33514 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12961 /* 33518 */ GIR_RootConstrainSelectedInstOperands,
12962 /* 33519 */ // GIR_Coverage, 426,
12963 /* 33519 */ GIR_EraseRootFromParent_Done,
12964 /* 33520 */ // Label 1037: @33520
12965 /* 33520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(33562), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 427 //
12966 /* 33527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12967 /* 33532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12968 /* 33535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12969 /* 33538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12970 /* 33542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12971 /* 33546 */ // (intrinsic_w_chain:{ *:[i32] } 7985:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
12972 /* 33546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
12973 /* 33549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12974 /* 33551 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12975 /* 33553 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12976 /* 33556 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12977 /* 33560 */ GIR_RootConstrainSelectedInstOperands,
12978 /* 33561 */ // GIR_Coverage, 427,
12979 /* 33561 */ GIR_EraseRootFromParent_Done,
12980 /* 33562 */ // Label 1038: @33562
12981 /* 33562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(33604), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 513 //
12982 /* 33569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12983 /* 33574 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12984 /* 33577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12985 /* 33580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12986 /* 33584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12987 /* 33588 */ // (intrinsic_w_chain:{ *:[v4i8] } 7984:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
12988 /* 33588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
12989 /* 33591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12990 /* 33593 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12991 /* 33595 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12992 /* 33598 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12993 /* 33602 */ GIR_RootConstrainSelectedInstOperands,
12994 /* 33603 */ // GIR_Coverage, 513,
12995 /* 33603 */ GIR_EraseRootFromParent_Done,
12996 /* 33604 */ // Label 1039: @33604
12997 /* 33604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(33646), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1308 //
12998 /* 33611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12999 /* 33616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13000 /* 33619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13001 /* 33622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13002 /* 33626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13003 /* 33630 */ // (intrinsic_w_chain:{ *:[v2i16] } 7983:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
13004 /* 33630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
13005 /* 33633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13006 /* 33635 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13007 /* 33637 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13008 /* 33640 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13009 /* 33644 */ GIR_RootConstrainSelectedInstOperands,
13010 /* 33645 */ // GIR_Coverage, 1308,
13011 /* 33645 */ GIR_EraseRootFromParent_Done,
13012 /* 33646 */ // Label 1040: @33646
13013 /* 33646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(33688), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1309 //
13014 /* 33653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13015 /* 33658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13016 /* 33661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13017 /* 33664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13018 /* 33668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13019 /* 33672 */ // (intrinsic_w_chain:{ *:[i32] } 7985:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
13020 /* 33672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
13021 /* 33675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13022 /* 33677 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13023 /* 33679 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13024 /* 33682 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13025 /* 33686 */ GIR_RootConstrainSelectedInstOperands,
13026 /* 33687 */ // GIR_Coverage, 1309,
13027 /* 33687 */ GIR_EraseRootFromParent_Done,
13028 /* 33688 */ // Label 1041: @33688
13029 /* 33688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(33730), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1389 //
13030 /* 33695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13031 /* 33700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13032 /* 33703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13033 /* 33706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13034 /* 33710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13035 /* 33714 */ // (intrinsic_w_chain:{ *:[v4i8] } 7984:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
13036 /* 33714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
13037 /* 33717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13038 /* 33719 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13039 /* 33721 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13040 /* 33724 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13041 /* 33728 */ GIR_RootConstrainSelectedInstOperands,
13042 /* 33729 */ // GIR_Coverage, 1389,
13043 /* 33729 */ GIR_EraseRootFromParent_Done,
13044 /* 33730 */ // Label 1042: @33730
13045 /* 33730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(33772), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 480 //
13046 /* 33737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13047 /* 33742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13048 /* 33745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13049 /* 33748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13050 /* 33752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13051 /* 33756 */ // (intrinsic_void 8161:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13052 /* 33756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
13053 /* 33759 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13054 /* 33761 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13055 /* 33763 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13056 /* 33766 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13057 /* 33770 */ GIR_RootConstrainSelectedInstOperands,
13058 /* 33771 */ // GIR_Coverage, 480,
13059 /* 33771 */ GIR_EraseRootFromParent_Done,
13060 /* 33772 */ // Label 1043: @33772
13061 /* 33772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1044*/ GIMT_Encode4(33814), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 481 //
13062 /* 33779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13063 /* 33784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13064 /* 33787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13065 /* 33790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13066 /* 33794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13067 /* 33798 */ // (intrinsic_void 8163:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13068 /* 33798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
13069 /* 33801 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13070 /* 33803 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13071 /* 33805 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13072 /* 33808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13073 /* 33812 */ GIR_RootConstrainSelectedInstOperands,
13074 /* 33813 */ // GIR_Coverage, 481,
13075 /* 33813 */ GIR_EraseRootFromParent_Done,
13076 /* 33814 */ // Label 1044: @33814
13077 /* 33814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1045*/ GIMT_Encode4(33856), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 482 //
13078 /* 33821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13079 /* 33826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13080 /* 33829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13081 /* 33832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13082 /* 33836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13083 /* 33840 */ // (intrinsic_void 8162:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13084 /* 33840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
13085 /* 33843 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13086 /* 33845 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13087 /* 33847 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13088 /* 33850 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13089 /* 33854 */ GIR_RootConstrainSelectedInstOperands,
13090 /* 33855 */ // GIR_Coverage, 482,
13091 /* 33855 */ GIR_EraseRootFromParent_Done,
13092 /* 33856 */ // Label 1045: @33856
13093 /* 33856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(33898), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 486 //
13094 /* 33863 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13095 /* 33868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13096 /* 33871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13097 /* 33874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13098 /* 33878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13099 /* 33882 */ // (intrinsic_void 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13100 /* 33882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
13101 /* 33885 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13102 /* 33887 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13103 /* 33889 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13104 /* 33892 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13105 /* 33896 */ GIR_RootConstrainSelectedInstOperands,
13106 /* 33897 */ // GIR_Coverage, 486,
13107 /* 33897 */ GIR_EraseRootFromParent_Done,
13108 /* 33898 */ // Label 1046: @33898
13109 /* 33898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1047*/ GIMT_Encode4(33940), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 487 //
13110 /* 33905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13111 /* 33910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13112 /* 33913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13113 /* 33916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13114 /* 33920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13115 /* 33924 */ // (intrinsic_void 8154:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13116 /* 33924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
13117 /* 33927 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13118 /* 33929 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13119 /* 33931 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13120 /* 33934 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13121 /* 33938 */ GIR_RootConstrainSelectedInstOperands,
13122 /* 33939 */ // GIR_Coverage, 487,
13123 /* 33939 */ GIR_EraseRootFromParent_Done,
13124 /* 33940 */ // Label 1047: @33940
13125 /* 33940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1048*/ GIMT_Encode4(33982), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 488 //
13126 /* 33947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13127 /* 33952 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13128 /* 33955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13129 /* 33958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13130 /* 33962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13131 /* 33966 */ // (intrinsic_void 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13132 /* 33966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
13133 /* 33969 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13134 /* 33971 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13135 /* 33973 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13136 /* 33976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13137 /* 33980 */ GIR_RootConstrainSelectedInstOperands,
13138 /* 33981 */ // GIR_Coverage, 488,
13139 /* 33981 */ GIR_EraseRootFromParent_Done,
13140 /* 33982 */ // Label 1048: @33982
13141 /* 33982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(34024), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1380 //
13142 /* 33989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13143 /* 33994 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13144 /* 33997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13145 /* 34000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13146 /* 34004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13147 /* 34008 */ // (intrinsic_void 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13148 /* 34008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
13149 /* 34011 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13150 /* 34013 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13151 /* 34015 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13152 /* 34018 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13153 /* 34022 */ GIR_RootConstrainSelectedInstOperands,
13154 /* 34023 */ // GIR_Coverage, 1380,
13155 /* 34023 */ GIR_EraseRootFromParent_Done,
13156 /* 34024 */ // Label 1049: @34024
13157 /* 34024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1050*/ GIMT_Encode4(34066), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1381 //
13158 /* 34031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13159 /* 34036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13160 /* 34039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13161 /* 34042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13162 /* 34046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13163 /* 34050 */ // (intrinsic_void 8154:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13164 /* 34050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
13165 /* 34053 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13166 /* 34055 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13167 /* 34057 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13168 /* 34060 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13169 /* 34064 */ GIR_RootConstrainSelectedInstOperands,
13170 /* 34065 */ // GIR_Coverage, 1381,
13171 /* 34065 */ GIR_EraseRootFromParent_Done,
13172 /* 34066 */ // Label 1050: @34066
13173 /* 34066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1051*/ GIMT_Encode4(34108), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1382 //
13174 /* 34073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13175 /* 34078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13176 /* 34081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13177 /* 34084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13178 /* 34088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13179 /* 34092 */ // (intrinsic_void 8153:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13180 /* 34092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
13181 /* 34095 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13182 /* 34097 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13183 /* 34099 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13184 /* 34102 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13185 /* 34106 */ GIR_RootConstrainSelectedInstOperands,
13186 /* 34107 */ // GIR_Coverage, 1382,
13187 /* 34107 */ GIR_EraseRootFromParent_Done,
13188 /* 34108 */ // Label 1051: @34108
13189 /* 34108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1052*/ GIMT_Encode4(34150), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1386 //
13190 /* 34115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13191 /* 34120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13192 /* 34123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13193 /* 34126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13194 /* 34130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13195 /* 34134 */ // (intrinsic_void 8161:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13196 /* 34134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
13197 /* 34137 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13198 /* 34139 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13199 /* 34141 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13200 /* 34144 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13201 /* 34148 */ GIR_RootConstrainSelectedInstOperands,
13202 /* 34149 */ // GIR_Coverage, 1386,
13203 /* 34149 */ GIR_EraseRootFromParent_Done,
13204 /* 34150 */ // Label 1052: @34150
13205 /* 34150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1053*/ GIMT_Encode4(34192), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1387 //
13206 /* 34157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13207 /* 34162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13208 /* 34165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13209 /* 34168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13210 /* 34172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13211 /* 34176 */ // (intrinsic_void 8163:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13212 /* 34176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13213 /* 34179 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13214 /* 34181 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13215 /* 34183 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13216 /* 34186 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13217 /* 34190 */ GIR_RootConstrainSelectedInstOperands,
13218 /* 34191 */ // GIR_Coverage, 1387,
13219 /* 34191 */ GIR_EraseRootFromParent_Done,
13220 /* 34192 */ // Label 1053: @34192
13221 /* 34192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1054*/ GIMT_Encode4(34234), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1388 //
13222 /* 34199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13223 /* 34204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13224 /* 34207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13225 /* 34210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13226 /* 34214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13227 /* 34218 */ // (intrinsic_void 8162:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13228 /* 34218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13229 /* 34221 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13230 /* 34223 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13231 /* 34225 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13232 /* 34228 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13233 /* 34232 */ GIR_RootConstrainSelectedInstOperands,
13234 /* 34233 */ // GIR_Coverage, 1388,
13235 /* 34233 */ GIR_EraseRootFromParent_Done,
13236 /* 34234 */ // Label 1054: @34234
13237 /* 34234 */ GIM_Reject,
13238 /* 34235 */ // Label 1030: @34235
13239 /* 34235 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(38266),
13240 /* 34240 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
13241 /* 34243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1056*/ GIMT_Encode4(34306), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 445 //
13242 /* 34250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13243 /* 34255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13244 /* 34258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13245 /* 34261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13246 /* 34264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13247 /* 34268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13248 /* 34272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13249 /* 34276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13250 /* 34280 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13251 /* 34284 */ // MIs[1] Operand 1
13252 /* 34284 */ // No operand predicates
13253 /* 34284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13254 /* 34286 */ // (intrinsic_w_chain:{ *:[v2i16] } 8539:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13255 /* 34286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
13256 /* 34289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13257 /* 34291 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13258 /* 34293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13259 /* 34296 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13260 /* 34299 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13261 /* 34304 */ GIR_RootConstrainSelectedInstOperands,
13262 /* 34305 */ // GIR_Coverage, 445,
13263 /* 34305 */ GIR_EraseRootFromParent_Done,
13264 /* 34306 */ // Label 1056: @34306
13265 /* 34306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1057*/ GIMT_Encode4(34369), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 450 //
13266 /* 34313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13267 /* 34318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13268 /* 34321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13269 /* 34324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13270 /* 34327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13271 /* 34331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13272 /* 34335 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13273 /* 34339 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13274 /* 34343 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13275 /* 34347 */ // MIs[1] Operand 1
13276 /* 34347 */ // No operand predicates
13277 /* 34347 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13278 /* 34349 */ // (intrinsic_w_chain:{ *:[i32] } 8540:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13279 /* 34349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
13280 /* 34352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13281 /* 34354 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13282 /* 34356 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13283 /* 34359 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13284 /* 34362 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13285 /* 34367 */ GIR_RootConstrainSelectedInstOperands,
13286 /* 34368 */ // GIR_Coverage, 450,
13287 /* 34368 */ GIR_EraseRootFromParent_Done,
13288 /* 34369 */ // Label 1057: @34369
13289 /* 34369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1058*/ GIMT_Encode4(34432), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1317 //
13290 /* 34376 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13291 /* 34381 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13292 /* 34384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13293 /* 34387 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13294 /* 34390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13295 /* 34394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13296 /* 34398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13297 /* 34402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13298 /* 34406 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13299 /* 34410 */ // MIs[1] Operand 1
13300 /* 34410 */ // No operand predicates
13301 /* 34410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13302 /* 34412 */ // (intrinsic_w_chain:{ *:[v2i16] } 8539:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
13303 /* 34412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
13304 /* 34415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13305 /* 34417 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13306 /* 34419 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13307 /* 34422 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13308 /* 34425 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13309 /* 34430 */ GIR_RootConstrainSelectedInstOperands,
13310 /* 34431 */ // GIR_Coverage, 1317,
13311 /* 34431 */ GIR_EraseRootFromParent_Done,
13312 /* 34432 */ // Label 1058: @34432
13313 /* 34432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(34495), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1322 //
13314 /* 34439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13315 /* 34444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13316 /* 34447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13317 /* 34450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13318 /* 34453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13319 /* 34457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13320 /* 34461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13321 /* 34465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13322 /* 34469 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13323 /* 34473 */ // MIs[1] Operand 1
13324 /* 34473 */ // No operand predicates
13325 /* 34473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13326 /* 34475 */ // (intrinsic_w_chain:{ *:[i32] } 8540:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
13327 /* 34475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
13328 /* 34478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13329 /* 34480 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13330 /* 34482 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13331 /* 34485 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13332 /* 34488 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13333 /* 34493 */ GIR_RootConstrainSelectedInstOperands,
13334 /* 34494 */ // GIR_Coverage, 1322,
13335 /* 34494 */ GIR_EraseRootFromParent_Done,
13336 /* 34495 */ // Label 1059: @34495
13337 /* 34495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(34549), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2193 //
13338 /* 34502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13339 /* 34507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13340 /* 34510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13341 /* 34513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13342 /* 34516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13343 /* 34520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13344 /* 34524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13345 /* 34528 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13346 /* 34532 */ // MIs[1] Operand 1
13347 /* 34532 */ // No operand predicates
13348 /* 34532 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13349 /* 34534 */ // (intrinsic_w_chain:{ *:[v2i16] } 8537:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
13350 /* 34534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
13351 /* 34537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13352 /* 34539 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13353 /* 34541 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13354 /* 34544 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13355 /* 34547 */ GIR_RootConstrainSelectedInstOperands,
13356 /* 34548 */ // GIR_Coverage, 2193,
13357 /* 34548 */ GIR_EraseRootFromParent_Done,
13358 /* 34549 */ // Label 1060: @34549
13359 /* 34549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(34603), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2199 //
13360 /* 34556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13361 /* 34561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13362 /* 34564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13363 /* 34567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13364 /* 34570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13365 /* 34574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13366 /* 34578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13367 /* 34582 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
13368 /* 34586 */ // MIs[1] Operand 1
13369 /* 34586 */ // No operand predicates
13370 /* 34586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13371 /* 34588 */ // (intrinsic_w_chain:{ *:[v4i8] } 8538:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
13372 /* 34588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
13373 /* 34591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13374 /* 34593 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13375 /* 34595 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13376 /* 34598 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13377 /* 34601 */ GIR_RootConstrainSelectedInstOperands,
13378 /* 34602 */ // GIR_Coverage, 2199,
13379 /* 34602 */ GIR_EraseRootFromParent_Done,
13380 /* 34603 */ // Label 1061: @34603
13381 /* 34603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1062*/ GIMT_Encode4(34654), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 422 //
13382 /* 34610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13383 /* 34615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13384 /* 34618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13385 /* 34621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13386 /* 34624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13387 /* 34628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13388 /* 34632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13389 /* 34636 */ // (intrinsic_w_chain:{ *:[i32] } 7992:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13390 /* 34636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
13391 /* 34639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13392 /* 34641 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13393 /* 34643 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13394 /* 34645 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13395 /* 34648 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13396 /* 34652 */ GIR_RootConstrainSelectedInstOperands,
13397 /* 34653 */ // GIR_Coverage, 422,
13398 /* 34653 */ GIR_EraseRootFromParent_Done,
13399 /* 34654 */ // Label 1062: @34654
13400 /* 34654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1063*/ GIMT_Encode4(34705), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 423 //
13401 /* 34661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13402 /* 34666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13403 /* 34669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13404 /* 34672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13405 /* 34675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13406 /* 34679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13407 /* 34683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13408 /* 34687 */ // (intrinsic_w_chain:{ *:[i32] } 8612:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13409 /* 34687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
13410 /* 34690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13411 /* 34692 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13412 /* 34694 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13413 /* 34696 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13414 /* 34699 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13415 /* 34703 */ GIR_RootConstrainSelectedInstOperands,
13416 /* 34704 */ // GIR_Coverage, 423,
13417 /* 34704 */ GIR_EraseRootFromParent_Done,
13418 /* 34705 */ // Label 1063: @34705
13419 /* 34705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(34756), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 430 //
13420 /* 34712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
13421 /* 34717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13422 /* 34720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13423 /* 34723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13424 /* 34726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13425 /* 34730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13426 /* 34734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13427 /* 34738 */ // (intrinsic_w_chain:{ *:[v2i16] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13428 /* 34738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
13429 /* 34741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13430 /* 34743 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13431 /* 34745 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13432 /* 34747 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13433 /* 34750 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13434 /* 34754 */ GIR_RootConstrainSelectedInstOperands,
13435 /* 34755 */ // GIR_Coverage, 430,
13436 /* 34755 */ GIR_EraseRootFromParent_Done,
13437 /* 34756 */ // Label 1064: @34756
13438 /* 34756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(34807), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 431 //
13439 /* 34763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13440 /* 34768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13441 /* 34771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13442 /* 34774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13443 /* 34777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13444 /* 34781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13445 /* 34785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13446 /* 34789 */ // (intrinsic_w_chain:{ *:[v4i8] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13447 /* 34789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
13448 /* 34792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13449 /* 34794 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13450 /* 34796 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13451 /* 34798 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13452 /* 34801 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13453 /* 34805 */ GIR_RootConstrainSelectedInstOperands,
13454 /* 34806 */ // GIR_Coverage, 431,
13455 /* 34806 */ GIR_EraseRootFromParent_Done,
13456 /* 34807 */ // Label 1065: @34807
13457 /* 34807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1066*/ GIMT_Encode4(34858), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 442 //
13458 /* 34814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13459 /* 34819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13460 /* 34822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13461 /* 34825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13462 /* 34828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13463 /* 34832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13464 /* 34836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13465 /* 34840 */ // (intrinsic_w_chain:{ *:[v4i8] } 8538:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13466 /* 34840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
13467 /* 34843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13468 /* 34845 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13469 /* 34847 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13470 /* 34849 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13471 /* 34852 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13472 /* 34856 */ GIR_RootConstrainSelectedInstOperands,
13473 /* 34857 */ // GIR_Coverage, 442,
13474 /* 34857 */ GIR_EraseRootFromParent_Done,
13475 /* 34858 */ // Label 1066: @34858
13476 /* 34858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1067*/ GIMT_Encode4(34909), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 444 //
13477 /* 34865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13478 /* 34870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13479 /* 34873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13480 /* 34876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13481 /* 34879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13482 /* 34883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13483 /* 34887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13484 /* 34891 */ // (intrinsic_w_chain:{ *:[v2i16] } 8537:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13485 /* 34891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
13486 /* 34894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13487 /* 34896 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13488 /* 34898 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13489 /* 34900 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13490 /* 34903 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13491 /* 34907 */ GIR_RootConstrainSelectedInstOperands,
13492 /* 34908 */ // GIR_Coverage, 444,
13493 /* 34908 */ GIR_EraseRootFromParent_Done,
13494 /* 34909 */ // Label 1067: @34909
13495 /* 34909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(34960), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 446 //
13496 /* 34916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13497 /* 34921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13498 /* 34924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13499 /* 34927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13500 /* 34930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13501 /* 34934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13502 /* 34938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13503 /* 34942 */ // (intrinsic_w_chain:{ *:[v2i16] } 8539:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13504 /* 34942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
13505 /* 34945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13506 /* 34947 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13507 /* 34949 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13508 /* 34951 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13509 /* 34954 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13510 /* 34958 */ GIR_RootConstrainSelectedInstOperands,
13511 /* 34959 */ // GIR_Coverage, 446,
13512 /* 34959 */ GIR_EraseRootFromParent_Done,
13513 /* 34960 */ // Label 1068: @34960
13514 /* 34960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1069*/ GIMT_Encode4(35011), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 451 //
13515 /* 34967 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13516 /* 34972 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13517 /* 34975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13518 /* 34978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13519 /* 34981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13520 /* 34985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13521 /* 34989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13522 /* 34993 */ // (intrinsic_w_chain:{ *:[i32] } 8540:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13523 /* 34993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
13524 /* 34996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13525 /* 34998 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13526 /* 35000 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13527 /* 35002 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13528 /* 35005 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13529 /* 35009 */ GIR_RootConstrainSelectedInstOperands,
13530 /* 35010 */ // GIR_Coverage, 451,
13531 /* 35010 */ GIR_EraseRootFromParent_Done,
13532 /* 35011 */ // Label 1069: @35011
13533 /* 35011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1070*/ GIMT_Encode4(35062), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 454 //
13534 /* 35018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13535 /* 35023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13536 /* 35026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13537 /* 35029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13538 /* 35032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13539 /* 35036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13540 /* 35040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13541 /* 35044 */ // (intrinsic_w_chain:{ *:[v2i16] } 8460:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13542 /* 35044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
13543 /* 35047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13544 /* 35049 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13545 /* 35051 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13546 /* 35053 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13547 /* 35056 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13548 /* 35060 */ GIR_RootConstrainSelectedInstOperands,
13549 /* 35061 */ // GIR_Coverage, 454,
13550 /* 35061 */ GIR_EraseRootFromParent_Done,
13551 /* 35062 */ // Label 1070: @35062
13552 /* 35062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1071*/ GIMT_Encode4(35113), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 455 //
13553 /* 35069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13554 /* 35074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13555 /* 35077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13556 /* 35080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13557 /* 35083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13558 /* 35087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13559 /* 35091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13560 /* 35095 */ // (intrinsic_w_chain:{ *:[v2i16] } 8461:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13561 /* 35095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
13562 /* 35098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13563 /* 35100 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13564 /* 35102 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13565 /* 35104 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13566 /* 35107 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13567 /* 35111 */ GIR_RootConstrainSelectedInstOperands,
13568 /* 35112 */ // GIR_Coverage, 455,
13569 /* 35112 */ GIR_EraseRootFromParent_Done,
13570 /* 35113 */ // Label 1071: @35113
13571 /* 35113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1072*/ GIMT_Encode4(35164), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 456 //
13572 /* 35120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13573 /* 35125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13574 /* 35128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13575 /* 35131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13576 /* 35134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13577 /* 35138 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13578 /* 35142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13579 /* 35146 */ // (intrinsic_w_chain:{ *:[i32] } 8458:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13580 /* 35146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
13581 /* 35149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13582 /* 35151 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13583 /* 35153 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13584 /* 35155 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13585 /* 35158 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13586 /* 35162 */ GIR_RootConstrainSelectedInstOperands,
13587 /* 35163 */ // GIR_Coverage, 456,
13588 /* 35163 */ GIR_EraseRootFromParent_Done,
13589 /* 35164 */ // Label 1072: @35164
13590 /* 35164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1073*/ GIMT_Encode4(35215), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 457 //
13591 /* 35171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13592 /* 35176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13593 /* 35179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13594 /* 35182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13595 /* 35185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13596 /* 35189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13597 /* 35193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13598 /* 35197 */ // (intrinsic_w_chain:{ *:[i32] } 8459:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13599 /* 35197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
13600 /* 35200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13601 /* 35202 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13602 /* 35204 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13603 /* 35206 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13604 /* 35209 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13605 /* 35213 */ GIR_RootConstrainSelectedInstOperands,
13606 /* 35214 */ // GIR_Coverage, 457,
13607 /* 35214 */ GIR_EraseRootFromParent_Done,
13608 /* 35215 */ // Label 1073: @35215
13609 /* 35215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1074*/ GIMT_Encode4(35266), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 458 //
13610 /* 35222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13611 /* 35227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13612 /* 35230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13613 /* 35233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13614 /* 35236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13615 /* 35240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13616 /* 35244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13617 /* 35248 */ // (intrinsic_w_chain:{ *:[v2i16] } 8462:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13618 /* 35248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
13619 /* 35251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13620 /* 35253 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13621 /* 35255 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13622 /* 35257 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13623 /* 35260 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13624 /* 35264 */ GIR_RootConstrainSelectedInstOperands,
13625 /* 35265 */ // GIR_Coverage, 458,
13626 /* 35265 */ GIR_EraseRootFromParent_Done,
13627 /* 35266 */ // Label 1074: @35266
13628 /* 35266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1075*/ GIMT_Encode4(35314), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 483 //
13629 /* 35273 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
13630 /* 35278 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13631 /* 35281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13632 /* 35284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13633 /* 35287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13634 /* 35291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13635 /* 35295 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13636 /* 35299 */ // (intrinsic_w_chain:{ *:[i32] } 8158:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13637 /* 35299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
13638 /* 35302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13639 /* 35304 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13640 /* 35306 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13641 /* 35308 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13642 /* 35312 */ GIR_RootConstrainSelectedInstOperands,
13643 /* 35313 */ // GIR_Coverage, 483,
13644 /* 35313 */ GIR_EraseRootFromParent_Done,
13645 /* 35314 */ // Label 1075: @35314
13646 /* 35314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1076*/ GIMT_Encode4(35362), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 484 //
13647 /* 35321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
13648 /* 35326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13649 /* 35329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13650 /* 35332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13651 /* 35335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13652 /* 35339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13653 /* 35343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13654 /* 35347 */ // (intrinsic_w_chain:{ *:[i32] } 8160:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13655 /* 35347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
13656 /* 35350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13657 /* 35352 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13658 /* 35354 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13659 /* 35356 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13660 /* 35360 */ GIR_RootConstrainSelectedInstOperands,
13661 /* 35361 */ // GIR_Coverage, 484,
13662 /* 35361 */ GIR_EraseRootFromParent_Done,
13663 /* 35362 */ // Label 1076: @35362
13664 /* 35362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1077*/ GIMT_Encode4(35410), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 485 //
13665 /* 35369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
13666 /* 35374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13667 /* 35377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13668 /* 35380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13669 /* 35383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13670 /* 35387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13671 /* 35391 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13672 /* 35395 */ // (intrinsic_w_chain:{ *:[i32] } 8159:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13673 /* 35395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
13674 /* 35398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13675 /* 35400 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13676 /* 35402 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13677 /* 35404 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13678 /* 35408 */ GIR_RootConstrainSelectedInstOperands,
13679 /* 35409 */ // GIR_Coverage, 485,
13680 /* 35409 */ GIR_EraseRootFromParent_Done,
13681 /* 35410 */ // Label 1077: @35410
13682 /* 35410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(35458), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 495 //
13683 /* 35417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
13684 /* 35422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13685 /* 35425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13686 /* 35428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13687 /* 35431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13688 /* 35435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13689 /* 35439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13690 /* 35443 */ // (intrinsic_w_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13691 /* 35443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
13692 /* 35446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13693 /* 35448 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13694 /* 35450 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13695 /* 35452 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13696 /* 35456 */ GIR_RootConstrainSelectedInstOperands,
13697 /* 35457 */ // GIR_Coverage, 495,
13698 /* 35457 */ GIR_EraseRootFromParent_Done,
13699 /* 35458 */ // Label 1078: @35458
13700 /* 35458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(35506), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 496 //
13701 /* 35465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
13702 /* 35470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13703 /* 35473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13704 /* 35476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13705 /* 35479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13706 /* 35483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13707 /* 35487 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13708 /* 35491 */ // (intrinsic_w_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13709 /* 35491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
13710 /* 35494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13711 /* 35496 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13712 /* 35498 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13713 /* 35500 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13714 /* 35504 */ GIR_RootConstrainSelectedInstOperands,
13715 /* 35505 */ // GIR_Coverage, 496,
13716 /* 35505 */ GIR_EraseRootFromParent_Done,
13717 /* 35506 */ // Label 1079: @35506
13718 /* 35506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(35554), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 500 //
13719 /* 35513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13720 /* 35518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13721 /* 35521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13722 /* 35524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13723 /* 35527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13724 /* 35531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13725 /* 35535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13726 /* 35539 */ // (intrinsic_w_chain:{ *:[i32] } 8360:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13727 /* 35539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
13728 /* 35542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13729 /* 35544 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
13730 /* 35546 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13731 /* 35548 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13732 /* 35552 */ GIR_RootConstrainSelectedInstOperands,
13733 /* 35553 */ // GIR_Coverage, 500,
13734 /* 35553 */ GIR_EraseRootFromParent_Done,
13735 /* 35554 */ // Label 1080: @35554
13736 /* 35554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1081*/ GIMT_Encode4(35605), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 506 //
13737 /* 35561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
13738 /* 35566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13739 /* 35569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13740 /* 35572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13741 /* 35575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13742 /* 35579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13743 /* 35583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13744 /* 35587 */ // (intrinsic_w_chain:{ *:[v2i16] } 8010:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13745 /* 35587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
13746 /* 35590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13747 /* 35592 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13748 /* 35594 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13749 /* 35596 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13750 /* 35599 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13751 /* 35603 */ GIR_RootConstrainSelectedInstOperands,
13752 /* 35604 */ // GIR_Coverage, 506,
13753 /* 35604 */ GIR_EraseRootFromParent_Done,
13754 /* 35605 */ // Label 1081: @35605
13755 /* 35605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1082*/ GIMT_Encode4(35656), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 507 //
13756 /* 35612 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
13757 /* 35617 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13758 /* 35620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13759 /* 35623 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13760 /* 35626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13761 /* 35630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13762 /* 35634 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13763 /* 35638 */ // (intrinsic_w_chain:{ *:[v2i16] } 8012:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13764 /* 35638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
13765 /* 35641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13766 /* 35643 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13767 /* 35645 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13768 /* 35647 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13769 /* 35650 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13770 /* 35654 */ GIR_RootConstrainSelectedInstOperands,
13771 /* 35655 */ // GIR_Coverage, 507,
13772 /* 35655 */ GIR_EraseRootFromParent_Done,
13773 /* 35656 */ // Label 1082: @35656
13774 /* 35656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(35707), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 508 //
13775 /* 35663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
13776 /* 35668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13777 /* 35671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13778 /* 35674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13779 /* 35677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13780 /* 35681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13781 /* 35685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13782 /* 35689 */ // (intrinsic_w_chain:{ *:[v2i16] } 8633:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13783 /* 35689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
13784 /* 35692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13785 /* 35694 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13786 /* 35696 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13787 /* 35698 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13788 /* 35701 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13789 /* 35705 */ GIR_RootConstrainSelectedInstOperands,
13790 /* 35706 */ // GIR_Coverage, 508,
13791 /* 35706 */ GIR_EraseRootFromParent_Done,
13792 /* 35707 */ // Label 1083: @35707
13793 /* 35707 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(35758), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 509 //
13794 /* 35714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
13795 /* 35719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13796 /* 35722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13797 /* 35725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13798 /* 35728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13799 /* 35732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13800 /* 35736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13801 /* 35740 */ // (intrinsic_w_chain:{ *:[v2i16] } 8635:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13802 /* 35740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
13803 /* 35743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13804 /* 35745 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13805 /* 35747 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13806 /* 35749 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13807 /* 35752 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13808 /* 35756 */ GIR_RootConstrainSelectedInstOperands,
13809 /* 35757 */ // GIR_Coverage, 509,
13810 /* 35757 */ GIR_EraseRootFromParent_Done,
13811 /* 35758 */ // Label 1084: @35758
13812 /* 35758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1085*/ GIMT_Encode4(35809), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 510 //
13813 /* 35765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13814 /* 35770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13815 /* 35773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13816 /* 35776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13817 /* 35779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13818 /* 35783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13819 /* 35787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13820 /* 35791 */ // (intrinsic_w_chain:{ *:[i32] } 8155:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13821 /* 35791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
13822 /* 35794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13823 /* 35796 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13824 /* 35798 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13825 /* 35800 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13826 /* 35803 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13827 /* 35807 */ GIR_RootConstrainSelectedInstOperands,
13828 /* 35808 */ // GIR_Coverage, 510,
13829 /* 35808 */ GIR_EraseRootFromParent_Done,
13830 /* 35809 */ // Label 1085: @35809
13831 /* 35809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1086*/ GIMT_Encode4(35860), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 511 //
13832 /* 35816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13833 /* 35821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13834 /* 35824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13835 /* 35827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13836 /* 35830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13837 /* 35834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13838 /* 35838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13839 /* 35842 */ // (intrinsic_w_chain:{ *:[i32] } 8157:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13840 /* 35842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
13841 /* 35845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13842 /* 35847 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13843 /* 35849 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13844 /* 35851 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13845 /* 35854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13846 /* 35858 */ GIR_RootConstrainSelectedInstOperands,
13847 /* 35859 */ // GIR_Coverage, 511,
13848 /* 35859 */ GIR_EraseRootFromParent_Done,
13849 /* 35860 */ // Label 1086: @35860
13850 /* 35860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(35911), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 512 //
13851 /* 35867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13852 /* 35872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13853 /* 35875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13854 /* 35878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13855 /* 35881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13856 /* 35885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13857 /* 35889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13858 /* 35893 */ // (intrinsic_w_chain:{ *:[i32] } 8156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13859 /* 35893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
13860 /* 35896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13861 /* 35898 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13862 /* 35900 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13863 /* 35902 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13864 /* 35905 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13865 /* 35909 */ GIR_RootConstrainSelectedInstOperands,
13866 /* 35910 */ // GIR_Coverage, 512,
13867 /* 35910 */ GIR_EraseRootFromParent_Done,
13868 /* 35911 */ // Label 1087: @35911
13869 /* 35911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1088*/ GIMT_Encode4(35962), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 526 //
13870 /* 35918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13871 /* 35923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13872 /* 35926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13873 /* 35929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13874 /* 35932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13875 /* 35936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13876 /* 35940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13877 /* 35944 */ // (intrinsic_w_chain:{ *:[v2i16] } 8457:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13878 /* 35944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
13879 /* 35947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13880 /* 35949 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13881 /* 35951 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13882 /* 35953 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13883 /* 35956 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13884 /* 35960 */ GIR_RootConstrainSelectedInstOperands,
13885 /* 35961 */ // GIR_Coverage, 526,
13886 /* 35961 */ GIR_EraseRootFromParent_Done,
13887 /* 35962 */ // Label 1088: @35962
13888 /* 35962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1089*/ GIMT_Encode4(36013), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 527 //
13889 /* 35969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13890 /* 35974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13891 /* 35977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13892 /* 35980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13893 /* 35983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13894 /* 35987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13895 /* 35991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13896 /* 35995 */ // (intrinsic_w_chain:{ *:[i32] } 8465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13897 /* 35995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
13898 /* 35998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13899 /* 36000 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13900 /* 36002 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13901 /* 36004 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13902 /* 36007 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13903 /* 36011 */ GIR_RootConstrainSelectedInstOperands,
13904 /* 36012 */ // GIR_Coverage, 527,
13905 /* 36012 */ GIR_EraseRootFromParent_Done,
13906 /* 36013 */ // Label 1089: @36013
13907 /* 36013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1090*/ GIMT_Encode4(36064), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 528 //
13908 /* 36020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13909 /* 36025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13910 /* 36028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13911 /* 36031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13912 /* 36034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13913 /* 36038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13914 /* 36042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13915 /* 36046 */ // (intrinsic_w_chain:{ *:[i32] } 8463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13916 /* 36046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
13917 /* 36049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13918 /* 36051 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13919 /* 36053 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13920 /* 36055 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13921 /* 36058 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13922 /* 36062 */ GIR_RootConstrainSelectedInstOperands,
13923 /* 36063 */ // GIR_Coverage, 528,
13924 /* 36063 */ GIR_EraseRootFromParent_Done,
13925 /* 36064 */ // Label 1090: @36064
13926 /* 36064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1091*/ GIMT_Encode4(36115), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 529 //
13927 /* 36071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13928 /* 36076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13929 /* 36079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13930 /* 36082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13931 /* 36085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13932 /* 36089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13933 /* 36093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13934 /* 36097 */ // (intrinsic_w_chain:{ *:[v2i16] } 8464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13935 /* 36097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
13936 /* 36100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13937 /* 36102 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13938 /* 36104 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13939 /* 36106 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13940 /* 36109 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13941 /* 36113 */ GIR_RootConstrainSelectedInstOperands,
13942 /* 36114 */ // GIR_Coverage, 529,
13943 /* 36114 */ GIR_EraseRootFromParent_Done,
13944 /* 36115 */ // Label 1091: @36115
13945 /* 36115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1092*/ GIMT_Encode4(36163), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 539 //
13946 /* 36122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13947 /* 36127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13948 /* 36130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13949 /* 36133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13950 /* 36136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13951 /* 36140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13952 /* 36144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13953 /* 36148 */ // (intrinsic_w_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13954 /* 36148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
13955 /* 36151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13956 /* 36153 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13957 /* 36155 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13958 /* 36157 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13959 /* 36161 */ GIR_RootConstrainSelectedInstOperands,
13960 /* 36162 */ // GIR_Coverage, 539,
13961 /* 36162 */ GIR_EraseRootFromParent_Done,
13962 /* 36163 */ // Label 1092: @36163
13963 /* 36163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1093*/ GIMT_Encode4(36214), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1302 //
13964 /* 36170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13965 /* 36175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13966 /* 36178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13967 /* 36181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13968 /* 36184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13969 /* 36188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13970 /* 36192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13971 /* 36196 */ // (intrinsic_w_chain:{ *:[i32] } 7992:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13972 /* 36196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
13973 /* 36199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13974 /* 36201 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13975 /* 36203 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13976 /* 36205 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13977 /* 36208 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13978 /* 36212 */ GIR_RootConstrainSelectedInstOperands,
13979 /* 36213 */ // GIR_Coverage, 1302,
13980 /* 36213 */ GIR_EraseRootFromParent_Done,
13981 /* 36214 */ // Label 1093: @36214
13982 /* 36214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1094*/ GIMT_Encode4(36262), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1310 //
13983 /* 36221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13984 /* 36226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13985 /* 36229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13986 /* 36232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13987 /* 36235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13988 /* 36239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13989 /* 36243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13990 /* 36247 */ // (intrinsic_w_chain:{ *:[i32] } 8360:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13991 /* 36247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
13992 /* 36250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13993 /* 36252 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
13994 /* 36254 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13995 /* 36256 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13996 /* 36260 */ GIR_RootConstrainSelectedInstOperands,
13997 /* 36261 */ // GIR_Coverage, 1310,
13998 /* 36261 */ GIR_EraseRootFromParent_Done,
13999 /* 36262 */ // Label 1094: @36262
14000 /* 36262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1095*/ GIMT_Encode4(36313), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1318 //
14001 /* 36269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14002 /* 36274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14003 /* 36277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14004 /* 36280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14005 /* 36283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14006 /* 36287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14007 /* 36291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14008 /* 36295 */ // (intrinsic_w_chain:{ *:[v2i16] } 8537:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14009 /* 36295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
14010 /* 36298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14011 /* 36300 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14012 /* 36302 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14013 /* 36304 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14014 /* 36307 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14015 /* 36311 */ GIR_RootConstrainSelectedInstOperands,
14016 /* 36312 */ // GIR_Coverage, 1318,
14017 /* 36312 */ GIR_EraseRootFromParent_Done,
14018 /* 36313 */ // Label 1095: @36313
14019 /* 36313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1096*/ GIMT_Encode4(36364), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1319 //
14020 /* 36320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14021 /* 36325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14022 /* 36328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14023 /* 36331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14024 /* 36334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14025 /* 36338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14026 /* 36342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14027 /* 36346 */ // (intrinsic_w_chain:{ *:[v2i16] } 8539:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14028 /* 36346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
14029 /* 36349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14030 /* 36351 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14031 /* 36353 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14032 /* 36355 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14033 /* 36358 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14034 /* 36362 */ GIR_RootConstrainSelectedInstOperands,
14035 /* 36363 */ // GIR_Coverage, 1319,
14036 /* 36363 */ GIR_EraseRootFromParent_Done,
14037 /* 36364 */ // Label 1096: @36364
14038 /* 36364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(36415), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1320 //
14039 /* 36371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14040 /* 36376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14041 /* 36379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14042 /* 36382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14043 /* 36385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14044 /* 36389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14045 /* 36393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14046 /* 36397 */ // (intrinsic_w_chain:{ *:[v4i8] } 8538:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14047 /* 36397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
14048 /* 36400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14049 /* 36402 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14050 /* 36404 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14051 /* 36406 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14052 /* 36409 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14053 /* 36413 */ GIR_RootConstrainSelectedInstOperands,
14054 /* 36414 */ // GIR_Coverage, 1320,
14055 /* 36414 */ GIR_EraseRootFromParent_Done,
14056 /* 36415 */ // Label 1097: @36415
14057 /* 36415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(36466), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1321 //
14058 /* 36422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14059 /* 36427 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14060 /* 36430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14061 /* 36433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14062 /* 36436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14063 /* 36440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14064 /* 36444 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14065 /* 36448 */ // (intrinsic_w_chain:{ *:[i32] } 8540:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14066 /* 36448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
14067 /* 36451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14068 /* 36453 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14069 /* 36455 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14070 /* 36457 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14071 /* 36460 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14072 /* 36464 */ GIR_RootConstrainSelectedInstOperands,
14073 /* 36465 */ // GIR_Coverage, 1321,
14074 /* 36465 */ GIR_EraseRootFromParent_Done,
14075 /* 36466 */ // Label 1098: @36466
14076 /* 36466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(36517), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1340 //
14077 /* 36473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14078 /* 36478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14079 /* 36481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14080 /* 36484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14081 /* 36487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14082 /* 36491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14083 /* 36495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14084 /* 36499 */ // (intrinsic_w_chain:{ *:[i32] } 8612:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14085 /* 36499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
14086 /* 36502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14087 /* 36504 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14088 /* 36506 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14089 /* 36508 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14090 /* 36511 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14091 /* 36515 */ GIR_RootConstrainSelectedInstOperands,
14092 /* 36516 */ // GIR_Coverage, 1340,
14093 /* 36516 */ GIR_EraseRootFromParent_Done,
14094 /* 36517 */ // Label 1099: @36517
14095 /* 36517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1100*/ GIMT_Encode4(36568), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1346 //
14096 /* 36524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14097 /* 36529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14098 /* 36532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14099 /* 36535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14100 /* 36538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14101 /* 36542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14102 /* 36546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14103 /* 36550 */ // (intrinsic_w_chain:{ *:[i32] } 8458:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14104 /* 36550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
14105 /* 36553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14106 /* 36555 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14107 /* 36557 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14108 /* 36559 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14109 /* 36562 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14110 /* 36566 */ GIR_RootConstrainSelectedInstOperands,
14111 /* 36567 */ // GIR_Coverage, 1346,
14112 /* 36567 */ GIR_EraseRootFromParent_Done,
14113 /* 36568 */ // Label 1100: @36568
14114 /* 36568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1101*/ GIMT_Encode4(36619), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1347 //
14115 /* 36575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14116 /* 36580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14117 /* 36583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14118 /* 36586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14119 /* 36589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14120 /* 36593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14121 /* 36597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14122 /* 36601 */ // (intrinsic_w_chain:{ *:[i32] } 8459:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14123 /* 36601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
14124 /* 36604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14125 /* 36606 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14126 /* 36608 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14127 /* 36610 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14128 /* 36613 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14129 /* 36617 */ GIR_RootConstrainSelectedInstOperands,
14130 /* 36618 */ // GIR_Coverage, 1347,
14131 /* 36618 */ GIR_EraseRootFromParent_Done,
14132 /* 36619 */ // Label 1101: @36619
14133 /* 36619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(36670), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1348 //
14134 /* 36626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14135 /* 36631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14136 /* 36634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14137 /* 36637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14138 /* 36640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14139 /* 36644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14140 /* 36648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14141 /* 36652 */ // (intrinsic_w_chain:{ *:[v2i16] } 8460:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14142 /* 36652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
14143 /* 36655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14144 /* 36657 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14145 /* 36659 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14146 /* 36661 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14147 /* 36664 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14148 /* 36668 */ GIR_RootConstrainSelectedInstOperands,
14149 /* 36669 */ // GIR_Coverage, 1348,
14150 /* 36669 */ GIR_EraseRootFromParent_Done,
14151 /* 36670 */ // Label 1102: @36670
14152 /* 36670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(36721), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1349 //
14153 /* 36677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14154 /* 36682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14155 /* 36685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14156 /* 36688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14157 /* 36691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14158 /* 36695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14159 /* 36699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14160 /* 36703 */ // (intrinsic_w_chain:{ *:[v2i16] } 8461:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14161 /* 36703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
14162 /* 36706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14163 /* 36708 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14164 /* 36710 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14165 /* 36712 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14166 /* 36715 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14167 /* 36719 */ GIR_RootConstrainSelectedInstOperands,
14168 /* 36720 */ // GIR_Coverage, 1349,
14169 /* 36720 */ GIR_EraseRootFromParent_Done,
14170 /* 36721 */ // Label 1103: @36721
14171 /* 36721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1104*/ GIMT_Encode4(36772), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1350 //
14172 /* 36728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14173 /* 36733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14174 /* 36736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14175 /* 36739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14176 /* 36742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14177 /* 36746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14178 /* 36750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14179 /* 36754 */ // (intrinsic_w_chain:{ *:[v2i16] } 8462:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14180 /* 36754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
14181 /* 36757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14182 /* 36759 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14183 /* 36761 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14184 /* 36763 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14185 /* 36766 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14186 /* 36770 */ GIR_RootConstrainSelectedInstOperands,
14187 /* 36771 */ // GIR_Coverage, 1350,
14188 /* 36771 */ GIR_EraseRootFromParent_Done,
14189 /* 36772 */ // Label 1104: @36772
14190 /* 36772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1105*/ GIMT_Encode4(36823), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1353 //
14191 /* 36779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14192 /* 36784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14193 /* 36787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14194 /* 36790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14195 /* 36793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14196 /* 36797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14197 /* 36801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14198 /* 36805 */ // (intrinsic_w_chain:{ *:[v4i8] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14199 /* 36805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
14200 /* 36808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14201 /* 36810 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14202 /* 36812 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14203 /* 36814 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14204 /* 36817 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14205 /* 36821 */ GIR_RootConstrainSelectedInstOperands,
14206 /* 36822 */ // GIR_Coverage, 1353,
14207 /* 36822 */ GIR_EraseRootFromParent_Done,
14208 /* 36823 */ // Label 1105: @36823
14209 /* 36823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(36874), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1354 //
14210 /* 36830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14211 /* 36835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14212 /* 36838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14213 /* 36841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14214 /* 36844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14215 /* 36848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14216 /* 36852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14217 /* 36856 */ // (intrinsic_w_chain:{ *:[v2i16] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14218 /* 36856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14219 /* 36859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14220 /* 36861 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14221 /* 36863 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14222 /* 36865 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14223 /* 36868 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14224 /* 36872 */ GIR_RootConstrainSelectedInstOperands,
14225 /* 36873 */ // GIR_Coverage, 1354,
14226 /* 36873 */ GIR_EraseRootFromParent_Done,
14227 /* 36874 */ // Label 1106: @36874
14228 /* 36874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1107*/ GIMT_Encode4(36922), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1372 //
14229 /* 36881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
14230 /* 36886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14231 /* 36889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14232 /* 36892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14233 /* 36895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14234 /* 36899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14235 /* 36903 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14236 /* 36907 */ // (intrinsic_w_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14237 /* 36907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
14238 /* 36910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14239 /* 36912 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14240 /* 36914 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14241 /* 36916 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14242 /* 36920 */ GIR_RootConstrainSelectedInstOperands,
14243 /* 36921 */ // GIR_Coverage, 1372,
14244 /* 36921 */ GIR_EraseRootFromParent_Done,
14245 /* 36922 */ // Label 1107: @36922
14246 /* 36922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1108*/ GIMT_Encode4(36970), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1373 //
14247 /* 36929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
14248 /* 36934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14249 /* 36937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14250 /* 36940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14251 /* 36943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14252 /* 36947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14253 /* 36951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14254 /* 36955 */ // (intrinsic_w_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14255 /* 36955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
14256 /* 36958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14257 /* 36960 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14258 /* 36962 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14259 /* 36964 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14260 /* 36968 */ GIR_RootConstrainSelectedInstOperands,
14261 /* 36969 */ // GIR_Coverage, 1373,
14262 /* 36969 */ GIR_EraseRootFromParent_Done,
14263 /* 36970 */ // Label 1108: @36970
14264 /* 36970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(37018), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1383 //
14265 /* 36977 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14266 /* 36982 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14267 /* 36985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14268 /* 36988 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14269 /* 36991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14270 /* 36995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14271 /* 36999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14272 /* 37003 */ // (intrinsic_w_chain:{ *:[i32] } 8158:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14273 /* 37003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
14274 /* 37006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14275 /* 37008 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14276 /* 37010 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14277 /* 37012 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14278 /* 37016 */ GIR_RootConstrainSelectedInstOperands,
14279 /* 37017 */ // GIR_Coverage, 1383,
14280 /* 37017 */ GIR_EraseRootFromParent_Done,
14281 /* 37018 */ // Label 1109: @37018
14282 /* 37018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1110*/ GIMT_Encode4(37066), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1384 //
14283 /* 37025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14284 /* 37030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14285 /* 37033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14286 /* 37036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14287 /* 37039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14288 /* 37043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14289 /* 37047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14290 /* 37051 */ // (intrinsic_w_chain:{ *:[i32] } 8160:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14291 /* 37051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
14292 /* 37054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14293 /* 37056 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14294 /* 37058 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14295 /* 37060 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14296 /* 37064 */ GIR_RootConstrainSelectedInstOperands,
14297 /* 37065 */ // GIR_Coverage, 1384,
14298 /* 37065 */ GIR_EraseRootFromParent_Done,
14299 /* 37066 */ // Label 1110: @37066
14300 /* 37066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1111*/ GIMT_Encode4(37114), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1385 //
14301 /* 37073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14302 /* 37078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14303 /* 37081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14304 /* 37084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14305 /* 37087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14306 /* 37091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14307 /* 37095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14308 /* 37099 */ // (intrinsic_w_chain:{ *:[i32] } 8159:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14309 /* 37099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
14310 /* 37102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14311 /* 37104 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14312 /* 37106 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14313 /* 37108 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14314 /* 37112 */ GIR_RootConstrainSelectedInstOperands,
14315 /* 37113 */ // GIR_Coverage, 1385,
14316 /* 37113 */ GIR_EraseRootFromParent_Done,
14317 /* 37114 */ // Label 1111: @37114
14318 /* 37114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1112*/ GIMT_Encode4(37165), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1394 //
14319 /* 37121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
14320 /* 37126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14321 /* 37129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14322 /* 37132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14323 /* 37135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14324 /* 37139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14325 /* 37143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14326 /* 37147 */ // (intrinsic_w_chain:{ *:[v2i16] } 8010:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14327 /* 37147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
14328 /* 37150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14329 /* 37152 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14330 /* 37154 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14331 /* 37156 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14332 /* 37159 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14333 /* 37163 */ GIR_RootConstrainSelectedInstOperands,
14334 /* 37164 */ // GIR_Coverage, 1394,
14335 /* 37164 */ GIR_EraseRootFromParent_Done,
14336 /* 37165 */ // Label 1112: @37165
14337 /* 37165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(37216), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1395 //
14338 /* 37172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14339 /* 37177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14340 /* 37180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14341 /* 37183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14342 /* 37186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14343 /* 37190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14344 /* 37194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14345 /* 37198 */ // (intrinsic_w_chain:{ *:[v2i16] } 8012:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14346 /* 37198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
14347 /* 37201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14348 /* 37203 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14349 /* 37205 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14350 /* 37207 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14351 /* 37210 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14352 /* 37214 */ GIR_RootConstrainSelectedInstOperands,
14353 /* 37215 */ // GIR_Coverage, 1395,
14354 /* 37215 */ GIR_EraseRootFromParent_Done,
14355 /* 37216 */ // Label 1113: @37216
14356 /* 37216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(37267), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1406 //
14357 /* 37223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14358 /* 37228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14359 /* 37231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14360 /* 37234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14361 /* 37237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14362 /* 37241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14363 /* 37245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14364 /* 37249 */ // (intrinsic_w_chain:{ *:[i32] } 8155:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14365 /* 37249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
14366 /* 37252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14367 /* 37254 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14368 /* 37256 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14369 /* 37258 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14370 /* 37261 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14371 /* 37265 */ GIR_RootConstrainSelectedInstOperands,
14372 /* 37266 */ // GIR_Coverage, 1406,
14373 /* 37266 */ GIR_EraseRootFromParent_Done,
14374 /* 37267 */ // Label 1114: @37267
14375 /* 37267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1115*/ GIMT_Encode4(37318), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1407 //
14376 /* 37274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14377 /* 37279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14378 /* 37282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14379 /* 37285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14380 /* 37288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14381 /* 37292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14382 /* 37296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14383 /* 37300 */ // (intrinsic_w_chain:{ *:[i32] } 8157:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14384 /* 37300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
14385 /* 37303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14386 /* 37305 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14387 /* 37307 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14388 /* 37309 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14389 /* 37312 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14390 /* 37316 */ GIR_RootConstrainSelectedInstOperands,
14391 /* 37317 */ // GIR_Coverage, 1407,
14392 /* 37317 */ GIR_EraseRootFromParent_Done,
14393 /* 37318 */ // Label 1115: @37318
14394 /* 37318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1116*/ GIMT_Encode4(37369), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1408 //
14395 /* 37325 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14396 /* 37330 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14397 /* 37333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14398 /* 37336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14399 /* 37339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14400 /* 37343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14401 /* 37347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14402 /* 37351 */ // (intrinsic_w_chain:{ *:[i32] } 8156:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14403 /* 37351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
14404 /* 37354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14405 /* 37356 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14406 /* 37358 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14407 /* 37360 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14408 /* 37363 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14409 /* 37367 */ GIR_RootConstrainSelectedInstOperands,
14410 /* 37368 */ // GIR_Coverage, 1408,
14411 /* 37368 */ GIR_EraseRootFromParent_Done,
14412 /* 37369 */ // Label 1116: @37369
14413 /* 37369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1117*/ GIMT_Encode4(37420), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1414 //
14414 /* 37376 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
14415 /* 37381 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14416 /* 37384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14417 /* 37387 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14418 /* 37390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14419 /* 37394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14420 /* 37398 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14421 /* 37402 */ // (intrinsic_w_chain:{ *:[v2i16] } 8633:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14422 /* 37402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
14423 /* 37405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14424 /* 37407 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14425 /* 37409 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14426 /* 37411 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14427 /* 37414 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14428 /* 37418 */ GIR_RootConstrainSelectedInstOperands,
14429 /* 37419 */ // GIR_Coverage, 1414,
14430 /* 37419 */ GIR_EraseRootFromParent_Done,
14431 /* 37420 */ // Label 1117: @37420
14432 /* 37420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1118*/ GIMT_Encode4(37471), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1415 //
14433 /* 37427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14434 /* 37432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14435 /* 37435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14436 /* 37438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14437 /* 37441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14438 /* 37445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14439 /* 37449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14440 /* 37453 */ // (intrinsic_w_chain:{ *:[v2i16] } 8635:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14441 /* 37453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
14442 /* 37456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14443 /* 37458 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14444 /* 37460 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14445 /* 37462 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14446 /* 37465 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14447 /* 37469 */ GIR_RootConstrainSelectedInstOperands,
14448 /* 37470 */ // GIR_Coverage, 1415,
14449 /* 37470 */ GIR_EraseRootFromParent_Done,
14450 /* 37471 */ // Label 1118: @37471
14451 /* 37471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(37522), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1422 //
14452 /* 37478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14453 /* 37483 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14454 /* 37486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14455 /* 37489 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14456 /* 37492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14457 /* 37496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14458 /* 37500 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14459 /* 37504 */ // (intrinsic_w_chain:{ *:[v2i16] } 8457:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14460 /* 37504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
14461 /* 37507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14462 /* 37509 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14463 /* 37511 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14464 /* 37513 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14465 /* 37516 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14466 /* 37520 */ GIR_RootConstrainSelectedInstOperands,
14467 /* 37521 */ // GIR_Coverage, 1422,
14468 /* 37521 */ GIR_EraseRootFromParent_Done,
14469 /* 37522 */ // Label 1119: @37522
14470 /* 37522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1120*/ GIMT_Encode4(37573), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1423 //
14471 /* 37529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14472 /* 37534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14473 /* 37537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14474 /* 37540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14475 /* 37543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14476 /* 37547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14477 /* 37551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14478 /* 37555 */ // (intrinsic_w_chain:{ *:[i32] } 8463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14479 /* 37555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
14480 /* 37558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14481 /* 37560 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14482 /* 37562 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14483 /* 37564 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14484 /* 37567 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14485 /* 37571 */ GIR_RootConstrainSelectedInstOperands,
14486 /* 37572 */ // GIR_Coverage, 1423,
14487 /* 37572 */ GIR_EraseRootFromParent_Done,
14488 /* 37573 */ // Label 1120: @37573
14489 /* 37573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1121*/ GIMT_Encode4(37624), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1424 //
14490 /* 37580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14491 /* 37585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14492 /* 37588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14493 /* 37591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14494 /* 37594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14495 /* 37598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14496 /* 37602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14497 /* 37606 */ // (intrinsic_w_chain:{ *:[v2i16] } 8464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14498 /* 37606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
14499 /* 37609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14500 /* 37611 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14501 /* 37613 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14502 /* 37615 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14503 /* 37618 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14504 /* 37622 */ GIR_RootConstrainSelectedInstOperands,
14505 /* 37623 */ // GIR_Coverage, 1424,
14506 /* 37623 */ GIR_EraseRootFromParent_Done,
14507 /* 37624 */ // Label 1121: @37624
14508 /* 37624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1122*/ GIMT_Encode4(37675), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1425 //
14509 /* 37631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14510 /* 37636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14511 /* 37639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14512 /* 37642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14513 /* 37645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14514 /* 37649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14515 /* 37653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14516 /* 37657 */ // (intrinsic_w_chain:{ *:[i32] } 8465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14517 /* 37657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
14518 /* 37660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14519 /* 37662 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14520 /* 37664 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14521 /* 37666 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14522 /* 37669 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14523 /* 37673 */ GIR_RootConstrainSelectedInstOperands,
14524 /* 37674 */ // GIR_Coverage, 1425,
14525 /* 37674 */ GIR_EraseRootFromParent_Done,
14526 /* 37675 */ // Label 1122: @37675
14527 /* 37675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1123*/ GIMT_Encode4(37723), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1426 //
14528 /* 37682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14529 /* 37687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14530 /* 37690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14531 /* 37693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14532 /* 37696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14533 /* 37700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14534 /* 37704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14535 /* 37708 */ // (intrinsic_w_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14536 /* 37708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
14537 /* 37711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14538 /* 37713 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14539 /* 37715 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14540 /* 37717 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14541 /* 37721 */ GIR_RootConstrainSelectedInstOperands,
14542 /* 37722 */ // GIR_Coverage, 1426,
14543 /* 37722 */ GIR_EraseRootFromParent_Done,
14544 /* 37723 */ // Label 1123: @37723
14545 /* 37723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1124*/ GIMT_Encode4(37766), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2180 //
14546 /* 37730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
14547 /* 37735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14548 /* 37738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14549 /* 37741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14550 /* 37744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14551 /* 37748 */ // (intrinsic_w_chain:{ *:[v2i16] } 8454:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
14552 /* 37748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
14553 /* 37751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14554 /* 37753 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14555 /* 37755 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14556 /* 37757 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14557 /* 37760 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14558 /* 37764 */ GIR_RootConstrainSelectedInstOperands,
14559 /* 37765 */ // GIR_Coverage, 2180,
14560 /* 37765 */ GIR_EraseRootFromParent_Done,
14561 /* 37766 */ // Label 1124: @37766
14562 /* 37766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1125*/ GIMT_Encode4(37809), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2186 //
14563 /* 37773 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
14564 /* 37778 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14565 /* 37781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14566 /* 37784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14567 /* 37787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14568 /* 37791 */ // (intrinsic_w_chain:{ *:[i32] } 8009:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14569 /* 37791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
14570 /* 37794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14571 /* 37796 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14572 /* 37798 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14573 /* 37800 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
14574 /* 37803 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14575 /* 37807 */ GIR_RootConstrainSelectedInstOperands,
14576 /* 37808 */ // GIR_Coverage, 2186,
14577 /* 37808 */ GIR_EraseRootFromParent_Done,
14578 /* 37809 */ // Label 1125: @37809
14579 /* 37809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1126*/ GIMT_Encode4(37852), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2188 //
14580 /* 37816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
14581 /* 37821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14582 /* 37824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14583 /* 37827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14584 /* 37830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14585 /* 37834 */ // (intrinsic_w_chain:{ *:[i32] } 8024:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14586 /* 37834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
14587 /* 37837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14588 /* 37839 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14589 /* 37841 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14590 /* 37843 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14591 /* 37846 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14592 /* 37850 */ GIR_RootConstrainSelectedInstOperands,
14593 /* 37851 */ // GIR_Coverage, 2188,
14594 /* 37851 */ GIR_EraseRootFromParent_Done,
14595 /* 37852 */ // Label 1126: @37852
14596 /* 37852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1127*/ GIMT_Encode4(37897), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 550 //
14597 /* 37859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
14598 /* 37864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
14599 /* 37867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14600 /* 37870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14601 /* 37874 */ // MIs[0] ptr
14602 /* 37874 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14603 /* 37878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14604 /* 37882 */ // (intrinsic_w_chain:{ *:[v2i64] } 8374:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14605 /* 37882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
14606 /* 37885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14607 /* 37887 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14608 /* 37889 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14609 /* 37891 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14610 /* 37895 */ GIR_RootConstrainSelectedInstOperands,
14611 /* 37896 */ // GIR_Coverage, 550,
14612 /* 37896 */ GIR_EraseRootFromParent_Done,
14613 /* 37897 */ // Label 1127: @37897
14614 /* 37897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1128*/ GIMT_Encode4(37942), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 551 //
14615 /* 37904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
14616 /* 37909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
14617 /* 37912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14618 /* 37915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14619 /* 37919 */ // MIs[0] ptr
14620 /* 37919 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14621 /* 37923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14622 /* 37927 */ // (intrinsic_w_chain:{ *:[v4i32] } 8375:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14623 /* 37927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
14624 /* 37930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14625 /* 37932 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14626 /* 37934 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14627 /* 37936 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14628 /* 37940 */ GIR_RootConstrainSelectedInstOperands,
14629 /* 37941 */ // GIR_Coverage, 551,
14630 /* 37941 */ GIR_EraseRootFromParent_Done,
14631 /* 37942 */ // Label 1128: @37942
14632 /* 37942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1129*/ GIMT_Encode4(37983), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 497 //
14633 /* 37949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14634 /* 37954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14635 /* 37957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14636 /* 37960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14637 /* 37964 */ // MIs[0] base
14638 /* 37964 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14639 /* 37968 */ // (intrinsic_w_chain:{ *:[i32] } 8378:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14640 /* 37968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
14641 /* 37971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14642 /* 37973 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14643 /* 37975 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14644 /* 37977 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14645 /* 37981 */ GIR_RootConstrainSelectedInstOperands,
14646 /* 37982 */ // GIR_Coverage, 497,
14647 /* 37982 */ GIR_EraseRootFromParent_Done,
14648 /* 37983 */ // Label 1129: @37983
14649 /* 37983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1130*/ GIMT_Encode4(38024), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 498 //
14650 /* 37990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14651 /* 37995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14652 /* 37998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14653 /* 38001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14654 /* 38005 */ // MIs[0] base
14655 /* 38005 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14656 /* 38009 */ // (intrinsic_w_chain:{ *:[i32] } 8376:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14657 /* 38009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
14658 /* 38012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14659 /* 38014 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14660 /* 38016 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14661 /* 38018 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14662 /* 38022 */ GIR_RootConstrainSelectedInstOperands,
14663 /* 38023 */ // GIR_Coverage, 498,
14664 /* 38023 */ GIR_EraseRootFromParent_Done,
14665 /* 38024 */ // Label 1130: @38024
14666 /* 38024 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(38093),
14667 /* 38029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
14668 /* 38034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14669 /* 38037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14670 /* 38040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14671 /* 38044 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14672 /* 38048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1132*/ GIMT_Encode4(38070), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 499 //
14673 /* 38055 */ // (intrinsic_w_chain:{ *:[i32] } 8365:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14674 /* 38055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
14675 /* 38058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14676 /* 38060 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14677 /* 38062 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14678 /* 38064 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14679 /* 38068 */ GIR_RootConstrainSelectedInstOperands,
14680 /* 38069 */ // GIR_Coverage, 499,
14681 /* 38069 */ GIR_EraseRootFromParent_Done,
14682 /* 38070 */ // Label 1132: @38070
14683 /* 38070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1133*/ GIMT_Encode4(38092), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1355 //
14684 /* 38077 */ // (intrinsic_w_chain:{ *:[i32] } 8365:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14685 /* 38077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
14686 /* 38080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14687 /* 38082 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14688 /* 38084 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14689 /* 38086 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14690 /* 38090 */ GIR_RootConstrainSelectedInstOperands,
14691 /* 38091 */ // GIR_Coverage, 1355,
14692 /* 38091 */ GIR_EraseRootFromParent_Done,
14693 /* 38092 */ // Label 1133: @38092
14694 /* 38092 */ GIM_Reject,
14695 /* 38093 */ // Label 1131: @38093
14696 /* 38093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1134*/ GIMT_Encode4(38134), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1356 //
14697 /* 38100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14698 /* 38105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14699 /* 38108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14700 /* 38111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14701 /* 38115 */ // MIs[0] base
14702 /* 38115 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14703 /* 38119 */ // (intrinsic_w_chain:{ *:[i32] } 8376:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14704 /* 38119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
14705 /* 38122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14706 /* 38124 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14707 /* 38126 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14708 /* 38128 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14709 /* 38132 */ GIR_RootConstrainSelectedInstOperands,
14710 /* 38133 */ // GIR_Coverage, 1356,
14711 /* 38133 */ GIR_EraseRootFromParent_Done,
14712 /* 38134 */ // Label 1134: @38134
14713 /* 38134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1135*/ GIMT_Encode4(38175), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1357 //
14714 /* 38141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14715 /* 38146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14716 /* 38149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14717 /* 38152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14718 /* 38156 */ // MIs[0] base
14719 /* 38156 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14720 /* 38160 */ // (intrinsic_w_chain:{ *:[i32] } 8378:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14721 /* 38160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
14722 /* 38163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14723 /* 38165 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14724 /* 38167 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14725 /* 38169 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14726 /* 38173 */ GIR_RootConstrainSelectedInstOperands,
14727 /* 38174 */ // GIR_Coverage, 1357,
14728 /* 38174 */ GIR_EraseRootFromParent_Done,
14729 /* 38175 */ // Label 1135: @38175
14730 /* 38175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1136*/ GIMT_Encode4(38220), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 552 //
14731 /* 38182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
14732 /* 38187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14733 /* 38190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14734 /* 38193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14735 /* 38197 */ // MIs[0] ptr
14736 /* 38197 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14737 /* 38201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14738 /* 38205 */ // (intrinsic_void 8608:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14739 /* 38205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
14740 /* 38208 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14741 /* 38210 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14742 /* 38212 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14743 /* 38214 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14744 /* 38218 */ GIR_RootConstrainSelectedInstOperands,
14745 /* 38219 */ // GIR_Coverage, 552,
14746 /* 38219 */ GIR_EraseRootFromParent_Done,
14747 /* 38220 */ // Label 1136: @38220
14748 /* 38220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1137*/ GIMT_Encode4(38265), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 553 //
14749 /* 38227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
14750 /* 38232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14751 /* 38235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14752 /* 38238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14753 /* 38242 */ // MIs[0] ptr
14754 /* 38242 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14755 /* 38246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14756 /* 38250 */ // (intrinsic_void 8609:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14757 /* 38250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
14758 /* 38253 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14759 /* 38255 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14760 /* 38257 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14761 /* 38259 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14762 /* 38263 */ GIR_RootConstrainSelectedInstOperands,
14763 /* 38264 */ // GIR_Coverage, 553,
14764 /* 38264 */ GIR_EraseRootFromParent_Done,
14765 /* 38265 */ // Label 1137: @38265
14766 /* 38265 */ GIM_Reject,
14767 /* 38266 */ // Label 1055: @38266
14768 /* 38266 */ GIM_Reject,
14769 /* 38267 */ // Label 32: @38267
14770 /* 38267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1138*/ GIMT_Encode4(38331), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1774 //
14771 /* 38274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14772 /* 38277 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14773 /* 38280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14774 /* 38284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14775 /* 38288 */ // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
14776 /* 38288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14777 /* 38291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14778 /* 38295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14779 /* 38300 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14780 /* 38302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14781 /* 38305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14782 /* 38307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14783 /* 38310 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14784 /* 38312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14785 /* 38315 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14786 /* 38320 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14787 /* 38325 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14788 /* 38330 */ // GIR_Coverage, 1774,
14789 /* 38330 */ GIR_EraseRootFromParent_Done,
14790 /* 38331 */ // Label 1138: @38331
14791 /* 38331 */ GIM_Reject,
14792 /* 38332 */ // Label 33: @38332
14793 /* 38332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1139*/ GIMT_Encode4(38394), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1767 //
14794 /* 38339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14795 /* 38342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14796 /* 38345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14797 /* 38349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14798 /* 38353 */ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
14799 /* 38353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14800 /* 38356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14801 /* 38360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14802 /* 38365 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
14803 /* 38371 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
14804 /* 38376 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14805 /* 38381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
14806 /* 38384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14807 /* 38386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14808 /* 38389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14809 /* 38392 */ GIR_RootConstrainSelectedInstOperands,
14810 /* 38393 */ // GIR_Coverage, 1767,
14811 /* 38393 */ GIR_EraseRootFromParent_Done,
14812 /* 38394 */ // Label 1139: @38394
14813 /* 38394 */ GIM_Reject,
14814 /* 38395 */ // Label 34: @38395
14815 /* 38395 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(38453),
14816 /* 38400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14817 /* 38403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1141*/ GIMT_Encode4(38428), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2424 //
14818 /* 38410 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
14819 /* 38414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
14820 /* 38418 */ // MIs[0] Operand 1
14821 /* 38418 */ // No operand predicates
14822 /* 38418 */ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
14823 /* 38418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
14824 /* 38421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14825 /* 38423 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14826 /* 38426 */ GIR_RootConstrainSelectedInstOperands,
14827 /* 38427 */ // GIR_Coverage, 2424,
14828 /* 38427 */ GIR_EraseRootFromParent_Done,
14829 /* 38428 */ // Label 1141: @38428
14830 /* 38428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1142*/ GIMT_Encode4(38452), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2100 //
14831 /* 38435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14832 /* 38439 */ // MIs[0] Operand 1
14833 /* 38439 */ // No operand predicates
14834 /* 38439 */ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
14835 /* 38439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
14836 /* 38442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
14837 /* 38444 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14838 /* 38447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
14839 /* 38450 */ GIR_RootConstrainSelectedInstOperands,
14840 /* 38451 */ // GIR_Coverage, 2100,
14841 /* 38451 */ GIR_EraseRootFromParent_Done,
14842 /* 38452 */ // Label 1142: @38452
14843 /* 38452 */ GIM_Reject,
14844 /* 38453 */ // Label 1140: @38453
14845 /* 38453 */ GIM_Reject,
14846 /* 38454 */ // Label 35: @38454
14847 /* 38454 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(39910),
14848 /* 38459 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14849 /* 38462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14850 /* 38465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14851 /* 38469 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(38574), // Rule ID 1834 //
14852 /* 38474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14853 /* 38478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14854 /* 38482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14855 /* 38486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14856 /* 38490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14857 /* 38495 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14858 /* 38499 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14859 /* 38503 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14860 /* 38507 */ // MIs[2] Operand 1
14861 /* 38507 */ // No operand predicates
14862 /* 38507 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14863 /* 38509 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14864 /* 38509 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14865 /* 38512 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
14866 /* 38516 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14867 /* 38521 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14868 /* 38525 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14869 /* 38528 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14870 /* 38530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14871 /* 38533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14872 /* 38537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14873 /* 38542 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14874 /* 38544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14875 /* 38547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14876 /* 38549 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14877 /* 38552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14878 /* 38555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14879 /* 38558 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14880 /* 38563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14881 /* 38568 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14882 /* 38573 */ // GIR_Coverage, 1834,
14883 /* 38573 */ GIR_EraseRootFromParent_Done,
14884 /* 38574 */ // Label 1144: @38574
14885 /* 38574 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(38679), // Rule ID 1830 //
14886 /* 38579 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14887 /* 38583 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
14888 /* 38587 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14889 /* 38591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14890 /* 38595 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14891 /* 38600 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14892 /* 38604 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14893 /* 38608 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14894 /* 38612 */ // MIs[2] Operand 1
14895 /* 38612 */ // No operand predicates
14896 /* 38612 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14897 /* 38614 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14898 /* 38614 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14899 /* 38617 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
14900 /* 38621 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14901 /* 38626 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14902 /* 38630 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14903 /* 38633 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14904 /* 38635 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14905 /* 38638 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14906 /* 38642 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14907 /* 38647 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14908 /* 38649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14909 /* 38652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14910 /* 38654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14911 /* 38657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14912 /* 38660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14913 /* 38663 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14914 /* 38668 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14915 /* 38673 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14916 /* 38678 */ // GIR_Coverage, 1830,
14917 /* 38678 */ GIR_EraseRootFromParent_Done,
14918 /* 38679 */ // Label 1145: @38679
14919 /* 38679 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(38784), // Rule ID 1826 //
14920 /* 38684 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14921 /* 38688 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
14922 /* 38692 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14923 /* 38696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14924 /* 38700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14925 /* 38705 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14926 /* 38709 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14927 /* 38713 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14928 /* 38717 */ // MIs[2] Operand 1
14929 /* 38717 */ // No operand predicates
14930 /* 38717 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14931 /* 38719 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14932 /* 38719 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14933 /* 38722 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
14934 /* 38726 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14935 /* 38731 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14936 /* 38735 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14937 /* 38738 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14938 /* 38740 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14939 /* 38743 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14940 /* 38747 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14941 /* 38752 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14942 /* 38754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14943 /* 38757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14944 /* 38759 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14945 /* 38762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14946 /* 38765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14947 /* 38768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14948 /* 38773 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14949 /* 38778 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14950 /* 38783 */ // GIR_Coverage, 1826,
14951 /* 38783 */ GIR_EraseRootFromParent_Done,
14952 /* 38784 */ // Label 1146: @38784
14953 /* 38784 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(38883), // Rule ID 1816 //
14954 /* 38789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14955 /* 38793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
14956 /* 38797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14957 /* 38801 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14958 /* 38805 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14959 /* 38810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14960 /* 38815 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14961 /* 38817 */ // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14962 /* 38817 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14963 /* 38820 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
14964 /* 38824 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14965 /* 38829 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14966 /* 38833 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14967 /* 38837 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14968 /* 38839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14969 /* 38842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14970 /* 38846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14971 /* 38851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14972 /* 38853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14973 /* 38856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14974 /* 38858 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14975 /* 38861 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14976 /* 38864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14977 /* 38867 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14978 /* 38872 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14979 /* 38877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14980 /* 38882 */ // GIR_Coverage, 1816,
14981 /* 38882 */ GIR_EraseRootFromParent_Done,
14982 /* 38883 */ // Label 1147: @38883
14983 /* 38883 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(38982), // Rule ID 1836 //
14984 /* 38888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14985 /* 38892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14986 /* 38896 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14987 /* 38900 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14988 /* 38904 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14989 /* 38909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14990 /* 38914 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14991 /* 38916 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14992 /* 38916 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14993 /* 38919 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
14994 /* 38923 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14995 /* 38928 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14996 /* 38932 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14997 /* 38936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14998 /* 38938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14999 /* 38941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15000 /* 38945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15001 /* 38950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15002 /* 38952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15003 /* 38955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15004 /* 38957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15005 /* 38960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15006 /* 38963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15007 /* 38966 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15008 /* 38971 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15009 /* 38976 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15010 /* 38981 */ // GIR_Coverage, 1836,
15011 /* 38981 */ GIR_EraseRootFromParent_Done,
15012 /* 38982 */ // Label 1148: @38982
15013 /* 38982 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(39081), // Rule ID 1832 //
15014 /* 38987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15015 /* 38991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15016 /* 38995 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15017 /* 38999 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15018 /* 39003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15019 /* 39008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15020 /* 39013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15021 /* 39015 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15022 /* 39015 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15023 /* 39018 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
15024 /* 39022 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15025 /* 39027 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15026 /* 39031 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15027 /* 39035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15028 /* 39037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15029 /* 39040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15030 /* 39044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15031 /* 39049 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15032 /* 39051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15033 /* 39054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15034 /* 39056 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15035 /* 39059 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15036 /* 39062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15037 /* 39065 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15038 /* 39070 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15039 /* 39075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15040 /* 39080 */ // GIR_Coverage, 1832,
15041 /* 39080 */ GIR_EraseRootFromParent_Done,
15042 /* 39081 */ // Label 1149: @39081
15043 /* 39081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1150*/ GIMT_Encode4(39188), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 1820 //
15044 /* 39088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15045 /* 39092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15046 /* 39096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15047 /* 39100 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15048 /* 39104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15049 /* 39109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15050 /* 39114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15051 /* 39116 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15052 /* 39116 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15053 /* 39119 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
15054 /* 39123 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15055 /* 39128 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15056 /* 39132 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15057 /* 39136 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
15058 /* 39139 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
15059 /* 39142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15060 /* 39144 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15061 /* 39147 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15062 /* 39151 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15063 /* 39156 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15064 /* 39158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15065 /* 39161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15066 /* 39163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15067 /* 39166 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15068 /* 39169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15069 /* 39172 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15070 /* 39177 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15071 /* 39182 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15072 /* 39187 */ // GIR_Coverage, 1820,
15073 /* 39187 */ GIR_EraseRootFromParent_Done,
15074 /* 39188 */ // Label 1150: @39188
15075 /* 39188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1151*/ GIMT_Encode4(39289), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2051 //
15076 /* 39195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15077 /* 39199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15078 /* 39203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15079 /* 39207 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15080 /* 39211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15081 /* 39216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15082 /* 39221 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15083 /* 39223 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15084 /* 39223 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15085 /* 39226 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
15086 /* 39230 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15087 /* 39235 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15088 /* 39239 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15089 /* 39243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15090 /* 39245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15091 /* 39248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15092 /* 39252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15093 /* 39257 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15094 /* 39259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15095 /* 39262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15096 /* 39264 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15097 /* 39267 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15098 /* 39270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15099 /* 39273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15100 /* 39278 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15101 /* 39283 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15102 /* 39288 */ // GIR_Coverage, 2051,
15103 /* 39288 */ GIR_EraseRootFromParent_Done,
15104 /* 39289 */ // Label 1151: @39289
15105 /* 39289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1152*/ GIMT_Encode4(39390), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2052 //
15106 /* 39296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15107 /* 39300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
15108 /* 39304 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15109 /* 39308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15110 /* 39312 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15111 /* 39317 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15112 /* 39322 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15113 /* 39324 */ // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15114 /* 39324 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15115 /* 39327 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
15116 /* 39331 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15117 /* 39336 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15118 /* 39340 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15119 /* 39344 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15120 /* 39346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15121 /* 39349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15122 /* 39353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15123 /* 39358 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15124 /* 39360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15125 /* 39363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15126 /* 39365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15127 /* 39368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15128 /* 39371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15129 /* 39374 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15130 /* 39379 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15131 /* 39384 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15132 /* 39389 */ // GIR_Coverage, 2052,
15133 /* 39389 */ GIR_EraseRootFromParent_Done,
15134 /* 39390 */ // Label 1152: @39390
15135 /* 39390 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(39489), // Rule ID 1828 //
15136 /* 39395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15137 /* 39399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15138 /* 39403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15139 /* 39407 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15140 /* 39411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15141 /* 39416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15142 /* 39421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15143 /* 39423 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15144 /* 39423 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15145 /* 39426 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15146 /* 39430 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15147 /* 39435 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15148 /* 39439 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15149 /* 39443 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15150 /* 39445 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15151 /* 39448 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15152 /* 39452 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15153 /* 39457 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15154 /* 39459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15155 /* 39462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15156 /* 39464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15157 /* 39467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15158 /* 39470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15159 /* 39473 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15160 /* 39478 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15161 /* 39483 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15162 /* 39488 */ // GIR_Coverage, 1828,
15163 /* 39488 */ GIR_EraseRootFromParent_Done,
15164 /* 39489 */ // Label 1153: @39489
15165 /* 39489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(39590), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2054 //
15166 /* 39496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15167 /* 39500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
15168 /* 39504 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15169 /* 39508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15170 /* 39512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15171 /* 39517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15172 /* 39522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15173 /* 39524 */ // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15174 /* 39524 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15175 /* 39527 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
15176 /* 39531 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15177 /* 39536 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15178 /* 39540 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15179 /* 39544 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15180 /* 39546 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15181 /* 39549 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15182 /* 39553 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15183 /* 39558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15184 /* 39560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15185 /* 39563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15186 /* 39565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15187 /* 39568 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15188 /* 39571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15189 /* 39574 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15190 /* 39579 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15191 /* 39584 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15192 /* 39589 */ // GIR_Coverage, 2054,
15193 /* 39589 */ GIR_EraseRootFromParent_Done,
15194 /* 39590 */ // Label 1154: @39590
15195 /* 39590 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(39689), // Rule ID 1818 //
15196 /* 39595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15197 /* 39599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
15198 /* 39603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15199 /* 39607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15200 /* 39611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15201 /* 39616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15202 /* 39621 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15203 /* 39623 */ // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15204 /* 39623 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15205 /* 39626 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
15206 /* 39630 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15207 /* 39635 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15208 /* 39639 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15209 /* 39643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15210 /* 39645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15211 /* 39648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15212 /* 39652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15213 /* 39657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15214 /* 39659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15215 /* 39662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15216 /* 39664 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15217 /* 39667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15218 /* 39670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15219 /* 39673 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15220 /* 39678 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15221 /* 39683 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15222 /* 39688 */ // GIR_Coverage, 1818,
15223 /* 39688 */ GIR_EraseRootFromParent_Done,
15224 /* 39689 */ // Label 1155: @39689
15225 /* 39689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1156*/ GIMT_Encode4(39790), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2053 //
15226 /* 39696 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15227 /* 39700 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
15228 /* 39704 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15229 /* 39708 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15230 /* 39712 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15231 /* 39717 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15232 /* 39722 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15233 /* 39724 */ // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15234 /* 39724 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15235 /* 39727 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
15236 /* 39731 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15237 /* 39736 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15238 /* 39740 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15239 /* 39744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15240 /* 39746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15241 /* 39749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15242 /* 39753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15243 /* 39758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15244 /* 39760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15245 /* 39763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15246 /* 39765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15247 /* 39768 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15248 /* 39771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15249 /* 39774 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15250 /* 39779 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15251 /* 39784 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15252 /* 39789 */ // GIR_Coverage, 2053,
15253 /* 39789 */ GIR_EraseRootFromParent_Done,
15254 /* 39790 */ // Label 1156: @39790
15255 /* 39790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1157*/ GIMT_Encode4(39891), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2055 //
15256 /* 39797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15257 /* 39801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
15258 /* 39805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15259 /* 39809 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15260 /* 39813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15261 /* 39818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15262 /* 39823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15263 /* 39825 */ // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15264 /* 39825 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15265 /* 39828 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
15266 /* 39832 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15267 /* 39837 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15268 /* 39841 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15269 /* 39845 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15270 /* 39847 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15271 /* 39850 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15272 /* 39854 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15273 /* 39859 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15274 /* 39861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15275 /* 39864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15276 /* 39866 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15277 /* 39869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15278 /* 39872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15279 /* 39875 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15280 /* 39880 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15281 /* 39885 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15282 /* 39890 */ // GIR_Coverage, 2055,
15283 /* 39890 */ GIR_EraseRootFromParent_Done,
15284 /* 39891 */ // Label 1157: @39891
15285 /* 39891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1158*/ GIMT_Encode4(39909), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1777 //
15286 /* 39898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15287 /* 39902 */ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
15288 /* 39902 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
15289 /* 39907 */ GIR_RootConstrainSelectedInstOperands,
15290 /* 39908 */ // GIR_Coverage, 1777,
15291 /* 39908 */ GIR_Done,
15292 /* 39909 */ // Label 1158: @39909
15293 /* 39909 */ GIM_Reject,
15294 /* 39910 */ // Label 1143: @39910
15295 /* 39910 */ GIM_Reject,
15296 /* 39911 */ // Label 36: @39911
15297 /* 39911 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1161*/ GIMT_Encode4(40229),
15298 /* 39922 */ /*GILLT_s32*//*Label 1159*/ GIMT_Encode4(39930),
15299 /* 39926 */ /*GILLT_s64*//*Label 1160*/ GIMT_Encode4(40130),
15300 /* 39930 */ // Label 1159: @39930
15301 /* 39930 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(40129),
15302 /* 39935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15303 /* 39938 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(40060),
15304 /* 39943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15305 /* 39947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15306 /* 39951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1164*/ GIMT_Encode4(39978), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 126 //
15307 /* 39958 */ // MIs[0] Operand 2
15308 /* 39958 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15309 /* 39969 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15310 /* 39969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
15311 /* 39972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15312 /* 39974 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15313 /* 39976 */ GIR_RootConstrainSelectedInstOperands,
15314 /* 39977 */ // GIR_Coverage, 126,
15315 /* 39977 */ GIR_EraseRootFromParent_Done,
15316 /* 39978 */ // Label 1164: @39978
15317 /* 39978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1165*/ GIMT_Encode4(40005), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 127 //
15318 /* 39985 */ // MIs[0] Operand 2
15319 /* 39985 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15320 /* 39996 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15321 /* 39996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
15322 /* 39999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15323 /* 40001 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15324 /* 40003 */ GIR_RootConstrainSelectedInstOperands,
15325 /* 40004 */ // GIR_Coverage, 127,
15326 /* 40004 */ GIR_EraseRootFromParent_Done,
15327 /* 40005 */ // Label 1165: @40005
15328 /* 40005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40032), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1181 //
15329 /* 40012 */ // MIs[0] Operand 2
15330 /* 40012 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15331 /* 40023 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15332 /* 40023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
15333 /* 40026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15334 /* 40028 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15335 /* 40030 */ GIR_RootConstrainSelectedInstOperands,
15336 /* 40031 */ // GIR_Coverage, 1181,
15337 /* 40031 */ GIR_EraseRootFromParent_Done,
15338 /* 40032 */ // Label 1166: @40032
15339 /* 40032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40059), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1182 //
15340 /* 40039 */ // MIs[0] Operand 2
15341 /* 40039 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15342 /* 40050 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15343 /* 40050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
15344 /* 40053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15345 /* 40055 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15346 /* 40057 */ GIR_RootConstrainSelectedInstOperands,
15347 /* 40058 */ // GIR_Coverage, 1182,
15348 /* 40058 */ GIR_EraseRootFromParent_Done,
15349 /* 40059 */ // Label 1167: @40059
15350 /* 40059 */ GIM_Reject,
15351 /* 40060 */ // Label 1163: @40060
15352 /* 40060 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40128),
15353 /* 40065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15354 /* 40069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15355 /* 40073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40100), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2158 //
15356 /* 40080 */ // MIs[0] Operand 2
15357 /* 40080 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15358 /* 40091 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) => (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15359 /* 40091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
15360 /* 40094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15361 /* 40096 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15362 /* 40098 */ GIR_RootConstrainSelectedInstOperands,
15363 /* 40099 */ // GIR_Coverage, 2158,
15364 /* 40099 */ GIR_EraseRootFromParent_Done,
15365 /* 40100 */ // Label 1169: @40100
15366 /* 40100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1170*/ GIMT_Encode4(40127), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2159 //
15367 /* 40107 */ // MIs[0] Operand 2
15368 /* 40107 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15369 /* 40118 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) => (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15370 /* 40118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
15371 /* 40121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15372 /* 40123 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15373 /* 40125 */ GIR_RootConstrainSelectedInstOperands,
15374 /* 40126 */ // GIR_Coverage, 2159,
15375 /* 40126 */ GIR_EraseRootFromParent_Done,
15376 /* 40127 */ // Label 1170: @40127
15377 /* 40127 */ GIM_Reject,
15378 /* 40128 */ // Label 1168: @40128
15379 /* 40128 */ GIM_Reject,
15380 /* 40129 */ // Label 1162: @40129
15381 /* 40129 */ GIM_Reject,
15382 /* 40130 */ // Label 1160: @40130
15383 /* 40130 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(40228),
15384 /* 40135 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15385 /* 40138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15386 /* 40142 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15387 /* 40146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1172*/ GIMT_Encode4(40173), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 335 //
15388 /* 40153 */ // MIs[0] Operand 2
15389 /* 40153 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15390 /* 40164 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) => (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15391 /* 40164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
15392 /* 40167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15393 /* 40169 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15394 /* 40171 */ GIR_RootConstrainSelectedInstOperands,
15395 /* 40172 */ // GIR_Coverage, 335,
15396 /* 40172 */ GIR_EraseRootFromParent_Done,
15397 /* 40173 */ // Label 1172: @40173
15398 /* 40173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1173*/ GIMT_Encode4(40200), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 336 //
15399 /* 40180 */ // MIs[0] Operand 2
15400 /* 40180 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15401 /* 40191 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) => (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15402 /* 40191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
15403 /* 40194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15404 /* 40196 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15405 /* 40198 */ GIR_RootConstrainSelectedInstOperands,
15406 /* 40199 */ // GIR_Coverage, 336,
15407 /* 40199 */ GIR_EraseRootFromParent_Done,
15408 /* 40200 */ // Label 1173: @40200
15409 /* 40200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1174*/ GIMT_Encode4(40227), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1780 //
15410 /* 40207 */ // MIs[0] Operand 2
15411 /* 40207 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
15412 /* 40218 */ // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) => (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
15413 /* 40218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
15414 /* 40221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15415 /* 40223 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15416 /* 40225 */ GIR_RootConstrainSelectedInstOperands,
15417 /* 40226 */ // GIR_Coverage, 1780,
15418 /* 40226 */ GIR_EraseRootFromParent_Done,
15419 /* 40227 */ // Label 1174: @40227
15420 /* 40227 */ GIM_Reject,
15421 /* 40228 */ // Label 1171: @40228
15422 /* 40228 */ GIM_Reject,
15423 /* 40229 */ // Label 1161: @40229
15424 /* 40229 */ GIM_Reject,
15425 /* 40230 */ // Label 37: @40230
15426 /* 40230 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(40426),
15427 /* 40235 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15428 /* 40238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15429 /* 40241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15430 /* 40245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1176*/ GIMT_Encode4(40300), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 355 //
15431 /* 40252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15432 /* 40256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15433 /* 40260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15434 /* 40264 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15435 /* 40268 */ // MIs[1] Operand 1
15436 /* 40268 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
15437 /* 40273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15438 /* 40278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15439 /* 40283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15440 /* 40285 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15441 /* 40285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
15442 /* 40288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15443 /* 40290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15444 /* 40294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15445 /* 40298 */ GIR_RootConstrainSelectedInstOperands,
15446 /* 40299 */ // GIR_Coverage, 355,
15447 /* 40299 */ GIR_EraseRootFromParent_Done,
15448 /* 40300 */ // Label 1176: @40300
15449 /* 40300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1177*/ GIMT_Encode4(40355), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 357 //
15450 /* 40307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15451 /* 40311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15452 /* 40315 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15453 /* 40319 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15454 /* 40323 */ // MIs[1] Operand 1
15455 /* 40323 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15456 /* 40328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15457 /* 40333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15458 /* 40338 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15459 /* 40340 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15460 /* 40340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
15461 /* 40343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15462 /* 40345 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15463 /* 40349 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15464 /* 40353 */ GIR_RootConstrainSelectedInstOperands,
15465 /* 40354 */ // GIR_Coverage, 357,
15466 /* 40354 */ GIR_EraseRootFromParent_Done,
15467 /* 40355 */ // Label 1177: @40355
15468 /* 40355 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(40425),
15469 /* 40360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15470 /* 40364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1179*/ GIMT_Encode4(40402), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1775 //
15471 /* 40371 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
15472 /* 40371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15473 /* 40374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
15474 /* 40378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15475 /* 40383 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
15476 /* 40387 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15477 /* 40389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
15478 /* 40392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15479 /* 40394 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15480 /* 40397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15481 /* 40400 */ GIR_RootConstrainSelectedInstOperands,
15482 /* 40401 */ // GIR_Coverage, 1775,
15483 /* 40401 */ GIR_EraseRootFromParent_Done,
15484 /* 40402 */ // Label 1179: @40402
15485 /* 40402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1180*/ GIMT_Encode4(40424), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1778 //
15486 /* 40409 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
15487 /* 40409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
15488 /* 40412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
15489 /* 40414 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15490 /* 40416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15491 /* 40419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15492 /* 40422 */ GIR_RootConstrainSelectedInstOperands,
15493 /* 40423 */ // GIR_Coverage, 1778,
15494 /* 40423 */ GIR_EraseRootFromParent_Done,
15495 /* 40424 */ // Label 1180: @40424
15496 /* 40424 */ GIM_Reject,
15497 /* 40425 */ // Label 1178: @40425
15498 /* 40425 */ GIM_Reject,
15499 /* 40426 */ // Label 1175: @40426
15500 /* 40426 */ GIM_Reject,
15501 /* 40427 */ // Label 38: @40427
15502 /* 40427 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1187*/ GIMT_Encode4(42201),
15503 /* 40438 */ /*GILLT_s32*//*Label 1181*/ GIMT_Encode4(40470),
15504 /* 40442 */ /*GILLT_s64*//*Label 1182*/ GIMT_Encode4(40723), GIMT_Encode4(0),
15505 /* 40450 */ /*GILLT_v16s8*//*Label 1183*/ GIMT_Encode4(40861), GIMT_Encode4(0),
15506 /* 40458 */ /*GILLT_v8s16*//*Label 1184*/ GIMT_Encode4(41510),
15507 /* 40462 */ /*GILLT_v4s32*//*Label 1185*/ GIMT_Encode4(41903),
15508 /* 40466 */ /*GILLT_v2s64*//*Label 1186*/ GIMT_Encode4(42168),
15509 /* 40470 */ // Label 1181: @40470
15510 /* 40470 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(40722),
15511 /* 40475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15512 /* 40478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15513 /* 40481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1189*/ GIMT_Encode4(40522), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 55 //
15514 /* 40488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15515 /* 40492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15516 /* 40496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15517 /* 40500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15518 /* 40504 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15519 /* 40508 */ // MIs[1] Operand 1
15520 /* 40508 */ // No operand predicates
15521 /* 40508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15522 /* 40510 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15523 /* 40510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
15524 /* 40513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15525 /* 40515 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15526 /* 40517 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15527 /* 40520 */ GIR_RootConstrainSelectedInstOperands,
15528 /* 40521 */ // GIR_Coverage, 55,
15529 /* 40521 */ GIR_EraseRootFromParent_Done,
15530 /* 40522 */ // Label 1189: @40522
15531 /* 40522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1190*/ GIMT_Encode4(40563), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2082 //
15532 /* 40529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15533 /* 40533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15534 /* 40537 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15535 /* 40541 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15536 /* 40545 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15537 /* 40549 */ // MIs[1] Operand 1
15538 /* 40549 */ // No operand predicates
15539 /* 40549 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15540 /* 40551 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15541 /* 40551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
15542 /* 40554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15543 /* 40556 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
15544 /* 40558 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15545 /* 40561 */ GIR_RootConstrainSelectedInstOperands,
15546 /* 40562 */ // GIR_Coverage, 2082,
15547 /* 40562 */ GIR_EraseRootFromParent_Done,
15548 /* 40563 */ // Label 1190: @40563
15549 /* 40563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1191*/ GIMT_Encode4(40604), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2436 //
15550 /* 40570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15551 /* 40574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15552 /* 40578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15553 /* 40582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15554 /* 40586 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
15555 /* 40590 */ // MIs[1] Operand 1
15556 /* 40590 */ // No operand predicates
15557 /* 40590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15558 /* 40592 */ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
15559 /* 40592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
15560 /* 40595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15561 /* 40597 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15562 /* 40599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15563 /* 40602 */ GIR_RootConstrainSelectedInstOperands,
15564 /* 40603 */ // GIR_Coverage, 2436,
15565 /* 40603 */ GIR_EraseRootFromParent_Done,
15566 /* 40604 */ // Label 1191: @40604
15567 /* 40604 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(40669),
15568 /* 40609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15569 /* 40613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15570 /* 40617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1193*/ GIMT_Encode4(40650), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2437 //
15571 /* 40624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15572 /* 40628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15573 /* 40632 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15574 /* 40636 */ // MIs[1] Operand 1
15575 /* 40636 */ // No operand predicates
15576 /* 40636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15577 /* 40638 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15578 /* 40638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
15579 /* 40641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15580 /* 40643 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15581 /* 40645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15582 /* 40648 */ GIR_RootConstrainSelectedInstOperands,
15583 /* 40649 */ // GIR_Coverage, 2437,
15584 /* 40649 */ GIR_EraseRootFromParent_Done,
15585 /* 40650 */ // Label 1193: @40650
15586 /* 40650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1194*/ GIMT_Encode4(40668), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 61 //
15587 /* 40657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15588 /* 40661 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15589 /* 40661 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15590 /* 40666 */ GIR_RootConstrainSelectedInstOperands,
15591 /* 40667 */ // GIR_Coverage, 61,
15592 /* 40667 */ GIR_Done,
15593 /* 40668 */ // Label 1194: @40668
15594 /* 40668 */ GIM_Reject,
15595 /* 40669 */ // Label 1192: @40669
15596 /* 40669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1195*/ GIMT_Encode4(40695), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2085 //
15597 /* 40676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15598 /* 40680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15599 /* 40684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15600 /* 40688 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
15601 /* 40688 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
15602 /* 40693 */ GIR_RootConstrainSelectedInstOperands,
15603 /* 40694 */ // GIR_Coverage, 2085,
15604 /* 40694 */ GIR_Done,
15605 /* 40695 */ // Label 1195: @40695
15606 /* 40695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1196*/ GIMT_Encode4(40721), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2438 //
15607 /* 40702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15608 /* 40706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15609 /* 40710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15610 /* 40714 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
15611 /* 40714 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
15612 /* 40719 */ GIR_RootConstrainSelectedInstOperands,
15613 /* 40720 */ // GIR_Coverage, 2438,
15614 /* 40720 */ GIR_Done,
15615 /* 40721 */ // Label 1196: @40721
15616 /* 40721 */ GIM_Reject,
15617 /* 40722 */ // Label 1188: @40722
15618 /* 40722 */ GIM_Reject,
15619 /* 40723 */ // Label 1182: @40723
15620 /* 40723 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(40860),
15621 /* 40728 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15622 /* 40731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15623 /* 40734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15624 /* 40738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15625 /* 40742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1198*/ GIMT_Encode4(40775), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 265 //
15626 /* 40749 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15627 /* 40753 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15628 /* 40757 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15629 /* 40761 */ // MIs[1] Operand 1
15630 /* 40761 */ // No operand predicates
15631 /* 40761 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15632 /* 40763 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15633 /* 40763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
15634 /* 40766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15635 /* 40768 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15636 /* 40770 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15637 /* 40773 */ GIR_RootConstrainSelectedInstOperands,
15638 /* 40774 */ // GIR_Coverage, 265,
15639 /* 40774 */ GIR_EraseRootFromParent_Done,
15640 /* 40775 */ // Label 1198: @40775
15641 /* 40775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1199*/ GIMT_Encode4(40841), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1768 //
15642 /* 40782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15643 /* 40786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
15644 /* 40790 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15645 /* 40794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15646 /* 40799 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15647 /* 40801 */ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15648 /* 40801 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15649 /* 40804 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15650 /* 40808 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15651 /* 40813 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
15652 /* 40819 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15653 /* 40824 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15654 /* 40829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15655 /* 40832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15656 /* 40834 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15657 /* 40836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15658 /* 40839 */ GIR_RootConstrainSelectedInstOperands,
15659 /* 40840 */ // GIR_Coverage, 1768,
15660 /* 40840 */ GIR_EraseRootFromParent_Done,
15661 /* 40841 */ // Label 1199: @40841
15662 /* 40841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1200*/ GIMT_Encode4(40859), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 271 //
15663 /* 40848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15664 /* 40852 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15665 /* 40852 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15666 /* 40857 */ GIR_RootConstrainSelectedInstOperands,
15667 /* 40858 */ // GIR_Coverage, 271,
15668 /* 40858 */ GIR_Done,
15669 /* 40859 */ // Label 1200: @40859
15670 /* 40859 */ GIM_Reject,
15671 /* 40860 */ // Label 1197: @40860
15672 /* 40860 */ GIM_Reject,
15673 /* 40861 */ // Label 1183: @40861
15674 /* 40861 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(41509),
15675 /* 40866 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
15676 /* 40869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15677 /* 40872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15678 /* 40876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1202*/ GIMT_Encode4(41181), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2804 //
15679 /* 40883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15680 /* 40887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15681 /* 40891 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15682 /* 40895 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15683 /* 40899 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15684 /* 40903 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15685 /* 40907 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15686 /* 40910 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15687 /* 40914 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15688 /* 40918 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15689 /* 40922 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15690 /* 40926 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15691 /* 40930 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15692 /* 40934 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15693 /* 40938 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15694 /* 40942 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15695 /* 40946 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15696 /* 40950 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15697 /* 40954 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15698 /* 40958 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15699 /* 40962 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15700 /* 40966 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15701 /* 40970 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15702 /* 40974 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15703 /* 40978 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15704 /* 40982 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15705 /* 40986 */ // MIs[3] Operand 1
15706 /* 40986 */ // No operand predicates
15707 /* 40986 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15708 /* 40990 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15709 /* 40994 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15710 /* 40998 */ // MIs[4] Operand 1
15711 /* 40998 */ // No operand predicates
15712 /* 40998 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15713 /* 41002 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15714 /* 41006 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15715 /* 41010 */ // MIs[5] Operand 1
15716 /* 41010 */ // No operand predicates
15717 /* 41010 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15718 /* 41014 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15719 /* 41018 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15720 /* 41022 */ // MIs[6] Operand 1
15721 /* 41022 */ // No operand predicates
15722 /* 41022 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15723 /* 41026 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15724 /* 41030 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15725 /* 41034 */ // MIs[7] Operand 1
15726 /* 41034 */ // No operand predicates
15727 /* 41034 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15728 /* 41038 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15729 /* 41042 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15730 /* 41046 */ // MIs[8] Operand 1
15731 /* 41046 */ // No operand predicates
15732 /* 41046 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15733 /* 41050 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15734 /* 41054 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15735 /* 41058 */ // MIs[9] Operand 1
15736 /* 41058 */ // No operand predicates
15737 /* 41058 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15738 /* 41062 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15739 /* 41066 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15740 /* 41070 */ // MIs[10] Operand 1
15741 /* 41070 */ // No operand predicates
15742 /* 41070 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15743 /* 41074 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15744 /* 41078 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15745 /* 41082 */ // MIs[11] Operand 1
15746 /* 41082 */ // No operand predicates
15747 /* 41082 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15748 /* 41086 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15749 /* 41090 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15750 /* 41094 */ // MIs[12] Operand 1
15751 /* 41094 */ // No operand predicates
15752 /* 41094 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15753 /* 41098 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15754 /* 41102 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15755 /* 41106 */ // MIs[13] Operand 1
15756 /* 41106 */ // No operand predicates
15757 /* 41106 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15758 /* 41110 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15759 /* 41114 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15760 /* 41118 */ // MIs[14] Operand 1
15761 /* 41118 */ // No operand predicates
15762 /* 41118 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15763 /* 41122 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15764 /* 41126 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15765 /* 41130 */ // MIs[15] Operand 1
15766 /* 41130 */ // No operand predicates
15767 /* 41130 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15768 /* 41134 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15769 /* 41138 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15770 /* 41142 */ // MIs[16] Operand 1
15771 /* 41142 */ // No operand predicates
15772 /* 41142 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15773 /* 41146 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15774 /* 41150 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15775 /* 41154 */ // MIs[17] Operand 1
15776 /* 41154 */ // No operand predicates
15777 /* 41154 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15778 /* 41158 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15779 /* 41162 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15780 /* 41166 */ // MIs[18] Operand 1
15781 /* 41166 */ // No operand predicates
15782 /* 41166 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
15783 /* 41168 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15784 /* 41168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15785 /* 41171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15786 /* 41173 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15787 /* 41175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15788 /* 41179 */ GIR_RootConstrainSelectedInstOperands,
15789 /* 41180 */ // GIR_Coverage, 2804,
15790 /* 41180 */ GIR_EraseRootFromParent_Done,
15791 /* 41181 */ // Label 1202: @41181
15792 /* 41181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1203*/ GIMT_Encode4(41486), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2330 //
15793 /* 41188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15794 /* 41192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15795 /* 41196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15796 /* 41200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15797 /* 41204 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15798 /* 41208 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15799 /* 41212 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15800 /* 41215 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15801 /* 41219 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15802 /* 41223 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15803 /* 41227 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15804 /* 41231 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15805 /* 41235 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15806 /* 41239 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15807 /* 41243 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15808 /* 41247 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15809 /* 41251 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15810 /* 41255 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15811 /* 41259 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15812 /* 41263 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15813 /* 41267 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15814 /* 41271 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15815 /* 41275 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15816 /* 41279 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15817 /* 41283 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15818 /* 41287 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15819 /* 41291 */ // MIs[3] Operand 1
15820 /* 41291 */ // No operand predicates
15821 /* 41291 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15822 /* 41295 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15823 /* 41299 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15824 /* 41303 */ // MIs[4] Operand 1
15825 /* 41303 */ // No operand predicates
15826 /* 41303 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15827 /* 41307 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15828 /* 41311 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15829 /* 41315 */ // MIs[5] Operand 1
15830 /* 41315 */ // No operand predicates
15831 /* 41315 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15832 /* 41319 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15833 /* 41323 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15834 /* 41327 */ // MIs[6] Operand 1
15835 /* 41327 */ // No operand predicates
15836 /* 41327 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15837 /* 41331 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15838 /* 41335 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15839 /* 41339 */ // MIs[7] Operand 1
15840 /* 41339 */ // No operand predicates
15841 /* 41339 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15842 /* 41343 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15843 /* 41347 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15844 /* 41351 */ // MIs[8] Operand 1
15845 /* 41351 */ // No operand predicates
15846 /* 41351 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15847 /* 41355 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15848 /* 41359 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15849 /* 41363 */ // MIs[9] Operand 1
15850 /* 41363 */ // No operand predicates
15851 /* 41363 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15852 /* 41367 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15853 /* 41371 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15854 /* 41375 */ // MIs[10] Operand 1
15855 /* 41375 */ // No operand predicates
15856 /* 41375 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15857 /* 41379 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15858 /* 41383 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15859 /* 41387 */ // MIs[11] Operand 1
15860 /* 41387 */ // No operand predicates
15861 /* 41387 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15862 /* 41391 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15863 /* 41395 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15864 /* 41399 */ // MIs[12] Operand 1
15865 /* 41399 */ // No operand predicates
15866 /* 41399 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15867 /* 41403 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15868 /* 41407 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15869 /* 41411 */ // MIs[13] Operand 1
15870 /* 41411 */ // No operand predicates
15871 /* 41411 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15872 /* 41415 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15873 /* 41419 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15874 /* 41423 */ // MIs[14] Operand 1
15875 /* 41423 */ // No operand predicates
15876 /* 41423 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15877 /* 41427 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15878 /* 41431 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15879 /* 41435 */ // MIs[15] Operand 1
15880 /* 41435 */ // No operand predicates
15881 /* 41435 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15882 /* 41439 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15883 /* 41443 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15884 /* 41447 */ // MIs[16] Operand 1
15885 /* 41447 */ // No operand predicates
15886 /* 41447 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15887 /* 41451 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15888 /* 41455 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15889 /* 41459 */ // MIs[17] Operand 1
15890 /* 41459 */ // No operand predicates
15891 /* 41459 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15892 /* 41463 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15893 /* 41467 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15894 /* 41471 */ // MIs[18] Operand 1
15895 /* 41471 */ // No operand predicates
15896 /* 41471 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
15897 /* 41473 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15898 /* 41473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15899 /* 41476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15900 /* 41478 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15901 /* 41480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15902 /* 41484 */ GIR_RootConstrainSelectedInstOperands,
15903 /* 41485 */ // GIR_Coverage, 2330,
15904 /* 41485 */ GIR_EraseRootFromParent_Done,
15905 /* 41486 */ // Label 1203: @41486
15906 /* 41486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1204*/ GIMT_Encode4(41508), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1024 //
15907 /* 41493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15908 /* 41497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15909 /* 41501 */ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15910 /* 41501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15911 /* 41506 */ GIR_RootConstrainSelectedInstOperands,
15912 /* 41507 */ // GIR_Coverage, 1024,
15913 /* 41507 */ GIR_Done,
15914 /* 41508 */ // Label 1204: @41508
15915 /* 41508 */ GIM_Reject,
15916 /* 41509 */ // Label 1201: @41509
15917 /* 41509 */ GIM_Reject,
15918 /* 41510 */ // Label 1184: @41510
15919 /* 41510 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(41902),
15920 /* 41515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
15921 /* 41518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15922 /* 41521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15923 /* 41525 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1206*/ GIMT_Encode4(41702), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2805 //
15924 /* 41532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15925 /* 41536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15926 /* 41540 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15927 /* 41544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15928 /* 41548 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15929 /* 41552 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15930 /* 41556 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15931 /* 41559 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15932 /* 41563 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15933 /* 41567 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15934 /* 41571 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15935 /* 41575 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15936 /* 41579 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15937 /* 41583 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15938 /* 41587 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15939 /* 41591 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15940 /* 41595 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15941 /* 41599 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15942 /* 41603 */ // MIs[3] Operand 1
15943 /* 41603 */ // No operand predicates
15944 /* 41603 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15945 /* 41607 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15946 /* 41611 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15947 /* 41615 */ // MIs[4] Operand 1
15948 /* 41615 */ // No operand predicates
15949 /* 41615 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15950 /* 41619 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15951 /* 41623 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15952 /* 41627 */ // MIs[5] Operand 1
15953 /* 41627 */ // No operand predicates
15954 /* 41627 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15955 /* 41631 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15956 /* 41635 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15957 /* 41639 */ // MIs[6] Operand 1
15958 /* 41639 */ // No operand predicates
15959 /* 41639 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15960 /* 41643 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15961 /* 41647 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15962 /* 41651 */ // MIs[7] Operand 1
15963 /* 41651 */ // No operand predicates
15964 /* 41651 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15965 /* 41655 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15966 /* 41659 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15967 /* 41663 */ // MIs[8] Operand 1
15968 /* 41663 */ // No operand predicates
15969 /* 41663 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15970 /* 41667 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15971 /* 41671 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15972 /* 41675 */ // MIs[9] Operand 1
15973 /* 41675 */ // No operand predicates
15974 /* 41675 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15975 /* 41679 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15976 /* 41683 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15977 /* 41687 */ // MIs[10] Operand 1
15978 /* 41687 */ // No operand predicates
15979 /* 41687 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
15980 /* 41689 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15981 /* 41689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
15982 /* 41692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15983 /* 41694 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15984 /* 41696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15985 /* 41700 */ GIR_RootConstrainSelectedInstOperands,
15986 /* 41701 */ // GIR_Coverage, 2805,
15987 /* 41701 */ GIR_EraseRootFromParent_Done,
15988 /* 41702 */ // Label 1206: @41702
15989 /* 41702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1207*/ GIMT_Encode4(41879), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2331 //
15990 /* 41709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15991 /* 41713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15992 /* 41717 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15993 /* 41721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15994 /* 41725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15995 /* 41729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15996 /* 41733 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15997 /* 41736 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15998 /* 41740 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15999 /* 41744 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16000 /* 41748 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16001 /* 41752 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16002 /* 41756 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16003 /* 41760 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16004 /* 41764 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16005 /* 41768 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16006 /* 41772 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16007 /* 41776 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16008 /* 41780 */ // MIs[3] Operand 1
16009 /* 41780 */ // No operand predicates
16010 /* 41780 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16011 /* 41784 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16012 /* 41788 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16013 /* 41792 */ // MIs[4] Operand 1
16014 /* 41792 */ // No operand predicates
16015 /* 41792 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16016 /* 41796 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16017 /* 41800 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16018 /* 41804 */ // MIs[5] Operand 1
16019 /* 41804 */ // No operand predicates
16020 /* 41804 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16021 /* 41808 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16022 /* 41812 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16023 /* 41816 */ // MIs[6] Operand 1
16024 /* 41816 */ // No operand predicates
16025 /* 41816 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16026 /* 41820 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16027 /* 41824 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16028 /* 41828 */ // MIs[7] Operand 1
16029 /* 41828 */ // No operand predicates
16030 /* 41828 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16031 /* 41832 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16032 /* 41836 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16033 /* 41840 */ // MIs[8] Operand 1
16034 /* 41840 */ // No operand predicates
16035 /* 41840 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16036 /* 41844 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16037 /* 41848 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16038 /* 41852 */ // MIs[9] Operand 1
16039 /* 41852 */ // No operand predicates
16040 /* 41852 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16041 /* 41856 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16042 /* 41860 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16043 /* 41864 */ // MIs[10] Operand 1
16044 /* 41864 */ // No operand predicates
16045 /* 41864 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16046 /* 41866 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16047 /* 41866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16048 /* 41869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16049 /* 41871 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16050 /* 41873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16051 /* 41877 */ GIR_RootConstrainSelectedInstOperands,
16052 /* 41878 */ // GIR_Coverage, 2331,
16053 /* 41878 */ GIR_EraseRootFromParent_Done,
16054 /* 41879 */ // Label 1207: @41879
16055 /* 41879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1208*/ GIMT_Encode4(41901), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1025 //
16056 /* 41886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16057 /* 41890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16058 /* 41894 */ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16059 /* 41894 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16060 /* 41899 */ GIR_RootConstrainSelectedInstOperands,
16061 /* 41900 */ // GIR_Coverage, 1025,
16062 /* 41900 */ GIR_Done,
16063 /* 41901 */ // Label 1208: @41901
16064 /* 41901 */ GIM_Reject,
16065 /* 41902 */ // Label 1205: @41902
16066 /* 41902 */ GIM_Reject,
16067 /* 41903 */ // Label 1185: @41903
16068 /* 41903 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(42167),
16069 /* 41908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16070 /* 41911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16071 /* 41914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16072 /* 41918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(42031), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2806 //
16073 /* 41925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16074 /* 41929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16075 /* 41933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16076 /* 41937 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16077 /* 41941 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16078 /* 41945 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16079 /* 41949 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16080 /* 41952 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16081 /* 41956 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16082 /* 41960 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16083 /* 41964 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16084 /* 41968 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16085 /* 41972 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16086 /* 41976 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16087 /* 41980 */ // MIs[3] Operand 1
16088 /* 41980 */ // No operand predicates
16089 /* 41980 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16090 /* 41984 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16091 /* 41988 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16092 /* 41992 */ // MIs[4] Operand 1
16093 /* 41992 */ // No operand predicates
16094 /* 41992 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16095 /* 41996 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16096 /* 42000 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16097 /* 42004 */ // MIs[5] Operand 1
16098 /* 42004 */ // No operand predicates
16099 /* 42004 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16100 /* 42008 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16101 /* 42012 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16102 /* 42016 */ // MIs[6] Operand 1
16103 /* 42016 */ // No operand predicates
16104 /* 42016 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16105 /* 42018 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16106 /* 42018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16107 /* 42021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16108 /* 42023 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16109 /* 42025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16110 /* 42029 */ GIR_RootConstrainSelectedInstOperands,
16111 /* 42030 */ // GIR_Coverage, 2806,
16112 /* 42030 */ GIR_EraseRootFromParent_Done,
16113 /* 42031 */ // Label 1210: @42031
16114 /* 42031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1211*/ GIMT_Encode4(42144), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2332 //
16115 /* 42038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16116 /* 42042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16117 /* 42046 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16118 /* 42050 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16119 /* 42054 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16120 /* 42058 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16121 /* 42062 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16122 /* 42065 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16123 /* 42069 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16124 /* 42073 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16125 /* 42077 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16126 /* 42081 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16127 /* 42085 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16128 /* 42089 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16129 /* 42093 */ // MIs[3] Operand 1
16130 /* 42093 */ // No operand predicates
16131 /* 42093 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16132 /* 42097 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16133 /* 42101 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16134 /* 42105 */ // MIs[4] Operand 1
16135 /* 42105 */ // No operand predicates
16136 /* 42105 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16137 /* 42109 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16138 /* 42113 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16139 /* 42117 */ // MIs[5] Operand 1
16140 /* 42117 */ // No operand predicates
16141 /* 42117 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16142 /* 42121 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16143 /* 42125 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16144 /* 42129 */ // MIs[6] Operand 1
16145 /* 42129 */ // No operand predicates
16146 /* 42129 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16147 /* 42131 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16148 /* 42131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16149 /* 42134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16150 /* 42136 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16151 /* 42138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16152 /* 42142 */ GIR_RootConstrainSelectedInstOperands,
16153 /* 42143 */ // GIR_Coverage, 2332,
16154 /* 42143 */ GIR_EraseRootFromParent_Done,
16155 /* 42144 */ // Label 1211: @42144
16156 /* 42144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1212*/ GIMT_Encode4(42166), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1026 //
16157 /* 42151 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16158 /* 42155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16159 /* 42159 */ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16160 /* 42159 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16161 /* 42164 */ GIR_RootConstrainSelectedInstOperands,
16162 /* 42165 */ // GIR_Coverage, 1026,
16163 /* 42165 */ GIR_Done,
16164 /* 42166 */ // Label 1212: @42166
16165 /* 42166 */ GIM_Reject,
16166 /* 42167 */ // Label 1209: @42167
16167 /* 42167 */ GIM_Reject,
16168 /* 42168 */ // Label 1186: @42168
16169 /* 42168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1213*/ GIMT_Encode4(42200), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1027 //
16170 /* 42175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16171 /* 42178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16172 /* 42181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16173 /* 42185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16174 /* 42189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16175 /* 42193 */ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16176 /* 42193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
16177 /* 42198 */ GIR_RootConstrainSelectedInstOperands,
16178 /* 42199 */ // GIR_Coverage, 1027,
16179 /* 42199 */ GIR_Done,
16180 /* 42200 */ // Label 1213: @42200
16181 /* 42200 */ GIM_Reject,
16182 /* 42201 */ // Label 1187: @42201
16183 /* 42201 */ GIM_Reject,
16184 /* 42202 */ // Label 39: @42202
16185 /* 42202 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1220*/ GIMT_Encode4(43976),
16186 /* 42213 */ /*GILLT_s32*//*Label 1214*/ GIMT_Encode4(42245),
16187 /* 42217 */ /*GILLT_s64*//*Label 1215*/ GIMT_Encode4(42498), GIMT_Encode4(0),
16188 /* 42225 */ /*GILLT_v16s8*//*Label 1216*/ GIMT_Encode4(42636), GIMT_Encode4(0),
16189 /* 42233 */ /*GILLT_v8s16*//*Label 1217*/ GIMT_Encode4(43285),
16190 /* 42237 */ /*GILLT_v4s32*//*Label 1218*/ GIMT_Encode4(43678),
16191 /* 42241 */ /*GILLT_v2s64*//*Label 1219*/ GIMT_Encode4(43943),
16192 /* 42245 */ // Label 1214: @42245
16193 /* 42245 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(42497),
16194 /* 42250 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16195 /* 42253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16196 /* 42256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1222*/ GIMT_Encode4(42297), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 57 //
16197 /* 42263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16198 /* 42267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16199 /* 42271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16200 /* 42275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16201 /* 42279 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16202 /* 42283 */ // MIs[1] Operand 1
16203 /* 42283 */ // No operand predicates
16204 /* 42283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16205 /* 42285 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16206 /* 42285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
16207 /* 42288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16208 /* 42290 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16209 /* 42292 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16210 /* 42295 */ GIR_RootConstrainSelectedInstOperands,
16211 /* 42296 */ // GIR_Coverage, 57,
16212 /* 42296 */ GIR_EraseRootFromParent_Done,
16213 /* 42297 */ // Label 1222: @42297
16214 /* 42297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1223*/ GIMT_Encode4(42338), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2083 //
16215 /* 42304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16216 /* 42308 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16217 /* 42312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16218 /* 42316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16219 /* 42320 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16220 /* 42324 */ // MIs[1] Operand 1
16221 /* 42324 */ // No operand predicates
16222 /* 42324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16223 /* 42326 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16224 /* 42326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
16225 /* 42329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16226 /* 42331 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16227 /* 42333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16228 /* 42336 */ GIR_RootConstrainSelectedInstOperands,
16229 /* 42337 */ // GIR_Coverage, 2083,
16230 /* 42337 */ GIR_EraseRootFromParent_Done,
16231 /* 42338 */ // Label 1223: @42338
16232 /* 42338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1224*/ GIMT_Encode4(42379), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2439 //
16233 /* 42345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16234 /* 42349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16235 /* 42353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16236 /* 42357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16237 /* 42361 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16238 /* 42365 */ // MIs[1] Operand 1
16239 /* 42365 */ // No operand predicates
16240 /* 42365 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16241 /* 42367 */ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16242 /* 42367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
16243 /* 42370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16244 /* 42372 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16245 /* 42374 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16246 /* 42377 */ GIR_RootConstrainSelectedInstOperands,
16247 /* 42378 */ // GIR_Coverage, 2439,
16248 /* 42378 */ GIR_EraseRootFromParent_Done,
16249 /* 42379 */ // Label 1224: @42379
16250 /* 42379 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(42444),
16251 /* 42384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16252 /* 42388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16253 /* 42392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1226*/ GIMT_Encode4(42425), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2440 //
16254 /* 42399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16255 /* 42403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16256 /* 42407 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16257 /* 42411 */ // MIs[1] Operand 1
16258 /* 42411 */ // No operand predicates
16259 /* 42411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16260 /* 42413 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16261 /* 42413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
16262 /* 42416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16263 /* 42418 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16264 /* 42420 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16265 /* 42423 */ GIR_RootConstrainSelectedInstOperands,
16266 /* 42424 */ // GIR_Coverage, 2440,
16267 /* 42424 */ GIR_EraseRootFromParent_Done,
16268 /* 42425 */ // Label 1226: @42425
16269 /* 42425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1227*/ GIMT_Encode4(42443), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 63 //
16270 /* 42432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16271 /* 42436 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16272 /* 42436 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
16273 /* 42441 */ GIR_RootConstrainSelectedInstOperands,
16274 /* 42442 */ // GIR_Coverage, 63,
16275 /* 42442 */ GIR_Done,
16276 /* 42443 */ // Label 1227: @42443
16277 /* 42443 */ GIM_Reject,
16278 /* 42444 */ // Label 1225: @42444
16279 /* 42444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1228*/ GIMT_Encode4(42470), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2087 //
16280 /* 42451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16281 /* 42455 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16282 /* 42459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16283 /* 42463 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16284 /* 42463 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
16285 /* 42468 */ GIR_RootConstrainSelectedInstOperands,
16286 /* 42469 */ // GIR_Coverage, 2087,
16287 /* 42469 */ GIR_Done,
16288 /* 42470 */ // Label 1228: @42470
16289 /* 42470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1229*/ GIMT_Encode4(42496), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2441 //
16290 /* 42477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16291 /* 42481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16292 /* 42485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16293 /* 42489 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16294 /* 42489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
16295 /* 42494 */ GIR_RootConstrainSelectedInstOperands,
16296 /* 42495 */ // GIR_Coverage, 2441,
16297 /* 42495 */ GIR_Done,
16298 /* 42496 */ // Label 1229: @42496
16299 /* 42496 */ GIM_Reject,
16300 /* 42497 */ // Label 1221: @42497
16301 /* 42497 */ GIM_Reject,
16302 /* 42498 */ // Label 1215: @42498
16303 /* 42498 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(42635),
16304 /* 42503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16305 /* 42506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16306 /* 42509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16307 /* 42513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16308 /* 42517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1231*/ GIMT_Encode4(42550), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 267 //
16309 /* 42524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16310 /* 42528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16311 /* 42532 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16312 /* 42536 */ // MIs[1] Operand 1
16313 /* 42536 */ // No operand predicates
16314 /* 42536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16315 /* 42538 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16316 /* 42538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
16317 /* 42541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16318 /* 42543 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16319 /* 42545 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16320 /* 42548 */ GIR_RootConstrainSelectedInstOperands,
16321 /* 42549 */ // GIR_Coverage, 267,
16322 /* 42549 */ GIR_EraseRootFromParent_Done,
16323 /* 42550 */ // Label 1231: @42550
16324 /* 42550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1232*/ GIMT_Encode4(42616), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1769 //
16325 /* 42557 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16326 /* 42561 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16327 /* 42565 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16328 /* 42569 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16329 /* 42574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16330 /* 42576 */ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16331 /* 42576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16332 /* 42579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16333 /* 42583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16334 /* 42588 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16335 /* 42594 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16336 /* 42599 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16337 /* 42604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16338 /* 42607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16339 /* 42609 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16340 /* 42611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16341 /* 42614 */ GIR_RootConstrainSelectedInstOperands,
16342 /* 42615 */ // GIR_Coverage, 1769,
16343 /* 42615 */ GIR_EraseRootFromParent_Done,
16344 /* 42616 */ // Label 1232: @42616
16345 /* 42616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1233*/ GIMT_Encode4(42634), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 275 //
16346 /* 42623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16347 /* 42627 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16348 /* 42627 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16349 /* 42632 */ GIR_RootConstrainSelectedInstOperands,
16350 /* 42633 */ // GIR_Coverage, 275,
16351 /* 42633 */ GIR_Done,
16352 /* 42634 */ // Label 1233: @42634
16353 /* 42634 */ GIM_Reject,
16354 /* 42635 */ // Label 1230: @42635
16355 /* 42635 */ GIM_Reject,
16356 /* 42636 */ // Label 1216: @42636
16357 /* 42636 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(43284),
16358 /* 42641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16359 /* 42644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16360 /* 42647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16361 /* 42651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1235*/ GIMT_Encode4(42956), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2820 //
16362 /* 42658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16363 /* 42662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16364 /* 42666 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16365 /* 42670 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16366 /* 42674 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16367 /* 42678 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16368 /* 42682 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16369 /* 42685 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16370 /* 42689 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16371 /* 42693 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16372 /* 42697 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16373 /* 42701 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16374 /* 42705 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16375 /* 42709 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16376 /* 42713 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16377 /* 42717 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16378 /* 42721 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16379 /* 42725 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16380 /* 42729 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16381 /* 42733 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16382 /* 42737 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16383 /* 42741 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16384 /* 42745 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16385 /* 42749 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16386 /* 42753 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16387 /* 42757 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16388 /* 42761 */ // MIs[3] Operand 1
16389 /* 42761 */ // No operand predicates
16390 /* 42761 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16391 /* 42765 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16392 /* 42769 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16393 /* 42773 */ // MIs[4] Operand 1
16394 /* 42773 */ // No operand predicates
16395 /* 42773 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16396 /* 42777 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16397 /* 42781 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16398 /* 42785 */ // MIs[5] Operand 1
16399 /* 42785 */ // No operand predicates
16400 /* 42785 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16401 /* 42789 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16402 /* 42793 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16403 /* 42797 */ // MIs[6] Operand 1
16404 /* 42797 */ // No operand predicates
16405 /* 42797 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16406 /* 42801 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16407 /* 42805 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16408 /* 42809 */ // MIs[7] Operand 1
16409 /* 42809 */ // No operand predicates
16410 /* 42809 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16411 /* 42813 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16412 /* 42817 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16413 /* 42821 */ // MIs[8] Operand 1
16414 /* 42821 */ // No operand predicates
16415 /* 42821 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16416 /* 42825 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16417 /* 42829 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16418 /* 42833 */ // MIs[9] Operand 1
16419 /* 42833 */ // No operand predicates
16420 /* 42833 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16421 /* 42837 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16422 /* 42841 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16423 /* 42845 */ // MIs[10] Operand 1
16424 /* 42845 */ // No operand predicates
16425 /* 42845 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16426 /* 42849 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16427 /* 42853 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16428 /* 42857 */ // MIs[11] Operand 1
16429 /* 42857 */ // No operand predicates
16430 /* 42857 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16431 /* 42861 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16432 /* 42865 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16433 /* 42869 */ // MIs[12] Operand 1
16434 /* 42869 */ // No operand predicates
16435 /* 42869 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16436 /* 42873 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16437 /* 42877 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16438 /* 42881 */ // MIs[13] Operand 1
16439 /* 42881 */ // No operand predicates
16440 /* 42881 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16441 /* 42885 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16442 /* 42889 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16443 /* 42893 */ // MIs[14] Operand 1
16444 /* 42893 */ // No operand predicates
16445 /* 42893 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16446 /* 42897 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16447 /* 42901 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16448 /* 42905 */ // MIs[15] Operand 1
16449 /* 42905 */ // No operand predicates
16450 /* 42905 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16451 /* 42909 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16452 /* 42913 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16453 /* 42917 */ // MIs[16] Operand 1
16454 /* 42917 */ // No operand predicates
16455 /* 42917 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16456 /* 42921 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16457 /* 42925 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16458 /* 42929 */ // MIs[17] Operand 1
16459 /* 42929 */ // No operand predicates
16460 /* 42929 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16461 /* 42933 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16462 /* 42937 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16463 /* 42941 */ // MIs[18] Operand 1
16464 /* 42941 */ // No operand predicates
16465 /* 42941 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16466 /* 42943 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16467 /* 42943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16468 /* 42946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16469 /* 42948 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16470 /* 42950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16471 /* 42954 */ GIR_RootConstrainSelectedInstOperands,
16472 /* 42955 */ // GIR_Coverage, 2820,
16473 /* 42955 */ GIR_EraseRootFromParent_Done,
16474 /* 42956 */ // Label 1235: @42956
16475 /* 42956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1236*/ GIMT_Encode4(43261), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2338 //
16476 /* 42963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16477 /* 42967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16478 /* 42971 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16479 /* 42975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16480 /* 42979 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16481 /* 42983 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16482 /* 42987 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16483 /* 42990 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16484 /* 42994 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16485 /* 42998 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16486 /* 43002 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16487 /* 43006 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16488 /* 43010 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16489 /* 43014 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16490 /* 43018 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16491 /* 43022 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16492 /* 43026 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16493 /* 43030 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16494 /* 43034 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16495 /* 43038 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16496 /* 43042 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16497 /* 43046 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16498 /* 43050 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16499 /* 43054 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16500 /* 43058 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16501 /* 43062 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16502 /* 43066 */ // MIs[3] Operand 1
16503 /* 43066 */ // No operand predicates
16504 /* 43066 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16505 /* 43070 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16506 /* 43074 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16507 /* 43078 */ // MIs[4] Operand 1
16508 /* 43078 */ // No operand predicates
16509 /* 43078 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16510 /* 43082 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16511 /* 43086 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16512 /* 43090 */ // MIs[5] Operand 1
16513 /* 43090 */ // No operand predicates
16514 /* 43090 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16515 /* 43094 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16516 /* 43098 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16517 /* 43102 */ // MIs[6] Operand 1
16518 /* 43102 */ // No operand predicates
16519 /* 43102 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16520 /* 43106 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16521 /* 43110 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16522 /* 43114 */ // MIs[7] Operand 1
16523 /* 43114 */ // No operand predicates
16524 /* 43114 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16525 /* 43118 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16526 /* 43122 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16527 /* 43126 */ // MIs[8] Operand 1
16528 /* 43126 */ // No operand predicates
16529 /* 43126 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16530 /* 43130 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16531 /* 43134 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16532 /* 43138 */ // MIs[9] Operand 1
16533 /* 43138 */ // No operand predicates
16534 /* 43138 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16535 /* 43142 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16536 /* 43146 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16537 /* 43150 */ // MIs[10] Operand 1
16538 /* 43150 */ // No operand predicates
16539 /* 43150 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16540 /* 43154 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16541 /* 43158 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16542 /* 43162 */ // MIs[11] Operand 1
16543 /* 43162 */ // No operand predicates
16544 /* 43162 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16545 /* 43166 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16546 /* 43170 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16547 /* 43174 */ // MIs[12] Operand 1
16548 /* 43174 */ // No operand predicates
16549 /* 43174 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16550 /* 43178 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16551 /* 43182 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16552 /* 43186 */ // MIs[13] Operand 1
16553 /* 43186 */ // No operand predicates
16554 /* 43186 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16555 /* 43190 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16556 /* 43194 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16557 /* 43198 */ // MIs[14] Operand 1
16558 /* 43198 */ // No operand predicates
16559 /* 43198 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16560 /* 43202 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16561 /* 43206 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16562 /* 43210 */ // MIs[15] Operand 1
16563 /* 43210 */ // No operand predicates
16564 /* 43210 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16565 /* 43214 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16566 /* 43218 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16567 /* 43222 */ // MIs[16] Operand 1
16568 /* 43222 */ // No operand predicates
16569 /* 43222 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16570 /* 43226 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16571 /* 43230 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16572 /* 43234 */ // MIs[17] Operand 1
16573 /* 43234 */ // No operand predicates
16574 /* 43234 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16575 /* 43238 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16576 /* 43242 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16577 /* 43246 */ // MIs[18] Operand 1
16578 /* 43246 */ // No operand predicates
16579 /* 43246 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16580 /* 43248 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16581 /* 43248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16582 /* 43251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16583 /* 43253 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16584 /* 43255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16585 /* 43259 */ GIR_RootConstrainSelectedInstOperands,
16586 /* 43260 */ // GIR_Coverage, 2338,
16587 /* 43260 */ GIR_EraseRootFromParent_Done,
16588 /* 43261 */ // Label 1236: @43261
16589 /* 43261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1237*/ GIMT_Encode4(43283), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1056 //
16590 /* 43268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16591 /* 43272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16592 /* 43276 */ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
16593 /* 43276 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16594 /* 43281 */ GIR_RootConstrainSelectedInstOperands,
16595 /* 43282 */ // GIR_Coverage, 1056,
16596 /* 43282 */ GIR_Done,
16597 /* 43283 */ // Label 1237: @43283
16598 /* 43283 */ GIM_Reject,
16599 /* 43284 */ // Label 1234: @43284
16600 /* 43284 */ GIM_Reject,
16601 /* 43285 */ // Label 1217: @43285
16602 /* 43285 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(43677),
16603 /* 43290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16604 /* 43293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16605 /* 43296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16606 /* 43300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1239*/ GIMT_Encode4(43477), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2821 //
16607 /* 43307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16608 /* 43311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16609 /* 43315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16610 /* 43319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16611 /* 43323 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16612 /* 43327 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16613 /* 43331 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16614 /* 43334 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16615 /* 43338 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16616 /* 43342 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16617 /* 43346 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16618 /* 43350 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16619 /* 43354 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16620 /* 43358 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16621 /* 43362 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16622 /* 43366 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16623 /* 43370 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16624 /* 43374 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16625 /* 43378 */ // MIs[3] Operand 1
16626 /* 43378 */ // No operand predicates
16627 /* 43378 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16628 /* 43382 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16629 /* 43386 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16630 /* 43390 */ // MIs[4] Operand 1
16631 /* 43390 */ // No operand predicates
16632 /* 43390 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16633 /* 43394 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16634 /* 43398 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16635 /* 43402 */ // MIs[5] Operand 1
16636 /* 43402 */ // No operand predicates
16637 /* 43402 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16638 /* 43406 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16639 /* 43410 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16640 /* 43414 */ // MIs[6] Operand 1
16641 /* 43414 */ // No operand predicates
16642 /* 43414 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16643 /* 43418 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16644 /* 43422 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16645 /* 43426 */ // MIs[7] Operand 1
16646 /* 43426 */ // No operand predicates
16647 /* 43426 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16648 /* 43430 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16649 /* 43434 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16650 /* 43438 */ // MIs[8] Operand 1
16651 /* 43438 */ // No operand predicates
16652 /* 43438 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16653 /* 43442 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16654 /* 43446 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16655 /* 43450 */ // MIs[9] Operand 1
16656 /* 43450 */ // No operand predicates
16657 /* 43450 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16658 /* 43454 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16659 /* 43458 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16660 /* 43462 */ // MIs[10] Operand 1
16661 /* 43462 */ // No operand predicates
16662 /* 43462 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16663 /* 43464 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16664 /* 43464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16665 /* 43467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16666 /* 43469 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16667 /* 43471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16668 /* 43475 */ GIR_RootConstrainSelectedInstOperands,
16669 /* 43476 */ // GIR_Coverage, 2821,
16670 /* 43476 */ GIR_EraseRootFromParent_Done,
16671 /* 43477 */ // Label 1239: @43477
16672 /* 43477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1240*/ GIMT_Encode4(43654), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2339 //
16673 /* 43484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16674 /* 43488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16675 /* 43492 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16676 /* 43496 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16677 /* 43500 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16678 /* 43504 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16679 /* 43508 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16680 /* 43511 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16681 /* 43515 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16682 /* 43519 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16683 /* 43523 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16684 /* 43527 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16685 /* 43531 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16686 /* 43535 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16687 /* 43539 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16688 /* 43543 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16689 /* 43547 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16690 /* 43551 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16691 /* 43555 */ // MIs[3] Operand 1
16692 /* 43555 */ // No operand predicates
16693 /* 43555 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16694 /* 43559 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16695 /* 43563 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16696 /* 43567 */ // MIs[4] Operand 1
16697 /* 43567 */ // No operand predicates
16698 /* 43567 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16699 /* 43571 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16700 /* 43575 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16701 /* 43579 */ // MIs[5] Operand 1
16702 /* 43579 */ // No operand predicates
16703 /* 43579 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16704 /* 43583 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16705 /* 43587 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16706 /* 43591 */ // MIs[6] Operand 1
16707 /* 43591 */ // No operand predicates
16708 /* 43591 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16709 /* 43595 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16710 /* 43599 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16711 /* 43603 */ // MIs[7] Operand 1
16712 /* 43603 */ // No operand predicates
16713 /* 43603 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16714 /* 43607 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16715 /* 43611 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16716 /* 43615 */ // MIs[8] Operand 1
16717 /* 43615 */ // No operand predicates
16718 /* 43615 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16719 /* 43619 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16720 /* 43623 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16721 /* 43627 */ // MIs[9] Operand 1
16722 /* 43627 */ // No operand predicates
16723 /* 43627 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16724 /* 43631 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16725 /* 43635 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16726 /* 43639 */ // MIs[10] Operand 1
16727 /* 43639 */ // No operand predicates
16728 /* 43639 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16729 /* 43641 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16730 /* 43641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16731 /* 43644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16732 /* 43646 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16733 /* 43648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16734 /* 43652 */ GIR_RootConstrainSelectedInstOperands,
16735 /* 43653 */ // GIR_Coverage, 2339,
16736 /* 43653 */ GIR_EraseRootFromParent_Done,
16737 /* 43654 */ // Label 1240: @43654
16738 /* 43654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1241*/ GIMT_Encode4(43676), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1057 //
16739 /* 43661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16740 /* 43665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16741 /* 43669 */ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16742 /* 43669 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16743 /* 43674 */ GIR_RootConstrainSelectedInstOperands,
16744 /* 43675 */ // GIR_Coverage, 1057,
16745 /* 43675 */ GIR_Done,
16746 /* 43676 */ // Label 1241: @43676
16747 /* 43676 */ GIM_Reject,
16748 /* 43677 */ // Label 1238: @43677
16749 /* 43677 */ GIM_Reject,
16750 /* 43678 */ // Label 1218: @43678
16751 /* 43678 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(43942),
16752 /* 43683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16753 /* 43686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16754 /* 43689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16755 /* 43693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1243*/ GIMT_Encode4(43806), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2822 //
16756 /* 43700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16757 /* 43704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16758 /* 43708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16759 /* 43712 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16760 /* 43716 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16761 /* 43720 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16762 /* 43724 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16763 /* 43727 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16764 /* 43731 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16765 /* 43735 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16766 /* 43739 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16767 /* 43743 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16768 /* 43747 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16769 /* 43751 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16770 /* 43755 */ // MIs[3] Operand 1
16771 /* 43755 */ // No operand predicates
16772 /* 43755 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16773 /* 43759 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16774 /* 43763 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16775 /* 43767 */ // MIs[4] Operand 1
16776 /* 43767 */ // No operand predicates
16777 /* 43767 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16778 /* 43771 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16779 /* 43775 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16780 /* 43779 */ // MIs[5] Operand 1
16781 /* 43779 */ // No operand predicates
16782 /* 43779 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16783 /* 43783 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16784 /* 43787 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16785 /* 43791 */ // MIs[6] Operand 1
16786 /* 43791 */ // No operand predicates
16787 /* 43791 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16788 /* 43793 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16789 /* 43793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16790 /* 43796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16791 /* 43798 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16792 /* 43800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16793 /* 43804 */ GIR_RootConstrainSelectedInstOperands,
16794 /* 43805 */ // GIR_Coverage, 2822,
16795 /* 43805 */ GIR_EraseRootFromParent_Done,
16796 /* 43806 */ // Label 1243: @43806
16797 /* 43806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1244*/ GIMT_Encode4(43919), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2340 //
16798 /* 43813 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16799 /* 43817 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16800 /* 43821 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16801 /* 43825 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16802 /* 43829 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16803 /* 43833 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16804 /* 43837 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16805 /* 43840 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16806 /* 43844 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16807 /* 43848 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16808 /* 43852 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16809 /* 43856 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16810 /* 43860 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16811 /* 43864 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16812 /* 43868 */ // MIs[3] Operand 1
16813 /* 43868 */ // No operand predicates
16814 /* 43868 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16815 /* 43872 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16816 /* 43876 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16817 /* 43880 */ // MIs[4] Operand 1
16818 /* 43880 */ // No operand predicates
16819 /* 43880 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16820 /* 43884 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16821 /* 43888 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16822 /* 43892 */ // MIs[5] Operand 1
16823 /* 43892 */ // No operand predicates
16824 /* 43892 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16825 /* 43896 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16826 /* 43900 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16827 /* 43904 */ // MIs[6] Operand 1
16828 /* 43904 */ // No operand predicates
16829 /* 43904 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16830 /* 43906 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16831 /* 43906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16832 /* 43909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16833 /* 43911 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16834 /* 43913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16835 /* 43917 */ GIR_RootConstrainSelectedInstOperands,
16836 /* 43918 */ // GIR_Coverage, 2340,
16837 /* 43918 */ GIR_EraseRootFromParent_Done,
16838 /* 43919 */ // Label 1244: @43919
16839 /* 43919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(43941), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1058 //
16840 /* 43926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16841 /* 43930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16842 /* 43934 */ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16843 /* 43934 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16844 /* 43939 */ GIR_RootConstrainSelectedInstOperands,
16845 /* 43940 */ // GIR_Coverage, 1058,
16846 /* 43940 */ GIR_Done,
16847 /* 43941 */ // Label 1245: @43941
16848 /* 43941 */ GIM_Reject,
16849 /* 43942 */ // Label 1242: @43942
16850 /* 43942 */ GIM_Reject,
16851 /* 43943 */ // Label 1219: @43943
16852 /* 43943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1246*/ GIMT_Encode4(43975), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1059 //
16853 /* 43950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16854 /* 43953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16855 /* 43956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16856 /* 43960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16857 /* 43964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16858 /* 43968 */ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16859 /* 43968 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
16860 /* 43973 */ GIR_RootConstrainSelectedInstOperands,
16861 /* 43974 */ // GIR_Coverage, 1059,
16862 /* 43974 */ GIR_Done,
16863 /* 43975 */ // Label 1246: @43975
16864 /* 43975 */ GIM_Reject,
16865 /* 43976 */ // Label 1220: @43976
16866 /* 43976 */ GIM_Reject,
16867 /* 43977 */ // Label 40: @43977
16868 /* 43977 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1253*/ GIMT_Encode4(45710),
16869 /* 43988 */ /*GILLT_s32*//*Label 1247*/ GIMT_Encode4(44020),
16870 /* 43992 */ /*GILLT_s64*//*Label 1248*/ GIMT_Encode4(44232), GIMT_Encode4(0),
16871 /* 44000 */ /*GILLT_v16s8*//*Label 1249*/ GIMT_Encode4(44370), GIMT_Encode4(0),
16872 /* 44008 */ /*GILLT_v8s16*//*Label 1250*/ GIMT_Encode4(45019),
16873 /* 44012 */ /*GILLT_v4s32*//*Label 1251*/ GIMT_Encode4(45412),
16874 /* 44016 */ /*GILLT_v2s64*//*Label 1252*/ GIMT_Encode4(45677),
16875 /* 44020 */ // Label 1247: @44020
16876 /* 44020 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(44231),
16877 /* 44025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16878 /* 44028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16879 /* 44031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1255*/ GIMT_Encode4(44072), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 59 //
16880 /* 44038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16881 /* 44042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16882 /* 44046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16883 /* 44050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16884 /* 44054 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16885 /* 44058 */ // MIs[1] Operand 1
16886 /* 44058 */ // No operand predicates
16887 /* 44058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16888 /* 44060 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16889 /* 44060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
16890 /* 44063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16891 /* 44065 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16892 /* 44067 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16893 /* 44070 */ GIR_RootConstrainSelectedInstOperands,
16894 /* 44071 */ // GIR_Coverage, 59,
16895 /* 44071 */ GIR_EraseRootFromParent_Done,
16896 /* 44072 */ // Label 1255: @44072
16897 /* 44072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1256*/ GIMT_Encode4(44113), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2084 //
16898 /* 44079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16899 /* 44083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16900 /* 44087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16901 /* 44091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16902 /* 44095 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16903 /* 44099 */ // MIs[1] Operand 1
16904 /* 44099 */ // No operand predicates
16905 /* 44099 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16906 /* 44101 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16907 /* 44101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
16908 /* 44104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16909 /* 44106 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16910 /* 44108 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16911 /* 44111 */ GIR_RootConstrainSelectedInstOperands,
16912 /* 44112 */ // GIR_Coverage, 2084,
16913 /* 44112 */ GIR_EraseRootFromParent_Done,
16914 /* 44113 */ // Label 1256: @44113
16915 /* 44113 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(44178),
16916 /* 44118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16917 /* 44122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16918 /* 44126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1258*/ GIMT_Encode4(44159), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2442 //
16919 /* 44133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16920 /* 44137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16921 /* 44141 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16922 /* 44145 */ // MIs[1] Operand 1
16923 /* 44145 */ // No operand predicates
16924 /* 44145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16925 /* 44147 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16926 /* 44147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
16927 /* 44150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16928 /* 44152 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16929 /* 44154 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16930 /* 44157 */ GIR_RootConstrainSelectedInstOperands,
16931 /* 44158 */ // GIR_Coverage, 2442,
16932 /* 44158 */ GIR_EraseRootFromParent_Done,
16933 /* 44159 */ // Label 1258: @44159
16934 /* 44159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1259*/ GIMT_Encode4(44177), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 65 //
16935 /* 44166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16936 /* 44170 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16937 /* 44170 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
16938 /* 44175 */ GIR_RootConstrainSelectedInstOperands,
16939 /* 44176 */ // GIR_Coverage, 65,
16940 /* 44176 */ GIR_Done,
16941 /* 44177 */ // Label 1259: @44177
16942 /* 44177 */ GIM_Reject,
16943 /* 44178 */ // Label 1257: @44178
16944 /* 44178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1260*/ GIMT_Encode4(44204), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2086 //
16945 /* 44185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16946 /* 44189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16947 /* 44193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16948 /* 44197 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16949 /* 44197 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
16950 /* 44202 */ GIR_RootConstrainSelectedInstOperands,
16951 /* 44203 */ // GIR_Coverage, 2086,
16952 /* 44203 */ GIR_Done,
16953 /* 44204 */ // Label 1260: @44204
16954 /* 44204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1261*/ GIMT_Encode4(44230), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2443 //
16955 /* 44211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16956 /* 44215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16957 /* 44219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16958 /* 44223 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16959 /* 44223 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
16960 /* 44228 */ GIR_RootConstrainSelectedInstOperands,
16961 /* 44229 */ // GIR_Coverage, 2443,
16962 /* 44229 */ GIR_Done,
16963 /* 44230 */ // Label 1261: @44230
16964 /* 44230 */ GIM_Reject,
16965 /* 44231 */ // Label 1254: @44231
16966 /* 44231 */ GIM_Reject,
16967 /* 44232 */ // Label 1248: @44232
16968 /* 44232 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(44369),
16969 /* 44237 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16970 /* 44240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16971 /* 44243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16972 /* 44247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16973 /* 44251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(44284), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 269 //
16974 /* 44258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16975 /* 44262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16976 /* 44266 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16977 /* 44270 */ // MIs[1] Operand 1
16978 /* 44270 */ // No operand predicates
16979 /* 44270 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16980 /* 44272 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16981 /* 44272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
16982 /* 44275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16983 /* 44277 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16984 /* 44279 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16985 /* 44282 */ GIR_RootConstrainSelectedInstOperands,
16986 /* 44283 */ // GIR_Coverage, 269,
16987 /* 44283 */ GIR_EraseRootFromParent_Done,
16988 /* 44284 */ // Label 1263: @44284
16989 /* 44284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1264*/ GIMT_Encode4(44350), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1770 //
16990 /* 44291 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16991 /* 44295 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16992 /* 44299 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16993 /* 44303 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16994 /* 44308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16995 /* 44310 */ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16996 /* 44310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16997 /* 44313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16998 /* 44317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16999 /* 44322 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17000 /* 44328 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17001 /* 44333 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17002 /* 44338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17003 /* 44341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17004 /* 44343 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17005 /* 44345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17006 /* 44348 */ GIR_RootConstrainSelectedInstOperands,
17007 /* 44349 */ // GIR_Coverage, 1770,
17008 /* 44349 */ GIR_EraseRootFromParent_Done,
17009 /* 44350 */ // Label 1264: @44350
17010 /* 44350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1265*/ GIMT_Encode4(44368), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 273 //
17011 /* 44357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17012 /* 44361 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17013 /* 44361 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17014 /* 44366 */ GIR_RootConstrainSelectedInstOperands,
17015 /* 44367 */ // GIR_Coverage, 273,
17016 /* 44367 */ GIR_Done,
17017 /* 44368 */ // Label 1265: @44368
17018 /* 44368 */ GIM_Reject,
17019 /* 44369 */ // Label 1262: @44369
17020 /* 44369 */ GIM_Reject,
17021 /* 44370 */ // Label 1249: @44370
17022 /* 44370 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(45018),
17023 /* 44375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17024 /* 44378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17025 /* 44381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17026 /* 44385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1267*/ GIMT_Encode4(44690), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2824 //
17027 /* 44392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17028 /* 44396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17029 /* 44400 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17030 /* 44404 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17031 /* 44408 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17032 /* 44412 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17033 /* 44416 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17034 /* 44419 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17035 /* 44423 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17036 /* 44427 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17037 /* 44431 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17038 /* 44435 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17039 /* 44439 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17040 /* 44443 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17041 /* 44447 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17042 /* 44451 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17043 /* 44455 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17044 /* 44459 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17045 /* 44463 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17046 /* 44467 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17047 /* 44471 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17048 /* 44475 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17049 /* 44479 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17050 /* 44483 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17051 /* 44487 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17052 /* 44491 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17053 /* 44495 */ // MIs[3] Operand 1
17054 /* 44495 */ // No operand predicates
17055 /* 44495 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17056 /* 44499 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17057 /* 44503 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17058 /* 44507 */ // MIs[4] Operand 1
17059 /* 44507 */ // No operand predicates
17060 /* 44507 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17061 /* 44511 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17062 /* 44515 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17063 /* 44519 */ // MIs[5] Operand 1
17064 /* 44519 */ // No operand predicates
17065 /* 44519 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17066 /* 44523 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17067 /* 44527 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17068 /* 44531 */ // MIs[6] Operand 1
17069 /* 44531 */ // No operand predicates
17070 /* 44531 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17071 /* 44535 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17072 /* 44539 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17073 /* 44543 */ // MIs[7] Operand 1
17074 /* 44543 */ // No operand predicates
17075 /* 44543 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17076 /* 44547 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17077 /* 44551 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17078 /* 44555 */ // MIs[8] Operand 1
17079 /* 44555 */ // No operand predicates
17080 /* 44555 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17081 /* 44559 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17082 /* 44563 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17083 /* 44567 */ // MIs[9] Operand 1
17084 /* 44567 */ // No operand predicates
17085 /* 44567 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17086 /* 44571 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17087 /* 44575 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17088 /* 44579 */ // MIs[10] Operand 1
17089 /* 44579 */ // No operand predicates
17090 /* 44579 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17091 /* 44583 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17092 /* 44587 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17093 /* 44591 */ // MIs[11] Operand 1
17094 /* 44591 */ // No operand predicates
17095 /* 44591 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17096 /* 44595 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17097 /* 44599 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17098 /* 44603 */ // MIs[12] Operand 1
17099 /* 44603 */ // No operand predicates
17100 /* 44603 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17101 /* 44607 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17102 /* 44611 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17103 /* 44615 */ // MIs[13] Operand 1
17104 /* 44615 */ // No operand predicates
17105 /* 44615 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17106 /* 44619 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17107 /* 44623 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17108 /* 44627 */ // MIs[14] Operand 1
17109 /* 44627 */ // No operand predicates
17110 /* 44627 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17111 /* 44631 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17112 /* 44635 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17113 /* 44639 */ // MIs[15] Operand 1
17114 /* 44639 */ // No operand predicates
17115 /* 44639 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17116 /* 44643 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17117 /* 44647 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17118 /* 44651 */ // MIs[16] Operand 1
17119 /* 44651 */ // No operand predicates
17120 /* 44651 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17121 /* 44655 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17122 /* 44659 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17123 /* 44663 */ // MIs[17] Operand 1
17124 /* 44663 */ // No operand predicates
17125 /* 44663 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17126 /* 44667 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17127 /* 44671 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17128 /* 44675 */ // MIs[18] Operand 1
17129 /* 44675 */ // No operand predicates
17130 /* 44675 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17131 /* 44677 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17132 /* 44677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17133 /* 44680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17134 /* 44682 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17135 /* 44684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17136 /* 44688 */ GIR_RootConstrainSelectedInstOperands,
17137 /* 44689 */ // GIR_Coverage, 2824,
17138 /* 44689 */ GIR_EraseRootFromParent_Done,
17139 /* 44690 */ // Label 1267: @44690
17140 /* 44690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1268*/ GIMT_Encode4(44995), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2342 //
17141 /* 44697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17142 /* 44701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17143 /* 44705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17144 /* 44709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17145 /* 44713 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17146 /* 44717 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17147 /* 44721 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17148 /* 44724 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17149 /* 44728 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17150 /* 44732 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17151 /* 44736 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17152 /* 44740 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17153 /* 44744 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17154 /* 44748 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17155 /* 44752 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17156 /* 44756 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17157 /* 44760 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17158 /* 44764 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17159 /* 44768 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17160 /* 44772 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17161 /* 44776 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17162 /* 44780 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17163 /* 44784 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17164 /* 44788 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17165 /* 44792 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17166 /* 44796 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17167 /* 44800 */ // MIs[3] Operand 1
17168 /* 44800 */ // No operand predicates
17169 /* 44800 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17170 /* 44804 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17171 /* 44808 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17172 /* 44812 */ // MIs[4] Operand 1
17173 /* 44812 */ // No operand predicates
17174 /* 44812 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17175 /* 44816 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17176 /* 44820 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17177 /* 44824 */ // MIs[5] Operand 1
17178 /* 44824 */ // No operand predicates
17179 /* 44824 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17180 /* 44828 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17181 /* 44832 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17182 /* 44836 */ // MIs[6] Operand 1
17183 /* 44836 */ // No operand predicates
17184 /* 44836 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17185 /* 44840 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17186 /* 44844 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17187 /* 44848 */ // MIs[7] Operand 1
17188 /* 44848 */ // No operand predicates
17189 /* 44848 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17190 /* 44852 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17191 /* 44856 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17192 /* 44860 */ // MIs[8] Operand 1
17193 /* 44860 */ // No operand predicates
17194 /* 44860 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17195 /* 44864 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17196 /* 44868 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17197 /* 44872 */ // MIs[9] Operand 1
17198 /* 44872 */ // No operand predicates
17199 /* 44872 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17200 /* 44876 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17201 /* 44880 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17202 /* 44884 */ // MIs[10] Operand 1
17203 /* 44884 */ // No operand predicates
17204 /* 44884 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17205 /* 44888 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17206 /* 44892 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17207 /* 44896 */ // MIs[11] Operand 1
17208 /* 44896 */ // No operand predicates
17209 /* 44896 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17210 /* 44900 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17211 /* 44904 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17212 /* 44908 */ // MIs[12] Operand 1
17213 /* 44908 */ // No operand predicates
17214 /* 44908 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17215 /* 44912 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17216 /* 44916 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17217 /* 44920 */ // MIs[13] Operand 1
17218 /* 44920 */ // No operand predicates
17219 /* 44920 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17220 /* 44924 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17221 /* 44928 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17222 /* 44932 */ // MIs[14] Operand 1
17223 /* 44932 */ // No operand predicates
17224 /* 44932 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17225 /* 44936 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17226 /* 44940 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17227 /* 44944 */ // MIs[15] Operand 1
17228 /* 44944 */ // No operand predicates
17229 /* 44944 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17230 /* 44948 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17231 /* 44952 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17232 /* 44956 */ // MIs[16] Operand 1
17233 /* 44956 */ // No operand predicates
17234 /* 44956 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17235 /* 44960 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17236 /* 44964 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17237 /* 44968 */ // MIs[17] Operand 1
17238 /* 44968 */ // No operand predicates
17239 /* 44968 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17240 /* 44972 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17241 /* 44976 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17242 /* 44980 */ // MIs[18] Operand 1
17243 /* 44980 */ // No operand predicates
17244 /* 44980 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17245 /* 44982 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17246 /* 44982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17247 /* 44985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17248 /* 44987 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17249 /* 44989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17250 /* 44993 */ GIR_RootConstrainSelectedInstOperands,
17251 /* 44994 */ // GIR_Coverage, 2342,
17252 /* 44994 */ GIR_EraseRootFromParent_Done,
17253 /* 44995 */ // Label 1268: @44995
17254 /* 44995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1269*/ GIMT_Encode4(45017), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1040 //
17255 /* 45002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17256 /* 45006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17257 /* 45010 */ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17258 /* 45010 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17259 /* 45015 */ GIR_RootConstrainSelectedInstOperands,
17260 /* 45016 */ // GIR_Coverage, 1040,
17261 /* 45016 */ GIR_Done,
17262 /* 45017 */ // Label 1269: @45017
17263 /* 45017 */ GIM_Reject,
17264 /* 45018 */ // Label 1266: @45018
17265 /* 45018 */ GIM_Reject,
17266 /* 45019 */ // Label 1250: @45019
17267 /* 45019 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(45411),
17268 /* 45024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17269 /* 45027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17270 /* 45030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17271 /* 45034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1271*/ GIMT_Encode4(45211), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2825 //
17272 /* 45041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17273 /* 45045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17274 /* 45049 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17275 /* 45053 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17276 /* 45057 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17277 /* 45061 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17278 /* 45065 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17279 /* 45068 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17280 /* 45072 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17281 /* 45076 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17282 /* 45080 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17283 /* 45084 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17284 /* 45088 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17285 /* 45092 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17286 /* 45096 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17287 /* 45100 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17288 /* 45104 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17289 /* 45108 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17290 /* 45112 */ // MIs[3] Operand 1
17291 /* 45112 */ // No operand predicates
17292 /* 45112 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17293 /* 45116 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17294 /* 45120 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17295 /* 45124 */ // MIs[4] Operand 1
17296 /* 45124 */ // No operand predicates
17297 /* 45124 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17298 /* 45128 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17299 /* 45132 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17300 /* 45136 */ // MIs[5] Operand 1
17301 /* 45136 */ // No operand predicates
17302 /* 45136 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17303 /* 45140 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17304 /* 45144 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17305 /* 45148 */ // MIs[6] Operand 1
17306 /* 45148 */ // No operand predicates
17307 /* 45148 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17308 /* 45152 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17309 /* 45156 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17310 /* 45160 */ // MIs[7] Operand 1
17311 /* 45160 */ // No operand predicates
17312 /* 45160 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17313 /* 45164 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17314 /* 45168 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17315 /* 45172 */ // MIs[8] Operand 1
17316 /* 45172 */ // No operand predicates
17317 /* 45172 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17318 /* 45176 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17319 /* 45180 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17320 /* 45184 */ // MIs[9] Operand 1
17321 /* 45184 */ // No operand predicates
17322 /* 45184 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17323 /* 45188 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17324 /* 45192 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17325 /* 45196 */ // MIs[10] Operand 1
17326 /* 45196 */ // No operand predicates
17327 /* 45196 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17328 /* 45198 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17329 /* 45198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17330 /* 45201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17331 /* 45203 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17332 /* 45205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17333 /* 45209 */ GIR_RootConstrainSelectedInstOperands,
17334 /* 45210 */ // GIR_Coverage, 2825,
17335 /* 45210 */ GIR_EraseRootFromParent_Done,
17336 /* 45211 */ // Label 1271: @45211
17337 /* 45211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1272*/ GIMT_Encode4(45388), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2343 //
17338 /* 45218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17339 /* 45222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17340 /* 45226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17341 /* 45230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17342 /* 45234 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17343 /* 45238 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17344 /* 45242 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17345 /* 45245 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17346 /* 45249 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17347 /* 45253 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17348 /* 45257 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17349 /* 45261 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17350 /* 45265 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17351 /* 45269 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17352 /* 45273 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17353 /* 45277 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17354 /* 45281 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17355 /* 45285 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17356 /* 45289 */ // MIs[3] Operand 1
17357 /* 45289 */ // No operand predicates
17358 /* 45289 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17359 /* 45293 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17360 /* 45297 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17361 /* 45301 */ // MIs[4] Operand 1
17362 /* 45301 */ // No operand predicates
17363 /* 45301 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17364 /* 45305 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17365 /* 45309 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17366 /* 45313 */ // MIs[5] Operand 1
17367 /* 45313 */ // No operand predicates
17368 /* 45313 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17369 /* 45317 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17370 /* 45321 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17371 /* 45325 */ // MIs[6] Operand 1
17372 /* 45325 */ // No operand predicates
17373 /* 45325 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17374 /* 45329 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17375 /* 45333 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17376 /* 45337 */ // MIs[7] Operand 1
17377 /* 45337 */ // No operand predicates
17378 /* 45337 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17379 /* 45341 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17380 /* 45345 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17381 /* 45349 */ // MIs[8] Operand 1
17382 /* 45349 */ // No operand predicates
17383 /* 45349 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17384 /* 45353 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17385 /* 45357 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17386 /* 45361 */ // MIs[9] Operand 1
17387 /* 45361 */ // No operand predicates
17388 /* 45361 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17389 /* 45365 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17390 /* 45369 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17391 /* 45373 */ // MIs[10] Operand 1
17392 /* 45373 */ // No operand predicates
17393 /* 45373 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17394 /* 45375 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17395 /* 45375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17396 /* 45378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17397 /* 45380 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17398 /* 45382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17399 /* 45386 */ GIR_RootConstrainSelectedInstOperands,
17400 /* 45387 */ // GIR_Coverage, 2343,
17401 /* 45387 */ GIR_EraseRootFromParent_Done,
17402 /* 45388 */ // Label 1272: @45388
17403 /* 45388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1273*/ GIMT_Encode4(45410), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1041 //
17404 /* 45395 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17405 /* 45399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17406 /* 45403 */ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
17407 /* 45403 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17408 /* 45408 */ GIR_RootConstrainSelectedInstOperands,
17409 /* 45409 */ // GIR_Coverage, 1041,
17410 /* 45409 */ GIR_Done,
17411 /* 45410 */ // Label 1273: @45410
17412 /* 45410 */ GIM_Reject,
17413 /* 45411 */ // Label 1270: @45411
17414 /* 45411 */ GIM_Reject,
17415 /* 45412 */ // Label 1251: @45412
17416 /* 45412 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(45676),
17417 /* 45417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17418 /* 45420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17419 /* 45423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17420 /* 45427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1275*/ GIMT_Encode4(45540), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2826 //
17421 /* 45434 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17422 /* 45438 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17423 /* 45442 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17424 /* 45446 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17425 /* 45450 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17426 /* 45454 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17427 /* 45458 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17428 /* 45461 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17429 /* 45465 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17430 /* 45469 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17431 /* 45473 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17432 /* 45477 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17433 /* 45481 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17434 /* 45485 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17435 /* 45489 */ // MIs[3] Operand 1
17436 /* 45489 */ // No operand predicates
17437 /* 45489 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17438 /* 45493 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17439 /* 45497 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17440 /* 45501 */ // MIs[4] Operand 1
17441 /* 45501 */ // No operand predicates
17442 /* 45501 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17443 /* 45505 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17444 /* 45509 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17445 /* 45513 */ // MIs[5] Operand 1
17446 /* 45513 */ // No operand predicates
17447 /* 45513 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17448 /* 45517 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17449 /* 45521 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17450 /* 45525 */ // MIs[6] Operand 1
17451 /* 45525 */ // No operand predicates
17452 /* 45525 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17453 /* 45527 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17454 /* 45527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17455 /* 45530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17456 /* 45532 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17457 /* 45534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17458 /* 45538 */ GIR_RootConstrainSelectedInstOperands,
17459 /* 45539 */ // GIR_Coverage, 2826,
17460 /* 45539 */ GIR_EraseRootFromParent_Done,
17461 /* 45540 */ // Label 1275: @45540
17462 /* 45540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1276*/ GIMT_Encode4(45653), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2344 //
17463 /* 45547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17464 /* 45551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17465 /* 45555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17466 /* 45559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17467 /* 45563 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17468 /* 45567 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17469 /* 45571 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17470 /* 45574 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17471 /* 45578 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17472 /* 45582 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17473 /* 45586 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17474 /* 45590 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17475 /* 45594 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17476 /* 45598 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17477 /* 45602 */ // MIs[3] Operand 1
17478 /* 45602 */ // No operand predicates
17479 /* 45602 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17480 /* 45606 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17481 /* 45610 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17482 /* 45614 */ // MIs[4] Operand 1
17483 /* 45614 */ // No operand predicates
17484 /* 45614 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17485 /* 45618 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17486 /* 45622 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17487 /* 45626 */ // MIs[5] Operand 1
17488 /* 45626 */ // No operand predicates
17489 /* 45626 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17490 /* 45630 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17491 /* 45634 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17492 /* 45638 */ // MIs[6] Operand 1
17493 /* 45638 */ // No operand predicates
17494 /* 45638 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17495 /* 45640 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17496 /* 45640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17497 /* 45643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17498 /* 45645 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17499 /* 45647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17500 /* 45651 */ GIR_RootConstrainSelectedInstOperands,
17501 /* 45652 */ // GIR_Coverage, 2344,
17502 /* 45652 */ GIR_EraseRootFromParent_Done,
17503 /* 45653 */ // Label 1276: @45653
17504 /* 45653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1277*/ GIMT_Encode4(45675), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1042 //
17505 /* 45660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17506 /* 45664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17507 /* 45668 */ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17508 /* 45668 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17509 /* 45673 */ GIR_RootConstrainSelectedInstOperands,
17510 /* 45674 */ // GIR_Coverage, 1042,
17511 /* 45674 */ GIR_Done,
17512 /* 45675 */ // Label 1277: @45675
17513 /* 45675 */ GIM_Reject,
17514 /* 45676 */ // Label 1274: @45676
17515 /* 45676 */ GIM_Reject,
17516 /* 45677 */ // Label 1252: @45677
17517 /* 45677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1278*/ GIMT_Encode4(45709), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1043 //
17518 /* 45684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17519 /* 45687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17520 /* 45690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17521 /* 45694 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17522 /* 45698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17523 /* 45702 */ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17524 /* 45702 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
17525 /* 45707 */ GIR_RootConstrainSelectedInstOperands,
17526 /* 45708 */ // GIR_Coverage, 1043,
17527 /* 45708 */ GIR_Done,
17528 /* 45709 */ // Label 1278: @45709
17529 /* 45709 */ GIM_Reject,
17530 /* 45710 */ // Label 1253: @45710
17531 /* 45710 */ GIM_Reject,
17532 /* 45711 */ // Label 41: @45711
17533 /* 45711 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1281*/ GIMT_Encode4(45993),
17534 /* 45722 */ /*GILLT_s32*//*Label 1279*/ GIMT_Encode4(45730),
17535 /* 45726 */ /*GILLT_s64*//*Label 1280*/ GIMT_Encode4(45855),
17536 /* 45730 */ // Label 1279: @45730
17537 /* 45730 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(45854),
17538 /* 45735 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17539 /* 45738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17540 /* 45741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17541 /* 45745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17542 /* 45749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1283*/ GIMT_Encode4(45782), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 67 //
17543 /* 45756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17544 /* 45760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17545 /* 45764 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17546 /* 45768 */ // MIs[1] Operand 1
17547 /* 45768 */ // No operand predicates
17548 /* 45768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17549 /* 45770 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17550 /* 45770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
17551 /* 45773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17552 /* 45775 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17553 /* 45777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17554 /* 45780 */ GIR_RootConstrainSelectedInstOperands,
17555 /* 45781 */ // GIR_Coverage, 67,
17556 /* 45781 */ GIR_EraseRootFromParent_Done,
17557 /* 45782 */ // Label 1283: @45782
17558 /* 45782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1284*/ GIMT_Encode4(45815), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1147 //
17559 /* 45789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17560 /* 45793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17561 /* 45797 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17562 /* 45801 */ // MIs[1] Operand 1
17563 /* 45801 */ // No operand predicates
17564 /* 45801 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17565 /* 45803 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17566 /* 45803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
17567 /* 45806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17568 /* 45808 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17569 /* 45810 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17570 /* 45813 */ GIR_RootConstrainSelectedInstOperands,
17571 /* 45814 */ // GIR_Coverage, 1147,
17572 /* 45814 */ GIR_EraseRootFromParent_Done,
17573 /* 45815 */ // Label 1284: @45815
17574 /* 45815 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(45853),
17575 /* 45820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17576 /* 45824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1286*/ GIMT_Encode4(45838), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 68 //
17577 /* 45831 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17578 /* 45831 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
17579 /* 45836 */ GIR_RootConstrainSelectedInstOperands,
17580 /* 45837 */ // GIR_Coverage, 68,
17581 /* 45837 */ GIR_Done,
17582 /* 45838 */ // Label 1286: @45838
17583 /* 45838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(45852), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1148 //
17584 /* 45845 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17585 /* 45845 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
17586 /* 45850 */ GIR_RootConstrainSelectedInstOperands,
17587 /* 45851 */ // GIR_Coverage, 1148,
17588 /* 45851 */ GIR_Done,
17589 /* 45852 */ // Label 1287: @45852
17590 /* 45852 */ GIM_Reject,
17591 /* 45853 */ // Label 1285: @45853
17592 /* 45853 */ GIM_Reject,
17593 /* 45854 */ // Label 1282: @45854
17594 /* 45854 */ GIM_Reject,
17595 /* 45855 */ // Label 1280: @45855
17596 /* 45855 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(45992),
17597 /* 45860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17598 /* 45863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17599 /* 45866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17600 /* 45870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17601 /* 45874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1289*/ GIMT_Encode4(45907), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 277 //
17602 /* 45881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17603 /* 45885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17604 /* 45889 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17605 /* 45893 */ // MIs[1] Operand 1
17606 /* 45893 */ // No operand predicates
17607 /* 45893 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17608 /* 45895 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17609 /* 45895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
17610 /* 45898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17611 /* 45900 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17612 /* 45902 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17613 /* 45905 */ GIR_RootConstrainSelectedInstOperands,
17614 /* 45906 */ // GIR_Coverage, 277,
17615 /* 45906 */ GIR_EraseRootFromParent_Done,
17616 /* 45907 */ // Label 1289: @45907
17617 /* 45907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1290*/ GIMT_Encode4(45973), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1771 //
17618 /* 45914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17619 /* 45918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17620 /* 45922 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17621 /* 45926 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17622 /* 45931 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17623 /* 45933 */ // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17624 /* 45933 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17625 /* 45936 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17626 /* 45940 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17627 /* 45945 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17628 /* 45951 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17629 /* 45956 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17630 /* 45961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17631 /* 45964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17632 /* 45966 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17633 /* 45968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17634 /* 45971 */ GIR_RootConstrainSelectedInstOperands,
17635 /* 45972 */ // GIR_Coverage, 1771,
17636 /* 45972 */ GIR_EraseRootFromParent_Done,
17637 /* 45973 */ // Label 1290: @45973
17638 /* 45973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1291*/ GIMT_Encode4(45991), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 278 //
17639 /* 45980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17640 /* 45984 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17641 /* 45984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17642 /* 45989 */ GIR_RootConstrainSelectedInstOperands,
17643 /* 45990 */ // GIR_Coverage, 278,
17644 /* 45990 */ GIR_Done,
17645 /* 45991 */ // Label 1291: @45991
17646 /* 45991 */ GIM_Reject,
17647 /* 45992 */ // Label 1288: @45992
17648 /* 45992 */ GIM_Reject,
17649 /* 45993 */ // Label 1281: @45993
17650 /* 45993 */ GIM_Reject,
17651 /* 45994 */ // Label 42: @45994
17652 /* 45994 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(48487),
17653 /* 45999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17654 /* 46002 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1295*/ GIMT_Encode4(48486),
17655 /* 46013 */ /*GILLT_s32*//*Label 1293*/ GIMT_Encode4(46021),
17656 /* 46017 */ /*GILLT_s64*//*Label 1294*/ GIMT_Encode4(47948),
17657 /* 46021 */ // Label 1293: @46021
17658 /* 46021 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(47947),
17659 /* 46026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17660 /* 46029 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(46259),
17661 /* 46034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17662 /* 46038 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(46191),
17663 /* 46043 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17664 /* 46048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17665 /* 46052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1299*/ GIMT_Encode4(46121), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit), // Rule ID 1597 //
17666 /* 46059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17667 /* 46063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
17668 /* 46067 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17669 /* 46071 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17670 /* 46075 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17671 /* 46079 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
17672 /* 46083 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
17673 /* 46088 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17674 /* 46090 */ // (setcc:{ *:[i32] } (bitconvert:{ *:[i32] } (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)), 0:{ *:[i32] }, SETLT:{ *:[Other] }) => (SLTi:{ *:[i32] } (MFHC1_D32:{ *:[i32] } AFGR64Opnd:{ *:[f64] }:$src), 0:{ *:[i32] })
17675 /* 46090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17676 /* 46093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::MFHC1_D32),
17677 /* 46097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17678 /* 46102 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src
17679 /* 46106 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17680 /* 46108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTi),
17681 /* 46111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17682 /* 46113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17683 /* 46116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17684 /* 46119 */ GIR_RootConstrainSelectedInstOperands,
17685 /* 46120 */ // GIR_Coverage, 1597,
17686 /* 46120 */ GIR_EraseRootFromParent_Done,
17687 /* 46121 */ // Label 1299: @46121
17688 /* 46121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1300*/ GIMT_Encode4(46190), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat), // Rule ID 1598 //
17689 /* 46128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17690 /* 46132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
17691 /* 46136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17692 /* 46140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17693 /* 46144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17694 /* 46148 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
17695 /* 46152 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17696 /* 46157 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17697 /* 46159 */ // (setcc:{ *:[i32] } (bitconvert:{ *:[i32] } (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)), 0:{ *:[i32] }, SETLT:{ *:[Other] }) => (SLTi:{ *:[i32] } (MFHC1_D64:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$src), 0:{ *:[i32] })
17698 /* 46159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17699 /* 46162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::MFHC1_D64),
17700 /* 46166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17701 /* 46171 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src
17702 /* 46175 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17703 /* 46177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTi),
17704 /* 46180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17705 /* 46182 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17706 /* 46185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17707 /* 46188 */ GIR_RootConstrainSelectedInstOperands,
17708 /* 46189 */ // GIR_Coverage, 1598,
17709 /* 46189 */ GIR_EraseRootFromParent_Done,
17710 /* 46190 */ // Label 1300: @46190
17711 /* 46190 */ GIM_Reject,
17712 /* 46191 */ // Label 1298: @46191
17713 /* 46191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1301*/ GIMT_Encode4(46223), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1500 //
17714 /* 46198 */ // MIs[0] Operand 1
17715 /* 46198 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17716 /* 46203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17717 /* 46207 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17718 /* 46211 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17719 /* 46211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
17720 /* 46214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17721 /* 46216 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17722 /* 46218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17723 /* 46221 */ GIR_RootConstrainSelectedInstOperands,
17724 /* 46222 */ // GIR_Coverage, 1500,
17725 /* 46222 */ GIR_EraseRootFromParent_Done,
17726 /* 46223 */ // Label 1301: @46223
17727 /* 46223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1302*/ GIMT_Encode4(46258), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1501 //
17728 /* 46230 */ // MIs[0] Operand 1
17729 /* 46230 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17730 /* 46235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17731 /* 46239 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17732 /* 46243 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17733 /* 46243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17734 /* 46246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17735 /* 46248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17736 /* 46254 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17737 /* 46256 */ GIR_RootConstrainSelectedInstOperands,
17738 /* 46257 */ // GIR_Coverage, 1501,
17739 /* 46257 */ GIR_EraseRootFromParent_Done,
17740 /* 46258 */ // Label 1302: @46258
17741 /* 46258 */ GIM_Reject,
17742 /* 46259 */ // Label 1297: @46259
17743 /* 46259 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(46386),
17744 /* 46264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17745 /* 46268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1304*/ GIMT_Encode4(46300), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2134 //
17746 /* 46275 */ // MIs[0] Operand 1
17747 /* 46275 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17748 /* 46280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17749 /* 46284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17750 /* 46288 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17751 /* 46288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17752 /* 46291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17753 /* 46293 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17754 /* 46295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17755 /* 46298 */ GIR_RootConstrainSelectedInstOperands,
17756 /* 46299 */ // GIR_Coverage, 2134,
17757 /* 46299 */ GIR_EraseRootFromParent_Done,
17758 /* 46300 */ // Label 1304: @46300
17759 /* 46300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(46385), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2136 //
17760 /* 46307 */ // MIs[0] Operand 1
17761 /* 46307 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17762 /* 46312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17763 /* 46316 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709518847u),
17764 /* 46327 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17765 /* 46327 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17766 /* 46330 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17767 /* 46334 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17768 /* 46339 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17769 /* 46342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17770 /* 46344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17771 /* 46347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
17772 /* 46351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17773 /* 46356 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17774 /* 46360 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
17775 /* 46370 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17776 /* 46372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17777 /* 46375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17778 /* 46377 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17779 /* 46380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17780 /* 46383 */ GIR_RootConstrainSelectedInstOperands,
17781 /* 46384 */ // GIR_Coverage, 2136,
17782 /* 46384 */ GIR_EraseRootFromParent_Done,
17783 /* 46385 */ // Label 1305: @46385
17784 /* 46385 */ GIM_Reject,
17785 /* 46386 */ // Label 1303: @46386
17786 /* 46386 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(46525),
17787 /* 46391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17788 /* 46395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1307*/ GIMT_Encode4(46427), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2476 //
17789 /* 46402 */ // MIs[0] Operand 1
17790 /* 46402 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17791 /* 46407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17792 /* 46411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17793 /* 46415 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17794 /* 46415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
17795 /* 46418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17796 /* 46420 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17797 /* 46422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17798 /* 46425 */ GIR_RootConstrainSelectedInstOperands,
17799 /* 46426 */ // GIR_Coverage, 2476,
17800 /* 46426 */ GIR_EraseRootFromParent_Done,
17801 /* 46427 */ // Label 1307: @46427
17802 /* 46427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1308*/ GIMT_Encode4(46462), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2477 //
17803 /* 46434 */ // MIs[0] Operand 1
17804 /* 46434 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17805 /* 46439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17806 /* 46443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17807 /* 46447 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17808 /* 46447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17809 /* 46450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17810 /* 46452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17811 /* 46458 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17812 /* 46460 */ GIR_RootConstrainSelectedInstOperands,
17813 /* 46461 */ // GIR_Coverage, 2477,
17814 /* 46461 */ GIR_EraseRootFromParent_Done,
17815 /* 46462 */ // Label 1308: @46462
17816 /* 46462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1309*/ GIMT_Encode4(46493), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 49 //
17817 /* 46469 */ // MIs[0] Operand 1
17818 /* 46469 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17819 /* 46474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17820 /* 46478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17821 /* 46482 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17822 /* 46482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17823 /* 46485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17824 /* 46487 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17825 /* 46489 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17826 /* 46491 */ GIR_RootConstrainSelectedInstOperands,
17827 /* 46492 */ // GIR_Coverage, 49,
17828 /* 46492 */ GIR_EraseRootFromParent_Done,
17829 /* 46493 */ // Label 1309: @46493
17830 /* 46493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1310*/ GIMT_Encode4(46524), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 50 //
17831 /* 46500 */ // MIs[0] Operand 1
17832 /* 46500 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
17833 /* 46505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17834 /* 46509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17835 /* 46513 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17836 /* 46513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17837 /* 46516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17838 /* 46518 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17839 /* 46520 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17840 /* 46522 */ GIR_RootConstrainSelectedInstOperands,
17841 /* 46523 */ // GIR_Coverage, 50,
17842 /* 46523 */ GIR_EraseRootFromParent_Done,
17843 /* 46524 */ // Label 1310: @46524
17844 /* 46524 */ GIM_Reject,
17845 /* 46525 */ // Label 1306: @46525
17846 /* 46525 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(46992),
17847 /* 46530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17848 /* 46534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1312*/ GIMT_Encode4(46565), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1141 //
17849 /* 46541 */ // MIs[0] Operand 1
17850 /* 46541 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17851 /* 46546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17852 /* 46550 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17853 /* 46554 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17854 /* 46554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
17855 /* 46557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17856 /* 46559 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17857 /* 46561 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17858 /* 46563 */ GIR_RootConstrainSelectedInstOperands,
17859 /* 46564 */ // GIR_Coverage, 1141,
17860 /* 46564 */ GIR_EraseRootFromParent_Done,
17861 /* 46565 */ // Label 1312: @46565
17862 /* 46565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1313*/ GIMT_Encode4(46596), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1142 //
17863 /* 46572 */ // MIs[0] Operand 1
17864 /* 46572 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
17865 /* 46577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17866 /* 46581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17867 /* 46585 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17868 /* 46585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17869 /* 46588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17870 /* 46590 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17871 /* 46592 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17872 /* 46594 */ GIR_RootConstrainSelectedInstOperands,
17873 /* 46595 */ // GIR_Coverage, 1142,
17874 /* 46595 */ GIR_EraseRootFromParent_Done,
17875 /* 46596 */ // Label 1313: @46596
17876 /* 46596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1314*/ GIMT_Encode4(46651), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1502 //
17877 /* 46603 */ // MIs[0] Operand 1
17878 /* 46603 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17879 /* 46608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17880 /* 46612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17881 /* 46616 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17882 /* 46616 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17883 /* 46619 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
17884 /* 46623 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17885 /* 46628 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17886 /* 46632 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17887 /* 46636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17888 /* 46638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
17889 /* 46641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17890 /* 46643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17891 /* 46646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17892 /* 46649 */ GIR_RootConstrainSelectedInstOperands,
17893 /* 46650 */ // GIR_Coverage, 1502,
17894 /* 46650 */ GIR_EraseRootFromParent_Done,
17895 /* 46651 */ // Label 1314: @46651
17896 /* 46651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1315*/ GIMT_Encode4(46709), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1503 //
17897 /* 46658 */ // MIs[0] Operand 1
17898 /* 46658 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17899 /* 46663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17900 /* 46667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17901 /* 46671 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } R0:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
17902 /* 46671 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17903 /* 46674 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
17904 /* 46678 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17905 /* 46683 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17906 /* 46687 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17907 /* 46691 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17908 /* 46693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17909 /* 46696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17910 /* 46698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17911 /* 46704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17912 /* 46707 */ GIR_RootConstrainSelectedInstOperands,
17913 /* 46708 */ // GIR_Coverage, 1503,
17914 /* 46708 */ GIR_EraseRootFromParent_Done,
17915 /* 46709 */ // Label 1315: @46709
17916 /* 46709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1316*/ GIMT_Encode4(46764), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1504 //
17917 /* 46716 */ // MIs[0] Operand 1
17918 /* 46716 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17919 /* 46721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17920 /* 46725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17921 /* 46729 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17922 /* 46729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17923 /* 46732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
17924 /* 46736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17925 /* 46741 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17926 /* 46745 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17927 /* 46749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17928 /* 46751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17929 /* 46754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17930 /* 46756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17931 /* 46759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17932 /* 46762 */ GIR_RootConstrainSelectedInstOperands,
17933 /* 46763 */ // GIR_Coverage, 1504,
17934 /* 46763 */ GIR_EraseRootFromParent_Done,
17935 /* 46764 */ // Label 1316: @46764
17936 /* 46764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(46819), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1505 //
17937 /* 46771 */ // MIs[0] Operand 1
17938 /* 46771 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17939 /* 46776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17940 /* 46780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17941 /* 46784 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17942 /* 46784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17943 /* 46787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17944 /* 46791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17945 /* 46796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17946 /* 46800 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17947 /* 46804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17948 /* 46806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17949 /* 46809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17950 /* 46811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17951 /* 46814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17952 /* 46817 */ GIR_RootConstrainSelectedInstOperands,
17953 /* 46818 */ // GIR_Coverage, 1505,
17954 /* 46818 */ GIR_EraseRootFromParent_Done,
17955 /* 46819 */ // Label 1317: @46819
17956 /* 46819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1318*/ GIMT_Encode4(46850), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1506 //
17957 /* 46826 */ // MIs[0] Operand 1
17958 /* 46826 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17959 /* 46831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17960 /* 46835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17961 /* 46839 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17962 /* 46839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17963 /* 46842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17964 /* 46844 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17965 /* 46846 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17966 /* 46848 */ GIR_RootConstrainSelectedInstOperands,
17967 /* 46849 */ // GIR_Coverage, 1506,
17968 /* 46849 */ GIR_EraseRootFromParent_Done,
17969 /* 46850 */ // Label 1318: @46850
17970 /* 46850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1319*/ GIMT_Encode4(46881), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1507 //
17971 /* 46857 */ // MIs[0] Operand 1
17972 /* 46857 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17973 /* 46862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17974 /* 46866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17975 /* 46870 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17976 /* 46870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17977 /* 46873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17978 /* 46875 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17979 /* 46877 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17980 /* 46879 */ GIR_RootConstrainSelectedInstOperands,
17981 /* 46880 */ // GIR_Coverage, 1507,
17982 /* 46880 */ GIR_EraseRootFromParent_Done,
17983 /* 46881 */ // Label 1319: @46881
17984 /* 46881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1320*/ GIMT_Encode4(46936), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1508 //
17985 /* 46888 */ // MIs[0] Operand 1
17986 /* 46888 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17987 /* 46893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17988 /* 46897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17989 /* 46901 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17990 /* 46901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17991 /* 46904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
17992 /* 46908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17993 /* 46913 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17994 /* 46917 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17995 /* 46921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17996 /* 46923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17997 /* 46926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17998 /* 46928 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17999 /* 46931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18000 /* 46934 */ GIR_RootConstrainSelectedInstOperands,
18001 /* 46935 */ // GIR_Coverage, 1508,
18002 /* 46935 */ GIR_EraseRootFromParent_Done,
18003 /* 46936 */ // Label 1320: @46936
18004 /* 46936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1321*/ GIMT_Encode4(46991), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1509 //
18005 /* 46943 */ // MIs[0] Operand 1
18006 /* 46943 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18007 /* 46948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18008 /* 46952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18009 /* 46956 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18010 /* 46956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18011 /* 46959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18012 /* 46963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18013 /* 46968 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18014 /* 46972 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18015 /* 46976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18016 /* 46978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18017 /* 46981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18018 /* 46983 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18019 /* 46986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18020 /* 46989 */ GIR_RootConstrainSelectedInstOperands,
18021 /* 46990 */ // GIR_Coverage, 1509,
18022 /* 46990 */ GIR_EraseRootFromParent_Done,
18023 /* 46991 */ // Label 1321: @46991
18024 /* 46991 */ GIM_Reject,
18025 /* 46992 */ // Label 1311: @46992
18026 /* 46992 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(47541),
18027 /* 46997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18028 /* 47001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(47056), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2133 //
18029 /* 47008 */ // MIs[0] Operand 1
18030 /* 47008 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18031 /* 47013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18032 /* 47017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18033 /* 47021 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18034 /* 47021 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18035 /* 47024 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18036 /* 47028 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18037 /* 47033 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18038 /* 47037 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18039 /* 47041 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18040 /* 47043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
18041 /* 47046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18042 /* 47048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18043 /* 47051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18044 /* 47054 */ GIR_RootConstrainSelectedInstOperands,
18045 /* 47055 */ // GIR_Coverage, 2133,
18046 /* 47055 */ GIR_EraseRootFromParent_Done,
18047 /* 47056 */ // Label 1323: @47056
18048 /* 47056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1324*/ GIMT_Encode4(47128), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2135 //
18049 /* 47063 */ // MIs[0] Operand 1
18050 /* 47063 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18051 /* 47068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18052 /* 47072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18053 /* 47076 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18054 /* 47076 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18055 /* 47079 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18056 /* 47083 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18057 /* 47088 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18058 /* 47091 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18059 /* 47093 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18060 /* 47096 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18061 /* 47100 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18062 /* 47105 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18063 /* 47109 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18064 /* 47113 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18065 /* 47115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18066 /* 47118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18067 /* 47120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18068 /* 47123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18069 /* 47126 */ GIR_RootConstrainSelectedInstOperands,
18070 /* 47127 */ // GIR_Coverage, 2135,
18071 /* 47127 */ GIR_EraseRootFromParent_Done,
18072 /* 47128 */ // Label 1324: @47128
18073 /* 47128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1325*/ GIMT_Encode4(47159), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2137 //
18074 /* 47135 */ // MIs[0] Operand 1
18075 /* 47135 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18076 /* 47140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18077 /* 47144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18078 /* 47148 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
18079 /* 47148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18080 /* 47151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18081 /* 47153 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18082 /* 47155 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18083 /* 47157 */ GIR_RootConstrainSelectedInstOperands,
18084 /* 47158 */ // GIR_Coverage, 2137,
18085 /* 47158 */ GIR_EraseRootFromParent_Done,
18086 /* 47159 */ // Label 1325: @47159
18087 /* 47159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1326*/ GIMT_Encode4(47231), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2138 //
18088 /* 47166 */ // MIs[0] Operand 1
18089 /* 47166 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18090 /* 47171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18091 /* 47175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18092 /* 47179 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
18093 /* 47179 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18094 /* 47182 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
18095 /* 47186 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18096 /* 47191 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18097 /* 47194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18098 /* 47196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18099 /* 47199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18100 /* 47203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18101 /* 47208 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18102 /* 47212 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18103 /* 47216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18104 /* 47218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18105 /* 47221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18106 /* 47223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18107 /* 47226 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18108 /* 47229 */ GIR_RootConstrainSelectedInstOperands,
18109 /* 47230 */ // GIR_Coverage, 2138,
18110 /* 47230 */ GIR_EraseRootFromParent_Done,
18111 /* 47231 */ // Label 1326: @47231
18112 /* 47231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1327*/ GIMT_Encode4(47262), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2139 //
18113 /* 47238 */ // MIs[0] Operand 1
18114 /* 47238 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18115 /* 47243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18116 /* 47247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18117 /* 47251 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
18118 /* 47251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
18119 /* 47254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18120 /* 47256 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
18121 /* 47258 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
18122 /* 47260 */ GIR_RootConstrainSelectedInstOperands,
18123 /* 47261 */ // GIR_Coverage, 2139,
18124 /* 47261 */ GIR_EraseRootFromParent_Done,
18125 /* 47262 */ // Label 1327: @47262
18126 /* 47262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1328*/ GIMT_Encode4(47334), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2141 //
18127 /* 47269 */ // MIs[0] Operand 1
18128 /* 47269 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18129 /* 47274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18130 /* 47278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18131 /* 47282 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
18132 /* 47282 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18133 /* 47285 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18134 /* 47289 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18135 /* 47294 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18136 /* 47298 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18137 /* 47302 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18138 /* 47304 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18139 /* 47307 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18140 /* 47311 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18141 /* 47316 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
18142 /* 47319 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18143 /* 47321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18144 /* 47324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18145 /* 47326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18146 /* 47329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18147 /* 47332 */ GIR_RootConstrainSelectedInstOperands,
18148 /* 47333 */ // GIR_Coverage, 2141,
18149 /* 47333 */ GIR_EraseRootFromParent_Done,
18150 /* 47334 */ // Label 1328: @47334
18151 /* 47334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(47406), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2142 //
18152 /* 47341 */ // MIs[0] Operand 1
18153 /* 47341 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18154 /* 47346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18155 /* 47350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18156 /* 47354 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18157 /* 47354 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18158 /* 47357 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18159 /* 47361 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18160 /* 47366 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18161 /* 47369 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18162 /* 47371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18163 /* 47374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18164 /* 47378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18165 /* 47383 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18166 /* 47387 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18167 /* 47391 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18168 /* 47393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18169 /* 47396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18170 /* 47398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18171 /* 47401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18172 /* 47404 */ GIR_RootConstrainSelectedInstOperands,
18173 /* 47405 */ // GIR_Coverage, 2142,
18174 /* 47405 */ GIR_EraseRootFromParent_Done,
18175 /* 47406 */ // Label 1329: @47406
18176 /* 47406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1330*/ GIMT_Encode4(47437), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2143 //
18177 /* 47413 */ // MIs[0] Operand 1
18178 /* 47413 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18179 /* 47418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18180 /* 47422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18181 /* 47426 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
18182 /* 47426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18183 /* 47429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18184 /* 47431 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18185 /* 47433 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18186 /* 47435 */ GIR_RootConstrainSelectedInstOperands,
18187 /* 47436 */ // GIR_Coverage, 2143,
18188 /* 47436 */ GIR_EraseRootFromParent_Done,
18189 /* 47437 */ // Label 1330: @47437
18190 /* 47437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1331*/ GIMT_Encode4(47509), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2144 //
18191 /* 47444 */ // MIs[0] Operand 1
18192 /* 47444 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18193 /* 47449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18194 /* 47453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18195 /* 47457 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18196 /* 47457 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18197 /* 47460 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18198 /* 47464 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18199 /* 47469 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18200 /* 47472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18201 /* 47474 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18202 /* 47477 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18203 /* 47481 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18204 /* 47486 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18205 /* 47490 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18206 /* 47494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18207 /* 47496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18208 /* 47499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18209 /* 47501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18210 /* 47504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18211 /* 47507 */ GIR_RootConstrainSelectedInstOperands,
18212 /* 47508 */ // GIR_Coverage, 2144,
18213 /* 47508 */ GIR_EraseRootFromParent_Done,
18214 /* 47509 */ // Label 1331: @47509
18215 /* 47509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1332*/ GIMT_Encode4(47540), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2145 //
18216 /* 47516 */ // MIs[0] Operand 1
18217 /* 47516 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18218 /* 47521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18219 /* 47525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18220 /* 47529 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
18221 /* 47529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18222 /* 47532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18223 /* 47534 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
18224 /* 47536 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
18225 /* 47538 */ GIR_RootConstrainSelectedInstOperands,
18226 /* 47539 */ // GIR_Coverage, 2145,
18227 /* 47539 */ GIR_EraseRootFromParent_Done,
18228 /* 47540 */ // Label 1332: @47540
18229 /* 47540 */ GIM_Reject,
18230 /* 47541 */ // Label 1322: @47541
18231 /* 47541 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(47946),
18232 /* 47546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18233 /* 47550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1334*/ GIMT_Encode4(47605), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2478 //
18234 /* 47557 */ // MIs[0] Operand 1
18235 /* 47557 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18236 /* 47562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18237 /* 47566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18238 /* 47570 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18239 /* 47570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18240 /* 47573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18241 /* 47577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18242 /* 47582 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18243 /* 47586 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18244 /* 47590 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18245 /* 47592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
18246 /* 47595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18247 /* 47597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18248 /* 47600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18249 /* 47603 */ GIR_RootConstrainSelectedInstOperands,
18250 /* 47604 */ // GIR_Coverage, 2478,
18251 /* 47604 */ GIR_EraseRootFromParent_Done,
18252 /* 47605 */ // Label 1334: @47605
18253 /* 47605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1335*/ GIMT_Encode4(47663), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2479 //
18254 /* 47612 */ // MIs[0] Operand 1
18255 /* 47612 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18256 /* 47617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18257 /* 47621 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18258 /* 47625 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } R0:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18259 /* 47625 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18260 /* 47628 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18261 /* 47632 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18262 /* 47637 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18263 /* 47641 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18264 /* 47645 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18265 /* 47647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18266 /* 47650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18267 /* 47652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18268 /* 47658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18269 /* 47661 */ GIR_RootConstrainSelectedInstOperands,
18270 /* 47662 */ // GIR_Coverage, 2479,
18271 /* 47662 */ GIR_EraseRootFromParent_Done,
18272 /* 47663 */ // Label 1335: @47663
18273 /* 47663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1336*/ GIMT_Encode4(47718), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2480 //
18274 /* 47670 */ // MIs[0] Operand 1
18275 /* 47670 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18276 /* 47675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18277 /* 47679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18278 /* 47683 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18279 /* 47683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18280 /* 47686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18281 /* 47690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18282 /* 47695 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18283 /* 47699 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18284 /* 47703 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18285 /* 47705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18286 /* 47708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18287 /* 47710 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18288 /* 47713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18289 /* 47716 */ GIR_RootConstrainSelectedInstOperands,
18290 /* 47717 */ // GIR_Coverage, 2480,
18291 /* 47717 */ GIR_EraseRootFromParent_Done,
18292 /* 47718 */ // Label 1336: @47718
18293 /* 47718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(47773), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2481 //
18294 /* 47725 */ // MIs[0] Operand 1
18295 /* 47725 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18296 /* 47730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18297 /* 47734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18298 /* 47738 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18299 /* 47738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18300 /* 47741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18301 /* 47745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18302 /* 47750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18303 /* 47754 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18304 /* 47758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18305 /* 47760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18306 /* 47763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18307 /* 47765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18308 /* 47768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18309 /* 47771 */ GIR_RootConstrainSelectedInstOperands,
18310 /* 47772 */ // GIR_Coverage, 2481,
18311 /* 47772 */ GIR_EraseRootFromParent_Done,
18312 /* 47773 */ // Label 1337: @47773
18313 /* 47773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(47804), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2482 //
18314 /* 47780 */ // MIs[0] Operand 1
18315 /* 47780 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18316 /* 47785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18317 /* 47789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18318 /* 47793 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18319 /* 47793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18320 /* 47796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18321 /* 47798 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18322 /* 47800 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18323 /* 47802 */ GIR_RootConstrainSelectedInstOperands,
18324 /* 47803 */ // GIR_Coverage, 2482,
18325 /* 47803 */ GIR_EraseRootFromParent_Done,
18326 /* 47804 */ // Label 1338: @47804
18327 /* 47804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(47835), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2483 //
18328 /* 47811 */ // MIs[0] Operand 1
18329 /* 47811 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18330 /* 47816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18331 /* 47820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18332 /* 47824 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18333 /* 47824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18334 /* 47827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18335 /* 47829 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18336 /* 47831 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18337 /* 47833 */ GIR_RootConstrainSelectedInstOperands,
18338 /* 47834 */ // GIR_Coverage, 2483,
18339 /* 47834 */ GIR_EraseRootFromParent_Done,
18340 /* 47835 */ // Label 1339: @47835
18341 /* 47835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1340*/ GIMT_Encode4(47890), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2484 //
18342 /* 47842 */ // MIs[0] Operand 1
18343 /* 47842 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18344 /* 47847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18345 /* 47851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18346 /* 47855 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18347 /* 47855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18348 /* 47858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18349 /* 47862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18350 /* 47867 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18351 /* 47871 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18352 /* 47875 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18353 /* 47877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18354 /* 47880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18355 /* 47882 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18356 /* 47885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18357 /* 47888 */ GIR_RootConstrainSelectedInstOperands,
18358 /* 47889 */ // GIR_Coverage, 2484,
18359 /* 47889 */ GIR_EraseRootFromParent_Done,
18360 /* 47890 */ // Label 1340: @47890
18361 /* 47890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(47945), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2485 //
18362 /* 47897 */ // MIs[0] Operand 1
18363 /* 47897 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18364 /* 47902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18365 /* 47906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18366 /* 47910 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18367 /* 47910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18368 /* 47913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18369 /* 47917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18370 /* 47922 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18371 /* 47926 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18372 /* 47930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18373 /* 47932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18374 /* 47935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18375 /* 47937 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18376 /* 47940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18377 /* 47943 */ GIR_RootConstrainSelectedInstOperands,
18378 /* 47944 */ // GIR_Coverage, 2485,
18379 /* 47944 */ GIR_EraseRootFromParent_Done,
18380 /* 47945 */ // Label 1341: @47945
18381 /* 47945 */ GIM_Reject,
18382 /* 47946 */ // Label 1333: @47946
18383 /* 47946 */ GIM_Reject,
18384 /* 47947 */ // Label 1296: @47947
18385 /* 47947 */ GIM_Reject,
18386 /* 47948 */ // Label 1294: @47948
18387 /* 47948 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(48485),
18388 /* 47953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18389 /* 47956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18390 /* 47960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(47992), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1753 //
18391 /* 47967 */ // MIs[0] Operand 1
18392 /* 47967 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18393 /* 47972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18394 /* 47976 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18395 /* 47980 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
18396 /* 47980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18397 /* 47983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18398 /* 47985 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18399 /* 47987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18400 /* 47990 */ GIR_RootConstrainSelectedInstOperands,
18401 /* 47991 */ // GIR_Coverage, 1753,
18402 /* 47991 */ GIR_EraseRootFromParent_Done,
18403 /* 47992 */ // Label 1343: @47992
18404 /* 47992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(48027), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1754 //
18405 /* 47999 */ // MIs[0] Operand 1
18406 /* 47999 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18407 /* 48004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18408 /* 48008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18409 /* 48012 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } R0_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
18410 /* 48012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18411 /* 48015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18412 /* 48017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18413 /* 48023 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18414 /* 48025 */ GIR_RootConstrainSelectedInstOperands,
18415 /* 48026 */ // GIR_Coverage, 1754,
18416 /* 48026 */ GIR_EraseRootFromParent_Done,
18417 /* 48027 */ // Label 1344: @48027
18418 /* 48027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(48058), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 259 //
18419 /* 48034 */ // MIs[0] Operand 1
18420 /* 48034 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18421 /* 48039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18422 /* 48043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18423 /* 48047 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18424 /* 48047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18425 /* 48050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18426 /* 48052 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18427 /* 48054 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18428 /* 48056 */ GIR_RootConstrainSelectedInstOperands,
18429 /* 48057 */ // GIR_Coverage, 259,
18430 /* 48057 */ GIR_EraseRootFromParent_Done,
18431 /* 48058 */ // Label 1345: @48058
18432 /* 48058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(48089), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 260 //
18433 /* 48065 */ // MIs[0] Operand 1
18434 /* 48065 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18435 /* 48070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18436 /* 48074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18437 /* 48078 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18438 /* 48078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18439 /* 48081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18440 /* 48083 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18441 /* 48085 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18442 /* 48087 */ GIR_RootConstrainSelectedInstOperands,
18443 /* 48088 */ // GIR_Coverage, 260,
18444 /* 48088 */ GIR_EraseRootFromParent_Done,
18445 /* 48089 */ // Label 1346: @48089
18446 /* 48089 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(48144), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1755 //
18447 /* 48096 */ // MIs[0] Operand 1
18448 /* 48096 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18449 /* 48101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18450 /* 48105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18451 /* 48109 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
18452 /* 48109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18453 /* 48112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18454 /* 48116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18455 /* 48121 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18456 /* 48125 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18457 /* 48129 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18458 /* 48131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18459 /* 48134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18460 /* 48136 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18461 /* 48139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18462 /* 48142 */ GIR_RootConstrainSelectedInstOperands,
18463 /* 48143 */ // GIR_Coverage, 1755,
18464 /* 48143 */ GIR_EraseRootFromParent_Done,
18465 /* 48144 */ // Label 1347: @48144
18466 /* 48144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(48202), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1756 //
18467 /* 48151 */ // MIs[0] Operand 1
18468 /* 48151 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18469 /* 48156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18470 /* 48160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18471 /* 48164 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } R0_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
18472 /* 48164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18473 /* 48167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18474 /* 48171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18475 /* 48176 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18476 /* 48180 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18477 /* 48184 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18478 /* 48186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18479 /* 48189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18480 /* 48191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::R0_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18481 /* 48197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18482 /* 48200 */ GIR_RootConstrainSelectedInstOperands,
18483 /* 48201 */ // GIR_Coverage, 1756,
18484 /* 48201 */ GIR_EraseRootFromParent_Done,
18485 /* 48202 */ // Label 1348: @48202
18486 /* 48202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(48257), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1757 //
18487 /* 48209 */ // MIs[0] Operand 1
18488 /* 48209 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18489 /* 48214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18490 /* 48218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18491 /* 48222 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18492 /* 48222 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18493 /* 48225 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18494 /* 48229 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18495 /* 48234 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18496 /* 48238 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18497 /* 48242 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18498 /* 48244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18499 /* 48247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18500 /* 48249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18501 /* 48252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18502 /* 48255 */ GIR_RootConstrainSelectedInstOperands,
18503 /* 48256 */ // GIR_Coverage, 1757,
18504 /* 48256 */ GIR_EraseRootFromParent_Done,
18505 /* 48257 */ // Label 1349: @48257
18506 /* 48257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(48312), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1758 //
18507 /* 48264 */ // MIs[0] Operand 1
18508 /* 48264 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18509 /* 48269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18510 /* 48273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18511 /* 48277 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18512 /* 48277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18513 /* 48280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18514 /* 48284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18515 /* 48289 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18516 /* 48293 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18517 /* 48297 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18518 /* 48299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18519 /* 48302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18520 /* 48304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18521 /* 48307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18522 /* 48310 */ GIR_RootConstrainSelectedInstOperands,
18523 /* 48311 */ // GIR_Coverage, 1758,
18524 /* 48311 */ GIR_EraseRootFromParent_Done,
18525 /* 48312 */ // Label 1350: @48312
18526 /* 48312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1351*/ GIMT_Encode4(48343), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1759 //
18527 /* 48319 */ // MIs[0] Operand 1
18528 /* 48319 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18529 /* 48324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18530 /* 48328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18531 /* 48332 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18532 /* 48332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18533 /* 48335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18534 /* 48337 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18535 /* 48339 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18536 /* 48341 */ GIR_RootConstrainSelectedInstOperands,
18537 /* 48342 */ // GIR_Coverage, 1759,
18538 /* 48342 */ GIR_EraseRootFromParent_Done,
18539 /* 48343 */ // Label 1351: @48343
18540 /* 48343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(48374), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1760 //
18541 /* 48350 */ // MIs[0] Operand 1
18542 /* 48350 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18543 /* 48355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18544 /* 48359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18545 /* 48363 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18546 /* 48363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18547 /* 48366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18548 /* 48368 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18549 /* 48370 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18550 /* 48372 */ GIR_RootConstrainSelectedInstOperands,
18551 /* 48373 */ // GIR_Coverage, 1760,
18552 /* 48373 */ GIR_EraseRootFromParent_Done,
18553 /* 48374 */ // Label 1352: @48374
18554 /* 48374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(48429), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1761 //
18555 /* 48381 */ // MIs[0] Operand 1
18556 /* 48381 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18557 /* 48386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18558 /* 48390 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18559 /* 48394 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18560 /* 48394 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18561 /* 48397 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18562 /* 48401 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18563 /* 48406 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18564 /* 48410 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18565 /* 48414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18566 /* 48416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18567 /* 48419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18568 /* 48421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18569 /* 48424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18570 /* 48427 */ GIR_RootConstrainSelectedInstOperands,
18571 /* 48428 */ // GIR_Coverage, 1761,
18572 /* 48428 */ GIR_EraseRootFromParent_Done,
18573 /* 48429 */ // Label 1353: @48429
18574 /* 48429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(48484), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1762 //
18575 /* 48436 */ // MIs[0] Operand 1
18576 /* 48436 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18577 /* 48441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18578 /* 48445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18579 /* 48449 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18580 /* 48449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18581 /* 48452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18582 /* 48456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18583 /* 48461 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18584 /* 48465 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18585 /* 48469 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18586 /* 48471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18587 /* 48474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18588 /* 48476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18589 /* 48479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18590 /* 48482 */ GIR_RootConstrainSelectedInstOperands,
18591 /* 48483 */ // GIR_Coverage, 1762,
18592 /* 48483 */ GIR_EraseRootFromParent_Done,
18593 /* 48484 */ // Label 1354: @48484
18594 /* 48484 */ GIM_Reject,
18595 /* 48485 */ // Label 1342: @48485
18596 /* 48485 */ GIM_Reject,
18597 /* 48486 */ // Label 1295: @48486
18598 /* 48486 */ GIM_Reject,
18599 /* 48487 */ // Label 1292: @48487
18600 /* 48487 */ GIM_Reject,
18601 /* 48488 */ // Label 43: @48488
18602 /* 48488 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(50014),
18603 /* 48493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18604 /* 48496 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1358*/ GIMT_Encode4(50013),
18605 /* 48507 */ /*GILLT_s32*//*Label 1356*/ GIMT_Encode4(48515),
18606 /* 48511 */ /*GILLT_s64*//*Label 1357*/ GIMT_Encode4(49201),
18607 /* 48515 */ // Label 1356: @48515
18608 /* 48515 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(49200),
18609 /* 48520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18610 /* 48523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18611 /* 48527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(48575), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1958 //
18612 /* 48534 */ // MIs[0] Operand 1
18613 /* 48534 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18614 /* 48539 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUO:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_UN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18615 /* 48539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18616 /* 48542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
18617 /* 48546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18618 /* 48551 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18619 /* 48555 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18620 /* 48559 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18621 /* 48561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18622 /* 48564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18623 /* 48566 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18624 /* 48569 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18625 /* 48574 */ // GIR_Coverage, 1958,
18626 /* 48574 */ GIR_EraseRootFromParent_Done,
18627 /* 48575 */ // Label 1360: @48575
18628 /* 48575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1361*/ GIMT_Encode4(48623), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1959 //
18629 /* 48582 */ // MIs[0] Operand 1
18630 /* 48582 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18631 /* 48587 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOEQ:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_EQ_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18632 /* 48587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18633 /* 48590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
18634 /* 48594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18635 /* 48599 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18636 /* 48603 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18637 /* 48607 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18638 /* 48609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18639 /* 48612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18640 /* 48614 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18641 /* 48617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18642 /* 48622 */ // GIR_Coverage, 1959,
18643 /* 48622 */ GIR_EraseRootFromParent_Done,
18644 /* 48623 */ // Label 1361: @48623
18645 /* 48623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(48671), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1960 //
18646 /* 48630 */ // MIs[0] Operand 1
18647 /* 48630 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18648 /* 48635 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUEQ:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_UEQ_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18649 /* 48635 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18650 /* 48638 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
18651 /* 48642 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18652 /* 48647 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18653 /* 48651 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18654 /* 48655 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18655 /* 48657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18656 /* 48660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18657 /* 48662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18658 /* 48665 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18659 /* 48670 */ // GIR_Coverage, 1960,
18660 /* 48670 */ GIR_EraseRootFromParent_Done,
18661 /* 48671 */ // Label 1362: @48671
18662 /* 48671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(48719), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1961 //
18663 /* 48678 */ // MIs[0] Operand 1
18664 /* 48678 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18665 /* 48683 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOLT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_LT_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18666 /* 48683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18667 /* 48686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
18668 /* 48690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18669 /* 48695 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18670 /* 48699 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18671 /* 48703 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18672 /* 48705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18673 /* 48708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18674 /* 48710 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18675 /* 48713 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18676 /* 48718 */ // GIR_Coverage, 1961,
18677 /* 48718 */ GIR_EraseRootFromParent_Done,
18678 /* 48719 */ // Label 1363: @48719
18679 /* 48719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1364*/ GIMT_Encode4(48767), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1962 //
18680 /* 48726 */ // MIs[0] Operand 1
18681 /* 48726 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18682 /* 48731 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETULT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_ULT_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18683 /* 48731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18684 /* 48734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
18685 /* 48738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18686 /* 48743 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18687 /* 48747 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18688 /* 48751 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18689 /* 48753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18690 /* 48756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18691 /* 48758 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18692 /* 48761 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18693 /* 48766 */ // GIR_Coverage, 1962,
18694 /* 48766 */ GIR_EraseRootFromParent_Done,
18695 /* 48767 */ // Label 1364: @48767
18696 /* 48767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(48815), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1963 //
18697 /* 48774 */ // MIs[0] Operand 1
18698 /* 48774 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18699 /* 48779 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOLE:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_LE_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18700 /* 48779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18701 /* 48782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
18702 /* 48786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18703 /* 48791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18704 /* 48795 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18705 /* 48799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18706 /* 48801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18707 /* 48804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18708 /* 48806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18709 /* 48809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18710 /* 48814 */ // GIR_Coverage, 1963,
18711 /* 48814 */ GIR_EraseRootFromParent_Done,
18712 /* 48815 */ // Label 1365: @48815
18713 /* 48815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1366*/ GIMT_Encode4(48863), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1964 //
18714 /* 48822 */ // MIs[0] Operand 1
18715 /* 48822 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18716 /* 48827 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETULE:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_ULE_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18717 /* 48827 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18718 /* 48830 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
18719 /* 48834 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18720 /* 48839 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18721 /* 48843 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18722 /* 48847 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18723 /* 48849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18724 /* 48852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18725 /* 48854 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18726 /* 48857 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18727 /* 48862 */ // GIR_Coverage, 1964,
18728 /* 48862 */ GIR_EraseRootFromParent_Done,
18729 /* 48863 */ // Label 1366: @48863
18730 /* 48863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1367*/ GIMT_Encode4(48911), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2596 //
18731 /* 48870 */ // MIs[0] Operand 1
18732 /* 48870 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18733 /* 48875 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUO:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18734 /* 48875 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18735 /* 48878 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
18736 /* 48882 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18737 /* 48887 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18738 /* 48891 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18739 /* 48895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18740 /* 48897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18741 /* 48900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18742 /* 48902 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18743 /* 48905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18744 /* 48910 */ // GIR_Coverage, 2596,
18745 /* 48910 */ GIR_EraseRootFromParent_Done,
18746 /* 48911 */ // Label 1367: @48911
18747 /* 48911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1368*/ GIMT_Encode4(48959), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2597 //
18748 /* 48918 */ // MIs[0] Operand 1
18749 /* 48918 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18750 /* 48923 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOEQ:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18751 /* 48923 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18752 /* 48926 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
18753 /* 48930 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18754 /* 48935 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18755 /* 48939 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18756 /* 48943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18757 /* 48945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18758 /* 48948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18759 /* 48950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18760 /* 48953 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18761 /* 48958 */ // GIR_Coverage, 2597,
18762 /* 48958 */ GIR_EraseRootFromParent_Done,
18763 /* 48959 */ // Label 1368: @48959
18764 /* 48959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1369*/ GIMT_Encode4(49007), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2598 //
18765 /* 48966 */ // MIs[0] Operand 1
18766 /* 48966 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18767 /* 48971 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUEQ:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18768 /* 48971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18769 /* 48974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
18770 /* 48978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18771 /* 48983 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18772 /* 48987 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18773 /* 48991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18774 /* 48993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18775 /* 48996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18776 /* 48998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18777 /* 49001 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18778 /* 49006 */ // GIR_Coverage, 2598,
18779 /* 49006 */ GIR_EraseRootFromParent_Done,
18780 /* 49007 */ // Label 1369: @49007
18781 /* 49007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1370*/ GIMT_Encode4(49055), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2599 //
18782 /* 49014 */ // MIs[0] Operand 1
18783 /* 49014 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18784 /* 49019 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOLT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_LT_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18785 /* 49019 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18786 /* 49022 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
18787 /* 49026 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18788 /* 49031 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18789 /* 49035 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18790 /* 49039 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18791 /* 49041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18792 /* 49044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18793 /* 49046 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18794 /* 49049 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18795 /* 49054 */ // GIR_Coverage, 2599,
18796 /* 49054 */ GIR_EraseRootFromParent_Done,
18797 /* 49055 */ // Label 1370: @49055
18798 /* 49055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1371*/ GIMT_Encode4(49103), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2600 //
18799 /* 49062 */ // MIs[0] Operand 1
18800 /* 49062 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18801 /* 49067 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETULT:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_ULT_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18802 /* 49067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18803 /* 49070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
18804 /* 49074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18805 /* 49079 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18806 /* 49083 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18807 /* 49087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18808 /* 49089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18809 /* 49092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18810 /* 49094 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18811 /* 49097 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18812 /* 49102 */ // GIR_Coverage, 2600,
18813 /* 49102 */ GIR_EraseRootFromParent_Done,
18814 /* 49103 */ // Label 1371: @49103
18815 /* 49103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1372*/ GIMT_Encode4(49151), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2601 //
18816 /* 49110 */ // MIs[0] Operand 1
18817 /* 49110 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18818 /* 49115 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETOLE:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_LE_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18819 /* 49115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18820 /* 49118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
18821 /* 49122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18822 /* 49127 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18823 /* 49131 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18824 /* 49135 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18825 /* 49137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18826 /* 49140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18827 /* 49142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18828 /* 49145 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18829 /* 49150 */ // GIR_Coverage, 2601,
18830 /* 49150 */ GIR_EraseRootFromParent_Done,
18831 /* 49151 */ // Label 1372: @49151
18832 /* 49151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1373*/ GIMT_Encode4(49199), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2602 //
18833 /* 49158 */ // MIs[0] Operand 1
18834 /* 49158 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18835 /* 49163 */ // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETULE:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (CMP_ULE_S_MMR6:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), FGR32:{ *:[i32] })
18836 /* 49163 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18837 /* 49166 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
18838 /* 49170 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18839 /* 49175 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18840 /* 49179 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18841 /* 49183 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18842 /* 49185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18843 /* 49188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18844 /* 49190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18845 /* 49193 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18846 /* 49198 */ // GIR_Coverage, 2602,
18847 /* 49198 */ GIR_EraseRootFromParent_Done,
18848 /* 49199 */ // Label 1373: @49199
18849 /* 49199 */ GIM_Reject,
18850 /* 49200 */ // Label 1359: @49200
18851 /* 49200 */ GIM_Reject,
18852 /* 49201 */ // Label 1357: @49201
18853 /* 49201 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(50012),
18854 /* 49206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18855 /* 49209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18856 /* 49213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1375*/ GIMT_Encode4(49270), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1970 //
18857 /* 49220 */ // MIs[0] Operand 1
18858 /* 49220 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18859 /* 49225 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_UN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18860 /* 49225 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18861 /* 49228 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
18862 /* 49232 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18863 /* 49237 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18864 /* 49241 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18865 /* 49245 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18866 /* 49247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18867 /* 49250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18868 /* 49252 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18869 /* 49259 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18870 /* 49264 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18871 /* 49269 */ // GIR_Coverage, 1970,
18872 /* 49269 */ GIR_EraseRootFromParent_Done,
18873 /* 49270 */ // Label 1375: @49270
18874 /* 49270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1376*/ GIMT_Encode4(49327), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1971 //
18875 /* 49277 */ // MIs[0] Operand 1
18876 /* 49277 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18877 /* 49282 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_EQ_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18878 /* 49282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18879 /* 49285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
18880 /* 49289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18881 /* 49294 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18882 /* 49298 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18883 /* 49302 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18884 /* 49304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18885 /* 49307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18886 /* 49309 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18887 /* 49316 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18888 /* 49321 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18889 /* 49326 */ // GIR_Coverage, 1971,
18890 /* 49326 */ GIR_EraseRootFromParent_Done,
18891 /* 49327 */ // Label 1376: @49327
18892 /* 49327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1377*/ GIMT_Encode4(49384), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1972 //
18893 /* 49334 */ // MIs[0] Operand 1
18894 /* 49334 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18895 /* 49339 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_UEQ_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18896 /* 49339 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18897 /* 49342 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
18898 /* 49346 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18899 /* 49351 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18900 /* 49355 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18901 /* 49359 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18902 /* 49361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18903 /* 49364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18904 /* 49366 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18905 /* 49373 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18906 /* 49378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18907 /* 49383 */ // GIR_Coverage, 1972,
18908 /* 49383 */ GIR_EraseRootFromParent_Done,
18909 /* 49384 */ // Label 1377: @49384
18910 /* 49384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1378*/ GIMT_Encode4(49441), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1973 //
18911 /* 49391 */ // MIs[0] Operand 1
18912 /* 49391 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18913 /* 49396 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_LT_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18914 /* 49396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18915 /* 49399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
18916 /* 49403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18917 /* 49408 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18918 /* 49412 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18919 /* 49416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18920 /* 49418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18921 /* 49421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18922 /* 49423 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18923 /* 49430 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18924 /* 49435 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18925 /* 49440 */ // GIR_Coverage, 1973,
18926 /* 49440 */ GIR_EraseRootFromParent_Done,
18927 /* 49441 */ // Label 1378: @49441
18928 /* 49441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1379*/ GIMT_Encode4(49498), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1974 //
18929 /* 49448 */ // MIs[0] Operand 1
18930 /* 49448 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18931 /* 49453 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_ULT_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18932 /* 49453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18933 /* 49456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
18934 /* 49460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18935 /* 49465 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18936 /* 49469 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18937 /* 49473 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18938 /* 49475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18939 /* 49478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18940 /* 49480 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18941 /* 49487 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18942 /* 49492 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18943 /* 49497 */ // GIR_Coverage, 1974,
18944 /* 49497 */ GIR_EraseRootFromParent_Done,
18945 /* 49498 */ // Label 1379: @49498
18946 /* 49498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1380*/ GIMT_Encode4(49555), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1975 //
18947 /* 49505 */ // MIs[0] Operand 1
18948 /* 49505 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18949 /* 49510 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOLE:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_LE_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18950 /* 49510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18951 /* 49513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
18952 /* 49517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18953 /* 49522 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18954 /* 49526 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18955 /* 49530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18956 /* 49532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18957 /* 49535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18958 /* 49537 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18959 /* 49544 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18960 /* 49549 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18961 /* 49554 */ // GIR_Coverage, 1975,
18962 /* 49554 */ GIR_EraseRootFromParent_Done,
18963 /* 49555 */ // Label 1380: @49555
18964 /* 49555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(49612), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1976 //
18965 /* 49562 */ // MIs[0] Operand 1
18966 /* 49562 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18967 /* 49567 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETULE:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_ULE_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18968 /* 49567 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18969 /* 49570 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
18970 /* 49574 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18971 /* 49579 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18972 /* 49583 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18973 /* 49587 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18974 /* 49589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18975 /* 49592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18976 /* 49594 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18977 /* 49601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18978 /* 49606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18979 /* 49611 */ // GIR_Coverage, 1976,
18980 /* 49611 */ GIR_EraseRootFromParent_Done,
18981 /* 49612 */ // Label 1381: @49612
18982 /* 49612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1382*/ GIMT_Encode4(49669), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2608 //
18983 /* 49619 */ // MIs[0] Operand 1
18984 /* 49619 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18985 /* 49624 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
18986 /* 49624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18987 /* 49627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
18988 /* 49631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18989 /* 49636 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18990 /* 49640 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18991 /* 49644 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18992 /* 49646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18993 /* 49649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
18994 /* 49651 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
18995 /* 49658 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
18996 /* 49663 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
18997 /* 49668 */ // GIR_Coverage, 2608,
18998 /* 49668 */ GIR_EraseRootFromParent_Done,
18999 /* 49669 */ // Label 1382: @49669
19000 /* 49669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1383*/ GIMT_Encode4(49726), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2609 //
19001 /* 49676 */ // MIs[0] Operand 1
19002 /* 49676 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19003 /* 49681 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19004 /* 49681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19005 /* 49684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
19006 /* 49688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19007 /* 49693 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19008 /* 49697 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19009 /* 49701 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19010 /* 49703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19011 /* 49706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19012 /* 49708 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19013 /* 49715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19014 /* 49720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19015 /* 49725 */ // GIR_Coverage, 2609,
19016 /* 49725 */ GIR_EraseRootFromParent_Done,
19017 /* 49726 */ // Label 1383: @49726
19018 /* 49726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1384*/ GIMT_Encode4(49783), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2610 //
19019 /* 49733 */ // MIs[0] Operand 1
19020 /* 49733 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19021 /* 49738 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19022 /* 49738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19023 /* 49741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
19024 /* 49745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19025 /* 49750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19026 /* 49754 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19027 /* 49758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19028 /* 49760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19029 /* 49763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19030 /* 49765 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19031 /* 49772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19032 /* 49777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19033 /* 49782 */ // GIR_Coverage, 2610,
19034 /* 49782 */ GIR_EraseRootFromParent_Done,
19035 /* 49783 */ // Label 1384: @49783
19036 /* 49783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1385*/ GIMT_Encode4(49840), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2611 //
19037 /* 49790 */ // MIs[0] Operand 1
19038 /* 49790 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19039 /* 49795 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_LT_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19040 /* 49795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19041 /* 49798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
19042 /* 49802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19043 /* 49807 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19044 /* 49811 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19045 /* 49815 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19046 /* 49817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19047 /* 49820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19048 /* 49822 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19049 /* 49829 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19050 /* 49834 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19051 /* 49839 */ // GIR_Coverage, 2611,
19052 /* 49839 */ GIR_EraseRootFromParent_Done,
19053 /* 49840 */ // Label 1385: @49840
19054 /* 49840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(49897), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2612 //
19055 /* 49847 */ // MIs[0] Operand 1
19056 /* 49847 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19057 /* 49852 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_ULT_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19058 /* 49852 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19059 /* 49855 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
19060 /* 49859 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19061 /* 49864 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19062 /* 49868 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19063 /* 49872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19064 /* 49874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19065 /* 49877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19066 /* 49879 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19067 /* 49886 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19068 /* 49891 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19069 /* 49896 */ // GIR_Coverage, 2612,
19070 /* 49896 */ GIR_EraseRootFromParent_Done,
19071 /* 49897 */ // Label 1386: @49897
19072 /* 49897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1387*/ GIMT_Encode4(49954), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2613 //
19073 /* 49904 */ // MIs[0] Operand 1
19074 /* 49904 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19075 /* 49909 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETOLE:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_LE_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19076 /* 49909 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19077 /* 49912 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
19078 /* 49916 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19079 /* 49921 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19080 /* 49925 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19081 /* 49929 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19082 /* 49931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19083 /* 49934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19084 /* 49936 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19085 /* 49943 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19086 /* 49948 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19087 /* 49953 */ // GIR_Coverage, 2613,
19088 /* 49953 */ GIR_EraseRootFromParent_Done,
19089 /* 49954 */ // Label 1387: @49954
19090 /* 49954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(50011), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2614 //
19091 /* 49961 */ // MIs[0] Operand 1
19092 /* 49961 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19093 /* 49966 */ // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETULE:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i32] } (CMP_ULE_D_MMR6:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), sub_lo:{ *:[i32] })
19094 /* 49966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19095 /* 49969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
19096 /* 49973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19097 /* 49978 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19098 /* 49982 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19099 /* 49986 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19100 /* 49988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
19101 /* 49991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
19102 /* 49993 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
19103 /* 50000 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
19104 /* 50005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
19105 /* 50010 */ // GIR_Coverage, 2614,
19106 /* 50010 */ GIR_EraseRootFromParent_Done,
19107 /* 50011 */ // Label 1388: @50011
19108 /* 50011 */ GIM_Reject,
19109 /* 50012 */ // Label 1374: @50012
19110 /* 50012 */ GIM_Reject,
19111 /* 50013 */ // Label 1358: @50013
19112 /* 50013 */ GIM_Reject,
19113 /* 50014 */ // Label 1355: @50014
19114 /* 50014 */ GIM_Reject,
19115 /* 50015 */ // Label 44: @50015
19116 /* 50015 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1395*/ GIMT_Encode4(59724),
19117 /* 50026 */ /*GILLT_s32*//*Label 1389*/ GIMT_Encode4(50058),
19118 /* 50030 */ /*GILLT_s64*//*Label 1390*/ GIMT_Encode4(55392), GIMT_Encode4(0),
19119 /* 50038 */ /*GILLT_v16s8*//*Label 1391*/ GIMT_Encode4(59442), GIMT_Encode4(0),
19120 /* 50046 */ /*GILLT_v8s16*//*Label 1392*/ GIMT_Encode4(59534),
19121 /* 50050 */ /*GILLT_v4s32*//*Label 1393*/ GIMT_Encode4(59580),
19122 /* 50054 */ /*GILLT_v2s64*//*Label 1394*/ GIMT_Encode4(59652),
19123 /* 50058 */ // Label 1389: @50058
19124 /* 50058 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1398*/ GIMT_Encode4(55391),
19125 /* 50069 */ /*GILLT_s32*//*Label 1396*/ GIMT_Encode4(50077),
19126 /* 50073 */ /*GILLT_s64*//*Label 1397*/ GIMT_Encode4(55306),
19127 /* 50077 */ // Label 1396: @50077
19128 /* 50077 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(55305),
19129 /* 50082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19130 /* 50085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19131 /* 50088 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(50322),
19132 /* 50093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19133 /* 50097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19134 /* 50101 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19135 /* 50105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1401*/ GIMT_Encode4(50159), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1846 //
19136 /* 50112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19137 /* 50116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19138 /* 50120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19139 /* 50124 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19140 /* 50128 */ // MIs[1] Operand 1
19141 /* 50128 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19142 /* 50133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19143 /* 50138 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19144 /* 50142 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19145 /* 50144 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19146 /* 50144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19147 /* 50147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19148 /* 50149 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19149 /* 50151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19150 /* 50155 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19151 /* 50157 */ GIR_RootConstrainSelectedInstOperands,
19152 /* 50158 */ // GIR_Coverage, 1846,
19153 /* 50158 */ GIR_EraseRootFromParent_Done,
19154 /* 50159 */ // Label 1401: @50159
19155 /* 50159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1402*/ GIMT_Encode4(50213), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1850 //
19156 /* 50166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19157 /* 50170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19158 /* 50174 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19159 /* 50178 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19160 /* 50182 */ // MIs[1] Operand 1
19161 /* 50182 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19162 /* 50187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19163 /* 50192 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19164 /* 50196 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19165 /* 50198 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19166 /* 50198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
19167 /* 50201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19168 /* 50203 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19169 /* 50205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19170 /* 50209 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19171 /* 50211 */ GIR_RootConstrainSelectedInstOperands,
19172 /* 50212 */ // GIR_Coverage, 1850,
19173 /* 50212 */ GIR_EraseRootFromParent_Done,
19174 /* 50213 */ // Label 1402: @50213
19175 /* 50213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1403*/ GIMT_Encode4(50267), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1878 //
19176 /* 50220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19177 /* 50224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19178 /* 50228 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19179 /* 50232 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19180 /* 50236 */ // MIs[1] Operand 1
19181 /* 50236 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19182 /* 50241 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19183 /* 50246 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19184 /* 50250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19185 /* 50252 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
19186 /* 50252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
19187 /* 50255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19188 /* 50257 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19189 /* 50259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19190 /* 50263 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19191 /* 50265 */ GIR_RootConstrainSelectedInstOperands,
19192 /* 50266 */ // GIR_Coverage, 1878,
19193 /* 50266 */ GIR_EraseRootFromParent_Done,
19194 /* 50267 */ // Label 1403: @50267
19195 /* 50267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1404*/ GIMT_Encode4(50321), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1889 //
19196 /* 50274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19197 /* 50278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19198 /* 50282 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19199 /* 50286 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19200 /* 50290 */ // MIs[1] Operand 1
19201 /* 50290 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19202 /* 50295 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19203 /* 50300 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19204 /* 50304 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19205 /* 50306 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
19206 /* 50306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
19207 /* 50309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19208 /* 50311 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19209 /* 50313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19210 /* 50317 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19211 /* 50319 */ GIR_RootConstrainSelectedInstOperands,
19212 /* 50320 */ // GIR_Coverage, 1889,
19213 /* 50320 */ GIR_EraseRootFromParent_Done,
19214 /* 50321 */ // Label 1404: @50321
19215 /* 50321 */ GIM_Reject,
19216 /* 50322 */ // Label 1400: @50322
19217 /* 50322 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(50556),
19218 /* 50327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19219 /* 50331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19220 /* 50335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19221 /* 50339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1406*/ GIMT_Encode4(50393), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1902 //
19222 /* 50346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19223 /* 50350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19224 /* 50354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19225 /* 50358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19226 /* 50362 */ // MIs[1] Operand 1
19227 /* 50362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19228 /* 50367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19229 /* 50372 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19230 /* 50376 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19231 /* 50378 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19232 /* 50378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19233 /* 50381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19234 /* 50383 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19235 /* 50385 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19236 /* 50389 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19237 /* 50391 */ GIR_RootConstrainSelectedInstOperands,
19238 /* 50392 */ // GIR_Coverage, 1902,
19239 /* 50392 */ GIR_EraseRootFromParent_Done,
19240 /* 50393 */ // Label 1406: @50393
19241 /* 50393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1407*/ GIMT_Encode4(50447), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1905 //
19242 /* 50400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19243 /* 50404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19244 /* 50408 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19245 /* 50412 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19246 /* 50416 */ // MIs[1] Operand 1
19247 /* 50416 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19248 /* 50421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19249 /* 50426 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19250 /* 50430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19251 /* 50432 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19252 /* 50432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
19253 /* 50435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19254 /* 50437 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19255 /* 50439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19256 /* 50443 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19257 /* 50445 */ GIR_RootConstrainSelectedInstOperands,
19258 /* 50446 */ // GIR_Coverage, 1905,
19259 /* 50446 */ GIR_EraseRootFromParent_Done,
19260 /* 50447 */ // Label 1407: @50447
19261 /* 50447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1408*/ GIMT_Encode4(50501), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1915 //
19262 /* 50454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19263 /* 50458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19264 /* 50462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19265 /* 50466 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19266 /* 50470 */ // MIs[1] Operand 1
19267 /* 50470 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19268 /* 50475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19269 /* 50480 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19270 /* 50484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19271 /* 50486 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19272 /* 50486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
19273 /* 50489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19274 /* 50491 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19275 /* 50493 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19276 /* 50497 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19277 /* 50499 */ GIR_RootConstrainSelectedInstOperands,
19278 /* 50500 */ // GIR_Coverage, 1915,
19279 /* 50500 */ GIR_EraseRootFromParent_Done,
19280 /* 50501 */ // Label 1408: @50501
19281 /* 50501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1409*/ GIMT_Encode4(50555), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1918 //
19282 /* 50508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19283 /* 50512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19284 /* 50516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19285 /* 50520 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19286 /* 50524 */ // MIs[1] Operand 1
19287 /* 50524 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19288 /* 50529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19289 /* 50534 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19290 /* 50538 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19291 /* 50540 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19292 /* 50540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
19293 /* 50543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19294 /* 50545 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19295 /* 50547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19296 /* 50551 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19297 /* 50553 */ GIR_RootConstrainSelectedInstOperands,
19298 /* 50554 */ // GIR_Coverage, 1918,
19299 /* 50554 */ GIR_EraseRootFromParent_Done,
19300 /* 50555 */ // Label 1409: @50555
19301 /* 50555 */ GIM_Reject,
19302 /* 50556 */ // Label 1405: @50556
19303 /* 50556 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(50682),
19304 /* 50561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19305 /* 50565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19306 /* 50569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19307 /* 50573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1411*/ GIMT_Encode4(50627), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2127 //
19308 /* 50580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19309 /* 50584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19310 /* 50588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19311 /* 50592 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19312 /* 50596 */ // MIs[1] Operand 1
19313 /* 50596 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19314 /* 50601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19315 /* 50606 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19316 /* 50610 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19317 /* 50612 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19318 /* 50612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
19319 /* 50615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19320 /* 50617 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19321 /* 50619 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19322 /* 50621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19323 /* 50625 */ GIR_RootConstrainSelectedInstOperands,
19324 /* 50626 */ // GIR_Coverage, 2127,
19325 /* 50626 */ GIR_EraseRootFromParent_Done,
19326 /* 50627 */ // Label 1411: @50627
19327 /* 50627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1412*/ GIMT_Encode4(50681), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2130 //
19328 /* 50634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19329 /* 50638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19330 /* 50642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19331 /* 50646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19332 /* 50650 */ // MIs[1] Operand 1
19333 /* 50650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19334 /* 50655 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19335 /* 50660 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19336 /* 50664 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19337 /* 50666 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19338 /* 50666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
19339 /* 50669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19340 /* 50671 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19341 /* 50673 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19342 /* 50675 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19343 /* 50679 */ GIR_RootConstrainSelectedInstOperands,
19344 /* 50680 */ // GIR_Coverage, 2130,
19345 /* 50680 */ GIR_EraseRootFromParent_Done,
19346 /* 50681 */ // Label 1412: @50681
19347 /* 50681 */ GIM_Reject,
19348 /* 50682 */ // Label 1410: @50682
19349 /* 50682 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(50916),
19350 /* 50687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19351 /* 50691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19352 /* 50695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19353 /* 50699 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1414*/ GIMT_Encode4(50753), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2497 //
19354 /* 50706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19355 /* 50710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19356 /* 50714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19357 /* 50718 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19358 /* 50722 */ // MIs[1] Operand 1
19359 /* 50722 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19360 /* 50727 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19361 /* 50732 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19362 /* 50736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19363 /* 50738 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19364 /* 50738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19365 /* 50741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19366 /* 50743 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19367 /* 50745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19368 /* 50749 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19369 /* 50751 */ GIR_RootConstrainSelectedInstOperands,
19370 /* 50752 */ // GIR_Coverage, 2497,
19371 /* 50752 */ GIR_EraseRootFromParent_Done,
19372 /* 50753 */ // Label 1414: @50753
19373 /* 50753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1415*/ GIMT_Encode4(50807), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2501 //
19374 /* 50760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19375 /* 50764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19376 /* 50768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19377 /* 50772 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19378 /* 50776 */ // MIs[1] Operand 1
19379 /* 50776 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19380 /* 50781 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19381 /* 50786 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19382 /* 50790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19383 /* 50792 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19384 /* 50792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19385 /* 50795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19386 /* 50797 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19387 /* 50799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19388 /* 50803 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19389 /* 50805 */ GIR_RootConstrainSelectedInstOperands,
19390 /* 50806 */ // GIR_Coverage, 2501,
19391 /* 50806 */ GIR_EraseRootFromParent_Done,
19392 /* 50807 */ // Label 1415: @50807
19393 /* 50807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1416*/ GIMT_Encode4(50861), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2511 //
19394 /* 50814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19395 /* 50818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19396 /* 50822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19397 /* 50826 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19398 /* 50830 */ // MIs[1] Operand 1
19399 /* 50830 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19400 /* 50835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19401 /* 50840 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19402 /* 50844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19403 /* 50846 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19404 /* 50846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19405 /* 50849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19406 /* 50851 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19407 /* 50853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19408 /* 50857 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19409 /* 50859 */ GIR_RootConstrainSelectedInstOperands,
19410 /* 50860 */ // GIR_Coverage, 2511,
19411 /* 50860 */ GIR_EraseRootFromParent_Done,
19412 /* 50861 */ // Label 1416: @50861
19413 /* 50861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1417*/ GIMT_Encode4(50915), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2515 //
19414 /* 50868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19415 /* 50872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19416 /* 50876 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19417 /* 50880 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19418 /* 50884 */ // MIs[1] Operand 1
19419 /* 50884 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19420 /* 50889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19421 /* 50894 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19422 /* 50898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19423 /* 50900 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19424 /* 50900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19425 /* 50903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19426 /* 50905 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19427 /* 50907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19428 /* 50911 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19429 /* 50913 */ GIR_RootConstrainSelectedInstOperands,
19430 /* 50914 */ // GIR_Coverage, 2515,
19431 /* 50914 */ GIR_EraseRootFromParent_Done,
19432 /* 50915 */ // Label 1417: @50915
19433 /* 50915 */ GIM_Reject,
19434 /* 50916 */ // Label 1413: @50916
19435 /* 50916 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(51042),
19436 /* 50921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19437 /* 50925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19438 /* 50929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19439 /* 50933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1419*/ GIMT_Encode4(50987), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2564 //
19440 /* 50940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19441 /* 50944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19442 /* 50948 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19443 /* 50952 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19444 /* 50956 */ // MIs[1] Operand 1
19445 /* 50956 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19446 /* 50961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19447 /* 50966 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19448 /* 50970 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19449 /* 50972 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19450 /* 50972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
19451 /* 50975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19452 /* 50977 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19453 /* 50979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19454 /* 50983 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19455 /* 50985 */ GIR_RootConstrainSelectedInstOperands,
19456 /* 50986 */ // GIR_Coverage, 2564,
19457 /* 50986 */ GIR_EraseRootFromParent_Done,
19458 /* 50987 */ // Label 1419: @50987
19459 /* 50987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(51041), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2567 //
19460 /* 50994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19461 /* 50998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19462 /* 51002 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19463 /* 51006 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19464 /* 51010 */ // MIs[1] Operand 1
19465 /* 51010 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19466 /* 51015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19467 /* 51020 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19468 /* 51024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19469 /* 51026 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19470 /* 51026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
19471 /* 51029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19472 /* 51031 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19473 /* 51033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19474 /* 51037 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19475 /* 51039 */ GIR_RootConstrainSelectedInstOperands,
19476 /* 51040 */ // GIR_Coverage, 2567,
19477 /* 51040 */ GIR_EraseRootFromParent_Done,
19478 /* 51041 */ // Label 1420: @51041
19479 /* 51041 */ GIM_Reject,
19480 /* 51042 */ // Label 1418: @51042
19481 /* 51042 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(51972),
19482 /* 51047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19483 /* 51051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19484 /* 51055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19485 /* 51059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(51135), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1837 //
19486 /* 51066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19487 /* 51070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19488 /* 51074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19489 /* 51078 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19490 /* 51082 */ // MIs[1] Operand 1
19491 /* 51082 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19492 /* 51087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19493 /* 51092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19494 /* 51097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19495 /* 51099 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19496 /* 51099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19497 /* 51102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19498 /* 51106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19499 /* 51111 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19500 /* 51115 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19501 /* 51119 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19502 /* 51121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19503 /* 51124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19504 /* 51126 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19505 /* 51128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19506 /* 51131 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19507 /* 51133 */ GIR_RootConstrainSelectedInstOperands,
19508 /* 51134 */ // GIR_Coverage, 1837,
19509 /* 51134 */ GIR_EraseRootFromParent_Done,
19510 /* 51135 */ // Label 1422: @51135
19511 /* 51135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(51211), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1838 //
19512 /* 51142 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19513 /* 51146 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19514 /* 51150 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19515 /* 51154 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19516 /* 51158 */ // MIs[1] Operand 1
19517 /* 51158 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19518 /* 51163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19519 /* 51168 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19520 /* 51173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19521 /* 51175 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19522 /* 51175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19523 /* 51178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19524 /* 51182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19525 /* 51187 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19526 /* 51191 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19527 /* 51195 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19528 /* 51197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19529 /* 51200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19530 /* 51202 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19531 /* 51204 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19532 /* 51207 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19533 /* 51209 */ GIR_RootConstrainSelectedInstOperands,
19534 /* 51210 */ // GIR_Coverage, 1838,
19535 /* 51210 */ GIR_EraseRootFromParent_Done,
19536 /* 51211 */ // Label 1423: @51211
19537 /* 51211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1424*/ GIMT_Encode4(51287), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1841 //
19538 /* 51218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19539 /* 51222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19540 /* 51226 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19541 /* 51230 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19542 /* 51234 */ // MIs[1] Operand 1
19543 /* 51234 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19544 /* 51239 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19545 /* 51244 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19546 /* 51249 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19547 /* 51251 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19548 /* 51251 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19549 /* 51254 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19550 /* 51258 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19551 /* 51263 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19552 /* 51267 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19553 /* 51271 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19554 /* 51273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19555 /* 51276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19556 /* 51278 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19557 /* 51280 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19558 /* 51283 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19559 /* 51285 */ GIR_RootConstrainSelectedInstOperands,
19560 /* 51286 */ // GIR_Coverage, 1841,
19561 /* 51286 */ GIR_EraseRootFromParent_Done,
19562 /* 51287 */ // Label 1424: @51287
19563 /* 51287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(51363), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1842 //
19564 /* 51294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19565 /* 51298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19566 /* 51302 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19567 /* 51306 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19568 /* 51310 */ // MIs[1] Operand 1
19569 /* 51310 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19570 /* 51315 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19571 /* 51320 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19572 /* 51325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19573 /* 51327 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19574 /* 51327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19575 /* 51330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19576 /* 51334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19577 /* 51339 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19578 /* 51343 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19579 /* 51347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19580 /* 51349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19581 /* 51352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19582 /* 51354 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19583 /* 51356 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19584 /* 51359 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19585 /* 51361 */ GIR_RootConstrainSelectedInstOperands,
19586 /* 51362 */ // GIR_Coverage, 1842,
19587 /* 51362 */ GIR_EraseRootFromParent_Done,
19588 /* 51363 */ // Label 1425: @51363
19589 /* 51363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1426*/ GIMT_Encode4(51439), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1845 //
19590 /* 51370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19591 /* 51374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19592 /* 51378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19593 /* 51382 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19594 /* 51386 */ // MIs[1] Operand 1
19595 /* 51386 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19596 /* 51391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19597 /* 51396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19598 /* 51401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19599 /* 51403 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19600 /* 51403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19601 /* 51406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19602 /* 51410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19603 /* 51415 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19604 /* 51419 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19605 /* 51423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19606 /* 51425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19607 /* 51428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19608 /* 51430 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19609 /* 51432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19610 /* 51435 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19611 /* 51437 */ GIR_RootConstrainSelectedInstOperands,
19612 /* 51438 */ // GIR_Coverage, 1845,
19613 /* 51438 */ GIR_EraseRootFromParent_Done,
19614 /* 51439 */ // Label 1426: @51439
19615 /* 51439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1427*/ GIMT_Encode4(51515), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1848 //
19616 /* 51446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19617 /* 51450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19618 /* 51454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19619 /* 51458 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19620 /* 51462 */ // MIs[1] Operand 1
19621 /* 51462 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19622 /* 51467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19623 /* 51472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19624 /* 51477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19625 /* 51479 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19626 /* 51479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19627 /* 51482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19628 /* 51486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19629 /* 51491 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19630 /* 51495 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19631 /* 51499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19632 /* 51501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
19633 /* 51504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19634 /* 51506 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19635 /* 51508 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19636 /* 51511 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19637 /* 51513 */ GIR_RootConstrainSelectedInstOperands,
19638 /* 51514 */ // GIR_Coverage, 1848,
19639 /* 51514 */ GIR_EraseRootFromParent_Done,
19640 /* 51515 */ // Label 1427: @51515
19641 /* 51515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1428*/ GIMT_Encode4(51591), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1859 //
19642 /* 51522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19643 /* 51526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19644 /* 51530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19645 /* 51534 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19646 /* 51538 */ // MIs[1] Operand 1
19647 /* 51538 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19648 /* 51543 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19649 /* 51548 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19650 /* 51553 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19651 /* 51555 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19652 /* 51555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19653 /* 51558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19654 /* 51562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19655 /* 51567 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19656 /* 51571 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19657 /* 51575 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19658 /* 51577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19659 /* 51580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19660 /* 51582 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19661 /* 51584 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19662 /* 51587 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19663 /* 51589 */ GIR_RootConstrainSelectedInstOperands,
19664 /* 51590 */ // GIR_Coverage, 1859,
19665 /* 51590 */ GIR_EraseRootFromParent_Done,
19666 /* 51591 */ // Label 1428: @51591
19667 /* 51591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1429*/ GIMT_Encode4(51667), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1860 //
19668 /* 51598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19669 /* 51602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19670 /* 51606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19671 /* 51610 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19672 /* 51614 */ // MIs[1] Operand 1
19673 /* 51614 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19674 /* 51619 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19675 /* 51624 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19676 /* 51629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19677 /* 51631 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19678 /* 51631 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19679 /* 51634 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19680 /* 51638 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19681 /* 51643 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19682 /* 51647 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19683 /* 51651 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19684 /* 51653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19685 /* 51656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19686 /* 51658 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19687 /* 51660 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19688 /* 51663 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19689 /* 51665 */ GIR_RootConstrainSelectedInstOperands,
19690 /* 51666 */ // GIR_Coverage, 1860,
19691 /* 51666 */ GIR_EraseRootFromParent_Done,
19692 /* 51667 */ // Label 1429: @51667
19693 /* 51667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1430*/ GIMT_Encode4(51743), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1863 //
19694 /* 51674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19695 /* 51678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19696 /* 51682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19697 /* 51686 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19698 /* 51690 */ // MIs[1] Operand 1
19699 /* 51690 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19700 /* 51695 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19701 /* 51700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19702 /* 51705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19703 /* 51707 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19704 /* 51707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19705 /* 51710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19706 /* 51714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19707 /* 51719 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19708 /* 51723 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19709 /* 51727 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19710 /* 51729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19711 /* 51732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19712 /* 51734 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19713 /* 51736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19714 /* 51739 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19715 /* 51741 */ GIR_RootConstrainSelectedInstOperands,
19716 /* 51742 */ // GIR_Coverage, 1863,
19717 /* 51742 */ GIR_EraseRootFromParent_Done,
19718 /* 51743 */ // Label 1430: @51743
19719 /* 51743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1431*/ GIMT_Encode4(51819), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1864 //
19720 /* 51750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19721 /* 51754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19722 /* 51758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19723 /* 51762 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19724 /* 51766 */ // MIs[1] Operand 1
19725 /* 51766 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19726 /* 51771 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19727 /* 51776 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19728 /* 51781 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19729 /* 51783 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19730 /* 51783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19731 /* 51786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19732 /* 51790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19733 /* 51795 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19734 /* 51799 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19735 /* 51803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19736 /* 51805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19737 /* 51808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19738 /* 51810 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19739 /* 51812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19740 /* 51815 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19741 /* 51817 */ GIR_RootConstrainSelectedInstOperands,
19742 /* 51818 */ // GIR_Coverage, 1864,
19743 /* 51818 */ GIR_EraseRootFromParent_Done,
19744 /* 51819 */ // Label 1431: @51819
19745 /* 51819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1432*/ GIMT_Encode4(51895), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1877 //
19746 /* 51826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19747 /* 51830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19748 /* 51834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19749 /* 51838 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19750 /* 51842 */ // MIs[1] Operand 1
19751 /* 51842 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19752 /* 51847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19753 /* 51852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19754 /* 51857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19755 /* 51859 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19756 /* 51859 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19757 /* 51862 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19758 /* 51866 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19759 /* 51871 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19760 /* 51875 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19761 /* 51879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19762 /* 51881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
19763 /* 51884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19764 /* 51886 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19765 /* 51888 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19766 /* 51891 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19767 /* 51893 */ GIR_RootConstrainSelectedInstOperands,
19768 /* 51894 */ // GIR_Coverage, 1877,
19769 /* 51894 */ GIR_EraseRootFromParent_Done,
19770 /* 51895 */ // Label 1432: @51895
19771 /* 51895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1433*/ GIMT_Encode4(51971), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1887 //
19772 /* 51902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19773 /* 51906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19774 /* 51910 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19775 /* 51914 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19776 /* 51918 */ // MIs[1] Operand 1
19777 /* 51918 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19778 /* 51923 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19779 /* 51928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19780 /* 51933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19781 /* 51935 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19782 /* 51935 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19783 /* 51938 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19784 /* 51942 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19785 /* 51947 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19786 /* 51951 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19787 /* 51955 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19788 /* 51957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
19789 /* 51960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19790 /* 51962 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19791 /* 51964 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19792 /* 51967 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19793 /* 51969 */ GIR_RootConstrainSelectedInstOperands,
19794 /* 51970 */ // GIR_Coverage, 1887,
19795 /* 51970 */ GIR_EraseRootFromParent_Done,
19796 /* 51971 */ // Label 1433: @51971
19797 /* 51971 */ GIM_Reject,
19798 /* 51972 */ // Label 1421: @51972
19799 /* 51972 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(52902),
19800 /* 51977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19801 /* 51981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19802 /* 51985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19803 /* 51989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1435*/ GIMT_Encode4(52065), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1893 //
19804 /* 51996 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19805 /* 52000 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19806 /* 52004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19807 /* 52008 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19808 /* 52012 */ // MIs[1] Operand 1
19809 /* 52012 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19810 /* 52017 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19811 /* 52022 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19812 /* 52027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19813 /* 52029 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19814 /* 52029 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19815 /* 52032 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19816 /* 52036 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19817 /* 52041 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19818 /* 52045 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19819 /* 52049 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19820 /* 52051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19821 /* 52054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19822 /* 52056 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19823 /* 52058 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19824 /* 52061 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19825 /* 52063 */ GIR_RootConstrainSelectedInstOperands,
19826 /* 52064 */ // GIR_Coverage, 1893,
19827 /* 52064 */ GIR_EraseRootFromParent_Done,
19828 /* 52065 */ // Label 1435: @52065
19829 /* 52065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1436*/ GIMT_Encode4(52141), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1894 //
19830 /* 52072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19831 /* 52076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19832 /* 52080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19833 /* 52084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19834 /* 52088 */ // MIs[1] Operand 1
19835 /* 52088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19836 /* 52093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19837 /* 52098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19838 /* 52103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19839 /* 52105 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19840 /* 52105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19841 /* 52108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19842 /* 52112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19843 /* 52117 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19844 /* 52121 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19845 /* 52125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19846 /* 52127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19847 /* 52130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19848 /* 52132 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19849 /* 52134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19850 /* 52137 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19851 /* 52139 */ GIR_RootConstrainSelectedInstOperands,
19852 /* 52140 */ // GIR_Coverage, 1894,
19853 /* 52140 */ GIR_EraseRootFromParent_Done,
19854 /* 52141 */ // Label 1436: @52141
19855 /* 52141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1437*/ GIMT_Encode4(52217), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1897 //
19856 /* 52148 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19857 /* 52152 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19858 /* 52156 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19859 /* 52160 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19860 /* 52164 */ // MIs[1] Operand 1
19861 /* 52164 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19862 /* 52169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19863 /* 52174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19864 /* 52179 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19865 /* 52181 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19866 /* 52181 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19867 /* 52184 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19868 /* 52188 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19869 /* 52193 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19870 /* 52197 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19871 /* 52201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19872 /* 52203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19873 /* 52206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19874 /* 52208 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19875 /* 52210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19876 /* 52213 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19877 /* 52215 */ GIR_RootConstrainSelectedInstOperands,
19878 /* 52216 */ // GIR_Coverage, 1897,
19879 /* 52216 */ GIR_EraseRootFromParent_Done,
19880 /* 52217 */ // Label 1437: @52217
19881 /* 52217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1438*/ GIMT_Encode4(52293), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1898 //
19882 /* 52224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19883 /* 52228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19884 /* 52232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19885 /* 52236 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19886 /* 52240 */ // MIs[1] Operand 1
19887 /* 52240 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19888 /* 52245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19889 /* 52250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19890 /* 52255 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19891 /* 52257 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19892 /* 52257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19893 /* 52260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19894 /* 52264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19895 /* 52269 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19896 /* 52273 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19897 /* 52277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19898 /* 52279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19899 /* 52282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19900 /* 52284 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19901 /* 52286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19902 /* 52289 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19903 /* 52291 */ GIR_RootConstrainSelectedInstOperands,
19904 /* 52292 */ // GIR_Coverage, 1898,
19905 /* 52292 */ GIR_EraseRootFromParent_Done,
19906 /* 52293 */ // Label 1438: @52293
19907 /* 52293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(52369), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1901 //
19908 /* 52300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19909 /* 52304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19910 /* 52308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19911 /* 52312 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19912 /* 52316 */ // MIs[1] Operand 1
19913 /* 52316 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19914 /* 52321 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19915 /* 52326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19916 /* 52331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19917 /* 52333 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19918 /* 52333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19919 /* 52336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19920 /* 52340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19921 /* 52345 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19922 /* 52349 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19923 /* 52353 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19924 /* 52355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19925 /* 52358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19926 /* 52360 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19927 /* 52362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19928 /* 52365 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19929 /* 52367 */ GIR_RootConstrainSelectedInstOperands,
19930 /* 52368 */ // GIR_Coverage, 1901,
19931 /* 52368 */ GIR_EraseRootFromParent_Done,
19932 /* 52369 */ // Label 1439: @52369
19933 /* 52369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(52445), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1903 //
19934 /* 52376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19935 /* 52380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19936 /* 52384 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19937 /* 52388 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19938 /* 52392 */ // MIs[1] Operand 1
19939 /* 52392 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19940 /* 52397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19941 /* 52402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19942 /* 52407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19943 /* 52409 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19944 /* 52409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19945 /* 52412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19946 /* 52416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19947 /* 52421 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19948 /* 52425 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19949 /* 52429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19950 /* 52431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
19951 /* 52434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19952 /* 52436 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19953 /* 52438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19954 /* 52441 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19955 /* 52443 */ GIR_RootConstrainSelectedInstOperands,
19956 /* 52444 */ // GIR_Coverage, 1903,
19957 /* 52444 */ GIR_EraseRootFromParent_Done,
19958 /* 52445 */ // Label 1440: @52445
19959 /* 52445 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(52521), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1906 //
19960 /* 52452 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19961 /* 52456 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19962 /* 52460 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19963 /* 52464 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19964 /* 52468 */ // MIs[1] Operand 1
19965 /* 52468 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19966 /* 52473 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19967 /* 52478 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19968 /* 52483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19969 /* 52485 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19970 /* 52485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19971 /* 52488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19972 /* 52492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19973 /* 52497 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19974 /* 52501 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19975 /* 52505 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19976 /* 52507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19977 /* 52510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19978 /* 52512 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19979 /* 52514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19980 /* 52517 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19981 /* 52519 */ GIR_RootConstrainSelectedInstOperands,
19982 /* 52520 */ // GIR_Coverage, 1906,
19983 /* 52520 */ GIR_EraseRootFromParent_Done,
19984 /* 52521 */ // Label 1441: @52521
19985 /* 52521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(52597), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1907 //
19986 /* 52528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19987 /* 52532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19988 /* 52536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19989 /* 52540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19990 /* 52544 */ // MIs[1] Operand 1
19991 /* 52544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19992 /* 52549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19993 /* 52554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19994 /* 52559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19995 /* 52561 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19996 /* 52561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19997 /* 52564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19998 /* 52568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19999 /* 52573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20000 /* 52577 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20001 /* 52581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20002 /* 52583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20003 /* 52586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20004 /* 52588 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20005 /* 52590 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20006 /* 52593 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20007 /* 52595 */ GIR_RootConstrainSelectedInstOperands,
20008 /* 52596 */ // GIR_Coverage, 1907,
20009 /* 52596 */ GIR_EraseRootFromParent_Done,
20010 /* 52597 */ // Label 1442: @52597
20011 /* 52597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(52673), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1910 //
20012 /* 52604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20013 /* 52608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20014 /* 52612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20015 /* 52616 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20016 /* 52620 */ // MIs[1] Operand 1
20017 /* 52620 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20018 /* 52625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20019 /* 52630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20020 /* 52635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20021 /* 52637 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
20022 /* 52637 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20023 /* 52640 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20024 /* 52644 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20025 /* 52649 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20026 /* 52653 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20027 /* 52657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20028 /* 52659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20029 /* 52662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20030 /* 52664 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20031 /* 52666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20032 /* 52669 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20033 /* 52671 */ GIR_RootConstrainSelectedInstOperands,
20034 /* 52672 */ // GIR_Coverage, 1910,
20035 /* 52672 */ GIR_EraseRootFromParent_Done,
20036 /* 52673 */ // Label 1443: @52673
20037 /* 52673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(52749), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1911 //
20038 /* 52680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20039 /* 52684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20040 /* 52688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20041 /* 52692 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20042 /* 52696 */ // MIs[1] Operand 1
20043 /* 52696 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20044 /* 52701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20045 /* 52706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20046 /* 52711 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20047 /* 52713 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
20048 /* 52713 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20049 /* 52716 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20050 /* 52720 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20051 /* 52725 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20052 /* 52729 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20053 /* 52733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20054 /* 52735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20055 /* 52738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20056 /* 52740 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20057 /* 52742 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20058 /* 52745 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20059 /* 52747 */ GIR_RootConstrainSelectedInstOperands,
20060 /* 52748 */ // GIR_Coverage, 1911,
20061 /* 52748 */ GIR_EraseRootFromParent_Done,
20062 /* 52749 */ // Label 1444: @52749
20063 /* 52749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(52825), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1914 //
20064 /* 52756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20065 /* 52760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20066 /* 52764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20067 /* 52768 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20068 /* 52772 */ // MIs[1] Operand 1
20069 /* 52772 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20070 /* 52777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20071 /* 52782 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20072 /* 52787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20073 /* 52789 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20074 /* 52789 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20075 /* 52792 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20076 /* 52796 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20077 /* 52801 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20078 /* 52805 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20079 /* 52809 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20080 /* 52811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
20081 /* 52814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20082 /* 52816 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20083 /* 52818 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20084 /* 52821 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20085 /* 52823 */ GIR_RootConstrainSelectedInstOperands,
20086 /* 52824 */ // GIR_Coverage, 1914,
20087 /* 52824 */ GIR_EraseRootFromParent_Done,
20088 /* 52825 */ // Label 1445: @52825
20089 /* 52825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1446*/ GIMT_Encode4(52901), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1916 //
20090 /* 52832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20091 /* 52836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20092 /* 52840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20093 /* 52844 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20094 /* 52848 */ // MIs[1] Operand 1
20095 /* 52848 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20096 /* 52853 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20097 /* 52858 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20098 /* 52863 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20099 /* 52865 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
20100 /* 52865 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20101 /* 52868 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20102 /* 52872 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20103 /* 52877 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20104 /* 52881 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20105 /* 52885 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20106 /* 52887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20107 /* 52890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20108 /* 52892 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20109 /* 52894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20110 /* 52897 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20111 /* 52899 */ GIR_RootConstrainSelectedInstOperands,
20112 /* 52900 */ // GIR_Coverage, 1916,
20113 /* 52900 */ GIR_EraseRootFromParent_Done,
20114 /* 52901 */ // Label 1446: @52901
20115 /* 52901 */ GIM_Reject,
20116 /* 52902 */ // Label 1434: @52902
20117 /* 52902 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(53392),
20118 /* 52907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20119 /* 52911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20120 /* 52915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20121 /* 52919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(52978), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2119 //
20122 /* 52926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20123 /* 52930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20124 /* 52934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20125 /* 52938 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20126 /* 52942 */ // MIs[1] Operand 1
20127 /* 52942 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20128 /* 52947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20129 /* 52952 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20130 /* 52957 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20131 /* 52959 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
20132 /* 52959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
20133 /* 52962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20134 /* 52964 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20135 /* 52966 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20136 /* 52968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20137 /* 52972 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20138 /* 52976 */ GIR_RootConstrainSelectedInstOperands,
20139 /* 52977 */ // GIR_Coverage, 2119,
20140 /* 52977 */ GIR_EraseRootFromParent_Done,
20141 /* 52978 */ // Label 1448: @52978
20142 /* 52978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(53037), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2120 //
20143 /* 52985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20144 /* 52989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20145 /* 52993 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20146 /* 52997 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20147 /* 53001 */ // MIs[1] Operand 1
20148 /* 53001 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
20149 /* 53006 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20150 /* 53011 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20151 /* 53016 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20152 /* 53018 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20153 /* 53018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
20154 /* 53021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20155 /* 53023 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20156 /* 53025 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20157 /* 53027 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20158 /* 53031 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20159 /* 53035 */ GIR_RootConstrainSelectedInstOperands,
20160 /* 53036 */ // GIR_Coverage, 2120,
20161 /* 53036 */ GIR_EraseRootFromParent_Done,
20162 /* 53037 */ // Label 1449: @53037
20163 /* 53037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(53096), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2121 //
20164 /* 53044 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20165 /* 53048 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20166 /* 53052 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20167 /* 53056 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20168 /* 53060 */ // MIs[1] Operand 1
20169 /* 53060 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20170 /* 53065 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20171 /* 53070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20172 /* 53075 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20173 /* 53077 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
20174 /* 53077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
20175 /* 53080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20176 /* 53082 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20177 /* 53084 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20178 /* 53086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20179 /* 53090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20180 /* 53094 */ GIR_RootConstrainSelectedInstOperands,
20181 /* 53095 */ // GIR_Coverage, 2121,
20182 /* 53095 */ GIR_EraseRootFromParent_Done,
20183 /* 53096 */ // Label 1450: @53096
20184 /* 53096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(53155), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2122 //
20185 /* 53103 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20186 /* 53107 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20187 /* 53111 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20188 /* 53115 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20189 /* 53119 */ // MIs[1] Operand 1
20190 /* 53119 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
20191 /* 53124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20192 /* 53129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20193 /* 53134 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20194 /* 53136 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20195 /* 53136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
20196 /* 53139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20197 /* 53141 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20198 /* 53143 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20199 /* 53145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20200 /* 53149 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20201 /* 53153 */ GIR_RootConstrainSelectedInstOperands,
20202 /* 53154 */ // GIR_Coverage, 2122,
20203 /* 53154 */ GIR_EraseRootFromParent_Done,
20204 /* 53155 */ // Label 1451: @53155
20205 /* 53155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(53214), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2124 //
20206 /* 53162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20207 /* 53166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20208 /* 53170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20209 /* 53174 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20210 /* 53178 */ // MIs[1] Operand 1
20211 /* 53178 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20212 /* 53183 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20213 /* 53188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20214 /* 53193 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20215 /* 53195 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20216 /* 53195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
20217 /* 53198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20218 /* 53200 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20219 /* 53202 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20220 /* 53204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20221 /* 53208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20222 /* 53212 */ GIR_RootConstrainSelectedInstOperands,
20223 /* 53213 */ // GIR_Coverage, 2124,
20224 /* 53213 */ GIR_EraseRootFromParent_Done,
20225 /* 53214 */ // Label 1452: @53214
20226 /* 53214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(53273), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2125 //
20227 /* 53221 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20228 /* 53225 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20229 /* 53229 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20230 /* 53233 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20231 /* 53237 */ // MIs[1] Operand 1
20232 /* 53237 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20233 /* 53242 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20234 /* 53247 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20235 /* 53252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20236 /* 53254 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20237 /* 53254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
20238 /* 53257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20239 /* 53259 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20240 /* 53261 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20241 /* 53263 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20242 /* 53267 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20243 /* 53271 */ GIR_RootConstrainSelectedInstOperands,
20244 /* 53272 */ // GIR_Coverage, 2125,
20245 /* 53272 */ GIR_EraseRootFromParent_Done,
20246 /* 53273 */ // Label 1453: @53273
20247 /* 53273 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1454*/ GIMT_Encode4(53332), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2126 //
20248 /* 53280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20249 /* 53284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20250 /* 53288 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20251 /* 53292 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20252 /* 53296 */ // MIs[1] Operand 1
20253 /* 53296 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20254 /* 53301 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20255 /* 53306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20256 /* 53311 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20257 /* 53313 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20258 /* 53313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
20259 /* 53316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20260 /* 53318 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20261 /* 53320 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20262 /* 53322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20263 /* 53326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20264 /* 53330 */ GIR_RootConstrainSelectedInstOperands,
20265 /* 53331 */ // GIR_Coverage, 2126,
20266 /* 53331 */ GIR_EraseRootFromParent_Done,
20267 /* 53332 */ // Label 1454: @53332
20268 /* 53332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(53391), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2129 //
20269 /* 53339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20270 /* 53343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20271 /* 53347 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20272 /* 53351 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20273 /* 53355 */ // MIs[1] Operand 1
20274 /* 53355 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20275 /* 53360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20276 /* 53365 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20277 /* 53370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20278 /* 53372 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20279 /* 53372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
20280 /* 53375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20281 /* 53377 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20282 /* 53379 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20283 /* 53381 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20284 /* 53385 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20285 /* 53389 */ GIR_RootConstrainSelectedInstOperands,
20286 /* 53390 */ // GIR_Coverage, 2129,
20287 /* 53390 */ GIR_EraseRootFromParent_Done,
20288 /* 53391 */ // Label 1455: @53391
20289 /* 53391 */ GIM_Reject,
20290 /* 53392 */ // Label 1447: @53392
20291 /* 53392 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(54322),
20292 /* 53397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20293 /* 53401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20294 /* 53405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20295 /* 53409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(53485), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2488 //
20296 /* 53416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20297 /* 53420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20298 /* 53424 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20299 /* 53428 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20300 /* 53432 */ // MIs[1] Operand 1
20301 /* 53432 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20302 /* 53437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20303 /* 53442 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20304 /* 53447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20305 /* 53449 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20306 /* 53449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20307 /* 53452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20308 /* 53456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20309 /* 53461 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20310 /* 53465 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20311 /* 53469 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20312 /* 53471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20313 /* 53474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20314 /* 53476 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20315 /* 53478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20316 /* 53481 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20317 /* 53483 */ GIR_RootConstrainSelectedInstOperands,
20318 /* 53484 */ // GIR_Coverage, 2488,
20319 /* 53484 */ GIR_EraseRootFromParent_Done,
20320 /* 53485 */ // Label 1457: @53485
20321 /* 53485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(53561), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2489 //
20322 /* 53492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20323 /* 53496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20324 /* 53500 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20325 /* 53504 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20326 /* 53508 */ // MIs[1] Operand 1
20327 /* 53508 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20328 /* 53513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20329 /* 53518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20330 /* 53523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20331 /* 53525 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20332 /* 53525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20333 /* 53528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20334 /* 53532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20335 /* 53537 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20336 /* 53541 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20337 /* 53545 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20338 /* 53547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20339 /* 53550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20340 /* 53552 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20341 /* 53554 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20342 /* 53557 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20343 /* 53559 */ GIR_RootConstrainSelectedInstOperands,
20344 /* 53560 */ // GIR_Coverage, 2489,
20345 /* 53560 */ GIR_EraseRootFromParent_Done,
20346 /* 53561 */ // Label 1458: @53561
20347 /* 53561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(53637), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2492 //
20348 /* 53568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20349 /* 53572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20350 /* 53576 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20351 /* 53580 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20352 /* 53584 */ // MIs[1] Operand 1
20353 /* 53584 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20354 /* 53589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20355 /* 53594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20356 /* 53599 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20357 /* 53601 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20358 /* 53601 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20359 /* 53604 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20360 /* 53608 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20361 /* 53613 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20362 /* 53617 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20363 /* 53621 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20364 /* 53623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20365 /* 53626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20366 /* 53628 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20367 /* 53630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20368 /* 53633 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20369 /* 53635 */ GIR_RootConstrainSelectedInstOperands,
20370 /* 53636 */ // GIR_Coverage, 2492,
20371 /* 53636 */ GIR_EraseRootFromParent_Done,
20372 /* 53637 */ // Label 1459: @53637
20373 /* 53637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(53713), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2493 //
20374 /* 53644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20375 /* 53648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20376 /* 53652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20377 /* 53656 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20378 /* 53660 */ // MIs[1] Operand 1
20379 /* 53660 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20380 /* 53665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20381 /* 53670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20382 /* 53675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20383 /* 53677 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20384 /* 53677 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20385 /* 53680 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20386 /* 53684 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20387 /* 53689 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20388 /* 53693 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20389 /* 53697 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20390 /* 53699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20391 /* 53702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20392 /* 53704 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20393 /* 53706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20394 /* 53709 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20395 /* 53711 */ GIR_RootConstrainSelectedInstOperands,
20396 /* 53712 */ // GIR_Coverage, 2493,
20397 /* 53712 */ GIR_EraseRootFromParent_Done,
20398 /* 53713 */ // Label 1460: @53713
20399 /* 53713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(53789), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2496 //
20400 /* 53720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20401 /* 53724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20402 /* 53728 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20403 /* 53732 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20404 /* 53736 */ // MIs[1] Operand 1
20405 /* 53736 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20406 /* 53741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20407 /* 53746 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20408 /* 53751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20409 /* 53753 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20410 /* 53753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20411 /* 53756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20412 /* 53760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20413 /* 53765 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20414 /* 53769 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20415 /* 53773 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20416 /* 53775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20417 /* 53778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20418 /* 53780 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20419 /* 53782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20420 /* 53785 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20421 /* 53787 */ GIR_RootConstrainSelectedInstOperands,
20422 /* 53788 */ // GIR_Coverage, 2496,
20423 /* 53788 */ GIR_EraseRootFromParent_Done,
20424 /* 53789 */ // Label 1461: @53789
20425 /* 53789 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1462*/ GIMT_Encode4(53865), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2499 //
20426 /* 53796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20427 /* 53800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20428 /* 53804 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20429 /* 53808 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20430 /* 53812 */ // MIs[1] Operand 1
20431 /* 53812 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20432 /* 53817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20433 /* 53822 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20434 /* 53827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20435 /* 53829 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20436 /* 53829 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20437 /* 53832 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20438 /* 53836 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20439 /* 53841 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20440 /* 53845 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20441 /* 53849 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20442 /* 53851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20443 /* 53854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20444 /* 53856 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20445 /* 53858 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20446 /* 53861 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20447 /* 53863 */ GIR_RootConstrainSelectedInstOperands,
20448 /* 53864 */ // GIR_Coverage, 2499,
20449 /* 53864 */ GIR_EraseRootFromParent_Done,
20450 /* 53865 */ // Label 1462: @53865
20451 /* 53865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(53941), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2502 //
20452 /* 53872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20453 /* 53876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20454 /* 53880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20455 /* 53884 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20456 /* 53888 */ // MIs[1] Operand 1
20457 /* 53888 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20458 /* 53893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20459 /* 53898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20460 /* 53903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20461 /* 53905 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20462 /* 53905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20463 /* 53908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20464 /* 53912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20465 /* 53917 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20466 /* 53921 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20467 /* 53925 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20468 /* 53927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20469 /* 53930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20470 /* 53932 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20471 /* 53934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20472 /* 53937 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20473 /* 53939 */ GIR_RootConstrainSelectedInstOperands,
20474 /* 53940 */ // GIR_Coverage, 2502,
20475 /* 53940 */ GIR_EraseRootFromParent_Done,
20476 /* 53941 */ // Label 1463: @53941
20477 /* 53941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(54017), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2503 //
20478 /* 53948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20479 /* 53952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20480 /* 53956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20481 /* 53960 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20482 /* 53964 */ // MIs[1] Operand 1
20483 /* 53964 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20484 /* 53969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20485 /* 53974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20486 /* 53979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20487 /* 53981 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20488 /* 53981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20489 /* 53984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20490 /* 53988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20491 /* 53993 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20492 /* 53997 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20493 /* 54001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20494 /* 54003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20495 /* 54006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20496 /* 54008 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20497 /* 54010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20498 /* 54013 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20499 /* 54015 */ GIR_RootConstrainSelectedInstOperands,
20500 /* 54016 */ // GIR_Coverage, 2503,
20501 /* 54016 */ GIR_EraseRootFromParent_Done,
20502 /* 54017 */ // Label 1464: @54017
20503 /* 54017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(54093), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2506 //
20504 /* 54024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20505 /* 54028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20506 /* 54032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20507 /* 54036 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20508 /* 54040 */ // MIs[1] Operand 1
20509 /* 54040 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20510 /* 54045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20511 /* 54050 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20512 /* 54055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20513 /* 54057 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20514 /* 54057 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20515 /* 54060 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20516 /* 54064 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20517 /* 54069 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20518 /* 54073 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20519 /* 54077 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20520 /* 54079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20521 /* 54082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20522 /* 54084 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20523 /* 54086 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20524 /* 54089 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20525 /* 54091 */ GIR_RootConstrainSelectedInstOperands,
20526 /* 54092 */ // GIR_Coverage, 2506,
20527 /* 54092 */ GIR_EraseRootFromParent_Done,
20528 /* 54093 */ // Label 1465: @54093
20529 /* 54093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1466*/ GIMT_Encode4(54169), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2507 //
20530 /* 54100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20531 /* 54104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20532 /* 54108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20533 /* 54112 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20534 /* 54116 */ // MIs[1] Operand 1
20535 /* 54116 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20536 /* 54121 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20537 /* 54126 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20538 /* 54131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20539 /* 54133 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20540 /* 54133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20541 /* 54136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20542 /* 54140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20543 /* 54145 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20544 /* 54149 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20545 /* 54153 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20546 /* 54155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20547 /* 54158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20548 /* 54160 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20549 /* 54162 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20550 /* 54165 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20551 /* 54167 */ GIR_RootConstrainSelectedInstOperands,
20552 /* 54168 */ // GIR_Coverage, 2507,
20553 /* 54168 */ GIR_EraseRootFromParent_Done,
20554 /* 54169 */ // Label 1466: @54169
20555 /* 54169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(54245), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2510 //
20556 /* 54176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20557 /* 54180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20558 /* 54184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20559 /* 54188 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20560 /* 54192 */ // MIs[1] Operand 1
20561 /* 54192 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20562 /* 54197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20563 /* 54202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20564 /* 54207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20565 /* 54209 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20566 /* 54209 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20567 /* 54212 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20568 /* 54216 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20569 /* 54221 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20570 /* 54225 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20571 /* 54229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20572 /* 54231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20573 /* 54234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20574 /* 54236 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20575 /* 54238 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20576 /* 54241 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20577 /* 54243 */ GIR_RootConstrainSelectedInstOperands,
20578 /* 54244 */ // GIR_Coverage, 2510,
20579 /* 54244 */ GIR_EraseRootFromParent_Done,
20580 /* 54245 */ // Label 1467: @54245
20581 /* 54245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(54321), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2513 //
20582 /* 54252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20583 /* 54256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20584 /* 54260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20585 /* 54264 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20586 /* 54268 */ // MIs[1] Operand 1
20587 /* 54268 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20588 /* 54273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20589 /* 54278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20590 /* 54283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20591 /* 54285 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20592 /* 54285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20593 /* 54288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20594 /* 54292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20595 /* 54297 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20596 /* 54301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20597 /* 54305 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20598 /* 54307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20599 /* 54310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20600 /* 54312 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20601 /* 54314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20602 /* 54317 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20603 /* 54319 */ GIR_RootConstrainSelectedInstOperands,
20604 /* 54320 */ // GIR_Coverage, 2513,
20605 /* 54320 */ GIR_EraseRootFromParent_Done,
20606 /* 54321 */ // Label 1468: @54321
20607 /* 54321 */ GIM_Reject,
20608 /* 54322 */ // Label 1456: @54322
20609 /* 54322 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(54796),
20610 /* 54327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20611 /* 54331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20612 /* 54335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20613 /* 54339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(54415), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2555 //
20614 /* 54346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20615 /* 54350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20616 /* 54354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20617 /* 54358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20618 /* 54362 */ // MIs[1] Operand 1
20619 /* 54362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20620 /* 54367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20621 /* 54372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20622 /* 54377 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20623 /* 54379 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20624 /* 54379 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20625 /* 54382 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20626 /* 54386 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20627 /* 54391 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20628 /* 54395 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20629 /* 54399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20630 /* 54401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20631 /* 54404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20632 /* 54406 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20633 /* 54408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20634 /* 54411 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20635 /* 54413 */ GIR_RootConstrainSelectedInstOperands,
20636 /* 54414 */ // GIR_Coverage, 2555,
20637 /* 54414 */ GIR_EraseRootFromParent_Done,
20638 /* 54415 */ // Label 1470: @54415
20639 /* 54415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(54491), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2556 //
20640 /* 54422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20641 /* 54426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20642 /* 54430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20643 /* 54434 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20644 /* 54438 */ // MIs[1] Operand 1
20645 /* 54438 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20646 /* 54443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20647 /* 54448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20648 /* 54453 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20649 /* 54455 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20650 /* 54455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20651 /* 54458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20652 /* 54462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20653 /* 54467 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20654 /* 54471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20655 /* 54475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20656 /* 54477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20657 /* 54480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20658 /* 54482 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20659 /* 54484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20660 /* 54487 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20661 /* 54489 */ GIR_RootConstrainSelectedInstOperands,
20662 /* 54490 */ // GIR_Coverage, 2556,
20663 /* 54490 */ GIR_EraseRootFromParent_Done,
20664 /* 54491 */ // Label 1471: @54491
20665 /* 54491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1472*/ GIMT_Encode4(54567), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2559 //
20666 /* 54498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20667 /* 54502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20668 /* 54506 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20669 /* 54510 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20670 /* 54514 */ // MIs[1] Operand 1
20671 /* 54514 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20672 /* 54519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20673 /* 54524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20674 /* 54529 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20675 /* 54531 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20676 /* 54531 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20677 /* 54534 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20678 /* 54538 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20679 /* 54543 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20680 /* 54547 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20681 /* 54551 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20682 /* 54553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20683 /* 54556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20684 /* 54558 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20685 /* 54560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20686 /* 54563 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20687 /* 54565 */ GIR_RootConstrainSelectedInstOperands,
20688 /* 54566 */ // GIR_Coverage, 2559,
20689 /* 54566 */ GIR_EraseRootFromParent_Done,
20690 /* 54567 */ // Label 1472: @54567
20691 /* 54567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1473*/ GIMT_Encode4(54643), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2560 //
20692 /* 54574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20693 /* 54578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20694 /* 54582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20695 /* 54586 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20696 /* 54590 */ // MIs[1] Operand 1
20697 /* 54590 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20698 /* 54595 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20699 /* 54600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20700 /* 54605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20701 /* 54607 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20702 /* 54607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20703 /* 54610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20704 /* 54614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20705 /* 54619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20706 /* 54623 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20707 /* 54627 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20708 /* 54629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20709 /* 54632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20710 /* 54634 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20711 /* 54636 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20712 /* 54639 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20713 /* 54641 */ GIR_RootConstrainSelectedInstOperands,
20714 /* 54642 */ // GIR_Coverage, 2560,
20715 /* 54642 */ GIR_EraseRootFromParent_Done,
20716 /* 54643 */ // Label 1473: @54643
20717 /* 54643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1474*/ GIMT_Encode4(54719), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2563 //
20718 /* 54650 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20719 /* 54654 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20720 /* 54658 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20721 /* 54662 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20722 /* 54666 */ // MIs[1] Operand 1
20723 /* 54666 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20724 /* 54671 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20725 /* 54676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20726 /* 54681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20727 /* 54683 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20728 /* 54683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20729 /* 54686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20730 /* 54690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20731 /* 54695 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20732 /* 54699 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20733 /* 54703 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20734 /* 54705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20735 /* 54708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20736 /* 54710 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20737 /* 54712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20738 /* 54715 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20739 /* 54717 */ GIR_RootConstrainSelectedInstOperands,
20740 /* 54718 */ // GIR_Coverage, 2563,
20741 /* 54718 */ GIR_EraseRootFromParent_Done,
20742 /* 54719 */ // Label 1474: @54719
20743 /* 54719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1475*/ GIMT_Encode4(54795), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2565 //
20744 /* 54726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20745 /* 54730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20746 /* 54734 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20747 /* 54738 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20748 /* 54742 */ // MIs[1] Operand 1
20749 /* 54742 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20750 /* 54747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20751 /* 54752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20752 /* 54757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20753 /* 54759 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20754 /* 54759 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20755 /* 54762 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20756 /* 54766 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20757 /* 54771 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20758 /* 54775 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20759 /* 54779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20760 /* 54781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20761 /* 54784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20762 /* 54786 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20763 /* 54788 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20764 /* 54791 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20765 /* 54793 */ GIR_RootConstrainSelectedInstOperands,
20766 /* 54794 */ // GIR_Coverage, 2565,
20767 /* 54794 */ GIR_EraseRootFromParent_Done,
20768 /* 54795 */ // Label 1475: @54795
20769 /* 54795 */ GIM_Reject,
20770 /* 54796 */ // Label 1469: @54796
20771 /* 54796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1476*/ GIMT_Encode4(54826), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 370 //
20772 /* 54803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20773 /* 54807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20774 /* 54811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20775 /* 54815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20776 /* 54819 */ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
20777 /* 54819 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
20778 /* 54824 */ GIR_RootConstrainSelectedInstOperands,
20779 /* 54825 */ // GIR_Coverage, 370,
20780 /* 54825 */ GIR_Done,
20781 /* 54826 */ // Label 1476: @54826
20782 /* 54826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(54856), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 372 //
20783 /* 54833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20784 /* 54837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20785 /* 54841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20786 /* 54845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20787 /* 54849 */ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
20788 /* 54849 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
20789 /* 54854 */ GIR_RootConstrainSelectedInstOperands,
20790 /* 54855 */ // GIR_Coverage, 372,
20791 /* 54855 */ GIR_Done,
20792 /* 54856 */ // Label 1477: @54856
20793 /* 54856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(54892), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1849 //
20794 /* 54863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20795 /* 54867 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20796 /* 54871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20797 /* 54875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20798 /* 54879 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20799 /* 54879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20800 /* 54882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20801 /* 54884 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20802 /* 54886 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20803 /* 54888 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20804 /* 54890 */ GIR_RootConstrainSelectedInstOperands,
20805 /* 54891 */ // GIR_Coverage, 1849,
20806 /* 54891 */ GIR_EraseRootFromParent_Done,
20807 /* 54892 */ // Label 1478: @54892
20808 /* 54892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(54928), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1904 //
20809 /* 54899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20810 /* 54903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20811 /* 54907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20812 /* 54911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20813 /* 54915 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20814 /* 54915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20815 /* 54918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20816 /* 54920 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20817 /* 54922 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20818 /* 54924 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20819 /* 54926 */ GIR_RootConstrainSelectedInstOperands,
20820 /* 54927 */ // GIR_Coverage, 1904,
20821 /* 54927 */ GIR_EraseRootFromParent_Done,
20822 /* 54928 */ // Label 1479: @54928
20823 /* 54928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(54964), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2131 //
20824 /* 54935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20825 /* 54939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20826 /* 54943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20827 /* 54947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20828 /* 54951 */ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20829 /* 54951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
20830 /* 54954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20831 /* 54956 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20832 /* 54958 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20833 /* 54960 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
20834 /* 54962 */ GIR_RootConstrainSelectedInstOperands,
20835 /* 54963 */ // GIR_Coverage, 2131,
20836 /* 54963 */ GIR_EraseRootFromParent_Done,
20837 /* 54964 */ // Label 1480: @54964
20838 /* 54964 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(55026),
20839 /* 54969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20840 /* 54973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20841 /* 54977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20842 /* 54981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20843 /* 54985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(55005), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2500 //
20844 /* 54992 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20845 /* 54992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20846 /* 54995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20847 /* 54997 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20848 /* 54999 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20849 /* 55001 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20850 /* 55003 */ GIR_RootConstrainSelectedInstOperands,
20851 /* 55004 */ // GIR_Coverage, 2500,
20852 /* 55004 */ GIR_EraseRootFromParent_Done,
20853 /* 55005 */ // Label 1482: @55005
20854 /* 55005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(55025), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2514 //
20855 /* 55012 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20856 /* 55012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20857 /* 55015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20858 /* 55017 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20859 /* 55019 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20860 /* 55021 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20861 /* 55023 */ GIR_RootConstrainSelectedInstOperands,
20862 /* 55024 */ // GIR_Coverage, 2514,
20863 /* 55024 */ GIR_EraseRootFromParent_Done,
20864 /* 55025 */ // Label 1483: @55025
20865 /* 55025 */ GIM_Reject,
20866 /* 55026 */ // Label 1481: @55026
20867 /* 55026 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(55166),
20868 /* 55031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20869 /* 55035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(55067), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2566 //
20870 /* 55042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20871 /* 55046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20872 /* 55050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20873 /* 55054 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20874 /* 55054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20875 /* 55057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20876 /* 55059 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20877 /* 55061 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20878 /* 55063 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20879 /* 55065 */ GIR_RootConstrainSelectedInstOperands,
20880 /* 55066 */ // GIR_Coverage, 2566,
20881 /* 55066 */ GIR_EraseRootFromParent_Done,
20882 /* 55067 */ // Label 1485: @55067
20883 /* 55067 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(55165),
20884 /* 55072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20885 /* 55076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20886 /* 55080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(55122), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 1999 //
20887 /* 55087 */ // (select:{ *:[f32] } i32:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$t, FGR32Opnd:{ *:[f32] }:$f) => (SEL_S:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$cond, FGR32:{ *:[i32] }), FGR32Opnd:{ *:[f32] }:$f, FGR32Opnd:{ *:[f32] }:$t)
20888 /* 55087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20889 /* 55090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20890 /* 55094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20891 /* 55099 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20892 /* 55103 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
20893 /* 55108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
20894 /* 55111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20895 /* 55113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20896 /* 55116 */ GIR_RootToRootCopy, /*OpIdx*/3, // f
20897 /* 55118 */ GIR_RootToRootCopy, /*OpIdx*/2, // t
20898 /* 55120 */ GIR_RootConstrainSelectedInstOperands,
20899 /* 55121 */ // GIR_Coverage, 1999,
20900 /* 55121 */ GIR_EraseRootFromParent_Done,
20901 /* 55122 */ // Label 1487: @55122
20902 /* 55122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(55164), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 2624 //
20903 /* 55129 */ // (select:{ *:[f32] } i32:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$t, FGR32Opnd:{ *:[f32] }:$f) => (SEL_S_MMR6:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$cond, FGR32:{ *:[i32] }), FGR32Opnd:{ *:[f32] }:$f, FGR32Opnd:{ *:[f32] }:$t)
20904 /* 55129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20905 /* 55132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
20906 /* 55136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20907 /* 55141 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20908 /* 55145 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
20909 /* 55150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
20910 /* 55153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20911 /* 55155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20912 /* 55158 */ GIR_RootToRootCopy, /*OpIdx*/3, // f
20913 /* 55160 */ GIR_RootToRootCopy, /*OpIdx*/2, // t
20914 /* 55162 */ GIR_RootConstrainSelectedInstOperands,
20915 /* 55163 */ // GIR_Coverage, 2624,
20916 /* 55163 */ GIR_EraseRootFromParent_Done,
20917 /* 55164 */ // Label 1488: @55164
20918 /* 55164 */ GIM_Reject,
20919 /* 55165 */ // Label 1486: @55165
20920 /* 55165 */ GIM_Reject,
20921 /* 55166 */ // Label 1484: @55166
20922 /* 55166 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(55304),
20923 /* 55171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20924 /* 55175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(55239), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1996 //
20925 /* 55182 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20926 /* 55182 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20927 /* 55185 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
20928 /* 55189 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20929 /* 55194 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20930 /* 55198 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20931 /* 55202 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20932 /* 55204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20933 /* 55207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
20934 /* 55211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20935 /* 55216 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20936 /* 55220 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20937 /* 55224 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20938 /* 55226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
20939 /* 55229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20940 /* 55231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20941 /* 55234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20942 /* 55237 */ GIR_RootConstrainSelectedInstOperands,
20943 /* 55238 */ // GIR_Coverage, 1996,
20944 /* 55238 */ GIR_EraseRootFromParent_Done,
20945 /* 55239 */ // Label 1490: @55239
20946 /* 55239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(55303), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2583 //
20947 /* 55246 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20948 /* 55246 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20949 /* 55249 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
20950 /* 55253 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20951 /* 55258 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20952 /* 55262 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20953 /* 55266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20954 /* 55268 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20955 /* 55271 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
20956 /* 55275 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20957 /* 55280 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20958 /* 55284 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20959 /* 55288 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20960 /* 55290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
20961 /* 55293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20962 /* 55295 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20963 /* 55298 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20964 /* 55301 */ GIR_RootConstrainSelectedInstOperands,
20965 /* 55302 */ // GIR_Coverage, 2583,
20966 /* 55302 */ GIR_EraseRootFromParent_Done,
20967 /* 55303 */ // Label 1491: @55303
20968 /* 55303 */ GIM_Reject,
20969 /* 55304 */ // Label 1489: @55304
20970 /* 55304 */ GIM_Reject,
20971 /* 55305 */ // Label 1399: @55305
20972 /* 55305 */ GIM_Reject,
20973 /* 55306 */ // Label 1397: @55306
20974 /* 55306 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(55390),
20975 /* 55311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20976 /* 55314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20977 /* 55317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(55353), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1888 //
20978 /* 55324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20979 /* 55328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20980 /* 55332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20981 /* 55336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20982 /* 55340 */ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
20983 /* 55340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20984 /* 55343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20985 /* 55345 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20986 /* 55347 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20987 /* 55349 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20988 /* 55351 */ GIR_RootConstrainSelectedInstOperands,
20989 /* 55352 */ // GIR_Coverage, 1888,
20990 /* 55352 */ GIR_EraseRootFromParent_Done,
20991 /* 55353 */ // Label 1493: @55353
20992 /* 55353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(55389), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1917 //
20993 /* 55360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20994 /* 55364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20995 /* 55368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20996 /* 55372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20997 /* 55376 */ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
20998 /* 55376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20999 /* 55379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21000 /* 55381 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21001 /* 55383 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
21002 /* 55385 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21003 /* 55387 */ GIR_RootConstrainSelectedInstOperands,
21004 /* 55388 */ // GIR_Coverage, 1917,
21005 /* 55388 */ GIR_EraseRootFromParent_Done,
21006 /* 55389 */ // Label 1494: @55389
21007 /* 55389 */ GIM_Reject,
21008 /* 55390 */ // Label 1492: @55390
21009 /* 55390 */ GIM_Reject,
21010 /* 55391 */ // Label 1398: @55391
21011 /* 55391 */ GIM_Reject,
21012 /* 55392 */ // Label 1390: @55392
21013 /* 55392 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1497*/ GIMT_Encode4(59441),
21014 /* 55403 */ /*GILLT_s32*//*Label 1495*/ GIMT_Encode4(55411),
21015 /* 55407 */ /*GILLT_s64*//*Label 1496*/ GIMT_Encode4(59288),
21016 /* 55411 */ // Label 1495: @55411
21017 /* 55411 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(59287),
21018 /* 55416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21019 /* 55419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21020 /* 55422 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(55656),
21021 /* 55427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21022 /* 55431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21023 /* 55435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21024 /* 55439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(55493), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1876 //
21025 /* 55446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21026 /* 55450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21027 /* 55454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21028 /* 55458 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21029 /* 55462 */ // MIs[1] Operand 1
21030 /* 55462 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21031 /* 55467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21032 /* 55472 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21033 /* 55476 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21034 /* 55478 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
21035 /* 55478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21036 /* 55481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21037 /* 55483 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21038 /* 55485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21039 /* 55489 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21040 /* 55491 */ GIR_RootConstrainSelectedInstOperands,
21041 /* 55492 */ // GIR_Coverage, 1876,
21042 /* 55492 */ GIR_EraseRootFromParent_Done,
21043 /* 55493 */ // Label 1500: @55493
21044 /* 55493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(55547), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1880 //
21045 /* 55500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21046 /* 55504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21047 /* 55508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21048 /* 55512 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21049 /* 55516 */ // MIs[1] Operand 1
21050 /* 55516 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21051 /* 55521 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21052 /* 55526 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21053 /* 55530 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21054 /* 55532 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
21055 /* 55532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
21056 /* 55535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21057 /* 55537 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21058 /* 55539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21059 /* 55543 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21060 /* 55545 */ GIR_RootConstrainSelectedInstOperands,
21061 /* 55546 */ // GIR_Coverage, 1880,
21062 /* 55546 */ GIR_EraseRootFromParent_Done,
21063 /* 55547 */ // Label 1501: @55547
21064 /* 55547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(55601), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1886 //
21065 /* 55554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21066 /* 55558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21067 /* 55562 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21068 /* 55566 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21069 /* 55570 */ // MIs[1] Operand 1
21070 /* 55570 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21071 /* 55575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21072 /* 55580 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21073 /* 55584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21074 /* 55586 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
21075 /* 55586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
21076 /* 55589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21077 /* 55591 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21078 /* 55593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21079 /* 55597 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21080 /* 55599 */ GIR_RootConstrainSelectedInstOperands,
21081 /* 55600 */ // GIR_Coverage, 1886,
21082 /* 55600 */ GIR_EraseRootFromParent_Done,
21083 /* 55601 */ // Label 1502: @55601
21084 /* 55601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(55655), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1892 //
21085 /* 55608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21086 /* 55612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21087 /* 55616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21088 /* 55620 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21089 /* 55624 */ // MIs[1] Operand 1
21090 /* 55624 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21091 /* 55629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21092 /* 55634 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21093 /* 55638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21094 /* 55640 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
21095 /* 55640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
21096 /* 55643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21097 /* 55645 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21098 /* 55647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21099 /* 55651 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21100 /* 55653 */ GIR_RootConstrainSelectedInstOperands,
21101 /* 55654 */ // GIR_Coverage, 1892,
21102 /* 55654 */ GIR_EraseRootFromParent_Done,
21103 /* 55655 */ // Label 1503: @55655
21104 /* 55655 */ GIM_Reject,
21105 /* 55656 */ // Label 1499: @55656
21106 /* 55656 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(55782),
21107 /* 55661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21108 /* 55665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21109 /* 55669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21110 /* 55673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1505*/ GIMT_Encode4(55727), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1928 //
21111 /* 55680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21112 /* 55684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21113 /* 55688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21114 /* 55692 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21115 /* 55696 */ // MIs[1] Operand 1
21116 /* 55696 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21117 /* 55701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21118 /* 55706 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21119 /* 55710 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21120 /* 55712 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21121 /* 55712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21122 /* 55715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21123 /* 55717 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21124 /* 55719 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21125 /* 55723 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21126 /* 55725 */ GIR_RootConstrainSelectedInstOperands,
21127 /* 55726 */ // GIR_Coverage, 1928,
21128 /* 55726 */ GIR_EraseRootFromParent_Done,
21129 /* 55727 */ // Label 1505: @55727
21130 /* 55727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(55781), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1931 //
21131 /* 55734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21132 /* 55738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21133 /* 55742 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21134 /* 55746 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21135 /* 55750 */ // MIs[1] Operand 1
21136 /* 55750 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21137 /* 55755 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21138 /* 55760 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21139 /* 55764 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21140 /* 55766 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21141 /* 55766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
21142 /* 55769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21143 /* 55771 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21144 /* 55773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21145 /* 55777 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21146 /* 55779 */ GIR_RootConstrainSelectedInstOperands,
21147 /* 55780 */ // GIR_Coverage, 1931,
21148 /* 55780 */ GIR_EraseRootFromParent_Done,
21149 /* 55781 */ // Label 1506: @55781
21150 /* 55781 */ GIM_Reject,
21151 /* 55782 */ // Label 1504: @55782
21152 /* 55782 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(56016),
21153 /* 55787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21154 /* 55791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21155 /* 55795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21156 /* 55799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(55853), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1949 //
21157 /* 55806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21158 /* 55810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21159 /* 55814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21160 /* 55818 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21161 /* 55822 */ // MIs[1] Operand 1
21162 /* 55822 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21163 /* 55827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21164 /* 55832 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21165 /* 55836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21166 /* 55838 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
21167 /* 55838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21168 /* 55841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21169 /* 55843 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21170 /* 55845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21171 /* 55849 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21172 /* 55851 */ GIR_RootConstrainSelectedInstOperands,
21173 /* 55852 */ // GIR_Coverage, 1949,
21174 /* 55852 */ GIR_EraseRootFromParent_Done,
21175 /* 55853 */ // Label 1508: @55853
21176 /* 55853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(55907), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1951 //
21177 /* 55860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21178 /* 55864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21179 /* 55868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21180 /* 55872 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21181 /* 55876 */ // MIs[1] Operand 1
21182 /* 55876 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21183 /* 55881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21184 /* 55886 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21185 /* 55890 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21186 /* 55892 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
21187 /* 55892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
21188 /* 55895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21189 /* 55897 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21190 /* 55899 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21191 /* 55903 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21192 /* 55905 */ GIR_RootConstrainSelectedInstOperands,
21193 /* 55906 */ // GIR_Coverage, 1951,
21194 /* 55906 */ GIR_EraseRootFromParent_Done,
21195 /* 55907 */ // Label 1509: @55907
21196 /* 55907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(55961), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1954 //
21197 /* 55914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21198 /* 55918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21199 /* 55922 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21200 /* 55926 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21201 /* 55930 */ // MIs[1] Operand 1
21202 /* 55930 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21203 /* 55935 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21204 /* 55940 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21205 /* 55944 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21206 /* 55946 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
21207 /* 55946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
21208 /* 55949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21209 /* 55951 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21210 /* 55953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21211 /* 55957 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21212 /* 55959 */ GIR_RootConstrainSelectedInstOperands,
21213 /* 55960 */ // GIR_Coverage, 1954,
21214 /* 55960 */ GIR_EraseRootFromParent_Done,
21215 /* 55961 */ // Label 1510: @55961
21216 /* 55961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(56015), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1957 //
21217 /* 55968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21218 /* 55972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21219 /* 55976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21220 /* 55980 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21221 /* 55984 */ // MIs[1] Operand 1
21222 /* 55984 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21223 /* 55989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21224 /* 55994 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21225 /* 55998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21226 /* 56000 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
21227 /* 56000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
21228 /* 56003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21229 /* 56005 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21230 /* 56007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21231 /* 56011 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21232 /* 56013 */ GIR_RootConstrainSelectedInstOperands,
21233 /* 56014 */ // GIR_Coverage, 1957,
21234 /* 56014 */ GIR_EraseRootFromParent_Done,
21235 /* 56015 */ // Label 1511: @56015
21236 /* 56015 */ GIM_Reject,
21237 /* 56016 */ // Label 1507: @56016
21238 /* 56016 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(56142),
21239 /* 56021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21240 /* 56025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21241 /* 56029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21242 /* 56033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(56087), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2577 //
21243 /* 56040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21244 /* 56044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21245 /* 56048 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21246 /* 56052 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21247 /* 56056 */ // MIs[1] Operand 1
21248 /* 56056 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21249 /* 56061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21250 /* 56066 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21251 /* 56070 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21252 /* 56072 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21253 /* 56072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21254 /* 56075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21255 /* 56077 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21256 /* 56079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21257 /* 56083 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21258 /* 56085 */ GIR_RootConstrainSelectedInstOperands,
21259 /* 56086 */ // GIR_Coverage, 2577,
21260 /* 56086 */ GIR_EraseRootFromParent_Done,
21261 /* 56087 */ // Label 1513: @56087
21262 /* 56087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(56141), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2580 //
21263 /* 56094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21264 /* 56098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21265 /* 56102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21266 /* 56106 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21267 /* 56110 */ // MIs[1] Operand 1
21268 /* 56110 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21269 /* 56115 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21270 /* 56120 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21271 /* 56124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21272 /* 56126 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21273 /* 56126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
21274 /* 56129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21275 /* 56131 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21276 /* 56133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21277 /* 56137 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21278 /* 56139 */ GIR_RootConstrainSelectedInstOperands,
21279 /* 56140 */ // GIR_Coverage, 2580,
21280 /* 56140 */ GIR_EraseRootFromParent_Done,
21281 /* 56141 */ // Label 1514: @56141
21282 /* 56141 */ GIM_Reject,
21283 /* 56142 */ // Label 1512: @56142
21284 /* 56142 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(57072),
21285 /* 56147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21286 /* 56151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21287 /* 56155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21288 /* 56159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(56235), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1851 //
21289 /* 56166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21290 /* 56170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21291 /* 56174 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21292 /* 56178 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21293 /* 56182 */ // MIs[1] Operand 1
21294 /* 56182 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21295 /* 56187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21296 /* 56192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21297 /* 56197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21298 /* 56199 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21299 /* 56199 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21300 /* 56202 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21301 /* 56206 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21302 /* 56211 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21303 /* 56215 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21304 /* 56219 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21305 /* 56221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21306 /* 56224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21307 /* 56226 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21308 /* 56228 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21309 /* 56231 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21310 /* 56233 */ GIR_RootConstrainSelectedInstOperands,
21311 /* 56234 */ // GIR_Coverage, 1851,
21312 /* 56234 */ GIR_EraseRootFromParent_Done,
21313 /* 56235 */ // Label 1516: @56235
21314 /* 56235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(56311), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1852 //
21315 /* 56242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21316 /* 56246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21317 /* 56250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21318 /* 56254 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21319 /* 56258 */ // MIs[1] Operand 1
21320 /* 56258 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21321 /* 56263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21322 /* 56268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21323 /* 56273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21324 /* 56275 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21325 /* 56275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21326 /* 56278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21327 /* 56282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21328 /* 56287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21329 /* 56291 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21330 /* 56295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21331 /* 56297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21332 /* 56300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21333 /* 56302 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21334 /* 56304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21335 /* 56307 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21336 /* 56309 */ GIR_RootConstrainSelectedInstOperands,
21337 /* 56310 */ // GIR_Coverage, 1852,
21338 /* 56310 */ GIR_EraseRootFromParent_Done,
21339 /* 56311 */ // Label 1517: @56311
21340 /* 56311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(56387), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1855 //
21341 /* 56318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21342 /* 56322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21343 /* 56326 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21344 /* 56330 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21345 /* 56334 */ // MIs[1] Operand 1
21346 /* 56334 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21347 /* 56339 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21348 /* 56344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21349 /* 56349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21350 /* 56351 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21351 /* 56351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21352 /* 56354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21353 /* 56358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21354 /* 56363 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21355 /* 56367 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21356 /* 56371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21357 /* 56373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21358 /* 56376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21359 /* 56378 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21360 /* 56380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21361 /* 56383 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21362 /* 56385 */ GIR_RootConstrainSelectedInstOperands,
21363 /* 56386 */ // GIR_Coverage, 1855,
21364 /* 56386 */ GIR_EraseRootFromParent_Done,
21365 /* 56387 */ // Label 1518: @56387
21366 /* 56387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(56463), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1856 //
21367 /* 56394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21368 /* 56398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21369 /* 56402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21370 /* 56406 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21371 /* 56410 */ // MIs[1] Operand 1
21372 /* 56410 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21373 /* 56415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21374 /* 56420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21375 /* 56425 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21376 /* 56427 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21377 /* 56427 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21378 /* 56430 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21379 /* 56434 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21380 /* 56439 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21381 /* 56443 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21382 /* 56447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21383 /* 56449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21384 /* 56452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21385 /* 56454 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21386 /* 56456 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21387 /* 56459 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21388 /* 56461 */ GIR_RootConstrainSelectedInstOperands,
21389 /* 56462 */ // GIR_Coverage, 1856,
21390 /* 56462 */ GIR_EraseRootFromParent_Done,
21391 /* 56463 */ // Label 1519: @56463
21392 /* 56463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(56539), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1867 //
21393 /* 56470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21394 /* 56474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21395 /* 56478 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21396 /* 56482 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21397 /* 56486 */ // MIs[1] Operand 1
21398 /* 56486 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21399 /* 56491 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21400 /* 56496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21401 /* 56501 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21402 /* 56503 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21403 /* 56503 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21404 /* 56506 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21405 /* 56510 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21406 /* 56515 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21407 /* 56519 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21408 /* 56523 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21409 /* 56525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21410 /* 56528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21411 /* 56530 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21412 /* 56532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21413 /* 56535 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21414 /* 56537 */ GIR_RootConstrainSelectedInstOperands,
21415 /* 56538 */ // GIR_Coverage, 1867,
21416 /* 56538 */ GIR_EraseRootFromParent_Done,
21417 /* 56539 */ // Label 1520: @56539
21418 /* 56539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(56615), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1868 //
21419 /* 56546 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21420 /* 56550 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21421 /* 56554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21422 /* 56558 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21423 /* 56562 */ // MIs[1] Operand 1
21424 /* 56562 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21425 /* 56567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21426 /* 56572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21427 /* 56577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21428 /* 56579 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21429 /* 56579 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21430 /* 56582 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21431 /* 56586 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21432 /* 56591 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21433 /* 56595 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21434 /* 56599 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21435 /* 56601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21436 /* 56604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21437 /* 56606 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21438 /* 56608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21439 /* 56611 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21440 /* 56613 */ GIR_RootConstrainSelectedInstOperands,
21441 /* 56614 */ // GIR_Coverage, 1868,
21442 /* 56614 */ GIR_EraseRootFromParent_Done,
21443 /* 56615 */ // Label 1521: @56615
21444 /* 56615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1522*/ GIMT_Encode4(56691), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1871 //
21445 /* 56622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21446 /* 56626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21447 /* 56630 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21448 /* 56634 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21449 /* 56638 */ // MIs[1] Operand 1
21450 /* 56638 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21451 /* 56643 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21452 /* 56648 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21453 /* 56653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21454 /* 56655 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21455 /* 56655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21456 /* 56658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21457 /* 56662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21458 /* 56667 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21459 /* 56671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21460 /* 56675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21461 /* 56677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21462 /* 56680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21463 /* 56682 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21464 /* 56684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21465 /* 56687 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21466 /* 56689 */ GIR_RootConstrainSelectedInstOperands,
21467 /* 56690 */ // GIR_Coverage, 1871,
21468 /* 56690 */ GIR_EraseRootFromParent_Done,
21469 /* 56691 */ // Label 1522: @56691
21470 /* 56691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1523*/ GIMT_Encode4(56767), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1872 //
21471 /* 56698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21472 /* 56702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21473 /* 56706 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21474 /* 56710 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21475 /* 56714 */ // MIs[1] Operand 1
21476 /* 56714 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21477 /* 56719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21478 /* 56724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21479 /* 56729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21480 /* 56731 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21481 /* 56731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21482 /* 56734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21483 /* 56738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21484 /* 56743 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21485 /* 56747 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21486 /* 56751 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21487 /* 56753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21488 /* 56756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21489 /* 56758 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21490 /* 56760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21491 /* 56763 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21492 /* 56765 */ GIR_RootConstrainSelectedInstOperands,
21493 /* 56766 */ // GIR_Coverage, 1872,
21494 /* 56766 */ GIR_EraseRootFromParent_Done,
21495 /* 56767 */ // Label 1523: @56767
21496 /* 56767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1524*/ GIMT_Encode4(56843), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1875 //
21497 /* 56774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21498 /* 56778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21499 /* 56782 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21500 /* 56786 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21501 /* 56790 */ // MIs[1] Operand 1
21502 /* 56790 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21503 /* 56795 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21504 /* 56800 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21505 /* 56805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21506 /* 56807 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21507 /* 56807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21508 /* 56810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21509 /* 56814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21510 /* 56819 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21511 /* 56823 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21512 /* 56827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21513 /* 56829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21514 /* 56832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21515 /* 56834 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21516 /* 56836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21517 /* 56839 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21518 /* 56841 */ GIR_RootConstrainSelectedInstOperands,
21519 /* 56842 */ // GIR_Coverage, 1875,
21520 /* 56842 */ GIR_EraseRootFromParent_Done,
21521 /* 56843 */ // Label 1524: @56843
21522 /* 56843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1525*/ GIMT_Encode4(56919), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1879 //
21523 /* 56850 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21524 /* 56854 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21525 /* 56858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21526 /* 56862 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21527 /* 56866 */ // MIs[1] Operand 1
21528 /* 56866 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21529 /* 56871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21530 /* 56876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21531 /* 56881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21532 /* 56883 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21533 /* 56883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21534 /* 56886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21535 /* 56890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21536 /* 56895 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21537 /* 56899 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21538 /* 56903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21539 /* 56905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
21540 /* 56908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21541 /* 56910 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21542 /* 56912 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21543 /* 56915 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21544 /* 56917 */ GIR_RootConstrainSelectedInstOperands,
21545 /* 56918 */ // GIR_Coverage, 1879,
21546 /* 56918 */ GIR_EraseRootFromParent_Done,
21547 /* 56919 */ // Label 1525: @56919
21548 /* 56919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1526*/ GIMT_Encode4(56995), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1884 //
21549 /* 56926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21550 /* 56930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21551 /* 56934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21552 /* 56938 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21553 /* 56942 */ // MIs[1] Operand 1
21554 /* 56942 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21555 /* 56947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21556 /* 56952 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21557 /* 56957 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21558 /* 56959 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21559 /* 56959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21560 /* 56962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21561 /* 56966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21562 /* 56971 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21563 /* 56975 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21564 /* 56979 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21565 /* 56981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
21566 /* 56984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21567 /* 56986 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21568 /* 56988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21569 /* 56991 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21570 /* 56993 */ GIR_RootConstrainSelectedInstOperands,
21571 /* 56994 */ // GIR_Coverage, 1884,
21572 /* 56994 */ GIR_EraseRootFromParent_Done,
21573 /* 56995 */ // Label 1526: @56995
21574 /* 56995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1527*/ GIMT_Encode4(57071), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1890 //
21575 /* 57002 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21576 /* 57006 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21577 /* 57010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21578 /* 57014 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21579 /* 57018 */ // MIs[1] Operand 1
21580 /* 57018 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21581 /* 57023 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21582 /* 57028 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21583 /* 57033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21584 /* 57035 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21585 /* 57035 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21586 /* 57038 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21587 /* 57042 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21588 /* 57047 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21589 /* 57051 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21590 /* 57055 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21591 /* 57057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
21592 /* 57060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21593 /* 57062 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21594 /* 57064 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21595 /* 57067 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21596 /* 57069 */ GIR_RootConstrainSelectedInstOperands,
21597 /* 57070 */ // GIR_Coverage, 1890,
21598 /* 57070 */ GIR_EraseRootFromParent_Done,
21599 /* 57071 */ // Label 1527: @57071
21600 /* 57071 */ GIM_Reject,
21601 /* 57072 */ // Label 1515: @57072
21602 /* 57072 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(57546),
21603 /* 57077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21604 /* 57081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21605 /* 57085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21606 /* 57089 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1529*/ GIMT_Encode4(57165), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1919 //
21607 /* 57096 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21608 /* 57100 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21609 /* 57104 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21610 /* 57108 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21611 /* 57112 */ // MIs[1] Operand 1
21612 /* 57112 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21613 /* 57117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21614 /* 57122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21615 /* 57127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21616 /* 57129 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21617 /* 57129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21618 /* 57132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21619 /* 57136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21620 /* 57141 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21621 /* 57145 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21622 /* 57149 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21623 /* 57151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21624 /* 57154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21625 /* 57156 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21626 /* 57158 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21627 /* 57161 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21628 /* 57163 */ GIR_RootConstrainSelectedInstOperands,
21629 /* 57164 */ // GIR_Coverage, 1919,
21630 /* 57164 */ GIR_EraseRootFromParent_Done,
21631 /* 57165 */ // Label 1529: @57165
21632 /* 57165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1530*/ GIMT_Encode4(57241), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1920 //
21633 /* 57172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21634 /* 57176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21635 /* 57180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21636 /* 57184 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21637 /* 57188 */ // MIs[1] Operand 1
21638 /* 57188 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21639 /* 57193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21640 /* 57198 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21641 /* 57203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21642 /* 57205 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21643 /* 57205 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21644 /* 57208 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21645 /* 57212 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21646 /* 57217 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21647 /* 57221 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21648 /* 57225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21649 /* 57227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21650 /* 57230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21651 /* 57232 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21652 /* 57234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21653 /* 57237 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21654 /* 57239 */ GIR_RootConstrainSelectedInstOperands,
21655 /* 57240 */ // GIR_Coverage, 1920,
21656 /* 57240 */ GIR_EraseRootFromParent_Done,
21657 /* 57241 */ // Label 1530: @57241
21658 /* 57241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1531*/ GIMT_Encode4(57317), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1923 //
21659 /* 57248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21660 /* 57252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21661 /* 57256 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21662 /* 57260 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21663 /* 57264 */ // MIs[1] Operand 1
21664 /* 57264 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21665 /* 57269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21666 /* 57274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21667 /* 57279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21668 /* 57281 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21669 /* 57281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21670 /* 57284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21671 /* 57288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21672 /* 57293 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21673 /* 57297 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21674 /* 57301 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21675 /* 57303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21676 /* 57306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21677 /* 57308 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21678 /* 57310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21679 /* 57313 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21680 /* 57315 */ GIR_RootConstrainSelectedInstOperands,
21681 /* 57316 */ // GIR_Coverage, 1923,
21682 /* 57316 */ GIR_EraseRootFromParent_Done,
21683 /* 57317 */ // Label 1531: @57317
21684 /* 57317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1532*/ GIMT_Encode4(57393), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1924 //
21685 /* 57324 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21686 /* 57328 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21687 /* 57332 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21688 /* 57336 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21689 /* 57340 */ // MIs[1] Operand 1
21690 /* 57340 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21691 /* 57345 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21692 /* 57350 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21693 /* 57355 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21694 /* 57357 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21695 /* 57357 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21696 /* 57360 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21697 /* 57364 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21698 /* 57369 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21699 /* 57373 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21700 /* 57377 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21701 /* 57379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21702 /* 57382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21703 /* 57384 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21704 /* 57386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21705 /* 57389 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21706 /* 57391 */ GIR_RootConstrainSelectedInstOperands,
21707 /* 57392 */ // GIR_Coverage, 1924,
21708 /* 57392 */ GIR_EraseRootFromParent_Done,
21709 /* 57393 */ // Label 1532: @57393
21710 /* 57393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1533*/ GIMT_Encode4(57469), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1927 //
21711 /* 57400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21712 /* 57404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21713 /* 57408 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21714 /* 57412 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21715 /* 57416 */ // MIs[1] Operand 1
21716 /* 57416 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21717 /* 57421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21718 /* 57426 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21719 /* 57431 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21720 /* 57433 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21721 /* 57433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21722 /* 57436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21723 /* 57440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21724 /* 57445 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21725 /* 57449 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21726 /* 57453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21727 /* 57455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21728 /* 57458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21729 /* 57460 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21730 /* 57462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21731 /* 57465 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21732 /* 57467 */ GIR_RootConstrainSelectedInstOperands,
21733 /* 57468 */ // GIR_Coverage, 1927,
21734 /* 57468 */ GIR_EraseRootFromParent_Done,
21735 /* 57469 */ // Label 1533: @57469
21736 /* 57469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1534*/ GIMT_Encode4(57545), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1929 //
21737 /* 57476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21738 /* 57480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21739 /* 57484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21740 /* 57488 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21741 /* 57492 */ // MIs[1] Operand 1
21742 /* 57492 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21743 /* 57497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21744 /* 57502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21745 /* 57507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21746 /* 57509 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21747 /* 57509 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21748 /* 57512 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21749 /* 57516 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21750 /* 57521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21751 /* 57525 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21752 /* 57529 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21753 /* 57531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
21754 /* 57534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21755 /* 57536 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21756 /* 57538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21757 /* 57541 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21758 /* 57543 */ GIR_RootConstrainSelectedInstOperands,
21759 /* 57544 */ // GIR_Coverage, 1929,
21760 /* 57544 */ GIR_EraseRootFromParent_Done,
21761 /* 57545 */ // Label 1534: @57545
21762 /* 57545 */ GIM_Reject,
21763 /* 57546 */ // Label 1528: @57546
21764 /* 57546 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(58476),
21765 /* 57551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21766 /* 57555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21767 /* 57559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21768 /* 57563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1536*/ GIMT_Encode4(57639), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1932 //
21769 /* 57570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21770 /* 57574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21771 /* 57578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21772 /* 57582 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21773 /* 57586 */ // MIs[1] Operand 1
21774 /* 57586 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21775 /* 57591 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21776 /* 57596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21777 /* 57601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21778 /* 57603 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21779 /* 57603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21780 /* 57606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21781 /* 57610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21782 /* 57615 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21783 /* 57619 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21784 /* 57623 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21785 /* 57625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21786 /* 57628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21787 /* 57630 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21788 /* 57632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21789 /* 57635 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21790 /* 57637 */ GIR_RootConstrainSelectedInstOperands,
21791 /* 57638 */ // GIR_Coverage, 1932,
21792 /* 57638 */ GIR_EraseRootFromParent_Done,
21793 /* 57639 */ // Label 1536: @57639
21794 /* 57639 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1537*/ GIMT_Encode4(57715), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1933 //
21795 /* 57646 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21796 /* 57650 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21797 /* 57654 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21798 /* 57658 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21799 /* 57662 */ // MIs[1] Operand 1
21800 /* 57662 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21801 /* 57667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21802 /* 57672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21803 /* 57677 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21804 /* 57679 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21805 /* 57679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21806 /* 57682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21807 /* 57686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21808 /* 57691 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21809 /* 57695 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21810 /* 57699 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21811 /* 57701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21812 /* 57704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21813 /* 57706 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21814 /* 57708 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21815 /* 57711 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21816 /* 57713 */ GIR_RootConstrainSelectedInstOperands,
21817 /* 57714 */ // GIR_Coverage, 1933,
21818 /* 57714 */ GIR_EraseRootFromParent_Done,
21819 /* 57715 */ // Label 1537: @57715
21820 /* 57715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1538*/ GIMT_Encode4(57791), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1936 //
21821 /* 57722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21822 /* 57726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21823 /* 57730 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21824 /* 57734 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21825 /* 57738 */ // MIs[1] Operand 1
21826 /* 57738 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21827 /* 57743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21828 /* 57748 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21829 /* 57753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21830 /* 57755 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21831 /* 57755 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21832 /* 57758 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21833 /* 57762 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21834 /* 57767 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21835 /* 57771 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21836 /* 57775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21837 /* 57777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21838 /* 57780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21839 /* 57782 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21840 /* 57784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21841 /* 57787 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21842 /* 57789 */ GIR_RootConstrainSelectedInstOperands,
21843 /* 57790 */ // GIR_Coverage, 1936,
21844 /* 57790 */ GIR_EraseRootFromParent_Done,
21845 /* 57791 */ // Label 1538: @57791
21846 /* 57791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1539*/ GIMT_Encode4(57867), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1937 //
21847 /* 57798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21848 /* 57802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21849 /* 57806 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21850 /* 57810 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21851 /* 57814 */ // MIs[1] Operand 1
21852 /* 57814 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21853 /* 57819 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21854 /* 57824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21855 /* 57829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21856 /* 57831 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21857 /* 57831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21858 /* 57834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21859 /* 57838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21860 /* 57843 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21861 /* 57847 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21862 /* 57851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21863 /* 57853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21864 /* 57856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21865 /* 57858 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21866 /* 57860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21867 /* 57863 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21868 /* 57865 */ GIR_RootConstrainSelectedInstOperands,
21869 /* 57866 */ // GIR_Coverage, 1937,
21870 /* 57866 */ GIR_EraseRootFromParent_Done,
21871 /* 57867 */ // Label 1539: @57867
21872 /* 57867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1540*/ GIMT_Encode4(57943), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1940 //
21873 /* 57874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21874 /* 57878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21875 /* 57882 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21876 /* 57886 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21877 /* 57890 */ // MIs[1] Operand 1
21878 /* 57890 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21879 /* 57895 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21880 /* 57900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21881 /* 57905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21882 /* 57907 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21883 /* 57907 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21884 /* 57910 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21885 /* 57914 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21886 /* 57919 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21887 /* 57923 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21888 /* 57927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21889 /* 57929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21890 /* 57932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21891 /* 57934 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21892 /* 57936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21893 /* 57939 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21894 /* 57941 */ GIR_RootConstrainSelectedInstOperands,
21895 /* 57942 */ // GIR_Coverage, 1940,
21896 /* 57942 */ GIR_EraseRootFromParent_Done,
21897 /* 57943 */ // Label 1540: @57943
21898 /* 57943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1541*/ GIMT_Encode4(58019), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1941 //
21899 /* 57950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21900 /* 57954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21901 /* 57958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21902 /* 57962 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21903 /* 57966 */ // MIs[1] Operand 1
21904 /* 57966 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21905 /* 57971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21906 /* 57976 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21907 /* 57981 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21908 /* 57983 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21909 /* 57983 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21910 /* 57986 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21911 /* 57990 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21912 /* 57995 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21913 /* 57999 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21914 /* 58003 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21915 /* 58005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21916 /* 58008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21917 /* 58010 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21918 /* 58012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21919 /* 58015 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21920 /* 58017 */ GIR_RootConstrainSelectedInstOperands,
21921 /* 58018 */ // GIR_Coverage, 1941,
21922 /* 58018 */ GIR_EraseRootFromParent_Done,
21923 /* 58019 */ // Label 1541: @58019
21924 /* 58019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1542*/ GIMT_Encode4(58095), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1944 //
21925 /* 58026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21926 /* 58030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21927 /* 58034 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21928 /* 58038 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21929 /* 58042 */ // MIs[1] Operand 1
21930 /* 58042 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21931 /* 58047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21932 /* 58052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21933 /* 58057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21934 /* 58059 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21935 /* 58059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21936 /* 58062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21937 /* 58066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21938 /* 58071 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21939 /* 58075 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21940 /* 58079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21941 /* 58081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21942 /* 58084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21943 /* 58086 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21944 /* 58088 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21945 /* 58091 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21946 /* 58093 */ GIR_RootConstrainSelectedInstOperands,
21947 /* 58094 */ // GIR_Coverage, 1944,
21948 /* 58094 */ GIR_EraseRootFromParent_Done,
21949 /* 58095 */ // Label 1542: @58095
21950 /* 58095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1543*/ GIMT_Encode4(58171), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1945 //
21951 /* 58102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21952 /* 58106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21953 /* 58110 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21954 /* 58114 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21955 /* 58118 */ // MIs[1] Operand 1
21956 /* 58118 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21957 /* 58123 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21958 /* 58128 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21959 /* 58133 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21960 /* 58135 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21961 /* 58135 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21962 /* 58138 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21963 /* 58142 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21964 /* 58147 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21965 /* 58151 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21966 /* 58155 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21967 /* 58157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21968 /* 58160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21969 /* 58162 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21970 /* 58164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21971 /* 58167 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21972 /* 58169 */ GIR_RootConstrainSelectedInstOperands,
21973 /* 58170 */ // GIR_Coverage, 1945,
21974 /* 58170 */ GIR_EraseRootFromParent_Done,
21975 /* 58171 */ // Label 1543: @58171
21976 /* 58171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1544*/ GIMT_Encode4(58247), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1948 //
21977 /* 58178 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21978 /* 58182 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21979 /* 58186 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21980 /* 58190 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21981 /* 58194 */ // MIs[1] Operand 1
21982 /* 58194 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21983 /* 58199 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21984 /* 58204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21985 /* 58209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21986 /* 58211 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21987 /* 58211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21988 /* 58214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21989 /* 58218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21990 /* 58223 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21991 /* 58227 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21992 /* 58231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21993 /* 58233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21994 /* 58236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21995 /* 58238 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21996 /* 58240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21997 /* 58243 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21998 /* 58245 */ GIR_RootConstrainSelectedInstOperands,
21999 /* 58246 */ // GIR_Coverage, 1948,
22000 /* 58246 */ GIR_EraseRootFromParent_Done,
22001 /* 58247 */ // Label 1544: @58247
22002 /* 58247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1545*/ GIMT_Encode4(58323), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1950 //
22003 /* 58254 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22004 /* 58258 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22005 /* 58262 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22006 /* 58266 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22007 /* 58270 */ // MIs[1] Operand 1
22008 /* 58270 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22009 /* 58275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22010 /* 58280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22011 /* 58285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22012 /* 58287 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
22013 /* 58287 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22014 /* 58290 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22015 /* 58294 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22016 /* 58299 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22017 /* 58303 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22018 /* 58307 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22019 /* 58309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
22020 /* 58312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22021 /* 58314 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22022 /* 58316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22023 /* 58319 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22024 /* 58321 */ GIR_RootConstrainSelectedInstOperands,
22025 /* 58322 */ // GIR_Coverage, 1950,
22026 /* 58322 */ GIR_EraseRootFromParent_Done,
22027 /* 58323 */ // Label 1545: @58323
22028 /* 58323 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1546*/ GIMT_Encode4(58399), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1952 //
22029 /* 58330 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22030 /* 58334 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22031 /* 58338 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22032 /* 58342 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22033 /* 58346 */ // MIs[1] Operand 1
22034 /* 58346 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22035 /* 58351 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22036 /* 58356 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22037 /* 58361 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22038 /* 58363 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
22039 /* 58363 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22040 /* 58366 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22041 /* 58370 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22042 /* 58375 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22043 /* 58379 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22044 /* 58383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22045 /* 58385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22046 /* 58388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22047 /* 58390 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22048 /* 58392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22049 /* 58395 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22050 /* 58397 */ GIR_RootConstrainSelectedInstOperands,
22051 /* 58398 */ // GIR_Coverage, 1952,
22052 /* 58398 */ GIR_EraseRootFromParent_Done,
22053 /* 58399 */ // Label 1546: @58399
22054 /* 58399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1547*/ GIMT_Encode4(58475), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1955 //
22055 /* 58406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22056 /* 58410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22057 /* 58414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22058 /* 58418 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22059 /* 58422 */ // MIs[1] Operand 1
22060 /* 58422 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22061 /* 58427 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22062 /* 58432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22063 /* 58437 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22064 /* 58439 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
22065 /* 58439 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22066 /* 58442 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22067 /* 58446 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22068 /* 58451 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22069 /* 58455 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22070 /* 58459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22071 /* 58461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22072 /* 58464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22073 /* 58466 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22074 /* 58468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22075 /* 58471 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22076 /* 58473 */ GIR_RootConstrainSelectedInstOperands,
22077 /* 58474 */ // GIR_Coverage, 1955,
22078 /* 58474 */ GIR_EraseRootFromParent_Done,
22079 /* 58475 */ // Label 1547: @58475
22080 /* 58475 */ GIM_Reject,
22081 /* 58476 */ // Label 1535: @58476
22082 /* 58476 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(58950),
22083 /* 58481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22084 /* 58485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22085 /* 58489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22086 /* 58493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(58569), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2568 //
22087 /* 58500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22088 /* 58504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22089 /* 58508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22090 /* 58512 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22091 /* 58516 */ // MIs[1] Operand 1
22092 /* 58516 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22093 /* 58521 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22094 /* 58526 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22095 /* 58531 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22096 /* 58533 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22097 /* 58533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22098 /* 58536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
22099 /* 58540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22100 /* 58545 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22101 /* 58549 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22102 /* 58553 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22103 /* 58555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22104 /* 58558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22105 /* 58560 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22106 /* 58562 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22107 /* 58565 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22108 /* 58567 */ GIR_RootConstrainSelectedInstOperands,
22109 /* 58568 */ // GIR_Coverage, 2568,
22110 /* 58568 */ GIR_EraseRootFromParent_Done,
22111 /* 58569 */ // Label 1549: @58569
22112 /* 58569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1550*/ GIMT_Encode4(58645), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2569 //
22113 /* 58576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22114 /* 58580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22115 /* 58584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22116 /* 58588 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22117 /* 58592 */ // MIs[1] Operand 1
22118 /* 58592 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22119 /* 58597 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22120 /* 58602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22121 /* 58607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22122 /* 58609 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22123 /* 58609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22124 /* 58612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
22125 /* 58616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22126 /* 58621 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22127 /* 58625 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22128 /* 58629 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22129 /* 58631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22130 /* 58634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22131 /* 58636 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22132 /* 58638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22133 /* 58641 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22134 /* 58643 */ GIR_RootConstrainSelectedInstOperands,
22135 /* 58644 */ // GIR_Coverage, 2569,
22136 /* 58644 */ GIR_EraseRootFromParent_Done,
22137 /* 58645 */ // Label 1550: @58645
22138 /* 58645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1551*/ GIMT_Encode4(58721), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2572 //
22139 /* 58652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22140 /* 58656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22141 /* 58660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22142 /* 58664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22143 /* 58668 */ // MIs[1] Operand 1
22144 /* 58668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22145 /* 58673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22146 /* 58678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22147 /* 58683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22148 /* 58685 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22149 /* 58685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22150 /* 58688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
22151 /* 58692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22152 /* 58697 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22153 /* 58701 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22154 /* 58705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22155 /* 58707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22156 /* 58710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22157 /* 58712 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22158 /* 58714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22159 /* 58717 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22160 /* 58719 */ GIR_RootConstrainSelectedInstOperands,
22161 /* 58720 */ // GIR_Coverage, 2572,
22162 /* 58720 */ GIR_EraseRootFromParent_Done,
22163 /* 58721 */ // Label 1551: @58721
22164 /* 58721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1552*/ GIMT_Encode4(58797), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2573 //
22165 /* 58728 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22166 /* 58732 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22167 /* 58736 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22168 /* 58740 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22169 /* 58744 */ // MIs[1] Operand 1
22170 /* 58744 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22171 /* 58749 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22172 /* 58754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22173 /* 58759 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22174 /* 58761 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22175 /* 58761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22176 /* 58764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
22177 /* 58768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22178 /* 58773 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22179 /* 58777 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22180 /* 58781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22181 /* 58783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22182 /* 58786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22183 /* 58788 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22184 /* 58790 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22185 /* 58793 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22186 /* 58795 */ GIR_RootConstrainSelectedInstOperands,
22187 /* 58796 */ // GIR_Coverage, 2573,
22188 /* 58796 */ GIR_EraseRootFromParent_Done,
22189 /* 58797 */ // Label 1552: @58797
22190 /* 58797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1553*/ GIMT_Encode4(58873), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2576 //
22191 /* 58804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22192 /* 58808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22193 /* 58812 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22194 /* 58816 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22195 /* 58820 */ // MIs[1] Operand 1
22196 /* 58820 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22197 /* 58825 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22198 /* 58830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22199 /* 58835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22200 /* 58837 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22201 /* 58837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22202 /* 58840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22203 /* 58844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22204 /* 58849 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22205 /* 58853 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22206 /* 58857 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22207 /* 58859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22208 /* 58862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22209 /* 58864 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22210 /* 58866 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22211 /* 58869 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22212 /* 58871 */ GIR_RootConstrainSelectedInstOperands,
22213 /* 58872 */ // GIR_Coverage, 2576,
22214 /* 58872 */ GIR_EraseRootFromParent_Done,
22215 /* 58873 */ // Label 1553: @58873
22216 /* 58873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1554*/ GIMT_Encode4(58949), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2578 //
22217 /* 58880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22218 /* 58884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22219 /* 58888 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22220 /* 58892 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22221 /* 58896 */ // MIs[1] Operand 1
22222 /* 58896 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22223 /* 58901 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22224 /* 58906 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22225 /* 58911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22226 /* 58913 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22227 /* 58913 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22228 /* 58916 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22229 /* 58920 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22230 /* 58925 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22231 /* 58929 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22232 /* 58933 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22233 /* 58935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22234 /* 58938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22235 /* 58940 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22236 /* 58942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22237 /* 58945 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22238 /* 58947 */ GIR_RootConstrainSelectedInstOperands,
22239 /* 58948 */ // GIR_Coverage, 2578,
22240 /* 58948 */ GIR_EraseRootFromParent_Done,
22241 /* 58949 */ // Label 1554: @58949
22242 /* 58949 */ GIM_Reject,
22243 /* 58950 */ // Label 1548: @58950
22244 /* 58950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1555*/ GIMT_Encode4(58980), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 371 //
22245 /* 58957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22246 /* 58961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22247 /* 58965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22248 /* 58969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22249 /* 58973 */ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
22250 /* 58973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
22251 /* 58978 */ GIR_RootConstrainSelectedInstOperands,
22252 /* 58979 */ // GIR_Coverage, 371,
22253 /* 58979 */ GIR_Done,
22254 /* 58980 */ // Label 1555: @58980
22255 /* 58980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1556*/ GIMT_Encode4(59010), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32), // Rule ID 373 //
22256 /* 58987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22257 /* 58991 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22258 /* 58995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22259 /* 58999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22260 /* 59003 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
22261 /* 59003 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
22262 /* 59008 */ GIR_RootConstrainSelectedInstOperands,
22263 /* 59009 */ // GIR_Coverage, 373,
22264 /* 59009 */ GIR_Done,
22265 /* 59010 */ // Label 1556: @59010
22266 /* 59010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1557*/ GIMT_Encode4(59040), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32), // Rule ID 374 //
22267 /* 59017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22268 /* 59021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22269 /* 59025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22270 /* 59029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22271 /* 59033 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
22272 /* 59033 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
22273 /* 59038 */ GIR_RootConstrainSelectedInstOperands,
22274 /* 59039 */ // GIR_Coverage, 374,
22275 /* 59039 */ GIR_Done,
22276 /* 59040 */ // Label 1557: @59040
22277 /* 59040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1558*/ GIMT_Encode4(59076), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1885 //
22278 /* 59047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22279 /* 59051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22280 /* 59055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22281 /* 59059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22282 /* 59063 */ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
22283 /* 59063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22284 /* 59066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22285 /* 59068 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22286 /* 59070 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22287 /* 59072 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22288 /* 59074 */ GIR_RootConstrainSelectedInstOperands,
22289 /* 59075 */ // GIR_Coverage, 1885,
22290 /* 59075 */ GIR_EraseRootFromParent_Done,
22291 /* 59076 */ // Label 1558: @59076
22292 /* 59076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1559*/ GIMT_Encode4(59112), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1930 //
22293 /* 59083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22294 /* 59087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22295 /* 59091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22296 /* 59095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22297 /* 59099 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22298 /* 59099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22299 /* 59102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22300 /* 59104 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22301 /* 59106 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22302 /* 59108 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22303 /* 59110 */ GIR_RootConstrainSelectedInstOperands,
22304 /* 59111 */ // GIR_Coverage, 1930,
22305 /* 59111 */ GIR_EraseRootFromParent_Done,
22306 /* 59112 */ // Label 1559: @59112
22307 /* 59112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1560*/ GIMT_Encode4(59148), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1953 //
22308 /* 59119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22309 /* 59123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22310 /* 59127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22311 /* 59131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22312 /* 59135 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
22313 /* 59135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22314 /* 59138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22315 /* 59140 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22316 /* 59142 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22317 /* 59144 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22318 /* 59146 */ GIR_RootConstrainSelectedInstOperands,
22319 /* 59147 */ // GIR_Coverage, 1953,
22320 /* 59147 */ GIR_EraseRootFromParent_Done,
22321 /* 59148 */ // Label 1560: @59148
22322 /* 59148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1561*/ GIMT_Encode4(59184), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2579 //
22323 /* 59155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22324 /* 59159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22325 /* 59163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22326 /* 59167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22327 /* 59171 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22328 /* 59171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22329 /* 59174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22330 /* 59176 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22331 /* 59178 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22332 /* 59180 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22333 /* 59182 */ GIR_RootConstrainSelectedInstOperands,
22334 /* 59183 */ // GIR_Coverage, 2579,
22335 /* 59183 */ GIR_EraseRootFromParent_Done,
22336 /* 59184 */ // Label 1561: @59184
22337 /* 59184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1562*/ GIMT_Encode4(59286), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2040 //
22338 /* 59191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22339 /* 59195 */ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
22340 /* 59195 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
22341 /* 59198 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22342 /* 59202 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22343 /* 59207 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
22344 /* 59211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
22345 /* 59213 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
22346 /* 59216 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22347 /* 59220 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22348 /* 59225 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
22349 /* 59229 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
22350 /* 59232 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
22351 /* 59234 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22352 /* 59237 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22353 /* 59241 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22354 /* 59246 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22355 /* 59250 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22356 /* 59252 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22357 /* 59255 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22358 /* 59259 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22359 /* 59264 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22360 /* 59268 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
22361 /* 59271 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22362 /* 59273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22363 /* 59276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22364 /* 59278 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22365 /* 59281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
22366 /* 59284 */ GIR_RootConstrainSelectedInstOperands,
22367 /* 59285 */ // GIR_Coverage, 2040,
22368 /* 59285 */ GIR_EraseRootFromParent_Done,
22369 /* 59286 */ // Label 1562: @59286
22370 /* 59286 */ GIM_Reject,
22371 /* 59287 */ // Label 1498: @59287
22372 /* 59287 */ GIM_Reject,
22373 /* 59288 */ // Label 1496: @59288
22374 /* 59288 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(59440),
22375 /* 59293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22376 /* 59296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22377 /* 59299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1564*/ GIMT_Encode4(59335), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1891 //
22378 /* 59306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22379 /* 59310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22380 /* 59314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22381 /* 59318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22382 /* 59322 */ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
22383 /* 59322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22384 /* 59325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22385 /* 59327 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22386 /* 59329 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22387 /* 59331 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22388 /* 59333 */ GIR_RootConstrainSelectedInstOperands,
22389 /* 59334 */ // GIR_Coverage, 1891,
22390 /* 59334 */ GIR_EraseRootFromParent_Done,
22391 /* 59335 */ // Label 1564: @59335
22392 /* 59335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1565*/ GIMT_Encode4(59371), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1956 //
22393 /* 59342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22394 /* 59346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22395 /* 59350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22396 /* 59354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22397 /* 59358 */ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
22398 /* 59358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22399 /* 59361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22400 /* 59363 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22401 /* 59365 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22402 /* 59367 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22403 /* 59369 */ GIR_RootConstrainSelectedInstOperands,
22404 /* 59370 */ // GIR_Coverage, 1956,
22405 /* 59370 */ GIR_EraseRootFromParent_Done,
22406 /* 59371 */ // Label 1565: @59371
22407 /* 59371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1566*/ GIMT_Encode4(59439), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 2029 //
22408 /* 59378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22409 /* 59382 */ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
22410 /* 59382 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22411 /* 59385 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22412 /* 59389 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22413 /* 59394 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22414 /* 59398 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22415 /* 59402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22416 /* 59404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22417 /* 59407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22418 /* 59411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22419 /* 59416 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22420 /* 59420 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22421 /* 59424 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22422 /* 59426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22423 /* 59429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22424 /* 59431 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22425 /* 59434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22426 /* 59437 */ GIR_RootConstrainSelectedInstOperands,
22427 /* 59438 */ // GIR_Coverage, 2029,
22428 /* 59438 */ GIR_EraseRootFromParent_Done,
22429 /* 59439 */ // Label 1566: @59439
22430 /* 59439 */ GIM_Reject,
22431 /* 59440 */ // Label 1563: @59440
22432 /* 59440 */ GIM_Reject,
22433 /* 59441 */ // Label 1497: @59441
22434 /* 59441 */ GIM_Reject,
22435 /* 59442 */ // Label 1391: @59442
22436 /* 59442 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(59533),
22437 /* 59447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
22438 /* 59450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22439 /* 59453 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22440 /* 59456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22441 /* 59460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22442 /* 59464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22443 /* 59468 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22444 /* 59472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1568*/ GIMT_Encode4(59492), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 631 //
22445 /* 59479 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22446 /* 59479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
22447 /* 59482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22448 /* 59484 */ GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
22449 /* 59486 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
22450 /* 59488 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
22451 /* 59490 */ GIR_RootConstrainSelectedInstOperands,
22452 /* 59491 */ // GIR_Coverage, 631,
22453 /* 59491 */ GIR_EraseRootFromParent_Done,
22454 /* 59492 */ // Label 1568: @59492
22455 /* 59492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1569*/ GIMT_Encode4(59512), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 633 //
22456 /* 59499 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22457 /* 59499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
22458 /* 59502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22459 /* 59504 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
22460 /* 59506 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22461 /* 59508 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
22462 /* 59510 */ GIR_RootConstrainSelectedInstOperands,
22463 /* 59511 */ // GIR_Coverage, 633,
22464 /* 59511 */ GIR_EraseRootFromParent_Done,
22465 /* 59512 */ // Label 1569: @59512
22466 /* 59512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1570*/ GIMT_Encode4(59532), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 643 //
22467 /* 59519 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22468 /* 59519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
22469 /* 59522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22470 /* 59524 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22471 /* 59526 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22472 /* 59528 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22473 /* 59530 */ GIR_RootConstrainSelectedInstOperands,
22474 /* 59531 */ // GIR_Coverage, 643,
22475 /* 59531 */ GIR_EraseRootFromParent_Done,
22476 /* 59532 */ // Label 1570: @59532
22477 /* 59532 */ GIM_Reject,
22478 /* 59533 */ // Label 1567: @59533
22479 /* 59533 */ GIM_Reject,
22480 /* 59534 */ // Label 1392: @59534
22481 /* 59534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1571*/ GIMT_Encode4(59579), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 644 //
22482 /* 59541 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22483 /* 59544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22484 /* 59547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22485 /* 59550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22486 /* 59554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22487 /* 59558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22488 /* 59562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22489 /* 59566 */ // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
22490 /* 59566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
22491 /* 59569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22492 /* 59571 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22493 /* 59573 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22494 /* 59575 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22495 /* 59577 */ GIR_RootConstrainSelectedInstOperands,
22496 /* 59578 */ // GIR_Coverage, 644,
22497 /* 59578 */ GIR_EraseRootFromParent_Done,
22498 /* 59579 */ // Label 1571: @59579
22499 /* 59579 */ GIM_Reject,
22500 /* 59580 */ // Label 1393: @59580
22501 /* 59580 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(59651),
22502 /* 59585 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22503 /* 59588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22504 /* 59591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22505 /* 59594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22506 /* 59598 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22507 /* 59602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22508 /* 59606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22509 /* 59610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1573*/ GIMT_Encode4(59630), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 645 //
22510 /* 59617 */ // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
22511 /* 59617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
22512 /* 59620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22513 /* 59622 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22514 /* 59624 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22515 /* 59626 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22516 /* 59628 */ GIR_RootConstrainSelectedInstOperands,
22517 /* 59629 */ // GIR_Coverage, 645,
22518 /* 59629 */ GIR_EraseRootFromParent_Done,
22519 /* 59630 */ // Label 1573: @59630
22520 /* 59630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1574*/ GIMT_Encode4(59650), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 647 //
22521 /* 59637 */ // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22522 /* 59637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
22523 /* 59640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22524 /* 59642 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22525 /* 59644 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22526 /* 59646 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22527 /* 59648 */ GIR_RootConstrainSelectedInstOperands,
22528 /* 59649 */ // GIR_Coverage, 647,
22529 /* 59649 */ GIR_EraseRootFromParent_Done,
22530 /* 59650 */ // Label 1574: @59650
22531 /* 59650 */ GIM_Reject,
22532 /* 59651 */ // Label 1572: @59651
22533 /* 59651 */ GIM_Reject,
22534 /* 59652 */ // Label 1394: @59652
22535 /* 59652 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(59723),
22536 /* 59657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22537 /* 59660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22538 /* 59663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22539 /* 59666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22540 /* 59670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22541 /* 59674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22542 /* 59678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22543 /* 59682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1576*/ GIMT_Encode4(59702), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 646 //
22544 /* 59689 */ // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
22545 /* 59689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
22546 /* 59692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22547 /* 59694 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22548 /* 59696 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22549 /* 59698 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22550 /* 59700 */ GIR_RootConstrainSelectedInstOperands,
22551 /* 59701 */ // GIR_Coverage, 646,
22552 /* 59701 */ GIR_EraseRootFromParent_Done,
22553 /* 59702 */ // Label 1576: @59702
22554 /* 59702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1577*/ GIMT_Encode4(59722), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 648 //
22555 /* 59709 */ // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22556 /* 59709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
22557 /* 59712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22558 /* 59714 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22559 /* 59716 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22560 /* 59718 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22561 /* 59720 */ GIR_RootConstrainSelectedInstOperands,
22562 /* 59721 */ // GIR_Coverage, 648,
22563 /* 59721 */ GIR_EraseRootFromParent_Done,
22564 /* 59722 */ // Label 1577: @59722
22565 /* 59722 */ GIM_Reject,
22566 /* 59723 */ // Label 1575: @59723
22567 /* 59723 */ GIM_Reject,
22568 /* 59724 */ // Label 1395: @59724
22569 /* 59724 */ GIM_Reject,
22570 /* 59725 */ // Label 45: @59725
22571 /* 59725 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1580*/ GIMT_Encode4(59830),
22572 /* 59736 */ /*GILLT_s32*//*Label 1578*/ GIMT_Encode4(59744),
22573 /* 59740 */ /*GILLT_s64*//*Label 1579*/ GIMT_Encode4(59797),
22574 /* 59744 */ // Label 1578: @59744
22575 /* 59744 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(59796),
22576 /* 59749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22577 /* 59752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22578 /* 59755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22579 /* 59759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22580 /* 59763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22581 /* 59767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1582*/ GIMT_Encode4(59781), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 392 //
22582 /* 59774 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22583 /* 59774 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
22584 /* 59779 */ GIR_RootConstrainSelectedInstOperands,
22585 /* 59780 */ // GIR_Coverage, 392,
22586 /* 59780 */ GIR_Done,
22587 /* 59781 */ // Label 1582: @59781
22588 /* 59781 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1583*/ GIMT_Encode4(59795), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1268 //
22589 /* 59788 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22590 /* 59788 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
22591 /* 59793 */ GIR_RootConstrainSelectedInstOperands,
22592 /* 59794 */ // GIR_Coverage, 1268,
22593 /* 59794 */ GIR_Done,
22594 /* 59795 */ // Label 1583: @59795
22595 /* 59795 */ GIM_Reject,
22596 /* 59796 */ // Label 1581: @59796
22597 /* 59796 */ GIM_Reject,
22598 /* 59797 */ // Label 1579: @59797
22599 /* 59797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1584*/ GIMT_Encode4(59829), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 409 //
22600 /* 59804 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22601 /* 59807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22602 /* 59810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22603 /* 59814 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22604 /* 59818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22605 /* 59822 */ // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22606 /* 59822 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
22607 /* 59827 */ GIR_RootConstrainSelectedInstOperands,
22608 /* 59828 */ // GIR_Coverage, 409,
22609 /* 59828 */ GIR_Done,
22610 /* 59829 */ // Label 1584: @59829
22611 /* 59829 */ GIM_Reject,
22612 /* 59830 */ // Label 1580: @59830
22613 /* 59830 */ GIM_Reject,
22614 /* 59831 */ // Label 46: @59831
22615 /* 59831 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1587*/ GIMT_Encode4(59936),
22616 /* 59842 */ /*GILLT_s32*//*Label 1585*/ GIMT_Encode4(59850),
22617 /* 59846 */ /*GILLT_s64*//*Label 1586*/ GIMT_Encode4(59903),
22618 /* 59850 */ // Label 1585: @59850
22619 /* 59850 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(59902),
22620 /* 59855 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22621 /* 59858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22622 /* 59861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22623 /* 59865 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22624 /* 59869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22625 /* 59873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1589*/ GIMT_Encode4(59887), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 391 //
22626 /* 59880 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22627 /* 59880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
22628 /* 59885 */ GIR_RootConstrainSelectedInstOperands,
22629 /* 59886 */ // GIR_Coverage, 391,
22630 /* 59886 */ GIR_Done,
22631 /* 59887 */ // Label 1589: @59887
22632 /* 59887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(59901), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1267 //
22633 /* 59894 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22634 /* 59894 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
22635 /* 59899 */ GIR_RootConstrainSelectedInstOperands,
22636 /* 59900 */ // GIR_Coverage, 1267,
22637 /* 59900 */ GIR_Done,
22638 /* 59901 */ // Label 1590: @59901
22639 /* 59901 */ GIM_Reject,
22640 /* 59902 */ // Label 1588: @59902
22641 /* 59902 */ GIM_Reject,
22642 /* 59903 */ // Label 1586: @59903
22643 /* 59903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1591*/ GIMT_Encode4(59935), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 408 //
22644 /* 59910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22645 /* 59913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22646 /* 59916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22647 /* 59920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22648 /* 59924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22649 /* 59928 */ // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22650 /* 59928 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
22651 /* 59933 */ GIR_RootConstrainSelectedInstOperands,
22652 /* 59934 */ // GIR_Coverage, 408,
22653 /* 59934 */ GIR_Done,
22654 /* 59935 */ // Label 1591: @59935
22655 /* 59935 */ GIM_Reject,
22656 /* 59936 */ // Label 1587: @59936
22657 /* 59936 */ GIM_Reject,
22658 /* 59937 */ // Label 47: @59937
22659 /* 59937 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1596*/ GIMT_Encode4(61248),
22660 /* 59948 */ /*GILLT_s32*//*Label 1592*/ GIMT_Encode4(59980),
22661 /* 59952 */ /*GILLT_s64*//*Label 1593*/ GIMT_Encode4(60289), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22662 /* 59972 */ /*GILLT_v4s32*//*Label 1594*/ GIMT_Encode4(60902),
22663 /* 59976 */ /*GILLT_v2s64*//*Label 1595*/ GIMT_Encode4(61075),
22664 /* 59980 */ // Label 1592: @59980
22665 /* 59980 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(60288),
22666 /* 59985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22667 /* 59988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22668 /* 59991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22669 /* 59995 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(60109),
22670 /* 60000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22671 /* 60004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1599*/ GIMT_Encode4(60056), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 208 //
22672 /* 60011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22673 /* 60015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22674 /* 60019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22675 /* 60023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22676 /* 60027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22677 /* 60032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22678 /* 60037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22679 /* 60039 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22680 /* 60039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22681 /* 60042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22682 /* 60044 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22683 /* 60046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22684 /* 60050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22685 /* 60054 */ GIR_RootConstrainSelectedInstOperands,
22686 /* 60055 */ // GIR_Coverage, 208,
22687 /* 60055 */ GIR_EraseRootFromParent_Done,
22688 /* 60056 */ // Label 1599: @60056
22689 /* 60056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1600*/ GIMT_Encode4(60108), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 207 //
22690 /* 60063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22691 /* 60067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22692 /* 60071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22693 /* 60075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22694 /* 60079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22695 /* 60084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22696 /* 60089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22697 /* 60091 */ // (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22698 /* 60091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22699 /* 60094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22700 /* 60096 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22701 /* 60098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22702 /* 60102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22703 /* 60106 */ GIR_RootConstrainSelectedInstOperands,
22704 /* 60107 */ // GIR_Coverage, 207,
22705 /* 60107 */ GIR_EraseRootFromParent_Done,
22706 /* 60108 */ // Label 1600: @60108
22707 /* 60108 */ GIM_Reject,
22708 /* 60109 */ // Label 1598: @60109
22709 /* 60109 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(60287),
22710 /* 60114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22711 /* 60118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1602*/ GIMT_Encode4(60170), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2660 //
22712 /* 60125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22713 /* 60129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22714 /* 60133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22715 /* 60137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22716 /* 60141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22717 /* 60146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22718 /* 60151 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22719 /* 60153 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22720 /* 60153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22721 /* 60156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22722 /* 60158 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22723 /* 60160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22724 /* 60164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22725 /* 60168 */ GIR_RootConstrainSelectedInstOperands,
22726 /* 60169 */ // GIR_Coverage, 2660,
22727 /* 60169 */ GIR_EraseRootFromParent_Done,
22728 /* 60170 */ // Label 1602: @60170
22729 /* 60170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1603*/ GIMT_Encode4(60222), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2659 //
22730 /* 60177 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22731 /* 60181 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22732 /* 60185 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22733 /* 60189 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22734 /* 60193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22735 /* 60198 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22736 /* 60203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22737 /* 60205 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22738 /* 60205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22739 /* 60208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22740 /* 60210 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22741 /* 60212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22742 /* 60216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22743 /* 60220 */ GIR_RootConstrainSelectedInstOperands,
22744 /* 60221 */ // GIR_Coverage, 2659,
22745 /* 60221 */ GIR_EraseRootFromParent_Done,
22746 /* 60222 */ // Label 1603: @60222
22747 /* 60222 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(60286),
22748 /* 60227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22749 /* 60231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1605*/ GIMT_Encode4(60249), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 182 //
22750 /* 60238 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22751 /* 60238 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
22752 /* 60243 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22753 /* 60247 */ GIR_RootConstrainSelectedInstOperands,
22754 /* 60248 */ // GIR_Coverage, 182,
22755 /* 60248 */ GIR_Done,
22756 /* 60249 */ // Label 1605: @60249
22757 /* 60249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1606*/ GIMT_Encode4(60267), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1211 //
22758 /* 60256 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22759 /* 60256 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
22760 /* 60261 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22761 /* 60265 */ GIR_RootConstrainSelectedInstOperands,
22762 /* 60266 */ // GIR_Coverage, 1211,
22763 /* 60266 */ GIR_Done,
22764 /* 60267 */ // Label 1606: @60267
22765 /* 60267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1607*/ GIMT_Encode4(60285), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1275 //
22766 /* 60274 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22767 /* 60274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
22768 /* 60277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22769 /* 60279 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22770 /* 60281 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
22771 /* 60283 */ GIR_RootConstrainSelectedInstOperands,
22772 /* 60284 */ // GIR_Coverage, 1275,
22773 /* 60284 */ GIR_EraseRootFromParent_Done,
22774 /* 60285 */ // Label 1607: @60285
22775 /* 60285 */ GIM_Reject,
22776 /* 60286 */ // Label 1604: @60286
22777 /* 60286 */ GIM_Reject,
22778 /* 60287 */ // Label 1601: @60287
22779 /* 60287 */ GIM_Reject,
22780 /* 60288 */ // Label 1597: @60288
22781 /* 60288 */ GIM_Reject,
22782 /* 60289 */ // Label 1593: @60289
22783 /* 60289 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(60901),
22784 /* 60294 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22785 /* 60297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22786 /* 60300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1609*/ GIMT_Encode4(60360), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 216 //
22787 /* 60307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22788 /* 60311 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22789 /* 60315 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22790 /* 60319 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22791 /* 60323 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22792 /* 60327 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22793 /* 60332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22794 /* 60337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22795 /* 60341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22796 /* 60343 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22797 /* 60343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22798 /* 60346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22799 /* 60348 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22800 /* 60350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22801 /* 60354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22802 /* 60358 */ GIR_RootConstrainSelectedInstOperands,
22803 /* 60359 */ // GIR_Coverage, 216,
22804 /* 60359 */ GIR_EraseRootFromParent_Done,
22805 /* 60360 */ // Label 1609: @60360
22806 /* 60360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1610*/ GIMT_Encode4(60420), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 224 //
22807 /* 60367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22808 /* 60371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22809 /* 60375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22810 /* 60379 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22811 /* 60383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22812 /* 60387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22813 /* 60392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22814 /* 60397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22815 /* 60401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22816 /* 60403 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22817 /* 60403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22818 /* 60406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22819 /* 60408 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22820 /* 60410 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22821 /* 60414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22822 /* 60418 */ GIR_RootConstrainSelectedInstOperands,
22823 /* 60419 */ // GIR_Coverage, 224,
22824 /* 60419 */ GIR_EraseRootFromParent_Done,
22825 /* 60420 */ // Label 1610: @60420
22826 /* 60420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1611*/ GIMT_Encode4(60480), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 215 //
22827 /* 60427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22828 /* 60431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22829 /* 60435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22830 /* 60439 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22831 /* 60443 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22832 /* 60447 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22833 /* 60452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22834 /* 60457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22835 /* 60461 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22836 /* 60463 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22837 /* 60463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22838 /* 60466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22839 /* 60468 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22840 /* 60470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22841 /* 60474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22842 /* 60478 */ GIR_RootConstrainSelectedInstOperands,
22843 /* 60479 */ // GIR_Coverage, 215,
22844 /* 60479 */ GIR_EraseRootFromParent_Done,
22845 /* 60480 */ // Label 1611: @60480
22846 /* 60480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1612*/ GIMT_Encode4(60540), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 223 //
22847 /* 60487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22848 /* 60491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22849 /* 60495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22850 /* 60499 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22851 /* 60503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22852 /* 60507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22853 /* 60512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22854 /* 60517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22855 /* 60521 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22856 /* 60523 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22857 /* 60523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22858 /* 60526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22859 /* 60528 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22860 /* 60530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22861 /* 60534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22862 /* 60538 */ GIR_RootConstrainSelectedInstOperands,
22863 /* 60539 */ // GIR_Coverage, 223,
22864 /* 60539 */ GIR_EraseRootFromParent_Done,
22865 /* 60540 */ // Label 1612: @60540
22866 /* 60540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1613*/ GIMT_Encode4(60600), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2664 //
22867 /* 60547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22868 /* 60551 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22869 /* 60555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22870 /* 60559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22871 /* 60563 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22872 /* 60567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22873 /* 60571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22874 /* 60576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22875 /* 60581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22876 /* 60583 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22877 /* 60583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22878 /* 60586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22879 /* 60588 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22880 /* 60590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22881 /* 60594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22882 /* 60598 */ GIR_RootConstrainSelectedInstOperands,
22883 /* 60599 */ // GIR_Coverage, 2664,
22884 /* 60599 */ GIR_EraseRootFromParent_Done,
22885 /* 60600 */ // Label 1613: @60600
22886 /* 60600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1614*/ GIMT_Encode4(60660), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2668 //
22887 /* 60607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22888 /* 60611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22889 /* 60615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22890 /* 60619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22891 /* 60623 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22892 /* 60627 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22893 /* 60631 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22894 /* 60636 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22895 /* 60641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22896 /* 60643 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22897 /* 60643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22898 /* 60646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22899 /* 60648 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22900 /* 60650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22901 /* 60654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22902 /* 60658 */ GIR_RootConstrainSelectedInstOperands,
22903 /* 60659 */ // GIR_Coverage, 2668,
22904 /* 60659 */ GIR_EraseRootFromParent_Done,
22905 /* 60660 */ // Label 1614: @60660
22906 /* 60660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1615*/ GIMT_Encode4(60720), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2663 //
22907 /* 60667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22908 /* 60671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22909 /* 60675 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22910 /* 60679 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22911 /* 60683 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22912 /* 60687 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22913 /* 60691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22914 /* 60696 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22915 /* 60701 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22916 /* 60703 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22917 /* 60703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22918 /* 60706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22919 /* 60708 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22920 /* 60710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22921 /* 60714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22922 /* 60718 */ GIR_RootConstrainSelectedInstOperands,
22923 /* 60719 */ // GIR_Coverage, 2663,
22924 /* 60719 */ GIR_EraseRootFromParent_Done,
22925 /* 60720 */ // Label 1615: @60720
22926 /* 60720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1616*/ GIMT_Encode4(60780), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2667 //
22927 /* 60727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22928 /* 60731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22929 /* 60735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22930 /* 60739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22931 /* 60743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22932 /* 60747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22933 /* 60751 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22934 /* 60756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22935 /* 60761 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22936 /* 60763 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22937 /* 60763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22938 /* 60766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22939 /* 60768 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22940 /* 60770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22941 /* 60774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22942 /* 60778 */ GIR_RootConstrainSelectedInstOperands,
22943 /* 60779 */ // GIR_Coverage, 2667,
22944 /* 60779 */ GIR_EraseRootFromParent_Done,
22945 /* 60780 */ // Label 1616: @60780
22946 /* 60780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1617*/ GIMT_Encode4(60810), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 184 //
22947 /* 60787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22948 /* 60791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22949 /* 60795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22950 /* 60799 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22951 /* 60799 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
22952 /* 60804 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22953 /* 60808 */ GIR_RootConstrainSelectedInstOperands,
22954 /* 60809 */ // GIR_Coverage, 184,
22955 /* 60809 */ GIR_Done,
22956 /* 60810 */ // Label 1617: @60810
22957 /* 60810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1618*/ GIMT_Encode4(60840), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 186 //
22958 /* 60817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22959 /* 60821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22960 /* 60825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22961 /* 60829 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22962 /* 60829 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
22963 /* 60834 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22964 /* 60838 */ GIR_RootConstrainSelectedInstOperands,
22965 /* 60839 */ // GIR_Coverage, 186,
22966 /* 60839 */ GIR_Done,
22967 /* 60840 */ // Label 1618: @60840
22968 /* 60840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1619*/ GIMT_Encode4(60870), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1215 //
22969 /* 60847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22970 /* 60851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22971 /* 60855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22972 /* 60859 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22973 /* 60859 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
22974 /* 60864 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22975 /* 60868 */ GIR_RootConstrainSelectedInstOperands,
22976 /* 60869 */ // GIR_Coverage, 1215,
22977 /* 60869 */ GIR_Done,
22978 /* 60870 */ // Label 1619: @60870
22979 /* 60870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1620*/ GIMT_Encode4(60900), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1216 //
22980 /* 60877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22981 /* 60881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22982 /* 60885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22983 /* 60889 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22984 /* 60889 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
22985 /* 60894 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22986 /* 60898 */ GIR_RootConstrainSelectedInstOperands,
22987 /* 60899 */ // GIR_Coverage, 1216,
22988 /* 60899 */ GIR_Done,
22989 /* 60900 */ // Label 1620: @60900
22990 /* 60900 */ GIM_Reject,
22991 /* 60901 */ // Label 1608: @60901
22992 /* 60901 */ GIM_Reject,
22993 /* 60902 */ // Label 1594: @60902
22994 /* 60902 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(61074),
22995 /* 60907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22996 /* 60910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22997 /* 60913 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(61047),
22998 /* 60918 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
22999 /* 60922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23000 /* 60926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1623*/ GIMT_Encode4(60986), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2802 //
23001 /* 60933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23002 /* 60937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23003 /* 60941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23004 /* 60945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
23005 /* 60949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23006 /* 60954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23007 /* 60959 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23008 /* 60963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23009 /* 60967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23010 /* 60969 */ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>, MSA128WOpnd:{ *:[v4f32] }:$wd)<<P:Predicate_fadd_contract>> => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23011 /* 60969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
23012 /* 60972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23013 /* 60974 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
23014 /* 60976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23015 /* 60980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23016 /* 60984 */ GIR_RootConstrainSelectedInstOperands,
23017 /* 60985 */ // GIR_Coverage, 2802,
23018 /* 60985 */ GIR_EraseRootFromParent_Done,
23019 /* 60986 */ // Label 1623: @60986
23020 /* 60986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1624*/ GIMT_Encode4(61046), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2243 //
23021 /* 60993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23022 /* 60997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23023 /* 61001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23024 /* 61005 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23025 /* 61009 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
23026 /* 61013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23027 /* 61018 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23028 /* 61023 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23029 /* 61027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23030 /* 61029 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23031 /* 61029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
23032 /* 61032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23033 /* 61034 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23034 /* 61036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23035 /* 61040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23036 /* 61044 */ GIR_RootConstrainSelectedInstOperands,
23037 /* 61045 */ // GIR_Coverage, 2243,
23038 /* 61045 */ GIR_EraseRootFromParent_Done,
23039 /* 61046 */ // Label 1624: @61046
23040 /* 61046 */ GIM_Reject,
23041 /* 61047 */ // Label 1622: @61047
23042 /* 61047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1625*/ GIMT_Encode4(61073), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 733 //
23043 /* 61054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23044 /* 61058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23045 /* 61062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23046 /* 61066 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23047 /* 61066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
23048 /* 61071 */ GIR_RootConstrainSelectedInstOperands,
23049 /* 61072 */ // GIR_Coverage, 733,
23050 /* 61072 */ GIR_Done,
23051 /* 61073 */ // Label 1625: @61073
23052 /* 61073 */ GIM_Reject,
23053 /* 61074 */ // Label 1621: @61074
23054 /* 61074 */ GIM_Reject,
23055 /* 61075 */ // Label 1595: @61075
23056 /* 61075 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(61247),
23057 /* 61080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23058 /* 61083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23059 /* 61086 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(61220),
23060 /* 61091 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
23061 /* 61095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23062 /* 61099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1628*/ GIMT_Encode4(61159), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2803 //
23063 /* 61106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23064 /* 61110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23065 /* 61114 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23066 /* 61118 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
23067 /* 61122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23068 /* 61127 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23069 /* 61132 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23070 /* 61136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23071 /* 61140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23072 /* 61142 */ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>, MSA128DOpnd:{ *:[v2f64] }:$wd)<<P:Predicate_fadd_contract>> => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23073 /* 61142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
23074 /* 61145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23075 /* 61147 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
23076 /* 61149 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23077 /* 61153 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23078 /* 61157 */ GIR_RootConstrainSelectedInstOperands,
23079 /* 61158 */ // GIR_Coverage, 2803,
23080 /* 61158 */ GIR_EraseRootFromParent_Done,
23081 /* 61159 */ // Label 1628: @61159
23082 /* 61159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1629*/ GIMT_Encode4(61219), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2244 //
23083 /* 61166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23084 /* 61170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23085 /* 61174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23086 /* 61178 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23087 /* 61182 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
23088 /* 61186 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23089 /* 61191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23090 /* 61196 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23091 /* 61200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23092 /* 61202 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23093 /* 61202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
23094 /* 61205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23095 /* 61207 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23096 /* 61209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23097 /* 61213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23098 /* 61217 */ GIR_RootConstrainSelectedInstOperands,
23099 /* 61218 */ // GIR_Coverage, 2244,
23100 /* 61218 */ GIR_EraseRootFromParent_Done,
23101 /* 61219 */ // Label 1629: @61219
23102 /* 61219 */ GIM_Reject,
23103 /* 61220 */ // Label 1627: @61220
23104 /* 61220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1630*/ GIMT_Encode4(61246), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 734 //
23105 /* 61227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23106 /* 61231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23107 /* 61235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23108 /* 61239 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23109 /* 61239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
23110 /* 61244 */ GIR_RootConstrainSelectedInstOperands,
23111 /* 61245 */ // GIR_Coverage, 734,
23112 /* 61245 */ GIR_Done,
23113 /* 61246 */ // Label 1630: @61246
23114 /* 61246 */ GIM_Reject,
23115 /* 61247 */ // Label 1626: @61247
23116 /* 61247 */ GIM_Reject,
23117 /* 61248 */ // Label 1596: @61248
23118 /* 61248 */ GIM_Reject,
23119 /* 61249 */ // Label 48: @61249
23120 /* 61249 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1635*/ GIMT_Encode4(62078),
23121 /* 61260 */ /*GILLT_s32*//*Label 1631*/ GIMT_Encode4(61292),
23122 /* 61264 */ /*GILLT_s64*//*Label 1632*/ GIMT_Encode4(61491), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23123 /* 61284 */ /*GILLT_v4s32*//*Label 1633*/ GIMT_Encode4(61864),
23124 /* 61288 */ /*GILLT_v2s64*//*Label 1634*/ GIMT_Encode4(61971),
23125 /* 61292 */ // Label 1631: @61292
23126 /* 61292 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(61490),
23127 /* 61297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23128 /* 61300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23129 /* 61303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23130 /* 61307 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(61421),
23131 /* 61312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23132 /* 61316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1638*/ GIMT_Encode4(61368), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 212 //
23133 /* 61323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23134 /* 61327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23135 /* 61331 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23136 /* 61335 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23137 /* 61339 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23138 /* 61344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23139 /* 61349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23140 /* 61351 */ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23141 /* 61351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
23142 /* 61354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23143 /* 61356 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23144 /* 61358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23145 /* 61362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23146 /* 61366 */ GIR_RootConstrainSelectedInstOperands,
23147 /* 61367 */ // GIR_Coverage, 212,
23148 /* 61367 */ GIR_EraseRootFromParent_Done,
23149 /* 61368 */ // Label 1638: @61368
23150 /* 61368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1639*/ GIMT_Encode4(61420), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 211 //
23151 /* 61375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23152 /* 61379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
23153 /* 61383 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23154 /* 61387 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23155 /* 61391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23156 /* 61396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23157 /* 61401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23158 /* 61403 */ // (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23159 /* 61403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
23160 /* 61406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23161 /* 61408 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23162 /* 61410 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23163 /* 61414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23164 /* 61418 */ GIR_RootConstrainSelectedInstOperands,
23165 /* 61419 */ // GIR_Coverage, 211,
23166 /* 61419 */ GIR_EraseRootFromParent_Done,
23167 /* 61420 */ // Label 1639: @61420
23168 /* 61420 */ GIM_Reject,
23169 /* 61421 */ // Label 1637: @61421
23170 /* 61421 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(61489),
23171 /* 61426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23172 /* 61430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23173 /* 61434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1641*/ GIMT_Encode4(61452), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 200 //
23174 /* 61441 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23175 /* 61441 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
23176 /* 61446 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23177 /* 61450 */ GIR_RootConstrainSelectedInstOperands,
23178 /* 61451 */ // GIR_Coverage, 200,
23179 /* 61451 */ GIR_Done,
23180 /* 61452 */ // Label 1641: @61452
23181 /* 61452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1642*/ GIMT_Encode4(61470), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1214 //
23182 /* 61459 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23183 /* 61459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
23184 /* 61464 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23185 /* 61468 */ GIR_RootConstrainSelectedInstOperands,
23186 /* 61469 */ // GIR_Coverage, 1214,
23187 /* 61469 */ GIR_Done,
23188 /* 61470 */ // Label 1642: @61470
23189 /* 61470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1643*/ GIMT_Encode4(61488), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1276 //
23190 /* 61477 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23191 /* 61477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
23192 /* 61480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23193 /* 61482 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23194 /* 61484 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23195 /* 61486 */ GIR_RootConstrainSelectedInstOperands,
23196 /* 61487 */ // GIR_Coverage, 1276,
23197 /* 61487 */ GIR_EraseRootFromParent_Done,
23198 /* 61488 */ // Label 1643: @61488
23199 /* 61488 */ GIM_Reject,
23200 /* 61489 */ // Label 1640: @61489
23201 /* 61489 */ GIM_Reject,
23202 /* 61490 */ // Label 1636: @61490
23203 /* 61490 */ GIM_Reject,
23204 /* 61491 */ // Label 1632: @61491
23205 /* 61491 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(61863),
23206 /* 61496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23207 /* 61499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23208 /* 61502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1645*/ GIMT_Encode4(61562), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 220 //
23209 /* 61509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23210 /* 61513 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23211 /* 61517 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23212 /* 61521 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23213 /* 61525 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23214 /* 61529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23215 /* 61534 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23216 /* 61539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23217 /* 61543 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23218 /* 61545 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23219 /* 61545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
23220 /* 61548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23221 /* 61550 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23222 /* 61552 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23223 /* 61556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23224 /* 61560 */ GIR_RootConstrainSelectedInstOperands,
23225 /* 61561 */ // GIR_Coverage, 220,
23226 /* 61561 */ GIR_EraseRootFromParent_Done,
23227 /* 61562 */ // Label 1645: @61562
23228 /* 61562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1646*/ GIMT_Encode4(61622), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 228 //
23229 /* 61569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23230 /* 61573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23231 /* 61577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23232 /* 61581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23233 /* 61585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23234 /* 61589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23235 /* 61594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23236 /* 61599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23237 /* 61603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23238 /* 61605 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23239 /* 61605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
23240 /* 61608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23241 /* 61610 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23242 /* 61612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23243 /* 61616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23244 /* 61620 */ GIR_RootConstrainSelectedInstOperands,
23245 /* 61621 */ // GIR_Coverage, 228,
23246 /* 61621 */ GIR_EraseRootFromParent_Done,
23247 /* 61622 */ // Label 1646: @61622
23248 /* 61622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1647*/ GIMT_Encode4(61682), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 219 //
23249 /* 61629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23250 /* 61633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23251 /* 61637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
23252 /* 61641 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23253 /* 61645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23254 /* 61649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23255 /* 61654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23256 /* 61659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23257 /* 61663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23258 /* 61665 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23259 /* 61665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
23260 /* 61668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23261 /* 61670 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23262 /* 61672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23263 /* 61676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23264 /* 61680 */ GIR_RootConstrainSelectedInstOperands,
23265 /* 61681 */ // GIR_Coverage, 219,
23266 /* 61681 */ GIR_EraseRootFromParent_Done,
23267 /* 61682 */ // Label 1647: @61682
23268 /* 61682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1648*/ GIMT_Encode4(61742), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 227 //
23269 /* 61689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23270 /* 61693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23271 /* 61697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
23272 /* 61701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23273 /* 61705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23274 /* 61709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23275 /* 61714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23276 /* 61719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23277 /* 61723 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23278 /* 61725 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23279 /* 61725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
23280 /* 61728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23281 /* 61730 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23282 /* 61732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23283 /* 61736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23284 /* 61740 */ GIR_RootConstrainSelectedInstOperands,
23285 /* 61741 */ // GIR_Coverage, 227,
23286 /* 61741 */ GIR_EraseRootFromParent_Done,
23287 /* 61742 */ // Label 1648: @61742
23288 /* 61742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1649*/ GIMT_Encode4(61772), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 202 //
23289 /* 61749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23290 /* 61753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23291 /* 61757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23292 /* 61761 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23293 /* 61761 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
23294 /* 61766 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23295 /* 61770 */ GIR_RootConstrainSelectedInstOperands,
23296 /* 61771 */ // GIR_Coverage, 202,
23297 /* 61771 */ GIR_Done,
23298 /* 61772 */ // Label 1649: @61772
23299 /* 61772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1650*/ GIMT_Encode4(61802), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 204 //
23300 /* 61779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23301 /* 61783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23302 /* 61787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23303 /* 61791 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23304 /* 61791 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
23305 /* 61796 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23306 /* 61800 */ GIR_RootConstrainSelectedInstOperands,
23307 /* 61801 */ // GIR_Coverage, 204,
23308 /* 61801 */ GIR_Done,
23309 /* 61802 */ // Label 1650: @61802
23310 /* 61802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(61832), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1221 //
23311 /* 61809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23312 /* 61813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23313 /* 61817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23314 /* 61821 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23315 /* 61821 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
23316 /* 61826 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23317 /* 61830 */ GIR_RootConstrainSelectedInstOperands,
23318 /* 61831 */ // GIR_Coverage, 1221,
23319 /* 61831 */ GIR_Done,
23320 /* 61832 */ // Label 1651: @61832
23321 /* 61832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1652*/ GIMT_Encode4(61862), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1222 //
23322 /* 61839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23323 /* 61843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23324 /* 61847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23325 /* 61851 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23326 /* 61851 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
23327 /* 61856 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23328 /* 61860 */ GIR_RootConstrainSelectedInstOperands,
23329 /* 61861 */ // GIR_Coverage, 1222,
23330 /* 61861 */ GIR_Done,
23331 /* 61862 */ // Label 1652: @61862
23332 /* 61862 */ GIM_Reject,
23333 /* 61863 */ // Label 1644: @61863
23334 /* 61863 */ GIM_Reject,
23335 /* 61864 */ // Label 1633: @61864
23336 /* 61864 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(61970),
23337 /* 61869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23338 /* 61872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23339 /* 61875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1654*/ GIMT_Encode4(61943), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2241 //
23340 /* 61882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23341 /* 61886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23342 /* 61890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23343 /* 61894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23344 /* 61898 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23345 /* 61902 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
23346 /* 61906 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23347 /* 61911 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23348 /* 61916 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23349 /* 61920 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
23350 /* 61924 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23351 /* 61926 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23352 /* 61926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
23353 /* 61929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23354 /* 61931 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23355 /* 61933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23356 /* 61937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23357 /* 61941 */ GIR_RootConstrainSelectedInstOperands,
23358 /* 61942 */ // GIR_Coverage, 2241,
23359 /* 61942 */ GIR_EraseRootFromParent_Done,
23360 /* 61943 */ // Label 1654: @61943
23361 /* 61943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1655*/ GIMT_Encode4(61969), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 821 //
23362 /* 61950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23363 /* 61954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23364 /* 61958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23365 /* 61962 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23366 /* 61962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
23367 /* 61967 */ GIR_RootConstrainSelectedInstOperands,
23368 /* 61968 */ // GIR_Coverage, 821,
23369 /* 61968 */ GIR_Done,
23370 /* 61969 */ // Label 1655: @61969
23371 /* 61969 */ GIM_Reject,
23372 /* 61970 */ // Label 1653: @61970
23373 /* 61970 */ GIM_Reject,
23374 /* 61971 */ // Label 1634: @61971
23375 /* 61971 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(62077),
23376 /* 61976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23377 /* 61979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23378 /* 61982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1657*/ GIMT_Encode4(62050), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2242 //
23379 /* 61989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23380 /* 61993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23381 /* 61997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23382 /* 62001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23383 /* 62005 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23384 /* 62009 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
23385 /* 62013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23386 /* 62018 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23387 /* 62023 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23388 /* 62027 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
23389 /* 62031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23390 /* 62033 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23391 /* 62033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
23392 /* 62036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23393 /* 62038 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23394 /* 62040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23395 /* 62044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23396 /* 62048 */ GIR_RootConstrainSelectedInstOperands,
23397 /* 62049 */ // GIR_Coverage, 2242,
23398 /* 62049 */ GIR_EraseRootFromParent_Done,
23399 /* 62050 */ // Label 1657: @62050
23400 /* 62050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1658*/ GIMT_Encode4(62076), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 822 //
23401 /* 62057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23402 /* 62061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23403 /* 62065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23404 /* 62069 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23405 /* 62069 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
23406 /* 62074 */ GIR_RootConstrainSelectedInstOperands,
23407 /* 62075 */ // GIR_Coverage, 822,
23408 /* 62075 */ GIR_Done,
23409 /* 62076 */ // Label 1658: @62076
23410 /* 62076 */ GIM_Reject,
23411 /* 62077 */ // Label 1656: @62077
23412 /* 62077 */ GIM_Reject,
23413 /* 62078 */ // Label 1635: @62078
23414 /* 62078 */ GIM_Reject,
23415 /* 62079 */ // Label 49: @62079
23416 /* 62079 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1663*/ GIMT_Encode4(62588),
23417 /* 62090 */ /*GILLT_s32*//*Label 1659*/ GIMT_Encode4(62122),
23418 /* 62094 */ /*GILLT_s64*//*Label 1660*/ GIMT_Encode4(62201), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23419 /* 62114 */ /*GILLT_v4s32*//*Label 1661*/ GIMT_Encode4(62334),
23420 /* 62118 */ /*GILLT_v2s64*//*Label 1662*/ GIMT_Encode4(62461),
23421 /* 62122 */ // Label 1659: @62122
23422 /* 62122 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(62200),
23423 /* 62127 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23424 /* 62130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23425 /* 62133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23426 /* 62137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23427 /* 62141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23428 /* 62145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1665*/ GIMT_Encode4(62163), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 194 //
23429 /* 62152 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23430 /* 62152 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
23431 /* 62157 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23432 /* 62161 */ GIR_RootConstrainSelectedInstOperands,
23433 /* 62162 */ // GIR_Coverage, 194,
23434 /* 62162 */ GIR_Done,
23435 /* 62163 */ // Label 1665: @62163
23436 /* 62163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1666*/ GIMT_Encode4(62181), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1213 //
23437 /* 62170 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23438 /* 62170 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
23439 /* 62175 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23440 /* 62179 */ GIR_RootConstrainSelectedInstOperands,
23441 /* 62180 */ // GIR_Coverage, 1213,
23442 /* 62180 */ GIR_Done,
23443 /* 62181 */ // Label 1666: @62181
23444 /* 62181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1667*/ GIMT_Encode4(62199), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1277 //
23445 /* 62188 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23446 /* 62188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
23447 /* 62191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23448 /* 62193 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23449 /* 62195 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23450 /* 62197 */ GIR_RootConstrainSelectedInstOperands,
23451 /* 62198 */ // GIR_Coverage, 1277,
23452 /* 62198 */ GIR_EraseRootFromParent_Done,
23453 /* 62199 */ // Label 1667: @62199
23454 /* 62199 */ GIM_Reject,
23455 /* 62200 */ // Label 1664: @62200
23456 /* 62200 */ GIM_Reject,
23457 /* 62201 */ // Label 1660: @62201
23458 /* 62201 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(62333),
23459 /* 62206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23460 /* 62209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23461 /* 62212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1669*/ GIMT_Encode4(62242), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 196 //
23462 /* 62219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23463 /* 62223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23464 /* 62227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23465 /* 62231 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23466 /* 62231 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
23467 /* 62236 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23468 /* 62240 */ GIR_RootConstrainSelectedInstOperands,
23469 /* 62241 */ // GIR_Coverage, 196,
23470 /* 62241 */ GIR_Done,
23471 /* 62242 */ // Label 1669: @62242
23472 /* 62242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1670*/ GIMT_Encode4(62272), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 198 //
23473 /* 62249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23474 /* 62253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23475 /* 62257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23476 /* 62261 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23477 /* 62261 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
23478 /* 62266 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23479 /* 62270 */ GIR_RootConstrainSelectedInstOperands,
23480 /* 62271 */ // GIR_Coverage, 198,
23481 /* 62271 */ GIR_Done,
23482 /* 62272 */ // Label 1670: @62272
23483 /* 62272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1671*/ GIMT_Encode4(62302), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1219 //
23484 /* 62279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23485 /* 62283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23486 /* 62287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23487 /* 62291 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23488 /* 62291 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
23489 /* 62296 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23490 /* 62300 */ GIR_RootConstrainSelectedInstOperands,
23491 /* 62301 */ // GIR_Coverage, 1219,
23492 /* 62301 */ GIR_Done,
23493 /* 62302 */ // Label 1671: @62302
23494 /* 62302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1672*/ GIMT_Encode4(62332), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1220 //
23495 /* 62309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23496 /* 62313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23497 /* 62317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23498 /* 62321 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23499 /* 62321 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
23500 /* 62326 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23501 /* 62330 */ GIR_RootConstrainSelectedInstOperands,
23502 /* 62331 */ // GIR_Coverage, 1220,
23503 /* 62331 */ GIR_Done,
23504 /* 62332 */ // Label 1672: @62332
23505 /* 62332 */ GIM_Reject,
23506 /* 62333 */ // Label 1668: @62333
23507 /* 62333 */ GIM_Reject,
23508 /* 62334 */ // Label 1661: @62334
23509 /* 62334 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(62460),
23510 /* 62339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23511 /* 62342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23512 /* 62345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23513 /* 62349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1674*/ GIMT_Encode4(62392), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2705 //
23514 /* 62356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23515 /* 62360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23516 /* 62364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23517 /* 62368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23518 /* 62373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23519 /* 62377 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23520 /* 62379 */ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23521 /* 62379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23522 /* 62382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23523 /* 62384 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
23524 /* 62386 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23525 /* 62390 */ GIR_RootConstrainSelectedInstOperands,
23526 /* 62391 */ // GIR_Coverage, 2705,
23527 /* 62391 */ GIR_EraseRootFromParent_Done,
23528 /* 62392 */ // Label 1674: @62392
23529 /* 62392 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(62459),
23530 /* 62397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23531 /* 62401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1676*/ GIMT_Encode4(62440), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 763 //
23532 /* 62408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23533 /* 62412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23534 /* 62416 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23535 /* 62420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23536 /* 62425 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23537 /* 62427 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23538 /* 62427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23539 /* 62430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23540 /* 62432 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
23541 /* 62434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23542 /* 62438 */ GIR_RootConstrainSelectedInstOperands,
23543 /* 62439 */ // GIR_Coverage, 763,
23544 /* 62439 */ GIR_EraseRootFromParent_Done,
23545 /* 62440 */ // Label 1676: @62440
23546 /* 62440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1677*/ GIMT_Encode4(62458), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 799 //
23547 /* 62447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23548 /* 62451 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23549 /* 62451 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
23550 /* 62456 */ GIR_RootConstrainSelectedInstOperands,
23551 /* 62457 */ // GIR_Coverage, 799,
23552 /* 62457 */ GIR_Done,
23553 /* 62458 */ // Label 1677: @62458
23554 /* 62458 */ GIM_Reject,
23555 /* 62459 */ // Label 1675: @62459
23556 /* 62459 */ GIM_Reject,
23557 /* 62460 */ // Label 1673: @62460
23558 /* 62460 */ GIM_Reject,
23559 /* 62461 */ // Label 1662: @62461
23560 /* 62461 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(62587),
23561 /* 62466 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23562 /* 62469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23563 /* 62472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23564 /* 62476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1679*/ GIMT_Encode4(62519), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2706 //
23565 /* 62483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23566 /* 62487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23567 /* 62491 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23568 /* 62495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23569 /* 62500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23570 /* 62504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23571 /* 62506 */ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23572 /* 62506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23573 /* 62509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23574 /* 62511 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
23575 /* 62513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23576 /* 62517 */ GIR_RootConstrainSelectedInstOperands,
23577 /* 62518 */ // GIR_Coverage, 2706,
23578 /* 62518 */ GIR_EraseRootFromParent_Done,
23579 /* 62519 */ // Label 1679: @62519
23580 /* 62519 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(62586),
23581 /* 62524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23582 /* 62528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1681*/ GIMT_Encode4(62567), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 764 //
23583 /* 62535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23584 /* 62539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23585 /* 62543 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23586 /* 62547 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23587 /* 62552 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23588 /* 62554 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23589 /* 62554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23590 /* 62557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23591 /* 62559 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
23592 /* 62561 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23593 /* 62565 */ GIR_RootConstrainSelectedInstOperands,
23594 /* 62566 */ // GIR_Coverage, 764,
23595 /* 62566 */ GIR_EraseRootFromParent_Done,
23596 /* 62567 */ // Label 1681: @62567
23597 /* 62567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1682*/ GIMT_Encode4(62585), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 800 //
23598 /* 62574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23599 /* 62578 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23600 /* 62578 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
23601 /* 62583 */ GIR_RootConstrainSelectedInstOperands,
23602 /* 62584 */ // GIR_Coverage, 800,
23603 /* 62584 */ GIR_Done,
23604 /* 62585 */ // Label 1682: @62585
23605 /* 62585 */ GIM_Reject,
23606 /* 62586 */ // Label 1680: @62586
23607 /* 62586 */ GIM_Reject,
23608 /* 62587 */ // Label 1678: @62587
23609 /* 62587 */ GIM_Reject,
23610 /* 62588 */ // Label 1663: @62588
23611 /* 62588 */ GIM_Reject,
23612 /* 62589 */ // Label 50: @62589
23613 /* 62589 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(62688),
23614 /* 62600 */ /*GILLT_v4s32*//*Label 1683*/ GIMT_Encode4(62608),
23615 /* 62604 */ /*GILLT_v2s64*//*Label 1684*/ GIMT_Encode4(62648),
23616 /* 62608 */ // Label 1683: @62608
23617 /* 62608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1686*/ GIMT_Encode4(62647), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 787 //
23618 /* 62615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23619 /* 62618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23620 /* 62621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23621 /* 62624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23622 /* 62628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23623 /* 62632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23624 /* 62636 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23625 /* 62640 */ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23626 /* 62640 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
23627 /* 62645 */ GIR_RootConstrainSelectedInstOperands,
23628 /* 62646 */ // GIR_Coverage, 787,
23629 /* 62646 */ GIR_Done,
23630 /* 62647 */ // Label 1686: @62647
23631 /* 62647 */ GIM_Reject,
23632 /* 62648 */ // Label 1684: @62648
23633 /* 62648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1687*/ GIMT_Encode4(62687), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 788 //
23634 /* 62655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23635 /* 62658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23636 /* 62661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23637 /* 62664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23638 /* 62668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23639 /* 62672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23640 /* 62676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23641 /* 62680 */ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23642 /* 62680 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
23643 /* 62685 */ GIR_RootConstrainSelectedInstOperands,
23644 /* 62686 */ // GIR_Coverage, 788,
23645 /* 62686 */ GIR_Done,
23646 /* 62687 */ // Label 1687: @62687
23647 /* 62687 */ GIM_Reject,
23648 /* 62688 */ // Label 1685: @62688
23649 /* 62688 */ GIM_Reject,
23650 /* 62689 */ // Label 51: @62689
23651 /* 62689 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1692*/ GIMT_Encode4(63010),
23652 /* 62700 */ /*GILLT_s32*//*Label 1688*/ GIMT_Encode4(62732),
23653 /* 62704 */ /*GILLT_s64*//*Label 1689*/ GIMT_Encode4(62811), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23654 /* 62724 */ /*GILLT_v4s32*//*Label 1690*/ GIMT_Encode4(62944),
23655 /* 62728 */ /*GILLT_v2s64*//*Label 1691*/ GIMT_Encode4(62977),
23656 /* 62732 */ // Label 1688: @62732
23657 /* 62732 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(62810),
23658 /* 62737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23659 /* 62740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23660 /* 62743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23661 /* 62747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23662 /* 62751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23663 /* 62755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1694*/ GIMT_Encode4(62773), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 188 //
23664 /* 62762 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23665 /* 62762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
23666 /* 62767 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23667 /* 62771 */ GIR_RootConstrainSelectedInstOperands,
23668 /* 62772 */ // GIR_Coverage, 188,
23669 /* 62772 */ GIR_Done,
23670 /* 62773 */ // Label 1694: @62773
23671 /* 62773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1695*/ GIMT_Encode4(62791), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1212 //
23672 /* 62780 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23673 /* 62780 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
23674 /* 62785 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23675 /* 62789 */ GIR_RootConstrainSelectedInstOperands,
23676 /* 62790 */ // GIR_Coverage, 1212,
23677 /* 62790 */ GIR_Done,
23678 /* 62791 */ // Label 1695: @62791
23679 /* 62791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1696*/ GIMT_Encode4(62809), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1278 //
23680 /* 62798 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23681 /* 62798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
23682 /* 62801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23683 /* 62803 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23684 /* 62805 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23685 /* 62807 */ GIR_RootConstrainSelectedInstOperands,
23686 /* 62808 */ // GIR_Coverage, 1278,
23687 /* 62808 */ GIR_EraseRootFromParent_Done,
23688 /* 62809 */ // Label 1696: @62809
23689 /* 62809 */ GIM_Reject,
23690 /* 62810 */ // Label 1693: @62810
23691 /* 62810 */ GIM_Reject,
23692 /* 62811 */ // Label 1689: @62811
23693 /* 62811 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(62943),
23694 /* 62816 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23695 /* 62819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23696 /* 62822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1698*/ GIMT_Encode4(62852), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 190 //
23697 /* 62829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23698 /* 62833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23699 /* 62837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23700 /* 62841 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23701 /* 62841 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
23702 /* 62846 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23703 /* 62850 */ GIR_RootConstrainSelectedInstOperands,
23704 /* 62851 */ // GIR_Coverage, 190,
23705 /* 62851 */ GIR_Done,
23706 /* 62852 */ // Label 1698: @62852
23707 /* 62852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1699*/ GIMT_Encode4(62882), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 192 //
23708 /* 62859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23709 /* 62863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23710 /* 62867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23711 /* 62871 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23712 /* 62871 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
23713 /* 62876 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23714 /* 62880 */ GIR_RootConstrainSelectedInstOperands,
23715 /* 62881 */ // GIR_Coverage, 192,
23716 /* 62881 */ GIR_Done,
23717 /* 62882 */ // Label 1699: @62882
23718 /* 62882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(62912), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1217 //
23719 /* 62889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23720 /* 62893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23721 /* 62897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23722 /* 62901 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23723 /* 62901 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
23724 /* 62906 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23725 /* 62910 */ GIR_RootConstrainSelectedInstOperands,
23726 /* 62911 */ // GIR_Coverage, 1217,
23727 /* 62911 */ GIR_Done,
23728 /* 62912 */ // Label 1700: @62912
23729 /* 62912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1701*/ GIMT_Encode4(62942), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1218 //
23730 /* 62919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23731 /* 62923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23732 /* 62927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23733 /* 62931 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23734 /* 62931 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
23735 /* 62936 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23736 /* 62940 */ GIR_RootConstrainSelectedInstOperands,
23737 /* 62941 */ // GIR_Coverage, 1218,
23738 /* 62941 */ GIR_Done,
23739 /* 62942 */ // Label 1701: @62942
23740 /* 62942 */ GIM_Reject,
23741 /* 62943 */ // Label 1697: @62943
23742 /* 62943 */ GIM_Reject,
23743 /* 62944 */ // Label 1690: @62944
23744 /* 62944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1702*/ GIMT_Encode4(62976), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 759 //
23745 /* 62951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23746 /* 62954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23747 /* 62957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23748 /* 62961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23749 /* 62965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23750 /* 62969 */ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23751 /* 62969 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
23752 /* 62974 */ GIR_RootConstrainSelectedInstOperands,
23753 /* 62975 */ // GIR_Coverage, 759,
23754 /* 62975 */ GIR_Done,
23755 /* 62976 */ // Label 1702: @62976
23756 /* 62976 */ GIM_Reject,
23757 /* 62977 */ // Label 1691: @62977
23758 /* 62977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1703*/ GIMT_Encode4(63009), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 760 //
23759 /* 62984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23760 /* 62987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23761 /* 62990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23762 /* 62994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23763 /* 62998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23764 /* 63002 */ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23765 /* 63002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
23766 /* 63007 */ GIR_RootConstrainSelectedInstOperands,
23767 /* 63008 */ // GIR_Coverage, 760,
23768 /* 63008 */ GIR_Done,
23769 /* 63009 */ // Label 1703: @63009
23770 /* 63009 */ GIM_Reject,
23771 /* 63010 */ // Label 1692: @63010
23772 /* 63010 */ GIM_Reject,
23773 /* 63011 */ // Label 52: @63011
23774 /* 63011 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1706*/ GIMT_Encode4(63082),
23775 /* 63022 */ /*GILLT_v4s32*//*Label 1704*/ GIMT_Encode4(63030),
23776 /* 63026 */ /*GILLT_v2s64*//*Label 1705*/ GIMT_Encode4(63056),
23777 /* 63030 */ // Label 1704: @63030
23778 /* 63030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1707*/ GIMT_Encode4(63055), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 765 //
23779 /* 63037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23780 /* 63040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23781 /* 63044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23782 /* 63048 */ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
23783 /* 63048 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
23784 /* 63053 */ GIR_RootConstrainSelectedInstOperands,
23785 /* 63054 */ // GIR_Coverage, 765,
23786 /* 63054 */ GIR_Done,
23787 /* 63055 */ // Label 1707: @63055
23788 /* 63055 */ GIM_Reject,
23789 /* 63056 */ // Label 1705: @63056
23790 /* 63056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1708*/ GIMT_Encode4(63081), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 766 //
23791 /* 63063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23792 /* 63066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23793 /* 63070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23794 /* 63074 */ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
23795 /* 63074 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
23796 /* 63079 */ GIR_RootConstrainSelectedInstOperands,
23797 /* 63080 */ // GIR_Coverage, 766,
23798 /* 63080 */ GIR_Done,
23799 /* 63081 */ // Label 1708: @63081
23800 /* 63081 */ GIM_Reject,
23801 /* 63082 */ // Label 1706: @63082
23802 /* 63082 */ GIM_Reject,
23803 /* 63083 */ // Label 53: @63083
23804 /* 63083 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1711*/ GIMT_Encode4(63154),
23805 /* 63094 */ /*GILLT_v4s32*//*Label 1709*/ GIMT_Encode4(63102),
23806 /* 63098 */ /*GILLT_v2s64*//*Label 1710*/ GIMT_Encode4(63128),
23807 /* 63102 */ // Label 1709: @63102
23808 /* 63102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1712*/ GIMT_Encode4(63127), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 785 //
23809 /* 63109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23810 /* 63112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23811 /* 63116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23812 /* 63120 */ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23813 /* 63120 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
23814 /* 63125 */ GIR_RootConstrainSelectedInstOperands,
23815 /* 63126 */ // GIR_Coverage, 785,
23816 /* 63126 */ GIR_Done,
23817 /* 63127 */ // Label 1712: @63127
23818 /* 63127 */ GIM_Reject,
23819 /* 63128 */ // Label 1710: @63128
23820 /* 63128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1713*/ GIMT_Encode4(63153), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 786 //
23821 /* 63135 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23822 /* 63138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23823 /* 63142 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23824 /* 63146 */ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23825 /* 63146 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
23826 /* 63151 */ GIR_RootConstrainSelectedInstOperands,
23827 /* 63152 */ // GIR_Coverage, 786,
23828 /* 63152 */ GIR_Done,
23829 /* 63153 */ // Label 1713: @63153
23830 /* 63153 */ GIM_Reject,
23831 /* 63154 */ // Label 1711: @63154
23832 /* 63154 */ GIM_Reject,
23833 /* 63155 */ // Label 54: @63155
23834 /* 63155 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1716*/ GIMT_Encode4(63332),
23835 /* 63166 */ /*GILLT_s32*//*Label 1714*/ GIMT_Encode4(63174),
23836 /* 63170 */ /*GILLT_s64*//*Label 1715*/ GIMT_Encode4(63234),
23837 /* 63174 */ // Label 1714: @63174
23838 /* 63174 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(63233),
23839 /* 63179 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23840 /* 63182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23841 /* 63186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23842 /* 63190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1718*/ GIMT_Encode4(63204), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat), // Rule ID 150 //
23843 /* 63197 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23844 /* 63197 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
23845 /* 63202 */ GIR_RootConstrainSelectedInstOperands,
23846 /* 63203 */ // GIR_Coverage, 150,
23847 /* 63203 */ GIR_Done,
23848 /* 63204 */ // Label 1718: @63204
23849 /* 63204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1719*/ GIMT_Encode4(63218), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1234 //
23850 /* 63211 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23851 /* 63211 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
23852 /* 63216 */ GIR_RootConstrainSelectedInstOperands,
23853 /* 63217 */ // GIR_Coverage, 1234,
23854 /* 63217 */ GIR_Done,
23855 /* 63218 */ // Label 1719: @63218
23856 /* 63218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1720*/ GIMT_Encode4(63232), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1279 //
23857 /* 63225 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23858 /* 63225 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
23859 /* 63230 */ GIR_RootConstrainSelectedInstOperands,
23860 /* 63231 */ // GIR_Coverage, 1279,
23861 /* 63231 */ GIR_Done,
23862 /* 63232 */ // Label 1720: @63232
23863 /* 63232 */ GIM_Reject,
23864 /* 63233 */ // Label 1717: @63233
23865 /* 63233 */ GIM_Reject,
23866 /* 63234 */ // Label 1715: @63234
23867 /* 63234 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(63331),
23868 /* 63239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23869 /* 63242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1722*/ GIMT_Encode4(63264), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 151 //
23870 /* 63249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23871 /* 63253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23872 /* 63257 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23873 /* 63257 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
23874 /* 63262 */ GIR_RootConstrainSelectedInstOperands,
23875 /* 63263 */ // GIR_Coverage, 151,
23876 /* 63263 */ GIR_Done,
23877 /* 63264 */ // Label 1722: @63264
23878 /* 63264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1723*/ GIMT_Encode4(63286), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 152 //
23879 /* 63271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23880 /* 63275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23881 /* 63279 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23882 /* 63279 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
23883 /* 63284 */ GIR_RootConstrainSelectedInstOperands,
23884 /* 63285 */ // GIR_Coverage, 152,
23885 /* 63285 */ GIR_Done,
23886 /* 63286 */ // Label 1723: @63286
23887 /* 63286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1724*/ GIMT_Encode4(63308), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1235 //
23888 /* 63293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23889 /* 63297 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23890 /* 63301 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23891 /* 63301 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
23892 /* 63306 */ GIR_RootConstrainSelectedInstOperands,
23893 /* 63307 */ // GIR_Coverage, 1235,
23894 /* 63307 */ GIR_Done,
23895 /* 63308 */ // Label 1724: @63308
23896 /* 63308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1725*/ GIMT_Encode4(63330), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1236 //
23897 /* 63315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23898 /* 63319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23899 /* 63323 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23900 /* 63323 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
23901 /* 63328 */ GIR_RootConstrainSelectedInstOperands,
23902 /* 63329 */ // GIR_Coverage, 1236,
23903 /* 63329 */ GIR_Done,
23904 /* 63330 */ // Label 1725: @63330
23905 /* 63330 */ GIM_Reject,
23906 /* 63331 */ // Label 1721: @63331
23907 /* 63331 */ GIM_Reject,
23908 /* 63332 */ // Label 1716: @63332
23909 /* 63332 */ GIM_Reject,
23910 /* 63333 */ // Label 55: @63333
23911 /* 63333 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(63447),
23912 /* 63338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23913 /* 63341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23914 /* 63344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1727*/ GIMT_Encode4(63370), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1605 //
23915 /* 63351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23916 /* 63355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23917 /* 63359 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23918 /* 63359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
23919 /* 63364 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23920 /* 63368 */ GIR_RootConstrainSelectedInstOperands,
23921 /* 63369 */ // GIR_Coverage, 1605,
23922 /* 63369 */ GIR_Done,
23923 /* 63370 */ // Label 1727: @63370
23924 /* 63370 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(63420),
23925 /* 63375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23926 /* 63379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23927 /* 63383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1729*/ GIMT_Encode4(63401), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1622 //
23928 /* 63390 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23929 /* 63390 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
23930 /* 63395 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23931 /* 63399 */ GIR_RootConstrainSelectedInstOperands,
23932 /* 63400 */ // GIR_Coverage, 1622,
23933 /* 63400 */ GIR_Done,
23934 /* 63401 */ // Label 1729: @63401
23935 /* 63401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1730*/ GIMT_Encode4(63419), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2549 //
23936 /* 63408 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23937 /* 63408 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
23938 /* 63413 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23939 /* 63417 */ GIR_RootConstrainSelectedInstOperands,
23940 /* 63418 */ // GIR_Coverage, 2549,
23941 /* 63418 */ GIR_Done,
23942 /* 63419 */ // Label 1730: @63419
23943 /* 63419 */ GIM_Reject,
23944 /* 63420 */ // Label 1728: @63420
23945 /* 63420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1731*/ GIMT_Encode4(63446), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2551 //
23946 /* 63427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23947 /* 63431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23948 /* 63435 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23949 /* 63435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
23950 /* 63440 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23951 /* 63444 */ GIR_RootConstrainSelectedInstOperands,
23952 /* 63445 */ // GIR_Coverage, 2551,
23953 /* 63445 */ GIR_Done,
23954 /* 63446 */ // Label 1731: @63446
23955 /* 63446 */ GIM_Reject,
23956 /* 63447 */ // Label 1726: @63447
23957 /* 63447 */ GIM_Reject,
23958 /* 63448 */ // Label 56: @63448
23959 /* 63448 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(63554),
23960 /* 63453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23961 /* 63456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23962 /* 63459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23963 /* 63463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1733*/ GIMT_Encode4(63485), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1603 //
23964 /* 63470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23965 /* 63474 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23966 /* 63474 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
23967 /* 63479 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23968 /* 63483 */ GIR_RootConstrainSelectedInstOperands,
23969 /* 63484 */ // GIR_Coverage, 1603,
23970 /* 63484 */ GIR_Done,
23971 /* 63485 */ // Label 1733: @63485
23972 /* 63485 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(63531),
23973 /* 63490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23974 /* 63494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1735*/ GIMT_Encode4(63512), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1620 //
23975 /* 63501 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23976 /* 63501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
23977 /* 63506 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23978 /* 63510 */ GIR_RootConstrainSelectedInstOperands,
23979 /* 63511 */ // GIR_Coverage, 1620,
23980 /* 63511 */ GIR_Done,
23981 /* 63512 */ // Label 1735: @63512
23982 /* 63512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1736*/ GIMT_Encode4(63530), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2548 //
23983 /* 63519 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23984 /* 63519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
23985 /* 63524 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23986 /* 63528 */ GIR_RootConstrainSelectedInstOperands,
23987 /* 63529 */ // GIR_Coverage, 2548,
23988 /* 63529 */ GIR_Done,
23989 /* 63530 */ // Label 1736: @63530
23990 /* 63530 */ GIM_Reject,
23991 /* 63531 */ // Label 1734: @63531
23992 /* 63531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1737*/ GIMT_Encode4(63553), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2550 //
23993 /* 63538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23994 /* 63542 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23995 /* 63542 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
23996 /* 63547 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23997 /* 63551 */ GIR_RootConstrainSelectedInstOperands,
23998 /* 63552 */ // GIR_Coverage, 2550,
23999 /* 63552 */ GIR_Done,
24000 /* 63553 */ // Label 1737: @63553
24001 /* 63553 */ GIM_Reject,
24002 /* 63554 */ // Label 1732: @63554
24003 /* 63554 */ GIM_Reject,
24004 /* 63555 */ // Label 57: @63555
24005 /* 63555 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1740*/ GIMT_Encode4(63626),
24006 /* 63566 */ /*GILLT_v4s32*//*Label 1738*/ GIMT_Encode4(63574),
24007 /* 63570 */ /*GILLT_v2s64*//*Label 1739*/ GIMT_Encode4(63600),
24008 /* 63574 */ // Label 1738: @63574
24009 /* 63574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1741*/ GIMT_Encode4(63599), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 839 //
24010 /* 63581 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24011 /* 63584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24012 /* 63588 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24013 /* 63592 */ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24014 /* 63592 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
24015 /* 63597 */ GIR_RootConstrainSelectedInstOperands,
24016 /* 63598 */ // GIR_Coverage, 839,
24017 /* 63598 */ GIR_Done,
24018 /* 63599 */ // Label 1741: @63599
24019 /* 63599 */ GIM_Reject,
24020 /* 63600 */ // Label 1739: @63600
24021 /* 63600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1742*/ GIMT_Encode4(63625), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 840 //
24022 /* 63607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24023 /* 63610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24024 /* 63614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24025 /* 63618 */ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24026 /* 63618 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
24027 /* 63623 */ GIR_RootConstrainSelectedInstOperands,
24028 /* 63624 */ // GIR_Coverage, 840,
24029 /* 63624 */ GIR_Done,
24030 /* 63625 */ // Label 1742: @63625
24031 /* 63625 */ GIM_Reject,
24032 /* 63626 */ // Label 1740: @63626
24033 /* 63626 */ GIM_Reject,
24034 /* 63627 */ // Label 58: @63627
24035 /* 63627 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1745*/ GIMT_Encode4(63698),
24036 /* 63638 */ /*GILLT_v4s32*//*Label 1743*/ GIMT_Encode4(63646),
24037 /* 63642 */ /*GILLT_v2s64*//*Label 1744*/ GIMT_Encode4(63672),
24038 /* 63646 */ // Label 1743: @63646
24039 /* 63646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1746*/ GIMT_Encode4(63671), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 841 //
24040 /* 63653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24041 /* 63656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24042 /* 63660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24043 /* 63664 */ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24044 /* 63664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
24045 /* 63669 */ GIR_RootConstrainSelectedInstOperands,
24046 /* 63670 */ // GIR_Coverage, 841,
24047 /* 63670 */ GIR_Done,
24048 /* 63671 */ // Label 1746: @63671
24049 /* 63671 */ GIM_Reject,
24050 /* 63672 */ // Label 1744: @63672
24051 /* 63672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1747*/ GIMT_Encode4(63697), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 842 //
24052 /* 63679 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24053 /* 63682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24054 /* 63686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24055 /* 63690 */ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24056 /* 63690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
24057 /* 63695 */ GIR_RootConstrainSelectedInstOperands,
24058 /* 63696 */ // GIR_Coverage, 842,
24059 /* 63696 */ GIR_Done,
24060 /* 63697 */ // Label 1747: @63697
24061 /* 63697 */ GIM_Reject,
24062 /* 63698 */ // Label 1745: @63698
24063 /* 63698 */ GIM_Reject,
24064 /* 63699 */ // Label 59: @63699
24065 /* 63699 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1752*/ GIMT_Encode4(63980),
24066 /* 63710 */ /*GILLT_s32*//*Label 1748*/ GIMT_Encode4(63742),
24067 /* 63714 */ /*GILLT_s64*//*Label 1749*/ GIMT_Encode4(63840), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
24068 /* 63734 */ /*GILLT_v4s32*//*Label 1750*/ GIMT_Encode4(63928),
24069 /* 63738 */ /*GILLT_v2s64*//*Label 1751*/ GIMT_Encode4(63954),
24070 /* 63742 */ // Label 1748: @63742
24071 /* 63742 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1755*/ GIMT_Encode4(63839),
24072 /* 63753 */ /*GILLT_s32*//*Label 1753*/ GIMT_Encode4(63761),
24073 /* 63757 */ /*GILLT_s64*//*Label 1754*/ GIMT_Encode4(63782),
24074 /* 63761 */ // Label 1753: @63761
24075 /* 63761 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(63781), // Rule ID 1593 //
24076 /* 63766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24077 /* 63770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24078 /* 63774 */ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
24079 /* 63774 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
24080 /* 63779 */ GIR_RootConstrainSelectedInstOperands,
24081 /* 63780 */ // GIR_Coverage, 1593,
24082 /* 63780 */ GIR_Done,
24083 /* 63781 */ // Label 1756: @63781
24084 /* 63781 */ GIM_Reject,
24085 /* 63782 */ // Label 1754: @63782
24086 /* 63782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1757*/ GIMT_Encode4(63838), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1613 //
24087 /* 63789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24088 /* 63793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24089 /* 63797 */ // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
24090 /* 63797 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24091 /* 63800 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
24092 /* 63804 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24093 /* 63809 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
24094 /* 63813 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24095 /* 63815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24096 /* 63818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24097 /* 63820 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
24098 /* 63827 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
24099 /* 63832 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
24100 /* 63837 */ // GIR_Coverage, 1613,
24101 /* 63837 */ GIR_EraseRootFromParent_Done,
24102 /* 63838 */ // Label 1757: @63838
24103 /* 63838 */ GIM_Reject,
24104 /* 63839 */ // Label 1755: @63839
24105 /* 63839 */ GIM_Reject,
24106 /* 63840 */ // Label 1749: @63840
24107 /* 63840 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1760*/ GIMT_Encode4(63927),
24108 /* 63851 */ /*GILLT_s32*//*Label 1758*/ GIMT_Encode4(63859),
24109 /* 63855 */ /*GILLT_s64*//*Label 1759*/ GIMT_Encode4(63904),
24110 /* 63859 */ // Label 1758: @63859
24111 /* 63859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1761*/ GIMT_Encode4(63881), GIMT_Encode2(GIFBS_IsNotSingleFloat_NotFP64bit), // Rule ID 1600 //
24112 /* 63866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24113 /* 63870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24114 /* 63874 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
24115 /* 63874 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
24116 /* 63879 */ GIR_RootConstrainSelectedInstOperands,
24117 /* 63880 */ // GIR_Coverage, 1600,
24118 /* 63880 */ GIR_Done,
24119 /* 63881 */ // Label 1761: @63881
24120 /* 63881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1762*/ GIMT_Encode4(63903), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1611 //
24121 /* 63888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24122 /* 63892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24123 /* 63896 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
24124 /* 63896 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
24125 /* 63901 */ GIR_RootConstrainSelectedInstOperands,
24126 /* 63902 */ // GIR_Coverage, 1611,
24127 /* 63902 */ GIR_Done,
24128 /* 63903 */ // Label 1762: @63903
24129 /* 63903 */ GIM_Reject,
24130 /* 63904 */ // Label 1759: @63904
24131 /* 63904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1763*/ GIMT_Encode4(63926), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1615 //
24132 /* 63911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24133 /* 63915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24134 /* 63919 */ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
24135 /* 63919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
24136 /* 63924 */ GIR_RootConstrainSelectedInstOperands,
24137 /* 63925 */ // GIR_Coverage, 1615,
24138 /* 63925 */ GIR_Done,
24139 /* 63926 */ // Label 1763: @63926
24140 /* 63926 */ GIM_Reject,
24141 /* 63927 */ // Label 1760: @63927
24142 /* 63927 */ GIM_Reject,
24143 /* 63928 */ // Label 1750: @63928
24144 /* 63928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1764*/ GIMT_Encode4(63953), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 771 //
24145 /* 63935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24146 /* 63938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24147 /* 63942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24148 /* 63946 */ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24149 /* 63946 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
24150 /* 63951 */ GIR_RootConstrainSelectedInstOperands,
24151 /* 63952 */ // GIR_Coverage, 771,
24152 /* 63952 */ GIR_Done,
24153 /* 63953 */ // Label 1764: @63953
24154 /* 63953 */ GIM_Reject,
24155 /* 63954 */ // Label 1751: @63954
24156 /* 63954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1765*/ GIMT_Encode4(63979), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 772 //
24157 /* 63961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24158 /* 63964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24159 /* 63968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24160 /* 63972 */ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24161 /* 63972 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
24162 /* 63977 */ GIR_RootConstrainSelectedInstOperands,
24163 /* 63978 */ // GIR_Coverage, 772,
24164 /* 63978 */ GIR_Done,
24165 /* 63979 */ // Label 1765: @63979
24166 /* 63979 */ GIM_Reject,
24167 /* 63980 */ // Label 1752: @63980
24168 /* 63980 */ GIM_Reject,
24169 /* 63981 */ // Label 60: @63981
24170 /* 63981 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1768*/ GIMT_Encode4(64052),
24171 /* 63992 */ /*GILLT_v4s32*//*Label 1766*/ GIMT_Encode4(64000),
24172 /* 63996 */ /*GILLT_v2s64*//*Label 1767*/ GIMT_Encode4(64026),
24173 /* 64000 */ // Label 1766: @64000
24174 /* 64000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1769*/ GIMT_Encode4(64025), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 773 //
24175 /* 64007 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24176 /* 64010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24177 /* 64014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24178 /* 64018 */ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24179 /* 64018 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
24180 /* 64023 */ GIR_RootConstrainSelectedInstOperands,
24181 /* 64024 */ // GIR_Coverage, 773,
24182 /* 64024 */ GIR_Done,
24183 /* 64025 */ // Label 1769: @64025
24184 /* 64025 */ GIM_Reject,
24185 /* 64026 */ // Label 1767: @64026
24186 /* 64026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1770*/ GIMT_Encode4(64051), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 774 //
24187 /* 64033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24188 /* 64036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24189 /* 64040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24190 /* 64044 */ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24191 /* 64044 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
24192 /* 64049 */ GIR_RootConstrainSelectedInstOperands,
24193 /* 64050 */ // GIR_Coverage, 774,
24194 /* 64050 */ GIR_Done,
24195 /* 64051 */ // Label 1770: @64051
24196 /* 64051 */ GIM_Reject,
24197 /* 64052 */ // Label 1768: @64052
24198 /* 64052 */ GIM_Reject,
24199 /* 64053 */ // Label 61: @64053
24200 /* 64053 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1775*/ GIMT_Encode4(64292),
24201 /* 64064 */ /*GILLT_s32*//*Label 1771*/ GIMT_Encode4(64096),
24202 /* 64068 */ /*GILLT_s64*//*Label 1772*/ GIMT_Encode4(64142), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
24203 /* 64088 */ /*GILLT_v4s32*//*Label 1773*/ GIMT_Encode4(64240),
24204 /* 64092 */ /*GILLT_v2s64*//*Label 1774*/ GIMT_Encode4(64266),
24205 /* 64096 */ // Label 1771: @64096
24206 /* 64096 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(64141),
24207 /* 64101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24208 /* 64104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24209 /* 64108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24210 /* 64112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1777*/ GIMT_Encode4(64126), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 147 //
24211 /* 64119 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24212 /* 64119 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S),
24213 /* 64124 */ GIR_RootConstrainSelectedInstOperands,
24214 /* 64125 */ // GIR_Coverage, 147,
24215 /* 64125 */ GIR_Done,
24216 /* 64126 */ // Label 1777: @64126
24217 /* 64126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1778*/ GIMT_Encode4(64140), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1233 //
24218 /* 64133 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24219 /* 64133 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S_MM),
24220 /* 64138 */ GIR_RootConstrainSelectedInstOperands,
24221 /* 64139 */ // GIR_Coverage, 1233,
24222 /* 64139 */ GIR_Done,
24223 /* 64140 */ // Label 1778: @64140
24224 /* 64140 */ GIM_Reject,
24225 /* 64141 */ // Label 1776: @64141
24226 /* 64141 */ GIM_Reject,
24227 /* 64142 */ // Label 1772: @64142
24228 /* 64142 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(64239),
24229 /* 64147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24230 /* 64150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1780*/ GIMT_Encode4(64172), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 148 //
24231 /* 64157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24232 /* 64161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24233 /* 64165 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24234 /* 64165 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32),
24235 /* 64170 */ GIR_RootConstrainSelectedInstOperands,
24236 /* 64171 */ // GIR_Coverage, 148,
24237 /* 64171 */ GIR_Done,
24238 /* 64172 */ // Label 1780: @64172
24239 /* 64172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1781*/ GIMT_Encode4(64194), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 149 //
24240 /* 64179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24241 /* 64183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24242 /* 64187 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24243 /* 64187 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64),
24244 /* 64192 */ GIR_RootConstrainSelectedInstOperands,
24245 /* 64193 */ // GIR_Coverage, 149,
24246 /* 64193 */ GIR_Done,
24247 /* 64194 */ // Label 1781: @64194
24248 /* 64194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1782*/ GIMT_Encode4(64216), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1231 //
24249 /* 64201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24250 /* 64205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24251 /* 64209 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24252 /* 64209 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
24253 /* 64214 */ GIR_RootConstrainSelectedInstOperands,
24254 /* 64215 */ // GIR_Coverage, 1231,
24255 /* 64215 */ GIR_Done,
24256 /* 64216 */ // Label 1782: @64216
24257 /* 64216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1783*/ GIMT_Encode4(64238), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1232 //
24258 /* 64223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24259 /* 64227 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24260 /* 64231 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24261 /* 64231 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
24262 /* 64236 */ GIR_RootConstrainSelectedInstOperands,
24263 /* 64237 */ // GIR_Coverage, 1232,
24264 /* 64237 */ GIR_Done,
24265 /* 64238 */ // Label 1783: @64238
24266 /* 64238 */ GIM_Reject,
24267 /* 64239 */ // Label 1779: @64239
24268 /* 64239 */ GIM_Reject,
24269 /* 64240 */ // Label 1773: @64240
24270 /* 64240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1784*/ GIMT_Encode4(64265), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1113 //
24271 /* 64247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24272 /* 64250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24273 /* 64254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24274 /* 64258 */ // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24275 /* 64258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
24276 /* 64263 */ GIR_RootConstrainSelectedInstOperands,
24277 /* 64264 */ // GIR_Coverage, 1113,
24278 /* 64264 */ GIR_Done,
24279 /* 64265 */ // Label 1784: @64265
24280 /* 64265 */ GIM_Reject,
24281 /* 64266 */ // Label 1774: @64266
24282 /* 64266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1785*/ GIMT_Encode4(64291), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1114 //
24283 /* 64273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24284 /* 64276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24285 /* 64280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24286 /* 64284 */ // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24287 /* 64284 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
24288 /* 64289 */ GIR_RootConstrainSelectedInstOperands,
24289 /* 64290 */ // GIR_Coverage, 1114,
24290 /* 64290 */ GIR_Done,
24291 /* 64291 */ // Label 1785: @64291
24292 /* 64291 */ GIM_Reject,
24293 /* 64292 */ // Label 1775: @64292
24294 /* 64292 */ GIM_Reject,
24295 /* 64293 */ // Label 62: @64293
24296 /* 64293 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1788*/ GIMT_Encode4(64364),
24297 /* 64304 */ /*GILLT_s32*//*Label 1786*/ GIMT_Encode4(64312),
24298 /* 64308 */ /*GILLT_s64*//*Label 1787*/ GIMT_Encode4(64338),
24299 /* 64312 */ // Label 1786: @64312
24300 /* 64312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1789*/ GIMT_Encode4(64337), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2009 //
24301 /* 64319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24302 /* 64322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24303 /* 64326 */ // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
24304 /* 64326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24305 /* 64329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24306 /* 64331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24307 /* 64333 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24308 /* 64335 */ GIR_RootConstrainSelectedInstOperands,
24309 /* 64336 */ // GIR_Coverage, 2009,
24310 /* 64336 */ GIR_EraseRootFromParent_Done,
24311 /* 64337 */ // Label 1789: @64337
24312 /* 64337 */ GIM_Reject,
24313 /* 64338 */ // Label 1787: @64338
24314 /* 64338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1790*/ GIMT_Encode4(64363), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2010 //
24315 /* 64345 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24316 /* 64348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24317 /* 64352 */ // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
24318 /* 64352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24319 /* 64355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24320 /* 64357 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24321 /* 64359 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24322 /* 64361 */ GIR_RootConstrainSelectedInstOperands,
24323 /* 64362 */ // GIR_Coverage, 2010,
24324 /* 64362 */ GIR_EraseRootFromParent_Done,
24325 /* 64363 */ // Label 1790: @64363
24326 /* 64363 */ GIM_Reject,
24327 /* 64364 */ // Label 1788: @64364
24328 /* 64364 */ GIM_Reject,
24329 /* 64365 */ // Label 63: @64365
24330 /* 64365 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1793*/ GIMT_Encode4(64434),
24331 /* 64376 */ /*GILLT_s32*//*Label 1791*/ GIMT_Encode4(64384),
24332 /* 64380 */ /*GILLT_s64*//*Label 1792*/ GIMT_Encode4(64409),
24333 /* 64384 */ // Label 1791: @64384
24334 /* 64384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1794*/ GIMT_Encode4(64408), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2006 //
24335 /* 64391 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24336 /* 64394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24337 /* 64397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24338 /* 64401 */ // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24339 /* 64401 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24340 /* 64406 */ GIR_RootConstrainSelectedInstOperands,
24341 /* 64407 */ // GIR_Coverage, 2006,
24342 /* 64407 */ GIR_Done,
24343 /* 64408 */ // Label 1794: @64408
24344 /* 64408 */ GIM_Reject,
24345 /* 64409 */ // Label 1792: @64409
24346 /* 64409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1795*/ GIMT_Encode4(64433), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2008 //
24347 /* 64416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24348 /* 64419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24349 /* 64422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24350 /* 64426 */ // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24351 /* 64426 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24352 /* 64431 */ GIR_RootConstrainSelectedInstOperands,
24353 /* 64432 */ // GIR_Coverage, 2008,
24354 /* 64432 */ GIR_Done,
24355 /* 64433 */ // Label 1795: @64433
24356 /* 64433 */ GIM_Reject,
24357 /* 64434 */ // Label 1793: @64434
24358 /* 64434 */ GIM_Reject,
24359 /* 64435 */ // Label 64: @64435
24360 /* 64435 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1798*/ GIMT_Encode4(64504),
24361 /* 64446 */ /*GILLT_s32*//*Label 1796*/ GIMT_Encode4(64454),
24362 /* 64450 */ /*GILLT_s64*//*Label 1797*/ GIMT_Encode4(64479),
24363 /* 64454 */ // Label 1796: @64454
24364 /* 64454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1799*/ GIMT_Encode4(64478), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2002 //
24365 /* 64461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24366 /* 64464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24367 /* 64467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24368 /* 64471 */ // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24369 /* 64471 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
24370 /* 64476 */ GIR_RootConstrainSelectedInstOperands,
24371 /* 64477 */ // GIR_Coverage, 2002,
24372 /* 64477 */ GIR_Done,
24373 /* 64478 */ // Label 1799: @64478
24374 /* 64478 */ GIM_Reject,
24375 /* 64479 */ // Label 1797: @64479
24376 /* 64479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1800*/ GIMT_Encode4(64503), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2004 //
24377 /* 64486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24378 /* 64489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24379 /* 64492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24380 /* 64496 */ // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24381 /* 64496 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
24382 /* 64501 */ GIR_RootConstrainSelectedInstOperands,
24383 /* 64502 */ // GIR_Coverage, 2004,
24384 /* 64502 */ GIR_Done,
24385 /* 64503 */ // Label 1800: @64503
24386 /* 64503 */ GIM_Reject,
24387 /* 64504 */ // Label 1798: @64504
24388 /* 64504 */ GIM_Reject,
24389 /* 64505 */ // Label 65: @64505
24390 /* 64505 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1803*/ GIMT_Encode4(64574),
24391 /* 64516 */ /*GILLT_s32*//*Label 1801*/ GIMT_Encode4(64524),
24392 /* 64520 */ /*GILLT_s64*//*Label 1802*/ GIMT_Encode4(64549),
24393 /* 64524 */ // Label 1801: @64524
24394 /* 64524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1804*/ GIMT_Encode4(64548), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2005 //
24395 /* 64531 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24396 /* 64534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24397 /* 64537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24398 /* 64541 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24399 /* 64541 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24400 /* 64546 */ GIR_RootConstrainSelectedInstOperands,
24401 /* 64547 */ // GIR_Coverage, 2005,
24402 /* 64547 */ GIR_Done,
24403 /* 64548 */ // Label 1804: @64548
24404 /* 64548 */ GIM_Reject,
24405 /* 64549 */ // Label 1802: @64549
24406 /* 64549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1805*/ GIMT_Encode4(64573), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2007 //
24407 /* 64556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24408 /* 64559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24409 /* 64562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24410 /* 64566 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24411 /* 64566 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24412 /* 64571 */ GIR_RootConstrainSelectedInstOperands,
24413 /* 64572 */ // GIR_Coverage, 2007,
24414 /* 64572 */ GIR_Done,
24415 /* 64573 */ // Label 1805: @64573
24416 /* 64573 */ GIM_Reject,
24417 /* 64574 */ // Label 1803: @64574
24418 /* 64574 */ GIM_Reject,
24419 /* 64575 */ // Label 66: @64575
24420 /* 64575 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1808*/ GIMT_Encode4(64644),
24421 /* 64586 */ /*GILLT_s32*//*Label 1806*/ GIMT_Encode4(64594),
24422 /* 64590 */ /*GILLT_s64*//*Label 1807*/ GIMT_Encode4(64619),
24423 /* 64594 */ // Label 1806: @64594
24424 /* 64594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(64618), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2001 //
24425 /* 64601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24426 /* 64604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24427 /* 64607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24428 /* 64611 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24429 /* 64611 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
24430 /* 64616 */ GIR_RootConstrainSelectedInstOperands,
24431 /* 64617 */ // GIR_Coverage, 2001,
24432 /* 64617 */ GIR_Done,
24433 /* 64618 */ // Label 1809: @64618
24434 /* 64618 */ GIM_Reject,
24435 /* 64619 */ // Label 1807: @64619
24436 /* 64619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1810*/ GIMT_Encode4(64643), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 2003 //
24437 /* 64626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24438 /* 64629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24439 /* 64632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24440 /* 64636 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24441 /* 64636 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
24442 /* 64641 */ GIR_RootConstrainSelectedInstOperands,
24443 /* 64642 */ // GIR_Coverage, 2003,
24444 /* 64642 */ GIR_Done,
24445 /* 64643 */ // Label 1810: @64643
24446 /* 64643 */ GIM_Reject,
24447 /* 64644 */ // Label 1808: @64644
24448 /* 64644 */ GIM_Reject,
24449 /* 64645 */ // Label 67: @64645
24450 /* 64645 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1815*/ GIMT_Encode4(64808),
24451 /* 64656 */ /*GILLT_v16s8*//*Label 1811*/ GIMT_Encode4(64676), GIMT_Encode4(0),
24452 /* 64664 */ /*GILLT_v8s16*//*Label 1812*/ GIMT_Encode4(64709),
24453 /* 64668 */ /*GILLT_v4s32*//*Label 1813*/ GIMT_Encode4(64742),
24454 /* 64672 */ /*GILLT_v2s64*//*Label 1814*/ GIMT_Encode4(64775),
24455 /* 64676 */ // Label 1811: @64676
24456 /* 64676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1816*/ GIMT_Encode4(64708), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 935 //
24457 /* 64683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24458 /* 64686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24459 /* 64689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24460 /* 64693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24461 /* 64697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24462 /* 64701 */ // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24463 /* 64701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
24464 /* 64706 */ GIR_RootConstrainSelectedInstOperands,
24465 /* 64707 */ // GIR_Coverage, 935,
24466 /* 64707 */ GIR_Done,
24467 /* 64708 */ // Label 1816: @64708
24468 /* 64708 */ GIM_Reject,
24469 /* 64709 */ // Label 1812: @64709
24470 /* 64709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1817*/ GIMT_Encode4(64741), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 936 //
24471 /* 64716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24472 /* 64719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24473 /* 64722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24474 /* 64726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24475 /* 64730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24476 /* 64734 */ // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24477 /* 64734 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
24478 /* 64739 */ GIR_RootConstrainSelectedInstOperands,
24479 /* 64740 */ // GIR_Coverage, 936,
24480 /* 64740 */ GIR_Done,
24481 /* 64741 */ // Label 1817: @64741
24482 /* 64741 */ GIM_Reject,
24483 /* 64742 */ // Label 1813: @64742
24484 /* 64742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1818*/ GIMT_Encode4(64774), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 937 //
24485 /* 64749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24486 /* 64752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24487 /* 64755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24488 /* 64759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24489 /* 64763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24490 /* 64767 */ // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24491 /* 64767 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
24492 /* 64772 */ GIR_RootConstrainSelectedInstOperands,
24493 /* 64773 */ // GIR_Coverage, 937,
24494 /* 64773 */ GIR_Done,
24495 /* 64774 */ // Label 1818: @64774
24496 /* 64774 */ GIM_Reject,
24497 /* 64775 */ // Label 1814: @64775
24498 /* 64775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1819*/ GIMT_Encode4(64807), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 938 //
24499 /* 64782 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24500 /* 64785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24501 /* 64788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24502 /* 64792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24503 /* 64796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24504 /* 64800 */ // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24505 /* 64800 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
24506 /* 64805 */ GIR_RootConstrainSelectedInstOperands,
24507 /* 64806 */ // GIR_Coverage, 938,
24508 /* 64806 */ GIR_Done,
24509 /* 64807 */ // Label 1819: @64807
24510 /* 64807 */ GIM_Reject,
24511 /* 64808 */ // Label 1815: @64808
24512 /* 64808 */ GIM_Reject,
24513 /* 64809 */ // Label 68: @64809
24514 /* 64809 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1824*/ GIMT_Encode4(64972),
24515 /* 64820 */ /*GILLT_v16s8*//*Label 1820*/ GIMT_Encode4(64840), GIMT_Encode4(0),
24516 /* 64828 */ /*GILLT_v8s16*//*Label 1821*/ GIMT_Encode4(64873),
24517 /* 64832 */ /*GILLT_v4s32*//*Label 1822*/ GIMT_Encode4(64906),
24518 /* 64836 */ /*GILLT_v2s64*//*Label 1823*/ GIMT_Encode4(64939),
24519 /* 64840 */ // Label 1820: @64840
24520 /* 64840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1825*/ GIMT_Encode4(64872), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 915 //
24521 /* 64847 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24522 /* 64850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24523 /* 64853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24524 /* 64857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24525 /* 64861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24526 /* 64865 */ // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24527 /* 64865 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
24528 /* 64870 */ GIR_RootConstrainSelectedInstOperands,
24529 /* 64871 */ // GIR_Coverage, 915,
24530 /* 64871 */ GIR_Done,
24531 /* 64872 */ // Label 1825: @64872
24532 /* 64872 */ GIM_Reject,
24533 /* 64873 */ // Label 1821: @64873
24534 /* 64873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1826*/ GIMT_Encode4(64905), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 916 //
24535 /* 64880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24536 /* 64883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24537 /* 64886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24538 /* 64890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24539 /* 64894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24540 /* 64898 */ // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24541 /* 64898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
24542 /* 64903 */ GIR_RootConstrainSelectedInstOperands,
24543 /* 64904 */ // GIR_Coverage, 916,
24544 /* 64904 */ GIR_Done,
24545 /* 64905 */ // Label 1826: @64905
24546 /* 64905 */ GIM_Reject,
24547 /* 64906 */ // Label 1822: @64906
24548 /* 64906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(64938), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 917 //
24549 /* 64913 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24550 /* 64916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24551 /* 64919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24552 /* 64923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24553 /* 64927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24554 /* 64931 */ // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24555 /* 64931 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
24556 /* 64936 */ GIR_RootConstrainSelectedInstOperands,
24557 /* 64937 */ // GIR_Coverage, 917,
24558 /* 64937 */ GIR_Done,
24559 /* 64938 */ // Label 1827: @64938
24560 /* 64938 */ GIM_Reject,
24561 /* 64939 */ // Label 1823: @64939
24562 /* 64939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1828*/ GIMT_Encode4(64971), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 918 //
24563 /* 64946 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24564 /* 64949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24565 /* 64952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24566 /* 64956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24567 /* 64960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24568 /* 64964 */ // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24569 /* 64964 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
24570 /* 64969 */ GIR_RootConstrainSelectedInstOperands,
24571 /* 64970 */ // GIR_Coverage, 918,
24572 /* 64970 */ GIR_Done,
24573 /* 64971 */ // Label 1828: @64971
24574 /* 64971 */ GIM_Reject,
24575 /* 64972 */ // Label 1824: @64972
24576 /* 64972 */ GIM_Reject,
24577 /* 64973 */ // Label 69: @64973
24578 /* 64973 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1833*/ GIMT_Encode4(65136),
24579 /* 64984 */ /*GILLT_v16s8*//*Label 1829*/ GIMT_Encode4(65004), GIMT_Encode4(0),
24580 /* 64992 */ /*GILLT_v8s16*//*Label 1830*/ GIMT_Encode4(65037),
24581 /* 64996 */ /*GILLT_v4s32*//*Label 1831*/ GIMT_Encode4(65070),
24582 /* 65000 */ /*GILLT_v2s64*//*Label 1832*/ GIMT_Encode4(65103),
24583 /* 65004 */ // Label 1829: @65004
24584 /* 65004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1834*/ GIMT_Encode4(65036), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 939 //
24585 /* 65011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24586 /* 65014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24587 /* 65017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24588 /* 65021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24589 /* 65025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24590 /* 65029 */ // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24591 /* 65029 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
24592 /* 65034 */ GIR_RootConstrainSelectedInstOperands,
24593 /* 65035 */ // GIR_Coverage, 939,
24594 /* 65035 */ GIR_Done,
24595 /* 65036 */ // Label 1834: @65036
24596 /* 65036 */ GIM_Reject,
24597 /* 65037 */ // Label 1830: @65037
24598 /* 65037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1835*/ GIMT_Encode4(65069), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 940 //
24599 /* 65044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24600 /* 65047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24601 /* 65050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24602 /* 65054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24603 /* 65058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24604 /* 65062 */ // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24605 /* 65062 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
24606 /* 65067 */ GIR_RootConstrainSelectedInstOperands,
24607 /* 65068 */ // GIR_Coverage, 940,
24608 /* 65068 */ GIR_Done,
24609 /* 65069 */ // Label 1835: @65069
24610 /* 65069 */ GIM_Reject,
24611 /* 65070 */ // Label 1831: @65070
24612 /* 65070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1836*/ GIMT_Encode4(65102), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 941 //
24613 /* 65077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24614 /* 65080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24615 /* 65083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24616 /* 65087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24617 /* 65091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24618 /* 65095 */ // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24619 /* 65095 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
24620 /* 65100 */ GIR_RootConstrainSelectedInstOperands,
24621 /* 65101 */ // GIR_Coverage, 941,
24622 /* 65101 */ GIR_Done,
24623 /* 65102 */ // Label 1836: @65102
24624 /* 65102 */ GIM_Reject,
24625 /* 65103 */ // Label 1832: @65103
24626 /* 65103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1837*/ GIMT_Encode4(65135), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 942 //
24627 /* 65110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24628 /* 65113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24629 /* 65116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24630 /* 65120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24631 /* 65124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24632 /* 65128 */ // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24633 /* 65128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
24634 /* 65133 */ GIR_RootConstrainSelectedInstOperands,
24635 /* 65134 */ // GIR_Coverage, 942,
24636 /* 65134 */ GIR_Done,
24637 /* 65135 */ // Label 1837: @65135
24638 /* 65135 */ GIM_Reject,
24639 /* 65136 */ // Label 1833: @65136
24640 /* 65136 */ GIM_Reject,
24641 /* 65137 */ // Label 70: @65137
24642 /* 65137 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1842*/ GIMT_Encode4(65300),
24643 /* 65148 */ /*GILLT_v16s8*//*Label 1838*/ GIMT_Encode4(65168), GIMT_Encode4(0),
24644 /* 65156 */ /*GILLT_v8s16*//*Label 1839*/ GIMT_Encode4(65201),
24645 /* 65160 */ /*GILLT_v4s32*//*Label 1840*/ GIMT_Encode4(65234),
24646 /* 65164 */ /*GILLT_v2s64*//*Label 1841*/ GIMT_Encode4(65267),
24647 /* 65168 */ // Label 1838: @65168
24648 /* 65168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1843*/ GIMT_Encode4(65200), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 919 //
24649 /* 65175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24650 /* 65178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24651 /* 65181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24652 /* 65185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24653 /* 65189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24654 /* 65193 */ // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24655 /* 65193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
24656 /* 65198 */ GIR_RootConstrainSelectedInstOperands,
24657 /* 65199 */ // GIR_Coverage, 919,
24658 /* 65199 */ GIR_Done,
24659 /* 65200 */ // Label 1843: @65200
24660 /* 65200 */ GIM_Reject,
24661 /* 65201 */ // Label 1839: @65201
24662 /* 65201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1844*/ GIMT_Encode4(65233), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 920 //
24663 /* 65208 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24664 /* 65211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24665 /* 65214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24666 /* 65218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24667 /* 65222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24668 /* 65226 */ // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24669 /* 65226 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
24670 /* 65231 */ GIR_RootConstrainSelectedInstOperands,
24671 /* 65232 */ // GIR_Coverage, 920,
24672 /* 65232 */ GIR_Done,
24673 /* 65233 */ // Label 1844: @65233
24674 /* 65233 */ GIM_Reject,
24675 /* 65234 */ // Label 1840: @65234
24676 /* 65234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(65266), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 921 //
24677 /* 65241 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24678 /* 65244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24679 /* 65247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24680 /* 65251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24681 /* 65255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24682 /* 65259 */ // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24683 /* 65259 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
24684 /* 65264 */ GIR_RootConstrainSelectedInstOperands,
24685 /* 65265 */ // GIR_Coverage, 921,
24686 /* 65265 */ GIR_Done,
24687 /* 65266 */ // Label 1845: @65266
24688 /* 65266 */ GIM_Reject,
24689 /* 65267 */ // Label 1841: @65267
24690 /* 65267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1846*/ GIMT_Encode4(65299), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 922 //
24691 /* 65274 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24692 /* 65277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24693 /* 65280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24694 /* 65284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24695 /* 65288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24696 /* 65292 */ // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24697 /* 65292 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
24698 /* 65297 */ GIR_RootConstrainSelectedInstOperands,
24699 /* 65298 */ // GIR_Coverage, 922,
24700 /* 65298 */ GIR_Done,
24701 /* 65299 */ // Label 1846: @65299
24702 /* 65299 */ GIM_Reject,
24703 /* 65300 */ // Label 1842: @65300
24704 /* 65300 */ GIM_Reject,
24705 /* 65301 */ // Label 71: @65301
24706 /* 65301 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(65418),
24707 /* 65306 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
24708 /* 65309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1848*/ GIMT_Encode4(65329), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC), // Rule ID 111 //
24709 /* 65316 */ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
24710 /* 65316 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
24711 /* 65321 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::R1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24712 /* 65327 */ GIR_RootConstrainSelectedInstOperands,
24713 /* 65328 */ // GIR_Coverage, 111,
24714 /* 65328 */ GIR_Done,
24715 /* 65329 */ // Label 1848: @65329
24716 /* 65329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1849*/ GIMT_Encode4(65349), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 118 //
24717 /* 65336 */ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
24718 /* 65336 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
24719 /* 65341 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::R1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24720 /* 65347 */ GIR_RootConstrainSelectedInstOperands,
24721 /* 65348 */ // GIR_Coverage, 118,
24722 /* 65348 */ GIR_Done,
24723 /* 65349 */ // Label 1849: @65349
24724 /* 65349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1850*/ GIMT_Encode4(65369), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC), // Rule ID 1184 //
24725 /* 65356 */ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
24726 /* 65356 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
24727 /* 65361 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::R1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24728 /* 65367 */ GIR_RootConstrainSelectedInstOperands,
24729 /* 65368 */ // GIR_Coverage, 1184,
24730 /* 65368 */ GIR_Done,
24731 /* 65369 */ // Label 1850: @65369
24732 /* 65369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1851*/ GIMT_Encode4(65389), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC), // Rule ID 1193 //
24733 /* 65376 */ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
24734 /* 65376 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
24735 /* 65381 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::R1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24736 /* 65387 */ GIR_RootConstrainSelectedInstOperands,
24737 /* 65388 */ // GIR_Coverage, 1193,
24738 /* 65388 */ GIR_Done,
24739 /* 65389 */ // Label 1851: @65389
24740 /* 65389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1852*/ GIMT_Encode4(65403), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1258 //
24741 /* 65396 */ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
24742 /* 65396 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
24743 /* 65401 */ GIR_RootConstrainSelectedInstOperands,
24744 /* 65402 */ // GIR_Coverage, 1258,
24745 /* 65402 */ GIR_Done,
24746 /* 65403 */ // Label 1852: @65403
24747 /* 65403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1853*/ GIMT_Encode4(65417), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2114 //
24748 /* 65410 */ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
24749 /* 65410 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
24750 /* 65415 */ GIR_RootConstrainSelectedInstOperands,
24751 /* 65416 */ // GIR_Coverage, 2114,
24752 /* 65416 */ GIR_Done,
24753 /* 65417 */ // Label 1853: @65417
24754 /* 65417 */ GIM_Reject,
24755 /* 65418 */ // Label 1847: @65418
24756 /* 65418 */ GIM_Reject,
24757 /* 65419 */ // Label 72: @65419
24758 /* 65419 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1858*/ GIMT_Encode4(66010),
24759 /* 65430 */ /*GILLT_v16s8*//*Label 1854*/ GIMT_Encode4(65450), GIMT_Encode4(0),
24760 /* 65438 */ /*GILLT_v8s16*//*Label 1855*/ GIMT_Encode4(65556),
24761 /* 65442 */ /*GILLT_v4s32*//*Label 1856*/ GIMT_Encode4(65662),
24762 /* 65446 */ /*GILLT_v2s64*//*Label 1857*/ GIMT_Encode4(65836),
24763 /* 65450 */ // Label 1854: @65450
24764 /* 65450 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(65555),
24765 /* 65455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24766 /* 65458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24767 /* 65461 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1862*/ GIMT_Encode4(65554),
24768 /* 65472 */ /*GILLT_s32*//*Label 1860*/ GIMT_Encode4(65480),
24769 /* 65476 */ /*GILLT_s64*//*Label 1861*/ GIMT_Encode4(65517),
24770 /* 65480 */ // Label 1860: @65480
24771 /* 65480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1863*/ GIMT_Encode4(65516), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 881 //
24772 /* 65487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24773 /* 65491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24774 /* 65495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24775 /* 65499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24776 /* 65503 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24777 /* 65503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
24778 /* 65506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24779 /* 65508 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24780 /* 65510 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24781 /* 65512 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24782 /* 65514 */ GIR_RootConstrainSelectedInstOperands,
24783 /* 65515 */ // GIR_Coverage, 881,
24784 /* 65515 */ GIR_EraseRootFromParent_Done,
24785 /* 65516 */ // Label 1863: @65516
24786 /* 65516 */ GIM_Reject,
24787 /* 65517 */ // Label 1861: @65517
24788 /* 65517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1864*/ GIMT_Encode4(65553), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 887 //
24789 /* 65524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24790 /* 65528 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24791 /* 65532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24792 /* 65536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24793 /* 65540 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24794 /* 65540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
24795 /* 65543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24796 /* 65545 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24797 /* 65547 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24798 /* 65549 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24799 /* 65551 */ GIR_RootConstrainSelectedInstOperands,
24800 /* 65552 */ // GIR_Coverage, 887,
24801 /* 65552 */ GIR_EraseRootFromParent_Done,
24802 /* 65553 */ // Label 1864: @65553
24803 /* 65553 */ GIM_Reject,
24804 /* 65554 */ // Label 1862: @65554
24805 /* 65554 */ GIM_Reject,
24806 /* 65555 */ // Label 1859: @65555
24807 /* 65555 */ GIM_Reject,
24808 /* 65556 */ // Label 1855: @65556
24809 /* 65556 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(65661),
24810 /* 65561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24811 /* 65564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24812 /* 65567 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1868*/ GIMT_Encode4(65660),
24813 /* 65578 */ /*GILLT_s32*//*Label 1866*/ GIMT_Encode4(65586),
24814 /* 65582 */ /*GILLT_s64*//*Label 1867*/ GIMT_Encode4(65623),
24815 /* 65586 */ // Label 1866: @65586
24816 /* 65586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1869*/ GIMT_Encode4(65622), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 882 //
24817 /* 65593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24818 /* 65597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24819 /* 65601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24820 /* 65605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24821 /* 65609 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24822 /* 65609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
24823 /* 65612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24824 /* 65614 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24825 /* 65616 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24826 /* 65618 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24827 /* 65620 */ GIR_RootConstrainSelectedInstOperands,
24828 /* 65621 */ // GIR_Coverage, 882,
24829 /* 65621 */ GIR_EraseRootFromParent_Done,
24830 /* 65622 */ // Label 1869: @65622
24831 /* 65622 */ GIM_Reject,
24832 /* 65623 */ // Label 1867: @65623
24833 /* 65623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1870*/ GIMT_Encode4(65659), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 888 //
24834 /* 65630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24835 /* 65634 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24836 /* 65638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24837 /* 65642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24838 /* 65646 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24839 /* 65646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
24840 /* 65649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24841 /* 65651 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24842 /* 65653 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24843 /* 65655 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24844 /* 65657 */ GIR_RootConstrainSelectedInstOperands,
24845 /* 65658 */ // GIR_Coverage, 888,
24846 /* 65658 */ GIR_EraseRootFromParent_Done,
24847 /* 65659 */ // Label 1870: @65659
24848 /* 65659 */ GIM_Reject,
24849 /* 65660 */ // Label 1868: @65660
24850 /* 65660 */ GIM_Reject,
24851 /* 65661 */ // Label 1865: @65661
24852 /* 65661 */ GIM_Reject,
24853 /* 65662 */ // Label 1856: @65662
24854 /* 65662 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(65835),
24855 /* 65667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24856 /* 65670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24857 /* 65673 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1874*/ GIMT_Encode4(65834),
24858 /* 65684 */ /*GILLT_s32*//*Label 1872*/ GIMT_Encode4(65692),
24859 /* 65688 */ /*GILLT_s64*//*Label 1873*/ GIMT_Encode4(65763),
24860 /* 65692 */ // Label 1872: @65692
24861 /* 65692 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(65762),
24862 /* 65697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24863 /* 65701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24864 /* 65705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1876*/ GIMT_Encode4(65733), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 883 //
24865 /* 65712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24866 /* 65716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24867 /* 65720 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24868 /* 65720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
24869 /* 65723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24870 /* 65725 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24871 /* 65727 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24872 /* 65729 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24873 /* 65731 */ GIR_RootConstrainSelectedInstOperands,
24874 /* 65732 */ // GIR_Coverage, 883,
24875 /* 65732 */ GIR_EraseRootFromParent_Done,
24876 /* 65733 */ // Label 1876: @65733
24877 /* 65733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1877*/ GIMT_Encode4(65761), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 885 //
24878 /* 65740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24879 /* 65744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24880 /* 65748 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24881 /* 65748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
24882 /* 65751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24883 /* 65753 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24884 /* 65755 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24885 /* 65757 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24886 /* 65759 */ GIR_RootConstrainSelectedInstOperands,
24887 /* 65760 */ // GIR_Coverage, 885,
24888 /* 65760 */ GIR_EraseRootFromParent_Done,
24889 /* 65761 */ // Label 1877: @65761
24890 /* 65761 */ GIM_Reject,
24891 /* 65762 */ // Label 1875: @65762
24892 /* 65762 */ GIM_Reject,
24893 /* 65763 */ // Label 1873: @65763
24894 /* 65763 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(65833),
24895 /* 65768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24896 /* 65772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24897 /* 65776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1879*/ GIMT_Encode4(65804), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 889 //
24898 /* 65783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24899 /* 65787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24900 /* 65791 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24901 /* 65791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
24902 /* 65794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24903 /* 65796 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24904 /* 65798 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24905 /* 65800 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24906 /* 65802 */ GIR_RootConstrainSelectedInstOperands,
24907 /* 65803 */ // GIR_Coverage, 889,
24908 /* 65803 */ GIR_EraseRootFromParent_Done,
24909 /* 65804 */ // Label 1879: @65804
24910 /* 65804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1880*/ GIMT_Encode4(65832), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 891 //
24911 /* 65811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24912 /* 65815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24913 /* 65819 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24914 /* 65819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
24915 /* 65822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24916 /* 65824 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24917 /* 65826 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24918 /* 65828 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24919 /* 65830 */ GIR_RootConstrainSelectedInstOperands,
24920 /* 65831 */ // GIR_Coverage, 891,
24921 /* 65831 */ GIR_EraseRootFromParent_Done,
24922 /* 65832 */ // Label 1880: @65832
24923 /* 65832 */ GIM_Reject,
24924 /* 65833 */ // Label 1878: @65833
24925 /* 65833 */ GIM_Reject,
24926 /* 65834 */ // Label 1874: @65834
24927 /* 65834 */ GIM_Reject,
24928 /* 65835 */ // Label 1871: @65835
24929 /* 65835 */ GIM_Reject,
24930 /* 65836 */ // Label 1857: @65836
24931 /* 65836 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(66009),
24932 /* 65841 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24933 /* 65844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24934 /* 65847 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1884*/ GIMT_Encode4(66008),
24935 /* 65858 */ /*GILLT_s32*//*Label 1882*/ GIMT_Encode4(65866),
24936 /* 65862 */ /*GILLT_s64*//*Label 1883*/ GIMT_Encode4(65937),
24937 /* 65866 */ // Label 1882: @65866
24938 /* 65866 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(65936),
24939 /* 65871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24940 /* 65875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24941 /* 65879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1886*/ GIMT_Encode4(65907), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 884 //
24942 /* 65886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24943 /* 65890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24944 /* 65894 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24945 /* 65894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
24946 /* 65897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24947 /* 65899 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24948 /* 65901 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24949 /* 65903 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24950 /* 65905 */ GIR_RootConstrainSelectedInstOperands,
24951 /* 65906 */ // GIR_Coverage, 884,
24952 /* 65906 */ GIR_EraseRootFromParent_Done,
24953 /* 65907 */ // Label 1886: @65907
24954 /* 65907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1887*/ GIMT_Encode4(65935), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 886 //
24955 /* 65914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24956 /* 65918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24957 /* 65922 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24958 /* 65922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
24959 /* 65925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24960 /* 65927 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24961 /* 65929 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24962 /* 65931 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24963 /* 65933 */ GIR_RootConstrainSelectedInstOperands,
24964 /* 65934 */ // GIR_Coverage, 886,
24965 /* 65934 */ GIR_EraseRootFromParent_Done,
24966 /* 65935 */ // Label 1887: @65935
24967 /* 65935 */ GIM_Reject,
24968 /* 65936 */ // Label 1885: @65936
24969 /* 65936 */ GIM_Reject,
24970 /* 65937 */ // Label 1883: @65937
24971 /* 65937 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(66007),
24972 /* 65942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24973 /* 65946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24974 /* 65950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1889*/ GIMT_Encode4(65978), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 890 //
24975 /* 65957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24976 /* 65961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24977 /* 65965 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24978 /* 65965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
24979 /* 65968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24980 /* 65970 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24981 /* 65972 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24982 /* 65974 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24983 /* 65976 */ GIR_RootConstrainSelectedInstOperands,
24984 /* 65977 */ // GIR_Coverage, 890,
24985 /* 65977 */ GIR_EraseRootFromParent_Done,
24986 /* 65978 */ // Label 1889: @65978
24987 /* 65978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1890*/ GIMT_Encode4(66006), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 892 //
24988 /* 65985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24989 /* 65989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24990 /* 65993 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24991 /* 65993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
24992 /* 65996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24993 /* 65998 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24994 /* 66000 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24995 /* 66002 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24996 /* 66004 */ GIR_RootConstrainSelectedInstOperands,
24997 /* 66005 */ // GIR_Coverage, 892,
24998 /* 66005 */ GIR_EraseRootFromParent_Done,
24999 /* 66006 */ // Label 1890: @66006
25000 /* 66006 */ GIM_Reject,
25001 /* 66007 */ // Label 1888: @66007
25002 /* 66007 */ GIM_Reject,
25003 /* 66008 */ // Label 1884: @66008
25004 /* 66008 */ GIM_Reject,
25005 /* 66009 */ // Label 1881: @66009
25006 /* 66009 */ GIM_Reject,
25007 /* 66010 */ // Label 1858: @66010
25008 /* 66010 */ GIM_Reject,
25009 /* 66011 */ // Label 73: @66011
25010 /* 66011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1891*/ GIMT_Encode4(66061), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2245 //
25011 /* 66018 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25012 /* 66021 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25013 /* 66024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25014 /* 66027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25015 /* 66031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25016 /* 66035 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25017 /* 66039 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25018 /* 66043 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
25019 /* 66047 */ // MIs[1] Operand 1
25020 /* 66047 */ // No operand predicates
25021 /* 66047 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25022 /* 66049 */ // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
25023 /* 66049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
25024 /* 66052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25025 /* 66054 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
25026 /* 66056 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
25027 /* 66059 */ GIR_RootConstrainSelectedInstOperands,
25028 /* 66060 */ // GIR_Coverage, 2245,
25029 /* 66060 */ GIR_EraseRootFromParent_Done,
25030 /* 66061 */ // Label 1891: @66061
25031 /* 66061 */ GIM_Reject,
25032 /* 66062 */ // Label 74: @66062
25033 /* 66062 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1898*/ GIMT_Encode4(66552),
25034 /* 66073 */ /*GILLT_s32*//*Label 1892*/ GIMT_Encode4(66105),
25035 /* 66077 */ /*GILLT_s64*//*Label 1893*/ GIMT_Encode4(66306), GIMT_Encode4(0),
25036 /* 66085 */ /*GILLT_v16s8*//*Label 1894*/ GIMT_Encode4(66448), GIMT_Encode4(0),
25037 /* 66093 */ /*GILLT_v8s16*//*Label 1895*/ GIMT_Encode4(66474),
25038 /* 66097 */ /*GILLT_v4s32*//*Label 1896*/ GIMT_Encode4(66500),
25039 /* 66101 */ /*GILLT_v2s64*//*Label 1897*/ GIMT_Encode4(66526),
25040 /* 66105 */ // Label 1892: @66105
25041 /* 66105 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(66305),
25042 /* 66110 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25043 /* 66113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25044 /* 66117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1900*/ GIMT_Encode4(66162), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 129 //
25045 /* 66124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25046 /* 66128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25047 /* 66132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25048 /* 66136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25049 /* 66140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25050 /* 66145 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
25051 /* 66149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25052 /* 66151 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25053 /* 66151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
25054 /* 66154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25055 /* 66156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25056 /* 66160 */ GIR_RootConstrainSelectedInstOperands,
25057 /* 66161 */ // GIR_Coverage, 129,
25058 /* 66161 */ GIR_EraseRootFromParent_Done,
25059 /* 66162 */ // Label 1900: @66162
25060 /* 66162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1901*/ GIMT_Encode4(66207), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 385 //
25061 /* 66169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25062 /* 66173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25063 /* 66177 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25064 /* 66181 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25065 /* 66185 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25066 /* 66190 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
25067 /* 66194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25068 /* 66196 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25069 /* 66196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
25070 /* 66199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25071 /* 66201 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25072 /* 66205 */ GIR_RootConstrainSelectedInstOperands,
25073 /* 66206 */ // GIR_Coverage, 385,
25074 /* 66206 */ GIR_EraseRootFromParent_Done,
25075 /* 66207 */ // Label 1901: @66207
25076 /* 66207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1902*/ GIMT_Encode4(66252), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1180 //
25077 /* 66214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25078 /* 66218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25079 /* 66222 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25080 /* 66226 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25081 /* 66230 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25082 /* 66235 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
25083 /* 66239 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25084 /* 66241 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25085 /* 66241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
25086 /* 66244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25087 /* 66246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25088 /* 66250 */ GIR_RootConstrainSelectedInstOperands,
25089 /* 66251 */ // GIR_Coverage, 1180,
25090 /* 66251 */ GIR_EraseRootFromParent_Done,
25091 /* 66252 */ // Label 1902: @66252
25092 /* 66252 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(66304),
25093 /* 66257 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25094 /* 66261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1904*/ GIMT_Encode4(66275), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 128 //
25095 /* 66268 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25096 /* 66268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
25097 /* 66273 */ GIR_RootConstrainSelectedInstOperands,
25098 /* 66274 */ // GIR_Coverage, 128,
25099 /* 66274 */ GIR_Done,
25100 /* 66275 */ // Label 1904: @66275
25101 /* 66275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1905*/ GIMT_Encode4(66289), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 386 //
25102 /* 66282 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25103 /* 66282 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
25104 /* 66287 */ GIR_RootConstrainSelectedInstOperands,
25105 /* 66288 */ // GIR_Coverage, 386,
25106 /* 66288 */ GIR_Done,
25107 /* 66289 */ // Label 1905: @66289
25108 /* 66289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1906*/ GIMT_Encode4(66303), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1179 //
25109 /* 66296 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25110 /* 66296 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
25111 /* 66301 */ GIR_RootConstrainSelectedInstOperands,
25112 /* 66302 */ // GIR_Coverage, 1179,
25113 /* 66302 */ GIR_Done,
25114 /* 66303 */ // Label 1906: @66303
25115 /* 66303 */ GIM_Reject,
25116 /* 66304 */ // Label 1903: @66304
25117 /* 66304 */ GIM_Reject,
25118 /* 66305 */ // Label 1899: @66305
25119 /* 66305 */ GIM_Reject,
25120 /* 66306 */ // Label 1893: @66306
25121 /* 66306 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(66447),
25122 /* 66311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25123 /* 66314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25124 /* 66318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1908*/ GIMT_Encode4(66363), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 338 //
25125 /* 66325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25126 /* 66329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25127 /* 66333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25128 /* 66337 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25129 /* 66341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25130 /* 66346 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
25131 /* 66350 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25132 /* 66352 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25133 /* 66352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
25134 /* 66355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25135 /* 66357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25136 /* 66361 */ GIR_RootConstrainSelectedInstOperands,
25137 /* 66362 */ // GIR_Coverage, 338,
25138 /* 66362 */ GIR_EraseRootFromParent_Done,
25139 /* 66363 */ // Label 1908: @66363
25140 /* 66363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1909*/ GIMT_Encode4(66408), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 402 //
25141 /* 66370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25142 /* 66374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25143 /* 66378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25144 /* 66382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25145 /* 66386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25146 /* 66391 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
25147 /* 66395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25148 /* 66397 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25149 /* 66397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
25150 /* 66400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25151 /* 66402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25152 /* 66406 */ GIR_RootConstrainSelectedInstOperands,
25153 /* 66407 */ // GIR_Coverage, 402,
25154 /* 66407 */ GIR_EraseRootFromParent_Done,
25155 /* 66408 */ // Label 1909: @66408
25156 /* 66408 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(66446),
25157 /* 66413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25158 /* 66417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1911*/ GIMT_Encode4(66431), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 337 //
25159 /* 66424 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25160 /* 66424 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
25161 /* 66429 */ GIR_RootConstrainSelectedInstOperands,
25162 /* 66430 */ // GIR_Coverage, 337,
25163 /* 66430 */ GIR_Done,
25164 /* 66431 */ // Label 1911: @66431
25165 /* 66431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1912*/ GIMT_Encode4(66445), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 403 //
25166 /* 66438 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25167 /* 66438 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
25168 /* 66443 */ GIR_RootConstrainSelectedInstOperands,
25169 /* 66444 */ // GIR_Coverage, 403,
25170 /* 66444 */ GIR_Done,
25171 /* 66445 */ // Label 1912: @66445
25172 /* 66445 */ GIM_Reject,
25173 /* 66446 */ // Label 1910: @66446
25174 /* 66446 */ GIM_Reject,
25175 /* 66447 */ // Label 1907: @66447
25176 /* 66447 */ GIM_Reject,
25177 /* 66448 */ // Label 1894: @66448
25178 /* 66448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1913*/ GIMT_Encode4(66473), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 979 //
25179 /* 66455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25180 /* 66458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25181 /* 66462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25182 /* 66466 */ // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
25183 /* 66466 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
25184 /* 66471 */ GIR_RootConstrainSelectedInstOperands,
25185 /* 66472 */ // GIR_Coverage, 979,
25186 /* 66472 */ GIR_Done,
25187 /* 66473 */ // Label 1913: @66473
25188 /* 66473 */ GIM_Reject,
25189 /* 66474 */ // Label 1895: @66474
25190 /* 66474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1914*/ GIMT_Encode4(66499), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 980 //
25191 /* 66481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25192 /* 66484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25193 /* 66488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25194 /* 66492 */ // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
25195 /* 66492 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
25196 /* 66497 */ GIR_RootConstrainSelectedInstOperands,
25197 /* 66498 */ // GIR_Coverage, 980,
25198 /* 66498 */ GIR_Done,
25199 /* 66499 */ // Label 1914: @66499
25200 /* 66499 */ GIM_Reject,
25201 /* 66500 */ // Label 1896: @66500
25202 /* 66500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1915*/ GIMT_Encode4(66525), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 981 //
25203 /* 66507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25204 /* 66510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25205 /* 66514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25206 /* 66518 */ // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25207 /* 66518 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
25208 /* 66523 */ GIR_RootConstrainSelectedInstOperands,
25209 /* 66524 */ // GIR_Coverage, 981,
25210 /* 66524 */ GIR_Done,
25211 /* 66525 */ // Label 1915: @66525
25212 /* 66525 */ GIM_Reject,
25213 /* 66526 */ // Label 1897: @66526
25214 /* 66526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1916*/ GIMT_Encode4(66551), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 982 //
25215 /* 66533 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25216 /* 66536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25217 /* 66540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25218 /* 66544 */ // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25219 /* 66544 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
25220 /* 66549 */ GIR_RootConstrainSelectedInstOperands,
25221 /* 66550 */ // GIR_Coverage, 982,
25222 /* 66550 */ GIR_Done,
25223 /* 66551 */ // Label 1916: @66551
25224 /* 66551 */ GIM_Reject,
25225 /* 66552 */ // Label 1898: @66552
25226 /* 66552 */ GIM_Reject,
25227 /* 66553 */ // Label 75: @66553
25228 /* 66553 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1923*/ GIMT_Encode4(66752),
25229 /* 66564 */ /*GILLT_s32*//*Label 1917*/ GIMT_Encode4(66596),
25230 /* 66568 */ /*GILLT_s64*//*Label 1918*/ GIMT_Encode4(66622), GIMT_Encode4(0),
25231 /* 66576 */ /*GILLT_v16s8*//*Label 1919*/ GIMT_Encode4(66648), GIMT_Encode4(0),
25232 /* 66584 */ /*GILLT_v8s16*//*Label 1920*/ GIMT_Encode4(66674),
25233 /* 66588 */ /*GILLT_v4s32*//*Label 1921*/ GIMT_Encode4(66700),
25234 /* 66592 */ /*GILLT_v2s64*//*Label 1922*/ GIMT_Encode4(66726),
25235 /* 66596 */ // Label 1917: @66596
25236 /* 66596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1924*/ GIMT_Encode4(66621), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 353 //
25237 /* 66603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25238 /* 66606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25239 /* 66610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25240 /* 66614 */ // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25241 /* 66614 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
25242 /* 66619 */ GIR_RootConstrainSelectedInstOperands,
25243 /* 66620 */ // GIR_Coverage, 353,
25244 /* 66620 */ GIR_Done,
25245 /* 66621 */ // Label 1924: @66621
25246 /* 66621 */ GIM_Reject,
25247 /* 66622 */ // Label 1918: @66622
25248 /* 66622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1925*/ GIMT_Encode4(66647), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 354 //
25249 /* 66629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25250 /* 66632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25251 /* 66636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25252 /* 66640 */ // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25253 /* 66640 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
25254 /* 66645 */ GIR_RootConstrainSelectedInstOperands,
25255 /* 66646 */ // GIR_Coverage, 354,
25256 /* 66646 */ GIR_Done,
25257 /* 66647 */ // Label 1925: @66647
25258 /* 66647 */ GIM_Reject,
25259 /* 66648 */ // Label 1919: @66648
25260 /* 66648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1926*/ GIMT_Encode4(66673), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1001 //
25261 /* 66655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25262 /* 66658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25263 /* 66662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25264 /* 66666 */ // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
25265 /* 66666 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
25266 /* 66671 */ GIR_RootConstrainSelectedInstOperands,
25267 /* 66672 */ // GIR_Coverage, 1001,
25268 /* 66672 */ GIR_Done,
25269 /* 66673 */ // Label 1926: @66673
25270 /* 66673 */ GIM_Reject,
25271 /* 66674 */ // Label 1920: @66674
25272 /* 66674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1927*/ GIMT_Encode4(66699), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1002 //
25273 /* 66681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25274 /* 66684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25275 /* 66688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25276 /* 66692 */ // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
25277 /* 66692 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
25278 /* 66697 */ GIR_RootConstrainSelectedInstOperands,
25279 /* 66698 */ // GIR_Coverage, 1002,
25280 /* 66698 */ GIR_Done,
25281 /* 66699 */ // Label 1927: @66699
25282 /* 66699 */ GIM_Reject,
25283 /* 66700 */ // Label 1921: @66700
25284 /* 66700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1928*/ GIMT_Encode4(66725), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1003 //
25285 /* 66707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25286 /* 66710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25287 /* 66714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25288 /* 66718 */ // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25289 /* 66718 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
25290 /* 66723 */ GIR_RootConstrainSelectedInstOperands,
25291 /* 66724 */ // GIR_Coverage, 1003,
25292 /* 66724 */ GIR_Done,
25293 /* 66725 */ // Label 1928: @66725
25294 /* 66725 */ GIM_Reject,
25295 /* 66726 */ // Label 1922: @66726
25296 /* 66726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1929*/ GIMT_Encode4(66751), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1004 //
25297 /* 66733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25298 /* 66736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25299 /* 66740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25300 /* 66744 */ // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25301 /* 66744 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
25302 /* 66749 */ GIR_RootConstrainSelectedInstOperands,
25303 /* 66750 */ // GIR_Coverage, 1004,
25304 /* 66750 */ GIR_Done,
25305 /* 66751 */ // Label 1929: @66751
25306 /* 66751 */ GIM_Reject,
25307 /* 66752 */ // Label 1923: @66752
25308 /* 66752 */ GIM_Reject,
25309 /* 66753 */ // Label 76: @66753
25310 /* 66753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1932*/ GIMT_Encode4(66913),
25311 /* 66764 */ /*GILLT_s32*//*Label 1930*/ GIMT_Encode4(66772),
25312 /* 66768 */ /*GILLT_s64*//*Label 1931*/ GIMT_Encode4(66866),
25313 /* 66772 */ // Label 1930: @66772
25314 /* 66772 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(66865),
25315 /* 66777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25316 /* 66780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25317 /* 66784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25318 /* 66788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1934*/ GIMT_Encode4(66826), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 1512 //
25319 /* 66795 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25320 /* 66795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25321 /* 66798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
25322 /* 66802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25323 /* 66807 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25324 /* 66811 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25325 /* 66813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
25326 /* 66816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25327 /* 66818 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25328 /* 66821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25329 /* 66824 */ GIR_RootConstrainSelectedInstOperands,
25330 /* 66825 */ // GIR_Coverage, 1512,
25331 /* 66825 */ GIR_EraseRootFromParent_Done,
25332 /* 66826 */ // Label 1934: @66826
25333 /* 66826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1935*/ GIMT_Encode4(66864), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2459 //
25334 /* 66833 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25335 /* 66833 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25336 /* 66836 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
25337 /* 66840 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25338 /* 66845 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25339 /* 66849 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25340 /* 66851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
25341 /* 66854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25342 /* 66856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25343 /* 66859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25344 /* 66862 */ GIR_RootConstrainSelectedInstOperands,
25345 /* 66863 */ // GIR_Coverage, 2459,
25346 /* 66863 */ GIR_EraseRootFromParent_Done,
25347 /* 66864 */ // Label 1935: @66864
25348 /* 66864 */ GIM_Reject,
25349 /* 66865 */ // Label 1933: @66865
25350 /* 66865 */ GIM_Reject,
25351 /* 66866 */ // Label 1931: @66866
25352 /* 66866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(66912), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc), // Rule ID 1781 //
25353 /* 66873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25354 /* 66876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25355 /* 66880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25356 /* 66884 */ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
25357 /* 66884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25358 /* 66887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
25359 /* 66891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25360 /* 66896 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25361 /* 66900 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25362 /* 66902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
25363 /* 66905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25364 /* 66907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25365 /* 66910 */ GIR_RootConstrainSelectedInstOperands,
25366 /* 66911 */ // GIR_Coverage, 1781,
25367 /* 66911 */ GIR_EraseRootFromParent_Done,
25368 /* 66912 */ // Label 1936: @66912
25369 /* 66912 */ GIM_Reject,
25370 /* 66913 */ // Label 1932: @66913
25371 /* 66913 */ GIM_Reject,
25372 /* 66914 */ // Label 77: @66914
25373 /* 66914 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1941*/ GIMT_Encode4(67177),
25374 /* 66925 */ /*GILLT_s32*//*Label 1937*/ GIMT_Encode4(66957),
25375 /* 66929 */ /*GILLT_s64*//*Label 1938*/ GIMT_Encode4(67011), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25376 /* 66949 */ /*GILLT_v4s32*//*Label 1939*/ GIMT_Encode4(67125),
25377 /* 66953 */ /*GILLT_v2s64*//*Label 1940*/ GIMT_Encode4(67151),
25378 /* 66957 */ // Label 1937: @66957
25379 /* 66957 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(67010),
25380 /* 66962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25381 /* 66965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25382 /* 66969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25383 /* 66973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(66991), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 154 //
25384 /* 66980 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25385 /* 66980 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
25386 /* 66985 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25387 /* 66989 */ GIR_RootConstrainSelectedInstOperands,
25388 /* 66990 */ // GIR_Coverage, 154,
25389 /* 66990 */ GIR_Done,
25390 /* 66991 */ // Label 1943: @66991
25391 /* 66991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(67009), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1243 //
25392 /* 66998 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25393 /* 66998 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
25394 /* 67003 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25395 /* 67007 */ GIR_RootConstrainSelectedInstOperands,
25396 /* 67008 */ // GIR_Coverage, 1243,
25397 /* 67008 */ GIR_Done,
25398 /* 67009 */ // Label 1944: @67009
25399 /* 67009 */ GIM_Reject,
25400 /* 67010 */ // Label 1942: @67010
25401 /* 67010 */ GIM_Reject,
25402 /* 67011 */ // Label 1938: @67011
25403 /* 67011 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(67124),
25404 /* 67016 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25405 /* 67019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(67045), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 156 //
25406 /* 67026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25407 /* 67030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25408 /* 67034 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25409 /* 67034 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
25410 /* 67039 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25411 /* 67043 */ GIR_RootConstrainSelectedInstOperands,
25412 /* 67044 */ // GIR_Coverage, 156,
25413 /* 67044 */ GIR_Done,
25414 /* 67045 */ // Label 1946: @67045
25415 /* 67045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(67071), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 158 //
25416 /* 67052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25417 /* 67056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25418 /* 67060 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25419 /* 67060 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
25420 /* 67065 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25421 /* 67069 */ GIR_RootConstrainSelectedInstOperands,
25422 /* 67070 */ // GIR_Coverage, 158,
25423 /* 67070 */ GIR_Done,
25424 /* 67071 */ // Label 1947: @67071
25425 /* 67071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(67097), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1229 //
25426 /* 67078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25427 /* 67082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25428 /* 67086 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25429 /* 67086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
25430 /* 67091 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25431 /* 67095 */ GIR_RootConstrainSelectedInstOperands,
25432 /* 67096 */ // GIR_Coverage, 1229,
25433 /* 67096 */ GIR_Done,
25434 /* 67097 */ // Label 1948: @67097
25435 /* 67097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1949*/ GIMT_Encode4(67123), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1230 //
25436 /* 67104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25437 /* 67108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25438 /* 67112 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25439 /* 67112 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
25440 /* 67117 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25441 /* 67121 */ GIR_RootConstrainSelectedInstOperands,
25442 /* 67122 */ // GIR_Coverage, 1230,
25443 /* 67122 */ GIR_Done,
25444 /* 67123 */ // Label 1949: @67123
25445 /* 67123 */ GIM_Reject,
25446 /* 67124 */ // Label 1945: @67124
25447 /* 67124 */ GIM_Reject,
25448 /* 67125 */ // Label 1939: @67125
25449 /* 67125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(67150), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 819 //
25450 /* 67132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25451 /* 67135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25452 /* 67139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25453 /* 67143 */ // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25454 /* 67143 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
25455 /* 67148 */ GIR_RootConstrainSelectedInstOperands,
25456 /* 67149 */ // GIR_Coverage, 819,
25457 /* 67149 */ GIR_Done,
25458 /* 67150 */ // Label 1950: @67150
25459 /* 67150 */ GIM_Reject,
25460 /* 67151 */ // Label 1940: @67151
25461 /* 67151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(67176), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 820 //
25462 /* 67158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25463 /* 67161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25464 /* 67165 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25465 /* 67169 */ // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25466 /* 67169 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
25467 /* 67174 */ GIR_RootConstrainSelectedInstOperands,
25468 /* 67175 */ // GIR_Coverage, 820,
25469 /* 67175 */ GIR_Done,
25470 /* 67176 */ // Label 1951: @67176
25471 /* 67176 */ GIM_Reject,
25472 /* 67177 */ // Label 1941: @67177
25473 /* 67177 */ GIM_Reject,
25474 /* 67178 */ // Label 78: @67178
25475 /* 67178 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1956*/ GIMT_Encode4(67333),
25476 /* 67189 */ /*GILLT_s32*//*Label 1952*/ GIMT_Encode4(67221),
25477 /* 67193 */ /*GILLT_s64*//*Label 1953*/ GIMT_Encode4(67251), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25478 /* 67213 */ /*GILLT_v4s32*//*Label 1954*/ GIMT_Encode4(67281),
25479 /* 67217 */ /*GILLT_v2s64*//*Label 1955*/ GIMT_Encode4(67307),
25480 /* 67221 */ // Label 1952: @67221
25481 /* 67221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(67250), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 397 //
25482 /* 67228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25483 /* 67231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25484 /* 67235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25485 /* 67239 */ // (frint:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (RINT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25486 /* 67239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::RINT_S),
25487 /* 67244 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25488 /* 67248 */ GIR_RootConstrainSelectedInstOperands,
25489 /* 67249 */ // GIR_Coverage, 397,
25490 /* 67249 */ GIR_Done,
25491 /* 67250 */ // Label 1957: @67250
25492 /* 67250 */ GIM_Reject,
25493 /* 67251 */ // Label 1953: @67251
25494 /* 67251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(67280), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 395 //
25495 /* 67258 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25496 /* 67261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25497 /* 67265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25498 /* 67269 */ // (frint:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (RINT_D:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25499 /* 67269 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::RINT_D),
25500 /* 67274 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25501 /* 67278 */ GIR_RootConstrainSelectedInstOperands,
25502 /* 67279 */ // GIR_Coverage, 395,
25503 /* 67279 */ GIR_Done,
25504 /* 67280 */ // Label 1958: @67280
25505 /* 67280 */ GIM_Reject,
25506 /* 67281 */ // Label 1954: @67281
25507 /* 67281 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(67306), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 801 //
25508 /* 67288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25509 /* 67291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25510 /* 67295 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25511 /* 67299 */ // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25512 /* 67299 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
25513 /* 67304 */ GIR_RootConstrainSelectedInstOperands,
25514 /* 67305 */ // GIR_Coverage, 801,
25515 /* 67305 */ GIR_Done,
25516 /* 67306 */ // Label 1959: @67306
25517 /* 67306 */ GIM_Reject,
25518 /* 67307 */ // Label 1955: @67307
25519 /* 67307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1960*/ GIMT_Encode4(67332), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 802 //
25520 /* 67314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25521 /* 67317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25522 /* 67321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25523 /* 67325 */ // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25524 /* 67325 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
25525 /* 67330 */ GIR_RootConstrainSelectedInstOperands,
25526 /* 67331 */ // GIR_Coverage, 802,
25527 /* 67331 */ GIR_Done,
25528 /* 67332 */ // Label 1960: @67332
25529 /* 67332 */ GIM_Reject,
25530 /* 67333 */ // Label 1956: @67333
25531 /* 67333 */ GIM_Reject,
25532 /* 67334 */ // Label 79: @67334
25533 /* 67334 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1963*/ GIMT_Encode4(68173),
25534 /* 67345 */ /*GILLT_s32*//*Label 1961*/ GIMT_Encode4(67353),
25535 /* 67349 */ /*GILLT_s64*//*Label 1962*/ GIMT_Encode4(67620),
25536 /* 67353 */ // Label 1961: @67353
25537 /* 67353 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(67619),
25538 /* 67358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25539 /* 67361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25540 /* 67364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25541 /* 67368 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(67482),
25542 /* 67373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25543 /* 67377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(67429), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 206 //
25544 /* 67384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25545 /* 67388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25546 /* 67392 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25547 /* 67396 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25548 /* 67400 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25549 /* 67405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25550 /* 67410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25551 /* 67412 */ // (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25552 /* 67412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25553 /* 67415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25554 /* 67417 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25555 /* 67419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25556 /* 67423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25557 /* 67427 */ GIR_RootConstrainSelectedInstOperands,
25558 /* 67428 */ // GIR_Coverage, 206,
25559 /* 67428 */ GIR_EraseRootFromParent_Done,
25560 /* 67429 */ // Label 1966: @67429
25561 /* 67429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(67481), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 205 //
25562 /* 67436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25563 /* 67440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25564 /* 67444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25565 /* 67448 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25566 /* 67452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25567 /* 67457 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25568 /* 67462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25569 /* 67464 */ // (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25570 /* 67464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25571 /* 67467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25572 /* 67469 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25573 /* 67471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25574 /* 67475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25575 /* 67479 */ GIR_RootConstrainSelectedInstOperands,
25576 /* 67480 */ // GIR_Coverage, 205,
25577 /* 67480 */ GIR_EraseRootFromParent_Done,
25578 /* 67481 */ // Label 1967: @67481
25579 /* 67481 */ GIM_Reject,
25580 /* 67482 */ // Label 1965: @67482
25581 /* 67482 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(67618),
25582 /* 67487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25583 /* 67491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(67543), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2658 //
25584 /* 67498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25585 /* 67502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25586 /* 67506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25587 /* 67510 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25588 /* 67514 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25589 /* 67519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25590 /* 67524 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25591 /* 67526 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25592 /* 67526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25593 /* 67529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25594 /* 67531 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25595 /* 67533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25596 /* 67537 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25597 /* 67541 */ GIR_RootConstrainSelectedInstOperands,
25598 /* 67542 */ // GIR_Coverage, 2658,
25599 /* 67542 */ GIR_EraseRootFromParent_Done,
25600 /* 67543 */ // Label 1969: @67543
25601 /* 67543 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(67595), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2657 //
25602 /* 67550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25603 /* 67554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25604 /* 67558 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25605 /* 67562 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25606 /* 67566 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25607 /* 67571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25608 /* 67576 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25609 /* 67578 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25610 /* 67578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25611 /* 67581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25612 /* 67583 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25613 /* 67585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25614 /* 67589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25615 /* 67593 */ GIR_RootConstrainSelectedInstOperands,
25616 /* 67594 */ // GIR_Coverage, 2657,
25617 /* 67594 */ GIR_EraseRootFromParent_Done,
25618 /* 67595 */ // Label 1970: @67595
25619 /* 67595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(67617), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 181 //
25620 /* 67602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25621 /* 67606 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25622 /* 67606 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
25623 /* 67611 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25624 /* 67615 */ GIR_RootConstrainSelectedInstOperands,
25625 /* 67616 */ // GIR_Coverage, 181,
25626 /* 67616 */ GIR_Done,
25627 /* 67617 */ // Label 1971: @67617
25628 /* 67617 */ GIM_Reject,
25629 /* 67618 */ // Label 1968: @67618
25630 /* 67618 */ GIM_Reject,
25631 /* 67619 */ // Label 1964: @67619
25632 /* 67619 */ GIM_Reject,
25633 /* 67620 */ // Label 1962: @67620
25634 /* 67620 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(68172),
25635 /* 67625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25636 /* 67628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25637 /* 67631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(67691), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 214 //
25638 /* 67638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25639 /* 67642 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25640 /* 67646 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25641 /* 67650 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25642 /* 67654 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25643 /* 67658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25644 /* 67663 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25645 /* 67668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25646 /* 67672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25647 /* 67674 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25648 /* 67674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25649 /* 67677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25650 /* 67679 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25651 /* 67681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25652 /* 67685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25653 /* 67689 */ GIR_RootConstrainSelectedInstOperands,
25654 /* 67690 */ // GIR_Coverage, 214,
25655 /* 67690 */ GIR_EraseRootFromParent_Done,
25656 /* 67691 */ // Label 1973: @67691
25657 /* 67691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1974*/ GIMT_Encode4(67751), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 222 //
25658 /* 67698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25659 /* 67702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25660 /* 67706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25661 /* 67710 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25662 /* 67714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25663 /* 67718 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25664 /* 67723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25665 /* 67728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25666 /* 67732 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25667 /* 67734 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25668 /* 67734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25669 /* 67737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25670 /* 67739 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25671 /* 67741 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25672 /* 67745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25673 /* 67749 */ GIR_RootConstrainSelectedInstOperands,
25674 /* 67750 */ // GIR_Coverage, 222,
25675 /* 67750 */ GIR_EraseRootFromParent_Done,
25676 /* 67751 */ // Label 1974: @67751
25677 /* 67751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1975*/ GIMT_Encode4(67811), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 213 //
25678 /* 67758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25679 /* 67762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25680 /* 67766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25681 /* 67770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25682 /* 67774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25683 /* 67778 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25684 /* 67783 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25685 /* 67788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25686 /* 67792 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25687 /* 67794 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25688 /* 67794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25689 /* 67797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25690 /* 67799 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25691 /* 67801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25692 /* 67805 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25693 /* 67809 */ GIR_RootConstrainSelectedInstOperands,
25694 /* 67810 */ // GIR_Coverage, 213,
25695 /* 67810 */ GIR_EraseRootFromParent_Done,
25696 /* 67811 */ // Label 1975: @67811
25697 /* 67811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1976*/ GIMT_Encode4(67871), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 221 //
25698 /* 67818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25699 /* 67822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25700 /* 67826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25701 /* 67830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25702 /* 67834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25703 /* 67838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25704 /* 67843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25705 /* 67848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25706 /* 67852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25707 /* 67854 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25708 /* 67854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25709 /* 67857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25710 /* 67859 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25711 /* 67861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25712 /* 67865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25713 /* 67869 */ GIR_RootConstrainSelectedInstOperands,
25714 /* 67870 */ // GIR_Coverage, 221,
25715 /* 67870 */ GIR_EraseRootFromParent_Done,
25716 /* 67871 */ // Label 1976: @67871
25717 /* 67871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1977*/ GIMT_Encode4(67931), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2662 //
25718 /* 67878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25719 /* 67882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25720 /* 67886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25721 /* 67890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25722 /* 67894 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25723 /* 67898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25724 /* 67902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25725 /* 67907 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25726 /* 67912 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25727 /* 67914 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25728 /* 67914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25729 /* 67917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25730 /* 67919 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25731 /* 67921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25732 /* 67925 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25733 /* 67929 */ GIR_RootConstrainSelectedInstOperands,
25734 /* 67930 */ // GIR_Coverage, 2662,
25735 /* 67930 */ GIR_EraseRootFromParent_Done,
25736 /* 67931 */ // Label 1977: @67931
25737 /* 67931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(67991), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2666 //
25738 /* 67938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25739 /* 67942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25740 /* 67946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25741 /* 67950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25742 /* 67954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25743 /* 67958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25744 /* 67962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25745 /* 67967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25746 /* 67972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25747 /* 67974 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25748 /* 67974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25749 /* 67977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25750 /* 67979 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25751 /* 67981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25752 /* 67985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25753 /* 67989 */ GIR_RootConstrainSelectedInstOperands,
25754 /* 67990 */ // GIR_Coverage, 2666,
25755 /* 67990 */ GIR_EraseRootFromParent_Done,
25756 /* 67991 */ // Label 1978: @67991
25757 /* 67991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1979*/ GIMT_Encode4(68051), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2661 //
25758 /* 67998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25759 /* 68002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25760 /* 68006 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25761 /* 68010 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25762 /* 68014 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25763 /* 68018 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25764 /* 68022 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25765 /* 68027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25766 /* 68032 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25767 /* 68034 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25768 /* 68034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25769 /* 68037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25770 /* 68039 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25771 /* 68041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25772 /* 68045 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25773 /* 68049 */ GIR_RootConstrainSelectedInstOperands,
25774 /* 68050 */ // GIR_Coverage, 2661,
25775 /* 68050 */ GIR_EraseRootFromParent_Done,
25776 /* 68051 */ // Label 1979: @68051
25777 /* 68051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1980*/ GIMT_Encode4(68111), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2665 //
25778 /* 68058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25779 /* 68062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25780 /* 68066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25781 /* 68070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25782 /* 68074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25783 /* 68078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25784 /* 68082 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25785 /* 68087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25786 /* 68092 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25787 /* 68094 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25788 /* 68094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25789 /* 68097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25790 /* 68099 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25791 /* 68101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25792 /* 68105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25793 /* 68109 */ GIR_RootConstrainSelectedInstOperands,
25794 /* 68110 */ // GIR_Coverage, 2665,
25795 /* 68110 */ GIR_EraseRootFromParent_Done,
25796 /* 68111 */ // Label 1980: @68111
25797 /* 68111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1981*/ GIMT_Encode4(68141), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 183 //
25798 /* 68118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25799 /* 68122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25800 /* 68126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25801 /* 68130 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25802 /* 68130 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
25803 /* 68135 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25804 /* 68139 */ GIR_RootConstrainSelectedInstOperands,
25805 /* 68140 */ // GIR_Coverage, 183,
25806 /* 68140 */ GIR_Done,
25807 /* 68141 */ // Label 1981: @68141
25808 /* 68141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1982*/ GIMT_Encode4(68171), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 185 //
25809 /* 68148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25810 /* 68152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25811 /* 68156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25812 /* 68160 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25813 /* 68160 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
25814 /* 68165 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25815 /* 68169 */ GIR_RootConstrainSelectedInstOperands,
25816 /* 68170 */ // GIR_Coverage, 185,
25817 /* 68170 */ GIR_Done,
25818 /* 68171 */ // Label 1982: @68171
25819 /* 68171 */ GIM_Reject,
25820 /* 68172 */ // Label 1972: @68172
25821 /* 68172 */ GIM_Reject,
25822 /* 68173 */ // Label 1963: @68173
25823 /* 68173 */ GIM_Reject,
25824 /* 68174 */ // Label 80: @68174
25825 /* 68174 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1985*/ GIMT_Encode4(68663),
25826 /* 68185 */ /*GILLT_s32*//*Label 1983*/ GIMT_Encode4(68193),
25827 /* 68189 */ /*GILLT_s64*//*Label 1984*/ GIMT_Encode4(68350),
25828 /* 68193 */ // Label 1983: @68193
25829 /* 68193 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(68349),
25830 /* 68198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25831 /* 68201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25832 /* 68204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25833 /* 68208 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(68322),
25834 /* 68213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25835 /* 68217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1988*/ GIMT_Encode4(68269), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 210 //
25836 /* 68224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25837 /* 68228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25838 /* 68232 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25839 /* 68236 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25840 /* 68240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25841 /* 68245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25842 /* 68250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25843 /* 68252 */ // (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25844 /* 68252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
25845 /* 68255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25846 /* 68257 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25847 /* 68259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25848 /* 68263 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25849 /* 68267 */ GIR_RootConstrainSelectedInstOperands,
25850 /* 68268 */ // GIR_Coverage, 210,
25851 /* 68268 */ GIR_EraseRootFromParent_Done,
25852 /* 68269 */ // Label 1988: @68269
25853 /* 68269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1989*/ GIMT_Encode4(68321), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 209 //
25854 /* 68276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25855 /* 68280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25856 /* 68284 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25857 /* 68288 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25858 /* 68292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25859 /* 68297 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25860 /* 68302 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25861 /* 68304 */ // (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25862 /* 68304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
25863 /* 68307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25864 /* 68309 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25865 /* 68311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25866 /* 68315 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25867 /* 68319 */ GIR_RootConstrainSelectedInstOperands,
25868 /* 68320 */ // GIR_Coverage, 209,
25869 /* 68320 */ GIR_EraseRootFromParent_Done,
25870 /* 68321 */ // Label 1989: @68321
25871 /* 68321 */ GIM_Reject,
25872 /* 68322 */ // Label 1987: @68322
25873 /* 68322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1990*/ GIMT_Encode4(68348), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 199 //
25874 /* 68329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25875 /* 68333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25876 /* 68337 */ // (strict_fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25877 /* 68337 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
25878 /* 68342 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25879 /* 68346 */ GIR_RootConstrainSelectedInstOperands,
25880 /* 68347 */ // GIR_Coverage, 199,
25881 /* 68347 */ GIR_Done,
25882 /* 68348 */ // Label 1990: @68348
25883 /* 68348 */ GIM_Reject,
25884 /* 68349 */ // Label 1986: @68349
25885 /* 68349 */ GIM_Reject,
25886 /* 68350 */ // Label 1984: @68350
25887 /* 68350 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(68662),
25888 /* 68355 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25889 /* 68358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25890 /* 68361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1992*/ GIMT_Encode4(68421), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 218 //
25891 /* 68368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25892 /* 68372 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25893 /* 68376 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25894 /* 68380 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25895 /* 68384 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25896 /* 68388 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25897 /* 68393 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25898 /* 68398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25899 /* 68402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25900 /* 68404 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25901 /* 68404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
25902 /* 68407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25903 /* 68409 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25904 /* 68411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25905 /* 68415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25906 /* 68419 */ GIR_RootConstrainSelectedInstOperands,
25907 /* 68420 */ // GIR_Coverage, 218,
25908 /* 68420 */ GIR_EraseRootFromParent_Done,
25909 /* 68421 */ // Label 1992: @68421
25910 /* 68421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1993*/ GIMT_Encode4(68481), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 226 //
25911 /* 68428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25912 /* 68432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25913 /* 68436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25914 /* 68440 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25915 /* 68444 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25916 /* 68448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25917 /* 68453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25918 /* 68458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25919 /* 68462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25920 /* 68464 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25921 /* 68464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
25922 /* 68467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25923 /* 68469 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25924 /* 68471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25925 /* 68475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25926 /* 68479 */ GIR_RootConstrainSelectedInstOperands,
25927 /* 68480 */ // GIR_Coverage, 226,
25928 /* 68480 */ GIR_EraseRootFromParent_Done,
25929 /* 68481 */ // Label 1993: @68481
25930 /* 68481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1994*/ GIMT_Encode4(68541), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 217 //
25931 /* 68488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25932 /* 68492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25933 /* 68496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25934 /* 68500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25935 /* 68504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25936 /* 68508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25937 /* 68513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25938 /* 68518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25939 /* 68522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25940 /* 68524 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25941 /* 68524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
25942 /* 68527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25943 /* 68529 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25944 /* 68531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25945 /* 68535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25946 /* 68539 */ GIR_RootConstrainSelectedInstOperands,
25947 /* 68540 */ // GIR_Coverage, 217,
25948 /* 68540 */ GIR_EraseRootFromParent_Done,
25949 /* 68541 */ // Label 1994: @68541
25950 /* 68541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1995*/ GIMT_Encode4(68601), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 225 //
25951 /* 68548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25952 /* 68552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25953 /* 68556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25954 /* 68560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25955 /* 68564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25956 /* 68568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25957 /* 68573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25958 /* 68578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25959 /* 68582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25960 /* 68584 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25961 /* 68584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
25962 /* 68587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25963 /* 68589 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25964 /* 68591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25965 /* 68595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25966 /* 68599 */ GIR_RootConstrainSelectedInstOperands,
25967 /* 68600 */ // GIR_Coverage, 225,
25968 /* 68600 */ GIR_EraseRootFromParent_Done,
25969 /* 68601 */ // Label 1995: @68601
25970 /* 68601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(68631), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 201 //
25971 /* 68608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25972 /* 68612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25973 /* 68616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25974 /* 68620 */ // (strict_fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25975 /* 68620 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
25976 /* 68625 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25977 /* 68629 */ GIR_RootConstrainSelectedInstOperands,
25978 /* 68630 */ // GIR_Coverage, 201,
25979 /* 68630 */ GIR_Done,
25980 /* 68631 */ // Label 1996: @68631
25981 /* 68631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1997*/ GIMT_Encode4(68661), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 203 //
25982 /* 68638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25983 /* 68642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25984 /* 68646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25985 /* 68650 */ // (strict_fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25986 /* 68650 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
25987 /* 68655 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25988 /* 68659 */ GIR_RootConstrainSelectedInstOperands,
25989 /* 68660 */ // GIR_Coverage, 203,
25990 /* 68660 */ GIR_Done,
25991 /* 68661 */ // Label 1997: @68661
25992 /* 68661 */ GIM_Reject,
25993 /* 68662 */ // Label 1991: @68662
25994 /* 68662 */ GIM_Reject,
25995 /* 68663 */ // Label 1985: @68663
25996 /* 68663 */ GIM_Reject,
25997 /* 68664 */ // Label 81: @68664
25998 /* 68664 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2000*/ GIMT_Encode4(68793),
25999 /* 68675 */ /*GILLT_s32*//*Label 1998*/ GIMT_Encode4(68683),
26000 /* 68679 */ /*GILLT_s64*//*Label 1999*/ GIMT_Encode4(68720),
26001 /* 68683 */ // Label 1998: @68683
26002 /* 68683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2001*/ GIMT_Encode4(68719), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 193 //
26003 /* 68690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26004 /* 68693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26005 /* 68696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26006 /* 68700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26007 /* 68704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26008 /* 68708 */ // (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
26009 /* 68708 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
26010 /* 68713 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26011 /* 68717 */ GIR_RootConstrainSelectedInstOperands,
26012 /* 68718 */ // GIR_Coverage, 193,
26013 /* 68718 */ GIR_Done,
26014 /* 68719 */ // Label 2001: @68719
26015 /* 68719 */ GIM_Reject,
26016 /* 68720 */ // Label 1999: @68720
26017 /* 68720 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(68792),
26018 /* 68725 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26019 /* 68728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26020 /* 68731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2003*/ GIMT_Encode4(68761), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 195 //
26021 /* 68738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26022 /* 68742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26023 /* 68746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26024 /* 68750 */ // (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
26025 /* 68750 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
26026 /* 68755 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26027 /* 68759 */ GIR_RootConstrainSelectedInstOperands,
26028 /* 68760 */ // GIR_Coverage, 195,
26029 /* 68760 */ GIR_Done,
26030 /* 68761 */ // Label 2003: @68761
26031 /* 68761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2004*/ GIMT_Encode4(68791), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 197 //
26032 /* 68768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26033 /* 68772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26034 /* 68776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26035 /* 68780 */ // (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
26036 /* 68780 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
26037 /* 68785 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26038 /* 68789 */ GIR_RootConstrainSelectedInstOperands,
26039 /* 68790 */ // GIR_Coverage, 197,
26040 /* 68790 */ GIR_Done,
26041 /* 68791 */ // Label 2004: @68791
26042 /* 68791 */ GIM_Reject,
26043 /* 68792 */ // Label 2002: @68792
26044 /* 68792 */ GIM_Reject,
26045 /* 68793 */ // Label 2000: @68793
26046 /* 68793 */ GIM_Reject,
26047 /* 68794 */ // Label 82: @68794
26048 /* 68794 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2007*/ GIMT_Encode4(68923),
26049 /* 68805 */ /*GILLT_s32*//*Label 2005*/ GIMT_Encode4(68813),
26050 /* 68809 */ /*GILLT_s64*//*Label 2006*/ GIMT_Encode4(68850),
26051 /* 68813 */ // Label 2005: @68813
26052 /* 68813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2008*/ GIMT_Encode4(68849), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 187 //
26053 /* 68820 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26054 /* 68823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26055 /* 68826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26056 /* 68830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26057 /* 68834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26058 /* 68838 */ // (strict_fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
26059 /* 68838 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
26060 /* 68843 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26061 /* 68847 */ GIR_RootConstrainSelectedInstOperands,
26062 /* 68848 */ // GIR_Coverage, 187,
26063 /* 68848 */ GIR_Done,
26064 /* 68849 */ // Label 2008: @68849
26065 /* 68849 */ GIM_Reject,
26066 /* 68850 */ // Label 2006: @68850
26067 /* 68850 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(68922),
26068 /* 68855 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26069 /* 68858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26070 /* 68861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2010*/ GIMT_Encode4(68891), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 189 //
26071 /* 68868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26072 /* 68872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26073 /* 68876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26074 /* 68880 */ // (strict_fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
26075 /* 68880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
26076 /* 68885 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26077 /* 68889 */ GIR_RootConstrainSelectedInstOperands,
26078 /* 68890 */ // GIR_Coverage, 189,
26079 /* 68890 */ GIR_Done,
26080 /* 68891 */ // Label 2010: @68891
26081 /* 68891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2011*/ GIMT_Encode4(68921), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 191 //
26082 /* 68898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26083 /* 68902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26084 /* 68906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26085 /* 68910 */ // (strict_fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
26086 /* 68910 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
26087 /* 68915 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26088 /* 68919 */ GIR_RootConstrainSelectedInstOperands,
26089 /* 68920 */ // GIR_Coverage, 191,
26090 /* 68920 */ GIR_Done,
26091 /* 68921 */ // Label 2011: @68921
26092 /* 68921 */ GIM_Reject,
26093 /* 68922 */ // Label 2009: @68922
26094 /* 68922 */ GIM_Reject,
26095 /* 68923 */ // Label 2007: @68923
26096 /* 68923 */ GIM_Reject,
26097 /* 68924 */ // Label 83: @68924
26098 /* 68924 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 2014*/ GIMT_Encode4(69035),
26099 /* 68935 */ /*GILLT_s32*//*Label 2012*/ GIMT_Encode4(68943),
26100 /* 68939 */ /*GILLT_s64*//*Label 2013*/ GIMT_Encode4(68973),
26101 /* 68943 */ // Label 2012: @68943
26102 /* 68943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2015*/ GIMT_Encode4(68972), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 153 //
26103 /* 68950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26104 /* 68953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26105 /* 68957 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26106 /* 68961 */ // (strict_fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
26107 /* 68961 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
26108 /* 68966 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26109 /* 68970 */ GIR_RootConstrainSelectedInstOperands,
26110 /* 68971 */ // GIR_Coverage, 153,
26111 /* 68971 */ GIR_Done,
26112 /* 68972 */ // Label 2015: @68972
26113 /* 68972 */ GIM_Reject,
26114 /* 68973 */ // Label 2013: @68973
26115 /* 68973 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(69034),
26116 /* 68978 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26117 /* 68981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2017*/ GIMT_Encode4(69007), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 155 //
26118 /* 68988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26119 /* 68992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26120 /* 68996 */ // (strict_fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
26121 /* 68996 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
26122 /* 69001 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26123 /* 69005 */ GIR_RootConstrainSelectedInstOperands,
26124 /* 69006 */ // GIR_Coverage, 155,
26125 /* 69006 */ GIR_Done,
26126 /* 69007 */ // Label 2017: @69007
26127 /* 69007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2018*/ GIMT_Encode4(69033), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 157 //
26128 /* 69014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26129 /* 69018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26130 /* 69022 */ // (strict_fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
26131 /* 69022 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
26132 /* 69027 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
26133 /* 69031 */ GIR_RootConstrainSelectedInstOperands,
26134 /* 69032 */ // GIR_Coverage, 157,
26135 /* 69032 */ GIR_Done,
26136 /* 69033 */ // Label 2018: @69033
26137 /* 69033 */ GIM_Reject,
26138 /* 69034 */ // Label 2016: @69034
26139 /* 69034 */ GIM_Reject,
26140 /* 69035 */ // Label 2014: @69035
26141 /* 69035 */ GIM_Reject,
26142 /* 69036 */ // Label 84: @69036
26143 /* 69036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2019*/ GIMT_Encode4(69050), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 110 //
26144 /* 69043 */ // (trap) => (TRAP)
26145 /* 69043 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
26146 /* 69048 */ GIR_RootConstrainSelectedInstOperands,
26147 /* 69049 */ // GIR_Coverage, 110,
26148 /* 69049 */ GIR_Done,
26149 /* 69050 */ // Label 2019: @69050
26150 /* 69050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2020*/ GIMT_Encode4(69064), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1195 //
26151 /* 69057 */ // (trap) => (TRAP_MM)
26152 /* 69057 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
26153 /* 69062 */ GIR_RootConstrainSelectedInstOperands,
26154 /* 69063 */ // GIR_Coverage, 1195,
26155 /* 69063 */ GIR_Done,
26156 /* 69064 */ // Label 2020: @69064
26157 /* 69064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2021*/ GIMT_Encode4(69078), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2157 //
26158 /* 69071 */ // (trap) => (Break16)
26159 /* 69071 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
26160 /* 69076 */ GIR_RootConstrainSelectedInstOperands,
26161 /* 69077 */ // GIR_Coverage, 2157,
26162 /* 69077 */ GIR_Done,
26163 /* 69078 */ // Label 2021: @69078
26164 /* 69078 */ GIM_Reject,
26165 /* 69079 */ // Label 85: @69079
26166 /* 69079 */ GIM_Reject,
26167 /* 69080 */ }; // Size: 69080 bytes
26168 return MatchTable0;
26169}
26170#undef GIMT_Encode2
26171#undef GIMT_Encode4
26172#undef GIMT_Encode8
26173
26174
26175#endif // GET_GLOBALISEL_IMPL
26176
26177#ifdef GET_GLOBALISEL_PREDICATES_DECL
26178
26179PredicateBitset AvailableModuleFeatures;
26180mutable PredicateBitset AvailableFunctionFeatures;
26181PredicateBitset getAvailableFeatures() const {
26182 return AvailableModuleFeatures | AvailableFunctionFeatures;
26183}
26184PredicateBitset
26185computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
26186PredicateBitset
26187computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
26188 const MachineFunction *MF) const;
26189void setupGeneratedPerFunctionState(MachineFunction &MF) override;
26190
26191#endif // GET_GLOBALISEL_PREDICATES_DECL
26192
26193#ifdef GET_GLOBALISEL_PREDICATES_INIT
26194
26195AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
26196AvailableFunctionFeatures()
26197
26198#endif // GET_GLOBALISEL_PREDICATES_INIT
26199
26200