1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 45;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s16,
47 GILLT_s32,
48 GILLT_s64,
49 GILLT_v4s8,
50 GILLT_v16s8,
51 GILLT_v2s16,
52 GILLT_v8s16,
53 GILLT_v4s32,
54 GILLT_v2s64,
55};
56const static size_t NumTypeObjects = 9;
57const static LLT TypeObjects[] = {
58 LLT::scalar(16),
59 LLT::scalar(32),
60 LLT::scalar(64),
61 LLT::vector(ElementCount::getFixed(4), LLT::scalar(8)),
62 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
63 LLT::vector(ElementCount::getFixed(2), LLT::scalar(16)),
64 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
65 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
66 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
67};
68
69// Bits for subtarget features that participate in instruction matching.
70enum SubtargetFeatureBits : uint8_t {
71 Feature_IsPTR64bitBit = 23,
72 Feature_UseCompactBranchesBit = 41,
73 Feature_HasMips2Bit = 7,
74 Feature_HasMips3Bit = 18,
75 Feature_HasMips4_32Bit = 26,
76 Feature_NotMips4_32Bit = 27,
77 Feature_HasMips4_32r2Bit = 19,
78 Feature_HasMips32Bit = 3,
79 Feature_HasMips32r2Bit = 6,
80 Feature_HasMips32r6Bit = 28,
81 Feature_NotMips32r6Bit = 4,
82 Feature_IsGP64bitBit = 21,
83 Feature_HasMips64Bit = 24,
84 Feature_HasMips64r2Bit = 22,
85 Feature_HasMips64r6Bit = 29,
86 Feature_NotMips64r6Bit = 5,
87 Feature_InMips16ModeBit = 30,
88 Feature_NotInMips16ModeBit = 0,
89 Feature_HasCnMipsBit = 25,
90 Feature_NotCnMipsBit = 8,
91 Feature_IsSym32Bit = 38,
92 Feature_IsSym64Bit = 39,
93 Feature_IsN64Bit = 40,
94 Feature_RelocNotPICBit = 10,
95 Feature_RelocPICBit = 36,
96 Feature_HasStdEncBit = 1,
97 Feature_NotDSPBit = 12,
98 Feature_InMicroMipsBit = 34,
99 Feature_NotInMicroMipsBit = 2,
100 Feature_IsLEBit = 43,
101 Feature_IsBEBit = 44,
102 Feature_HasEVABit = 35,
103 Feature_HasMSABit = 33,
104 Feature_HasMadd4Bit = 20,
105 Feature_UseIndirectJumpsHazardBit = 13,
106 Feature_NoIndirectJumpGuardsBit = 11,
107 Feature_IsR5900Bit = 37,
108 Feature_NotR5900Bit = 9,
109 Feature_AllowFPOpFusionBit = 42,
110 Feature_IsFP64bitBit = 17,
111 Feature_NotFP64bitBit = 16,
112 Feature_IsNotSingleFloatBit = 15,
113 Feature_IsNotSoftFloatBit = 14,
114 Feature_HasDSPBit = 31,
115 Feature_HasDSPR2Bit = 32,
116};
117
118PredicateBitset MipsInstructionSelector::
119computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
120 PredicateBitset Features{};
121 if (Subtarget->isABI_N64())
122 Features.set(Feature_IsPTR64bitBit);
123 if (Subtarget->useCompactBranches())
124 Features.set(Feature_UseCompactBranchesBit);
125 if (Subtarget->hasMips2())
126 Features.set(Feature_HasMips2Bit);
127 if (Subtarget->hasMips3())
128 Features.set(Feature_HasMips3Bit);
129 if (Subtarget->hasMips4_32())
130 Features.set(Feature_HasMips4_32Bit);
131 if (!Subtarget->hasMips4_32())
132 Features.set(Feature_NotMips4_32Bit);
133 if (Subtarget->hasMips4_32r2())
134 Features.set(Feature_HasMips4_32r2Bit);
135 if (Subtarget->hasMips32())
136 Features.set(Feature_HasMips32Bit);
137 if (Subtarget->hasMips32r2())
138 Features.set(Feature_HasMips32r2Bit);
139 if (Subtarget->hasMips32r6())
140 Features.set(Feature_HasMips32r6Bit);
141 if (!Subtarget->hasMips32r6())
142 Features.set(Feature_NotMips32r6Bit);
143 if (Subtarget->isGP64bit())
144 Features.set(Feature_IsGP64bitBit);
145 if (Subtarget->hasMips64())
146 Features.set(Feature_HasMips64Bit);
147 if (Subtarget->hasMips64r2())
148 Features.set(Feature_HasMips64r2Bit);
149 if (Subtarget->hasMips64r6())
150 Features.set(Feature_HasMips64r6Bit);
151 if (!Subtarget->hasMips64r6())
152 Features.set(Feature_NotMips64r6Bit);
153 if (Subtarget->inMips16Mode())
154 Features.set(Feature_InMips16ModeBit);
155 if (!Subtarget->inMips16Mode())
156 Features.set(Feature_NotInMips16ModeBit);
157 if (Subtarget->hasCnMips())
158 Features.set(Feature_HasCnMipsBit);
159 if (!Subtarget->hasCnMips())
160 Features.set(Feature_NotCnMipsBit);
161 if (Subtarget->hasSym32())
162 Features.set(Feature_IsSym32Bit);
163 if (!Subtarget->hasSym32())
164 Features.set(Feature_IsSym64Bit);
165 if (Subtarget->isABI_N64())
166 Features.set(Feature_IsN64Bit);
167 if (!TM.isPositionIndependent())
168 Features.set(Feature_RelocNotPICBit);
169 if (TM.isPositionIndependent())
170 Features.set(Feature_RelocPICBit);
171 if (Subtarget->hasStandardEncoding())
172 Features.set(Feature_HasStdEncBit);
173 if (!Subtarget->hasDSP())
174 Features.set(Feature_NotDSPBit);
175 if (Subtarget->inMicroMipsMode())
176 Features.set(Feature_InMicroMipsBit);
177 if (!Subtarget->inMicroMipsMode())
178 Features.set(Feature_NotInMicroMipsBit);
179 if (Subtarget->isLittle())
180 Features.set(Feature_IsLEBit);
181 if (!Subtarget->isLittle())
182 Features.set(Feature_IsBEBit);
183 if (Subtarget->hasEVA())
184 Features.set(Feature_HasEVABit);
185 if (Subtarget->hasMSA())
186 Features.set(Feature_HasMSABit);
187 if (!Subtarget->disableMadd4())
188 Features.set(Feature_HasMadd4Bit);
189 if (Subtarget->useIndirectJumpsHazard())
190 Features.set(Feature_UseIndirectJumpsHazardBit);
191 if (!Subtarget->useIndirectJumpsHazard())
192 Features.set(Feature_NoIndirectJumpGuardsBit);
193 if (Subtarget->isR5900())
194 Features.set(Feature_IsR5900Bit);
195 if (!Subtarget->isR5900())
196 Features.set(Feature_NotR5900Bit);
197 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
198 Features.set(Feature_AllowFPOpFusionBit);
199 if (Subtarget->isFP64bit())
200 Features.set(Feature_IsFP64bitBit);
201 if (!Subtarget->isFP64bit())
202 Features.set(Feature_NotFP64bitBit);
203 if (!Subtarget->isSingleFloat())
204 Features.set(Feature_IsNotSingleFloatBit);
205 if (!Subtarget->useSoftFloat())
206 Features.set(Feature_IsNotSoftFloatBit);
207 if (Subtarget->hasDSP())
208 Features.set(Feature_HasDSPBit);
209 if (Subtarget->hasDSPR2())
210 Features.set(Feature_HasDSPR2Bit);
211 return Features;
212}
213
214void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
215 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
216}
217PredicateBitset MipsInstructionSelector::
218computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
219 PredicateBitset Features{};
220 return Features;
221}
222
223// Feature bitsets.
224enum {
225 GIFBS_Invalid,
226 GIFBS_HasCnMips,
227 GIFBS_HasDSP,
228 GIFBS_HasDSPR2,
229 GIFBS_HasMSA,
230 GIFBS_InMicroMips,
231 GIFBS_InMips16Mode,
232 GIFBS_NotInMips16Mode,
233 GIFBS_HasDSP_InMicroMips,
234 GIFBS_HasDSP_NotInMicroMips,
235 GIFBS_HasDSPR2_InMicroMips,
236 GIFBS_HasMSA_HasStdEnc,
237 GIFBS_HasMSA_IsBE,
238 GIFBS_HasMSA_IsLE,
239 GIFBS_HasMips32r6_HasStdEnc,
240 GIFBS_HasMips32r6_InMicroMips,
241 GIFBS_HasMips64r2_HasStdEnc,
242 GIFBS_HasMips64r6_HasStdEnc,
243 GIFBS_HasStdEnc_IsNotSoftFloat,
244 GIFBS_HasStdEnc_NotInMicroMips,
245 GIFBS_HasStdEnc_NotMips4_32,
246 GIFBS_InMicroMips_IsNotSoftFloat,
247 GIFBS_InMicroMips_NotMips32r6,
248 GIFBS_IsFP64bit_IsNotSingleFloat,
249 GIFBS_IsGP64bit_NotInMips16Mode,
250 GIFBS_IsNotSingleFloat_NotFP64bit,
251 GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
252 GIFBS_HasMSA_HasMips64_HasStdEnc,
253 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
254 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
255 GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
256 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
257 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
258 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
259 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
260 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
261 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
262 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
263 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat,
264 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit,
265 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
266 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
267 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
268 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
269 GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat,
270 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
271 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
272 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
273 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
274 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
275 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
276 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips,
277 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32,
278 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips,
279 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32,
280 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
281 GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit,
282 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6,
283 GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode,
284 GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
285 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
286 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
287 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
288 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
289 GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
290 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
291 GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
292 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
293 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
294 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
295 GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
296 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
297 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
298};
299constexpr static PredicateBitset FeatureBitsets[] {
300 {}, // GIFBS_Invalid
301 {Feature_HasCnMipsBit, },
302 {Feature_HasDSPBit, },
303 {Feature_HasDSPR2Bit, },
304 {Feature_HasMSABit, },
305 {Feature_InMicroMipsBit, },
306 {Feature_InMips16ModeBit, },
307 {Feature_NotInMips16ModeBit, },
308 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
309 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
310 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
311 {Feature_HasMSABit, Feature_HasStdEncBit, },
312 {Feature_HasMSABit, Feature_IsBEBit, },
313 {Feature_HasMSABit, Feature_IsLEBit, },
314 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
315 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
316 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
317 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
318 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
319 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
320 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
321 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
322 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
323 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
324 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
325 {Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
326 {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
327 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
328 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
329 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
330 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
331 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
332 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
333 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
334 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
335 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
336 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
337 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
338 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
339 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
340 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
341 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
342 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
343 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
344 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
345 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
346 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
347 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
348 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
349 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
350 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
351 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, },
352 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, },
353 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
354 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
355 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
356 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
357 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
358 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
359 {Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
360 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
361 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
362 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
363 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
364 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
365 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
366 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
367 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
368 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
369 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
370 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
371 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
372 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
373};
374
375// ComplexPattern predicates.
376enum {
377 GICP_Invalid,
378};
379// See constructor for table contents
380
381MipsInstructionSelector::ComplexMatcherMemFn
382MipsInstructionSelector::ComplexPredicateFns[] = {
383 nullptr, // GICP_Invalid
384};
385
386// PatFrag predicates.
387enum {
388 GICXXPred_MI_Predicate_ffloor_nnan = GICXXPred_Invalid + 1,
389 GICXXPred_MI_Predicate_or_disjoint,
390};
391bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
392 const MachineFunction &MF = *MI.getParent()->getParent();
393 const MachineRegisterInfo &MRI = MF.getRegInfo();
394 const auto &Operands = State.RecordedOperands;
395 (void)Operands;
396 (void)MRI;
397 switch (PredicateID) {
398 case GICXXPred_MI_Predicate_ffloor_nnan: {
399
400 return MI.getFlag(MachineInstr::FmNoNans);
401
402 }
403 case GICXXPred_MI_Predicate_or_disjoint: {
404
405 return MI.getFlag(MachineInstr::Disjoint);
406
407 }
408 }
409 llvm_unreachable("Unknown predicate");
410 return false;
411}
412// PatFrag predicates.
413bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
414 const auto &Operands = State.RecordedOperands;
415 Register Reg = MO.getReg();
416 (void)Operands;
417 (void)Reg;
418 llvm_unreachable("Unknown predicate");
419 return false;
420}
421// PatFrag predicates.
422enum {
423 GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
424 GICXXPred_I64_Predicate_immSExt6,
425 GICXXPred_I64_Predicate_immSExt10,
426 GICXXPred_I64_Predicate_immSExtAddiur2,
427 GICXXPred_I64_Predicate_immSExtAddius5,
428 GICXXPred_I64_Predicate_immZExt1,
429 GICXXPred_I64_Predicate_immZExt1Ptr,
430 GICXXPred_I64_Predicate_immZExt2,
431 GICXXPred_I64_Predicate_immZExt2Lsa,
432 GICXXPred_I64_Predicate_immZExt2Ptr,
433 GICXXPred_I64_Predicate_immZExt2Shift,
434 GICXXPred_I64_Predicate_immZExt3,
435 GICXXPred_I64_Predicate_immZExt3Ptr,
436 GICXXPred_I64_Predicate_immZExt4,
437 GICXXPred_I64_Predicate_immZExt4Ptr,
438 GICXXPred_I64_Predicate_immZExt5,
439 GICXXPred_I64_Predicate_immZExt5_64,
440 GICXXPred_I64_Predicate_immZExt6,
441 GICXXPred_I64_Predicate_immZExt8,
442 GICXXPred_I64_Predicate_immZExt10,
443 GICXXPred_I64_Predicate_immZExtAndi16,
444 GICXXPred_I64_Predicate_immi32Cst7,
445 GICXXPred_I64_Predicate_immi32Cst15,
446 GICXXPred_I64_Predicate_immi32Cst31,
447 GICXXPred_I64_Predicate_timmSExt6,
448 GICXXPred_I64_Predicate_timmZExt1,
449 GICXXPred_I64_Predicate_timmZExt1Ptr,
450 GICXXPred_I64_Predicate_timmZExt2,
451 GICXXPred_I64_Predicate_timmZExt2Ptr,
452 GICXXPred_I64_Predicate_timmZExt3,
453 GICXXPred_I64_Predicate_timmZExt3Ptr,
454 GICXXPred_I64_Predicate_timmZExt4,
455 GICXXPred_I64_Predicate_timmZExt4Ptr,
456 GICXXPred_I64_Predicate_timmZExt5,
457 GICXXPred_I64_Predicate_timmZExt6,
458 GICXXPred_I64_Predicate_timmZExt8,
459 GICXXPred_I64_Predicate_timmZExt10,
460};
461bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
462 switch (PredicateID) {
463 case GICXXPred_I64_Predicate_immLi16: {
464 return Imm >= -1 && Imm <= 126;
465 }
466 case GICXXPred_I64_Predicate_immSExt6: {
467 return isInt<6>(Imm);
468 }
469 case GICXXPred_I64_Predicate_immSExt10: {
470 return isInt<10>(Imm);
471 }
472 case GICXXPred_I64_Predicate_immSExtAddiur2: {
473 return Imm == 1 || Imm == -1 ||
474 ((Imm % 4 == 0) &&
475 Imm < 28 && Imm > 0);
476 }
477 case GICXXPred_I64_Predicate_immSExtAddius5: {
478 return Imm >= -8 && Imm <= 7;
479 }
480 case GICXXPred_I64_Predicate_immZExt1: {
481 return isUInt<1>(Imm);
482 }
483 case GICXXPred_I64_Predicate_immZExt1Ptr: {
484 return isUInt<1>(Imm);
485 }
486 case GICXXPred_I64_Predicate_immZExt2: {
487 return isUInt<2>(Imm);
488 }
489 case GICXXPred_I64_Predicate_immZExt2Lsa: {
490 return isUInt<2>(Imm - 1);
491 }
492 case GICXXPred_I64_Predicate_immZExt2Ptr: {
493 return isUInt<2>(Imm);
494 }
495 case GICXXPred_I64_Predicate_immZExt2Shift: {
496 return Imm >= 1 && Imm <= 8;
497 }
498 case GICXXPred_I64_Predicate_immZExt3: {
499 return isUInt<3>(Imm);
500 }
501 case GICXXPred_I64_Predicate_immZExt3Ptr: {
502 return isUInt<3>(Imm);
503 }
504 case GICXXPred_I64_Predicate_immZExt4: {
505 return isUInt<4>(Imm);
506 }
507 case GICXXPred_I64_Predicate_immZExt4Ptr: {
508 return isUInt<4>(Imm);
509 }
510 case GICXXPred_I64_Predicate_immZExt5: {
511 return Imm == (Imm & 0x1f);
512 }
513 case GICXXPred_I64_Predicate_immZExt5_64: {
514 return Imm == (Imm & 0x1f);
515 }
516 case GICXXPred_I64_Predicate_immZExt6: {
517 return Imm == (Imm & 0x3f);
518 }
519 case GICXXPred_I64_Predicate_immZExt8: {
520 return isUInt<8>(Imm);
521 }
522 case GICXXPred_I64_Predicate_immZExt10: {
523 return isUInt<10>(Imm);
524 }
525 case GICXXPred_I64_Predicate_immZExtAndi16: {
526 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
527 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
528 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
529 }
530 case GICXXPred_I64_Predicate_immi32Cst7: {
531 return isUInt<32>(Imm) && Imm == 7;
532 }
533 case GICXXPred_I64_Predicate_immi32Cst15: {
534 return isUInt<32>(Imm) && Imm == 15;
535 }
536 case GICXXPred_I64_Predicate_immi32Cst31: {
537 return isUInt<32>(Imm) && Imm == 31;
538 }
539 case GICXXPred_I64_Predicate_timmSExt6: {
540 return isInt<6>(Imm);
541 }
542 case GICXXPred_I64_Predicate_timmZExt1: {
543 return isUInt<1>(Imm);
544 }
545 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
546 return isUInt<1>(Imm);
547 }
548 case GICXXPred_I64_Predicate_timmZExt2: {
549 return isUInt<2>(Imm);
550 }
551 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
552 return isUInt<2>(Imm);
553 }
554 case GICXXPred_I64_Predicate_timmZExt3: {
555 return isUInt<3>(Imm);
556 }
557 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
558 return isUInt<3>(Imm);
559 }
560 case GICXXPred_I64_Predicate_timmZExt4: {
561 return isUInt<4>(Imm);
562 }
563 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
564 return isUInt<4>(Imm);
565 }
566 case GICXXPred_I64_Predicate_timmZExt5: {
567 return Imm == (Imm & 0x1f);
568 }
569 case GICXXPred_I64_Predicate_timmZExt6: {
570 return Imm == (Imm & 0x3f);
571 }
572 case GICXXPred_I64_Predicate_timmZExt8: {
573 return isUInt<8>(Imm);
574 }
575 case GICXXPred_I64_Predicate_timmZExt10: {
576 return isUInt<10>(Imm);
577 }
578 }
579 llvm_unreachable("Unknown predicate");
580 return false;
581}
582// PatFrag predicates.
583bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
584 llvm_unreachable("Unknown predicate");
585 return false;
586}
587// PatFrag predicates.
588enum {
589 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
590 GICXXPred_APInt_Predicate_imm32ZExt16,
591};
592bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
593 switch (PredicateID) {
594 case GICXXPred_APInt_Predicate_imm32SExt16: {
595 return isInt<16>(Imm.getSExtValue());
596 }
597 case GICXXPred_APInt_Predicate_imm32ZExt16: {
598
599 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
600
601 }
602 }
603 llvm_unreachable("Unknown predicate");
604 return false;
605}
606bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
607 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
608 return false;
609}
610// Custom renderers.
611enum {
612 GICR_Invalid,
613};
614MipsInstructionSelector::CustomRendererFn
615MipsInstructionSelector::CustomRenderers[] = {
616 nullptr, // GICR_Invalid
617};
618
619bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
620 const PredicateBitset AvailableFeatures = getAvailableFeatures();
621 MachineIRBuilder B(I);
622 State.MIs.clear();
623 State.MIs.push_back(&I);
624
625 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
626 return true;
627 }
628
629 return false;
630}
631
632bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
633 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
634}
635#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
636#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
637#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
638#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
639#else
640#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
641#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
642#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
643#endif
644const uint8_t *MipsInstructionSelector::getMatchTable() const {
645 constexpr static uint8_t MatchTable0[] = {
646 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(304), /*)*//*default:*//*Label 84*/ GIMT_Encode4(72215),
647 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1006),
648 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2304),
649 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2995),
650 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3476),
651 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3745),
652 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(4014),
653 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4283), GIMT_Encode4(0), GIMT_Encode4(0),
654 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4552),
655 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5108),
656 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5512), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
657 /* 118 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6404),
658 /* 122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6477), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
659 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6818), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
660 /* 186 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(11129),
661 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(11194),
662 /* 194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11262), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
663 /* 222 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(11330),
664 /* 226 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11522),
665 /* 230 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11692),
666 /* 234 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11862),
667 /* 238 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(12032),
668 /* 242 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(12202),
669 /* 246 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(12372),
670 /* 250 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12542),
671 /* 254 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12712),
672 /* 258 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12882),
673 /* 262 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(13052),
674 /* 266 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(13222), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
675 /* 326 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(13392), GIMT_Encode4(0), GIMT_Encode4(0),
676 /* 338 */ /*TargetOpcode::G_INTRINSIC*//*Label 29*/ GIMT_Encode4(19937),
677 /* 342 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ GIMT_Encode4(34202), GIMT_Encode4(0), GIMT_Encode4(0),
678 /* 354 */ /*TargetOpcode::G_ANYEXT*//*Label 31*/ GIMT_Encode4(39296),
679 /* 358 */ /*TargetOpcode::G_TRUNC*//*Label 32*/ GIMT_Encode4(39362), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
680 /* 374 */ /*TargetOpcode::G_CONSTANT*//*Label 33*/ GIMT_Encode4(39426), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
681 /* 390 */ /*TargetOpcode::G_SEXT*//*Label 34*/ GIMT_Encode4(39487),
682 /* 394 */ /*TargetOpcode::G_SEXT_INREG*//*Label 35*/ GIMT_Encode4(40951),
683 /* 398 */ /*TargetOpcode::G_ZEXT*//*Label 36*/ GIMT_Encode4(41299),
684 /* 402 */ /*TargetOpcode::G_SHL*//*Label 37*/ GIMT_Encode4(41500),
685 /* 406 */ /*TargetOpcode::G_LSHR*//*Label 38*/ GIMT_Encode4(43297),
686 /* 410 */ /*TargetOpcode::G_ASHR*//*Label 39*/ GIMT_Encode4(45094), GIMT_Encode4(0), GIMT_Encode4(0),
687 /* 422 */ /*TargetOpcode::G_ROTR*//*Label 40*/ GIMT_Encode4(46849), GIMT_Encode4(0),
688 /* 430 */ /*TargetOpcode::G_ICMP*//*Label 41*/ GIMT_Encode4(47137),
689 /* 434 */ /*TargetOpcode::G_FCMP*//*Label 42*/ GIMT_Encode4(49668), GIMT_Encode4(0), GIMT_Encode4(0),
690 /* 446 */ /*TargetOpcode::G_SELECT*//*Label 43*/ GIMT_Encode4(50668), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
691 /* 490 */ /*TargetOpcode::G_UMULH*//*Label 44*/ GIMT_Encode4(62798),
692 /* 494 */ /*TargetOpcode::G_SMULH*//*Label 45*/ GIMT_Encode4(62907), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
693 /* 554 */ /*TargetOpcode::G_FADD*//*Label 46*/ GIMT_Encode4(63016),
694 /* 558 */ /*TargetOpcode::G_FSUB*//*Label 47*/ GIMT_Encode4(64319),
695 /* 562 */ /*TargetOpcode::G_FMUL*//*Label 48*/ GIMT_Encode4(65142),
696 /* 566 */ /*TargetOpcode::G_FMA*//*Label 49*/ GIMT_Encode4(65661), GIMT_Encode4(0),
697 /* 574 */ /*TargetOpcode::G_FDIV*//*Label 50*/ GIMT_Encode4(65763), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
698 /* 598 */ /*TargetOpcode::G_FEXP2*//*Label 51*/ GIMT_Encode4(66094), GIMT_Encode4(0), GIMT_Encode4(0),
699 /* 610 */ /*TargetOpcode::G_FLOG2*//*Label 52*/ GIMT_Encode4(66168), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
700 /* 626 */ /*TargetOpcode::G_FNEG*//*Label 53*/ GIMT_Encode4(66242),
701 /* 630 */ /*TargetOpcode::G_FPEXT*//*Label 54*/ GIMT_Encode4(66435),
702 /* 634 */ /*TargetOpcode::G_FPTRUNC*//*Label 55*/ GIMT_Encode4(66629),
703 /* 638 */ /*TargetOpcode::G_FPTOSI*//*Label 56*/ GIMT_Encode4(66808),
704 /* 642 */ /*TargetOpcode::G_FPTOUI*//*Label 57*/ GIMT_Encode4(66882),
705 /* 646 */ /*TargetOpcode::G_SITOFP*//*Label 58*/ GIMT_Encode4(66956),
706 /* 650 */ /*TargetOpcode::G_UITOFP*//*Label 59*/ GIMT_Encode4(67217), GIMT_Encode4(0), GIMT_Encode4(0),
707 /* 662 */ /*TargetOpcode::G_FABS*//*Label 60*/ GIMT_Encode4(67291), GIMT_Encode4(0), GIMT_Encode4(0),
708 /* 674 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 61*/ GIMT_Encode4(67441),
709 /* 678 */ /*TargetOpcode::G_FMINNUM*//*Label 62*/ GIMT_Encode4(67515),
710 /* 682 */ /*TargetOpcode::G_FMAXNUM*//*Label 63*/ GIMT_Encode4(67587),
711 /* 686 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 64*/ GIMT_Encode4(67659),
712 /* 690 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 65*/ GIMT_Encode4(67731), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
713 /* 750 */ /*TargetOpcode::G_SMIN*//*Label 66*/ GIMT_Encode4(67803),
714 /* 754 */ /*TargetOpcode::G_SMAX*//*Label 67*/ GIMT_Encode4(67971),
715 /* 758 */ /*TargetOpcode::G_UMIN*//*Label 68*/ GIMT_Encode4(68139),
716 /* 762 */ /*TargetOpcode::G_UMAX*//*Label 69*/ GIMT_Encode4(68307), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
717 /* 778 */ /*TargetOpcode::G_BR*//*Label 70*/ GIMT_Encode4(68475), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
718 /* 798 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(68599),
719 /* 802 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(69163), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
720 /* 830 */ /*TargetOpcode::G_CTLZ*//*Label 73*/ GIMT_Encode4(69215), GIMT_Encode4(0), GIMT_Encode4(0),
721 /* 842 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(69720),
722 /* 846 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(69926), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
723 /* 902 */ /*TargetOpcode::G_FSQRT*//*Label 76*/ GIMT_Encode4(70090), GIMT_Encode4(0),
724 /* 910 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(70362), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
725 /* 942 */ /*TargetOpcode::G_STRICT_FADD*//*Label 78*/ GIMT_Encode4(70436),
726 /* 946 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 79*/ GIMT_Encode4(71291),
727 /* 950 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 80*/ GIMT_Encode4(71788),
728 /* 954 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 81*/ GIMT_Encode4(71921), GIMT_Encode4(0), GIMT_Encode4(0),
729 /* 966 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 82*/ GIMT_Encode4(72054), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
730 /* 1002 */ /*TargetOpcode::G_TRAP*//*Label 83*/ GIMT_Encode4(72169),
731 /* 1006 */ // Label 0: @1006
732 /* 1006 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 93*/ GIMT_Encode4(2303),
733 /* 1017 */ /*GILLT_s32*//*Label 85*/ GIMT_Encode4(1049),
734 /* 1021 */ /*GILLT_s64*//*Label 86*/ GIMT_Encode4(1457),
735 /* 1025 */ /*GILLT_v4s8*//*Label 87*/ GIMT_Encode4(1623),
736 /* 1029 */ /*GILLT_v16s8*//*Label 88*/ GIMT_Encode4(1655),
737 /* 1033 */ /*GILLT_v2s16*//*Label 89*/ GIMT_Encode4(1809),
738 /* 1037 */ /*GILLT_v8s16*//*Label 90*/ GIMT_Encode4(1841),
739 /* 1041 */ /*GILLT_v4s32*//*Label 91*/ GIMT_Encode4(1995),
740 /* 1045 */ /*GILLT_v2s64*//*Label 92*/ GIMT_Encode4(2149),
741 /* 1049 */ // Label 85: @1049
742 /* 1049 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1456),
743 /* 1054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
744 /* 1057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
745 /* 1060 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1127), // Rule ID 2538 //
746 /* 1065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
747 /* 1068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
748 /* 1072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
749 /* 1076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
750 /* 1080 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
751 /* 1084 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
752 /* 1088 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
753 /* 1093 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
754 /* 1097 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
755 /* 1101 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
756 /* 1105 */ // MIs[2] Operand 1
757 /* 1105 */ // No operand predicates
758 /* 1105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
759 /* 1109 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
760 /* 1111 */ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
761 /* 1111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
762 /* 1114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
763 /* 1116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
764 /* 1120 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
765 /* 1122 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
766 /* 1125 */ GIR_RootConstrainSelectedInstOperands,
767 /* 1126 */ // GIR_Coverage, 2538,
768 /* 1126 */ GIR_EraseRootFromParent_Done,
769 /* 1127 */ // Label 95: @1127
770 /* 1127 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1194), // Rule ID 858 //
771 /* 1132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
772 /* 1135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
773 /* 1139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
774 /* 1143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
775 /* 1147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
776 /* 1151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
777 /* 1155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
778 /* 1159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
779 /* 1164 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
780 /* 1168 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
781 /* 1172 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
782 /* 1176 */ // MIs[2] Operand 1
783 /* 1176 */ // No operand predicates
784 /* 1176 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
785 /* 1178 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
786 /* 1178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
787 /* 1181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
788 /* 1183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
789 /* 1187 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
790 /* 1189 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
791 /* 1192 */ GIR_RootConstrainSelectedInstOperands,
792 /* 1193 */ // GIR_Coverage, 858,
793 /* 1193 */ GIR_EraseRootFromParent_Done,
794 /* 1194 */ // Label 96: @1194
795 /* 1194 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1236), // Rule ID 40 //
796 /* 1199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
797 /* 1202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
798 /* 1206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
799 /* 1210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
800 /* 1214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
801 /* 1218 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
802 /* 1222 */ // MIs[1] Operand 1
803 /* 1222 */ // No operand predicates
804 /* 1222 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
805 /* 1224 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
806 /* 1224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
807 /* 1227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
808 /* 1229 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
809 /* 1231 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
810 /* 1234 */ GIR_RootConstrainSelectedInstOperands,
811 /* 1235 */ // GIR_Coverage, 40,
812 /* 1235 */ GIR_EraseRootFromParent_Done,
813 /* 1236 */ // Label 97: @1236
814 /* 1236 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1278), // Rule ID 2296 //
815 /* 1241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
816 /* 1244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
817 /* 1248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
818 /* 1252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
819 /* 1256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
820 /* 1260 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
821 /* 1264 */ // MIs[1] Operand 1
822 /* 1264 */ // No operand predicates
823 /* 1264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
824 /* 1266 */ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
825 /* 1266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
826 /* 1269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
827 /* 1271 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
828 /* 1273 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
829 /* 1276 */ GIR_RootConstrainSelectedInstOperands,
830 /* 1277 */ // GIR_Coverage, 2296,
831 /* 1277 */ GIR_EraseRootFromParent_Done,
832 /* 1278 */ // Label 98: @1278
833 /* 1278 */ GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1320), // Rule ID 2297 //
834 /* 1283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
835 /* 1286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
836 /* 1290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
837 /* 1294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
838 /* 1298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
839 /* 1302 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
840 /* 1306 */ // MIs[1] Operand 1
841 /* 1306 */ // No operand predicates
842 /* 1306 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
843 /* 1308 */ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
844 /* 1308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
845 /* 1311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
846 /* 1313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
847 /* 1315 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
848 /* 1318 */ GIR_RootConstrainSelectedInstOperands,
849 /* 1319 */ // GIR_Coverage, 2297,
850 /* 1319 */ GIR_EraseRootFromParent_Done,
851 /* 1320 */ // Label 99: @1320
852 /* 1320 */ GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1347), // Rule ID 1231 //
853 /* 1325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
854 /* 1328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
855 /* 1332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
856 /* 1336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
857 /* 1340 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
858 /* 1340 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
859 /* 1345 */ GIR_RootConstrainSelectedInstOperands,
860 /* 1346 */ // GIR_Coverage, 1231,
861 /* 1346 */ GIR_Done,
862 /* 1347 */ // Label 100: @1347
863 /* 1347 */ GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1374), // Rule ID 46 //
864 /* 1352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
865 /* 1355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
866 /* 1359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
867 /* 1363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
868 /* 1367 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
869 /* 1367 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
870 /* 1372 */ GIR_RootConstrainSelectedInstOperands,
871 /* 1373 */ // GIR_Coverage, 46,
872 /* 1373 */ GIR_Done,
873 /* 1374 */ // Label 101: @1374
874 /* 1374 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1401), // Rule ID 1084 //
875 /* 1379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
876 /* 1382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
877 /* 1386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
878 /* 1390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
879 /* 1394 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
880 /* 1394 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
881 /* 1399 */ GIR_RootConstrainSelectedInstOperands,
882 /* 1400 */ // GIR_Coverage, 1084,
883 /* 1400 */ GIR_Done,
884 /* 1401 */ // Label 102: @1401
885 /* 1401 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1428), // Rule ID 1096 //
886 /* 1406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
887 /* 1409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
888 /* 1413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
889 /* 1417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
890 /* 1421 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
891 /* 1421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
892 /* 1426 */ GIR_RootConstrainSelectedInstOperands,
893 /* 1427 */ // GIR_Coverage, 1096,
894 /* 1427 */ GIR_Done,
895 /* 1428 */ // Label 103: @1428
896 /* 1428 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1455), // Rule ID 1954 //
897 /* 1433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
898 /* 1436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
899 /* 1440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
900 /* 1444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
901 /* 1448 */ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
902 /* 1448 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
903 /* 1453 */ GIR_RootConstrainSelectedInstOperands,
904 /* 1454 */ // GIR_Coverage, 1954,
905 /* 1454 */ GIR_Done,
906 /* 1455 */ // Label 104: @1455
907 /* 1455 */ GIM_Reject,
908 /* 1456 */ // Label 94: @1456
909 /* 1456 */ GIM_Reject,
910 /* 1457 */ // Label 86: @1457
911 /* 1457 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1622),
912 /* 1462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
913 /* 1465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
914 /* 1468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
915 /* 1472 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1535), // Rule ID 2539 //
916 /* 1477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
917 /* 1480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
918 /* 1484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
919 /* 1488 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
920 /* 1492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
921 /* 1496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
922 /* 1501 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
923 /* 1505 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
924 /* 1509 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
925 /* 1513 */ // MIs[2] Operand 1
926 /* 1513 */ // No operand predicates
927 /* 1513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
928 /* 1517 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
929 /* 1519 */ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
930 /* 1519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
931 /* 1522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
932 /* 1524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
933 /* 1528 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
934 /* 1530 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
935 /* 1533 */ GIR_RootConstrainSelectedInstOperands,
936 /* 1534 */ // GIR_Coverage, 2539,
937 /* 1534 */ GIR_EraseRootFromParent_Done,
938 /* 1535 */ // Label 106: @1535
939 /* 1535 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1598), // Rule ID 859 //
940 /* 1540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
941 /* 1543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
942 /* 1547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
943 /* 1551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
944 /* 1555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
945 /* 1559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
946 /* 1563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
947 /* 1568 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
948 /* 1572 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
949 /* 1576 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
950 /* 1580 */ // MIs[2] Operand 1
951 /* 1580 */ // No operand predicates
952 /* 1580 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
953 /* 1582 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
954 /* 1582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
955 /* 1585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
956 /* 1587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
957 /* 1591 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
958 /* 1593 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
959 /* 1596 */ GIR_RootConstrainSelectedInstOperands,
960 /* 1597 */ // GIR_Coverage, 859,
961 /* 1597 */ GIR_EraseRootFromParent_Done,
962 /* 1598 */ // Label 107: @1598
963 /* 1598 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1621), // Rule ID 226 //
964 /* 1603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
965 /* 1606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
966 /* 1610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
967 /* 1614 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
968 /* 1614 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
969 /* 1619 */ GIR_RootConstrainSelectedInstOperands,
970 /* 1620 */ // GIR_Coverage, 226,
971 /* 1620 */ GIR_Done,
972 /* 1621 */ // Label 108: @1621
973 /* 1621 */ GIM_Reject,
974 /* 1622 */ // Label 105: @1622
975 /* 1622 */ GIM_Reject,
976 /* 1623 */ // Label 87: @1623
977 /* 1623 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1654), // Rule ID 2059 //
978 /* 1628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
979 /* 1631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
980 /* 1634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
981 /* 1637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
982 /* 1641 */ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
983 /* 1641 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
984 /* 1646 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
985 /* 1652 */ GIR_RootConstrainSelectedInstOperands,
986 /* 1653 */ // GIR_Coverage, 2059,
987 /* 1653 */ GIR_Done,
988 /* 1654 */ // Label 109: @1654
989 /* 1654 */ GIM_Reject,
990 /* 1655 */ // Label 88: @1655
991 /* 1655 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1808),
992 /* 1660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
993 /* 1663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
994 /* 1666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
995 /* 1670 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1727), // Rule ID 2540 //
996 /* 1675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
997 /* 1678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
998 /* 1682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
999 /* 1686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1000 /* 1690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1001 /* 1694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1002 /* 1699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1003 /* 1704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1004 /* 1708 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1005 /* 1710 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1006 /* 1710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1007 /* 1713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1008 /* 1715 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1009 /* 1717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1010 /* 1721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1011 /* 1725 */ GIR_RootConstrainSelectedInstOperands,
1012 /* 1726 */ // GIR_Coverage, 2540,
1013 /* 1726 */ GIR_EraseRootFromParent_Done,
1014 /* 1727 */ // Label 111: @1727
1015 /* 1727 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1784), // Rule ID 864 //
1016 /* 1732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1017 /* 1735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1018 /* 1739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1019 /* 1743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1020 /* 1747 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1021 /* 1751 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1022 /* 1755 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1023 /* 1760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1024 /* 1765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1025 /* 1767 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1026 /* 1767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1027 /* 1770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1028 /* 1772 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1029 /* 1774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1030 /* 1778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1031 /* 1782 */ GIR_RootConstrainSelectedInstOperands,
1032 /* 1783 */ // GIR_Coverage, 864,
1033 /* 1783 */ GIR_EraseRootFromParent_Done,
1034 /* 1784 */ // Label 112: @1784
1035 /* 1784 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1807), // Rule ID 531 //
1036 /* 1789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1037 /* 1792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1038 /* 1796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1039 /* 1800 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1040 /* 1800 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1041 /* 1805 */ GIR_RootConstrainSelectedInstOperands,
1042 /* 1806 */ // GIR_Coverage, 531,
1043 /* 1806 */ GIR_Done,
1044 /* 1807 */ // Label 113: @1807
1045 /* 1807 */ GIM_Reject,
1046 /* 1808 */ // Label 110: @1808
1047 /* 1808 */ GIM_Reject,
1048 /* 1809 */ // Label 89: @1809
1049 /* 1809 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1840), // Rule ID 2053 //
1050 /* 1814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1051 /* 1817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1052 /* 1820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1053 /* 1823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1054 /* 1827 */ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1055 /* 1827 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
1056 /* 1832 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1057 /* 1838 */ GIR_RootConstrainSelectedInstOperands,
1058 /* 1839 */ // GIR_Coverage, 2053,
1059 /* 1839 */ GIR_Done,
1060 /* 1840 */ // Label 114: @1840
1061 /* 1840 */ GIM_Reject,
1062 /* 1841 */ // Label 90: @1841
1063 /* 1841 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1994),
1064 /* 1846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1065 /* 1849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1066 /* 1852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1067 /* 1856 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1913), // Rule ID 2541 //
1068 /* 1861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1069 /* 1864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1070 /* 1868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1071 /* 1872 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1072 /* 1876 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1073 /* 1880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1074 /* 1885 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1075 /* 1890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1076 /* 1894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1077 /* 1896 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1078 /* 1896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1079 /* 1899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1080 /* 1901 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1081 /* 1903 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1082 /* 1907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1083 /* 1911 */ GIR_RootConstrainSelectedInstOperands,
1084 /* 1912 */ // GIR_Coverage, 2541,
1085 /* 1912 */ GIR_EraseRootFromParent_Done,
1086 /* 1913 */ // Label 116: @1913
1087 /* 1913 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1970), // Rule ID 865 //
1088 /* 1918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1089 /* 1921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1090 /* 1925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1091 /* 1929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1092 /* 1933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1093 /* 1937 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1094 /* 1941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1095 /* 1946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1096 /* 1951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1097 /* 1953 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1098 /* 1953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1099 /* 1956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1100 /* 1958 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1101 /* 1960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1102 /* 1964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1103 /* 1968 */ GIR_RootConstrainSelectedInstOperands,
1104 /* 1969 */ // GIR_Coverage, 865,
1105 /* 1969 */ GIR_EraseRootFromParent_Done,
1106 /* 1970 */ // Label 117: @1970
1107 /* 1970 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1993), // Rule ID 532 //
1108 /* 1975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1109 /* 1978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1110 /* 1982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1111 /* 1986 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1112 /* 1986 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1113 /* 1991 */ GIR_RootConstrainSelectedInstOperands,
1114 /* 1992 */ // GIR_Coverage, 532,
1115 /* 1992 */ GIR_Done,
1116 /* 1993 */ // Label 118: @1993
1117 /* 1993 */ GIM_Reject,
1118 /* 1994 */ // Label 115: @1994
1119 /* 1994 */ GIM_Reject,
1120 /* 1995 */ // Label 91: @1995
1121 /* 1995 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2148),
1122 /* 2000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1123 /* 2003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1124 /* 2006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1125 /* 2010 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2067), // Rule ID 2542 //
1126 /* 2015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1127 /* 2018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1128 /* 2022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1129 /* 2026 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1130 /* 2030 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1131 /* 2034 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1132 /* 2039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1133 /* 2044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1134 /* 2048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1135 /* 2050 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1136 /* 2050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1137 /* 2053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1138 /* 2055 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1139 /* 2057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1140 /* 2061 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1141 /* 2065 */ GIR_RootConstrainSelectedInstOperands,
1142 /* 2066 */ // GIR_Coverage, 2542,
1143 /* 2066 */ GIR_EraseRootFromParent_Done,
1144 /* 2067 */ // Label 120: @2067
1145 /* 2067 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2124), // Rule ID 866 //
1146 /* 2072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1147 /* 2075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1148 /* 2079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1149 /* 2083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1150 /* 2087 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1151 /* 2091 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1152 /* 2095 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1153 /* 2100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1154 /* 2105 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1155 /* 2107 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1156 /* 2107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1157 /* 2110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1158 /* 2112 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1159 /* 2114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1160 /* 2118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1161 /* 2122 */ GIR_RootConstrainSelectedInstOperands,
1162 /* 2123 */ // GIR_Coverage, 866,
1163 /* 2123 */ GIR_EraseRootFromParent_Done,
1164 /* 2124 */ // Label 121: @2124
1165 /* 2124 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2147), // Rule ID 533 //
1166 /* 2129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1167 /* 2132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1168 /* 2136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1169 /* 2140 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1170 /* 2140 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1171 /* 2145 */ GIR_RootConstrainSelectedInstOperands,
1172 /* 2146 */ // GIR_Coverage, 533,
1173 /* 2146 */ GIR_Done,
1174 /* 2147 */ // Label 122: @2147
1175 /* 2147 */ GIM_Reject,
1176 /* 2148 */ // Label 119: @2148
1177 /* 2148 */ GIM_Reject,
1178 /* 2149 */ // Label 92: @2149
1179 /* 2149 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2302),
1180 /* 2154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1181 /* 2157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1182 /* 2160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1183 /* 2164 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2221), // Rule ID 2543 //
1184 /* 2169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1185 /* 2172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1186 /* 2176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1187 /* 2180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1188 /* 2184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1189 /* 2188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1190 /* 2193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1191 /* 2198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1192 /* 2202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1193 /* 2204 */ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1194 /* 2204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1195 /* 2207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1196 /* 2209 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1197 /* 2211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1198 /* 2215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1199 /* 2219 */ GIR_RootConstrainSelectedInstOperands,
1200 /* 2220 */ // GIR_Coverage, 2543,
1201 /* 2220 */ GIR_EraseRootFromParent_Done,
1202 /* 2221 */ // Label 124: @2221
1203 /* 2221 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2278), // Rule ID 867 //
1204 /* 2226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1205 /* 2229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1206 /* 2233 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1207 /* 2237 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1208 /* 2241 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1209 /* 2245 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1210 /* 2249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1211 /* 2254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1212 /* 2259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1213 /* 2261 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1214 /* 2261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1215 /* 2264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1216 /* 2266 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1217 /* 2268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1218 /* 2272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1219 /* 2276 */ GIR_RootConstrainSelectedInstOperands,
1220 /* 2277 */ // GIR_Coverage, 867,
1221 /* 2277 */ GIR_EraseRootFromParent_Done,
1222 /* 2278 */ // Label 125: @2278
1223 /* 2278 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2301), // Rule ID 534 //
1224 /* 2283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1225 /* 2286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1226 /* 2290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1227 /* 2294 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1228 /* 2294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
1229 /* 2299 */ GIR_RootConstrainSelectedInstOperands,
1230 /* 2300 */ // GIR_Coverage, 534,
1231 /* 2300 */ GIR_Done,
1232 /* 2301 */ // Label 126: @2301
1233 /* 2301 */ GIM_Reject,
1234 /* 2302 */ // Label 123: @2302
1235 /* 2302 */ GIM_Reject,
1236 /* 2303 */ // Label 93: @2303
1237 /* 2303 */ GIM_Reject,
1238 /* 2304 */ // Label 1: @2304
1239 /* 2304 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 135*/ GIMT_Encode4(2994),
1240 /* 2315 */ /*GILLT_s32*//*Label 127*/ GIMT_Encode4(2347),
1241 /* 2319 */ /*GILLT_s64*//*Label 128*/ GIMT_Encode4(2524),
1242 /* 2323 */ /*GILLT_v4s8*//*Label 129*/ GIMT_Encode4(2558),
1243 /* 2327 */ /*GILLT_v16s8*//*Label 130*/ GIMT_Encode4(2590),
1244 /* 2331 */ /*GILLT_v2s16*//*Label 131*/ GIMT_Encode4(2683),
1245 /* 2335 */ /*GILLT_v8s16*//*Label 132*/ GIMT_Encode4(2715),
1246 /* 2339 */ /*GILLT_v4s32*//*Label 133*/ GIMT_Encode4(2808),
1247 /* 2343 */ /*GILLT_v2s64*//*Label 134*/ GIMT_Encode4(2901),
1248 /* 2347 */ // Label 127: @2347
1249 /* 2347 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2523),
1250 /* 2352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1251 /* 2355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1252 /* 2358 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2387), // Rule ID 1953 //
1253 /* 2363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1254 /* 2366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1255 /* 2370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1256 /* 2374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1257 /* 2378 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1258 /* 2378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1259 /* 2381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1260 /* 2383 */ GIR_RootToRootCopy, /*OpIdx*/2, // r
1261 /* 2385 */ GIR_RootConstrainSelectedInstOperands,
1262 /* 2386 */ // GIR_Coverage, 1953,
1263 /* 2386 */ GIR_EraseRootFromParent_Done,
1264 /* 2387 */ // Label 137: @2387
1265 /* 2387 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(2414), // Rule ID 1233 //
1266 /* 2392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1267 /* 2395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1268 /* 2399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1269 /* 2403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1270 /* 2407 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1271 /* 2407 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1272 /* 2412 */ GIR_RootConstrainSelectedInstOperands,
1273 /* 2413 */ // GIR_Coverage, 1233,
1274 /* 2413 */ GIR_Done,
1275 /* 2414 */ // Label 138: @2414
1276 /* 2414 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(2441), // Rule ID 47 //
1277 /* 2419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
1278 /* 2422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1279 /* 2426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1280 /* 2430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1281 /* 2434 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1282 /* 2434 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1283 /* 2439 */ GIR_RootConstrainSelectedInstOperands,
1284 /* 2440 */ // GIR_Coverage, 47,
1285 /* 2440 */ GIR_Done,
1286 /* 2441 */ // Label 139: @2441
1287 /* 2441 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(2468), // Rule ID 1088 //
1288 /* 2446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1289 /* 2449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1290 /* 2453 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1291 /* 2457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1292 /* 2461 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1293 /* 2461 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1294 /* 2466 */ GIR_RootConstrainSelectedInstOperands,
1295 /* 2467 */ // GIR_Coverage, 1088,
1296 /* 2467 */ GIR_Done,
1297 /* 2468 */ // Label 140: @2468
1298 /* 2468 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2495), // Rule ID 1097 //
1299 /* 2473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1300 /* 2476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1301 /* 2480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1302 /* 2484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1303 /* 2488 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1304 /* 2488 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1305 /* 2493 */ GIR_RootConstrainSelectedInstOperands,
1306 /* 2494 */ // GIR_Coverage, 1097,
1307 /* 2494 */ GIR_Done,
1308 /* 2495 */ // Label 141: @2495
1309 /* 2495 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2522), // Rule ID 1958 //
1310 /* 2500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1311 /* 2503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1312 /* 2507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1313 /* 2511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1314 /* 2515 */ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1315 /* 2515 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1316 /* 2520 */ GIR_RootConstrainSelectedInstOperands,
1317 /* 2521 */ // GIR_Coverage, 1958,
1318 /* 2521 */ GIR_Done,
1319 /* 2522 */ // Label 142: @2522
1320 /* 2522 */ GIM_Reject,
1321 /* 2523 */ // Label 136: @2523
1322 /* 2523 */ GIM_Reject,
1323 /* 2524 */ // Label 128: @2524
1324 /* 2524 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2557), // Rule ID 227 //
1325 /* 2529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
1326 /* 2532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1327 /* 2535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1328 /* 2538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1329 /* 2542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1330 /* 2546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1331 /* 2550 */ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1332 /* 2550 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1333 /* 2555 */ GIR_RootConstrainSelectedInstOperands,
1334 /* 2556 */ // GIR_Coverage, 227,
1335 /* 2556 */ GIR_Done,
1336 /* 2557 */ // Label 143: @2557
1337 /* 2557 */ GIM_Reject,
1338 /* 2558 */ // Label 129: @2558
1339 /* 2558 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2589), // Rule ID 2061 //
1340 /* 2563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1341 /* 2566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1342 /* 2569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1343 /* 2572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1344 /* 2576 */ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1345 /* 2576 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1346 /* 2581 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1347 /* 2587 */ GIR_RootConstrainSelectedInstOperands,
1348 /* 2588 */ // GIR_Coverage, 2061,
1349 /* 2588 */ GIR_Done,
1350 /* 2589 */ // Label 144: @2589
1351 /* 2589 */ GIM_Reject,
1352 /* 2590 */ // Label 130: @2590
1353 /* 2590 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2682),
1354 /* 2595 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1355 /* 2598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1356 /* 2601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1357 /* 2605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1358 /* 2609 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2662), // Rule ID 920 //
1359 /* 2614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1360 /* 2617 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1361 /* 2621 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1362 /* 2625 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1363 /* 2629 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1364 /* 2633 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1365 /* 2638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1366 /* 2643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1367 /* 2645 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1368 /* 2645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1369 /* 2648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1370 /* 2650 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1371 /* 2652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1372 /* 2656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1373 /* 2660 */ GIR_RootConstrainSelectedInstOperands,
1374 /* 2661 */ // GIR_Coverage, 920,
1375 /* 2661 */ GIR_EraseRootFromParent_Done,
1376 /* 2662 */ // Label 146: @2662
1377 /* 2662 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2681), // Rule ID 1049 //
1378 /* 2667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1379 /* 2670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1380 /* 2674 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1381 /* 2674 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1382 /* 2679 */ GIR_RootConstrainSelectedInstOperands,
1383 /* 2680 */ // GIR_Coverage, 1049,
1384 /* 2680 */ GIR_Done,
1385 /* 2681 */ // Label 147: @2681
1386 /* 2681 */ GIM_Reject,
1387 /* 2682 */ // Label 145: @2682
1388 /* 2682 */ GIM_Reject,
1389 /* 2683 */ // Label 131: @2683
1390 /* 2683 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2714), // Rule ID 2055 //
1391 /* 2688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1392 /* 2691 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1393 /* 2694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1394 /* 2697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1395 /* 2701 */ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1396 /* 2701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1397 /* 2706 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1398 /* 2712 */ GIR_RootConstrainSelectedInstOperands,
1399 /* 2713 */ // GIR_Coverage, 2055,
1400 /* 2713 */ GIR_Done,
1401 /* 2714 */ // Label 148: @2714
1402 /* 2714 */ GIM_Reject,
1403 /* 2715 */ // Label 132: @2715
1404 /* 2715 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2807),
1405 /* 2720 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1406 /* 2723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1407 /* 2726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1408 /* 2730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1409 /* 2734 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2787), // Rule ID 921 //
1410 /* 2739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1411 /* 2742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1412 /* 2746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1413 /* 2750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1414 /* 2754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1415 /* 2758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1416 /* 2763 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1417 /* 2768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1418 /* 2770 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1419 /* 2770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1420 /* 2773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1421 /* 2775 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1422 /* 2777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1423 /* 2781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1424 /* 2785 */ GIR_RootConstrainSelectedInstOperands,
1425 /* 2786 */ // GIR_Coverage, 921,
1426 /* 2786 */ GIR_EraseRootFromParent_Done,
1427 /* 2787 */ // Label 150: @2787
1428 /* 2787 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2806), // Rule ID 1050 //
1429 /* 2792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1430 /* 2795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1431 /* 2799 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1432 /* 2799 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1433 /* 2804 */ GIR_RootConstrainSelectedInstOperands,
1434 /* 2805 */ // GIR_Coverage, 1050,
1435 /* 2805 */ GIR_Done,
1436 /* 2806 */ // Label 151: @2806
1437 /* 2806 */ GIM_Reject,
1438 /* 2807 */ // Label 149: @2807
1439 /* 2807 */ GIM_Reject,
1440 /* 2808 */ // Label 133: @2808
1441 /* 2808 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2900),
1442 /* 2813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1443 /* 2816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1444 /* 2819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1445 /* 2823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1446 /* 2827 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2880), // Rule ID 922 //
1447 /* 2832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1448 /* 2835 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1449 /* 2839 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1450 /* 2843 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1451 /* 2847 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1452 /* 2851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1453 /* 2856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1454 /* 2861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1455 /* 2863 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1456 /* 2863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1457 /* 2866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1458 /* 2868 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1459 /* 2870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1460 /* 2874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1461 /* 2878 */ GIR_RootConstrainSelectedInstOperands,
1462 /* 2879 */ // GIR_Coverage, 922,
1463 /* 2879 */ GIR_EraseRootFromParent_Done,
1464 /* 2880 */ // Label 153: @2880
1465 /* 2880 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2899), // Rule ID 1051 //
1466 /* 2885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1467 /* 2888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1468 /* 2892 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1469 /* 2892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1470 /* 2897 */ GIR_RootConstrainSelectedInstOperands,
1471 /* 2898 */ // GIR_Coverage, 1051,
1472 /* 2898 */ GIR_Done,
1473 /* 2899 */ // Label 154: @2899
1474 /* 2899 */ GIM_Reject,
1475 /* 2900 */ // Label 152: @2900
1476 /* 2900 */ GIM_Reject,
1477 /* 2901 */ // Label 134: @2901
1478 /* 2901 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2993),
1479 /* 2906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1480 /* 2909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1481 /* 2912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1482 /* 2916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1483 /* 2920 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2973), // Rule ID 923 //
1484 /* 2925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1485 /* 2928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1486 /* 2932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1487 /* 2936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1488 /* 2940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1489 /* 2944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1490 /* 2949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1491 /* 2954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1492 /* 2956 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1493 /* 2956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1494 /* 2959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1495 /* 2961 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1496 /* 2963 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1497 /* 2967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1498 /* 2971 */ GIR_RootConstrainSelectedInstOperands,
1499 /* 2972 */ // GIR_Coverage, 923,
1500 /* 2972 */ GIR_EraseRootFromParent_Done,
1501 /* 2973 */ // Label 156: @2973
1502 /* 2973 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2992), // Rule ID 1052 //
1503 /* 2978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1504 /* 2981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1505 /* 2985 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1506 /* 2985 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1507 /* 2990 */ GIR_RootConstrainSelectedInstOperands,
1508 /* 2991 */ // GIR_Coverage, 1052,
1509 /* 2991 */ GIR_Done,
1510 /* 2992 */ // Label 157: @2992
1511 /* 2992 */ GIM_Reject,
1512 /* 2993 */ // Label 155: @2993
1513 /* 2993 */ GIM_Reject,
1514 /* 2994 */ // Label 135: @2994
1515 /* 2994 */ GIM_Reject,
1516 /* 2995 */ // Label 2: @2995
1517 /* 2995 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 165*/ GIMT_Encode4(3475),
1518 /* 3006 */ /*GILLT_s32*//*Label 158*/ GIMT_Encode4(3038),
1519 /* 3010 */ /*GILLT_s64*//*Label 159*/ GIMT_Encode4(3222), GIMT_Encode4(0),
1520 /* 3018 */ /*GILLT_v16s8*//*Label 160*/ GIMT_Encode4(3307),
1521 /* 3022 */ /*GILLT_v2s16*//*Label 161*/ GIMT_Encode4(3341),
1522 /* 3026 */ /*GILLT_v8s16*//*Label 162*/ GIMT_Encode4(3373),
1523 /* 3030 */ /*GILLT_v4s32*//*Label 163*/ GIMT_Encode4(3407),
1524 /* 3034 */ /*GILLT_v2s64*//*Label 164*/ GIMT_Encode4(3441),
1525 /* 3038 */ // Label 158: @3038
1526 /* 3038 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3221),
1527 /* 3043 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1528 /* 3046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1529 /* 3049 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3088), // Rule ID 48 //
1530 /* 3054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
1531 /* 3057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1532 /* 3061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1533 /* 3065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1534 /* 3069 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1535 /* 3069 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1536 /* 3074 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1537 /* 3080 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1538 /* 3086 */ GIR_RootConstrainSelectedInstOperands,
1539 /* 3087 */ // GIR_Coverage, 48,
1540 /* 3087 */ GIR_Done,
1541 /* 3088 */ // Label 167: @3088
1542 /* 3088 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3115), // Rule ID 356 //
1543 /* 3093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1544 /* 3096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1545 /* 3100 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1546 /* 3104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1547 /* 3108 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1548 /* 3108 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1549 /* 3113 */ GIR_RootConstrainSelectedInstOperands,
1550 /* 3114 */ // GIR_Coverage, 356,
1551 /* 3114 */ GIR_Done,
1552 /* 3115 */ // Label 168: @3115
1553 /* 3115 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3154), // Rule ID 1098 //
1554 /* 3120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1555 /* 3123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1556 /* 3127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1557 /* 3131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1558 /* 3135 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1559 /* 3135 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1560 /* 3140 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1561 /* 3146 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1562 /* 3152 */ GIR_RootConstrainSelectedInstOperands,
1563 /* 3153 */ // GIR_Coverage, 1098,
1564 /* 3153 */ GIR_Done,
1565 /* 3154 */ // Label 169: @3154
1566 /* 3154 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3181), // Rule ID 1202 //
1567 /* 3159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1568 /* 3162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1569 /* 3166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1570 /* 3170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1571 /* 3174 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1572 /* 3174 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1573 /* 3179 */ GIR_RootConstrainSelectedInstOperands,
1574 /* 3180 */ // GIR_Coverage, 1202,
1575 /* 3180 */ GIR_Done,
1576 /* 3181 */ // Label 170: @3181
1577 /* 3181 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3220), // Rule ID 1956 //
1578 /* 3186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1579 /* 3189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1580 /* 3193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1581 /* 3197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1582 /* 3201 */ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1583 /* 3201 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1584 /* 3206 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1585 /* 3212 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1586 /* 3218 */ GIR_RootConstrainSelectedInstOperands,
1587 /* 3219 */ // GIR_Coverage, 1956,
1588 /* 3219 */ GIR_Done,
1589 /* 3220 */ // Label 171: @3220
1590 /* 3220 */ GIM_Reject,
1591 /* 3221 */ // Label 166: @3221
1592 /* 3221 */ GIM_Reject,
1593 /* 3222 */ // Label 159: @3222
1594 /* 3222 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3306),
1595 /* 3227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1596 /* 3230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1597 /* 3233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1598 /* 3237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1599 /* 3241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1600 /* 3245 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3290), // Rule ID 298 //
1601 /* 3250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
1602 /* 3253 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1603 /* 3253 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1604 /* 3258 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1605 /* 3264 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1606 /* 3270 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1607 /* 3276 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1608 /* 3282 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1609 /* 3288 */ GIR_RootConstrainSelectedInstOperands,
1610 /* 3289 */ // GIR_Coverage, 298,
1611 /* 3289 */ GIR_Done,
1612 /* 3290 */ // Label 173: @3290
1613 /* 3290 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3305), // Rule ID 371 //
1614 /* 3295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1615 /* 3298 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1616 /* 3298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1617 /* 3303 */ GIR_RootConstrainSelectedInstOperands,
1618 /* 3304 */ // GIR_Coverage, 371,
1619 /* 3304 */ GIR_Done,
1620 /* 3305 */ // Label 174: @3305
1621 /* 3305 */ GIM_Reject,
1622 /* 3306 */ // Label 172: @3306
1623 /* 3306 */ GIM_Reject,
1624 /* 3307 */ // Label 160: @3307
1625 /* 3307 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(3340), // Rule ID 928 //
1626 /* 3312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1627 /* 3315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1628 /* 3318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1629 /* 3321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1630 /* 3325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1631 /* 3329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1632 /* 3333 */ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1633 /* 3333 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1634 /* 3338 */ GIR_RootConstrainSelectedInstOperands,
1635 /* 3339 */ // GIR_Coverage, 928,
1636 /* 3339 */ GIR_Done,
1637 /* 3340 */ // Label 175: @3340
1638 /* 3340 */ GIM_Reject,
1639 /* 3341 */ // Label 161: @3341
1640 /* 3341 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(3372), // Rule ID 2057 //
1641 /* 3346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
1642 /* 3349 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1643 /* 3352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1644 /* 3355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1645 /* 3359 */ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1646 /* 3359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1647 /* 3364 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1648 /* 3370 */ GIR_RootConstrainSelectedInstOperands,
1649 /* 3371 */ // GIR_Coverage, 2057,
1650 /* 3371 */ GIR_Done,
1651 /* 3372 */ // Label 176: @3372
1652 /* 3372 */ GIM_Reject,
1653 /* 3373 */ // Label 162: @3373
1654 /* 3373 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(3406), // Rule ID 929 //
1655 /* 3378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1656 /* 3381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1657 /* 3384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1658 /* 3387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1659 /* 3391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1660 /* 3395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1661 /* 3399 */ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1662 /* 3399 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1663 /* 3404 */ GIR_RootConstrainSelectedInstOperands,
1664 /* 3405 */ // GIR_Coverage, 929,
1665 /* 3405 */ GIR_Done,
1666 /* 3406 */ // Label 177: @3406
1667 /* 3406 */ GIM_Reject,
1668 /* 3407 */ // Label 163: @3407
1669 /* 3407 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(3440), // Rule ID 930 //
1670 /* 3412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1671 /* 3415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1672 /* 3418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1673 /* 3421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1674 /* 3425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1675 /* 3429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1676 /* 3433 */ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1677 /* 3433 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1678 /* 3438 */ GIR_RootConstrainSelectedInstOperands,
1679 /* 3439 */ // GIR_Coverage, 930,
1680 /* 3439 */ GIR_Done,
1681 /* 3440 */ // Label 178: @3440
1682 /* 3440 */ GIM_Reject,
1683 /* 3441 */ // Label 164: @3441
1684 /* 3441 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(3474), // Rule ID 931 //
1685 /* 3446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1686 /* 3449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1687 /* 3452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1688 /* 3455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1689 /* 3459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1690 /* 3463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1691 /* 3467 */ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1692 /* 3467 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1693 /* 3472 */ GIR_RootConstrainSelectedInstOperands,
1694 /* 3473 */ // GIR_Coverage, 931,
1695 /* 3473 */ GIR_Done,
1696 /* 3474 */ // Label 179: @3474
1697 /* 3474 */ GIM_Reject,
1698 /* 3475 */ // Label 165: @3475
1699 /* 3475 */ GIM_Reject,
1700 /* 3476 */ // Label 3: @3476
1701 /* 3476 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 186*/ GIMT_Encode4(3744),
1702 /* 3487 */ /*GILLT_s32*//*Label 180*/ GIMT_Encode4(3519),
1703 /* 3491 */ /*GILLT_s64*//*Label 181*/ GIMT_Encode4(3574), GIMT_Encode4(0),
1704 /* 3499 */ /*GILLT_v16s8*//*Label 182*/ GIMT_Encode4(3608), GIMT_Encode4(0),
1705 /* 3507 */ /*GILLT_v8s16*//*Label 183*/ GIMT_Encode4(3642),
1706 /* 3511 */ /*GILLT_v4s32*//*Label 184*/ GIMT_Encode4(3676),
1707 /* 3515 */ /*GILLT_v2s64*//*Label 185*/ GIMT_Encode4(3710),
1708 /* 3519 */ // Label 180: @3519
1709 /* 3519 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3573),
1710 /* 3524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1711 /* 3527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1712 /* 3530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1713 /* 3534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1714 /* 3538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1715 /* 3542 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3557), // Rule ID 350 //
1716 /* 3547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1717 /* 3550 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1718 /* 3550 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1719 /* 3555 */ GIR_RootConstrainSelectedInstOperands,
1720 /* 3556 */ // GIR_Coverage, 350,
1721 /* 3556 */ GIR_Done,
1722 /* 3557 */ // Label 188: @3557
1723 /* 3557 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3572), // Rule ID 1195 //
1724 /* 3562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1725 /* 3565 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1726 /* 3565 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1727 /* 3570 */ GIR_RootConstrainSelectedInstOperands,
1728 /* 3571 */ // GIR_Coverage, 1195,
1729 /* 3571 */ GIR_Done,
1730 /* 3572 */ // Label 189: @3572
1731 /* 3572 */ GIM_Reject,
1732 /* 3573 */ // Label 187: @3573
1733 /* 3573 */ GIM_Reject,
1734 /* 3574 */ // Label 181: @3574
1735 /* 3574 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(3607), // Rule ID 365 //
1736 /* 3579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1737 /* 3582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1738 /* 3585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1739 /* 3588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1740 /* 3592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1741 /* 3596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1742 /* 3600 */ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1743 /* 3600 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1744 /* 3605 */ GIR_RootConstrainSelectedInstOperands,
1745 /* 3606 */ // GIR_Coverage, 365,
1746 /* 3606 */ GIR_Done,
1747 /* 3607 */ // Label 190: @3607
1748 /* 3607 */ GIM_Reject,
1749 /* 3608 */ // Label 182: @3608
1750 /* 3608 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(3641), // Rule ID 668 //
1751 /* 3613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1752 /* 3616 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1753 /* 3619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1754 /* 3622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1755 /* 3626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1756 /* 3630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1757 /* 3634 */ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1758 /* 3634 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1759 /* 3639 */ GIR_RootConstrainSelectedInstOperands,
1760 /* 3640 */ // GIR_Coverage, 668,
1761 /* 3640 */ GIR_Done,
1762 /* 3641 */ // Label 191: @3641
1763 /* 3641 */ GIM_Reject,
1764 /* 3642 */ // Label 183: @3642
1765 /* 3642 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(3675), // Rule ID 669 //
1766 /* 3647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1767 /* 3650 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1768 /* 3653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1769 /* 3656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1770 /* 3660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1771 /* 3664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1772 /* 3668 */ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1773 /* 3668 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1774 /* 3673 */ GIR_RootConstrainSelectedInstOperands,
1775 /* 3674 */ // GIR_Coverage, 669,
1776 /* 3674 */ GIR_Done,
1777 /* 3675 */ // Label 192: @3675
1778 /* 3675 */ GIM_Reject,
1779 /* 3676 */ // Label 184: @3676
1780 /* 3676 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(3709), // Rule ID 670 //
1781 /* 3681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1782 /* 3684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1783 /* 3687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1784 /* 3690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1785 /* 3694 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1786 /* 3698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1787 /* 3702 */ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1788 /* 3702 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1789 /* 3707 */ GIR_RootConstrainSelectedInstOperands,
1790 /* 3708 */ // GIR_Coverage, 670,
1791 /* 3708 */ GIR_Done,
1792 /* 3709 */ // Label 193: @3709
1793 /* 3709 */ GIM_Reject,
1794 /* 3710 */ // Label 185: @3710
1795 /* 3710 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(3743), // Rule ID 671 //
1796 /* 3715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1797 /* 3718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1798 /* 3721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1799 /* 3724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1800 /* 3728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1801 /* 3732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1802 /* 3736 */ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1803 /* 3736 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1804 /* 3741 */ GIR_RootConstrainSelectedInstOperands,
1805 /* 3742 */ // GIR_Coverage, 671,
1806 /* 3742 */ GIR_Done,
1807 /* 3743 */ // Label 194: @3743
1808 /* 3743 */ GIM_Reject,
1809 /* 3744 */ // Label 186: @3744
1810 /* 3744 */ GIM_Reject,
1811 /* 3745 */ // Label 4: @3745
1812 /* 3745 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 201*/ GIMT_Encode4(4013),
1813 /* 3756 */ /*GILLT_s32*//*Label 195*/ GIMT_Encode4(3788),
1814 /* 3760 */ /*GILLT_s64*//*Label 196*/ GIMT_Encode4(3843), GIMT_Encode4(0),
1815 /* 3768 */ /*GILLT_v16s8*//*Label 197*/ GIMT_Encode4(3877), GIMT_Encode4(0),
1816 /* 3776 */ /*GILLT_v8s16*//*Label 198*/ GIMT_Encode4(3911),
1817 /* 3780 */ /*GILLT_v4s32*//*Label 199*/ GIMT_Encode4(3945),
1818 /* 3784 */ /*GILLT_v2s64*//*Label 200*/ GIMT_Encode4(3979),
1819 /* 3788 */ // Label 195: @3788
1820 /* 3788 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(3842),
1821 /* 3793 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1822 /* 3796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1823 /* 3799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1824 /* 3803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1825 /* 3807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1826 /* 3811 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(3826), // Rule ID 351 //
1827 /* 3816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1828 /* 3819 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1829 /* 3819 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1830 /* 3824 */ GIR_RootConstrainSelectedInstOperands,
1831 /* 3825 */ // GIR_Coverage, 351,
1832 /* 3825 */ GIR_Done,
1833 /* 3826 */ // Label 203: @3826
1834 /* 3826 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(3841), // Rule ID 1196 //
1835 /* 3831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1836 /* 3834 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1837 /* 3834 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1838 /* 3839 */ GIR_RootConstrainSelectedInstOperands,
1839 /* 3840 */ // GIR_Coverage, 1196,
1840 /* 3840 */ GIR_Done,
1841 /* 3841 */ // Label 204: @3841
1842 /* 3841 */ GIM_Reject,
1843 /* 3842 */ // Label 202: @3842
1844 /* 3842 */ GIM_Reject,
1845 /* 3843 */ // Label 196: @3843
1846 /* 3843 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(3876), // Rule ID 366 //
1847 /* 3848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1848 /* 3851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1849 /* 3854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1850 /* 3857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1851 /* 3861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1852 /* 3865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1853 /* 3869 */ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1854 /* 3869 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1855 /* 3874 */ GIR_RootConstrainSelectedInstOperands,
1856 /* 3875 */ // GIR_Coverage, 366,
1857 /* 3875 */ GIR_Done,
1858 /* 3876 */ // Label 205: @3876
1859 /* 3876 */ GIM_Reject,
1860 /* 3877 */ // Label 197: @3877
1861 /* 3877 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(3910), // Rule ID 672 //
1862 /* 3882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1863 /* 3885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1864 /* 3888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1865 /* 3891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1866 /* 3895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1867 /* 3899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1868 /* 3903 */ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1869 /* 3903 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1870 /* 3908 */ GIR_RootConstrainSelectedInstOperands,
1871 /* 3909 */ // GIR_Coverage, 672,
1872 /* 3909 */ GIR_Done,
1873 /* 3910 */ // Label 206: @3910
1874 /* 3910 */ GIM_Reject,
1875 /* 3911 */ // Label 198: @3911
1876 /* 3911 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(3944), // Rule ID 673 //
1877 /* 3916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1878 /* 3919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1879 /* 3922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1880 /* 3925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1881 /* 3929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1882 /* 3933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1883 /* 3937 */ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1884 /* 3937 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1885 /* 3942 */ GIR_RootConstrainSelectedInstOperands,
1886 /* 3943 */ // GIR_Coverage, 673,
1887 /* 3943 */ GIR_Done,
1888 /* 3944 */ // Label 207: @3944
1889 /* 3944 */ GIM_Reject,
1890 /* 3945 */ // Label 199: @3945
1891 /* 3945 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(3978), // Rule ID 674 //
1892 /* 3950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1893 /* 3953 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1894 /* 3956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1895 /* 3959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1896 /* 3963 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1897 /* 3967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1898 /* 3971 */ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1899 /* 3971 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1900 /* 3976 */ GIR_RootConstrainSelectedInstOperands,
1901 /* 3977 */ // GIR_Coverage, 674,
1902 /* 3977 */ GIR_Done,
1903 /* 3978 */ // Label 208: @3978
1904 /* 3978 */ GIM_Reject,
1905 /* 3979 */ // Label 200: @3979
1906 /* 3979 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(4012), // Rule ID 675 //
1907 /* 3984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1908 /* 3987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1909 /* 3990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1910 /* 3993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1911 /* 3997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1912 /* 4001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1913 /* 4005 */ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1914 /* 4005 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1915 /* 4010 */ GIR_RootConstrainSelectedInstOperands,
1916 /* 4011 */ // GIR_Coverage, 675,
1917 /* 4011 */ GIR_Done,
1918 /* 4012 */ // Label 209: @4012
1919 /* 4012 */ GIM_Reject,
1920 /* 4013 */ // Label 201: @4013
1921 /* 4013 */ GIM_Reject,
1922 /* 4014 */ // Label 5: @4014
1923 /* 4014 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 216*/ GIMT_Encode4(4282),
1924 /* 4025 */ /*GILLT_s32*//*Label 210*/ GIMT_Encode4(4057),
1925 /* 4029 */ /*GILLT_s64*//*Label 211*/ GIMT_Encode4(4112), GIMT_Encode4(0),
1926 /* 4037 */ /*GILLT_v16s8*//*Label 212*/ GIMT_Encode4(4146), GIMT_Encode4(0),
1927 /* 4045 */ /*GILLT_v8s16*//*Label 213*/ GIMT_Encode4(4180),
1928 /* 4049 */ /*GILLT_v4s32*//*Label 214*/ GIMT_Encode4(4214),
1929 /* 4053 */ /*GILLT_v2s64*//*Label 215*/ GIMT_Encode4(4248),
1930 /* 4057 */ // Label 210: @4057
1931 /* 4057 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4111),
1932 /* 4062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1933 /* 4065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1934 /* 4068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1935 /* 4072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1936 /* 4076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1937 /* 4080 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4095), // Rule ID 352 //
1938 /* 4085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1939 /* 4088 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1940 /* 4088 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1941 /* 4093 */ GIR_RootConstrainSelectedInstOperands,
1942 /* 4094 */ // GIR_Coverage, 352,
1943 /* 4094 */ GIR_Done,
1944 /* 4095 */ // Label 218: @4095
1945 /* 4095 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4110), // Rule ID 1200 //
1946 /* 4100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1947 /* 4103 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1948 /* 4103 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1949 /* 4108 */ GIR_RootConstrainSelectedInstOperands,
1950 /* 4109 */ // GIR_Coverage, 1200,
1951 /* 4109 */ GIR_Done,
1952 /* 4110 */ // Label 219: @4110
1953 /* 4110 */ GIM_Reject,
1954 /* 4111 */ // Label 217: @4111
1955 /* 4111 */ GIM_Reject,
1956 /* 4112 */ // Label 211: @4112
1957 /* 4112 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(4145), // Rule ID 367 //
1958 /* 4117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1959 /* 4120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1960 /* 4123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1961 /* 4126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1962 /* 4130 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1963 /* 4134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1964 /* 4138 */ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1965 /* 4138 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1966 /* 4143 */ GIR_RootConstrainSelectedInstOperands,
1967 /* 4144 */ // GIR_Coverage, 367,
1968 /* 4144 */ GIR_Done,
1969 /* 4145 */ // Label 220: @4145
1970 /* 4145 */ GIM_Reject,
1971 /* 4146 */ // Label 212: @4146
1972 /* 4146 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(4179), // Rule ID 908 //
1973 /* 4151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1974 /* 4154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1975 /* 4157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1976 /* 4160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1977 /* 4164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1978 /* 4168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1979 /* 4172 */ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1980 /* 4172 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
1981 /* 4177 */ GIR_RootConstrainSelectedInstOperands,
1982 /* 4178 */ // GIR_Coverage, 908,
1983 /* 4178 */ GIR_Done,
1984 /* 4179 */ // Label 221: @4179
1985 /* 4179 */ GIM_Reject,
1986 /* 4180 */ // Label 213: @4180
1987 /* 4180 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(4213), // Rule ID 909 //
1988 /* 4185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1989 /* 4188 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1990 /* 4191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1991 /* 4194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1992 /* 4198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1993 /* 4202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1994 /* 4206 */ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1995 /* 4206 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
1996 /* 4211 */ GIR_RootConstrainSelectedInstOperands,
1997 /* 4212 */ // GIR_Coverage, 909,
1998 /* 4212 */ GIR_Done,
1999 /* 4213 */ // Label 222: @4213
2000 /* 4213 */ GIM_Reject,
2001 /* 4214 */ // Label 214: @4214
2002 /* 4214 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(4247), // Rule ID 910 //
2003 /* 4219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2004 /* 4222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2005 /* 4225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2006 /* 4228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2007 /* 4232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2008 /* 4236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2009 /* 4240 */ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2010 /* 4240 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
2011 /* 4245 */ GIR_RootConstrainSelectedInstOperands,
2012 /* 4246 */ // GIR_Coverage, 910,
2013 /* 4246 */ GIR_Done,
2014 /* 4247 */ // Label 223: @4247
2015 /* 4247 */ GIM_Reject,
2016 /* 4248 */ // Label 215: @4248
2017 /* 4248 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(4281), // Rule ID 911 //
2018 /* 4253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2019 /* 4256 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2020 /* 4259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2021 /* 4262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2022 /* 4266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2023 /* 4270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2024 /* 4274 */ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2025 /* 4274 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
2026 /* 4279 */ GIR_RootConstrainSelectedInstOperands,
2027 /* 4280 */ // GIR_Coverage, 911,
2028 /* 4280 */ GIR_Done,
2029 /* 4281 */ // Label 224: @4281
2030 /* 4281 */ GIM_Reject,
2031 /* 4282 */ // Label 216: @4282
2032 /* 4282 */ GIM_Reject,
2033 /* 4283 */ // Label 6: @4283
2034 /* 4283 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 231*/ GIMT_Encode4(4551),
2035 /* 4294 */ /*GILLT_s32*//*Label 225*/ GIMT_Encode4(4326),
2036 /* 4298 */ /*GILLT_s64*//*Label 226*/ GIMT_Encode4(4381), GIMT_Encode4(0),
2037 /* 4306 */ /*GILLT_v16s8*//*Label 227*/ GIMT_Encode4(4415), GIMT_Encode4(0),
2038 /* 4314 */ /*GILLT_v8s16*//*Label 228*/ GIMT_Encode4(4449),
2039 /* 4318 */ /*GILLT_v4s32*//*Label 229*/ GIMT_Encode4(4483),
2040 /* 4322 */ /*GILLT_v2s64*//*Label 230*/ GIMT_Encode4(4517),
2041 /* 4326 */ // Label 225: @4326
2042 /* 4326 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4380),
2043 /* 4331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2044 /* 4334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2045 /* 4337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2046 /* 4341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2047 /* 4345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2048 /* 4349 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4364), // Rule ID 353 //
2049 /* 4354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
2050 /* 4357 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2051 /* 4357 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2052 /* 4362 */ GIR_RootConstrainSelectedInstOperands,
2053 /* 4363 */ // GIR_Coverage, 353,
2054 /* 4363 */ GIR_Done,
2055 /* 4364 */ // Label 233: @4364
2056 /* 4364 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4379), // Rule ID 1201 //
2057 /* 4369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2058 /* 4372 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2059 /* 4372 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2060 /* 4377 */ GIR_RootConstrainSelectedInstOperands,
2061 /* 4378 */ // GIR_Coverage, 1201,
2062 /* 4378 */ GIR_Done,
2063 /* 4379 */ // Label 234: @4379
2064 /* 4379 */ GIM_Reject,
2065 /* 4380 */ // Label 232: @4380
2066 /* 4380 */ GIM_Reject,
2067 /* 4381 */ // Label 226: @4381
2068 /* 4381 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4414), // Rule ID 368 //
2069 /* 4386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
2070 /* 4389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2071 /* 4392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2072 /* 4395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2073 /* 4399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2074 /* 4403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2075 /* 4407 */ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2076 /* 4407 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2077 /* 4412 */ GIR_RootConstrainSelectedInstOperands,
2078 /* 4413 */ // GIR_Coverage, 368,
2079 /* 4413 */ GIR_Done,
2080 /* 4414 */ // Label 235: @4414
2081 /* 4414 */ GIM_Reject,
2082 /* 4415 */ // Label 227: @4415
2083 /* 4415 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4448), // Rule ID 912 //
2084 /* 4420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2085 /* 4423 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2086 /* 4426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2087 /* 4429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2088 /* 4433 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2089 /* 4437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2090 /* 4441 */ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2091 /* 4441 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2092 /* 4446 */ GIR_RootConstrainSelectedInstOperands,
2093 /* 4447 */ // GIR_Coverage, 912,
2094 /* 4447 */ GIR_Done,
2095 /* 4448 */ // Label 236: @4448
2096 /* 4448 */ GIM_Reject,
2097 /* 4449 */ // Label 228: @4449
2098 /* 4449 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4482), // Rule ID 913 //
2099 /* 4454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2100 /* 4457 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2101 /* 4460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2102 /* 4463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2103 /* 4467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2104 /* 4471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2105 /* 4475 */ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2106 /* 4475 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2107 /* 4480 */ GIR_RootConstrainSelectedInstOperands,
2108 /* 4481 */ // GIR_Coverage, 913,
2109 /* 4481 */ GIR_Done,
2110 /* 4482 */ // Label 237: @4482
2111 /* 4482 */ GIM_Reject,
2112 /* 4483 */ // Label 229: @4483
2113 /* 4483 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4516), // Rule ID 914 //
2114 /* 4488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2115 /* 4491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2116 /* 4494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2117 /* 4497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2118 /* 4501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2119 /* 4505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2120 /* 4509 */ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2121 /* 4509 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2122 /* 4514 */ GIR_RootConstrainSelectedInstOperands,
2123 /* 4515 */ // GIR_Coverage, 914,
2124 /* 4515 */ GIR_Done,
2125 /* 4516 */ // Label 238: @4516
2126 /* 4516 */ GIM_Reject,
2127 /* 4517 */ // Label 230: @4517
2128 /* 4517 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4550), // Rule ID 915 //
2129 /* 4522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2130 /* 4525 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2131 /* 4528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2132 /* 4531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2133 /* 4535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2134 /* 4539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2135 /* 4543 */ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2136 /* 4543 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2137 /* 4548 */ GIR_RootConstrainSelectedInstOperands,
2138 /* 4549 */ // GIR_Coverage, 915,
2139 /* 4549 */ GIR_Done,
2140 /* 4550 */ // Label 239: @4550
2141 /* 4550 */ GIM_Reject,
2142 /* 4551 */ // Label 231: @4551
2143 /* 4551 */ GIM_Reject,
2144 /* 4552 */ // Label 7: @4552
2145 /* 4552 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 246*/ GIMT_Encode4(5107),
2146 /* 4563 */ /*GILLT_s32*//*Label 240*/ GIMT_Encode4(4595),
2147 /* 4567 */ /*GILLT_s64*//*Label 241*/ GIMT_Encode4(4869), GIMT_Encode4(0),
2148 /* 4575 */ /*GILLT_v16s8*//*Label 242*/ GIMT_Encode4(4971), GIMT_Encode4(0),
2149 /* 4583 */ /*GILLT_v8s16*//*Label 243*/ GIMT_Encode4(5005),
2150 /* 4587 */ /*GILLT_v4s32*//*Label 244*/ GIMT_Encode4(5039),
2151 /* 4591 */ /*GILLT_v2s64*//*Label 245*/ GIMT_Encode4(5073),
2152 /* 4595 */ // Label 240: @4595
2153 /* 4595 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(4868),
2154 /* 4600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2155 /* 4603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2156 /* 4606 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4648), // Rule ID 41 //
2157 /* 4611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2158 /* 4614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2159 /* 4618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2160 /* 4622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2161 /* 4626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2162 /* 4630 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2163 /* 4634 */ // MIs[1] Operand 1
2164 /* 4634 */ // No operand predicates
2165 /* 4634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2166 /* 4636 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2167 /* 4636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2168 /* 4639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2169 /* 4641 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2170 /* 4643 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2171 /* 4646 */ GIR_RootConstrainSelectedInstOperands,
2172 /* 4647 */ // GIR_Coverage, 41,
2173 /* 4647 */ GIR_EraseRootFromParent_Done,
2174 /* 4648 */ // Label 248: @4648
2175 /* 4648 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4690), // Rule ID 2299 //
2176 /* 4653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2177 /* 4656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2178 /* 4660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2179 /* 4664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2180 /* 4668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2181 /* 4672 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2182 /* 4676 */ // MIs[1] Operand 1
2183 /* 4676 */ // No operand predicates
2184 /* 4676 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2185 /* 4678 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2186 /* 4678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2187 /* 4681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2188 /* 4683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2189 /* 4685 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2190 /* 4688 */ GIR_RootConstrainSelectedInstOperands,
2191 /* 4689 */ // GIR_Coverage, 2299,
2192 /* 4689 */ GIR_EraseRootFromParent_Done,
2193 /* 4690 */ // Label 249: @4690
2194 /* 4690 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4732), // Rule ID 2463 //
2195 /* 4695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2196 /* 4698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2197 /* 4702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2198 /* 4706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2199 /* 4710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2200 /* 4714 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2201 /* 4718 */ // MIs[1] Operand 1
2202 /* 4718 */ // No operand predicates
2203 /* 4718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2204 /* 4720 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2205 /* 4720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2206 /* 4723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2207 /* 4725 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2208 /* 4727 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2209 /* 4730 */ GIR_RootConstrainSelectedInstOperands,
2210 /* 4731 */ // GIR_Coverage, 2463,
2211 /* 4731 */ GIR_EraseRootFromParent_Done,
2212 /* 4732 */ // Label 250: @4732
2213 /* 4732 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4759), // Rule ID 51 //
2214 /* 4737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2215 /* 4740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2216 /* 4744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2217 /* 4748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2218 /* 4752 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2219 /* 4752 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2220 /* 4757 */ GIR_RootConstrainSelectedInstOperands,
2221 /* 4758 */ // GIR_Coverage, 51,
2222 /* 4758 */ GIR_Done,
2223 /* 4759 */ // Label 251: @4759
2224 /* 4759 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4786), // Rule ID 1085 //
2225 /* 4764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2226 /* 4767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2227 /* 4771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2228 /* 4775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2229 /* 4779 */ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2230 /* 4779 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2231 /* 4784 */ GIR_RootConstrainSelectedInstOperands,
2232 /* 4785 */ // GIR_Coverage, 1085,
2233 /* 4785 */ GIR_Done,
2234 /* 4786 */ // Label 252: @4786
2235 /* 4786 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4813), // Rule ID 1101 //
2236 /* 4791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2237 /* 4794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2238 /* 4798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2239 /* 4802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2240 /* 4806 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2241 /* 4806 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2242 /* 4811 */ GIR_RootConstrainSelectedInstOperands,
2243 /* 4812 */ // GIR_Coverage, 1101,
2244 /* 4812 */ GIR_Done,
2245 /* 4813 */ // Label 253: @4813
2246 /* 4813 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4840), // Rule ID 1193 //
2247 /* 4818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2248 /* 4821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2249 /* 4825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2250 /* 4829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2251 /* 4833 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2252 /* 4833 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2253 /* 4838 */ GIR_RootConstrainSelectedInstOperands,
2254 /* 4839 */ // GIR_Coverage, 1193,
2255 /* 4839 */ GIR_Done,
2256 /* 4840 */ // Label 254: @4840
2257 /* 4840 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4867), // Rule ID 1955 //
2258 /* 4845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2259 /* 4848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2260 /* 4852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2261 /* 4856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2262 /* 4860 */ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2263 /* 4860 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2264 /* 4865 */ GIR_RootConstrainSelectedInstOperands,
2265 /* 4866 */ // GIR_Coverage, 1955,
2266 /* 4866 */ GIR_Done,
2267 /* 4867 */ // Label 255: @4867
2268 /* 4867 */ GIM_Reject,
2269 /* 4868 */ // Label 247: @4868
2270 /* 4868 */ GIM_Reject,
2271 /* 4869 */ // Label 241: @4869
2272 /* 4869 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4970),
2273 /* 4874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2274 /* 4877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2275 /* 4880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2276 /* 4884 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4946), // Rule ID 293 //
2277 /* 4889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
2278 /* 4892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2279 /* 4896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2280 /* 4900 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2281 /* 4904 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2282 /* 4908 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2283 /* 4913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2284 /* 4918 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2285 /* 4929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2286 /* 4931 */ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2287 /* 4931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2288 /* 4934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2289 /* 4936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2290 /* 4940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2291 /* 4944 */ GIR_RootConstrainSelectedInstOperands,
2292 /* 4945 */ // GIR_Coverage, 293,
2293 /* 4945 */ GIR_EraseRootFromParent_Done,
2294 /* 4946 */ // Label 257: @4946
2295 /* 4946 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4969), // Rule ID 230 //
2296 /* 4951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2297 /* 4954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2298 /* 4958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2299 /* 4962 */ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2300 /* 4962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2301 /* 4967 */ GIR_RootConstrainSelectedInstOperands,
2302 /* 4968 */ // GIR_Coverage, 230,
2303 /* 4968 */ GIR_Done,
2304 /* 4969 */ // Label 258: @4969
2305 /* 4969 */ GIM_Reject,
2306 /* 4970 */ // Label 256: @4970
2307 /* 4970 */ GIM_Reject,
2308 /* 4971 */ // Label 242: @4971
2309 /* 4971 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(5004), // Rule ID 539 //
2310 /* 4976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2311 /* 4979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2312 /* 4982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2313 /* 4985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2314 /* 4989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2315 /* 4993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2316 /* 4997 */ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2317 /* 4997 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2318 /* 5002 */ GIR_RootConstrainSelectedInstOperands,
2319 /* 5003 */ // GIR_Coverage, 539,
2320 /* 5003 */ GIR_Done,
2321 /* 5004 */ // Label 259: @5004
2322 /* 5004 */ GIM_Reject,
2323 /* 5005 */ // Label 243: @5005
2324 /* 5005 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5038), // Rule ID 540 //
2325 /* 5010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2326 /* 5013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2327 /* 5016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2328 /* 5019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2329 /* 5023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2330 /* 5027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2331 /* 5031 */ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2332 /* 5031 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2333 /* 5036 */ GIR_RootConstrainSelectedInstOperands,
2334 /* 5037 */ // GIR_Coverage, 540,
2335 /* 5037 */ GIR_Done,
2336 /* 5038 */ // Label 260: @5038
2337 /* 5038 */ GIM_Reject,
2338 /* 5039 */ // Label 244: @5039
2339 /* 5039 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5072), // Rule ID 541 //
2340 /* 5044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2341 /* 5047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2342 /* 5050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2343 /* 5053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2344 /* 5057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2345 /* 5061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2346 /* 5065 */ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2347 /* 5065 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2348 /* 5070 */ GIR_RootConstrainSelectedInstOperands,
2349 /* 5071 */ // GIR_Coverage, 541,
2350 /* 5071 */ GIR_Done,
2351 /* 5072 */ // Label 261: @5072
2352 /* 5072 */ GIM_Reject,
2353 /* 5073 */ // Label 245: @5073
2354 /* 5073 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(5106), // Rule ID 542 //
2355 /* 5078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2356 /* 5081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2357 /* 5084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2358 /* 5087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2359 /* 5091 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2360 /* 5095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2361 /* 5099 */ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2362 /* 5099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2363 /* 5104 */ GIR_RootConstrainSelectedInstOperands,
2364 /* 5105 */ // GIR_Coverage, 542,
2365 /* 5105 */ GIR_Done,
2366 /* 5106 */ // Label 262: @5106
2367 /* 5106 */ GIM_Reject,
2368 /* 5107 */ // Label 246: @5107
2369 /* 5107 */ GIM_Reject,
2370 /* 5108 */ // Label 8: @5108
2371 /* 5108 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 269*/ GIMT_Encode4(5511),
2372 /* 5119 */ /*GILLT_s32*//*Label 263*/ GIMT_Encode4(5151),
2373 /* 5123 */ /*GILLT_s64*//*Label 264*/ GIMT_Encode4(5341), GIMT_Encode4(0),
2374 /* 5131 */ /*GILLT_v16s8*//*Label 265*/ GIMT_Encode4(5375), GIMT_Encode4(0),
2375 /* 5139 */ /*GILLT_v8s16*//*Label 266*/ GIMT_Encode4(5409),
2376 /* 5143 */ /*GILLT_v4s32*//*Label 267*/ GIMT_Encode4(5443),
2377 /* 5147 */ /*GILLT_v2s64*//*Label 268*/ GIMT_Encode4(5477),
2378 /* 5151 */ // Label 263: @5151
2379 /* 5151 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5340),
2380 /* 5156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2381 /* 5159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2382 /* 5162 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5204), // Rule ID 42 //
2383 /* 5167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2384 /* 5170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2385 /* 5174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2386 /* 5178 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2387 /* 5182 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2388 /* 5186 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2389 /* 5190 */ // MIs[1] Operand 1
2390 /* 5190 */ // No operand predicates
2391 /* 5190 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2392 /* 5192 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2393 /* 5192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2394 /* 5195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2395 /* 5197 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2396 /* 5199 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2397 /* 5202 */ GIR_RootConstrainSelectedInstOperands,
2398 /* 5203 */ // GIR_Coverage, 42,
2399 /* 5203 */ GIR_EraseRootFromParent_Done,
2400 /* 5204 */ // Label 271: @5204
2401 /* 5204 */ GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5231), // Rule ID 52 //
2402 /* 5209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2403 /* 5212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2404 /* 5216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2405 /* 5220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2406 /* 5224 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2407 /* 5224 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2408 /* 5229 */ GIR_RootConstrainSelectedInstOperands,
2409 /* 5230 */ // GIR_Coverage, 52,
2410 /* 5230 */ GIR_Done,
2411 /* 5231 */ // Label 272: @5231
2412 /* 5231 */ GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5258), // Rule ID 1087 //
2413 /* 5236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2414 /* 5239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2415 /* 5243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2416 /* 5247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2417 /* 5251 */ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2418 /* 5251 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2419 /* 5256 */ GIR_RootConstrainSelectedInstOperands,
2420 /* 5257 */ // GIR_Coverage, 1087,
2421 /* 5257 */ GIR_Done,
2422 /* 5258 */ // Label 273: @5258
2423 /* 5258 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5285), // Rule ID 1102 //
2424 /* 5263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2425 /* 5266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2426 /* 5270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2427 /* 5274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2428 /* 5278 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2429 /* 5278 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2430 /* 5283 */ GIR_RootConstrainSelectedInstOperands,
2431 /* 5284 */ // GIR_Coverage, 1102,
2432 /* 5284 */ GIR_Done,
2433 /* 5285 */ // Label 274: @5285
2434 /* 5285 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5312), // Rule ID 1206 //
2435 /* 5290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2436 /* 5293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2437 /* 5297 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2438 /* 5301 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2439 /* 5305 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2440 /* 5305 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2441 /* 5310 */ GIR_RootConstrainSelectedInstOperands,
2442 /* 5311 */ // GIR_Coverage, 1206,
2443 /* 5311 */ GIR_Done,
2444 /* 5312 */ // Label 275: @5312
2445 /* 5312 */ GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5339), // Rule ID 1957 //
2446 /* 5317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2447 /* 5320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2448 /* 5324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2449 /* 5328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2450 /* 5332 */ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2451 /* 5332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2452 /* 5337 */ GIR_RootConstrainSelectedInstOperands,
2453 /* 5338 */ // GIR_Coverage, 1957,
2454 /* 5338 */ GIR_Done,
2455 /* 5339 */ // Label 276: @5339
2456 /* 5339 */ GIM_Reject,
2457 /* 5340 */ // Label 270: @5340
2458 /* 5340 */ GIM_Reject,
2459 /* 5341 */ // Label 264: @5341
2460 /* 5341 */ GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5374), // Rule ID 231 //
2461 /* 5346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2462 /* 5349 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2463 /* 5352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2464 /* 5355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2465 /* 5359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2466 /* 5363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2467 /* 5367 */ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2468 /* 5367 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2469 /* 5372 */ GIR_RootConstrainSelectedInstOperands,
2470 /* 5373 */ // GIR_Coverage, 231,
2471 /* 5373 */ GIR_Done,
2472 /* 5374 */ // Label 277: @5374
2473 /* 5374 */ GIM_Reject,
2474 /* 5375 */ // Label 265: @5375
2475 /* 5375 */ GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5408), // Rule ID 945 //
2476 /* 5380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2477 /* 5383 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2478 /* 5386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2479 /* 5389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2480 /* 5393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2481 /* 5397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2482 /* 5401 */ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2483 /* 5401 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2484 /* 5406 */ GIR_RootConstrainSelectedInstOperands,
2485 /* 5407 */ // GIR_Coverage, 945,
2486 /* 5407 */ GIR_Done,
2487 /* 5408 */ // Label 278: @5408
2488 /* 5408 */ GIM_Reject,
2489 /* 5409 */ // Label 266: @5409
2490 /* 5409 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5442), // Rule ID 946 //
2491 /* 5414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2492 /* 5417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2493 /* 5420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2494 /* 5423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2495 /* 5427 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2496 /* 5431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2497 /* 5435 */ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2498 /* 5435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2499 /* 5440 */ GIR_RootConstrainSelectedInstOperands,
2500 /* 5441 */ // GIR_Coverage, 946,
2501 /* 5441 */ GIR_Done,
2502 /* 5442 */ // Label 279: @5442
2503 /* 5442 */ GIM_Reject,
2504 /* 5443 */ // Label 267: @5443
2505 /* 5443 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5476), // Rule ID 947 //
2506 /* 5448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2507 /* 5451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2508 /* 5454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2509 /* 5457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2510 /* 5461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2511 /* 5465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2512 /* 5469 */ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2513 /* 5469 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2514 /* 5474 */ GIR_RootConstrainSelectedInstOperands,
2515 /* 5475 */ // GIR_Coverage, 947,
2516 /* 5475 */ GIR_Done,
2517 /* 5476 */ // Label 280: @5476
2518 /* 5476 */ GIM_Reject,
2519 /* 5477 */ // Label 268: @5477
2520 /* 5477 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5510), // Rule ID 948 //
2521 /* 5482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2522 /* 5485 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2523 /* 5488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2524 /* 5491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2525 /* 5495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2526 /* 5499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2527 /* 5503 */ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2528 /* 5503 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2529 /* 5508 */ GIR_RootConstrainSelectedInstOperands,
2530 /* 5509 */ // GIR_Coverage, 948,
2531 /* 5509 */ GIR_Done,
2532 /* 5510 */ // Label 281: @5510
2533 /* 5510 */ GIM_Reject,
2534 /* 5511 */ // Label 269: @5511
2535 /* 5511 */ GIM_Reject,
2536 /* 5512 */ // Label 9: @5512
2537 /* 5512 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 288*/ GIMT_Encode4(6403),
2538 /* 5523 */ /*GILLT_s32*//*Label 282*/ GIMT_Encode4(5555),
2539 /* 5527 */ /*GILLT_s64*//*Label 283*/ GIMT_Encode4(6172), GIMT_Encode4(0),
2540 /* 5535 */ /*GILLT_v16s8*//*Label 284*/ GIMT_Encode4(6267), GIMT_Encode4(0),
2541 /* 5543 */ /*GILLT_v8s16*//*Label 285*/ GIMT_Encode4(6301),
2542 /* 5547 */ /*GILLT_v4s32*//*Label 286*/ GIMT_Encode4(6335),
2543 /* 5551 */ /*GILLT_v2s64*//*Label 287*/ GIMT_Encode4(6369),
2544 /* 5555 */ // Label 282: @5555
2545 /* 5555 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(6171),
2546 /* 5560 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2547 /* 5563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2548 /* 5566 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(5625), // Rule ID 54 //
2549 /* 5571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2550 /* 5574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2551 /* 5578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2552 /* 5582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2553 /* 5586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2554 /* 5590 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2555 /* 5594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2556 /* 5599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2557 /* 5604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2558 /* 5608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2559 /* 5610 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2560 /* 5610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2561 /* 5613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2562 /* 5615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2563 /* 5619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2564 /* 5623 */ GIR_RootConstrainSelectedInstOperands,
2565 /* 5624 */ // GIR_Coverage, 54,
2566 /* 5624 */ GIR_EraseRootFromParent_Done,
2567 /* 5625 */ // Label 290: @5625
2568 /* 5625 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5684), // Rule ID 1104 //
2569 /* 5630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2570 /* 5633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2571 /* 5637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2572 /* 5641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2573 /* 5645 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2574 /* 5649 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2575 /* 5653 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2576 /* 5658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2577 /* 5663 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2578 /* 5667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2579 /* 5669 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2580 /* 5669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2581 /* 5672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2582 /* 5674 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2583 /* 5678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2584 /* 5682 */ GIR_RootConstrainSelectedInstOperands,
2585 /* 5683 */ // GIR_Coverage, 1104,
2586 /* 5683 */ GIR_EraseRootFromParent_Done,
2587 /* 5684 */ // Label 291: @5684
2588 /* 5684 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5743), // Rule ID 1205 //
2589 /* 5689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2590 /* 5692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2591 /* 5696 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2592 /* 5700 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2593 /* 5704 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2594 /* 5708 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2595 /* 5712 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2596 /* 5717 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2597 /* 5722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2598 /* 5726 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2599 /* 5728 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2600 /* 5728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2601 /* 5731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2602 /* 5733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2603 /* 5737 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2604 /* 5741 */ GIR_RootConstrainSelectedInstOperands,
2605 /* 5742 */ // GIR_Coverage, 1205,
2606 /* 5742 */ GIR_EraseRootFromParent_Done,
2607 /* 5743 */ // Label 292: @5743
2608 /* 5743 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5772), // Rule ID 1232 //
2609 /* 5748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2610 /* 5751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2611 /* 5755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2612 /* 5759 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2613 /* 5763 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2614 /* 5763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2615 /* 5766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2616 /* 5768 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2617 /* 5770 */ GIR_RootConstrainSelectedInstOperands,
2618 /* 5771 */ // GIR_Coverage, 1232,
2619 /* 5771 */ GIR_EraseRootFromParent_Done,
2620 /* 5772 */ // Label 293: @5772
2621 /* 5772 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5801), // Rule ID 1086 //
2622 /* 5777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2623 /* 5780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2624 /* 5784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2625 /* 5788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2626 /* 5792 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2627 /* 5792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2628 /* 5795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2629 /* 5797 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2630 /* 5799 */ GIR_RootConstrainSelectedInstOperands,
2631 /* 5800 */ // GIR_Coverage, 1086,
2632 /* 5800 */ GIR_EraseRootFromParent_Done,
2633 /* 5801 */ // Label 294: @5801
2634 /* 5801 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(5836), // Rule ID 1420 //
2635 /* 5806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2636 /* 5809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2637 /* 5813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2638 /* 5817 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2639 /* 5821 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2640 /* 5821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2641 /* 5824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2642 /* 5826 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2643 /* 5828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2644 /* 5834 */ GIR_RootConstrainSelectedInstOperands,
2645 /* 5835 */ // GIR_Coverage, 1420,
2646 /* 5835 */ GIR_EraseRootFromParent_Done,
2647 /* 5836 */ // Label 295: @5836
2648 /* 5836 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(5865), // Rule ID 1952 //
2649 /* 5841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2650 /* 5844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2651 /* 5848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2652 /* 5852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2653 /* 5856 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2654 /* 5856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2655 /* 5859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2656 /* 5861 */ GIR_RootToRootCopy, /*OpIdx*/1, // r
2657 /* 5863 */ GIR_RootConstrainSelectedInstOperands,
2658 /* 5864 */ // GIR_Coverage, 1952,
2659 /* 5864 */ GIR_EraseRootFromParent_Done,
2660 /* 5865 */ // Label 296: @5865
2661 /* 5865 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(5894), // Rule ID 2294 //
2662 /* 5870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2663 /* 5873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2664 /* 5877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2665 /* 5881 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2666 /* 5885 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2667 /* 5885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2668 /* 5888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2669 /* 5890 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2670 /* 5892 */ GIR_RootConstrainSelectedInstOperands,
2671 /* 5893 */ // GIR_Coverage, 2294,
2672 /* 5893 */ GIR_EraseRootFromParent_Done,
2673 /* 5894 */ // Label 297: @5894
2674 /* 5894 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(5929), // Rule ID 2295 //
2675 /* 5899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2676 /* 5902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2677 /* 5906 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2678 /* 5910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2679 /* 5914 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2680 /* 5914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2681 /* 5917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2682 /* 5919 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2683 /* 5921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2684 /* 5927 */ GIR_RootConstrainSelectedInstOperands,
2685 /* 5928 */ // GIR_Coverage, 2295,
2686 /* 5928 */ GIR_EraseRootFromParent_Done,
2687 /* 5929 */ // Label 298: @5929
2688 /* 5929 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(5958), // Rule ID 2466 //
2689 /* 5934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2690 /* 5937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2691 /* 5941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2692 /* 5945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2693 /* 5949 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2694 /* 5949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2695 /* 5952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2696 /* 5954 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2697 /* 5956 */ GIR_RootConstrainSelectedInstOperands,
2698 /* 5957 */ // GIR_Coverage, 2466,
2699 /* 5957 */ GIR_EraseRootFromParent_Done,
2700 /* 5958 */ // Label 299: @5958
2701 /* 5958 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(5993), // Rule ID 2467 //
2702 /* 5963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2703 /* 5966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2704 /* 5970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2705 /* 5974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2706 /* 5978 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2707 /* 5978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2708 /* 5981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2709 /* 5983 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2710 /* 5985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2711 /* 5991 */ GIR_RootConstrainSelectedInstOperands,
2712 /* 5992 */ // GIR_Coverage, 2467,
2713 /* 5992 */ GIR_EraseRootFromParent_Done,
2714 /* 5993 */ // Label 300: @5993
2715 /* 5993 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6035), // Rule ID 43 //
2716 /* 5998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2717 /* 6001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2718 /* 6005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2719 /* 6009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2720 /* 6013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2721 /* 6017 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2722 /* 6021 */ // MIs[1] Operand 1
2723 /* 6021 */ // No operand predicates
2724 /* 6021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2725 /* 6023 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2726 /* 6023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2727 /* 6026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2728 /* 6028 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2729 /* 6030 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2730 /* 6033 */ GIR_RootConstrainSelectedInstOperands,
2731 /* 6034 */ // GIR_Coverage, 43,
2732 /* 6034 */ GIR_EraseRootFromParent_Done,
2733 /* 6035 */ // Label 301: @6035
2734 /* 6035 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6062), // Rule ID 53 //
2735 /* 6040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2736 /* 6043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2737 /* 6047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2738 /* 6051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2739 /* 6055 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2740 /* 6055 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2741 /* 6060 */ GIR_RootConstrainSelectedInstOperands,
2742 /* 6061 */ // GIR_Coverage, 53,
2743 /* 6061 */ GIR_Done,
2744 /* 6062 */ // Label 302: @6062
2745 /* 6062 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6089), // Rule ID 1089 //
2746 /* 6067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2747 /* 6070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2748 /* 6074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2749 /* 6078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2750 /* 6082 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2751 /* 6082 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2752 /* 6087 */ GIR_RootConstrainSelectedInstOperands,
2753 /* 6088 */ // GIR_Coverage, 1089,
2754 /* 6088 */ GIR_Done,
2755 /* 6089 */ // Label 303: @6089
2756 /* 6089 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6116), // Rule ID 1103 //
2757 /* 6094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2758 /* 6097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2759 /* 6101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2760 /* 6105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2761 /* 6109 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2762 /* 6109 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2763 /* 6114 */ GIR_RootConstrainSelectedInstOperands,
2764 /* 6115 */ // GIR_Coverage, 1103,
2765 /* 6115 */ GIR_Done,
2766 /* 6116 */ // Label 304: @6116
2767 /* 6116 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(6143), // Rule ID 1209 //
2768 /* 6121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2769 /* 6124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2770 /* 6128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2771 /* 6132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2772 /* 6136 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2773 /* 6136 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2774 /* 6141 */ GIR_RootConstrainSelectedInstOperands,
2775 /* 6142 */ // GIR_Coverage, 1209,
2776 /* 6142 */ GIR_Done,
2777 /* 6143 */ // Label 305: @6143
2778 /* 6143 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(6170), // Rule ID 1959 //
2779 /* 6148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2780 /* 6151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2781 /* 6155 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2782 /* 6159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2783 /* 6163 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2784 /* 6163 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2785 /* 6168 */ GIR_RootConstrainSelectedInstOperands,
2786 /* 6169 */ // GIR_Coverage, 1959,
2787 /* 6169 */ GIR_Done,
2788 /* 6170 */ // Label 306: @6170
2789 /* 6170 */ GIM_Reject,
2790 /* 6171 */ // Label 289: @6171
2791 /* 6171 */ GIM_Reject,
2792 /* 6172 */ // Label 283: @6172
2793 /* 6172 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6266),
2794 /* 6177 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2795 /* 6180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2796 /* 6183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2797 /* 6187 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6242), // Rule ID 233 //
2798 /* 6192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2799 /* 6195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2800 /* 6199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2801 /* 6203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2802 /* 6207 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2803 /* 6211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2804 /* 6216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2805 /* 6221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2806 /* 6225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2807 /* 6227 */ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2808 /* 6227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2809 /* 6230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2810 /* 6232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2811 /* 6236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2812 /* 6240 */ GIR_RootConstrainSelectedInstOperands,
2813 /* 6241 */ // GIR_Coverage, 233,
2814 /* 6241 */ GIR_EraseRootFromParent_Done,
2815 /* 6242 */ // Label 308: @6242
2816 /* 6242 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6265), // Rule ID 232 //
2817 /* 6247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2818 /* 6250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2819 /* 6254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2820 /* 6258 */ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2821 /* 6258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2822 /* 6263 */ GIR_RootConstrainSelectedInstOperands,
2823 /* 6264 */ // GIR_Coverage, 232,
2824 /* 6264 */ GIR_Done,
2825 /* 6265 */ // Label 309: @6265
2826 /* 6265 */ GIM_Reject,
2827 /* 6266 */ // Label 307: @6266
2828 /* 6266 */ GIM_Reject,
2829 /* 6267 */ // Label 284: @6267
2830 /* 6267 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6300), // Rule ID 1061 //
2831 /* 6272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2832 /* 6275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2833 /* 6278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2834 /* 6281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2835 /* 6285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2836 /* 6289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2837 /* 6293 */ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2838 /* 6293 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2839 /* 6298 */ GIR_RootConstrainSelectedInstOperands,
2840 /* 6299 */ // GIR_Coverage, 1061,
2841 /* 6299 */ GIR_Done,
2842 /* 6300 */ // Label 310: @6300
2843 /* 6300 */ GIM_Reject,
2844 /* 6301 */ // Label 285: @6301
2845 /* 6301 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6334), // Rule ID 1062 //
2846 /* 6306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2847 /* 6309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2848 /* 6312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2849 /* 6315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2850 /* 6319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2851 /* 6323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2852 /* 6327 */ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2853 /* 6327 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2854 /* 6332 */ GIR_RootConstrainSelectedInstOperands,
2855 /* 6333 */ // GIR_Coverage, 1062,
2856 /* 6333 */ GIR_Done,
2857 /* 6334 */ // Label 311: @6334
2858 /* 6334 */ GIM_Reject,
2859 /* 6335 */ // Label 286: @6335
2860 /* 6335 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6368), // Rule ID 1063 //
2861 /* 6340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2862 /* 6343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2863 /* 6346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2864 /* 6349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2865 /* 6353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2866 /* 6357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2867 /* 6361 */ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2868 /* 6361 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2869 /* 6366 */ GIR_RootConstrainSelectedInstOperands,
2870 /* 6367 */ // GIR_Coverage, 1063,
2871 /* 6367 */ GIR_Done,
2872 /* 6368 */ // Label 312: @6368
2873 /* 6368 */ GIM_Reject,
2874 /* 6369 */ // Label 287: @6369
2875 /* 6369 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6402), // Rule ID 1064 //
2876 /* 6374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2877 /* 6377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2878 /* 6380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2879 /* 6383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2880 /* 6387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2881 /* 6391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2882 /* 6395 */ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2883 /* 6395 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2884 /* 6400 */ GIR_RootConstrainSelectedInstOperands,
2885 /* 6401 */ // GIR_Coverage, 1064,
2886 /* 6401 */ GIR_Done,
2887 /* 6402 */ // Label 313: @6402
2888 /* 6402 */ GIM_Reject,
2889 /* 6403 */ // Label 288: @6403
2890 /* 6403 */ GIM_Reject,
2891 /* 6404 */ // Label 10: @6404
2892 /* 6404 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6476),
2893 /* 6409 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2894 /* 6412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2895 /* 6415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2896 /* 6418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2897 /* 6421 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6448), // Rule ID 204 //
2898 /* 6426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
2899 /* 6429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2900 /* 6433 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2901 /* 6437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2902 /* 6441 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2903 /* 6441 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2904 /* 6446 */ GIR_RootConstrainSelectedInstOperands,
2905 /* 6447 */ // GIR_Coverage, 204,
2906 /* 6447 */ GIR_Done,
2907 /* 6448 */ // Label 315: @6448
2908 /* 6448 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6475), // Rule ID 205 //
2909 /* 6453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode),
2910 /* 6456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2911 /* 6460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2912 /* 6464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2913 /* 6468 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2914 /* 6468 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2915 /* 6473 */ GIR_RootConstrainSelectedInstOperands,
2916 /* 6474 */ // GIR_Coverage, 205,
2917 /* 6474 */ GIR_Done,
2918 /* 6475 */ // Label 316: @6475
2919 /* 6475 */ GIM_Reject,
2920 /* 6476 */ // Label 314: @6476
2921 /* 6476 */ GIM_Reject,
2922 /* 6477 */ // Label 11: @6477
2923 /* 6477 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6548),
2924 /* 6482 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2925 /* 6485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2926 /* 6488 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2927 /* 6491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2928 /* 6495 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6521), // Rule ID 743 //
2929 /* 6500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
2930 /* 6503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2931 /* 6507 */ // MIs[0] rs
2932 /* 6507 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2933 /* 6512 */ // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2934 /* 6512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2935 /* 6515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2936 /* 6517 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2937 /* 6519 */ GIR_RootConstrainSelectedInstOperands,
2938 /* 6520 */ // GIR_Coverage, 743,
2939 /* 6520 */ GIR_EraseRootFromParent_Done,
2940 /* 6521 */ // Label 318: @6521
2941 /* 6521 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6547), // Rule ID 745 //
2942 /* 6526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2943 /* 6529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2944 /* 6533 */ // MIs[0] fs
2945 /* 6533 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2946 /* 6538 */ // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2947 /* 6538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2948 /* 6541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2949 /* 6543 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2950 /* 6545 */ GIR_RootConstrainSelectedInstOperands,
2951 /* 6546 */ // GIR_Coverage, 745,
2952 /* 6546 */ GIR_EraseRootFromParent_Done,
2953 /* 6547 */ // Label 319: @6547
2954 /* 6547 */ GIM_Reject,
2955 /* 6548 */ // Label 317: @6548
2956 /* 6548 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6639),
2957 /* 6553 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2958 /* 6556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2959 /* 6559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2960 /* 6562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2961 /* 6566 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6602), // Rule ID 742 //
2962 /* 6571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2963 /* 6574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2964 /* 6578 */ // MIs[0] rs
2965 /* 6578 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2966 /* 6583 */ // MIs[0] rs
2967 /* 6583 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2968 /* 6588 */ // MIs[0] rs
2969 /* 6588 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2970 /* 6593 */ // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2971 /* 6593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2972 /* 6596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2973 /* 6598 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2974 /* 6600 */ GIR_RootConstrainSelectedInstOperands,
2975 /* 6601 */ // GIR_Coverage, 742,
2976 /* 6601 */ GIR_EraseRootFromParent_Done,
2977 /* 6602 */ // Label 321: @6602
2978 /* 6602 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(6638), // Rule ID 744 //
2979 /* 6607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2980 /* 6610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2981 /* 6614 */ // MIs[0] fs
2982 /* 6614 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2983 /* 6619 */ // MIs[0] fs
2984 /* 6619 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2985 /* 6624 */ // MIs[0] fs
2986 /* 6624 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2987 /* 6629 */ // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2988 /* 6629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2989 /* 6632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2990 /* 6634 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2991 /* 6636 */ GIR_RootConstrainSelectedInstOperands,
2992 /* 6637 */ // GIR_Coverage, 744,
2993 /* 6637 */ GIR_EraseRootFromParent_Done,
2994 /* 6638 */ // Label 322: @6638
2995 /* 6638 */ GIM_Reject,
2996 /* 6639 */ // Label 320: @6639
2997 /* 6639 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6708), // Rule ID 741 //
2998 /* 6644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2999 /* 6647 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
3000 /* 6650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
3001 /* 6653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3002 /* 6656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3003 /* 6660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3004 /* 6664 */ // MIs[0] rs
3005 /* 6664 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3006 /* 6669 */ // MIs[0] rs
3007 /* 6669 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3008 /* 6674 */ // MIs[0] rs
3009 /* 6674 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3010 /* 6679 */ // MIs[0] rs
3011 /* 6679 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3012 /* 6684 */ // MIs[0] rs
3013 /* 6684 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3014 /* 6689 */ // MIs[0] rs
3015 /* 6689 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3016 /* 6694 */ // MIs[0] rs
3017 /* 6694 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3018 /* 6699 */ // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
3019 /* 6699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
3020 /* 6702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3021 /* 6704 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3022 /* 6706 */ GIR_RootConstrainSelectedInstOperands,
3023 /* 6707 */ // GIR_Coverage, 741,
3024 /* 6707 */ GIR_EraseRootFromParent_Done,
3025 /* 6708 */ // Label 323: @6708
3026 /* 6708 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6817), // Rule ID 740 //
3027 /* 6713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
3028 /* 6716 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
3029 /* 6719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
3030 /* 6722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3031 /* 6725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3032 /* 6729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3033 /* 6733 */ // MIs[0] rs
3034 /* 6733 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3035 /* 6738 */ // MIs[0] rs
3036 /* 6738 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3037 /* 6743 */ // MIs[0] rs
3038 /* 6743 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3039 /* 6748 */ // MIs[0] rs
3040 /* 6748 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3041 /* 6753 */ // MIs[0] rs
3042 /* 6753 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3043 /* 6758 */ // MIs[0] rs
3044 /* 6758 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3045 /* 6763 */ // MIs[0] rs
3046 /* 6763 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3047 /* 6768 */ // MIs[0] rs
3048 /* 6768 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3049 /* 6773 */ // MIs[0] rs
3050 /* 6773 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3051 /* 6778 */ // MIs[0] rs
3052 /* 6778 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3053 /* 6783 */ // MIs[0] rs
3054 /* 6783 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3055 /* 6788 */ // MIs[0] rs
3056 /* 6788 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3057 /* 6793 */ // MIs[0] rs
3058 /* 6793 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3059 /* 6798 */ // MIs[0] rs
3060 /* 6798 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3061 /* 6803 */ // MIs[0] rs
3062 /* 6803 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3063 /* 6808 */ // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3064 /* 6808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
3065 /* 6811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3066 /* 6813 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3067 /* 6815 */ GIR_RootConstrainSelectedInstOperands,
3068 /* 6816 */ // GIR_Coverage, 740,
3069 /* 6816 */ GIR_EraseRootFromParent_Done,
3070 /* 6817 */ // Label 324: @6817
3071 /* 6817 */ GIM_Reject,
3072 /* 6818 */ // Label 12: @6818
3073 /* 6818 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 333*/ GIMT_Encode4(11128),
3074 /* 6829 */ /*GILLT_s32*//*Label 325*/ GIMT_Encode4(6861),
3075 /* 6833 */ /*GILLT_s64*//*Label 326*/ GIMT_Encode4(7138),
3076 /* 6837 */ /*GILLT_v4s8*//*Label 327*/ GIMT_Encode4(7194),
3077 /* 6841 */ /*GILLT_v16s8*//*Label 328*/ GIMT_Encode4(7254),
3078 /* 6845 */ /*GILLT_v2s16*//*Label 329*/ GIMT_Encode4(7939),
3079 /* 6849 */ /*GILLT_v8s16*//*Label 330*/ GIMT_Encode4(7999),
3080 /* 6853 */ /*GILLT_v4s32*//*Label 331*/ GIMT_Encode4(8924),
3081 /* 6857 */ /*GILLT_v2s64*//*Label 332*/ GIMT_Encode4(9993),
3082 /* 6861 */ // Label 325: @6861
3083 /* 6861 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(6887), // Rule ID 135 //
3084 /* 6866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3085 /* 6869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3086 /* 6872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3087 /* 6876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3088 /* 6880 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3089 /* 6880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3090 /* 6885 */ GIR_RootConstrainSelectedInstOperands,
3091 /* 6886 */ // GIR_Coverage, 135,
3092 /* 6886 */ GIR_Done,
3093 /* 6887 */ // Label 334: @6887
3094 /* 6887 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(6913), // Rule ID 136 //
3095 /* 6892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3096 /* 6895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3097 /* 6898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3098 /* 6902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3099 /* 6906 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3100 /* 6906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3101 /* 6911 */ GIR_RootConstrainSelectedInstOperands,
3102 /* 6912 */ // GIR_Coverage, 136,
3103 /* 6912 */ GIR_Done,
3104 /* 6913 */ // Label 335: @6913
3105 /* 6913 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(6939), // Rule ID 1183 //
3106 /* 6918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3107 /* 6921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3108 /* 6924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3109 /* 6928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3110 /* 6932 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3111 /* 6932 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3112 /* 6937 */ GIR_RootConstrainSelectedInstOperands,
3113 /* 6938 */ // GIR_Coverage, 1183,
3114 /* 6938 */ GIR_Done,
3115 /* 6939 */ // Label 336: @6939
3116 /* 6939 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(6965), // Rule ID 1184 //
3117 /* 6944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3118 /* 6947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3119 /* 6950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3120 /* 6954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3121 /* 6958 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3122 /* 6958 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3123 /* 6963 */ GIR_RootConstrainSelectedInstOperands,
3124 /* 6964 */ // GIR_Coverage, 1184,
3125 /* 6964 */ GIR_Done,
3126 /* 6965 */ // Label 337: @6965
3127 /* 6965 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(6991), // Rule ID 1198 //
3128 /* 6970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3129 /* 6973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3130 /* 6976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3131 /* 6980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3132 /* 6984 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3133 /* 6984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3134 /* 6989 */ GIR_RootConstrainSelectedInstOperands,
3135 /* 6990 */ // GIR_Coverage, 1198,
3136 /* 6990 */ GIR_Done,
3137 /* 6991 */ // Label 338: @6991
3138 /* 6991 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7017), // Rule ID 1199 //
3139 /* 6996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3140 /* 6999 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3141 /* 7002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3142 /* 7006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3143 /* 7010 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3144 /* 7010 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3145 /* 7015 */ GIR_RootConstrainSelectedInstOperands,
3146 /* 7016 */ // GIR_Coverage, 1199,
3147 /* 7016 */ GIR_Done,
3148 /* 7017 */ // Label 339: @7017
3149 /* 7017 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7047), // Rule ID 2040 //
3150 /* 7022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3151 /* 7025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3152 /* 7028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3153 /* 7032 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3154 /* 7036 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3155 /* 7036 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3156 /* 7041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3157 /* 7046 */ // GIR_Coverage, 2040,
3158 /* 7046 */ GIR_Done,
3159 /* 7047 */ // Label 340: @7047
3160 /* 7047 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7077), // Rule ID 2041 //
3161 /* 7052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3162 /* 7055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3163 /* 7058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3164 /* 7062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3165 /* 7066 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3166 /* 7066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3167 /* 7071 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3168 /* 7076 */ // GIR_Coverage, 2041,
3169 /* 7076 */ GIR_Done,
3170 /* 7077 */ // Label 341: @7077
3171 /* 7077 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7107), // Rule ID 2044 //
3172 /* 7082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3173 /* 7085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3174 /* 7088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3175 /* 7092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3176 /* 7096 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3177 /* 7096 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3178 /* 7101 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3179 /* 7106 */ // GIR_Coverage, 2044,
3180 /* 7106 */ GIR_Done,
3181 /* 7107 */ // Label 342: @7107
3182 /* 7107 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7137), // Rule ID 2045 //
3183 /* 7112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3184 /* 7115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3185 /* 7118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3186 /* 7122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3187 /* 7126 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3188 /* 7126 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3189 /* 7131 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3190 /* 7136 */ // GIR_Coverage, 2045,
3191 /* 7136 */ GIR_Done,
3192 /* 7137 */ // Label 343: @7137
3193 /* 7137 */ GIM_Reject,
3194 /* 7138 */ // Label 326: @7138
3195 /* 7138 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7193),
3196 /* 7143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3197 /* 7146 */ GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7169), // Rule ID 137 //
3198 /* 7151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat),
3199 /* 7154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3200 /* 7158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3201 /* 7162 */ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3202 /* 7162 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3203 /* 7167 */ GIR_RootConstrainSelectedInstOperands,
3204 /* 7168 */ // GIR_Coverage, 137,
3205 /* 7168 */ GIR_Done,
3206 /* 7169 */ // Label 345: @7169
3207 /* 7169 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7192), // Rule ID 138 //
3208 /* 7174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat),
3209 /* 7177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3210 /* 7181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3211 /* 7185 */ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3212 /* 7185 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3213 /* 7190 */ GIR_RootConstrainSelectedInstOperands,
3214 /* 7191 */ // GIR_Coverage, 138,
3215 /* 7191 */ GIR_Done,
3216 /* 7192 */ // Label 346: @7192
3217 /* 7192 */ GIM_Reject,
3218 /* 7193 */ // Label 344: @7193
3219 /* 7193 */ GIM_Reject,
3220 /* 7194 */ // Label 327: @7194
3221 /* 7194 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7253),
3222 /* 7199 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3223 /* 7202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3224 /* 7206 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7229), // Rule ID 2043 //
3225 /* 7211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3226 /* 7214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3227 /* 7218 */ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3228 /* 7218 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3229 /* 7223 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3230 /* 7228 */ // GIR_Coverage, 2043,
3231 /* 7228 */ GIR_Done,
3232 /* 7229 */ // Label 348: @7229
3233 /* 7229 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7252), // Rule ID 2047 //
3234 /* 7234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3235 /* 7237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3236 /* 7241 */ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3237 /* 7241 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3238 /* 7246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3239 /* 7251 */ // GIR_Coverage, 2047,
3240 /* 7251 */ GIR_Done,
3241 /* 7252 */ // Label 349: @7252
3242 /* 7252 */ GIM_Reject,
3243 /* 7253 */ // Label 347: @7253
3244 /* 7253 */ GIM_Reject,
3245 /* 7254 */ // Label 328: @7254
3246 /* 7254 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7280), // Rule ID 2131 //
3247 /* 7259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3248 /* 7262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3249 /* 7265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3250 /* 7269 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3251 /* 7269 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3252 /* 7274 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3253 /* 7279 */ // GIR_Coverage, 2131,
3254 /* 7279 */ GIR_Done,
3255 /* 7280 */ // Label 350: @7280
3256 /* 7280 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7306), // Rule ID 2132 //
3257 /* 7285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3258 /* 7288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3259 /* 7291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3260 /* 7295 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3261 /* 7295 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3262 /* 7300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3263 /* 7305 */ // GIR_Coverage, 2132,
3264 /* 7305 */ GIR_Done,
3265 /* 7306 */ // Label 351: @7306
3266 /* 7306 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7332), // Rule ID 2133 //
3267 /* 7311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3268 /* 7314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3269 /* 7317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3270 /* 7321 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3271 /* 7321 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3272 /* 7326 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3273 /* 7331 */ // GIR_Coverage, 2133,
3274 /* 7331 */ GIR_Done,
3275 /* 7332 */ // Label 352: @7332
3276 /* 7332 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7358), // Rule ID 2134 //
3277 /* 7337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3278 /* 7340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3279 /* 7343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3280 /* 7347 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
3281 /* 7347 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3282 /* 7352 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3283 /* 7357 */ // GIR_Coverage, 2134,
3284 /* 7357 */ GIR_Done,
3285 /* 7358 */ // Label 353: @7358
3286 /* 7358 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7384), // Rule ID 2135 //
3287 /* 7363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3288 /* 7366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3289 /* 7369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3290 /* 7373 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
3291 /* 7373 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3292 /* 7378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3293 /* 7383 */ // GIR_Coverage, 2135,
3294 /* 7383 */ GIR_Done,
3295 /* 7384 */ // Label 354: @7384
3296 /* 7384 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7410), // Rule ID 2136 //
3297 /* 7389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3298 /* 7392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3299 /* 7395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3300 /* 7399 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
3301 /* 7399 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3302 /* 7404 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3303 /* 7409 */ // GIR_Coverage, 2136,
3304 /* 7409 */ GIR_Done,
3305 /* 7410 */ // Label 355: @7410
3306 /* 7410 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7487), // Rule ID 2168 //
3307 /* 7415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3308 /* 7418 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3309 /* 7421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3310 /* 7425 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3311 /* 7425 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3312 /* 7428 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3313 /* 7432 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3314 /* 7437 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3315 /* 7441 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3316 /* 7446 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3317 /* 7449 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3318 /* 7453 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3319 /* 7458 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3320 /* 7461 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3321 /* 7471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3322 /* 7473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3323 /* 7476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3324 /* 7478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3325 /* 7481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3326 /* 7486 */ // GIR_Coverage, 2168,
3327 /* 7486 */ GIR_EraseRootFromParent_Done,
3328 /* 7487 */ // Label 356: @7487
3329 /* 7487 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7564), // Rule ID 2173 //
3330 /* 7492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3331 /* 7495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3332 /* 7498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3333 /* 7502 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3334 /* 7502 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3335 /* 7505 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3336 /* 7509 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3337 /* 7514 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3338 /* 7518 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3339 /* 7523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3340 /* 7526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3341 /* 7530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3342 /* 7535 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3343 /* 7538 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3344 /* 7548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3345 /* 7550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3346 /* 7553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3347 /* 7555 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3348 /* 7558 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3349 /* 7563 */ // GIR_Coverage, 2173,
3350 /* 7563 */ GIR_EraseRootFromParent_Done,
3351 /* 7564 */ // Label 357: @7564
3352 /* 7564 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7634), // Rule ID 2178 //
3353 /* 7569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3354 /* 7572 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3355 /* 7575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3356 /* 7579 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3357 /* 7579 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3358 /* 7582 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3359 /* 7586 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3360 /* 7591 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3361 /* 7595 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3362 /* 7600 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3363 /* 7603 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3364 /* 7607 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3365 /* 7612 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3366 /* 7615 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3367 /* 7618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3368 /* 7620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3369 /* 7623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3370 /* 7625 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3371 /* 7628 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3372 /* 7633 */ // GIR_Coverage, 2178,
3373 /* 7633 */ GIR_EraseRootFromParent_Done,
3374 /* 7634 */ // Label 358: @7634
3375 /* 7634 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(7704), // Rule ID 2183 //
3376 /* 7639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3377 /* 7642 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3378 /* 7645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3379 /* 7649 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3380 /* 7649 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3381 /* 7652 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3382 /* 7656 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3383 /* 7661 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3384 /* 7665 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3385 /* 7670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3386 /* 7673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3387 /* 7677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3388 /* 7682 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3389 /* 7685 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3390 /* 7688 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3391 /* 7690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3392 /* 7693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3393 /* 7695 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3394 /* 7698 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3395 /* 7703 */ // GIR_Coverage, 2183,
3396 /* 7703 */ GIR_EraseRootFromParent_Done,
3397 /* 7704 */ // Label 359: @7704
3398 /* 7704 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(7821), // Rule ID 2188 //
3399 /* 7709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3400 /* 7712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3401 /* 7715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3402 /* 7719 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3403 /* 7719 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3404 /* 7722 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3405 /* 7726 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3406 /* 7731 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3407 /* 7735 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3408 /* 7740 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3409 /* 7743 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3410 /* 7747 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3411 /* 7752 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3412 /* 7755 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3413 /* 7758 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3414 /* 7760 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3415 /* 7763 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3416 /* 7767 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3417 /* 7772 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3418 /* 7775 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3419 /* 7780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3420 /* 7783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3421 /* 7787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3422 /* 7792 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3423 /* 7795 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3424 /* 7805 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3425 /* 7807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3426 /* 7810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3427 /* 7812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3428 /* 7815 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3429 /* 7820 */ // GIR_Coverage, 2188,
3430 /* 7820 */ GIR_EraseRootFromParent_Done,
3431 /* 7821 */ // Label 360: @7821
3432 /* 7821 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(7938), // Rule ID 2193 //
3433 /* 7826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3434 /* 7829 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3435 /* 7832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3436 /* 7836 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3437 /* 7836 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3438 /* 7839 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3439 /* 7843 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3440 /* 7848 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3441 /* 7852 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3442 /* 7857 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3443 /* 7860 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3444 /* 7864 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3445 /* 7869 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3446 /* 7872 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3447 /* 7875 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3448 /* 7877 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3449 /* 7880 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3450 /* 7884 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3451 /* 7889 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3452 /* 7892 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3453 /* 7897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3454 /* 7900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3455 /* 7904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3456 /* 7909 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3457 /* 7912 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3458 /* 7922 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3459 /* 7924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3460 /* 7927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3461 /* 7929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3462 /* 7932 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3463 /* 7937 */ // GIR_Coverage, 2193,
3464 /* 7937 */ GIR_EraseRootFromParent_Done,
3465 /* 7938 */ // Label 361: @7938
3466 /* 7938 */ GIM_Reject,
3467 /* 7939 */ // Label 329: @7939
3468 /* 7939 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(7998),
3469 /* 7944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3470 /* 7947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3471 /* 7951 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(7974), // Rule ID 2042 //
3472 /* 7956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3473 /* 7959 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3474 /* 7963 */ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3475 /* 7963 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3476 /* 7968 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3477 /* 7973 */ // GIR_Coverage, 2042,
3478 /* 7973 */ GIR_Done,
3479 /* 7974 */ // Label 363: @7974
3480 /* 7974 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(7997), // Rule ID 2046 //
3481 /* 7979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3482 /* 7982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3483 /* 7986 */ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3484 /* 7986 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3485 /* 7991 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3486 /* 7996 */ // GIR_Coverage, 2046,
3487 /* 7996 */ GIR_Done,
3488 /* 7997 */ // Label 364: @7997
3489 /* 7997 */ GIM_Reject,
3490 /* 7998 */ // Label 362: @7998
3491 /* 7998 */ GIM_Reject,
3492 /* 7999 */ // Label 330: @7999
3493 /* 7999 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8025), // Rule ID 2125 //
3494 /* 8004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3495 /* 8007 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3496 /* 8010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3497 /* 8014 */ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3498 /* 8014 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3499 /* 8019 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3500 /* 8024 */ // GIR_Coverage, 2125,
3501 /* 8024 */ GIR_Done,
3502 /* 8025 */ // Label 365: @8025
3503 /* 8025 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8051), // Rule ID 2128 //
3504 /* 8030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3505 /* 8033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3506 /* 8036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3507 /* 8040 */ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3508 /* 8040 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3509 /* 8045 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3510 /* 8050 */ // GIR_Coverage, 2128,
3511 /* 8050 */ GIR_Done,
3512 /* 8051 */ // Label 366: @8051
3513 /* 8051 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8077), // Rule ID 2137 //
3514 /* 8056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3515 /* 8059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3516 /* 8062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3517 /* 8066 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3518 /* 8066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3519 /* 8071 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3520 /* 8076 */ // GIR_Coverage, 2137,
3521 /* 8076 */ GIR_Done,
3522 /* 8077 */ // Label 367: @8077
3523 /* 8077 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8103), // Rule ID 2138 //
3524 /* 8082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3525 /* 8085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3526 /* 8088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3527 /* 8092 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3528 /* 8092 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3529 /* 8097 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3530 /* 8102 */ // GIR_Coverage, 2138,
3531 /* 8102 */ GIR_Done,
3532 /* 8103 */ // Label 368: @8103
3533 /* 8103 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8129), // Rule ID 2139 //
3534 /* 8108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3535 /* 8111 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3536 /* 8114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3537 /* 8118 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3538 /* 8118 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3539 /* 8123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3540 /* 8128 */ // GIR_Coverage, 2139,
3541 /* 8128 */ GIR_Done,
3542 /* 8129 */ // Label 369: @8129
3543 /* 8129 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8155), // Rule ID 2140 //
3544 /* 8134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3545 /* 8137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3546 /* 8140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3547 /* 8144 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3548 /* 8144 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3549 /* 8149 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3550 /* 8154 */ // GIR_Coverage, 2140,
3551 /* 8154 */ GIR_Done,
3552 /* 8155 */ // Label 370: @8155
3553 /* 8155 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8181), // Rule ID 2141 //
3554 /* 8160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3555 /* 8163 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3556 /* 8166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3557 /* 8170 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3558 /* 8170 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3559 /* 8175 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3560 /* 8180 */ // GIR_Coverage, 2141,
3561 /* 8180 */ GIR_Done,
3562 /* 8181 */ // Label 371: @8181
3563 /* 8181 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8258), // Rule ID 2162 //
3564 /* 8186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3565 /* 8189 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3566 /* 8192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3567 /* 8196 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3568 /* 8196 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3569 /* 8199 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3570 /* 8203 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3571 /* 8208 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3572 /* 8212 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3573 /* 8217 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3574 /* 8220 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3575 /* 8224 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3576 /* 8229 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3577 /* 8232 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3578 /* 8242 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3579 /* 8244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3580 /* 8247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3581 /* 8249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3582 /* 8252 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3583 /* 8257 */ // GIR_Coverage, 2162,
3584 /* 8257 */ GIR_EraseRootFromParent_Done,
3585 /* 8258 */ // Label 372: @8258
3586 /* 8258 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8335), // Rule ID 2163 //
3587 /* 8263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3588 /* 8266 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3589 /* 8269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3590 /* 8273 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3591 /* 8273 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3592 /* 8276 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3593 /* 8280 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3594 /* 8285 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3595 /* 8289 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3596 /* 8294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3597 /* 8297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3598 /* 8301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3599 /* 8306 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3600 /* 8309 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3601 /* 8319 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3602 /* 8321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3603 /* 8324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3604 /* 8326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3605 /* 8329 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3606 /* 8334 */ // GIR_Coverage, 2163,
3607 /* 8334 */ GIR_EraseRootFromParent_Done,
3608 /* 8335 */ // Label 373: @8335
3609 /* 8335 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8412), // Rule ID 2179 //
3610 /* 8340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3611 /* 8343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3612 /* 8346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3613 /* 8350 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3614 /* 8350 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3615 /* 8353 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3616 /* 8357 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3617 /* 8362 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3618 /* 8366 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3619 /* 8371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3620 /* 8374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3621 /* 8378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3622 /* 8383 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3623 /* 8386 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3624 /* 8396 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3625 /* 8398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3626 /* 8401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3627 /* 8403 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3628 /* 8406 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3629 /* 8411 */ // GIR_Coverage, 2179,
3630 /* 8411 */ GIR_EraseRootFromParent_Done,
3631 /* 8412 */ // Label 374: @8412
3632 /* 8412 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8489), // Rule ID 2180 //
3633 /* 8417 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3634 /* 8420 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3635 /* 8423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3636 /* 8427 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3637 /* 8427 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3638 /* 8430 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3639 /* 8434 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3640 /* 8439 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3641 /* 8443 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3642 /* 8448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3643 /* 8451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3644 /* 8455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3645 /* 8460 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3646 /* 8463 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3647 /* 8473 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3648 /* 8475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3649 /* 8478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3650 /* 8480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3651 /* 8483 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3652 /* 8488 */ // GIR_Coverage, 2180,
3653 /* 8488 */ GIR_EraseRootFromParent_Done,
3654 /* 8489 */ // Label 375: @8489
3655 /* 8489 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8566), // Rule ID 2184 //
3656 /* 8494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3657 /* 8497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3658 /* 8500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3659 /* 8504 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3660 /* 8504 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3661 /* 8507 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3662 /* 8511 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3663 /* 8516 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3664 /* 8520 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3665 /* 8525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3666 /* 8528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3667 /* 8532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3668 /* 8537 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3669 /* 8540 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3670 /* 8550 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3671 /* 8552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3672 /* 8555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3673 /* 8557 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3674 /* 8560 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3675 /* 8565 */ // GIR_Coverage, 2184,
3676 /* 8565 */ GIR_EraseRootFromParent_Done,
3677 /* 8566 */ // Label 376: @8566
3678 /* 8566 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8643), // Rule ID 2185 //
3679 /* 8571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3680 /* 8574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3681 /* 8577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3682 /* 8581 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3683 /* 8581 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3684 /* 8584 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3685 /* 8588 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3686 /* 8593 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3687 /* 8597 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3688 /* 8602 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3689 /* 8605 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3690 /* 8609 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3691 /* 8614 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3692 /* 8617 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3693 /* 8627 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3694 /* 8629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3695 /* 8632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3696 /* 8634 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3697 /* 8637 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3698 /* 8642 */ // GIR_Coverage, 2185,
3699 /* 8642 */ GIR_EraseRootFromParent_Done,
3700 /* 8643 */ // Label 377: @8643
3701 /* 8643 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8713), // Rule ID 2189 //
3702 /* 8648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3703 /* 8651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3704 /* 8654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3705 /* 8658 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3706 /* 8658 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3707 /* 8661 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3708 /* 8665 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3709 /* 8670 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3710 /* 8674 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3711 /* 8679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3712 /* 8682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3713 /* 8686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3714 /* 8691 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3715 /* 8694 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3716 /* 8697 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3717 /* 8699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3718 /* 8702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3719 /* 8704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3720 /* 8707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3721 /* 8712 */ // GIR_Coverage, 2189,
3722 /* 8712 */ GIR_EraseRootFromParent_Done,
3723 /* 8713 */ // Label 378: @8713
3724 /* 8713 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(8783), // Rule ID 2190 //
3725 /* 8718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3726 /* 8721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3727 /* 8724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3728 /* 8728 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3729 /* 8728 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3730 /* 8731 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3731 /* 8735 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3732 /* 8740 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3733 /* 8744 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3734 /* 8749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3735 /* 8752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3736 /* 8756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3737 /* 8761 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3738 /* 8764 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3739 /* 8767 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3740 /* 8769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3741 /* 8772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3742 /* 8774 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3743 /* 8777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3744 /* 8782 */ // GIR_Coverage, 2190,
3745 /* 8782 */ GIR_EraseRootFromParent_Done,
3746 /* 8783 */ // Label 379: @8783
3747 /* 8783 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(8853), // Rule ID 2194 //
3748 /* 8788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3749 /* 8791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3750 /* 8794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3751 /* 8798 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3752 /* 8798 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3753 /* 8801 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3754 /* 8805 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3755 /* 8810 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3756 /* 8814 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3757 /* 8819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3758 /* 8822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3759 /* 8826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3760 /* 8831 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3761 /* 8834 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3762 /* 8837 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3763 /* 8839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3764 /* 8842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3765 /* 8844 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3766 /* 8847 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3767 /* 8852 */ // GIR_Coverage, 2194,
3768 /* 8852 */ GIR_EraseRootFromParent_Done,
3769 /* 8853 */ // Label 380: @8853
3770 /* 8853 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(8923), // Rule ID 2195 //
3771 /* 8858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3772 /* 8861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3773 /* 8864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3774 /* 8868 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3775 /* 8868 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3776 /* 8871 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3777 /* 8875 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3778 /* 8880 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3779 /* 8884 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3780 /* 8889 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3781 /* 8892 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3782 /* 8896 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3783 /* 8901 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3784 /* 8904 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3785 /* 8907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3786 /* 8909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3787 /* 8912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3788 /* 8914 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3789 /* 8917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3790 /* 8922 */ // GIR_Coverage, 2195,
3791 /* 8922 */ GIR_EraseRootFromParent_Done,
3792 /* 8923 */ // Label 381: @8923
3793 /* 8923 */ GIM_Reject,
3794 /* 8924 */ // Label 331: @8924
3795 /* 8924 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(8950), // Rule ID 2126 //
3796 /* 8929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3797 /* 8932 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3798 /* 8935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3799 /* 8939 */ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3800 /* 8939 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3801 /* 8944 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3802 /* 8949 */ // GIR_Coverage, 2126,
3803 /* 8949 */ GIR_Done,
3804 /* 8950 */ // Label 382: @8950
3805 /* 8950 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(8976), // Rule ID 2129 //
3806 /* 8955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3807 /* 8958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3808 /* 8961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3809 /* 8965 */ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3810 /* 8965 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3811 /* 8970 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3812 /* 8975 */ // GIR_Coverage, 2129,
3813 /* 8975 */ GIR_Done,
3814 /* 8976 */ // Label 383: @8976
3815 /* 8976 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(9002), // Rule ID 2142 //
3816 /* 8981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3817 /* 8984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3818 /* 8987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3819 /* 8991 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3820 /* 8991 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3821 /* 8996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3822 /* 9001 */ // GIR_Coverage, 2142,
3823 /* 9001 */ GIR_Done,
3824 /* 9002 */ // Label 384: @9002
3825 /* 9002 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(9028), // Rule ID 2143 //
3826 /* 9007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3827 /* 9010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3828 /* 9013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3829 /* 9017 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3830 /* 9017 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3831 /* 9022 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3832 /* 9027 */ // GIR_Coverage, 2143,
3833 /* 9027 */ GIR_Done,
3834 /* 9028 */ // Label 385: @9028
3835 /* 9028 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(9054), // Rule ID 2144 //
3836 /* 9033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3837 /* 9036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3838 /* 9039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3839 /* 9043 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3840 /* 9043 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3841 /* 9048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3842 /* 9053 */ // GIR_Coverage, 2144,
3843 /* 9053 */ GIR_Done,
3844 /* 9054 */ // Label 386: @9054
3845 /* 9054 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(9080), // Rule ID 2145 //
3846 /* 9059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3847 /* 9062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3848 /* 9065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3849 /* 9069 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3850 /* 9069 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3851 /* 9074 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3852 /* 9079 */ // GIR_Coverage, 2145,
3853 /* 9079 */ GIR_Done,
3854 /* 9080 */ // Label 387: @9080
3855 /* 9080 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(9106), // Rule ID 2146 //
3856 /* 9085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3857 /* 9088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3858 /* 9091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3859 /* 9095 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3860 /* 9095 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3861 /* 9100 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3862 /* 9105 */ // GIR_Coverage, 2146,
3863 /* 9105 */ GIR_Done,
3864 /* 9106 */ // Label 388: @9106
3865 /* 9106 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(9132), // Rule ID 2152 //
3866 /* 9111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3867 /* 9114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3868 /* 9117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3869 /* 9121 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3870 /* 9121 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3871 /* 9126 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3872 /* 9131 */ // GIR_Coverage, 2152,
3873 /* 9131 */ GIR_Done,
3874 /* 9132 */ // Label 389: @9132
3875 /* 9132 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(9158), // Rule ID 2153 //
3876 /* 9137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3877 /* 9140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3878 /* 9143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3879 /* 9147 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3880 /* 9147 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3881 /* 9152 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3882 /* 9157 */ // GIR_Coverage, 2153,
3883 /* 9157 */ GIR_Done,
3884 /* 9158 */ // Label 390: @9158
3885 /* 9158 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(9184), // Rule ID 2154 //
3886 /* 9163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3887 /* 9166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3888 /* 9169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3889 /* 9173 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3890 /* 9173 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3891 /* 9178 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3892 /* 9183 */ // GIR_Coverage, 2154,
3893 /* 9183 */ GIR_Done,
3894 /* 9184 */ // Label 391: @9184
3895 /* 9184 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(9210), // Rule ID 2155 //
3896 /* 9189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3897 /* 9192 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3898 /* 9195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3899 /* 9199 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3900 /* 9199 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3901 /* 9204 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3902 /* 9209 */ // GIR_Coverage, 2155,
3903 /* 9209 */ GIR_Done,
3904 /* 9210 */ // Label 392: @9210
3905 /* 9210 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(9236), // Rule ID 2156 //
3906 /* 9215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3907 /* 9218 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3908 /* 9221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3909 /* 9225 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3910 /* 9225 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3911 /* 9230 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3912 /* 9235 */ // GIR_Coverage, 2156,
3913 /* 9235 */ GIR_Done,
3914 /* 9236 */ // Label 393: @9236
3915 /* 9236 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(9306), // Rule ID 2164 //
3916 /* 9241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3917 /* 9244 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3918 /* 9247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3919 /* 9251 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3920 /* 9251 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3921 /* 9254 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3922 /* 9258 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3923 /* 9263 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3924 /* 9267 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3925 /* 9272 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3926 /* 9275 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3927 /* 9279 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3928 /* 9284 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3929 /* 9287 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3930 /* 9290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3931 /* 9292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3932 /* 9295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3933 /* 9297 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3934 /* 9300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3935 /* 9305 */ // GIR_Coverage, 2164,
3936 /* 9305 */ GIR_EraseRootFromParent_Done,
3937 /* 9306 */ // Label 394: @9306
3938 /* 9306 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(9376), // Rule ID 2165 //
3939 /* 9311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3940 /* 9314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3941 /* 9317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3942 /* 9321 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3943 /* 9321 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3944 /* 9324 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3945 /* 9328 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3946 /* 9333 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3947 /* 9337 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3948 /* 9342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3949 /* 9345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3950 /* 9349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3951 /* 9354 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3952 /* 9357 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3953 /* 9360 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3954 /* 9362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3955 /* 9365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3956 /* 9367 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3957 /* 9370 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3958 /* 9375 */ // GIR_Coverage, 2165,
3959 /* 9375 */ GIR_EraseRootFromParent_Done,
3960 /* 9376 */ // Label 395: @9376
3961 /* 9376 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(9453), // Rule ID 2169 //
3962 /* 9381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3963 /* 9384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3964 /* 9387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3965 /* 9391 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3966 /* 9391 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3967 /* 9394 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3968 /* 9398 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3969 /* 9403 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3970 /* 9407 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3971 /* 9412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3972 /* 9415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3973 /* 9419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3974 /* 9424 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3975 /* 9427 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3976 /* 9437 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3977 /* 9439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3978 /* 9442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3979 /* 9444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3980 /* 9447 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3981 /* 9452 */ // GIR_Coverage, 2169,
3982 /* 9452 */ GIR_EraseRootFromParent_Done,
3983 /* 9453 */ // Label 396: @9453
3984 /* 9453 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(9530), // Rule ID 2170 //
3985 /* 9458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3986 /* 9461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3987 /* 9464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3988 /* 9468 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3989 /* 9468 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3990 /* 9471 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3991 /* 9475 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3992 /* 9480 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3993 /* 9484 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3994 /* 9489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3995 /* 9492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3996 /* 9496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3997 /* 9501 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3998 /* 9504 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3999 /* 9514 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4000 /* 9516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4001 /* 9519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4002 /* 9521 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4003 /* 9524 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4004 /* 9529 */ // GIR_Coverage, 2170,
4005 /* 9529 */ GIR_EraseRootFromParent_Done,
4006 /* 9530 */ // Label 397: @9530
4007 /* 9530 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(9607), // Rule ID 2174 //
4008 /* 9535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4009 /* 9538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4010 /* 9541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4011 /* 9545 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4012 /* 9545 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4013 /* 9548 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4014 /* 9552 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4015 /* 9557 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4016 /* 9561 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4017 /* 9566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4018 /* 9569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4019 /* 9573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4020 /* 9578 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4021 /* 9581 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4022 /* 9591 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4023 /* 9593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4024 /* 9596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4025 /* 9598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4026 /* 9601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4027 /* 9606 */ // GIR_Coverage, 2174,
4028 /* 9606 */ GIR_EraseRootFromParent_Done,
4029 /* 9607 */ // Label 398: @9607
4030 /* 9607 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(9684), // Rule ID 2175 //
4031 /* 9612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4032 /* 9615 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4033 /* 9618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4034 /* 9622 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4035 /* 9622 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4036 /* 9625 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4037 /* 9629 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4038 /* 9634 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4039 /* 9638 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4040 /* 9643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4041 /* 9646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4042 /* 9650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4043 /* 9655 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4044 /* 9658 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4045 /* 9668 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4046 /* 9670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4047 /* 9673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4048 /* 9675 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4049 /* 9678 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4050 /* 9683 */ // GIR_Coverage, 2175,
4051 /* 9683 */ GIR_EraseRootFromParent_Done,
4052 /* 9684 */ // Label 399: @9684
4053 /* 9684 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(9761), // Rule ID 2191 //
4054 /* 9689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4055 /* 9692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4056 /* 9695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4057 /* 9699 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4058 /* 9699 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4059 /* 9702 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4060 /* 9706 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4061 /* 9711 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4062 /* 9715 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4063 /* 9720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4064 /* 9723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4065 /* 9727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4066 /* 9732 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4067 /* 9735 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4068 /* 9745 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4069 /* 9747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4070 /* 9750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4071 /* 9752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4072 /* 9755 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4073 /* 9760 */ // GIR_Coverage, 2191,
4074 /* 9760 */ GIR_EraseRootFromParent_Done,
4075 /* 9761 */ // Label 400: @9761
4076 /* 9761 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(9838), // Rule ID 2192 //
4077 /* 9766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4078 /* 9769 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4079 /* 9772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4080 /* 9776 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4081 /* 9776 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4082 /* 9779 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4083 /* 9783 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4084 /* 9788 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4085 /* 9792 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4086 /* 9797 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4087 /* 9800 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4088 /* 9804 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4089 /* 9809 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4090 /* 9812 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4091 /* 9822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4092 /* 9824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4093 /* 9827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4094 /* 9829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4095 /* 9832 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4096 /* 9837 */ // GIR_Coverage, 2192,
4097 /* 9837 */ GIR_EraseRootFromParent_Done,
4098 /* 9838 */ // Label 401: @9838
4099 /* 9838 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(9915), // Rule ID 2196 //
4100 /* 9843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4101 /* 9846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4102 /* 9849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4103 /* 9853 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4104 /* 9853 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4105 /* 9856 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4106 /* 9860 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4107 /* 9865 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4108 /* 9869 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4109 /* 9874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4110 /* 9877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4111 /* 9881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4112 /* 9886 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4113 /* 9889 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4114 /* 9899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4115 /* 9901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4116 /* 9904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4117 /* 9906 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4118 /* 9909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4119 /* 9914 */ // GIR_Coverage, 2196,
4120 /* 9914 */ GIR_EraseRootFromParent_Done,
4121 /* 9915 */ // Label 402: @9915
4122 /* 9915 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(9992), // Rule ID 2197 //
4123 /* 9920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4124 /* 9923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4125 /* 9926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
4126 /* 9930 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
4127 /* 9930 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4128 /* 9933 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4129 /* 9937 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4130 /* 9942 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4131 /* 9946 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4132 /* 9951 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4133 /* 9954 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4134 /* 9958 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4135 /* 9963 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4136 /* 9966 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4137 /* 9976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4138 /* 9978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4139 /* 9981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4140 /* 9983 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4141 /* 9986 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4142 /* 9991 */ // GIR_Coverage, 2197,
4143 /* 9991 */ GIR_EraseRootFromParent_Done,
4144 /* 9992 */ // Label 403: @9992
4145 /* 9992 */ GIM_Reject,
4146 /* 9993 */ // Label 332: @9993
4147 /* 9993 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(10019), // Rule ID 2127 //
4148 /* 9998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
4149 /* 10001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4150 /* 10004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4151 /* 10008 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
4152 /* 10008 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4153 /* 10013 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4154 /* 10018 */ // GIR_Coverage, 2127,
4155 /* 10018 */ GIR_Done,
4156 /* 10019 */ // Label 404: @10019
4157 /* 10019 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(10045), // Rule ID 2130 //
4158 /* 10024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
4159 /* 10027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4160 /* 10030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4161 /* 10034 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
4162 /* 10034 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4163 /* 10039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4164 /* 10044 */ // GIR_Coverage, 2130,
4165 /* 10044 */ GIR_Done,
4166 /* 10045 */ // Label 405: @10045
4167 /* 10045 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(10071), // Rule ID 2147 //
4168 /* 10050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4169 /* 10053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4170 /* 10056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4171 /* 10060 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
4172 /* 10060 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4173 /* 10065 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4174 /* 10070 */ // GIR_Coverage, 2147,
4175 /* 10070 */ GIR_Done,
4176 /* 10071 */ // Label 406: @10071
4177 /* 10071 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(10097), // Rule ID 2148 //
4178 /* 10076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4179 /* 10079 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4180 /* 10082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4181 /* 10086 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4182 /* 10086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4183 /* 10091 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4184 /* 10096 */ // GIR_Coverage, 2148,
4185 /* 10096 */ GIR_Done,
4186 /* 10097 */ // Label 407: @10097
4187 /* 10097 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(10123), // Rule ID 2149 //
4188 /* 10102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4189 /* 10105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4190 /* 10108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4191 /* 10112 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4192 /* 10112 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4193 /* 10117 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4194 /* 10122 */ // GIR_Coverage, 2149,
4195 /* 10122 */ GIR_Done,
4196 /* 10123 */ // Label 408: @10123
4197 /* 10123 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(10149), // Rule ID 2150 //
4198 /* 10128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4199 /* 10131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4200 /* 10134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4201 /* 10138 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4202 /* 10138 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4203 /* 10143 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4204 /* 10148 */ // GIR_Coverage, 2150,
4205 /* 10148 */ GIR_Done,
4206 /* 10149 */ // Label 409: @10149
4207 /* 10149 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(10175), // Rule ID 2151 //
4208 /* 10154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4209 /* 10157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4210 /* 10160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4211 /* 10164 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4212 /* 10164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4213 /* 10169 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4214 /* 10174 */ // GIR_Coverage, 2151,
4215 /* 10174 */ GIR_Done,
4216 /* 10175 */ // Label 410: @10175
4217 /* 10175 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(10201), // Rule ID 2157 //
4218 /* 10180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4219 /* 10183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4220 /* 10186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4221 /* 10190 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
4222 /* 10190 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4223 /* 10195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4224 /* 10200 */ // GIR_Coverage, 2157,
4225 /* 10200 */ GIR_Done,
4226 /* 10201 */ // Label 411: @10201
4227 /* 10201 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(10227), // Rule ID 2158 //
4228 /* 10206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4229 /* 10209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4230 /* 10212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4231 /* 10216 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4232 /* 10216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4233 /* 10221 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4234 /* 10226 */ // GIR_Coverage, 2158,
4235 /* 10226 */ GIR_Done,
4236 /* 10227 */ // Label 412: @10227
4237 /* 10227 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(10253), // Rule ID 2159 //
4238 /* 10232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4239 /* 10235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4240 /* 10238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4241 /* 10242 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4242 /* 10242 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4243 /* 10247 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4244 /* 10252 */ // GIR_Coverage, 2159,
4245 /* 10252 */ GIR_Done,
4246 /* 10253 */ // Label 413: @10253
4247 /* 10253 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(10279), // Rule ID 2160 //
4248 /* 10258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4249 /* 10261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4250 /* 10264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4251 /* 10268 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4252 /* 10268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4253 /* 10273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4254 /* 10278 */ // GIR_Coverage, 2160,
4255 /* 10278 */ GIR_Done,
4256 /* 10279 */ // Label 414: @10279
4257 /* 10279 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(10305), // Rule ID 2161 //
4258 /* 10284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4259 /* 10287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4260 /* 10290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4261 /* 10294 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4262 /* 10294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4263 /* 10299 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4264 /* 10304 */ // GIR_Coverage, 2161,
4265 /* 10304 */ GIR_Done,
4266 /* 10305 */ // Label 415: @10305
4267 /* 10305 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(10422), // Rule ID 2166 //
4268 /* 10310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4269 /* 10313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4270 /* 10316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4271 /* 10320 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4272 /* 10320 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4273 /* 10323 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4274 /* 10327 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4275 /* 10332 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4276 /* 10336 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4277 /* 10341 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4278 /* 10344 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4279 /* 10348 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4280 /* 10353 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4281 /* 10356 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4282 /* 10359 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4283 /* 10361 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4284 /* 10364 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4285 /* 10368 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4286 /* 10373 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4287 /* 10376 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4288 /* 10381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4289 /* 10384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4290 /* 10388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4291 /* 10393 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4292 /* 10396 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4293 /* 10406 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4294 /* 10408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4295 /* 10411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4296 /* 10413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4297 /* 10416 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4298 /* 10421 */ // GIR_Coverage, 2166,
4299 /* 10421 */ GIR_EraseRootFromParent_Done,
4300 /* 10422 */ // Label 416: @10422
4301 /* 10422 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(10539), // Rule ID 2167 //
4302 /* 10427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4303 /* 10430 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4304 /* 10433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4305 /* 10437 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4306 /* 10437 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4307 /* 10440 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4308 /* 10444 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4309 /* 10449 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4310 /* 10453 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4311 /* 10458 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4312 /* 10461 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4313 /* 10465 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4314 /* 10470 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4315 /* 10473 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4316 /* 10476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4317 /* 10478 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4318 /* 10481 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4319 /* 10485 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4320 /* 10490 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4321 /* 10493 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4322 /* 10498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4323 /* 10501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4324 /* 10505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4325 /* 10510 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4326 /* 10513 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4327 /* 10523 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4328 /* 10525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4329 /* 10528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4330 /* 10530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4331 /* 10533 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4332 /* 10538 */ // GIR_Coverage, 2167,
4333 /* 10538 */ GIR_EraseRootFromParent_Done,
4334 /* 10539 */ // Label 417: @10539
4335 /* 10539 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(10609), // Rule ID 2171 //
4336 /* 10544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4337 /* 10547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4338 /* 10550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4339 /* 10554 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4340 /* 10554 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4341 /* 10557 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4342 /* 10561 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4343 /* 10566 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4344 /* 10570 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4345 /* 10575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4346 /* 10578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4347 /* 10582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4348 /* 10587 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4349 /* 10590 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4350 /* 10593 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4351 /* 10595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4352 /* 10598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4353 /* 10600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4354 /* 10603 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4355 /* 10608 */ // GIR_Coverage, 2171,
4356 /* 10608 */ GIR_EraseRootFromParent_Done,
4357 /* 10609 */ // Label 418: @10609
4358 /* 10609 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(10679), // Rule ID 2172 //
4359 /* 10614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4360 /* 10617 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4361 /* 10620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4362 /* 10624 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4363 /* 10624 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4364 /* 10627 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4365 /* 10631 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4366 /* 10636 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4367 /* 10640 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4368 /* 10645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4369 /* 10648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4370 /* 10652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4371 /* 10657 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4372 /* 10660 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4373 /* 10663 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4374 /* 10665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4375 /* 10668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4376 /* 10670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4377 /* 10673 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4378 /* 10678 */ // GIR_Coverage, 2172,
4379 /* 10678 */ GIR_EraseRootFromParent_Done,
4380 /* 10679 */ // Label 419: @10679
4381 /* 10679 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(10749), // Rule ID 2176 //
4382 /* 10684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4383 /* 10687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4384 /* 10690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4385 /* 10694 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4386 /* 10694 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4387 /* 10697 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4388 /* 10701 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4389 /* 10706 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4390 /* 10710 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4391 /* 10715 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4392 /* 10718 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4393 /* 10722 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4394 /* 10727 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4395 /* 10730 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4396 /* 10733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4397 /* 10735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4398 /* 10738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4399 /* 10740 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4400 /* 10743 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4401 /* 10748 */ // GIR_Coverage, 2176,
4402 /* 10748 */ GIR_EraseRootFromParent_Done,
4403 /* 10749 */ // Label 420: @10749
4404 /* 10749 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(10819), // Rule ID 2177 //
4405 /* 10754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4406 /* 10757 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4407 /* 10760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4408 /* 10764 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4409 /* 10764 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4410 /* 10767 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4411 /* 10771 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4412 /* 10776 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4413 /* 10780 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4414 /* 10785 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4415 /* 10788 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4416 /* 10792 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4417 /* 10797 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4418 /* 10800 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4419 /* 10803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4420 /* 10805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4421 /* 10808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4422 /* 10810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4423 /* 10813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4424 /* 10818 */ // GIR_Coverage, 2177,
4425 /* 10818 */ GIR_EraseRootFromParent_Done,
4426 /* 10819 */ // Label 421: @10819
4427 /* 10819 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(10896), // Rule ID 2181 //
4428 /* 10824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4429 /* 10827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4430 /* 10830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4431 /* 10834 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4432 /* 10834 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4433 /* 10837 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4434 /* 10841 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4435 /* 10846 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4436 /* 10850 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4437 /* 10855 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4438 /* 10858 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4439 /* 10862 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4440 /* 10867 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4441 /* 10870 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4442 /* 10880 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4443 /* 10882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4444 /* 10885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4445 /* 10887 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4446 /* 10890 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4447 /* 10895 */ // GIR_Coverage, 2181,
4448 /* 10895 */ GIR_EraseRootFromParent_Done,
4449 /* 10896 */ // Label 422: @10896
4450 /* 10896 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(10973), // Rule ID 2182 //
4451 /* 10901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4452 /* 10904 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4453 /* 10907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4454 /* 10911 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4455 /* 10911 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4456 /* 10914 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4457 /* 10918 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4458 /* 10923 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4459 /* 10927 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4460 /* 10932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4461 /* 10935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4462 /* 10939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4463 /* 10944 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4464 /* 10947 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4465 /* 10957 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4466 /* 10959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4467 /* 10962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4468 /* 10964 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4469 /* 10967 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4470 /* 10972 */ // GIR_Coverage, 2182,
4471 /* 10972 */ GIR_EraseRootFromParent_Done,
4472 /* 10973 */ // Label 423: @10973
4473 /* 10973 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(11050), // Rule ID 2186 //
4474 /* 10978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4475 /* 10981 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4476 /* 10984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4477 /* 10988 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4478 /* 10988 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4479 /* 10991 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4480 /* 10995 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4481 /* 11000 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4482 /* 11004 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4483 /* 11009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4484 /* 11012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4485 /* 11016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4486 /* 11021 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4487 /* 11024 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4488 /* 11034 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4489 /* 11036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4490 /* 11039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4491 /* 11041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4492 /* 11044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4493 /* 11049 */ // GIR_Coverage, 2186,
4494 /* 11049 */ GIR_EraseRootFromParent_Done,
4495 /* 11050 */ // Label 424: @11050
4496 /* 11050 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(11127), // Rule ID 2187 //
4497 /* 11055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4498 /* 11058 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4499 /* 11061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4500 /* 11065 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4501 /* 11065 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4502 /* 11068 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4503 /* 11072 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4504 /* 11077 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4505 /* 11081 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4506 /* 11086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4507 /* 11089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4508 /* 11093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4509 /* 11098 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4510 /* 11101 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4511 /* 11111 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4512 /* 11113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4513 /* 11116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4514 /* 11118 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4515 /* 11121 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4516 /* 11126 */ // GIR_Coverage, 2187,
4517 /* 11126 */ GIR_EraseRootFromParent_Done,
4518 /* 11127 */ // Label 425: @11127
4519 /* 11127 */ GIM_Reject,
4520 /* 11128 */ // Label 333: @11128
4521 /* 11128 */ GIM_Reject,
4522 /* 11129 */ // Label 13: @11129
4523 /* 11129 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(11193), // Rule ID 2116 //
4524 /* 11134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4525 /* 11137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4526 /* 11140 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4527 /* 11143 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4528 /* 11147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4529 /* 11151 */ // MIs[0] Operand 1
4530 /* 11151 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4531 /* 11155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4532 /* 11159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4533 /* 11163 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4534 /* 11167 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4535 /* 11171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4536 /* 11173 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4537 /* 11173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4538 /* 11176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4539 /* 11178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4540 /* 11182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4541 /* 11186 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4542 /* 11191 */ GIR_RootConstrainSelectedInstOperands,
4543 /* 11192 */ // GIR_Coverage, 2116,
4544 /* 11192 */ GIR_EraseRootFromParent_Done,
4545 /* 11193 */ // Label 426: @11193
4546 /* 11193 */ GIM_Reject,
4547 /* 11194 */ // Label 14: @11194
4548 /* 11194 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(11261), // Rule ID 2115 //
4549 /* 11199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4550 /* 11202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4551 /* 11205 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4552 /* 11208 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4553 /* 11215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4554 /* 11219 */ // MIs[0] Operand 1
4555 /* 11219 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4556 /* 11223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4557 /* 11227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4558 /* 11231 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4559 /* 11235 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4560 /* 11239 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4561 /* 11241 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4562 /* 11241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4563 /* 11244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4564 /* 11246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4565 /* 11250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4566 /* 11254 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4567 /* 11259 */ GIR_RootConstrainSelectedInstOperands,
4568 /* 11260 */ // GIR_Coverage, 2115,
4569 /* 11260 */ GIR_EraseRootFromParent_Done,
4570 /* 11261 */ // Label 427: @11261
4571 /* 11261 */ GIM_Reject,
4572 /* 11262 */ // Label 15: @11262
4573 /* 11262 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(11329), // Rule ID 2114 //
4574 /* 11267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4575 /* 11270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4576 /* 11273 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4577 /* 11276 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4578 /* 11283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4579 /* 11287 */ // MIs[0] Operand 1
4580 /* 11287 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4581 /* 11291 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4582 /* 11295 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4583 /* 11299 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4584 /* 11303 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4585 /* 11307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4586 /* 11309 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4587 /* 11309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4588 /* 11312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4589 /* 11314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4590 /* 11318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4591 /* 11322 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4592 /* 11327 */ GIR_RootConstrainSelectedInstOperands,
4593 /* 11328 */ // GIR_Coverage, 2114,
4594 /* 11328 */ GIR_EraseRootFromParent_Done,
4595 /* 11329 */ // Label 428: @11329
4596 /* 11329 */ GIM_Reject,
4597 /* 11330 */ // Label 16: @11330
4598 /* 11330 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 431*/ GIMT_Encode4(11521),
4599 /* 11341 */ /*GILLT_s32*//*Label 429*/ GIMT_Encode4(11349),
4600 /* 11345 */ /*GILLT_s64*//*Label 430*/ GIMT_Encode4(11476),
4601 /* 11349 */ // Label 429: @11349
4602 /* 11349 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(11475),
4603 /* 11354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4604 /* 11357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
4605 /* 11360 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(11398), // Rule ID 25 //
4606 /* 11365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4607 /* 11368 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4608 /* 11375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4609 /* 11379 */ // MIs[0] ptr
4610 /* 11379 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4611 /* 11383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4612 /* 11387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4613 /* 11391 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4614 /* 11391 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4615 /* 11396 */ GIR_RootConstrainSelectedInstOperands,
4616 /* 11397 */ // GIR_Coverage, 25,
4617 /* 11397 */ GIR_Done,
4618 /* 11398 */ // Label 433: @11398
4619 /* 11398 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(11436), // Rule ID 26 //
4620 /* 11403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4621 /* 11406 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4622 /* 11413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4623 /* 11417 */ // MIs[0] ptr
4624 /* 11417 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4625 /* 11421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4626 /* 11425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4627 /* 11429 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4628 /* 11429 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4629 /* 11434 */ GIR_RootConstrainSelectedInstOperands,
4630 /* 11435 */ // GIR_Coverage, 26,
4631 /* 11435 */ GIR_Done,
4632 /* 11436 */ // Label 434: @11436
4633 /* 11436 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(11474), // Rule ID 27 //
4634 /* 11441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4635 /* 11444 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4636 /* 11451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4637 /* 11455 */ // MIs[0] ptr
4638 /* 11455 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4639 /* 11459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4640 /* 11463 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4641 /* 11467 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4642 /* 11467 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4643 /* 11472 */ GIR_RootConstrainSelectedInstOperands,
4644 /* 11473 */ // GIR_Coverage, 27,
4645 /* 11473 */ GIR_Done,
4646 /* 11474 */ // Label 435: @11474
4647 /* 11474 */ GIM_Reject,
4648 /* 11475 */ // Label 432: @11475
4649 /* 11475 */ GIM_Reject,
4650 /* 11476 */ // Label 430: @11476
4651 /* 11476 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(11520), // Rule ID 215 //
4652 /* 11481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4653 /* 11484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4654 /* 11487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
4655 /* 11490 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4656 /* 11497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4657 /* 11501 */ // MIs[0] ptr
4658 /* 11501 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4659 /* 11505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4660 /* 11509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4661 /* 11513 */ // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4662 /* 11513 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4663 /* 11518 */ GIR_RootConstrainSelectedInstOperands,
4664 /* 11519 */ // GIR_Coverage, 215,
4665 /* 11519 */ GIR_Done,
4666 /* 11520 */ // Label 436: @11520
4667 /* 11520 */ GIM_Reject,
4668 /* 11521 */ // Label 431: @11521
4669 /* 11521 */ GIM_Reject,
4670 /* 11522 */ // Label 17: @11522
4671 /* 11522 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 439*/ GIMT_Encode4(11691),
4672 /* 11533 */ /*GILLT_s32*//*Label 437*/ GIMT_Encode4(11541),
4673 /* 11537 */ /*GILLT_s64*//*Label 438*/ GIMT_Encode4(11653),
4674 /* 11541 */ // Label 437: @11541
4675 /* 11541 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(11652),
4676 /* 11546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4677 /* 11549 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(11583), // Rule ID 22 //
4678 /* 11554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4679 /* 11557 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4680 /* 11564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4681 /* 11568 */ // MIs[0] ptr
4682 /* 11568 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4683 /* 11572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4684 /* 11576 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4685 /* 11576 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4686 /* 11581 */ GIR_RootConstrainSelectedInstOperands,
4687 /* 11582 */ // GIR_Coverage, 22,
4688 /* 11582 */ GIR_Done,
4689 /* 11583 */ // Label 441: @11583
4690 /* 11583 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(11617), // Rule ID 23 //
4691 /* 11588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4692 /* 11591 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4693 /* 11598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4694 /* 11602 */ // MIs[0] ptr
4695 /* 11602 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4696 /* 11606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4697 /* 11610 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4698 /* 11610 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4699 /* 11615 */ GIR_RootConstrainSelectedInstOperands,
4700 /* 11616 */ // GIR_Coverage, 23,
4701 /* 11616 */ GIR_Done,
4702 /* 11617 */ // Label 442: @11617
4703 /* 11617 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(11651), // Rule ID 24 //
4704 /* 11622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4705 /* 11625 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4706 /* 11632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4707 /* 11636 */ // MIs[0] ptr
4708 /* 11636 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4709 /* 11640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4710 /* 11644 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4711 /* 11644 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4712 /* 11649 */ GIR_RootConstrainSelectedInstOperands,
4713 /* 11650 */ // GIR_Coverage, 24,
4714 /* 11650 */ GIR_Done,
4715 /* 11651 */ // Label 443: @11651
4716 /* 11651 */ GIM_Reject,
4717 /* 11652 */ // Label 440: @11652
4718 /* 11652 */ GIM_Reject,
4719 /* 11653 */ // Label 438: @11653
4720 /* 11653 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(11690), // Rule ID 214 //
4721 /* 11658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4722 /* 11661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4723 /* 11664 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4724 /* 11671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4725 /* 11675 */ // MIs[0] ptr
4726 /* 11675 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4727 /* 11679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4728 /* 11683 */ // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4729 /* 11683 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4730 /* 11688 */ GIR_RootConstrainSelectedInstOperands,
4731 /* 11689 */ // GIR_Coverage, 214,
4732 /* 11689 */ GIR_Done,
4733 /* 11690 */ // Label 444: @11690
4734 /* 11690 */ GIM_Reject,
4735 /* 11691 */ // Label 439: @11691
4736 /* 11691 */ GIM_Reject,
4737 /* 11692 */ // Label 18: @11692
4738 /* 11692 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 447*/ GIMT_Encode4(11861),
4739 /* 11703 */ /*GILLT_s32*//*Label 445*/ GIMT_Encode4(11711),
4740 /* 11707 */ /*GILLT_s64*//*Label 446*/ GIMT_Encode4(11823),
4741 /* 11711 */ // Label 445: @11711
4742 /* 11711 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(11822),
4743 /* 11716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4744 /* 11719 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(11753), // Rule ID 4 //
4745 /* 11724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4746 /* 11727 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4747 /* 11734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4748 /* 11738 */ // MIs[0] ptr
4749 /* 11738 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4750 /* 11742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4751 /* 11746 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4752 /* 11746 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4753 /* 11751 */ GIR_RootConstrainSelectedInstOperands,
4754 /* 11752 */ // GIR_Coverage, 4,
4755 /* 11752 */ GIR_Done,
4756 /* 11753 */ // Label 449: @11753
4757 /* 11753 */ GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(11787), // Rule ID 5 //
4758 /* 11758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4759 /* 11761 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4760 /* 11768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4761 /* 11772 */ // MIs[0] ptr
4762 /* 11772 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4763 /* 11776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4764 /* 11780 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4765 /* 11780 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4766 /* 11785 */ GIR_RootConstrainSelectedInstOperands,
4767 /* 11786 */ // GIR_Coverage, 5,
4768 /* 11786 */ GIR_Done,
4769 /* 11787 */ // Label 450: @11787
4770 /* 11787 */ GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(11821), // Rule ID 6 //
4771 /* 11792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4772 /* 11795 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4773 /* 11802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4774 /* 11806 */ // MIs[0] ptr
4775 /* 11806 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4776 /* 11810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4777 /* 11814 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4778 /* 11814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4779 /* 11819 */ GIR_RootConstrainSelectedInstOperands,
4780 /* 11820 */ // GIR_Coverage, 6,
4781 /* 11820 */ GIR_Done,
4782 /* 11821 */ // Label 451: @11821
4783 /* 11821 */ GIM_Reject,
4784 /* 11822 */ // Label 448: @11822
4785 /* 11822 */ GIM_Reject,
4786 /* 11823 */ // Label 446: @11823
4787 /* 11823 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(11860), // Rule ID 208 //
4788 /* 11828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4789 /* 11831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4790 /* 11834 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4791 /* 11841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4792 /* 11845 */ // MIs[0] ptr
4793 /* 11845 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4794 /* 11849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4795 /* 11853 */ // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4796 /* 11853 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4797 /* 11858 */ GIR_RootConstrainSelectedInstOperands,
4798 /* 11859 */ // GIR_Coverage, 208,
4799 /* 11859 */ GIR_Done,
4800 /* 11860 */ // Label 452: @11860
4801 /* 11860 */ GIM_Reject,
4802 /* 11861 */ // Label 447: @11861
4803 /* 11861 */ GIM_Reject,
4804 /* 11862 */ // Label 19: @11862
4805 /* 11862 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 455*/ GIMT_Encode4(12031),
4806 /* 11873 */ /*GILLT_s32*//*Label 453*/ GIMT_Encode4(11881),
4807 /* 11877 */ /*GILLT_s64*//*Label 454*/ GIMT_Encode4(11993),
4808 /* 11881 */ // Label 453: @11881
4809 /* 11881 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(11992),
4810 /* 11886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4811 /* 11889 */ GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(11923), // Rule ID 7 //
4812 /* 11894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4813 /* 11897 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4814 /* 11904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4815 /* 11908 */ // MIs[0] ptr
4816 /* 11908 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4817 /* 11912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4818 /* 11916 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4819 /* 11916 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4820 /* 11921 */ GIR_RootConstrainSelectedInstOperands,
4821 /* 11922 */ // GIR_Coverage, 7,
4822 /* 11922 */ GIR_Done,
4823 /* 11923 */ // Label 457: @11923
4824 /* 11923 */ GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(11957), // Rule ID 8 //
4825 /* 11928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4826 /* 11931 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4827 /* 11938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4828 /* 11942 */ // MIs[0] ptr
4829 /* 11942 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4830 /* 11946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4831 /* 11950 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4832 /* 11950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4833 /* 11955 */ GIR_RootConstrainSelectedInstOperands,
4834 /* 11956 */ // GIR_Coverage, 8,
4835 /* 11956 */ GIR_Done,
4836 /* 11957 */ // Label 458: @11957
4837 /* 11957 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(11991), // Rule ID 9 //
4838 /* 11962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4839 /* 11965 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4840 /* 11972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4841 /* 11976 */ // MIs[0] ptr
4842 /* 11976 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4843 /* 11980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4844 /* 11984 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4845 /* 11984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4846 /* 11989 */ GIR_RootConstrainSelectedInstOperands,
4847 /* 11990 */ // GIR_Coverage, 9,
4848 /* 11990 */ GIR_Done,
4849 /* 11991 */ // Label 459: @11991
4850 /* 11991 */ GIM_Reject,
4851 /* 11992 */ // Label 456: @11992
4852 /* 11992 */ GIM_Reject,
4853 /* 11993 */ // Label 454: @11993
4854 /* 11993 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(12030), // Rule ID 209 //
4855 /* 11998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4856 /* 12001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4857 /* 12004 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4858 /* 12011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4859 /* 12015 */ // MIs[0] ptr
4860 /* 12015 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4861 /* 12019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4862 /* 12023 */ // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4863 /* 12023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4864 /* 12028 */ GIR_RootConstrainSelectedInstOperands,
4865 /* 12029 */ // GIR_Coverage, 209,
4866 /* 12029 */ GIR_Done,
4867 /* 12030 */ // Label 460: @12030
4868 /* 12030 */ GIM_Reject,
4869 /* 12031 */ // Label 455: @12031
4870 /* 12031 */ GIM_Reject,
4871 /* 12032 */ // Label 20: @12032
4872 /* 12032 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 463*/ GIMT_Encode4(12201),
4873 /* 12043 */ /*GILLT_s32*//*Label 461*/ GIMT_Encode4(12051),
4874 /* 12047 */ /*GILLT_s64*//*Label 462*/ GIMT_Encode4(12163),
4875 /* 12051 */ // Label 461: @12051
4876 /* 12051 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(12162),
4877 /* 12056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4878 /* 12059 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(12093), // Rule ID 10 //
4879 /* 12064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4880 /* 12067 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4881 /* 12074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4882 /* 12078 */ // MIs[0] ptr
4883 /* 12078 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4884 /* 12082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4885 /* 12086 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4886 /* 12086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4887 /* 12091 */ GIR_RootConstrainSelectedInstOperands,
4888 /* 12092 */ // GIR_Coverage, 10,
4889 /* 12092 */ GIR_Done,
4890 /* 12093 */ // Label 465: @12093
4891 /* 12093 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(12127), // Rule ID 11 //
4892 /* 12098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4893 /* 12101 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4894 /* 12108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4895 /* 12112 */ // MIs[0] ptr
4896 /* 12112 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4897 /* 12116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4898 /* 12120 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4899 /* 12120 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4900 /* 12125 */ GIR_RootConstrainSelectedInstOperands,
4901 /* 12126 */ // GIR_Coverage, 11,
4902 /* 12126 */ GIR_Done,
4903 /* 12127 */ // Label 466: @12127
4904 /* 12127 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(12161), // Rule ID 12 //
4905 /* 12132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4906 /* 12135 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4907 /* 12142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4908 /* 12146 */ // MIs[0] ptr
4909 /* 12146 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4910 /* 12150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4911 /* 12154 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4912 /* 12154 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4913 /* 12159 */ GIR_RootConstrainSelectedInstOperands,
4914 /* 12160 */ // GIR_Coverage, 12,
4915 /* 12160 */ GIR_Done,
4916 /* 12161 */ // Label 467: @12161
4917 /* 12161 */ GIM_Reject,
4918 /* 12162 */ // Label 464: @12162
4919 /* 12162 */ GIM_Reject,
4920 /* 12163 */ // Label 462: @12163
4921 /* 12163 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(12200), // Rule ID 210 //
4922 /* 12168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4923 /* 12171 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4924 /* 12174 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4925 /* 12181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4926 /* 12185 */ // MIs[0] ptr
4927 /* 12185 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4928 /* 12189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4929 /* 12193 */ // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4930 /* 12193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4931 /* 12198 */ GIR_RootConstrainSelectedInstOperands,
4932 /* 12199 */ // GIR_Coverage, 210,
4933 /* 12199 */ GIR_Done,
4934 /* 12200 */ // Label 468: @12200
4935 /* 12200 */ GIM_Reject,
4936 /* 12201 */ // Label 463: @12201
4937 /* 12201 */ GIM_Reject,
4938 /* 12202 */ // Label 21: @12202
4939 /* 12202 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 471*/ GIMT_Encode4(12371),
4940 /* 12213 */ /*GILLT_s32*//*Label 469*/ GIMT_Encode4(12221),
4941 /* 12217 */ /*GILLT_s64*//*Label 470*/ GIMT_Encode4(12333),
4942 /* 12221 */ // Label 469: @12221
4943 /* 12221 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(12332),
4944 /* 12226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4945 /* 12229 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(12263), // Rule ID 19 //
4946 /* 12234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4947 /* 12237 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4948 /* 12244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4949 /* 12248 */ // MIs[0] ptr
4950 /* 12248 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4951 /* 12252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4952 /* 12256 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4953 /* 12256 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4954 /* 12261 */ GIR_RootConstrainSelectedInstOperands,
4955 /* 12262 */ // GIR_Coverage, 19,
4956 /* 12262 */ GIR_Done,
4957 /* 12263 */ // Label 473: @12263
4958 /* 12263 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(12297), // Rule ID 20 //
4959 /* 12268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4960 /* 12271 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4961 /* 12278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4962 /* 12282 */ // MIs[0] ptr
4963 /* 12282 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4964 /* 12286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4965 /* 12290 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4966 /* 12290 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4967 /* 12295 */ GIR_RootConstrainSelectedInstOperands,
4968 /* 12296 */ // GIR_Coverage, 20,
4969 /* 12296 */ GIR_Done,
4970 /* 12297 */ // Label 474: @12297
4971 /* 12297 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(12331), // Rule ID 21 //
4972 /* 12302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4973 /* 12305 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4974 /* 12312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4975 /* 12316 */ // MIs[0] ptr
4976 /* 12316 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4977 /* 12320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4978 /* 12324 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4979 /* 12324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4980 /* 12329 */ GIR_RootConstrainSelectedInstOperands,
4981 /* 12330 */ // GIR_Coverage, 21,
4982 /* 12330 */ GIR_Done,
4983 /* 12331 */ // Label 475: @12331
4984 /* 12331 */ GIM_Reject,
4985 /* 12332 */ // Label 472: @12332
4986 /* 12332 */ GIM_Reject,
4987 /* 12333 */ // Label 470: @12333
4988 /* 12333 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(12370), // Rule ID 213 //
4989 /* 12338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4990 /* 12341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4991 /* 12344 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4992 /* 12351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4993 /* 12355 */ // MIs[0] ptr
4994 /* 12355 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4995 /* 12359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4996 /* 12363 */ // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4997 /* 12363 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4998 /* 12368 */ GIR_RootConstrainSelectedInstOperands,
4999 /* 12369 */ // GIR_Coverage, 213,
5000 /* 12369 */ GIR_Done,
5001 /* 12370 */ // Label 476: @12370
5002 /* 12370 */ GIM_Reject,
5003 /* 12371 */ // Label 471: @12371
5004 /* 12371 */ GIM_Reject,
5005 /* 12372 */ // Label 22: @12372
5006 /* 12372 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 479*/ GIMT_Encode4(12541),
5007 /* 12383 */ /*GILLT_s32*//*Label 477*/ GIMT_Encode4(12391),
5008 /* 12387 */ /*GILLT_s64*//*Label 478*/ GIMT_Encode4(12503),
5009 /* 12391 */ // Label 477: @12391
5010 /* 12391 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(12502),
5011 /* 12396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5012 /* 12399 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(12433), // Rule ID 13 //
5013 /* 12404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5014 /* 12407 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5015 /* 12414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5016 /* 12418 */ // MIs[0] ptr
5017 /* 12418 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5018 /* 12422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5019 /* 12426 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5020 /* 12426 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
5021 /* 12431 */ GIR_RootConstrainSelectedInstOperands,
5022 /* 12432 */ // GIR_Coverage, 13,
5023 /* 12432 */ GIR_Done,
5024 /* 12433 */ // Label 481: @12433
5025 /* 12433 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(12467), // Rule ID 14 //
5026 /* 12438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5027 /* 12441 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5028 /* 12448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5029 /* 12452 */ // MIs[0] ptr
5030 /* 12452 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5031 /* 12456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5032 /* 12460 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5033 /* 12460 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
5034 /* 12465 */ GIR_RootConstrainSelectedInstOperands,
5035 /* 12466 */ // GIR_Coverage, 14,
5036 /* 12466 */ GIR_Done,
5037 /* 12467 */ // Label 482: @12467
5038 /* 12467 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(12501), // Rule ID 15 //
5039 /* 12472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5040 /* 12475 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5041 /* 12482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5042 /* 12486 */ // MIs[0] ptr
5043 /* 12486 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5044 /* 12490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5045 /* 12494 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5046 /* 12494 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
5047 /* 12499 */ GIR_RootConstrainSelectedInstOperands,
5048 /* 12500 */ // GIR_Coverage, 15,
5049 /* 12500 */ GIR_Done,
5050 /* 12501 */ // Label 483: @12501
5051 /* 12501 */ GIM_Reject,
5052 /* 12502 */ // Label 480: @12502
5053 /* 12502 */ GIM_Reject,
5054 /* 12503 */ // Label 478: @12503
5055 /* 12503 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(12540), // Rule ID 211 //
5056 /* 12508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5057 /* 12511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5058 /* 12514 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5059 /* 12521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5060 /* 12525 */ // MIs[0] ptr
5061 /* 12525 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5062 /* 12529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5063 /* 12533 */ // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5064 /* 12533 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
5065 /* 12538 */ GIR_RootConstrainSelectedInstOperands,
5066 /* 12539 */ // GIR_Coverage, 211,
5067 /* 12539 */ GIR_Done,
5068 /* 12540 */ // Label 484: @12540
5069 /* 12540 */ GIM_Reject,
5070 /* 12541 */ // Label 479: @12541
5071 /* 12541 */ GIM_Reject,
5072 /* 12542 */ // Label 23: @12542
5073 /* 12542 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 487*/ GIMT_Encode4(12711),
5074 /* 12553 */ /*GILLT_s32*//*Label 485*/ GIMT_Encode4(12561),
5075 /* 12557 */ /*GILLT_s64*//*Label 486*/ GIMT_Encode4(12673),
5076 /* 12561 */ // Label 485: @12561
5077 /* 12561 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(12672),
5078 /* 12566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5079 /* 12569 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(12603), // Rule ID 16 //
5080 /* 12574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5081 /* 12577 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5082 /* 12584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5083 /* 12588 */ // MIs[0] ptr
5084 /* 12588 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5085 /* 12592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5086 /* 12596 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5087 /* 12596 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
5088 /* 12601 */ GIR_RootConstrainSelectedInstOperands,
5089 /* 12602 */ // GIR_Coverage, 16,
5090 /* 12602 */ GIR_Done,
5091 /* 12603 */ // Label 489: @12603
5092 /* 12603 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(12637), // Rule ID 17 //
5093 /* 12608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5094 /* 12611 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5095 /* 12618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5096 /* 12622 */ // MIs[0] ptr
5097 /* 12622 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5098 /* 12626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5099 /* 12630 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5100 /* 12630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
5101 /* 12635 */ GIR_RootConstrainSelectedInstOperands,
5102 /* 12636 */ // GIR_Coverage, 17,
5103 /* 12636 */ GIR_Done,
5104 /* 12637 */ // Label 490: @12637
5105 /* 12637 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(12671), // Rule ID 18 //
5106 /* 12642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5107 /* 12645 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5108 /* 12652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5109 /* 12656 */ // MIs[0] ptr
5110 /* 12656 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5111 /* 12660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5112 /* 12664 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5113 /* 12664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
5114 /* 12669 */ GIR_RootConstrainSelectedInstOperands,
5115 /* 12670 */ // GIR_Coverage, 18,
5116 /* 12670 */ GIR_Done,
5117 /* 12671 */ // Label 491: @12671
5118 /* 12671 */ GIM_Reject,
5119 /* 12672 */ // Label 488: @12672
5120 /* 12672 */ GIM_Reject,
5121 /* 12673 */ // Label 486: @12673
5122 /* 12673 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(12710), // Rule ID 212 //
5123 /* 12678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5124 /* 12681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5125 /* 12684 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5126 /* 12691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5127 /* 12695 */ // MIs[0] ptr
5128 /* 12695 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5129 /* 12699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5130 /* 12703 */ // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5131 /* 12703 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
5132 /* 12708 */ GIR_RootConstrainSelectedInstOperands,
5133 /* 12709 */ // GIR_Coverage, 212,
5134 /* 12709 */ GIR_Done,
5135 /* 12710 */ // Label 492: @12710
5136 /* 12710 */ GIM_Reject,
5137 /* 12711 */ // Label 487: @12711
5138 /* 12711 */ GIM_Reject,
5139 /* 12712 */ // Label 24: @12712
5140 /* 12712 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 495*/ GIMT_Encode4(12881),
5141 /* 12723 */ /*GILLT_s32*//*Label 493*/ GIMT_Encode4(12731),
5142 /* 12727 */ /*GILLT_s64*//*Label 494*/ GIMT_Encode4(12843),
5143 /* 12731 */ // Label 493: @12731
5144 /* 12731 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(12842),
5145 /* 12736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5146 /* 12739 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(12773), // Rule ID 31 //
5147 /* 12744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5148 /* 12747 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5149 /* 12754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5150 /* 12758 */ // MIs[0] ptr
5151 /* 12758 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5152 /* 12762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5153 /* 12766 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5154 /* 12766 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
5155 /* 12771 */ GIR_RootConstrainSelectedInstOperands,
5156 /* 12772 */ // GIR_Coverage, 31,
5157 /* 12772 */ GIR_Done,
5158 /* 12773 */ // Label 497: @12773
5159 /* 12773 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(12807), // Rule ID 32 //
5160 /* 12778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5161 /* 12781 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5162 /* 12788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5163 /* 12792 */ // MIs[0] ptr
5164 /* 12792 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5165 /* 12796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5166 /* 12800 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5167 /* 12800 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
5168 /* 12805 */ GIR_RootConstrainSelectedInstOperands,
5169 /* 12806 */ // GIR_Coverage, 32,
5170 /* 12806 */ GIR_Done,
5171 /* 12807 */ // Label 498: @12807
5172 /* 12807 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(12841), // Rule ID 33 //
5173 /* 12812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5174 /* 12815 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5175 /* 12822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5176 /* 12826 */ // MIs[0] ptr
5177 /* 12826 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5178 /* 12830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5179 /* 12834 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5180 /* 12834 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
5181 /* 12839 */ GIR_RootConstrainSelectedInstOperands,
5182 /* 12840 */ // GIR_Coverage, 33,
5183 /* 12840 */ GIR_Done,
5184 /* 12841 */ // Label 499: @12841
5185 /* 12841 */ GIM_Reject,
5186 /* 12842 */ // Label 496: @12842
5187 /* 12842 */ GIM_Reject,
5188 /* 12843 */ // Label 494: @12843
5189 /* 12843 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(12880), // Rule ID 217 //
5190 /* 12848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5191 /* 12851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5192 /* 12854 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5193 /* 12861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5194 /* 12865 */ // MIs[0] ptr
5195 /* 12865 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5196 /* 12869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5197 /* 12873 */ // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5198 /* 12873 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
5199 /* 12878 */ GIR_RootConstrainSelectedInstOperands,
5200 /* 12879 */ // GIR_Coverage, 217,
5201 /* 12879 */ GIR_Done,
5202 /* 12880 */ // Label 500: @12880
5203 /* 12880 */ GIM_Reject,
5204 /* 12881 */ // Label 495: @12881
5205 /* 12881 */ GIM_Reject,
5206 /* 12882 */ // Label 25: @12882
5207 /* 12882 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 503*/ GIMT_Encode4(13051),
5208 /* 12893 */ /*GILLT_s32*//*Label 501*/ GIMT_Encode4(12901),
5209 /* 12897 */ /*GILLT_s64*//*Label 502*/ GIMT_Encode4(13013),
5210 /* 12901 */ // Label 501: @12901
5211 /* 12901 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(13012),
5212 /* 12906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5213 /* 12909 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(12943), // Rule ID 28 //
5214 /* 12914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5215 /* 12917 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5216 /* 12924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5217 /* 12928 */ // MIs[0] ptr
5218 /* 12928 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5219 /* 12932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5220 /* 12936 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5221 /* 12936 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
5222 /* 12941 */ GIR_RootConstrainSelectedInstOperands,
5223 /* 12942 */ // GIR_Coverage, 28,
5224 /* 12942 */ GIR_Done,
5225 /* 12943 */ // Label 505: @12943
5226 /* 12943 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(12977), // Rule ID 29 //
5227 /* 12948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5228 /* 12951 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5229 /* 12958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5230 /* 12962 */ // MIs[0] ptr
5231 /* 12962 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5232 /* 12966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5233 /* 12970 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5234 /* 12970 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
5235 /* 12975 */ GIR_RootConstrainSelectedInstOperands,
5236 /* 12976 */ // GIR_Coverage, 29,
5237 /* 12976 */ GIR_Done,
5238 /* 12977 */ // Label 506: @12977
5239 /* 12977 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(13011), // Rule ID 30 //
5240 /* 12982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5241 /* 12985 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5242 /* 12992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5243 /* 12996 */ // MIs[0] ptr
5244 /* 12996 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5245 /* 13000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5246 /* 13004 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5247 /* 13004 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
5248 /* 13009 */ GIR_RootConstrainSelectedInstOperands,
5249 /* 13010 */ // GIR_Coverage, 30,
5250 /* 13010 */ GIR_Done,
5251 /* 13011 */ // Label 507: @13011
5252 /* 13011 */ GIM_Reject,
5253 /* 13012 */ // Label 504: @13012
5254 /* 13012 */ GIM_Reject,
5255 /* 13013 */ // Label 502: @13013
5256 /* 13013 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(13050), // Rule ID 216 //
5257 /* 13018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5258 /* 13021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5259 /* 13024 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5260 /* 13031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5261 /* 13035 */ // MIs[0] ptr
5262 /* 13035 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5263 /* 13039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5264 /* 13043 */ // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5265 /* 13043 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
5266 /* 13048 */ GIR_RootConstrainSelectedInstOperands,
5267 /* 13049 */ // GIR_Coverage, 216,
5268 /* 13049 */ GIR_Done,
5269 /* 13050 */ // Label 508: @13050
5270 /* 13050 */ GIM_Reject,
5271 /* 13051 */ // Label 503: @13051
5272 /* 13051 */ GIM_Reject,
5273 /* 13052 */ // Label 26: @13052
5274 /* 13052 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 511*/ GIMT_Encode4(13221),
5275 /* 13063 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(13071),
5276 /* 13067 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(13183),
5277 /* 13071 */ // Label 509: @13071
5278 /* 13071 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(13182),
5279 /* 13076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5280 /* 13079 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(13113), // Rule ID 37 //
5281 /* 13084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5282 /* 13087 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5283 /* 13094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5284 /* 13098 */ // MIs[0] ptr
5285 /* 13098 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5286 /* 13102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5287 /* 13106 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5288 /* 13106 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
5289 /* 13111 */ GIR_RootConstrainSelectedInstOperands,
5290 /* 13112 */ // GIR_Coverage, 37,
5291 /* 13112 */ GIR_Done,
5292 /* 13113 */ // Label 513: @13113
5293 /* 13113 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(13147), // Rule ID 38 //
5294 /* 13118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5295 /* 13121 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5296 /* 13128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5297 /* 13132 */ // MIs[0] ptr
5298 /* 13132 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5299 /* 13136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5300 /* 13140 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5301 /* 13140 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5302 /* 13145 */ GIR_RootConstrainSelectedInstOperands,
5303 /* 13146 */ // GIR_Coverage, 38,
5304 /* 13146 */ GIR_Done,
5305 /* 13147 */ // Label 514: @13147
5306 /* 13147 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(13181), // Rule ID 39 //
5307 /* 13152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5308 /* 13155 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5309 /* 13162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5310 /* 13166 */ // MIs[0] ptr
5311 /* 13166 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5312 /* 13170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5313 /* 13174 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5314 /* 13174 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5315 /* 13179 */ GIR_RootConstrainSelectedInstOperands,
5316 /* 13180 */ // GIR_Coverage, 39,
5317 /* 13180 */ GIR_Done,
5318 /* 13181 */ // Label 515: @13181
5319 /* 13181 */ GIM_Reject,
5320 /* 13182 */ // Label 512: @13182
5321 /* 13182 */ GIM_Reject,
5322 /* 13183 */ // Label 510: @13183
5323 /* 13183 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(13220), // Rule ID 219 //
5324 /* 13188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5325 /* 13191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5326 /* 13194 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5327 /* 13201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5328 /* 13205 */ // MIs[0] ptr
5329 /* 13205 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5330 /* 13209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5331 /* 13213 */ // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5332 /* 13213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5333 /* 13218 */ GIR_RootConstrainSelectedInstOperands,
5334 /* 13219 */ // GIR_Coverage, 219,
5335 /* 13219 */ GIR_Done,
5336 /* 13220 */ // Label 516: @13220
5337 /* 13220 */ GIM_Reject,
5338 /* 13221 */ // Label 511: @13221
5339 /* 13221 */ GIM_Reject,
5340 /* 13222 */ // Label 27: @13222
5341 /* 13222 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 519*/ GIMT_Encode4(13391),
5342 /* 13233 */ /*GILLT_s32*//*Label 517*/ GIMT_Encode4(13241),
5343 /* 13237 */ /*GILLT_s64*//*Label 518*/ GIMT_Encode4(13353),
5344 /* 13241 */ // Label 517: @13241
5345 /* 13241 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(13352),
5346 /* 13246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5347 /* 13249 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(13283), // Rule ID 34 //
5348 /* 13254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5349 /* 13257 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5350 /* 13264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5351 /* 13268 */ // MIs[0] ptr
5352 /* 13268 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5353 /* 13272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5354 /* 13276 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5355 /* 13276 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5356 /* 13281 */ GIR_RootConstrainSelectedInstOperands,
5357 /* 13282 */ // GIR_Coverage, 34,
5358 /* 13282 */ GIR_Done,
5359 /* 13283 */ // Label 521: @13283
5360 /* 13283 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(13317), // Rule ID 35 //
5361 /* 13288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5362 /* 13291 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5363 /* 13298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5364 /* 13302 */ // MIs[0] ptr
5365 /* 13302 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5366 /* 13306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5367 /* 13310 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5368 /* 13310 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5369 /* 13315 */ GIR_RootConstrainSelectedInstOperands,
5370 /* 13316 */ // GIR_Coverage, 35,
5371 /* 13316 */ GIR_Done,
5372 /* 13317 */ // Label 522: @13317
5373 /* 13317 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(13351), // Rule ID 36 //
5374 /* 13322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5375 /* 13325 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5376 /* 13332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5377 /* 13336 */ // MIs[0] ptr
5378 /* 13336 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5379 /* 13340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5380 /* 13344 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5381 /* 13344 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5382 /* 13349 */ GIR_RootConstrainSelectedInstOperands,
5383 /* 13350 */ // GIR_Coverage, 36,
5384 /* 13350 */ GIR_Done,
5385 /* 13351 */ // Label 523: @13351
5386 /* 13351 */ GIM_Reject,
5387 /* 13352 */ // Label 520: @13352
5388 /* 13352 */ GIM_Reject,
5389 /* 13353 */ // Label 518: @13353
5390 /* 13353 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(13390), // Rule ID 218 //
5391 /* 13358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5392 /* 13361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5393 /* 13364 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5394 /* 13371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5395 /* 13375 */ // MIs[0] ptr
5396 /* 13375 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5397 /* 13379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5398 /* 13383 */ // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5399 /* 13383 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5400 /* 13388 */ GIR_RootConstrainSelectedInstOperands,
5401 /* 13389 */ // GIR_Coverage, 218,
5402 /* 13389 */ GIR_Done,
5403 /* 13390 */ // Label 524: @13390
5404 /* 13390 */ GIM_Reject,
5405 /* 13391 */ // Label 519: @13391
5406 /* 13391 */ GIM_Reject,
5407 /* 13392 */ // Label 28: @13392
5408 /* 13392 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 527*/ GIMT_Encode4(19936),
5409 /* 13403 */ /*GILLT_s32*//*Label 525*/ GIMT_Encode4(13411),
5410 /* 13407 */ /*GILLT_s64*//*Label 526*/ GIMT_Encode4(19902),
5411 /* 13411 */ // Label 525: @13411
5412 /* 13411 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(13519), // Rule ID 2503 //
5413 /* 13416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5414 /* 13419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5415 /* 13423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5416 /* 13427 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5417 /* 13431 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5418 /* 13435 */ // MIs[1] Operand 1
5419 /* 13435 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5420 /* 13440 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5421 /* 13444 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5422 /* 13448 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5423 /* 13452 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5424 /* 13456 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5425 /* 13460 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5426 /* 13464 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5427 /* 13468 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5428 /* 13472 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5429 /* 13476 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5430 /* 13480 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5431 /* 13484 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5432 /* 13488 */ // MIs[4] Operand 1
5433 /* 13488 */ // No operand predicates
5434 /* 13488 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5435 /* 13493 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5436 /* 13497 */ // MIs[0] offset
5437 /* 13497 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5438 /* 13500 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5439 /* 13502 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5440 /* 13502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5441 /* 13505 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5442 /* 13509 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5443 /* 13512 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5444 /* 13514 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5445 /* 13517 */ GIR_RootConstrainSelectedInstOperands,
5446 /* 13518 */ // GIR_Coverage, 2503,
5447 /* 13518 */ GIR_EraseRootFromParent_Done,
5448 /* 13519 */ // Label 528: @13519
5449 /* 13519 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(13634), // Rule ID 2504 //
5450 /* 13524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5451 /* 13527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5452 /* 13531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5453 /* 13535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5454 /* 13539 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5455 /* 13543 */ // MIs[1] Operand 1
5456 /* 13543 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5457 /* 13548 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5458 /* 13552 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5459 /* 13556 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5460 /* 13560 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5461 /* 13564 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5462 /* 13568 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5463 /* 13572 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5464 /* 13576 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5465 /* 13580 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5466 /* 13591 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5467 /* 13595 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5468 /* 13599 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5469 /* 13603 */ // MIs[4] Operand 1
5470 /* 13603 */ // No operand predicates
5471 /* 13603 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5472 /* 13608 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5473 /* 13612 */ // MIs[0] offset
5474 /* 13612 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5475 /* 13615 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5476 /* 13617 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5477 /* 13617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5478 /* 13620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5479 /* 13624 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5480 /* 13627 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5481 /* 13629 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5482 /* 13632 */ GIR_RootConstrainSelectedInstOperands,
5483 /* 13633 */ // GIR_Coverage, 2504,
5484 /* 13633 */ GIR_EraseRootFromParent_Done,
5485 /* 13634 */ // Label 529: @13634
5486 /* 13634 */ GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(13742), // Rule ID 2505 //
5487 /* 13639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5488 /* 13642 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5489 /* 13646 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5490 /* 13650 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5491 /* 13654 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5492 /* 13658 */ // MIs[1] Operand 1
5493 /* 13658 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5494 /* 13663 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5495 /* 13667 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5496 /* 13671 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5497 /* 13675 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5498 /* 13679 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5499 /* 13683 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5500 /* 13687 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5501 /* 13691 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5502 /* 13695 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5503 /* 13699 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5504 /* 13703 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5505 /* 13707 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5506 /* 13711 */ // MIs[4] Operand 1
5507 /* 13711 */ // No operand predicates
5508 /* 13711 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5509 /* 13716 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5510 /* 13720 */ // MIs[0] offset
5511 /* 13720 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5512 /* 13723 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5513 /* 13725 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5514 /* 13725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5515 /* 13728 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5516 /* 13732 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5517 /* 13735 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5518 /* 13737 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5519 /* 13740 */ GIR_RootConstrainSelectedInstOperands,
5520 /* 13741 */ // GIR_Coverage, 2505,
5521 /* 13741 */ GIR_EraseRootFromParent_Done,
5522 /* 13742 */ // Label 530: @13742
5523 /* 13742 */ GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(13857), // Rule ID 2506 //
5524 /* 13747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5525 /* 13750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5526 /* 13754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5527 /* 13758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5528 /* 13762 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5529 /* 13766 */ // MIs[1] Operand 1
5530 /* 13766 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5531 /* 13771 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5532 /* 13775 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5533 /* 13779 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5534 /* 13783 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5535 /* 13787 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5536 /* 13791 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5537 /* 13795 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5538 /* 13799 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5539 /* 13803 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5540 /* 13814 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5541 /* 13818 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5542 /* 13822 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5543 /* 13826 */ // MIs[4] Operand 1
5544 /* 13826 */ // No operand predicates
5545 /* 13826 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5546 /* 13831 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5547 /* 13835 */ // MIs[0] offset
5548 /* 13835 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5549 /* 13838 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5550 /* 13840 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5551 /* 13840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5552 /* 13843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5553 /* 13847 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5554 /* 13850 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5555 /* 13852 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5556 /* 13855 */ GIR_RootConstrainSelectedInstOperands,
5557 /* 13856 */ // GIR_Coverage, 2506,
5558 /* 13856 */ GIR_EraseRootFromParent_Done,
5559 /* 13857 */ // Label 531: @13857
5560 /* 13857 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(13965), // Rule ID 294 //
5561 /* 13862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5562 /* 13865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5563 /* 13869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5564 /* 13873 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5565 /* 13877 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5566 /* 13881 */ // MIs[1] Operand 1
5567 /* 13881 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5568 /* 13886 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5569 /* 13890 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5570 /* 13894 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5571 /* 13898 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5572 /* 13902 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5573 /* 13907 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5574 /* 13911 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5575 /* 13915 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5576 /* 13919 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5577 /* 13923 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5578 /* 13927 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5579 /* 13931 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5580 /* 13935 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5581 /* 13939 */ // MIs[4] Operand 1
5582 /* 13939 */ // No operand predicates
5583 /* 13939 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5584 /* 13943 */ // MIs[0] offset
5585 /* 13943 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5586 /* 13946 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5587 /* 13948 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5588 /* 13948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5589 /* 13951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5590 /* 13955 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5591 /* 13958 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5592 /* 13960 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5593 /* 13963 */ GIR_RootConstrainSelectedInstOperands,
5594 /* 13964 */ // GIR_Coverage, 294,
5595 /* 13964 */ GIR_EraseRootFromParent_Done,
5596 /* 13965 */ // Label 532: @13965
5597 /* 13965 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(14080), // Rule ID 295 //
5598 /* 13970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5599 /* 13973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5600 /* 13977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5601 /* 13981 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5602 /* 13985 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5603 /* 13989 */ // MIs[1] Operand 1
5604 /* 13989 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5605 /* 13994 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5606 /* 13998 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5607 /* 14002 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5608 /* 14006 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5609 /* 14010 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5610 /* 14015 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5611 /* 14019 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5612 /* 14023 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5613 /* 14027 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5614 /* 14031 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5615 /* 14042 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5616 /* 14046 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5617 /* 14050 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5618 /* 14054 */ // MIs[4] Operand 1
5619 /* 14054 */ // No operand predicates
5620 /* 14054 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5621 /* 14058 */ // MIs[0] offset
5622 /* 14058 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5623 /* 14061 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5624 /* 14063 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5625 /* 14063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5626 /* 14066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5627 /* 14070 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5628 /* 14073 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5629 /* 14075 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5630 /* 14078 */ GIR_RootConstrainSelectedInstOperands,
5631 /* 14079 */ // GIR_Coverage, 295,
5632 /* 14079 */ GIR_EraseRootFromParent_Done,
5633 /* 14080 */ // Label 533: @14080
5634 /* 14080 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(14188), // Rule ID 296 //
5635 /* 14085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5636 /* 14088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5637 /* 14092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5638 /* 14096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5639 /* 14100 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5640 /* 14104 */ // MIs[1] Operand 1
5641 /* 14104 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5642 /* 14109 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5643 /* 14113 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5644 /* 14117 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5645 /* 14121 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5646 /* 14125 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5647 /* 14130 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5648 /* 14134 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5649 /* 14138 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5650 /* 14142 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5651 /* 14146 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5652 /* 14150 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5653 /* 14154 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5654 /* 14158 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5655 /* 14162 */ // MIs[4] Operand 1
5656 /* 14162 */ // No operand predicates
5657 /* 14162 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5658 /* 14166 */ // MIs[0] offset
5659 /* 14166 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5660 /* 14169 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5661 /* 14171 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5662 /* 14171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5663 /* 14174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5664 /* 14178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5665 /* 14181 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5666 /* 14183 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5667 /* 14186 */ GIR_RootConstrainSelectedInstOperands,
5668 /* 14187 */ // GIR_Coverage, 296,
5669 /* 14187 */ GIR_EraseRootFromParent_Done,
5670 /* 14188 */ // Label 534: @14188
5671 /* 14188 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(14303), // Rule ID 297 //
5672 /* 14193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5673 /* 14196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5674 /* 14200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5675 /* 14204 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5676 /* 14208 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5677 /* 14212 */ // MIs[1] Operand 1
5678 /* 14212 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5679 /* 14217 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5680 /* 14221 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5681 /* 14225 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5682 /* 14229 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5683 /* 14233 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5684 /* 14238 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5685 /* 14242 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5686 /* 14246 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5687 /* 14250 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5688 /* 14254 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5689 /* 14265 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5690 /* 14269 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5691 /* 14273 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5692 /* 14277 */ // MIs[4] Operand 1
5693 /* 14277 */ // No operand predicates
5694 /* 14277 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5695 /* 14281 */ // MIs[0] offset
5696 /* 14281 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5697 /* 14284 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5698 /* 14286 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5699 /* 14286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5700 /* 14289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5701 /* 14293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5702 /* 14296 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5703 /* 14298 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5704 /* 14301 */ GIR_RootConstrainSelectedInstOperands,
5705 /* 14302 */ // GIR_Coverage, 297,
5706 /* 14302 */ GIR_EraseRootFromParent_Done,
5707 /* 14303 */ // Label 535: @14303
5708 /* 14303 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(14360), // Rule ID 94 //
5709 /* 14308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5710 /* 14311 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5711 /* 14315 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5712 /* 14319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5713 /* 14323 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5714 /* 14327 */ // MIs[1] Operand 1
5715 /* 14327 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5716 /* 14332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5717 /* 14337 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5718 /* 14341 */ // MIs[0] offset
5719 /* 14341 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5720 /* 14344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5721 /* 14346 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5722 /* 14346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5723 /* 14349 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5724 /* 14353 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5725 /* 14355 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5726 /* 14358 */ GIR_RootConstrainSelectedInstOperands,
5727 /* 14359 */ // GIR_Coverage, 94,
5728 /* 14359 */ GIR_EraseRootFromParent_Done,
5729 /* 14360 */ // Label 536: @14360
5730 /* 14360 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(14417), // Rule ID 95 //
5731 /* 14365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5732 /* 14368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5733 /* 14372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5734 /* 14376 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5735 /* 14380 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5736 /* 14384 */ // MIs[1] Operand 1
5737 /* 14384 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5738 /* 14389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5739 /* 14394 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5740 /* 14398 */ // MIs[0] offset
5741 /* 14398 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5742 /* 14401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5743 /* 14403 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5744 /* 14403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
5745 /* 14406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5746 /* 14410 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5747 /* 14412 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5748 /* 14415 */ GIR_RootConstrainSelectedInstOperands,
5749 /* 14416 */ // GIR_Coverage, 95,
5750 /* 14416 */ GIR_EraseRootFromParent_Done,
5751 /* 14417 */ // Label 537: @14417
5752 /* 14417 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(14474), // Rule ID 96 //
5753 /* 14422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5754 /* 14425 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5755 /* 14429 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5756 /* 14433 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5757 /* 14437 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5758 /* 14441 */ // MIs[1] Operand 1
5759 /* 14441 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5760 /* 14446 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5761 /* 14451 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5762 /* 14455 */ // MIs[0] offset
5763 /* 14455 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5764 /* 14458 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5765 /* 14460 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5766 /* 14460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5767 /* 14463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5768 /* 14467 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5769 /* 14469 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5770 /* 14472 */ GIR_RootConstrainSelectedInstOperands,
5771 /* 14473 */ // GIR_Coverage, 96,
5772 /* 14473 */ GIR_EraseRootFromParent_Done,
5773 /* 14474 */ // Label 538: @14474
5774 /* 14474 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(14531), // Rule ID 97 //
5775 /* 14479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5776 /* 14482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5777 /* 14486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5778 /* 14490 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5779 /* 14494 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5780 /* 14498 */ // MIs[1] Operand 1
5781 /* 14498 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5782 /* 14503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5783 /* 14508 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5784 /* 14512 */ // MIs[0] offset
5785 /* 14512 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5786 /* 14515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5787 /* 14517 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5788 /* 14517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
5789 /* 14520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5790 /* 14524 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5791 /* 14526 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5792 /* 14529 */ GIR_RootConstrainSelectedInstOperands,
5793 /* 14530 */ // GIR_Coverage, 97,
5794 /* 14530 */ GIR_EraseRootFromParent_Done,
5795 /* 14531 */ // Label 539: @14531
5796 /* 14531 */ GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(14588), // Rule ID 269 //
5797 /* 14536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5798 /* 14539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5799 /* 14543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5800 /* 14547 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5801 /* 14551 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5802 /* 14555 */ // MIs[1] Operand 1
5803 /* 14555 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5804 /* 14560 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5805 /* 14565 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5806 /* 14569 */ // MIs[0] offset
5807 /* 14569 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5808 /* 14572 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5809 /* 14574 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5810 /* 14574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5811 /* 14577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5812 /* 14581 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5813 /* 14583 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5814 /* 14586 */ GIR_RootConstrainSelectedInstOperands,
5815 /* 14587 */ // GIR_Coverage, 269,
5816 /* 14587 */ GIR_EraseRootFromParent_Done,
5817 /* 14588 */ // Label 540: @14588
5818 /* 14588 */ GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(14645), // Rule ID 270 //
5819 /* 14593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5820 /* 14596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5821 /* 14600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5822 /* 14604 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5823 /* 14608 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5824 /* 14612 */ // MIs[1] Operand 1
5825 /* 14612 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5826 /* 14617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5827 /* 14622 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5828 /* 14626 */ // MIs[0] offset
5829 /* 14626 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5830 /* 14629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5831 /* 14631 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5832 /* 14631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
5833 /* 14634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5834 /* 14638 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5835 /* 14640 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5836 /* 14643 */ GIR_RootConstrainSelectedInstOperands,
5837 /* 14644 */ // GIR_Coverage, 270,
5838 /* 14644 */ GIR_EraseRootFromParent_Done,
5839 /* 14645 */ // Label 541: @14645
5840 /* 14645 */ GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(14702), // Rule ID 271 //
5841 /* 14650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5842 /* 14653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5843 /* 14657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5844 /* 14661 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5845 /* 14665 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5846 /* 14669 */ // MIs[1] Operand 1
5847 /* 14669 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5848 /* 14674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5849 /* 14679 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5850 /* 14683 */ // MIs[0] offset
5851 /* 14683 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5852 /* 14686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5853 /* 14688 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5854 /* 14688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5855 /* 14691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5856 /* 14695 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5857 /* 14697 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5858 /* 14700 */ GIR_RootConstrainSelectedInstOperands,
5859 /* 14701 */ // GIR_Coverage, 271,
5860 /* 14701 */ GIR_EraseRootFromParent_Done,
5861 /* 14702 */ // Label 542: @14702
5862 /* 14702 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(14759), // Rule ID 272 //
5863 /* 14707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5864 /* 14710 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5865 /* 14714 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5866 /* 14718 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5867 /* 14722 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5868 /* 14726 */ // MIs[1] Operand 1
5869 /* 14726 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5870 /* 14731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5871 /* 14736 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5872 /* 14740 */ // MIs[0] offset
5873 /* 14740 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5874 /* 14743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5875 /* 14745 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5876 /* 14745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5877 /* 14748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5878 /* 14752 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5879 /* 14754 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5880 /* 14757 */ GIR_RootConstrainSelectedInstOperands,
5881 /* 14758 */ // GIR_Coverage, 272,
5882 /* 14758 */ GIR_EraseRootFromParent_Done,
5883 /* 14759 */ // Label 543: @14759
5884 /* 14759 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(14816), // Rule ID 1133 //
5885 /* 14764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5886 /* 14767 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5887 /* 14771 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5888 /* 14775 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5889 /* 14779 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5890 /* 14783 */ // MIs[1] Operand 1
5891 /* 14783 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5892 /* 14788 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5893 /* 14793 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5894 /* 14797 */ // MIs[0] offset
5895 /* 14797 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5896 /* 14800 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5897 /* 14802 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5898 /* 14802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5899 /* 14805 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5900 /* 14809 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5901 /* 14811 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5902 /* 14814 */ GIR_RootConstrainSelectedInstOperands,
5903 /* 14815 */ // GIR_Coverage, 1133,
5904 /* 14815 */ GIR_EraseRootFromParent_Done,
5905 /* 14816 */ // Label 544: @14816
5906 /* 14816 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(14873), // Rule ID 1134 //
5907 /* 14821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5908 /* 14824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5909 /* 14828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5910 /* 14832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5911 /* 14836 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5912 /* 14840 */ // MIs[1] Operand 1
5913 /* 14840 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5914 /* 14845 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5915 /* 14850 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5916 /* 14854 */ // MIs[0] offset
5917 /* 14854 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5918 /* 14857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5919 /* 14859 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5920 /* 14859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5921 /* 14862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5922 /* 14866 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5923 /* 14868 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5924 /* 14871 */ GIR_RootConstrainSelectedInstOperands,
5925 /* 14872 */ // GIR_Coverage, 1134,
5926 /* 14872 */ GIR_EraseRootFromParent_Done,
5927 /* 14873 */ // Label 545: @14873
5928 /* 14873 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(14930), // Rule ID 1135 //
5929 /* 14878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5930 /* 14881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5931 /* 14885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5932 /* 14889 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5933 /* 14893 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5934 /* 14897 */ // MIs[1] Operand 1
5935 /* 14897 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5936 /* 14902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5937 /* 14907 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5938 /* 14911 */ // MIs[0] offset
5939 /* 14911 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5940 /* 14914 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5941 /* 14916 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5942 /* 14916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5943 /* 14919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5944 /* 14923 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5945 /* 14925 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5946 /* 14928 */ GIR_RootConstrainSelectedInstOperands,
5947 /* 14929 */ // GIR_Coverage, 1135,
5948 /* 14929 */ GIR_EraseRootFromParent_Done,
5949 /* 14930 */ // Label 546: @14930
5950 /* 14930 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(14987), // Rule ID 1136 //
5951 /* 14935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5952 /* 14938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5953 /* 14942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5954 /* 14946 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5955 /* 14950 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5956 /* 14954 */ // MIs[1] Operand 1
5957 /* 14954 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5958 /* 14959 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5959 /* 14964 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5960 /* 14968 */ // MIs[0] offset
5961 /* 14968 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5962 /* 14971 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5963 /* 14973 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5964 /* 14973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5965 /* 14976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5966 /* 14980 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5967 /* 14982 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5968 /* 14985 */ GIR_RootConstrainSelectedInstOperands,
5969 /* 14986 */ // GIR_Coverage, 1136,
5970 /* 14986 */ GIR_EraseRootFromParent_Done,
5971 /* 14987 */ // Label 547: @14987
5972 /* 14987 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(15050), // Rule ID 1425 //
5973 /* 14992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5974 /* 14995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5975 /* 14999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5976 /* 15003 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5977 /* 15007 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5978 /* 15011 */ // MIs[1] Operand 1
5979 /* 15011 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5980 /* 15016 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5981 /* 15021 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5982 /* 15025 */ // MIs[0] dst
5983 /* 15025 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5984 /* 15028 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5985 /* 15030 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5986 /* 15030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5987 /* 15033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5988 /* 15037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5989 /* 15043 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5990 /* 15045 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5991 /* 15048 */ GIR_RootConstrainSelectedInstOperands,
5992 /* 15049 */ // GIR_Coverage, 1425,
5993 /* 15049 */ GIR_EraseRootFromParent_Done,
5994 /* 15050 */ // Label 548: @15050
5995 /* 15050 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(15113), // Rule ID 1426 //
5996 /* 15055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5997 /* 15058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5998 /* 15062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5999 /* 15066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6000 /* 15070 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6001 /* 15074 */ // MIs[1] Operand 1
6002 /* 15074 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6003 /* 15079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6004 /* 15084 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6005 /* 15088 */ // MIs[0] dst
6006 /* 15088 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6007 /* 15091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6008 /* 15093 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6009 /* 15093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6010 /* 15096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6011 /* 15100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6012 /* 15106 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6013 /* 15108 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6014 /* 15111 */ GIR_RootConstrainSelectedInstOperands,
6015 /* 15112 */ // GIR_Coverage, 1426,
6016 /* 15112 */ GIR_EraseRootFromParent_Done,
6017 /* 15113 */ // Label 549: @15113
6018 /* 15113 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(15176), // Rule ID 1651 //
6019 /* 15118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6020 /* 15121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6021 /* 15125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6022 /* 15129 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6023 /* 15133 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6024 /* 15137 */ // MIs[1] Operand 1
6025 /* 15137 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6026 /* 15142 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6027 /* 15147 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6028 /* 15151 */ // MIs[0] dst
6029 /* 15151 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6030 /* 15154 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6031 /* 15156 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6032 /* 15156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6033 /* 15159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6034 /* 15163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6035 /* 15169 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6036 /* 15171 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6037 /* 15174 */ GIR_RootConstrainSelectedInstOperands,
6038 /* 15175 */ // GIR_Coverage, 1651,
6039 /* 15175 */ GIR_EraseRootFromParent_Done,
6040 /* 15176 */ // Label 550: @15176
6041 /* 15176 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(15239), // Rule ID 1652 //
6042 /* 15181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6043 /* 15184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6044 /* 15188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6045 /* 15192 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6046 /* 15196 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6047 /* 15200 */ // MIs[1] Operand 1
6048 /* 15200 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6049 /* 15205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6050 /* 15210 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6051 /* 15214 */ // MIs[0] dst
6052 /* 15214 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6053 /* 15217 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6054 /* 15219 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6055 /* 15219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6056 /* 15222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6057 /* 15226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6058 /* 15232 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6059 /* 15234 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6060 /* 15237 */ GIR_RootConstrainSelectedInstOperands,
6061 /* 15238 */ // GIR_Coverage, 1652,
6062 /* 15238 */ GIR_EraseRootFromParent_Done,
6063 /* 15239 */ // Label 551: @15239
6064 /* 15239 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(15293), // Rule ID 1983 //
6065 /* 15244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6066 /* 15247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6067 /* 15251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6068 /* 15255 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6069 /* 15259 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6070 /* 15263 */ // MIs[1] Operand 1
6071 /* 15263 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6072 /* 15268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6073 /* 15273 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6074 /* 15277 */ // MIs[0] targ16
6075 /* 15277 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6076 /* 15280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6077 /* 15282 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6078 /* 15282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
6079 /* 15285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6080 /* 15289 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6081 /* 15291 */ GIR_RootConstrainSelectedInstOperands,
6082 /* 15292 */ // GIR_Coverage, 1983,
6083 /* 15292 */ GIR_EraseRootFromParent_Done,
6084 /* 15293 */ // Label 552: @15293
6085 /* 15293 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(15347), // Rule ID 1992 //
6086 /* 15298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6087 /* 15301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6088 /* 15305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6089 /* 15309 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6090 /* 15313 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6091 /* 15317 */ // MIs[1] Operand 1
6092 /* 15317 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6093 /* 15322 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6094 /* 15327 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6095 /* 15331 */ // MIs[0] targ16
6096 /* 15331 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6097 /* 15334 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6098 /* 15336 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6099 /* 15336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
6100 /* 15339 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6101 /* 15343 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6102 /* 15345 */ GIR_RootConstrainSelectedInstOperands,
6103 /* 15346 */ // GIR_Coverage, 1992,
6104 /* 15346 */ GIR_EraseRootFromParent_Done,
6105 /* 15347 */ // Label 553: @15347
6106 /* 15347 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(15410), // Rule ID 2322 //
6107 /* 15352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6108 /* 15355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6109 /* 15359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6110 /* 15363 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6111 /* 15367 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6112 /* 15371 */ // MIs[1] Operand 1
6113 /* 15371 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6114 /* 15376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6115 /* 15381 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6116 /* 15385 */ // MIs[0] dst
6117 /* 15385 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6118 /* 15388 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6119 /* 15390 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6120 /* 15390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6121 /* 15393 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6122 /* 15397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6123 /* 15403 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6124 /* 15405 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6125 /* 15408 */ GIR_RootConstrainSelectedInstOperands,
6126 /* 15409 */ // GIR_Coverage, 2322,
6127 /* 15409 */ GIR_EraseRootFromParent_Done,
6128 /* 15410 */ // Label 554: @15410
6129 /* 15410 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(15473), // Rule ID 2323 //
6130 /* 15415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6131 /* 15418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6132 /* 15422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6133 /* 15426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6134 /* 15430 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6135 /* 15434 */ // MIs[1] Operand 1
6136 /* 15434 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6137 /* 15439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6138 /* 15444 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6139 /* 15448 */ // MIs[0] dst
6140 /* 15448 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6141 /* 15451 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6142 /* 15453 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6143 /* 15453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6144 /* 15456 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6145 /* 15460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6146 /* 15466 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6147 /* 15468 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6148 /* 15471 */ GIR_RootConstrainSelectedInstOperands,
6149 /* 15472 */ // GIR_Coverage, 2323,
6150 /* 15472 */ GIR_EraseRootFromParent_Done,
6151 /* 15473 */ // Label 555: @15473
6152 /* 15473 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(15530), // Rule ID 2474 //
6153 /* 15478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6154 /* 15481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6155 /* 15485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6156 /* 15489 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6157 /* 15493 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6158 /* 15497 */ // MIs[1] Operand 1
6159 /* 15497 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6160 /* 15502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6161 /* 15507 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6162 /* 15511 */ // MIs[0] dst
6163 /* 15511 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6164 /* 15514 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6165 /* 15516 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6166 /* 15516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
6167 /* 15519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6168 /* 15523 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6169 /* 15525 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6170 /* 15528 */ GIR_RootConstrainSelectedInstOperands,
6171 /* 15529 */ // GIR_Coverage, 2474,
6172 /* 15529 */ GIR_EraseRootFromParent_Done,
6173 /* 15530 */ // Label 556: @15530
6174 /* 15530 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(15587), // Rule ID 2475 //
6175 /* 15535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6176 /* 15538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6177 /* 15542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6178 /* 15546 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6179 /* 15550 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6180 /* 15554 */ // MIs[1] Operand 1
6181 /* 15554 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6182 /* 15559 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6183 /* 15564 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6184 /* 15568 */ // MIs[0] dst
6185 /* 15568 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6186 /* 15571 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6187 /* 15573 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6188 /* 15573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6189 /* 15576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6190 /* 15580 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6191 /* 15582 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6192 /* 15585 */ GIR_RootConstrainSelectedInstOperands,
6193 /* 15586 */ // GIR_Coverage, 2475,
6194 /* 15586 */ GIR_EraseRootFromParent_Done,
6195 /* 15587 */ // Label 557: @15587
6196 /* 15587 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(15639), // Rule ID 1436 //
6197 /* 15592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6198 /* 15595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6199 /* 15599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6200 /* 15603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6201 /* 15607 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6202 /* 15611 */ // MIs[1] Operand 1
6203 /* 15611 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6204 /* 15616 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6205 /* 15620 */ // MIs[0] dst
6206 /* 15620 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6207 /* 15623 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6208 /* 15625 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6209 /* 15625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
6210 /* 15628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6211 /* 15632 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6212 /* 15634 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6213 /* 15637 */ GIR_RootConstrainSelectedInstOperands,
6214 /* 15638 */ // GIR_Coverage, 1436,
6215 /* 15638 */ GIR_EraseRootFromParent_Done,
6216 /* 15639 */ // Label 558: @15639
6217 /* 15639 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(15691), // Rule ID 1437 //
6218 /* 15644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6219 /* 15647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6220 /* 15651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6221 /* 15655 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6222 /* 15659 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6223 /* 15663 */ // MIs[1] Operand 1
6224 /* 15663 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6225 /* 15668 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6226 /* 15672 */ // MIs[0] dst
6227 /* 15672 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6228 /* 15675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6229 /* 15677 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6230 /* 15677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
6231 /* 15680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6232 /* 15684 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6233 /* 15686 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6234 /* 15689 */ GIR_RootConstrainSelectedInstOperands,
6235 /* 15690 */ // GIR_Coverage, 1437,
6236 /* 15690 */ GIR_EraseRootFromParent_Done,
6237 /* 15691 */ // Label 559: @15691
6238 /* 15691 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(15743), // Rule ID 1662 //
6239 /* 15696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6240 /* 15699 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6241 /* 15703 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6242 /* 15707 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6243 /* 15711 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6244 /* 15715 */ // MIs[1] Operand 1
6245 /* 15715 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6246 /* 15720 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6247 /* 15724 */ // MIs[0] dst
6248 /* 15724 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6249 /* 15727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6250 /* 15729 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6251 /* 15729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
6252 /* 15732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6253 /* 15736 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6254 /* 15738 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6255 /* 15741 */ GIR_RootConstrainSelectedInstOperands,
6256 /* 15742 */ // GIR_Coverage, 1662,
6257 /* 15742 */ GIR_EraseRootFromParent_Done,
6258 /* 15743 */ // Label 560: @15743
6259 /* 15743 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(15795), // Rule ID 1663 //
6260 /* 15748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6261 /* 15751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6262 /* 15755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6263 /* 15759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6264 /* 15763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6265 /* 15767 */ // MIs[1] Operand 1
6266 /* 15767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6267 /* 15772 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6268 /* 15776 */ // MIs[0] dst
6269 /* 15776 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6270 /* 15779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6271 /* 15781 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6272 /* 15781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
6273 /* 15784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6274 /* 15788 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6275 /* 15790 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6276 /* 15793 */ GIR_RootConstrainSelectedInstOperands,
6277 /* 15794 */ // GIR_Coverage, 1663,
6278 /* 15794 */ GIR_EraseRootFromParent_Done,
6279 /* 15795 */ // Label 561: @15795
6280 /* 15795 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(15847), // Rule ID 1893 //
6281 /* 15800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6282 /* 15803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6283 /* 15807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6284 /* 15811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6285 /* 15815 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6286 /* 15819 */ // MIs[1] Operand 1
6287 /* 15819 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6288 /* 15824 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6289 /* 15828 */ // MIs[0] offset
6290 /* 15828 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6291 /* 15831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6292 /* 15833 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6293 /* 15833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6294 /* 15836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6295 /* 15840 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6296 /* 15842 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6297 /* 15845 */ GIR_RootConstrainSelectedInstOperands,
6298 /* 15846 */ // GIR_Coverage, 1893,
6299 /* 15846 */ GIR_EraseRootFromParent_Done,
6300 /* 15847 */ // Label 562: @15847
6301 /* 15847 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(15899), // Rule ID 1894 //
6302 /* 15852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6303 /* 15855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6304 /* 15859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6305 /* 15863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6306 /* 15867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6307 /* 15871 */ // MIs[1] Operand 1
6308 /* 15871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6309 /* 15876 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6310 /* 15880 */ // MIs[0] offset
6311 /* 15880 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6312 /* 15883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6313 /* 15885 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6314 /* 15885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6315 /* 15888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6316 /* 15892 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6317 /* 15894 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6318 /* 15897 */ GIR_RootConstrainSelectedInstOperands,
6319 /* 15898 */ // GIR_Coverage, 1894,
6320 /* 15898 */ GIR_EraseRootFromParent_Done,
6321 /* 15899 */ // Label 563: @15899
6322 /* 15899 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(15951), // Rule ID 1895 //
6323 /* 15904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6324 /* 15907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6325 /* 15911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6326 /* 15915 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6327 /* 15919 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6328 /* 15923 */ // MIs[1] Operand 1
6329 /* 15923 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6330 /* 15928 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6331 /* 15932 */ // MIs[0] offset
6332 /* 15932 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6333 /* 15935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6334 /* 15937 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6335 /* 15937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6336 /* 15940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6337 /* 15944 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6338 /* 15946 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6339 /* 15949 */ GIR_RootConstrainSelectedInstOperands,
6340 /* 15950 */ // GIR_Coverage, 1895,
6341 /* 15950 */ GIR_EraseRootFromParent_Done,
6342 /* 15951 */ // Label 564: @15951
6343 /* 15951 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(16003), // Rule ID 1896 //
6344 /* 15956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6345 /* 15959 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6346 /* 15963 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6347 /* 15967 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6348 /* 15971 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6349 /* 15975 */ // MIs[1] Operand 1
6350 /* 15975 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6351 /* 15980 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6352 /* 15984 */ // MIs[0] offset
6353 /* 15984 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6354 /* 15987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6355 /* 15989 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6356 /* 15989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6357 /* 15992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6358 /* 15996 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6359 /* 15998 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6360 /* 16001 */ GIR_RootConstrainSelectedInstOperands,
6361 /* 16002 */ // GIR_Coverage, 1896,
6362 /* 16002 */ GIR_EraseRootFromParent_Done,
6363 /* 16003 */ // Label 565: @16003
6364 /* 16003 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(16055), // Rule ID 1897 //
6365 /* 16008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6366 /* 16011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6367 /* 16015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6368 /* 16019 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6369 /* 16023 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6370 /* 16027 */ // MIs[1] Operand 1
6371 /* 16027 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6372 /* 16032 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6373 /* 16036 */ // MIs[0] offset
6374 /* 16036 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6375 /* 16039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6376 /* 16041 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6377 /* 16041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6378 /* 16044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6379 /* 16048 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6380 /* 16050 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6381 /* 16053 */ GIR_RootConstrainSelectedInstOperands,
6382 /* 16054 */ // GIR_Coverage, 1897,
6383 /* 16054 */ GIR_EraseRootFromParent_Done,
6384 /* 16055 */ // Label 566: @16055
6385 /* 16055 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(16107), // Rule ID 1898 //
6386 /* 16060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6387 /* 16063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6388 /* 16067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6389 /* 16071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6390 /* 16075 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6391 /* 16079 */ // MIs[1] Operand 1
6392 /* 16079 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6393 /* 16084 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6394 /* 16088 */ // MIs[0] offset
6395 /* 16088 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6396 /* 16091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6397 /* 16093 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6398 /* 16093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6399 /* 16096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6400 /* 16100 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6401 /* 16102 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6402 /* 16105 */ GIR_RootConstrainSelectedInstOperands,
6403 /* 16106 */ // GIR_Coverage, 1898,
6404 /* 16106 */ GIR_EraseRootFromParent_Done,
6405 /* 16107 */ // Label 567: @16107
6406 /* 16107 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(16159), // Rule ID 1899 //
6407 /* 16112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6408 /* 16115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6409 /* 16119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6410 /* 16123 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6411 /* 16127 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6412 /* 16131 */ // MIs[1] Operand 1
6413 /* 16131 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6414 /* 16136 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6415 /* 16140 */ // MIs[0] offset
6416 /* 16140 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6417 /* 16143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6418 /* 16145 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6419 /* 16145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6420 /* 16148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6421 /* 16152 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6422 /* 16154 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6423 /* 16157 */ GIR_RootConstrainSelectedInstOperands,
6424 /* 16158 */ // GIR_Coverage, 1899,
6425 /* 16158 */ GIR_EraseRootFromParent_Done,
6426 /* 16159 */ // Label 568: @16159
6427 /* 16159 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(16211), // Rule ID 1900 //
6428 /* 16164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6429 /* 16167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6430 /* 16171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6431 /* 16175 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6432 /* 16179 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6433 /* 16183 */ // MIs[1] Operand 1
6434 /* 16183 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6435 /* 16188 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6436 /* 16192 */ // MIs[0] offset
6437 /* 16192 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6438 /* 16195 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6439 /* 16197 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6440 /* 16197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6441 /* 16200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6442 /* 16204 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6443 /* 16206 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6444 /* 16209 */ GIR_RootConstrainSelectedInstOperands,
6445 /* 16210 */ // GIR_Coverage, 1900,
6446 /* 16210 */ GIR_EraseRootFromParent_Done,
6447 /* 16211 */ // Label 569: @16211
6448 /* 16211 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(16263), // Rule ID 1936 //
6449 /* 16216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6450 /* 16219 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6451 /* 16223 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6452 /* 16227 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6453 /* 16231 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6454 /* 16235 */ // MIs[1] Operand 1
6455 /* 16235 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6456 /* 16240 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6457 /* 16244 */ // MIs[0] offset
6458 /* 16244 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6459 /* 16247 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6460 /* 16249 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6461 /* 16249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6462 /* 16252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6463 /* 16256 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6464 /* 16258 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6465 /* 16261 */ GIR_RootConstrainSelectedInstOperands,
6466 /* 16262 */ // GIR_Coverage, 1936,
6467 /* 16262 */ GIR_EraseRootFromParent_Done,
6468 /* 16263 */ // Label 570: @16263
6469 /* 16263 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(16315), // Rule ID 1937 //
6470 /* 16268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6471 /* 16271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6472 /* 16275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6473 /* 16279 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6474 /* 16283 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6475 /* 16287 */ // MIs[1] Operand 1
6476 /* 16287 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6477 /* 16292 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6478 /* 16296 */ // MIs[0] offset
6479 /* 16296 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6480 /* 16299 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6481 /* 16301 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6482 /* 16301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6483 /* 16304 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6484 /* 16308 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6485 /* 16310 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6486 /* 16313 */ GIR_RootConstrainSelectedInstOperands,
6487 /* 16314 */ // GIR_Coverage, 1937,
6488 /* 16314 */ GIR_EraseRootFromParent_Done,
6489 /* 16315 */ // Label 571: @16315
6490 /* 16315 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(16367), // Rule ID 1938 //
6491 /* 16320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6492 /* 16323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6493 /* 16327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6494 /* 16331 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6495 /* 16335 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6496 /* 16339 */ // MIs[1] Operand 1
6497 /* 16339 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6498 /* 16344 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6499 /* 16348 */ // MIs[0] offset
6500 /* 16348 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6501 /* 16351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6502 /* 16353 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6503 /* 16353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6504 /* 16356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6505 /* 16360 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6506 /* 16362 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6507 /* 16365 */ GIR_RootConstrainSelectedInstOperands,
6508 /* 16366 */ // GIR_Coverage, 1938,
6509 /* 16366 */ GIR_EraseRootFromParent_Done,
6510 /* 16367 */ // Label 572: @16367
6511 /* 16367 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(16419), // Rule ID 1939 //
6512 /* 16372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6513 /* 16375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6514 /* 16379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6515 /* 16383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6516 /* 16387 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6517 /* 16391 */ // MIs[1] Operand 1
6518 /* 16391 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6519 /* 16396 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6520 /* 16400 */ // MIs[0] offset
6521 /* 16400 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6522 /* 16403 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6523 /* 16405 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6524 /* 16405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6525 /* 16408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6526 /* 16412 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6527 /* 16414 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6528 /* 16417 */ GIR_RootConstrainSelectedInstOperands,
6529 /* 16418 */ // GIR_Coverage, 1939,
6530 /* 16418 */ GIR_EraseRootFromParent_Done,
6531 /* 16419 */ // Label 573: @16419
6532 /* 16419 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(16471), // Rule ID 1940 //
6533 /* 16424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6534 /* 16427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6535 /* 16431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6536 /* 16435 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6537 /* 16439 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6538 /* 16443 */ // MIs[1] Operand 1
6539 /* 16443 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6540 /* 16448 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6541 /* 16452 */ // MIs[0] offset
6542 /* 16452 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6543 /* 16455 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6544 /* 16457 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6545 /* 16457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6546 /* 16460 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6547 /* 16464 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6548 /* 16466 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6549 /* 16469 */ GIR_RootConstrainSelectedInstOperands,
6550 /* 16470 */ // GIR_Coverage, 1940,
6551 /* 16470 */ GIR_EraseRootFromParent_Done,
6552 /* 16471 */ // Label 574: @16471
6553 /* 16471 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(16523), // Rule ID 1941 //
6554 /* 16476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6555 /* 16479 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6556 /* 16483 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6557 /* 16487 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6558 /* 16491 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6559 /* 16495 */ // MIs[1] Operand 1
6560 /* 16495 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6561 /* 16500 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6562 /* 16504 */ // MIs[0] offset
6563 /* 16504 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6564 /* 16507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6565 /* 16509 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6566 /* 16509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6567 /* 16512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6568 /* 16516 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6569 /* 16518 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6570 /* 16521 */ GIR_RootConstrainSelectedInstOperands,
6571 /* 16522 */ // GIR_Coverage, 1941,
6572 /* 16522 */ GIR_EraseRootFromParent_Done,
6573 /* 16523 */ // Label 575: @16523
6574 /* 16523 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(16575), // Rule ID 1942 //
6575 /* 16528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6576 /* 16531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6577 /* 16535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6578 /* 16539 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6579 /* 16543 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6580 /* 16547 */ // MIs[1] Operand 1
6581 /* 16547 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6582 /* 16552 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6583 /* 16556 */ // MIs[0] offset
6584 /* 16556 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6585 /* 16559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6586 /* 16561 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6587 /* 16561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6588 /* 16564 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6589 /* 16568 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6590 /* 16570 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6591 /* 16573 */ GIR_RootConstrainSelectedInstOperands,
6592 /* 16574 */ // GIR_Coverage, 1942,
6593 /* 16574 */ GIR_EraseRootFromParent_Done,
6594 /* 16575 */ // Label 576: @16575
6595 /* 16575 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(16627), // Rule ID 1943 //
6596 /* 16580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6597 /* 16583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6598 /* 16587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6599 /* 16591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6600 /* 16595 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6601 /* 16599 */ // MIs[1] Operand 1
6602 /* 16599 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6603 /* 16604 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6604 /* 16608 */ // MIs[0] offset
6605 /* 16608 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6606 /* 16611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6607 /* 16613 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6608 /* 16613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6609 /* 16616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6610 /* 16620 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6611 /* 16622 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6612 /* 16625 */ GIR_RootConstrainSelectedInstOperands,
6613 /* 16626 */ // GIR_Coverage, 1943,
6614 /* 16626 */ GIR_EraseRootFromParent_Done,
6615 /* 16627 */ // Label 577: @16627
6616 /* 16627 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(16679), // Rule ID 2333 //
6617 /* 16632 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6618 /* 16635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6619 /* 16639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6620 /* 16643 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6621 /* 16647 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6622 /* 16651 */ // MIs[1] Operand 1
6623 /* 16651 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6624 /* 16656 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6625 /* 16660 */ // MIs[0] dst
6626 /* 16660 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6627 /* 16663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6628 /* 16665 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6629 /* 16665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
6630 /* 16668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6631 /* 16672 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6632 /* 16674 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6633 /* 16677 */ GIR_RootConstrainSelectedInstOperands,
6634 /* 16678 */ // GIR_Coverage, 2333,
6635 /* 16678 */ GIR_EraseRootFromParent_Done,
6636 /* 16679 */ // Label 578: @16679
6637 /* 16679 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(16731), // Rule ID 2334 //
6638 /* 16684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6639 /* 16687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6640 /* 16691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6641 /* 16695 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6642 /* 16699 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6643 /* 16703 */ // MIs[1] Operand 1
6644 /* 16703 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6645 /* 16708 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6646 /* 16712 */ // MIs[0] dst
6647 /* 16712 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6648 /* 16715 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6649 /* 16717 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6650 /* 16717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
6651 /* 16720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6652 /* 16724 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6653 /* 16726 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6654 /* 16729 */ GIR_RootConstrainSelectedInstOperands,
6655 /* 16730 */ // GIR_Coverage, 2334,
6656 /* 16730 */ GIR_EraseRootFromParent_Done,
6657 /* 16731 */ // Label 579: @16731
6658 /* 16731 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(16793), // Rule ID 92 //
6659 /* 16736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6660 /* 16739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6661 /* 16743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6662 /* 16747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6663 /* 16751 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6664 /* 16755 */ // MIs[1] Operand 1
6665 /* 16755 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6666 /* 16760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6667 /* 16765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6668 /* 16770 */ // MIs[0] offset
6669 /* 16770 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6670 /* 16773 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6671 /* 16775 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6672 /* 16775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6673 /* 16778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6674 /* 16782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6675 /* 16786 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6676 /* 16788 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6677 /* 16791 */ GIR_RootConstrainSelectedInstOperands,
6678 /* 16792 */ // GIR_Coverage, 92,
6679 /* 16792 */ GIR_EraseRootFromParent_Done,
6680 /* 16793 */ // Label 580: @16793
6681 /* 16793 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(16855), // Rule ID 93 //
6682 /* 16798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6683 /* 16801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6684 /* 16805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6685 /* 16809 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6686 /* 16813 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6687 /* 16817 */ // MIs[1] Operand 1
6688 /* 16817 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6689 /* 16822 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6690 /* 16827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6691 /* 16832 */ // MIs[0] offset
6692 /* 16832 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6693 /* 16835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6694 /* 16837 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6695 /* 16837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6696 /* 16840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6697 /* 16844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6698 /* 16848 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6699 /* 16850 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6700 /* 16853 */ GIR_RootConstrainSelectedInstOperands,
6701 /* 16854 */ // GIR_Coverage, 93,
6702 /* 16854 */ GIR_EraseRootFromParent_Done,
6703 /* 16855 */ // Label 581: @16855
6704 /* 16855 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(16917), // Rule ID 267 //
6705 /* 16860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6706 /* 16863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6707 /* 16867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6708 /* 16871 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6709 /* 16875 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6710 /* 16879 */ // MIs[1] Operand 1
6711 /* 16879 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6712 /* 16884 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6713 /* 16889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6714 /* 16894 */ // MIs[0] offset
6715 /* 16894 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6716 /* 16897 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6717 /* 16899 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6718 /* 16899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6719 /* 16902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6720 /* 16906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6721 /* 16910 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6722 /* 16912 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6723 /* 16915 */ GIR_RootConstrainSelectedInstOperands,
6724 /* 16916 */ // GIR_Coverage, 267,
6725 /* 16916 */ GIR_EraseRootFromParent_Done,
6726 /* 16917 */ // Label 582: @16917
6727 /* 16917 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(16979), // Rule ID 268 //
6728 /* 16922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6729 /* 16925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6730 /* 16929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6731 /* 16933 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6732 /* 16937 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6733 /* 16941 */ // MIs[1] Operand 1
6734 /* 16941 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6735 /* 16946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6736 /* 16951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6737 /* 16956 */ // MIs[0] offset
6738 /* 16956 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6739 /* 16959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6740 /* 16961 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6741 /* 16961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6742 /* 16964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6743 /* 16968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6744 /* 16972 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6745 /* 16974 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6746 /* 16977 */ GIR_RootConstrainSelectedInstOperands,
6747 /* 16978 */ // GIR_Coverage, 268,
6748 /* 16978 */ GIR_EraseRootFromParent_Done,
6749 /* 16979 */ // Label 583: @16979
6750 /* 16979 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(17041), // Rule ID 1131 //
6751 /* 16984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6752 /* 16987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6753 /* 16991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6754 /* 16995 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6755 /* 16999 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6756 /* 17003 */ // MIs[1] Operand 1
6757 /* 17003 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6758 /* 17008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6759 /* 17013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6760 /* 17018 */ // MIs[0] offset
6761 /* 17018 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6762 /* 17021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6763 /* 17023 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6764 /* 17023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6765 /* 17026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6766 /* 17030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6767 /* 17034 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6768 /* 17036 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6769 /* 17039 */ GIR_RootConstrainSelectedInstOperands,
6770 /* 17040 */ // GIR_Coverage, 1131,
6771 /* 17040 */ GIR_EraseRootFromParent_Done,
6772 /* 17041 */ // Label 584: @17041
6773 /* 17041 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(17103), // Rule ID 1132 //
6774 /* 17046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6775 /* 17049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6776 /* 17053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6777 /* 17057 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6778 /* 17061 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6779 /* 17065 */ // MIs[1] Operand 1
6780 /* 17065 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6781 /* 17070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6782 /* 17075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6783 /* 17080 */ // MIs[0] offset
6784 /* 17080 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6785 /* 17083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6786 /* 17085 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6787 /* 17085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6788 /* 17088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6789 /* 17092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6790 /* 17096 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6791 /* 17098 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6792 /* 17101 */ GIR_RootConstrainSelectedInstOperands,
6793 /* 17102 */ // GIR_Coverage, 1132,
6794 /* 17102 */ GIR_EraseRootFromParent_Done,
6795 /* 17103 */ // Label 585: @17103
6796 /* 17103 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(17188), // Rule ID 1427 //
6797 /* 17108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6798 /* 17111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6799 /* 17115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6800 /* 17119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6801 /* 17123 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6802 /* 17127 */ // MIs[1] Operand 1
6803 /* 17127 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6804 /* 17132 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6805 /* 17137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6806 /* 17142 */ // MIs[0] dst
6807 /* 17142 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6808 /* 17145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6809 /* 17147 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6810 /* 17147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6811 /* 17150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6812 /* 17154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6813 /* 17159 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6814 /* 17163 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6815 /* 17167 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6816 /* 17169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6817 /* 17172 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6818 /* 17175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6819 /* 17181 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6820 /* 17183 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6821 /* 17186 */ GIR_RootConstrainSelectedInstOperands,
6822 /* 17187 */ // GIR_Coverage, 1427,
6823 /* 17187 */ GIR_EraseRootFromParent_Done,
6824 /* 17188 */ // Label 586: @17188
6825 /* 17188 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(17273), // Rule ID 1428 //
6826 /* 17193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6827 /* 17196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6828 /* 17200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6829 /* 17204 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6830 /* 17208 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6831 /* 17212 */ // MIs[1] Operand 1
6832 /* 17212 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6833 /* 17217 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6834 /* 17222 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6835 /* 17227 */ // MIs[0] dst
6836 /* 17227 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6837 /* 17230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6838 /* 17232 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6839 /* 17232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6840 /* 17235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6841 /* 17239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6842 /* 17244 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6843 /* 17248 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6844 /* 17252 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6845 /* 17254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6846 /* 17257 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6847 /* 17260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6848 /* 17266 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6849 /* 17268 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6850 /* 17271 */ GIR_RootConstrainSelectedInstOperands,
6851 /* 17272 */ // GIR_Coverage, 1428,
6852 /* 17272 */ GIR_EraseRootFromParent_Done,
6853 /* 17273 */ // Label 587: @17273
6854 /* 17273 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(17358), // Rule ID 1433 //
6855 /* 17278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6856 /* 17281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6857 /* 17285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6858 /* 17289 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6859 /* 17293 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6860 /* 17297 */ // MIs[1] Operand 1
6861 /* 17297 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6862 /* 17302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6863 /* 17307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6864 /* 17312 */ // MIs[0] dst
6865 /* 17312 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6866 /* 17315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6867 /* 17317 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6868 /* 17317 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6869 /* 17320 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6870 /* 17324 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6871 /* 17329 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6872 /* 17333 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6873 /* 17337 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6874 /* 17339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6875 /* 17342 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6876 /* 17345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6877 /* 17351 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6878 /* 17353 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6879 /* 17356 */ GIR_RootConstrainSelectedInstOperands,
6880 /* 17357 */ // GIR_Coverage, 1433,
6881 /* 17357 */ GIR_EraseRootFromParent_Done,
6882 /* 17358 */ // Label 588: @17358
6883 /* 17358 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(17443), // Rule ID 1434 //
6884 /* 17363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6885 /* 17366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6886 /* 17370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6887 /* 17374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6888 /* 17378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6889 /* 17382 */ // MIs[1] Operand 1
6890 /* 17382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6891 /* 17387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6892 /* 17392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6893 /* 17397 */ // MIs[0] dst
6894 /* 17397 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6895 /* 17400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6896 /* 17402 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6897 /* 17402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6898 /* 17405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6899 /* 17409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6900 /* 17414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6901 /* 17418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6902 /* 17422 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6903 /* 17424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6904 /* 17427 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6905 /* 17430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6906 /* 17436 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6907 /* 17438 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6908 /* 17441 */ GIR_RootConstrainSelectedInstOperands,
6909 /* 17442 */ // GIR_Coverage, 1434,
6910 /* 17442 */ GIR_EraseRootFromParent_Done,
6911 /* 17443 */ // Label 589: @17443
6912 /* 17443 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(17528), // Rule ID 1653 //
6913 /* 17448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6914 /* 17451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6915 /* 17455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6916 /* 17459 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6917 /* 17463 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6918 /* 17467 */ // MIs[1] Operand 1
6919 /* 17467 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6920 /* 17472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6921 /* 17477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6922 /* 17482 */ // MIs[0] dst
6923 /* 17482 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6924 /* 17485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6925 /* 17487 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6926 /* 17487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6927 /* 17490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6928 /* 17494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6929 /* 17499 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6930 /* 17503 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6931 /* 17507 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6932 /* 17509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6933 /* 17512 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6934 /* 17515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6935 /* 17521 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6936 /* 17523 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6937 /* 17526 */ GIR_RootConstrainSelectedInstOperands,
6938 /* 17527 */ // GIR_Coverage, 1653,
6939 /* 17527 */ GIR_EraseRootFromParent_Done,
6940 /* 17528 */ // Label 590: @17528
6941 /* 17528 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(17613), // Rule ID 1654 //
6942 /* 17533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6943 /* 17536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6944 /* 17540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6945 /* 17544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6946 /* 17548 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6947 /* 17552 */ // MIs[1] Operand 1
6948 /* 17552 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6949 /* 17557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6950 /* 17562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6951 /* 17567 */ // MIs[0] dst
6952 /* 17567 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6953 /* 17570 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6954 /* 17572 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6955 /* 17572 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6956 /* 17575 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6957 /* 17579 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6958 /* 17584 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6959 /* 17588 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6960 /* 17592 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6961 /* 17594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6962 /* 17597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6963 /* 17600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6964 /* 17606 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6965 /* 17608 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6966 /* 17611 */ GIR_RootConstrainSelectedInstOperands,
6967 /* 17612 */ // GIR_Coverage, 1654,
6968 /* 17612 */ GIR_EraseRootFromParent_Done,
6969 /* 17613 */ // Label 591: @17613
6970 /* 17613 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(17698), // Rule ID 1659 //
6971 /* 17618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6972 /* 17621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6973 /* 17625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6974 /* 17629 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6975 /* 17633 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6976 /* 17637 */ // MIs[1] Operand 1
6977 /* 17637 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6978 /* 17642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6979 /* 17647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6980 /* 17652 */ // MIs[0] dst
6981 /* 17652 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6982 /* 17655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6983 /* 17657 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6984 /* 17657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6985 /* 17660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6986 /* 17664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6987 /* 17669 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6988 /* 17673 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6989 /* 17677 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6990 /* 17679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6991 /* 17682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6992 /* 17685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6993 /* 17691 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6994 /* 17693 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6995 /* 17696 */ GIR_RootConstrainSelectedInstOperands,
6996 /* 17697 */ // GIR_Coverage, 1659,
6997 /* 17697 */ GIR_EraseRootFromParent_Done,
6998 /* 17698 */ // Label 592: @17698
6999 /* 17698 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(17783), // Rule ID 1660 //
7000 /* 17703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
7001 /* 17706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7002 /* 17710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7003 /* 17714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7004 /* 17718 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7005 /* 17722 */ // MIs[1] Operand 1
7006 /* 17722 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7007 /* 17727 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7008 /* 17732 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7009 /* 17737 */ // MIs[0] dst
7010 /* 17737 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7011 /* 17740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7012 /* 17742 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7013 /* 17742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7014 /* 17745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
7015 /* 17749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7016 /* 17754 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7017 /* 17758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7018 /* 17762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7019 /* 17764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
7020 /* 17767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7021 /* 17770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7022 /* 17776 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7023 /* 17778 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7024 /* 17781 */ GIR_RootConstrainSelectedInstOperands,
7025 /* 17782 */ // GIR_Coverage, 1660,
7026 /* 17782 */ GIR_EraseRootFromParent_Done,
7027 /* 17783 */ // Label 593: @17783
7028 /* 17783 */ GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(17845), // Rule ID 1901 //
7029 /* 17788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7030 /* 17791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7031 /* 17795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7032 /* 17799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7033 /* 17803 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7034 /* 17807 */ // MIs[1] Operand 1
7035 /* 17807 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7036 /* 17812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7037 /* 17817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7038 /* 17822 */ // MIs[0] offset
7039 /* 17822 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7040 /* 17825 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7041 /* 17827 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7042 /* 17827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
7043 /* 17830 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7044 /* 17834 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7045 /* 17838 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7046 /* 17840 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7047 /* 17843 */ GIR_RootConstrainSelectedInstOperands,
7048 /* 17844 */ // GIR_Coverage, 1901,
7049 /* 17844 */ GIR_EraseRootFromParent_Done,
7050 /* 17845 */ // Label 594: @17845
7051 /* 17845 */ GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(17907), // Rule ID 1902 //
7052 /* 17850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7053 /* 17853 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7054 /* 17857 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7055 /* 17861 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7056 /* 17865 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7057 /* 17869 */ // MIs[1] Operand 1
7058 /* 17869 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7059 /* 17874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7060 /* 17879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7061 /* 17884 */ // MIs[0] offset
7062 /* 17884 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7063 /* 17887 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7064 /* 17889 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7065 /* 17889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
7066 /* 17892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7067 /* 17896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7068 /* 17900 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7069 /* 17902 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7070 /* 17905 */ GIR_RootConstrainSelectedInstOperands,
7071 /* 17906 */ // GIR_Coverage, 1902,
7072 /* 17906 */ GIR_EraseRootFromParent_Done,
7073 /* 17907 */ // Label 595: @17907
7074 /* 17907 */ GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(17969), // Rule ID 1903 //
7075 /* 17912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7076 /* 17915 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7077 /* 17919 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7078 /* 17923 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7079 /* 17927 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7080 /* 17931 */ // MIs[1] Operand 1
7081 /* 17931 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7082 /* 17936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7083 /* 17941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7084 /* 17946 */ // MIs[0] offset
7085 /* 17946 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7086 /* 17949 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7087 /* 17951 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7088 /* 17951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
7089 /* 17954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7090 /* 17958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7091 /* 17962 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7092 /* 17964 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7093 /* 17967 */ GIR_RootConstrainSelectedInstOperands,
7094 /* 17968 */ // GIR_Coverage, 1903,
7095 /* 17968 */ GIR_EraseRootFromParent_Done,
7096 /* 17969 */ // Label 596: @17969
7097 /* 17969 */ GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(18031), // Rule ID 1904 //
7098 /* 17974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7099 /* 17977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7100 /* 17981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7101 /* 17985 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7102 /* 17989 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7103 /* 17993 */ // MIs[1] Operand 1
7104 /* 17993 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7105 /* 17998 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7106 /* 18003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7107 /* 18008 */ // MIs[0] offset
7108 /* 18008 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7109 /* 18011 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7110 /* 18013 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7111 /* 18013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
7112 /* 18016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7113 /* 18020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7114 /* 18024 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7115 /* 18026 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7116 /* 18029 */ GIR_RootConstrainSelectedInstOperands,
7117 /* 18030 */ // GIR_Coverage, 1904,
7118 /* 18030 */ GIR_EraseRootFromParent_Done,
7119 /* 18031 */ // Label 597: @18031
7120 /* 18031 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(18093), // Rule ID 1905 //
7121 /* 18036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7122 /* 18039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7123 /* 18043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7124 /* 18047 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7125 /* 18051 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7126 /* 18055 */ // MIs[1] Operand 1
7127 /* 18055 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
7128 /* 18060 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7129 /* 18065 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7130 /* 18070 */ // MIs[0] offset
7131 /* 18070 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7132 /* 18073 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7133 /* 18075 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7134 /* 18075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
7135 /* 18078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7136 /* 18082 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7137 /* 18086 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7138 /* 18088 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7139 /* 18091 */ GIR_RootConstrainSelectedInstOperands,
7140 /* 18092 */ // GIR_Coverage, 1905,
7141 /* 18092 */ GIR_EraseRootFromParent_Done,
7142 /* 18093 */ // Label 598: @18093
7143 /* 18093 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(18155), // Rule ID 1906 //
7144 /* 18098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7145 /* 18101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7146 /* 18105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7147 /* 18109 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7148 /* 18113 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7149 /* 18117 */ // MIs[1] Operand 1
7150 /* 18117 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7151 /* 18122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7152 /* 18127 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7153 /* 18132 */ // MIs[0] offset
7154 /* 18132 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7155 /* 18135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7156 /* 18137 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7157 /* 18137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
7158 /* 18140 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7159 /* 18144 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7160 /* 18148 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7161 /* 18150 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7162 /* 18153 */ GIR_RootConstrainSelectedInstOperands,
7163 /* 18154 */ // GIR_Coverage, 1906,
7164 /* 18154 */ GIR_EraseRootFromParent_Done,
7165 /* 18155 */ // Label 599: @18155
7166 /* 18155 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(18217), // Rule ID 1907 //
7167 /* 18160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7168 /* 18163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7169 /* 18167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7170 /* 18171 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7171 /* 18175 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7172 /* 18179 */ // MIs[1] Operand 1
7173 /* 18179 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
7174 /* 18184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7175 /* 18189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7176 /* 18194 */ // MIs[0] offset
7177 /* 18194 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7178 /* 18197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7179 /* 18199 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7180 /* 18199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
7181 /* 18202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7182 /* 18206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7183 /* 18210 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7184 /* 18212 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7185 /* 18215 */ GIR_RootConstrainSelectedInstOperands,
7186 /* 18216 */ // GIR_Coverage, 1907,
7187 /* 18216 */ GIR_EraseRootFromParent_Done,
7188 /* 18217 */ // Label 600: @18217
7189 /* 18217 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(18279), // Rule ID 1908 //
7190 /* 18222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7191 /* 18225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7192 /* 18229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7193 /* 18233 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7194 /* 18237 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7195 /* 18241 */ // MIs[1] Operand 1
7196 /* 18241 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7197 /* 18246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7198 /* 18251 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7199 /* 18256 */ // MIs[0] offset
7200 /* 18256 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7201 /* 18259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7202 /* 18261 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7203 /* 18261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
7204 /* 18264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7205 /* 18268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7206 /* 18272 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7207 /* 18274 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7208 /* 18277 */ GIR_RootConstrainSelectedInstOperands,
7209 /* 18278 */ // GIR_Coverage, 1908,
7210 /* 18278 */ GIR_EraseRootFromParent_Done,
7211 /* 18279 */ // Label 601: @18279
7212 /* 18279 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(18341), // Rule ID 1944 //
7213 /* 18284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7214 /* 18287 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7215 /* 18291 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7216 /* 18295 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7217 /* 18299 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7218 /* 18303 */ // MIs[1] Operand 1
7219 /* 18303 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7220 /* 18308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7221 /* 18313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7222 /* 18318 */ // MIs[0] offset
7223 /* 18318 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7224 /* 18321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7225 /* 18323 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7226 /* 18323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
7227 /* 18326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7228 /* 18330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7229 /* 18334 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7230 /* 18336 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7231 /* 18339 */ GIR_RootConstrainSelectedInstOperands,
7232 /* 18340 */ // GIR_Coverage, 1944,
7233 /* 18340 */ GIR_EraseRootFromParent_Done,
7234 /* 18341 */ // Label 602: @18341
7235 /* 18341 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(18403), // Rule ID 1945 //
7236 /* 18346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7237 /* 18349 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7238 /* 18353 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7239 /* 18357 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7240 /* 18361 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7241 /* 18365 */ // MIs[1] Operand 1
7242 /* 18365 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7243 /* 18370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7244 /* 18375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7245 /* 18380 */ // MIs[0] offset
7246 /* 18380 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7247 /* 18383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7248 /* 18385 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7249 /* 18385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
7250 /* 18388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7251 /* 18392 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7252 /* 18396 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7253 /* 18398 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7254 /* 18401 */ GIR_RootConstrainSelectedInstOperands,
7255 /* 18402 */ // GIR_Coverage, 1945,
7256 /* 18402 */ GIR_EraseRootFromParent_Done,
7257 /* 18403 */ // Label 603: @18403
7258 /* 18403 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(18465), // Rule ID 1946 //
7259 /* 18408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7260 /* 18411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7261 /* 18415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7262 /* 18419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7263 /* 18423 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7264 /* 18427 */ // MIs[1] Operand 1
7265 /* 18427 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7266 /* 18432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7267 /* 18437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7268 /* 18442 */ // MIs[0] offset
7269 /* 18442 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7270 /* 18445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7271 /* 18447 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7272 /* 18447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
7273 /* 18450 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7274 /* 18454 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7275 /* 18458 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7276 /* 18460 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7277 /* 18463 */ GIR_RootConstrainSelectedInstOperands,
7278 /* 18464 */ // GIR_Coverage, 1946,
7279 /* 18464 */ GIR_EraseRootFromParent_Done,
7280 /* 18465 */ // Label 604: @18465
7281 /* 18465 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(18527), // Rule ID 1947 //
7282 /* 18470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7283 /* 18473 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7284 /* 18477 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7285 /* 18481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7286 /* 18485 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7287 /* 18489 */ // MIs[1] Operand 1
7288 /* 18489 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7289 /* 18494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7290 /* 18499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7291 /* 18504 */ // MIs[0] offset
7292 /* 18504 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7293 /* 18507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7294 /* 18509 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7295 /* 18509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
7296 /* 18512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7297 /* 18516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7298 /* 18520 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7299 /* 18522 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7300 /* 18525 */ GIR_RootConstrainSelectedInstOperands,
7301 /* 18526 */ // GIR_Coverage, 1947,
7302 /* 18526 */ GIR_EraseRootFromParent_Done,
7303 /* 18527 */ // Label 605: @18527
7304 /* 18527 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(18589), // Rule ID 1948 //
7305 /* 18532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7306 /* 18535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7307 /* 18539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7308 /* 18543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7309 /* 18547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7310 /* 18551 */ // MIs[1] Operand 1
7311 /* 18551 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
7312 /* 18556 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7313 /* 18561 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7314 /* 18566 */ // MIs[0] offset
7315 /* 18566 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7316 /* 18569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7317 /* 18571 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7318 /* 18571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
7319 /* 18574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7320 /* 18578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7321 /* 18582 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7322 /* 18584 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7323 /* 18587 */ GIR_RootConstrainSelectedInstOperands,
7324 /* 18588 */ // GIR_Coverage, 1948,
7325 /* 18588 */ GIR_EraseRootFromParent_Done,
7326 /* 18589 */ // Label 606: @18589
7327 /* 18589 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(18651), // Rule ID 1949 //
7328 /* 18594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7329 /* 18597 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7330 /* 18601 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7331 /* 18605 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7332 /* 18609 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7333 /* 18613 */ // MIs[1] Operand 1
7334 /* 18613 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7335 /* 18618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7336 /* 18623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7337 /* 18628 */ // MIs[0] offset
7338 /* 18628 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7339 /* 18631 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7340 /* 18633 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7341 /* 18633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
7342 /* 18636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7343 /* 18640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7344 /* 18644 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7345 /* 18646 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7346 /* 18649 */ GIR_RootConstrainSelectedInstOperands,
7347 /* 18650 */ // GIR_Coverage, 1949,
7348 /* 18650 */ GIR_EraseRootFromParent_Done,
7349 /* 18651 */ // Label 607: @18651
7350 /* 18651 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(18713), // Rule ID 1950 //
7351 /* 18656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7352 /* 18659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7353 /* 18663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7354 /* 18667 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7355 /* 18671 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7356 /* 18675 */ // MIs[1] Operand 1
7357 /* 18675 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
7358 /* 18680 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7359 /* 18685 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7360 /* 18690 */ // MIs[0] offset
7361 /* 18690 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7362 /* 18693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7363 /* 18695 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7364 /* 18695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
7365 /* 18698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7366 /* 18702 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7367 /* 18706 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7368 /* 18708 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7369 /* 18711 */ GIR_RootConstrainSelectedInstOperands,
7370 /* 18712 */ // GIR_Coverage, 1950,
7371 /* 18712 */ GIR_EraseRootFromParent_Done,
7372 /* 18713 */ // Label 608: @18713
7373 /* 18713 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(18775), // Rule ID 1951 //
7374 /* 18718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7375 /* 18721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7376 /* 18725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7377 /* 18729 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7378 /* 18733 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7379 /* 18737 */ // MIs[1] Operand 1
7380 /* 18737 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7381 /* 18742 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7382 /* 18747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7383 /* 18752 */ // MIs[0] offset
7384 /* 18752 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7385 /* 18755 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7386 /* 18757 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7387 /* 18757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
7388 /* 18760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7389 /* 18764 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7390 /* 18768 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7391 /* 18770 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7392 /* 18773 */ GIR_RootConstrainSelectedInstOperands,
7393 /* 18774 */ // GIR_Coverage, 1951,
7394 /* 18774 */ GIR_EraseRootFromParent_Done,
7395 /* 18775 */ // Label 609: @18775
7396 /* 18775 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(18834), // Rule ID 1981 //
7397 /* 18780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7398 /* 18783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7399 /* 18787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7400 /* 18791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7401 /* 18795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7402 /* 18799 */ // MIs[1] Operand 1
7403 /* 18799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
7404 /* 18804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7405 /* 18809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7406 /* 18814 */ // MIs[0] imm16
7407 /* 18814 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7408 /* 18817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7409 /* 18819 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7410 /* 18819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
7411 /* 18822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7412 /* 18826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7413 /* 18830 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7414 /* 18832 */ GIR_RootConstrainSelectedInstOperands,
7415 /* 18833 */ // GIR_Coverage, 1981,
7416 /* 18833 */ GIR_EraseRootFromParent_Done,
7417 /* 18834 */ // Label 610: @18834
7418 /* 18834 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(18893), // Rule ID 1984 //
7419 /* 18839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7420 /* 18842 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7421 /* 18846 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7422 /* 18850 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7423 /* 18854 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7424 /* 18858 */ // MIs[1] Operand 1
7425 /* 18858 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7426 /* 18863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7427 /* 18868 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7428 /* 18873 */ // MIs[0] imm16
7429 /* 18873 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7430 /* 18876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7431 /* 18878 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
7432 /* 18878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
7433 /* 18881 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7434 /* 18885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7435 /* 18889 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7436 /* 18891 */ GIR_RootConstrainSelectedInstOperands,
7437 /* 18892 */ // GIR_Coverage, 1984,
7438 /* 18892 */ GIR_EraseRootFromParent_Done,
7439 /* 18893 */ // Label 611: @18893
7440 /* 18893 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(18952), // Rule ID 1985 //
7441 /* 18898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7442 /* 18901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7443 /* 18905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7444 /* 18909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7445 /* 18913 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7446 /* 18917 */ // MIs[1] Operand 1
7447 /* 18917 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7448 /* 18922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7449 /* 18927 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7450 /* 18932 */ // MIs[0] imm16
7451 /* 18932 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7452 /* 18935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7453 /* 18937 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7454 /* 18937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7455 /* 18940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7456 /* 18944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7457 /* 18948 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7458 /* 18950 */ GIR_RootConstrainSelectedInstOperands,
7459 /* 18951 */ // GIR_Coverage, 1985,
7460 /* 18951 */ GIR_EraseRootFromParent_Done,
7461 /* 18952 */ // Label 612: @18952
7462 /* 18952 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(19011), // Rule ID 1987 //
7463 /* 18957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7464 /* 18960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7465 /* 18964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7466 /* 18968 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7467 /* 18972 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7468 /* 18976 */ // MIs[1] Operand 1
7469 /* 18976 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7470 /* 18981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7471 /* 18986 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7472 /* 18991 */ // MIs[0] imm16
7473 /* 18991 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7474 /* 18994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7475 /* 18996 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7476 /* 18996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
7477 /* 18999 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7478 /* 19003 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7479 /* 19007 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7480 /* 19009 */ GIR_RootConstrainSelectedInstOperands,
7481 /* 19010 */ // GIR_Coverage, 1987,
7482 /* 19010 */ GIR_EraseRootFromParent_Done,
7483 /* 19011 */ // Label 613: @19011
7484 /* 19011 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(19070), // Rule ID 1989 //
7485 /* 19016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7486 /* 19019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7487 /* 19023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7488 /* 19027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7489 /* 19031 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7490 /* 19035 */ // MIs[1] Operand 1
7491 /* 19035 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7492 /* 19040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7493 /* 19045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7494 /* 19050 */ // MIs[0] imm16
7495 /* 19050 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7496 /* 19053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7497 /* 19055 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
7498 /* 19055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7499 /* 19058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7500 /* 19062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7501 /* 19066 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7502 /* 19068 */ GIR_RootConstrainSelectedInstOperands,
7503 /* 19069 */ // GIR_Coverage, 1989,
7504 /* 19069 */ GIR_EraseRootFromParent_Done,
7505 /* 19070 */ // Label 614: @19070
7506 /* 19070 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(19129), // Rule ID 1990 //
7507 /* 19075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7508 /* 19078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7509 /* 19082 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7510 /* 19086 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7511 /* 19090 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7512 /* 19094 */ // MIs[1] Operand 1
7513 /* 19094 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
7514 /* 19099 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7515 /* 19104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7516 /* 19109 */ // MIs[0] imm16
7517 /* 19109 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7518 /* 19112 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7519 /* 19114 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7520 /* 19114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
7521 /* 19117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7522 /* 19121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7523 /* 19125 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7524 /* 19127 */ GIR_RootConstrainSelectedInstOperands,
7525 /* 19128 */ // GIR_Coverage, 1990,
7526 /* 19128 */ GIR_EraseRootFromParent_Done,
7527 /* 19129 */ // Label 615: @19129
7528 /* 19129 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(19214), // Rule ID 2324 //
7529 /* 19134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7530 /* 19137 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7531 /* 19141 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7532 /* 19145 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7533 /* 19149 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7534 /* 19153 */ // MIs[1] Operand 1
7535 /* 19153 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7536 /* 19158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7537 /* 19163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7538 /* 19168 */ // MIs[0] dst
7539 /* 19168 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7540 /* 19171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7541 /* 19173 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7542 /* 19173 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7543 /* 19176 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7544 /* 19180 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7545 /* 19185 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7546 /* 19189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7547 /* 19193 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7548 /* 19195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7549 /* 19198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7550 /* 19201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7551 /* 19207 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7552 /* 19209 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7553 /* 19212 */ GIR_RootConstrainSelectedInstOperands,
7554 /* 19213 */ // GIR_Coverage, 2324,
7555 /* 19213 */ GIR_EraseRootFromParent_Done,
7556 /* 19214 */ // Label 616: @19214
7557 /* 19214 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19299), // Rule ID 2325 //
7558 /* 19219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7559 /* 19222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7560 /* 19226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7561 /* 19230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7562 /* 19234 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7563 /* 19238 */ // MIs[1] Operand 1
7564 /* 19238 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7565 /* 19243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7566 /* 19248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7567 /* 19253 */ // MIs[0] dst
7568 /* 19253 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7569 /* 19256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7570 /* 19258 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7571 /* 19258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7572 /* 19261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7573 /* 19265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7574 /* 19270 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7575 /* 19274 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7576 /* 19278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7577 /* 19280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7578 /* 19283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7579 /* 19286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7580 /* 19292 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7581 /* 19294 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7582 /* 19297 */ GIR_RootConstrainSelectedInstOperands,
7583 /* 19298 */ // GIR_Coverage, 2325,
7584 /* 19298 */ GIR_EraseRootFromParent_Done,
7585 /* 19299 */ // Label 617: @19299
7586 /* 19299 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19384), // Rule ID 2330 //
7587 /* 19304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7588 /* 19307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7589 /* 19311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7590 /* 19315 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7591 /* 19319 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7592 /* 19323 */ // MIs[1] Operand 1
7593 /* 19323 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7594 /* 19328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7595 /* 19333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7596 /* 19338 */ // MIs[0] dst
7597 /* 19338 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7598 /* 19341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7599 /* 19343 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7600 /* 19343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7601 /* 19346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7602 /* 19350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7603 /* 19355 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7604 /* 19359 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7605 /* 19363 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7606 /* 19365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7607 /* 19368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7608 /* 19371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7609 /* 19377 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7610 /* 19379 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7611 /* 19382 */ GIR_RootConstrainSelectedInstOperands,
7612 /* 19383 */ // GIR_Coverage, 2330,
7613 /* 19383 */ GIR_EraseRootFromParent_Done,
7614 /* 19384 */ // Label 618: @19384
7615 /* 19384 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19469), // Rule ID 2331 //
7616 /* 19389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7617 /* 19392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7618 /* 19396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7619 /* 19400 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7620 /* 19404 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7621 /* 19408 */ // MIs[1] Operand 1
7622 /* 19408 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7623 /* 19413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7624 /* 19418 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7625 /* 19423 */ // MIs[0] dst
7626 /* 19423 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7627 /* 19426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7628 /* 19428 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7629 /* 19428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7630 /* 19431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7631 /* 19435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7632 /* 19440 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7633 /* 19444 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7634 /* 19448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7635 /* 19450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7636 /* 19453 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7637 /* 19456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7638 /* 19462 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7639 /* 19464 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7640 /* 19467 */ GIR_RootConstrainSelectedInstOperands,
7641 /* 19468 */ // GIR_Coverage, 2331,
7642 /* 19468 */ GIR_EraseRootFromParent_Done,
7643 /* 19469 */ // Label 619: @19469
7644 /* 19469 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19548), // Rule ID 2476 //
7645 /* 19474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7646 /* 19477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7647 /* 19481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7648 /* 19485 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7649 /* 19489 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7650 /* 19493 */ // MIs[1] Operand 1
7651 /* 19493 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7652 /* 19498 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7653 /* 19503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7654 /* 19508 */ // MIs[0] dst
7655 /* 19508 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7656 /* 19511 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7657 /* 19513 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7658 /* 19513 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7659 /* 19516 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7660 /* 19520 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7661 /* 19525 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7662 /* 19529 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7663 /* 19533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7664 /* 19535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7665 /* 19538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7666 /* 19541 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7667 /* 19543 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7668 /* 19546 */ GIR_RootConstrainSelectedInstOperands,
7669 /* 19547 */ // GIR_Coverage, 2476,
7670 /* 19547 */ GIR_EraseRootFromParent_Done,
7671 /* 19548 */ // Label 620: @19548
7672 /* 19548 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19627), // Rule ID 2477 //
7673 /* 19553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7674 /* 19556 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7675 /* 19560 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7676 /* 19564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7677 /* 19568 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7678 /* 19572 */ // MIs[1] Operand 1
7679 /* 19572 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7680 /* 19577 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7681 /* 19582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7682 /* 19587 */ // MIs[0] dst
7683 /* 19587 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7684 /* 19590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7685 /* 19592 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7686 /* 19592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7687 /* 19595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7688 /* 19599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7689 /* 19604 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7690 /* 19608 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7691 /* 19612 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7692 /* 19614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7693 /* 19617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7694 /* 19620 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7695 /* 19622 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7696 /* 19625 */ GIR_RootConstrainSelectedInstOperands,
7697 /* 19626 */ // GIR_Coverage, 2477,
7698 /* 19626 */ GIR_EraseRootFromParent_Done,
7699 /* 19627 */ // Label 621: @19627
7700 /* 19627 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19706), // Rule ID 2482 //
7701 /* 19632 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7702 /* 19635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7703 /* 19639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7704 /* 19643 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7705 /* 19647 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7706 /* 19651 */ // MIs[1] Operand 1
7707 /* 19651 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7708 /* 19656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7709 /* 19661 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7710 /* 19666 */ // MIs[0] dst
7711 /* 19666 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7712 /* 19669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7713 /* 19671 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7714 /* 19671 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7715 /* 19674 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7716 /* 19678 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7717 /* 19683 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7718 /* 19687 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7719 /* 19691 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7720 /* 19693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7721 /* 19696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7722 /* 19699 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7723 /* 19701 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7724 /* 19704 */ GIR_RootConstrainSelectedInstOperands,
7725 /* 19705 */ // GIR_Coverage, 2482,
7726 /* 19705 */ GIR_EraseRootFromParent_Done,
7727 /* 19706 */ // Label 622: @19706
7728 /* 19706 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19785), // Rule ID 2483 //
7729 /* 19711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7730 /* 19714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7731 /* 19718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7732 /* 19722 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7733 /* 19726 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7734 /* 19730 */ // MIs[1] Operand 1
7735 /* 19730 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7736 /* 19735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7737 /* 19740 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7738 /* 19745 */ // MIs[0] dst
7739 /* 19745 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7740 /* 19748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7741 /* 19750 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7742 /* 19750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7743 /* 19753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7744 /* 19757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7745 /* 19762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7746 /* 19766 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7747 /* 19770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7748 /* 19772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7749 /* 19775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7750 /* 19778 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7751 /* 19780 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7752 /* 19783 */ GIR_RootConstrainSelectedInstOperands,
7753 /* 19784 */ // GIR_Coverage, 2483,
7754 /* 19784 */ GIR_EraseRootFromParent_Done,
7755 /* 19785 */ // Label 623: @19785
7756 /* 19785 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19818), // Rule ID 1435 //
7757 /* 19790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
7758 /* 19793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7759 /* 19797 */ // MIs[0] dst
7760 /* 19797 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7761 /* 19800 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7762 /* 19800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
7763 /* 19803 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7764 /* 19805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7765 /* 19811 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7766 /* 19813 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7767 /* 19816 */ GIR_RootConstrainSelectedInstOperands,
7768 /* 19817 */ // GIR_Coverage, 1435,
7769 /* 19817 */ GIR_EraseRootFromParent_Done,
7770 /* 19818 */ // Label 624: @19818
7771 /* 19818 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19840), // Rule ID 1993 //
7772 /* 19823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7773 /* 19826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7774 /* 19830 */ // MIs[0] targ16
7775 /* 19830 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7776 /* 19833 */ // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
7777 /* 19833 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
7778 /* 19838 */ GIR_RootConstrainSelectedInstOperands,
7779 /* 19839 */ // GIR_Coverage, 1993,
7780 /* 19839 */ GIR_Done,
7781 /* 19840 */ // Label 625: @19840
7782 /* 19840 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19873), // Rule ID 2332 //
7783 /* 19845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7784 /* 19848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7785 /* 19852 */ // MIs[0] dst
7786 /* 19852 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7787 /* 19855 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7788 /* 19855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
7789 /* 19858 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7790 /* 19860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7791 /* 19866 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7792 /* 19868 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7793 /* 19871 */ GIR_RootConstrainSelectedInstOperands,
7794 /* 19872 */ // GIR_Coverage, 2332,
7795 /* 19872 */ GIR_EraseRootFromParent_Done,
7796 /* 19873 */ // Label 626: @19873
7797 /* 19873 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19901), // Rule ID 2484 //
7798 /* 19878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7799 /* 19881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7800 /* 19885 */ // MIs[0] dst
7801 /* 19885 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7802 /* 19888 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
7803 /* 19888 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
7804 /* 19893 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
7805 /* 19899 */ GIR_RootConstrainSelectedInstOperands,
7806 /* 19900 */ // GIR_Coverage, 2484,
7807 /* 19900 */ GIR_Done,
7808 /* 19901 */ // Label 627: @19901
7809 /* 19901 */ GIM_Reject,
7810 /* 19902 */ // Label 526: @19902
7811 /* 19902 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19935), // Rule ID 1661 //
7812 /* 19907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
7813 /* 19910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7814 /* 19914 */ // MIs[0] dst
7815 /* 19914 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7816 /* 19917 */ // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
7817 /* 19917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
7818 /* 19920 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7819 /* 19922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7820 /* 19928 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7821 /* 19930 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7822 /* 19933 */ GIR_RootConstrainSelectedInstOperands,
7823 /* 19934 */ // GIR_Coverage, 1661,
7824 /* 19934 */ GIR_EraseRootFromParent_Done,
7825 /* 19935 */ // Label 628: @19935
7826 /* 19935 */ GIM_Reject,
7827 /* 19936 */ // Label 527: @19936
7828 /* 19936 */ GIM_Reject,
7829 /* 19937 */ // Label 29: @19937
7830 /* 19937 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(21934),
7831 /* 19942 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7832 /* 19945 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19992), // Rule ID 452 //
7833 /* 19950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7834 /* 19953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7835 /* 19958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7836 /* 19961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7837 /* 19964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7838 /* 19968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7839 /* 19972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7840 /* 19976 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7841 /* 19980 */ // MIs[1] Operand 1
7842 /* 19980 */ // No operand predicates
7843 /* 19980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7844 /* 19982 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7845 /* 19982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
7846 /* 19985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7847 /* 19987 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7848 /* 19990 */ GIR_RootConstrainSelectedInstOperands,
7849 /* 19991 */ // GIR_Coverage, 452,
7850 /* 19991 */ GIR_EraseRootFromParent_Done,
7851 /* 19992 */ // Label 630: @19992
7852 /* 19992 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(20039), // Rule ID 453 //
7853 /* 19997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7854 /* 20000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7855 /* 20005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7856 /* 20008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7857 /* 20011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7858 /* 20015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7859 /* 20019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7860 /* 20023 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7861 /* 20027 */ // MIs[1] Operand 1
7862 /* 20027 */ // No operand predicates
7863 /* 20027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7864 /* 20029 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7865 /* 20029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
7866 /* 20032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7867 /* 20034 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7868 /* 20037 */ GIR_RootConstrainSelectedInstOperands,
7869 /* 20038 */ // GIR_Coverage, 453,
7870 /* 20038 */ GIR_EraseRootFromParent_Done,
7871 /* 20039 */ // Label 631: @20039
7872 /* 20039 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(20086), // Rule ID 1311 //
7873 /* 20044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7874 /* 20047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7875 /* 20052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7876 /* 20055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7877 /* 20058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7878 /* 20062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7879 /* 20066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7880 /* 20070 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7881 /* 20074 */ // MIs[1] Operand 1
7882 /* 20074 */ // No operand predicates
7883 /* 20074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7884 /* 20076 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7885 /* 20076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
7886 /* 20079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7887 /* 20081 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7888 /* 20084 */ GIR_RootConstrainSelectedInstOperands,
7889 /* 20085 */ // GIR_Coverage, 1311,
7890 /* 20085 */ GIR_EraseRootFromParent_Done,
7891 /* 20086 */ // Label 632: @20086
7892 /* 20086 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(20133), // Rule ID 1312 //
7893 /* 20091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7894 /* 20094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7895 /* 20099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7896 /* 20102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7897 /* 20105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7898 /* 20109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7899 /* 20113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7900 /* 20117 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7901 /* 20121 */ // MIs[1] Operand 1
7902 /* 20121 */ // No operand predicates
7903 /* 20121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7904 /* 20123 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7905 /* 20123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
7906 /* 20126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7907 /* 20128 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7908 /* 20131 */ GIR_RootConstrainSelectedInstOperands,
7909 /* 20132 */ // GIR_Coverage, 1312,
7910 /* 20132 */ GIR_EraseRootFromParent_Done,
7911 /* 20133 */ // Label 633: @20133
7912 /* 20133 */ GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(20169), // Rule ID 386 //
7913 /* 20138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7914 /* 20141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7915 /* 20146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7916 /* 20149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7917 /* 20152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7918 /* 20156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7919 /* 20160 */ // (intrinsic_wo_chain:{ *:[i32] } 8510:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7920 /* 20160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
7921 /* 20163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7922 /* 20165 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7923 /* 20167 */ GIR_RootConstrainSelectedInstOperands,
7924 /* 20168 */ // GIR_Coverage, 386,
7925 /* 20168 */ GIR_EraseRootFromParent_Done,
7926 /* 20169 */ // Label 634: @20169
7927 /* 20169 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(20205), // Rule ID 393 //
7928 /* 20174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7929 /* 20177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7930 /* 20182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7931 /* 20185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7932 /* 20188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7933 /* 20192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7934 /* 20196 */ // (intrinsic_wo_chain:{ *:[i32] } 8492:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7935 /* 20196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7936 /* 20199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7937 /* 20201 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7938 /* 20203 */ GIR_RootConstrainSelectedInstOperands,
7939 /* 20204 */ // GIR_Coverage, 393,
7940 /* 20204 */ GIR_EraseRootFromParent_Done,
7941 /* 20205 */ // Label 635: @20205
7942 /* 20205 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(20241), // Rule ID 394 //
7943 /* 20210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7944 /* 20213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7945 /* 20218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7946 /* 20221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7947 /* 20224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7948 /* 20228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7949 /* 20232 */ // (intrinsic_wo_chain:{ *:[i32] } 8493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7950 /* 20232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7951 /* 20235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7952 /* 20237 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7953 /* 20239 */ GIR_RootConstrainSelectedInstOperands,
7954 /* 20240 */ // GIR_Coverage, 394,
7955 /* 20240 */ GIR_EraseRootFromParent_Done,
7956 /* 20241 */ // Label 636: @20241
7957 /* 20241 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(20277), // Rule ID 395 //
7958 /* 20246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7959 /* 20249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7960 /* 20254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7961 /* 20257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7962 /* 20260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7963 /* 20264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7964 /* 20268 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7965 /* 20268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7966 /* 20271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7967 /* 20273 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7968 /* 20275 */ GIR_RootConstrainSelectedInstOperands,
7969 /* 20276 */ // GIR_Coverage, 395,
7970 /* 20276 */ GIR_EraseRootFromParent_Done,
7971 /* 20277 */ // Label 637: @20277
7972 /* 20277 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(20313), // Rule ID 396 //
7973 /* 20282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7974 /* 20285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7975 /* 20290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7976 /* 20293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7977 /* 20296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7978 /* 20300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7979 /* 20304 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7980 /* 20304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7981 /* 20307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7982 /* 20309 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7983 /* 20311 */ GIR_RootConstrainSelectedInstOperands,
7984 /* 20312 */ // GIR_Coverage, 396,
7985 /* 20312 */ GIR_EraseRootFromParent_Done,
7986 /* 20313 */ // Label 638: @20313
7987 /* 20313 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(20349), // Rule ID 397 //
7988 /* 20318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7989 /* 20321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7990 /* 20326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7991 /* 20329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7992 /* 20332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7993 /* 20336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7994 /* 20340 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7995 /* 20340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7996 /* 20343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7997 /* 20345 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7998 /* 20347 */ GIR_RootConstrainSelectedInstOperands,
7999 /* 20348 */ // GIR_Coverage, 397,
8000 /* 20348 */ GIR_EraseRootFromParent_Done,
8001 /* 20349 */ // Label 639: @20349
8002 /* 20349 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(20385), // Rule ID 398 //
8003 /* 20354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8004 /* 20357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
8005 /* 20362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8006 /* 20365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8007 /* 20368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8008 /* 20372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8009 /* 20376 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8010 /* 20376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
8011 /* 20379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8012 /* 20381 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8013 /* 20383 */ GIR_RootConstrainSelectedInstOperands,
8014 /* 20384 */ // GIR_Coverage, 398,
8015 /* 20384 */ GIR_EraseRootFromParent_Done,
8016 /* 20385 */ // Label 640: @20385
8017 /* 20385 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(20421), // Rule ID 399 //
8018 /* 20390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8019 /* 20393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
8020 /* 20398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8021 /* 20401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8022 /* 20404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8023 /* 20408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8024 /* 20412 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8498:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8025 /* 20412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
8026 /* 20415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8027 /* 20417 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8028 /* 20419 */ GIR_RootConstrainSelectedInstOperands,
8029 /* 20420 */ // GIR_Coverage, 399,
8030 /* 20420 */ GIR_EraseRootFromParent_Done,
8031 /* 20421 */ // Label 641: @20421
8032 /* 20421 */ GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(20457), // Rule ID 400 //
8033 /* 20426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8034 /* 20429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
8035 /* 20434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8036 /* 20437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8037 /* 20440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8038 /* 20444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8039 /* 20448 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8500:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8040 /* 20448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
8041 /* 20451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8042 /* 20453 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8043 /* 20455 */ GIR_RootConstrainSelectedInstOperands,
8044 /* 20456 */ // GIR_Coverage, 400,
8045 /* 20456 */ GIR_EraseRootFromParent_Done,
8046 /* 20457 */ // Label 642: @20457
8047 /* 20457 */ GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(20493), // Rule ID 401 //
8048 /* 20462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8049 /* 20465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
8050 /* 20470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8051 /* 20473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8052 /* 20476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8053 /* 20480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8054 /* 20484 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8055 /* 20484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
8056 /* 20487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8057 /* 20489 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8058 /* 20491 */ GIR_RootConstrainSelectedInstOperands,
8059 /* 20492 */ // GIR_Coverage, 401,
8060 /* 20492 */ GIR_EraseRootFromParent_Done,
8061 /* 20493 */ // Label 643: @20493
8062 /* 20493 */ GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(20529), // Rule ID 402 //
8063 /* 20498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8064 /* 20501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
8065 /* 20506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8066 /* 20509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8067 /* 20512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8068 /* 20516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8069 /* 20520 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8070 /* 20520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
8071 /* 20523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8072 /* 20525 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8073 /* 20527 */ GIR_RootConstrainSelectedInstOperands,
8074 /* 20528 */ // GIR_Coverage, 402,
8075 /* 20528 */ GIR_EraseRootFromParent_Done,
8076 /* 20529 */ // Label 644: @20529
8077 /* 20529 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20565), // Rule ID 450 //
8078 /* 20534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8079 /* 20537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8080 /* 20542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8081 /* 20545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8082 /* 20548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8083 /* 20552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8084 /* 20556 */ // (intrinsic_wo_chain:{ *:[i32] } 8066:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
8085 /* 20556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
8086 /* 20559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8087 /* 20561 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8088 /* 20563 */ GIR_RootConstrainSelectedInstOperands,
8089 /* 20564 */ // GIR_Coverage, 450,
8090 /* 20564 */ GIR_EraseRootFromParent_Done,
8091 /* 20565 */ // Label 645: @20565
8092 /* 20565 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20601), // Rule ID 454 //
8093 /* 20570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8094 /* 20573 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8095 /* 20578 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8096 /* 20581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8097 /* 20584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8098 /* 20588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8099 /* 20592 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
8100 /* 20592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
8101 /* 20595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8102 /* 20597 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8103 /* 20599 */ GIR_RootConstrainSelectedInstOperands,
8104 /* 20600 */ // GIR_Coverage, 454,
8105 /* 20600 */ GIR_EraseRootFromParent_Done,
8106 /* 20601 */ // Label 646: @20601
8107 /* 20601 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(20637), // Rule ID 455 //
8108 /* 20606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8109 /* 20609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8110 /* 20614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8111 /* 20617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8112 /* 20620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8113 /* 20624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8114 /* 20628 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
8115 /* 20628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
8116 /* 20631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8117 /* 20633 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8118 /* 20635 */ GIR_RootConstrainSelectedInstOperands,
8119 /* 20636 */ // GIR_Coverage, 455,
8120 /* 20636 */ GIR_EraseRootFromParent_Done,
8121 /* 20637 */ // Label 647: @20637
8122 /* 20637 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20673), // Rule ID 704 //
8123 /* 20642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8124 /* 20645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
8125 /* 20650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8126 /* 20653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8127 /* 20656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8128 /* 20660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8129 /* 20664 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8218:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8130 /* 20664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
8131 /* 20667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8132 /* 20669 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8133 /* 20671 */ GIR_RootConstrainSelectedInstOperands,
8134 /* 20672 */ // GIR_Coverage, 704,
8135 /* 20672 */ GIR_EraseRootFromParent_Done,
8136 /* 20673 */ // Label 648: @20673
8137 /* 20673 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20709), // Rule ID 705 //
8138 /* 20678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8139 /* 20681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
8140 /* 20686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8141 /* 20689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8142 /* 20692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8143 /* 20696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8144 /* 20700 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8217:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8145 /* 20700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
8146 /* 20703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8147 /* 20705 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8148 /* 20707 */ GIR_RootConstrainSelectedInstOperands,
8149 /* 20708 */ // GIR_Coverage, 705,
8150 /* 20708 */ GIR_EraseRootFromParent_Done,
8151 /* 20709 */ // Label 649: @20709
8152 /* 20709 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20745), // Rule ID 728 //
8153 /* 20714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8154 /* 20717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
8155 /* 20722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8156 /* 20725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8157 /* 20728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8158 /* 20732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8159 /* 20736 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8244:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
8160 /* 20736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
8161 /* 20739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8162 /* 20741 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8163 /* 20743 */ GIR_RootConstrainSelectedInstOperands,
8164 /* 20744 */ // GIR_Coverage, 728,
8165 /* 20744 */ GIR_EraseRootFromParent_Done,
8166 /* 20745 */ // Label 650: @20745
8167 /* 20745 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20781), // Rule ID 729 //
8168 /* 20750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8169 /* 20753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
8170 /* 20758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8171 /* 20761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8172 /* 20764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8173 /* 20768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8174 /* 20772 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8243:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8175 /* 20772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
8176 /* 20775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8177 /* 20777 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8178 /* 20779 */ GIR_RootConstrainSelectedInstOperands,
8179 /* 20780 */ // GIR_Coverage, 729,
8180 /* 20780 */ GIR_EraseRootFromParent_Done,
8181 /* 20781 */ // Label 651: @20781
8182 /* 20781 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20817), // Rule ID 730 //
8183 /* 20786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8184 /* 20789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
8185 /* 20794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8186 /* 20797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8187 /* 20800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8188 /* 20804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8189 /* 20808 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8246:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
8190 /* 20808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
8191 /* 20811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8192 /* 20813 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8193 /* 20815 */ GIR_RootConstrainSelectedInstOperands,
8194 /* 20816 */ // GIR_Coverage, 730,
8195 /* 20816 */ GIR_EraseRootFromParent_Done,
8196 /* 20817 */ // Label 652: @20817
8197 /* 20817 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20853), // Rule ID 731 //
8198 /* 20822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8199 /* 20825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
8200 /* 20830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8201 /* 20833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8202 /* 20836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8203 /* 20840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8204 /* 20844 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8245:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8205 /* 20844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
8206 /* 20847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8207 /* 20849 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8208 /* 20851 */ GIR_RootConstrainSelectedInstOperands,
8209 /* 20852 */ // GIR_Coverage, 731,
8210 /* 20852 */ GIR_EraseRootFromParent_Done,
8211 /* 20853 */ // Label 653: @20853
8212 /* 20853 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20889), // Rule ID 736 //
8213 /* 20858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8214 /* 20861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
8215 /* 20866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8216 /* 20869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8217 /* 20872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8218 /* 20876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8219 /* 20880 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8220 /* 20880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
8221 /* 20883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8222 /* 20885 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8223 /* 20887 */ GIR_RootConstrainSelectedInstOperands,
8224 /* 20888 */ // GIR_Coverage, 736,
8225 /* 20888 */ GIR_EraseRootFromParent_Done,
8226 /* 20889 */ // Label 654: @20889
8227 /* 20889 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20925), // Rule ID 737 //
8228 /* 20894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8229 /* 20897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
8230 /* 20902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8231 /* 20905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8232 /* 20908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8233 /* 20912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8234 /* 20916 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8251:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8235 /* 20916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
8236 /* 20919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8237 /* 20921 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8238 /* 20923 */ GIR_RootConstrainSelectedInstOperands,
8239 /* 20924 */ // GIR_Coverage, 737,
8240 /* 20924 */ GIR_EraseRootFromParent_Done,
8241 /* 20925 */ // Label 655: @20925
8242 /* 20925 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20961), // Rule ID 738 //
8243 /* 20930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8244 /* 20933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
8245 /* 20938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8246 /* 20941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8247 /* 20944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8248 /* 20948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8249 /* 20952 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8254:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8250 /* 20952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
8251 /* 20955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8252 /* 20957 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8253 /* 20959 */ GIR_RootConstrainSelectedInstOperands,
8254 /* 20960 */ // GIR_Coverage, 738,
8255 /* 20960 */ GIR_EraseRootFromParent_Done,
8256 /* 20961 */ // Label 656: @20961
8257 /* 20961 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20997), // Rule ID 739 //
8258 /* 20966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8259 /* 20969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
8260 /* 20974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8261 /* 20977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8262 /* 20980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8263 /* 20984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8264 /* 20988 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8265 /* 20988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
8266 /* 20991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8267 /* 20993 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8268 /* 20995 */ GIR_RootConstrainSelectedInstOperands,
8269 /* 20996 */ // GIR_Coverage, 739,
8270 /* 20996 */ GIR_EraseRootFromParent_Done,
8271 /* 20997 */ // Label 657: @20997
8272 /* 20997 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(21033), // Rule ID 764 //
8273 /* 21002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8274 /* 21005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
8275 /* 21010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8276 /* 21013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8277 /* 21016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8278 /* 21020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8279 /* 21024 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8276:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8280 /* 21024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
8281 /* 21027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8282 /* 21029 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8283 /* 21031 */ GIR_RootConstrainSelectedInstOperands,
8284 /* 21032 */ // GIR_Coverage, 764,
8285 /* 21032 */ GIR_EraseRootFromParent_Done,
8286 /* 21033 */ // Label 658: @21033
8287 /* 21033 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(21069), // Rule ID 765 //
8288 /* 21038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8289 /* 21041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
8290 /* 21046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8291 /* 21049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8292 /* 21052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8293 /* 21056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8294 /* 21060 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8275:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8295 /* 21060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
8296 /* 21063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8297 /* 21065 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8298 /* 21067 */ GIR_RootConstrainSelectedInstOperands,
8299 /* 21068 */ // GIR_Coverage, 765,
8300 /* 21068 */ GIR_EraseRootFromParent_Done,
8301 /* 21069 */ // Label 659: @21069
8302 /* 21069 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(21105), // Rule ID 766 //
8303 /* 21074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8304 /* 21077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
8305 /* 21082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8306 /* 21085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8307 /* 21088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8308 /* 21092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8309 /* 21096 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8310 /* 21096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
8311 /* 21099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8312 /* 21101 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8313 /* 21103 */ GIR_RootConstrainSelectedInstOperands,
8314 /* 21104 */ // GIR_Coverage, 766,
8315 /* 21104 */ GIR_EraseRootFromParent_Done,
8316 /* 21105 */ // Label 660: @21105
8317 /* 21105 */ GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(21141), // Rule ID 767 //
8318 /* 21110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8319 /* 21113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
8320 /* 21118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8321 /* 21121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8322 /* 21124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8323 /* 21128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8324 /* 21132 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8279:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8325 /* 21132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
8326 /* 21135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8327 /* 21137 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8328 /* 21139 */ GIR_RootConstrainSelectedInstOperands,
8329 /* 21140 */ // GIR_Coverage, 767,
8330 /* 21140 */ GIR_EraseRootFromParent_Done,
8331 /* 21141 */ // Label 661: @21141
8332 /* 21141 */ GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(21177), // Rule ID 794 //
8333 /* 21146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8334 /* 21149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
8335 /* 21154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8336 /* 21157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8337 /* 21160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8338 /* 21164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8339 /* 21168 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8308:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8340 /* 21168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
8341 /* 21171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8342 /* 21173 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8343 /* 21175 */ GIR_RootConstrainSelectedInstOperands,
8344 /* 21176 */ // GIR_Coverage, 794,
8345 /* 21176 */ GIR_EraseRootFromParent_Done,
8346 /* 21177 */ // Label 662: @21177
8347 /* 21177 */ GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(21213), // Rule ID 795 //
8348 /* 21182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8349 /* 21185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
8350 /* 21190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8351 /* 21193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8352 /* 21196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8353 /* 21200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8354 /* 21204 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8307:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8355 /* 21204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
8356 /* 21207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8357 /* 21209 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8358 /* 21211 */ GIR_RootConstrainSelectedInstOperands,
8359 /* 21212 */ // GIR_Coverage, 795,
8360 /* 21212 */ GIR_EraseRootFromParent_Done,
8361 /* 21213 */ // Label 663: @21213
8362 /* 21213 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(21249), // Rule ID 796 //
8363 /* 21218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8364 /* 21221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
8365 /* 21226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8366 /* 21229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8367 /* 21232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8368 /* 21236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8369 /* 21240 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8310:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8370 /* 21240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
8371 /* 21243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8372 /* 21245 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8373 /* 21247 */ GIR_RootConstrainSelectedInstOperands,
8374 /* 21248 */ // GIR_Coverage, 796,
8375 /* 21248 */ GIR_EraseRootFromParent_Done,
8376 /* 21249 */ // Label 664: @21249
8377 /* 21249 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(21285), // Rule ID 797 //
8378 /* 21254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8379 /* 21257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
8380 /* 21262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8381 /* 21265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8382 /* 21268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8383 /* 21272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8384 /* 21276 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8309:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8385 /* 21276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
8386 /* 21279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8387 /* 21281 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8388 /* 21283 */ GIR_RootConstrainSelectedInstOperands,
8389 /* 21284 */ // GIR_Coverage, 797,
8390 /* 21284 */ GIR_EraseRootFromParent_Done,
8391 /* 21285 */ // Label 665: @21285
8392 /* 21285 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(21321), // Rule ID 932 //
8393 /* 21290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8394 /* 21293 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
8395 /* 21298 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8396 /* 21301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8397 /* 21304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8398 /* 21308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8399 /* 21312 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8465:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
8400 /* 21312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
8401 /* 21315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8402 /* 21317 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8403 /* 21319 */ GIR_RootConstrainSelectedInstOperands,
8404 /* 21320 */ // GIR_Coverage, 932,
8405 /* 21320 */ GIR_EraseRootFromParent_Done,
8406 /* 21321 */ // Label 666: @21321
8407 /* 21321 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21357), // Rule ID 933 //
8408 /* 21326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8409 /* 21329 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
8410 /* 21334 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8411 /* 21337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8412 /* 21340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8413 /* 21344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8414 /* 21348 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8467:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8415 /* 21348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
8416 /* 21351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8417 /* 21353 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8418 /* 21355 */ GIR_RootConstrainSelectedInstOperands,
8419 /* 21356 */ // GIR_Coverage, 933,
8420 /* 21356 */ GIR_EraseRootFromParent_Done,
8421 /* 21357 */ // Label 667: @21357
8422 /* 21357 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21393), // Rule ID 934 //
8423 /* 21362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8424 /* 21365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
8425 /* 21370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8426 /* 21373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8427 /* 21376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8428 /* 21380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8429 /* 21384 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8468:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8430 /* 21384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
8431 /* 21387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8432 /* 21389 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8433 /* 21391 */ GIR_RootConstrainSelectedInstOperands,
8434 /* 21392 */ // GIR_Coverage, 934,
8435 /* 21392 */ GIR_EraseRootFromParent_Done,
8436 /* 21393 */ // Label 668: @21393
8437 /* 21393 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21429), // Rule ID 935 //
8438 /* 21398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8439 /* 21401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
8440 /* 21406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8441 /* 21409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8442 /* 21412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8443 /* 21416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8444 /* 21420 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8466:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
8445 /* 21420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
8446 /* 21423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8447 /* 21425 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8448 /* 21427 */ GIR_RootConstrainSelectedInstOperands,
8449 /* 21428 */ // GIR_Coverage, 935,
8450 /* 21428 */ GIR_EraseRootFromParent_Done,
8451 /* 21429 */ // Label 669: @21429
8452 /* 21429 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21465), // Rule ID 1274 //
8453 /* 21434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8454 /* 21437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
8455 /* 21442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8456 /* 21445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8457 /* 21448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8458 /* 21452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8459 /* 21456 */ // (intrinsic_wo_chain:{ *:[i32] } 8492:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8460 /* 21456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
8461 /* 21459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8462 /* 21461 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8463 /* 21463 */ GIR_RootConstrainSelectedInstOperands,
8464 /* 21464 */ // GIR_Coverage, 1274,
8465 /* 21464 */ GIR_EraseRootFromParent_Done,
8466 /* 21465 */ // Label 670: @21465
8467 /* 21465 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21501), // Rule ID 1275 //
8468 /* 21470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8469 /* 21473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
8470 /* 21478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8471 /* 21481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8472 /* 21484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8473 /* 21488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8474 /* 21492 */ // (intrinsic_wo_chain:{ *:[i32] } 8493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8475 /* 21492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
8476 /* 21495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8477 /* 21497 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8478 /* 21499 */ GIR_RootConstrainSelectedInstOperands,
8479 /* 21500 */ // GIR_Coverage, 1275,
8480 /* 21500 */ GIR_EraseRootFromParent_Done,
8481 /* 21501 */ // Label 671: @21501
8482 /* 21501 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21537), // Rule ID 1276 //
8483 /* 21506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8484 /* 21509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
8485 /* 21514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8486 /* 21517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8487 /* 21520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8488 /* 21524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8489 /* 21528 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8490 /* 21528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
8491 /* 21531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8492 /* 21533 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8493 /* 21535 */ GIR_RootConstrainSelectedInstOperands,
8494 /* 21536 */ // GIR_Coverage, 1276,
8495 /* 21536 */ GIR_EraseRootFromParent_Done,
8496 /* 21537 */ // Label 672: @21537
8497 /* 21537 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21573), // Rule ID 1277 //
8498 /* 21542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8499 /* 21545 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
8500 /* 21550 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8501 /* 21553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8502 /* 21556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8503 /* 21560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8504 /* 21564 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8505 /* 21564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
8506 /* 21567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8507 /* 21569 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8508 /* 21571 */ GIR_RootConstrainSelectedInstOperands,
8509 /* 21572 */ // GIR_Coverage, 1277,
8510 /* 21572 */ GIR_EraseRootFromParent_Done,
8511 /* 21573 */ // Label 673: @21573
8512 /* 21573 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21609), // Rule ID 1278 //
8513 /* 21578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8514 /* 21581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
8515 /* 21586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8516 /* 21589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8517 /* 21592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8518 /* 21596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8519 /* 21600 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8520 /* 21600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
8521 /* 21603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8522 /* 21605 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8523 /* 21607 */ GIR_RootConstrainSelectedInstOperands,
8524 /* 21608 */ // GIR_Coverage, 1278,
8525 /* 21608 */ GIR_EraseRootFromParent_Done,
8526 /* 21609 */ // Label 674: @21609
8527 /* 21609 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21645), // Rule ID 1279 //
8528 /* 21614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8529 /* 21617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
8530 /* 21622 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8531 /* 21625 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8532 /* 21628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8533 /* 21632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8534 /* 21636 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8535 /* 21636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
8536 /* 21639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8537 /* 21641 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8538 /* 21643 */ GIR_RootConstrainSelectedInstOperands,
8539 /* 21644 */ // GIR_Coverage, 1279,
8540 /* 21644 */ GIR_EraseRootFromParent_Done,
8541 /* 21645 */ // Label 675: @21645
8542 /* 21645 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21681), // Rule ID 1280 //
8543 /* 21650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8544 /* 21653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
8545 /* 21658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8546 /* 21661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8547 /* 21664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8548 /* 21668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8549 /* 21672 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8498:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8550 /* 21672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
8551 /* 21675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8552 /* 21677 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8553 /* 21679 */ GIR_RootConstrainSelectedInstOperands,
8554 /* 21680 */ // GIR_Coverage, 1280,
8555 /* 21680 */ GIR_EraseRootFromParent_Done,
8556 /* 21681 */ // Label 676: @21681
8557 /* 21681 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21717), // Rule ID 1281 //
8558 /* 21686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8559 /* 21689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
8560 /* 21694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8561 /* 21697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8562 /* 21700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8563 /* 21704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8564 /* 21708 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8565 /* 21708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
8566 /* 21711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8567 /* 21713 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8568 /* 21715 */ GIR_RootConstrainSelectedInstOperands,
8569 /* 21716 */ // GIR_Coverage, 1281,
8570 /* 21716 */ GIR_EraseRootFromParent_Done,
8571 /* 21717 */ // Label 677: @21717
8572 /* 21717 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21753), // Rule ID 1282 //
8573 /* 21722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8574 /* 21725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
8575 /* 21730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8576 /* 21733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8577 /* 21736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8578 /* 21740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8579 /* 21744 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8500:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8580 /* 21744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
8581 /* 21747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8582 /* 21749 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8583 /* 21751 */ GIR_RootConstrainSelectedInstOperands,
8584 /* 21752 */ // GIR_Coverage, 1282,
8585 /* 21752 */ GIR_EraseRootFromParent_Done,
8586 /* 21753 */ // Label 678: @21753
8587 /* 21753 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21789), // Rule ID 1283 //
8588 /* 21758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8589 /* 21761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
8590 /* 21766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8591 /* 21769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8592 /* 21772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8593 /* 21776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8594 /* 21780 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8595 /* 21780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
8596 /* 21783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8597 /* 21785 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8598 /* 21787 */ GIR_RootConstrainSelectedInstOperands,
8599 /* 21788 */ // GIR_Coverage, 1283,
8600 /* 21788 */ GIR_EraseRootFromParent_Done,
8601 /* 21789 */ // Label 679: @21789
8602 /* 21789 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21825), // Rule ID 1309 //
8603 /* 21794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8604 /* 21797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
8605 /* 21802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8606 /* 21805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8607 /* 21808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8608 /* 21812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8609 /* 21816 */ // (intrinsic_wo_chain:{ *:[i32] } 8510:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
8610 /* 21816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
8611 /* 21819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8612 /* 21821 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8613 /* 21823 */ GIR_RootConstrainSelectedInstOperands,
8614 /* 21824 */ // GIR_Coverage, 1309,
8615 /* 21824 */ GIR_EraseRootFromParent_Done,
8616 /* 21825 */ // Label 680: @21825
8617 /* 21825 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21861), // Rule ID 1313 //
8618 /* 21830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8619 /* 21833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8620 /* 21838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8621 /* 21841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8622 /* 21844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8623 /* 21848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8624 /* 21852 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8512:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
8625 /* 21852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
8626 /* 21855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8627 /* 21857 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8628 /* 21859 */ GIR_RootConstrainSelectedInstOperands,
8629 /* 21860 */ // GIR_Coverage, 1313,
8630 /* 21860 */ GIR_EraseRootFromParent_Done,
8631 /* 21861 */ // Label 681: @21861
8632 /* 21861 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21897), // Rule ID 1314 //
8633 /* 21866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8634 /* 21869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8635 /* 21874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8636 /* 21877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8637 /* 21880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8638 /* 21884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8639 /* 21888 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8513:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
8640 /* 21888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
8641 /* 21891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8642 /* 21893 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8643 /* 21895 */ GIR_RootConstrainSelectedInstOperands,
8644 /* 21896 */ // GIR_Coverage, 1314,
8645 /* 21896 */ GIR_EraseRootFromParent_Done,
8646 /* 21897 */ // Label 682: @21897
8647 /* 21897 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21933), // Rule ID 1324 //
8648 /* 21902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8649 /* 21905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8650 /* 21910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8651 /* 21913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8652 /* 21916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8653 /* 21920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8654 /* 21924 */ // (intrinsic_wo_chain:{ *:[i32] } 8066:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
8655 /* 21924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
8656 /* 21927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8657 /* 21929 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8658 /* 21931 */ GIR_RootConstrainSelectedInstOperands,
8659 /* 21932 */ // GIR_Coverage, 1324,
8660 /* 21932 */ GIR_EraseRootFromParent_Done,
8661 /* 21933 */ // Label 683: @21933
8662 /* 21933 */ GIM_Reject,
8663 /* 21934 */ // Label 629: @21934
8664 /* 21934 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31687),
8665 /* 21939 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
8666 /* 21942 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21988), // Rule ID 962 //
8667 /* 21947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8668 /* 21950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
8669 /* 21955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8670 /* 21958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8671 /* 21961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8672 /* 21965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8673 /* 21969 */ // MIs[0] m
8674 /* 21969 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8675 /* 21972 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8676 /* 21977 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8514:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8677 /* 21977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
8678 /* 21980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8679 /* 21982 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8680 /* 21984 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8681 /* 21986 */ GIR_RootConstrainSelectedInstOperands,
8682 /* 21987 */ // GIR_Coverage, 962,
8683 /* 21987 */ GIR_EraseRootFromParent_Done,
8684 /* 21988 */ // Label 685: @21988
8685 /* 21988 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(22034), // Rule ID 963 //
8686 /* 21993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8687 /* 21996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
8688 /* 22001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8689 /* 22004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8690 /* 22007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8691 /* 22011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8692 /* 22015 */ // MIs[0] m
8693 /* 22015 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8694 /* 22018 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8695 /* 22023 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8516:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8696 /* 22023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
8697 /* 22026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8698 /* 22028 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8699 /* 22030 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8700 /* 22032 */ GIR_RootConstrainSelectedInstOperands,
8701 /* 22033 */ // GIR_Coverage, 963,
8702 /* 22033 */ GIR_EraseRootFromParent_Done,
8703 /* 22034 */ // Label 686: @22034
8704 /* 22034 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(22080), // Rule ID 964 //
8705 /* 22039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8706 /* 22042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
8707 /* 22047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8708 /* 22050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8709 /* 22053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8710 /* 22057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8711 /* 22061 */ // MIs[0] m
8712 /* 22061 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8713 /* 22064 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8714 /* 22069 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8517:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8715 /* 22069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
8716 /* 22072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8717 /* 22074 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8718 /* 22076 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8719 /* 22078 */ GIR_RootConstrainSelectedInstOperands,
8720 /* 22079 */ // GIR_Coverage, 964,
8721 /* 22079 */ GIR_EraseRootFromParent_Done,
8722 /* 22080 */ // Label 687: @22080
8723 /* 22080 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(22126), // Rule ID 965 //
8724 /* 22085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8725 /* 22088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8726 /* 22093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8727 /* 22096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8728 /* 22099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8729 /* 22103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8730 /* 22107 */ // MIs[0] m
8731 /* 22107 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8732 /* 22110 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8733 /* 22115 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8515:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8734 /* 22115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
8735 /* 22118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8736 /* 22120 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8737 /* 22122 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8738 /* 22124 */ GIR_RootConstrainSelectedInstOperands,
8739 /* 22125 */ // GIR_Coverage, 965,
8740 /* 22125 */ GIR_EraseRootFromParent_Done,
8741 /* 22126 */ // Label 688: @22126
8742 /* 22126 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(22172), // Rule ID 966 //
8743 /* 22131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8744 /* 22134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8745 /* 22139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8746 /* 22142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8747 /* 22145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8748 /* 22149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8749 /* 22153 */ // MIs[0] m
8750 /* 22153 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8751 /* 22156 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8752 /* 22161 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8518:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8753 /* 22161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
8754 /* 22164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8755 /* 22166 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8756 /* 22168 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8757 /* 22170 */ GIR_RootConstrainSelectedInstOperands,
8758 /* 22171 */ // GIR_Coverage, 966,
8759 /* 22171 */ GIR_EraseRootFromParent_Done,
8760 /* 22172 */ // Label 689: @22172
8761 /* 22172 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(22218), // Rule ID 967 //
8762 /* 22177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8763 /* 22180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8764 /* 22185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8765 /* 22188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8766 /* 22191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8767 /* 22195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8768 /* 22199 */ // MIs[0] m
8769 /* 22199 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8770 /* 22202 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8771 /* 22207 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8520:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8772 /* 22207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
8773 /* 22210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8774 /* 22212 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8775 /* 22214 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8776 /* 22216 */ GIR_RootConstrainSelectedInstOperands,
8777 /* 22217 */ // GIR_Coverage, 967,
8778 /* 22217 */ GIR_EraseRootFromParent_Done,
8779 /* 22218 */ // Label 690: @22218
8780 /* 22218 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(22264), // Rule ID 968 //
8781 /* 22223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8782 /* 22226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8783 /* 22231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8784 /* 22234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8785 /* 22237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8786 /* 22241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8787 /* 22245 */ // MIs[0] m
8788 /* 22245 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8789 /* 22248 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8790 /* 22253 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8521:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8791 /* 22253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
8792 /* 22256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8793 /* 22258 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8794 /* 22260 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8795 /* 22262 */ GIR_RootConstrainSelectedInstOperands,
8796 /* 22263 */ // GIR_Coverage, 968,
8797 /* 22263 */ GIR_EraseRootFromParent_Done,
8798 /* 22264 */ // Label 691: @22264
8799 /* 22264 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(22310), // Rule ID 969 //
8800 /* 22269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8801 /* 22272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8802 /* 22277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8803 /* 22280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8804 /* 22283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8805 /* 22287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8806 /* 22291 */ // MIs[0] m
8807 /* 22291 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8808 /* 22294 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8809 /* 22299 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8519:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8810 /* 22299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
8811 /* 22302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8812 /* 22304 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8813 /* 22306 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8814 /* 22308 */ GIR_RootConstrainSelectedInstOperands,
8815 /* 22309 */ // GIR_Coverage, 969,
8816 /* 22309 */ GIR_EraseRootFromParent_Done,
8817 /* 22310 */ // Label 692: @22310
8818 /* 22310 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(22356), // Rule ID 1009 //
8819 /* 22315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8820 /* 22318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
8821 /* 22323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8822 /* 22326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8823 /* 22329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8824 /* 22333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8825 /* 22337 */ // MIs[0] m
8826 /* 22337 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8827 /* 22340 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8828 /* 22345 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8573:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8829 /* 22345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
8830 /* 22348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8831 /* 22350 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8832 /* 22352 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8833 /* 22354 */ GIR_RootConstrainSelectedInstOperands,
8834 /* 22355 */ // GIR_Coverage, 1009,
8835 /* 22355 */ GIR_EraseRootFromParent_Done,
8836 /* 22356 */ // Label 693: @22356
8837 /* 22356 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(22402), // Rule ID 1010 //
8838 /* 22361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8839 /* 22364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
8840 /* 22369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8841 /* 22372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8842 /* 22375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8843 /* 22379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8844 /* 22383 */ // MIs[0] m
8845 /* 22383 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8846 /* 22386 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8847 /* 22391 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8575:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8848 /* 22391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
8849 /* 22394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8850 /* 22396 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8851 /* 22398 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8852 /* 22400 */ GIR_RootConstrainSelectedInstOperands,
8853 /* 22401 */ // GIR_Coverage, 1010,
8854 /* 22401 */ GIR_EraseRootFromParent_Done,
8855 /* 22402 */ // Label 694: @22402
8856 /* 22402 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(22448), // Rule ID 1011 //
8857 /* 22407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8858 /* 22410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
8859 /* 22415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8860 /* 22418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8861 /* 22421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8862 /* 22425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8863 /* 22429 */ // MIs[0] m
8864 /* 22429 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8865 /* 22432 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8866 /* 22437 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8576:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8867 /* 22437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
8868 /* 22440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8869 /* 22442 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8870 /* 22444 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8871 /* 22446 */ GIR_RootConstrainSelectedInstOperands,
8872 /* 22447 */ // GIR_Coverage, 1011,
8873 /* 22447 */ GIR_EraseRootFromParent_Done,
8874 /* 22448 */ // Label 695: @22448
8875 /* 22448 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(22494), // Rule ID 1012 //
8876 /* 22453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8877 /* 22456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
8878 /* 22461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8879 /* 22464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8880 /* 22467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8881 /* 22471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8882 /* 22475 */ // MIs[0] m
8883 /* 22475 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8884 /* 22478 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8885 /* 22483 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8574:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8886 /* 22483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
8887 /* 22486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8888 /* 22488 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8889 /* 22490 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8890 /* 22492 */ GIR_RootConstrainSelectedInstOperands,
8891 /* 22493 */ // GIR_Coverage, 1012,
8892 /* 22493 */ GIR_EraseRootFromParent_Done,
8893 /* 22494 */ // Label 696: @22494
8894 /* 22494 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(22540), // Rule ID 1025 //
8895 /* 22499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8896 /* 22502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
8897 /* 22507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8898 /* 22510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8899 /* 22513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8900 /* 22517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8901 /* 22521 */ // MIs[0] m
8902 /* 22521 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8903 /* 22524 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8904 /* 22529 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8589:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8905 /* 22529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
8906 /* 22532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8907 /* 22534 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8908 /* 22536 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8909 /* 22538 */ GIR_RootConstrainSelectedInstOperands,
8910 /* 22539 */ // GIR_Coverage, 1025,
8911 /* 22539 */ GIR_EraseRootFromParent_Done,
8912 /* 22540 */ // Label 697: @22540
8913 /* 22540 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(22586), // Rule ID 1026 //
8914 /* 22545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8915 /* 22548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
8916 /* 22553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8917 /* 22556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8918 /* 22559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8919 /* 22563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8920 /* 22567 */ // MIs[0] m
8921 /* 22567 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8922 /* 22570 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8923 /* 22575 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8591:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8924 /* 22575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
8925 /* 22578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8926 /* 22580 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8927 /* 22582 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8928 /* 22584 */ GIR_RootConstrainSelectedInstOperands,
8929 /* 22585 */ // GIR_Coverage, 1026,
8930 /* 22585 */ GIR_EraseRootFromParent_Done,
8931 /* 22586 */ // Label 698: @22586
8932 /* 22586 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(22632), // Rule ID 1027 //
8933 /* 22591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8934 /* 22594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
8935 /* 22599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8936 /* 22602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8937 /* 22605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8938 /* 22609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8939 /* 22613 */ // MIs[0] m
8940 /* 22613 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8941 /* 22616 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8942 /* 22621 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8592:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8943 /* 22621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
8944 /* 22624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8945 /* 22626 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8946 /* 22628 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8947 /* 22630 */ GIR_RootConstrainSelectedInstOperands,
8948 /* 22631 */ // GIR_Coverage, 1027,
8949 /* 22631 */ GIR_EraseRootFromParent_Done,
8950 /* 22632 */ // Label 699: @22632
8951 /* 22632 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(22678), // Rule ID 1028 //
8952 /* 22637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8953 /* 22640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
8954 /* 22645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8955 /* 22648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8956 /* 22651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8957 /* 22655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8958 /* 22659 */ // MIs[0] m
8959 /* 22659 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8960 /* 22662 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8961 /* 22667 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8590:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8962 /* 22667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
8963 /* 22670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8964 /* 22672 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8965 /* 22674 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8966 /* 22676 */ GIR_RootConstrainSelectedInstOperands,
8967 /* 22677 */ // GIR_Coverage, 1028,
8968 /* 22677 */ GIR_EraseRootFromParent_Done,
8969 /* 22678 */ // Label 700: @22678
8970 /* 22678 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(22734), // Rule ID 409 //
8971 /* 22683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8972 /* 22686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8973 /* 22691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8974 /* 22694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8975 /* 22697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8976 /* 22700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8977 /* 22704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8978 /* 22708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8979 /* 22712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8980 /* 22716 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8981 /* 22720 */ // MIs[1] Operand 1
8982 /* 22720 */ // No operand predicates
8983 /* 22720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8984 /* 22722 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8532:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8985 /* 22722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
8986 /* 22725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8987 /* 22727 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8988 /* 22729 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8989 /* 22732 */ GIR_RootConstrainSelectedInstOperands,
8990 /* 22733 */ // GIR_Coverage, 409,
8991 /* 22733 */ GIR_EraseRootFromParent_Done,
8992 /* 22734 */ // Label 701: @22734
8993 /* 22734 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(22790), // Rule ID 413 //
8994 /* 22739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8995 /* 22742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8996 /* 22747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8997 /* 22750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8998 /* 22753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8999 /* 22756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9000 /* 22760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9001 /* 22764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9002 /* 22768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9003 /* 22772 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
9004 /* 22776 */ // MIs[1] Operand 1
9005 /* 22776 */ // No operand predicates
9006 /* 22776 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9007 /* 22778 */ // (intrinsic_wo_chain:{ *:[i32] } 8534:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
9008 /* 22778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
9009 /* 22781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9010 /* 22783 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9011 /* 22785 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
9012 /* 22788 */ GIR_RootConstrainSelectedInstOperands,
9013 /* 22789 */ // GIR_Coverage, 413,
9014 /* 22789 */ GIR_EraseRootFromParent_Done,
9015 /* 22790 */ // Label 702: @22790
9016 /* 22790 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(22846), // Rule ID 504 //
9017 /* 22795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9018 /* 22798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9019 /* 22803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9020 /* 22806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9021 /* 22809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9022 /* 22812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9023 /* 22816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9024 /* 22820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9025 /* 22824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9026 /* 22828 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9027 /* 22832 */ // MIs[1] Operand 1
9028 /* 22832 */ // No operand predicates
9029 /* 22832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9030 /* 22834 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8533:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
9031 /* 22834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
9032 /* 22837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9033 /* 22839 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9034 /* 22841 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
9035 /* 22844 */ GIR_RootConstrainSelectedInstOperands,
9036 /* 22845 */ // GIR_Coverage, 504,
9037 /* 22845 */ GIR_EraseRootFromParent_Done,
9038 /* 22846 */ // Label 703: @22846
9039 /* 22846 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(22902), // Rule ID 1268 //
9040 /* 22851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
9041 /* 22854 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
9042 /* 22859 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9043 /* 22862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9044 /* 22865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9045 /* 22868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9046 /* 22872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9047 /* 22876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9048 /* 22880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9049 /* 22884 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9050 /* 22888 */ // MIs[1] Operand 1
9051 /* 22888 */ // No operand predicates
9052 /* 22888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9053 /* 22890 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8532:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
9054 /* 22890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
9055 /* 22893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9056 /* 22895 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9057 /* 22897 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9058 /* 22900 */ GIR_RootConstrainSelectedInstOperands,
9059 /* 22901 */ // GIR_Coverage, 1268,
9060 /* 22901 */ GIR_EraseRootFromParent_Done,
9061 /* 22902 */ // Label 704: @22902
9062 /* 22902 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(22958), // Rule ID 1272 //
9063 /* 22907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
9064 /* 22910 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
9065 /* 22915 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9066 /* 22918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9067 /* 22921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9068 /* 22924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9069 /* 22928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9070 /* 22932 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9071 /* 22936 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9072 /* 22940 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
9073 /* 22944 */ // MIs[1] Operand 1
9074 /* 22944 */ // No operand predicates
9075 /* 22944 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9076 /* 22946 */ // (intrinsic_wo_chain:{ *:[i32] } 8534:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
9077 /* 22946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
9078 /* 22949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9079 /* 22951 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9080 /* 22953 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9081 /* 22956 */ GIR_RootConstrainSelectedInstOperands,
9082 /* 22957 */ // GIR_Coverage, 1272,
9083 /* 22957 */ GIR_EraseRootFromParent_Done,
9084 /* 22958 */ // Label 705: @22958
9085 /* 22958 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(23014), // Rule ID 1347 //
9086 /* 22963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
9087 /* 22966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9088 /* 22971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9089 /* 22974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9090 /* 22977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9091 /* 22980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9092 /* 22984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9093 /* 22988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9094 /* 22992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9095 /* 22996 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9096 /* 23000 */ // MIs[1] Operand 1
9097 /* 23000 */ // No operand predicates
9098 /* 23000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9099 /* 23002 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8533:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
9100 /* 23002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
9101 /* 23005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9102 /* 23007 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9103 /* 23009 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9104 /* 23012 */ GIR_RootConstrainSelectedInstOperands,
9105 /* 23013 */ // GIR_Coverage, 1347,
9106 /* 23013 */ GIR_EraseRootFromParent_Done,
9107 /* 23014 */ // Label 706: @23014
9108 /* 23014 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(23066), // Rule ID 2070 //
9109 /* 23019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9110 /* 23022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
9111 /* 23027 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9112 /* 23030 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9113 /* 23033 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9114 /* 23036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9115 /* 23040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9116 /* 23044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9117 /* 23048 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9118 /* 23052 */ // MIs[1] Operand 1
9119 /* 23052 */ // No operand predicates
9120 /* 23052 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9121 /* 23054 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8530:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
9122 /* 23054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
9123 /* 23057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9124 /* 23059 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9125 /* 23061 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9126 /* 23064 */ GIR_RootConstrainSelectedInstOperands,
9127 /* 23065 */ // GIR_Coverage, 2070,
9128 /* 23065 */ GIR_EraseRootFromParent_Done,
9129 /* 23066 */ // Label 707: @23066
9130 /* 23066 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(23118), // Rule ID 2071 //
9131 /* 23071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9132 /* 23074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9133 /* 23079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9134 /* 23082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9135 /* 23085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9136 /* 23088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9137 /* 23092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9138 /* 23096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9139 /* 23100 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9140 /* 23104 */ // MIs[1] Operand 1
9141 /* 23104 */ // No operand predicates
9142 /* 23104 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9143 /* 23106 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8535:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
9144 /* 23106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
9145 /* 23109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9146 /* 23111 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9147 /* 23113 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9148 /* 23116 */ GIR_RootConstrainSelectedInstOperands,
9149 /* 23117 */ // GIR_Coverage, 2071,
9150 /* 23117 */ GIR_EraseRootFromParent_Done,
9151 /* 23118 */ // Label 708: @23118
9152 /* 23118 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(23170), // Rule ID 2076 //
9153 /* 23123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9154 /* 23126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
9155 /* 23131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9156 /* 23134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9157 /* 23137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9158 /* 23140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9159 /* 23144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9160 /* 23148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9161 /* 23152 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9162 /* 23156 */ // MIs[1] Operand 1
9163 /* 23156 */ // No operand predicates
9164 /* 23156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9165 /* 23158 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8531:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
9166 /* 23158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
9167 /* 23161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9168 /* 23163 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9169 /* 23165 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9170 /* 23168 */ GIR_RootConstrainSelectedInstOperands,
9171 /* 23169 */ // GIR_Coverage, 2076,
9172 /* 23169 */ GIR_EraseRootFromParent_Done,
9173 /* 23170 */ // Label 709: @23170
9174 /* 23170 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(23222), // Rule ID 2077 //
9175 /* 23175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9176 /* 23178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
9177 /* 23183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9178 /* 23186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9179 /* 23189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9180 /* 23192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9181 /* 23196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9182 /* 23200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9183 /* 23204 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9184 /* 23208 */ // MIs[1] Operand 1
9185 /* 23208 */ // No operand predicates
9186 /* 23208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9187 /* 23210 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8536:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
9188 /* 23210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
9189 /* 23213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9190 /* 23215 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9191 /* 23217 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9192 /* 23220 */ GIR_RootConstrainSelectedInstOperands,
9193 /* 23221 */ // GIR_Coverage, 2077,
9194 /* 23221 */ GIR_EraseRootFromParent_Done,
9195 /* 23222 */ // Label 710: @23222
9196 /* 23222 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(23270), // Rule ID 379 //
9197 /* 23227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9198 /* 23230 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
9199 /* 23235 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9200 /* 23238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9201 /* 23241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9202 /* 23244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9203 /* 23248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9204 /* 23252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9205 /* 23256 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8002:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9206 /* 23256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
9207 /* 23259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9208 /* 23261 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9209 /* 23263 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9210 /* 23265 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9211 /* 23268 */ GIR_RootConstrainSelectedInstOperands,
9212 /* 23269 */ // GIR_Coverage, 379,
9213 /* 23269 */ GIR_EraseRootFromParent_Done,
9214 /* 23270 */ // Label 711: @23270
9215 /* 23270 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(23318), // Rule ID 380 //
9216 /* 23275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9217 /* 23278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
9218 /* 23283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9219 /* 23286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9220 /* 23289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9221 /* 23292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9222 /* 23296 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9223 /* 23300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9224 /* 23304 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8625:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9225 /* 23304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
9226 /* 23307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9227 /* 23309 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9228 /* 23311 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9229 /* 23313 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9230 /* 23316 */ GIR_RootConstrainSelectedInstOperands,
9231 /* 23317 */ // GIR_Coverage, 380,
9232 /* 23317 */ GIR_EraseRootFromParent_Done,
9233 /* 23318 */ // Label 712: @23318
9234 /* 23318 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(23366), // Rule ID 381 //
9235 /* 23323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9236 /* 23326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
9237 /* 23331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9238 /* 23334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9239 /* 23337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9240 /* 23340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9241 /* 23344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9242 /* 23348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9243 /* 23352 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9244 /* 23352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
9245 /* 23355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9246 /* 23357 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9247 /* 23359 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9248 /* 23361 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9249 /* 23364 */ GIR_RootConstrainSelectedInstOperands,
9250 /* 23365 */ // GIR_Coverage, 381,
9251 /* 23365 */ GIR_EraseRootFromParent_Done,
9252 /* 23366 */ // Label 713: @23366
9253 /* 23366 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(23414), // Rule ID 382 //
9254 /* 23371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9255 /* 23374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
9256 /* 23379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9257 /* 23382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9258 /* 23385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9259 /* 23388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9260 /* 23392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9261 /* 23396 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9262 /* 23400 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8600:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9263 /* 23400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
9264 /* 23403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9265 /* 23405 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9266 /* 23407 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9267 /* 23409 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9268 /* 23412 */ GIR_RootConstrainSelectedInstOperands,
9269 /* 23413 */ // GIR_Coverage, 382,
9270 /* 23413 */ GIR_EraseRootFromParent_Done,
9271 /* 23414 */ // Label 714: @23414
9272 /* 23414 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(23459), // Rule ID 385 //
9273 /* 23419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9274 /* 23422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
9275 /* 23427 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9276 /* 23430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9277 /* 23433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9278 /* 23436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9279 /* 23440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9280 /* 23444 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9281 /* 23448 */ // (intrinsic_wo_chain:{ *:[i32] } 8430:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9282 /* 23448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
9283 /* 23451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9284 /* 23453 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9285 /* 23455 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9286 /* 23457 */ GIR_RootConstrainSelectedInstOperands,
9287 /* 23458 */ // GIR_Coverage, 385,
9288 /* 23458 */ GIR_EraseRootFromParent_Done,
9289 /* 23459 */ // Label 715: @23459
9290 /* 23459 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(23504), // Rule ID 389 //
9291 /* 23464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9292 /* 23467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
9293 /* 23472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9294 /* 23475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9295 /* 23478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9296 /* 23481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9297 /* 23485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9298 /* 23489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9299 /* 23493 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8506:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9300 /* 23493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
9301 /* 23496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9302 /* 23498 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9303 /* 23500 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9304 /* 23502 */ GIR_RootConstrainSelectedInstOperands,
9305 /* 23503 */ // GIR_Coverage, 389,
9306 /* 23503 */ GIR_EraseRootFromParent_Done,
9307 /* 23504 */ // Label 716: @23504
9308 /* 23504 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(23549), // Rule ID 390 //
9309 /* 23509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9310 /* 23512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
9311 /* 23517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9312 /* 23520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9313 /* 23523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9314 /* 23526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9315 /* 23530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9316 /* 23534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9317 /* 23538 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8505:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9318 /* 23538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
9319 /* 23541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9320 /* 23543 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9321 /* 23545 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9322 /* 23547 */ GIR_RootConstrainSelectedInstOperands,
9323 /* 23548 */ // GIR_Coverage, 390,
9324 /* 23548 */ GIR_EraseRootFromParent_Done,
9325 /* 23549 */ // Label 717: @23549
9326 /* 23549 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(23594), // Rule ID 404 //
9327 /* 23554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9328 /* 23557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
9329 /* 23562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9330 /* 23565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9331 /* 23568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9332 /* 23571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9333 /* 23575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9334 /* 23579 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9335 /* 23583 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8536:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9336 /* 23583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
9337 /* 23586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9338 /* 23588 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9339 /* 23590 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9340 /* 23592 */ GIR_RootConstrainSelectedInstOperands,
9341 /* 23593 */ // GIR_Coverage, 404,
9342 /* 23593 */ GIR_EraseRootFromParent_Done,
9343 /* 23594 */ // Label 718: @23594
9344 /* 23594 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(23639), // Rule ID 408 //
9345 /* 23599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9346 /* 23602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
9347 /* 23607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9348 /* 23610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9349 /* 23613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9350 /* 23616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9351 /* 23620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9352 /* 23624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9353 /* 23628 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8530:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9354 /* 23628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
9355 /* 23631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9356 /* 23633 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9357 /* 23635 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9358 /* 23637 */ GIR_RootConstrainSelectedInstOperands,
9359 /* 23638 */ // GIR_Coverage, 408,
9360 /* 23638 */ GIR_EraseRootFromParent_Done,
9361 /* 23639 */ // Label 719: @23639
9362 /* 23639 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(23684), // Rule ID 410 //
9363 /* 23644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9364 /* 23647 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
9365 /* 23652 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9366 /* 23655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9367 /* 23658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9368 /* 23661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9369 /* 23665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9370 /* 23669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9371 /* 23673 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8532:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9372 /* 23673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
9373 /* 23676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9374 /* 23678 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9375 /* 23680 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9376 /* 23682 */ GIR_RootConstrainSelectedInstOperands,
9377 /* 23683 */ // GIR_Coverage, 410,
9378 /* 23683 */ GIR_EraseRootFromParent_Done,
9379 /* 23684 */ // Label 720: @23684
9380 /* 23684 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(23729), // Rule ID 414 //
9381 /* 23689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9382 /* 23692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
9383 /* 23697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9384 /* 23700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9385 /* 23703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9386 /* 23706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9387 /* 23710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9388 /* 23714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9389 /* 23718 */ // (intrinsic_wo_chain:{ *:[i32] } 8534:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9390 /* 23718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
9391 /* 23721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9392 /* 23723 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9393 /* 23725 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9394 /* 23727 */ GIR_RootConstrainSelectedInstOperands,
9395 /* 23728 */ // GIR_Coverage, 414,
9396 /* 23728 */ GIR_EraseRootFromParent_Done,
9397 /* 23729 */ // Label 721: @23729
9398 /* 23729 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(23774), // Rule ID 451 //
9399 /* 23734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9400 /* 23737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
9401 /* 23742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9402 /* 23745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9403 /* 23748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9404 /* 23751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9405 /* 23755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9406 /* 23759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9407 /* 23763 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8477:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9408 /* 23763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
9409 /* 23766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9410 /* 23768 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9411 /* 23770 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9412 /* 23772 */ GIR_RootConstrainSelectedInstOperands,
9413 /* 23773 */ // GIR_Coverage, 451,
9414 /* 23773 */ GIR_EraseRootFromParent_Done,
9415 /* 23774 */ // Label 722: @23774
9416 /* 23774 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(23819), // Rule ID 475 //
9417 /* 23779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9418 /* 23782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
9419 /* 23787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9420 /* 23790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9421 /* 23793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9422 /* 23796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9423 /* 23800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9424 /* 23804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9425 /* 23808 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8003:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9426 /* 23808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
9427 /* 23811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9428 /* 23813 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9429 /* 23815 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9430 /* 23817 */ GIR_RootConstrainSelectedInstOperands,
9431 /* 23818 */ // GIR_Coverage, 475,
9432 /* 23818 */ GIR_EraseRootFromParent_Done,
9433 /* 23819 */ // Label 723: @23819
9434 /* 23819 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(23864), // Rule ID 476 //
9435 /* 23824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9436 /* 23827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
9437 /* 23832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9438 /* 23835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9439 /* 23838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9440 /* 23841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9441 /* 23845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9442 /* 23849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9443 /* 23853 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8004:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9444 /* 23853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
9445 /* 23856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9446 /* 23858 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9447 /* 23860 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9448 /* 23862 */ GIR_RootConstrainSelectedInstOperands,
9449 /* 23863 */ // GIR_Coverage, 476,
9450 /* 23863 */ GIR_EraseRootFromParent_Done,
9451 /* 23864 */ // Label 724: @23864
9452 /* 23864 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(23909), // Rule ID 477 //
9453 /* 23869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9454 /* 23872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
9455 /* 23877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9456 /* 23880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9457 /* 23883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9458 /* 23886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9459 /* 23890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9460 /* 23894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9461 /* 23898 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8626:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9462 /* 23898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
9463 /* 23901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9464 /* 23903 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9465 /* 23905 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9466 /* 23907 */ GIR_RootConstrainSelectedInstOperands,
9467 /* 23908 */ // GIR_Coverage, 477,
9468 /* 23908 */ GIR_EraseRootFromParent_Done,
9469 /* 23909 */ // Label 725: @23909
9470 /* 23909 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(23954), // Rule ID 478 //
9471 /* 23914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9472 /* 23917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
9473 /* 23922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9474 /* 23925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9475 /* 23928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9476 /* 23931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9477 /* 23935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9478 /* 23939 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9479 /* 23943 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8627:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9480 /* 23943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
9481 /* 23946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9482 /* 23948 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9483 /* 23950 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9484 /* 23952 */ GIR_RootConstrainSelectedInstOperands,
9485 /* 23953 */ // GIR_Coverage, 478,
9486 /* 23953 */ GIR_EraseRootFromParent_Done,
9487 /* 23954 */ // Label 726: @23954
9488 /* 23954 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(23999), // Rule ID 479 //
9489 /* 23959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9490 /* 23962 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
9491 /* 23967 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9492 /* 23970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9493 /* 23973 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9494 /* 23976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9495 /* 23980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9496 /* 23984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9497 /* 23988 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7982:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9498 /* 23988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
9499 /* 23991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9500 /* 23993 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9501 /* 23995 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9502 /* 23997 */ GIR_RootConstrainSelectedInstOperands,
9503 /* 23998 */ // GIR_Coverage, 479,
9504 /* 23998 */ GIR_EraseRootFromParent_Done,
9505 /* 23999 */ // Label 727: @23999
9506 /* 23999 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(24044), // Rule ID 480 //
9507 /* 24004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9508 /* 24007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
9509 /* 24012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9510 /* 24015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9511 /* 24018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9512 /* 24021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9513 /* 24025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9514 /* 24029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9515 /* 24033 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7983:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9516 /* 24033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
9517 /* 24036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9518 /* 24038 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9519 /* 24040 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9520 /* 24042 */ GIR_RootConstrainSelectedInstOperands,
9521 /* 24043 */ // GIR_Coverage, 480,
9522 /* 24043 */ GIR_EraseRootFromParent_Done,
9523 /* 24044 */ // Label 728: @24044
9524 /* 24044 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(24089), // Rule ID 481 //
9525 /* 24049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9526 /* 24052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
9527 /* 24057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9528 /* 24060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9529 /* 24063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9530 /* 24066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9531 /* 24070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9532 /* 24074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9533 /* 24078 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8602:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9534 /* 24078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
9535 /* 24081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9536 /* 24083 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9537 /* 24085 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9538 /* 24087 */ GIR_RootConstrainSelectedInstOperands,
9539 /* 24088 */ // GIR_Coverage, 481,
9540 /* 24088 */ GIR_EraseRootFromParent_Done,
9541 /* 24089 */ // Label 729: @24089
9542 /* 24089 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(24134), // Rule ID 482 //
9543 /* 24094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9544 /* 24097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
9545 /* 24102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9546 /* 24105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9547 /* 24108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9548 /* 24111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9549 /* 24115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9550 /* 24119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9551 /* 24123 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8603:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9552 /* 24123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
9553 /* 24126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9554 /* 24128 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9555 /* 24130 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9556 /* 24132 */ GIR_RootConstrainSelectedInstOperands,
9557 /* 24133 */ // GIR_Coverage, 482,
9558 /* 24133 */ GIR_EraseRootFromParent_Done,
9559 /* 24134 */ // Label 730: @24134
9560 /* 24134 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(24179), // Rule ID 483 //
9561 /* 24139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9562 /* 24142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
9563 /* 24147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9564 /* 24150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9565 /* 24153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9566 /* 24156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9567 /* 24160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9568 /* 24164 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9569 /* 24168 */ // (intrinsic_wo_chain:{ *:[i32] } 7985:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9570 /* 24168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
9571 /* 24171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9572 /* 24173 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9573 /* 24175 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9574 /* 24177 */ GIR_RootConstrainSelectedInstOperands,
9575 /* 24178 */ // GIR_Coverage, 483,
9576 /* 24178 */ GIR_EraseRootFromParent_Done,
9577 /* 24179 */ // Label 731: @24179
9578 /* 24179 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(24224), // Rule ID 484 //
9579 /* 24184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9580 /* 24187 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
9581 /* 24192 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9582 /* 24195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9583 /* 24198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9584 /* 24201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9585 /* 24205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9586 /* 24209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9587 /* 24213 */ // (intrinsic_wo_chain:{ *:[i32] } 7984:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9588 /* 24213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
9589 /* 24216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9590 /* 24218 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9591 /* 24220 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9592 /* 24222 */ GIR_RootConstrainSelectedInstOperands,
9593 /* 24223 */ // GIR_Coverage, 484,
9594 /* 24223 */ GIR_EraseRootFromParent_Done,
9595 /* 24224 */ // Label 732: @24224
9596 /* 24224 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(24269), // Rule ID 485 //
9597 /* 24229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9598 /* 24232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
9599 /* 24237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9600 /* 24240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9601 /* 24243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9602 /* 24246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9603 /* 24250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9604 /* 24254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9605 /* 24258 */ // (intrinsic_wo_chain:{ *:[i32] } 8605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9606 /* 24258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
9607 /* 24261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9608 /* 24263 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9609 /* 24265 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9610 /* 24267 */ GIR_RootConstrainSelectedInstOperands,
9611 /* 24268 */ // GIR_Coverage, 485,
9612 /* 24268 */ GIR_EraseRootFromParent_Done,
9613 /* 24269 */ // Label 733: @24269
9614 /* 24269 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(24314), // Rule ID 486 //
9615 /* 24274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9616 /* 24277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
9617 /* 24282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9618 /* 24285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9619 /* 24288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9620 /* 24291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9621 /* 24295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9622 /* 24299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9623 /* 24303 */ // (intrinsic_wo_chain:{ *:[i32] } 8604:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9624 /* 24303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
9625 /* 24306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9626 /* 24308 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9627 /* 24310 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9628 /* 24312 */ GIR_RootConstrainSelectedInstOperands,
9629 /* 24313 */ // GIR_Coverage, 486,
9630 /* 24313 */ GIR_EraseRootFromParent_Done,
9631 /* 24314 */ // Label 734: @24314
9632 /* 24314 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(24359), // Rule ID 503 //
9633 /* 24319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9634 /* 24322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
9635 /* 24327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9636 /* 24330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9637 /* 24333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9638 /* 24336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9639 /* 24340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9640 /* 24344 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9641 /* 24348 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8531:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9642 /* 24348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
9643 /* 24351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9644 /* 24353 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9645 /* 24355 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9646 /* 24357 */ GIR_RootConstrainSelectedInstOperands,
9647 /* 24358 */ // GIR_Coverage, 503,
9648 /* 24358 */ GIR_EraseRootFromParent_Done,
9649 /* 24359 */ // Label 735: @24359
9650 /* 24359 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(24404), // Rule ID 505 //
9651 /* 24364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9652 /* 24367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9653 /* 24372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9654 /* 24375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9655 /* 24378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9656 /* 24381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9657 /* 24385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9658 /* 24389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9659 /* 24393 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8533:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9660 /* 24393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
9661 /* 24396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9662 /* 24398 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9663 /* 24400 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9664 /* 24402 */ GIR_RootConstrainSelectedInstOperands,
9665 /* 24403 */ // GIR_Coverage, 505,
9666 /* 24403 */ GIR_EraseRootFromParent_Done,
9667 /* 24404 */ // Label 736: @24404
9668 /* 24404 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(24449), // Rule ID 506 //
9669 /* 24409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9670 /* 24412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9671 /* 24417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9672 /* 24420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9673 /* 24423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9674 /* 24426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9675 /* 24430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9676 /* 24434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9677 /* 24438 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8535:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9678 /* 24438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
9679 /* 24441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9680 /* 24443 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9681 /* 24445 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9682 /* 24447 */ GIR_RootConstrainSelectedInstOperands,
9683 /* 24448 */ // GIR_Coverage, 506,
9684 /* 24448 */ GIR_EraseRootFromParent_Done,
9685 /* 24449 */ // Label 737: @24449
9686 /* 24449 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(24494), // Rule ID 515 //
9687 /* 24454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9688 /* 24457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
9689 /* 24462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9690 /* 24465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9691 /* 24468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9692 /* 24471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9693 /* 24475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9694 /* 24479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9695 /* 24483 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7975:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9696 /* 24483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
9697 /* 24486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9698 /* 24488 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9699 /* 24490 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9700 /* 24492 */ GIR_RootConstrainSelectedInstOperands,
9701 /* 24493 */ // GIR_Coverage, 515,
9702 /* 24493 */ GIR_EraseRootFromParent_Done,
9703 /* 24494 */ // Label 738: @24494
9704 /* 24494 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(24539), // Rule ID 516 //
9705 /* 24499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9706 /* 24502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
9707 /* 24507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9708 /* 24510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9709 /* 24513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9710 /* 24516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9711 /* 24520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9712 /* 24524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9713 /* 24528 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7977:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9714 /* 24528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
9715 /* 24531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9716 /* 24533 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9717 /* 24535 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9718 /* 24537 */ GIR_RootConstrainSelectedInstOperands,
9719 /* 24538 */ // GIR_Coverage, 516,
9720 /* 24538 */ GIR_EraseRootFromParent_Done,
9721 /* 24539 */ // Label 739: @24539
9722 /* 24539 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(24584), // Rule ID 517 //
9723 /* 24544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9724 /* 24547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
9725 /* 24552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9726 /* 24555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9727 /* 24558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9728 /* 24561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9729 /* 24565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9730 /* 24569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9731 /* 24573 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7978:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9732 /* 24573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
9733 /* 24576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9734 /* 24578 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9735 /* 24580 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9736 /* 24582 */ GIR_RootConstrainSelectedInstOperands,
9737 /* 24583 */ // GIR_Coverage, 517,
9738 /* 24583 */ GIR_EraseRootFromParent_Done,
9739 /* 24584 */ // Label 740: @24584
9740 /* 24584 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(24629), // Rule ID 518 //
9741 /* 24589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9742 /* 24592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
9743 /* 24597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9744 /* 24600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9745 /* 24603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9746 /* 24606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9747 /* 24610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9748 /* 24614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9749 /* 24618 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7976:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9750 /* 24618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
9751 /* 24621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9752 /* 24623 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9753 /* 24625 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9754 /* 24627 */ GIR_RootConstrainSelectedInstOperands,
9755 /* 24628 */ // GIR_Coverage, 518,
9756 /* 24628 */ GIR_EraseRootFromParent_Done,
9757 /* 24629 */ // Label 741: @24629
9758 /* 24629 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(24674), // Rule ID 519 //
9759 /* 24634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9760 /* 24637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9761 /* 24642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9762 /* 24645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9763 /* 24648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9764 /* 24651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9765 /* 24655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9766 /* 24659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9767 /* 24663 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7986:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9768 /* 24663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
9769 /* 24666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9770 /* 24668 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9771 /* 24670 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9772 /* 24672 */ GIR_RootConstrainSelectedInstOperands,
9773 /* 24673 */ // GIR_Coverage, 519,
9774 /* 24673 */ GIR_EraseRootFromParent_Done,
9775 /* 24674 */ // Label 742: @24674
9776 /* 24674 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(24719), // Rule ID 520 //
9777 /* 24679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9778 /* 24682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9779 /* 24687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9780 /* 24690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9781 /* 24693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9782 /* 24696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9783 /* 24700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9784 /* 24704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9785 /* 24708 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7988:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9786 /* 24708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
9787 /* 24711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9788 /* 24713 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9789 /* 24715 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9790 /* 24717 */ GIR_RootConstrainSelectedInstOperands,
9791 /* 24718 */ // GIR_Coverage, 520,
9792 /* 24718 */ GIR_EraseRootFromParent_Done,
9793 /* 24719 */ // Label 743: @24719
9794 /* 24719 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(24764), // Rule ID 521 //
9795 /* 24724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9796 /* 24727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9797 /* 24732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9798 /* 24735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9799 /* 24738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9800 /* 24741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9801 /* 24745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9802 /* 24749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9803 /* 24753 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7989:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9804 /* 24753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
9805 /* 24756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9806 /* 24758 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9807 /* 24760 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9808 /* 24762 */ GIR_RootConstrainSelectedInstOperands,
9809 /* 24763 */ // GIR_Coverage, 521,
9810 /* 24763 */ GIR_EraseRootFromParent_Done,
9811 /* 24764 */ // Label 744: @24764
9812 /* 24764 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(24809), // Rule ID 522 //
9813 /* 24769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9814 /* 24772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9815 /* 24777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9816 /* 24780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9817 /* 24783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9818 /* 24786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9819 /* 24790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9820 /* 24794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9821 /* 24798 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7987:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9822 /* 24798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
9823 /* 24801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9824 /* 24803 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9825 /* 24805 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9826 /* 24807 */ GIR_RootConstrainSelectedInstOperands,
9827 /* 24808 */ // GIR_Coverage, 522,
9828 /* 24808 */ GIR_EraseRootFromParent_Done,
9829 /* 24809 */ // Label 745: @24809
9830 /* 24809 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(24854), // Rule ID 523 //
9831 /* 24814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9832 /* 24817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9833 /* 24822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9834 /* 24825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9835 /* 24828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9836 /* 24831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9837 /* 24835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9838 /* 24839 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9839 /* 24843 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7990:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9840 /* 24843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
9841 /* 24846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9842 /* 24848 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9843 /* 24850 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9844 /* 24852 */ GIR_RootConstrainSelectedInstOperands,
9845 /* 24853 */ // GIR_Coverage, 523,
9846 /* 24853 */ GIR_EraseRootFromParent_Done,
9847 /* 24854 */ // Label 746: @24854
9848 /* 24854 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(24899), // Rule ID 524 //
9849 /* 24859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9850 /* 24862 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9851 /* 24867 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9852 /* 24870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9853 /* 24873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9854 /* 24876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9855 /* 24880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9856 /* 24884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9857 /* 24888 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7992:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9858 /* 24888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
9859 /* 24891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9860 /* 24893 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9861 /* 24895 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9862 /* 24897 */ GIR_RootConstrainSelectedInstOperands,
9863 /* 24898 */ // GIR_Coverage, 524,
9864 /* 24898 */ GIR_EraseRootFromParent_Done,
9865 /* 24899 */ // Label 747: @24899
9866 /* 24899 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(24944), // Rule ID 525 //
9867 /* 24904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9868 /* 24907 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9869 /* 24912 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9870 /* 24915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9871 /* 24918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9872 /* 24921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9873 /* 24925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9874 /* 24929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9875 /* 24933 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7993:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9876 /* 24933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
9877 /* 24936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9878 /* 24938 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9879 /* 24940 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9880 /* 24942 */ GIR_RootConstrainSelectedInstOperands,
9881 /* 24943 */ // GIR_Coverage, 525,
9882 /* 24943 */ GIR_EraseRootFromParent_Done,
9883 /* 24944 */ // Label 748: @24944
9884 /* 24944 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(24989), // Rule ID 526 //
9885 /* 24949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9886 /* 24952 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9887 /* 24957 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9888 /* 24960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9889 /* 24963 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9890 /* 24966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9891 /* 24970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9892 /* 24974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9893 /* 24978 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7991:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9894 /* 24978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
9895 /* 24981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9896 /* 24983 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9897 /* 24985 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9898 /* 24987 */ GIR_RootConstrainSelectedInstOperands,
9899 /* 24988 */ // GIR_Coverage, 526,
9900 /* 24988 */ GIR_EraseRootFromParent_Done,
9901 /* 24989 */ // Label 749: @24989
9902 /* 24989 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(25034), // Rule ID 527 //
9903 /* 24994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9904 /* 24997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9905 /* 25002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9906 /* 25005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9907 /* 25008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9908 /* 25011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9909 /* 25015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9910 /* 25019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9911 /* 25023 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7994:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9912 /* 25023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
9913 /* 25026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9914 /* 25028 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9915 /* 25030 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9916 /* 25032 */ GIR_RootConstrainSelectedInstOperands,
9917 /* 25033 */ // GIR_Coverage, 527,
9918 /* 25033 */ GIR_EraseRootFromParent_Done,
9919 /* 25034 */ // Label 750: @25034
9920 /* 25034 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(25079), // Rule ID 528 //
9921 /* 25039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9922 /* 25042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9923 /* 25047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9924 /* 25050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9925 /* 25053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9926 /* 25056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9927 /* 25060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9928 /* 25064 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9929 /* 25068 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7996:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9930 /* 25068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
9931 /* 25071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9932 /* 25073 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9933 /* 25075 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9934 /* 25077 */ GIR_RootConstrainSelectedInstOperands,
9935 /* 25078 */ // GIR_Coverage, 528,
9936 /* 25078 */ GIR_EraseRootFromParent_Done,
9937 /* 25079 */ // Label 751: @25079
9938 /* 25079 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(25124), // Rule ID 529 //
9939 /* 25084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9940 /* 25087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9941 /* 25092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9942 /* 25095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9943 /* 25098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9944 /* 25101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9945 /* 25105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9946 /* 25109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9947 /* 25113 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7997:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9948 /* 25113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
9949 /* 25116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9950 /* 25118 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9951 /* 25120 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9952 /* 25122 */ GIR_RootConstrainSelectedInstOperands,
9953 /* 25123 */ // GIR_Coverage, 529,
9954 /* 25123 */ GIR_EraseRootFromParent_Done,
9955 /* 25124 */ // Label 752: @25124
9956 /* 25124 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(25169), // Rule ID 530 //
9957 /* 25129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9958 /* 25132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9959 /* 25137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9960 /* 25140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9961 /* 25143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9962 /* 25146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9963 /* 25150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9964 /* 25154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9965 /* 25158 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7995:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9966 /* 25158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
9967 /* 25161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9968 /* 25163 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9969 /* 25165 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9970 /* 25167 */ GIR_RootConstrainSelectedInstOperands,
9971 /* 25168 */ // GIR_Coverage, 530,
9972 /* 25168 */ GIR_EraseRootFromParent_Done,
9973 /* 25169 */ // Label 753: @25169
9974 /* 25169 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(25214), // Rule ID 544 //
9975 /* 25174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9976 /* 25177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9977 /* 25182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9978 /* 25185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9979 /* 25188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9980 /* 25191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9981 /* 25195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9982 /* 25199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9983 /* 25203 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8017:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9984 /* 25203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
9985 /* 25206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9986 /* 25208 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9987 /* 25210 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9988 /* 25212 */ GIR_RootConstrainSelectedInstOperands,
9989 /* 25213 */ // GIR_Coverage, 544,
9990 /* 25213 */ GIR_EraseRootFromParent_Done,
9991 /* 25214 */ // Label 754: @25214
9992 /* 25214 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(25259), // Rule ID 545 //
9993 /* 25219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9994 /* 25222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9995 /* 25227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9996 /* 25230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9997 /* 25233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9998 /* 25236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9999 /* 25240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10000 /* 25244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10001 /* 25248 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8019:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10002 /* 25248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
10003 /* 25251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10004 /* 25253 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10005 /* 25255 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10006 /* 25257 */ GIR_RootConstrainSelectedInstOperands,
10007 /* 25258 */ // GIR_Coverage, 545,
10008 /* 25258 */ GIR_EraseRootFromParent_Done,
10009 /* 25259 */ // Label 755: @25259
10010 /* 25259 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(25304), // Rule ID 546 //
10011 /* 25264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10012 /* 25267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
10013 /* 25272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10014 /* 25275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10015 /* 25278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10016 /* 25281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10017 /* 25285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10018 /* 25289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10019 /* 25293 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8020:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10020 /* 25293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
10021 /* 25296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10022 /* 25298 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10023 /* 25300 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10024 /* 25302 */ GIR_RootConstrainSelectedInstOperands,
10025 /* 25303 */ // GIR_Coverage, 546,
10026 /* 25303 */ GIR_EraseRootFromParent_Done,
10027 /* 25304 */ // Label 756: @25304
10028 /* 25304 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(25349), // Rule ID 547 //
10029 /* 25309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10030 /* 25312 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
10031 /* 25317 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10032 /* 25320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10033 /* 25323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10034 /* 25326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10035 /* 25330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10036 /* 25334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10037 /* 25338 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8018:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10038 /* 25338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
10039 /* 25341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10040 /* 25343 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10041 /* 25345 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10042 /* 25347 */ GIR_RootConstrainSelectedInstOperands,
10043 /* 25348 */ // GIR_Coverage, 547,
10044 /* 25348 */ GIR_EraseRootFromParent_Done,
10045 /* 25349 */ // Label 757: @25349
10046 /* 25349 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(25394), // Rule ID 548 //
10047 /* 25354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10048 /* 25357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
10049 /* 25362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10050 /* 25365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10051 /* 25368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10052 /* 25371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10053 /* 25375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10054 /* 25379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10055 /* 25383 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8021:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10056 /* 25383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
10057 /* 25386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10058 /* 25388 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10059 /* 25390 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10060 /* 25392 */ GIR_RootConstrainSelectedInstOperands,
10061 /* 25393 */ // GIR_Coverage, 548,
10062 /* 25393 */ GIR_EraseRootFromParent_Done,
10063 /* 25394 */ // Label 758: @25394
10064 /* 25394 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(25439), // Rule ID 549 //
10065 /* 25399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10066 /* 25402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
10067 /* 25407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10068 /* 25410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10069 /* 25413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10070 /* 25416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10071 /* 25420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10072 /* 25424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10073 /* 25428 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8023:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10074 /* 25428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
10075 /* 25431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10076 /* 25433 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10077 /* 25435 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10078 /* 25437 */ GIR_RootConstrainSelectedInstOperands,
10079 /* 25438 */ // GIR_Coverage, 549,
10080 /* 25438 */ GIR_EraseRootFromParent_Done,
10081 /* 25439 */ // Label 759: @25439
10082 /* 25439 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(25484), // Rule ID 550 //
10083 /* 25444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10084 /* 25447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
10085 /* 25452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10086 /* 25455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10087 /* 25458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10088 /* 25461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10089 /* 25465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10090 /* 25469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10091 /* 25473 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8024:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10092 /* 25473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
10093 /* 25476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10094 /* 25478 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10095 /* 25480 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10096 /* 25482 */ GIR_RootConstrainSelectedInstOperands,
10097 /* 25483 */ // GIR_Coverage, 550,
10098 /* 25483 */ GIR_EraseRootFromParent_Done,
10099 /* 25484 */ // Label 760: @25484
10100 /* 25484 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(25529), // Rule ID 551 //
10101 /* 25489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10102 /* 25492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
10103 /* 25497 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10104 /* 25500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10105 /* 25503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10106 /* 25506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10107 /* 25510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10108 /* 25514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10109 /* 25518 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8022:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10110 /* 25518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
10111 /* 25521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10112 /* 25523 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10113 /* 25525 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10114 /* 25527 */ GIR_RootConstrainSelectedInstOperands,
10115 /* 25528 */ // GIR_Coverage, 551,
10116 /* 25528 */ GIR_EraseRootFromParent_Done,
10117 /* 25529 */ // Label 761: @25529
10118 /* 25529 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(25574), // Rule ID 552 //
10119 /* 25534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10120 /* 25537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
10121 /* 25542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10122 /* 25545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10123 /* 25548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10124 /* 25551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10125 /* 25555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10126 /* 25559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10127 /* 25563 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8025:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10128 /* 25563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
10129 /* 25566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10130 /* 25568 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10131 /* 25570 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10132 /* 25572 */ GIR_RootConstrainSelectedInstOperands,
10133 /* 25573 */ // GIR_Coverage, 552,
10134 /* 25573 */ GIR_EraseRootFromParent_Done,
10135 /* 25574 */ // Label 762: @25574
10136 /* 25574 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(25619), // Rule ID 553 //
10137 /* 25579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10138 /* 25582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
10139 /* 25587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10140 /* 25590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10141 /* 25593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10142 /* 25596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10143 /* 25600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10144 /* 25604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10145 /* 25608 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8027:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10146 /* 25608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
10147 /* 25611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10148 /* 25613 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10149 /* 25615 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10150 /* 25617 */ GIR_RootConstrainSelectedInstOperands,
10151 /* 25618 */ // GIR_Coverage, 553,
10152 /* 25618 */ GIR_EraseRootFromParent_Done,
10153 /* 25619 */ // Label 763: @25619
10154 /* 25619 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(25664), // Rule ID 554 //
10155 /* 25624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10156 /* 25627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
10157 /* 25632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10158 /* 25635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10159 /* 25638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10160 /* 25641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10161 /* 25645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10162 /* 25649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10163 /* 25653 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8028:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10164 /* 25653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
10165 /* 25656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10166 /* 25658 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10167 /* 25660 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10168 /* 25662 */ GIR_RootConstrainSelectedInstOperands,
10169 /* 25663 */ // GIR_Coverage, 554,
10170 /* 25663 */ GIR_EraseRootFromParent_Done,
10171 /* 25664 */ // Label 764: @25664
10172 /* 25664 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(25709), // Rule ID 555 //
10173 /* 25669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10174 /* 25672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
10175 /* 25677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10176 /* 25680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10177 /* 25683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10178 /* 25686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10179 /* 25690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10180 /* 25694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10181 /* 25698 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8026:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10182 /* 25698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
10183 /* 25701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10184 /* 25703 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10185 /* 25705 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10186 /* 25707 */ GIR_RootConstrainSelectedInstOperands,
10187 /* 25708 */ // GIR_Coverage, 555,
10188 /* 25708 */ GIR_EraseRootFromParent_Done,
10189 /* 25709 */ // Label 765: @25709
10190 /* 25709 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(25754), // Rule ID 556 //
10191 /* 25714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10192 /* 25717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
10193 /* 25722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10194 /* 25725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10195 /* 25728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10196 /* 25731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10197 /* 25735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10198 /* 25739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10199 /* 25743 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8029:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10200 /* 25743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
10201 /* 25746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10202 /* 25748 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10203 /* 25750 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10204 /* 25752 */ GIR_RootConstrainSelectedInstOperands,
10205 /* 25753 */ // GIR_Coverage, 556,
10206 /* 25753 */ GIR_EraseRootFromParent_Done,
10207 /* 25754 */ // Label 766: @25754
10208 /* 25754 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(25799), // Rule ID 557 //
10209 /* 25759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10210 /* 25762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
10211 /* 25767 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10212 /* 25770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10213 /* 25773 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10214 /* 25776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10215 /* 25780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10216 /* 25784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10217 /* 25788 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8031:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10218 /* 25788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
10219 /* 25791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10220 /* 25793 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10221 /* 25795 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10222 /* 25797 */ GIR_RootConstrainSelectedInstOperands,
10223 /* 25798 */ // GIR_Coverage, 557,
10224 /* 25798 */ GIR_EraseRootFromParent_Done,
10225 /* 25799 */ // Label 767: @25799
10226 /* 25799 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(25844), // Rule ID 558 //
10227 /* 25804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10228 /* 25807 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
10229 /* 25812 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10230 /* 25815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10231 /* 25818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10232 /* 25821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10233 /* 25825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10234 /* 25829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10235 /* 25833 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8032:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10236 /* 25833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
10237 /* 25836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10238 /* 25838 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10239 /* 25840 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10240 /* 25842 */ GIR_RootConstrainSelectedInstOperands,
10241 /* 25843 */ // GIR_Coverage, 558,
10242 /* 25843 */ GIR_EraseRootFromParent_Done,
10243 /* 25844 */ // Label 768: @25844
10244 /* 25844 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(25889), // Rule ID 559 //
10245 /* 25849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10246 /* 25852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
10247 /* 25857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10248 /* 25860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10249 /* 25863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10250 /* 25866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10251 /* 25870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10252 /* 25874 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10253 /* 25878 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8030:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10254 /* 25878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
10255 /* 25881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10256 /* 25883 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10257 /* 25885 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10258 /* 25887 */ GIR_RootConstrainSelectedInstOperands,
10259 /* 25888 */ // GIR_Coverage, 559,
10260 /* 25888 */ GIR_EraseRootFromParent_Done,
10261 /* 25889 */ // Label 769: @25889
10262 /* 25889 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(25934), // Rule ID 560 //
10263 /* 25894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10264 /* 25897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
10265 /* 25902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10266 /* 25905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10267 /* 25908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10268 /* 25911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10269 /* 25915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10270 /* 25919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10271 /* 25923 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8033:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10272 /* 25923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
10273 /* 25926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10274 /* 25928 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10275 /* 25930 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10276 /* 25932 */ GIR_RootConstrainSelectedInstOperands,
10277 /* 25933 */ // GIR_Coverage, 560,
10278 /* 25933 */ GIR_EraseRootFromParent_Done,
10279 /* 25934 */ // Label 770: @25934
10280 /* 25934 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(25979), // Rule ID 561 //
10281 /* 25939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10282 /* 25942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
10283 /* 25947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10284 /* 25950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10285 /* 25953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10286 /* 25956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10287 /* 25960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10288 /* 25964 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10289 /* 25968 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8035:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10290 /* 25968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
10291 /* 25971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10292 /* 25973 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10293 /* 25975 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10294 /* 25977 */ GIR_RootConstrainSelectedInstOperands,
10295 /* 25978 */ // GIR_Coverage, 561,
10296 /* 25978 */ GIR_EraseRootFromParent_Done,
10297 /* 25979 */ // Label 771: @25979
10298 /* 25979 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(26024), // Rule ID 562 //
10299 /* 25984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10300 /* 25987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
10301 /* 25992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10302 /* 25995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10303 /* 25998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10304 /* 26001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10305 /* 26005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10306 /* 26009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10307 /* 26013 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8036:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10308 /* 26013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
10309 /* 26016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10310 /* 26018 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10311 /* 26020 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10312 /* 26022 */ GIR_RootConstrainSelectedInstOperands,
10313 /* 26023 */ // GIR_Coverage, 562,
10314 /* 26023 */ GIR_EraseRootFromParent_Done,
10315 /* 26024 */ // Label 772: @26024
10316 /* 26024 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(26069), // Rule ID 563 //
10317 /* 26029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10318 /* 26032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
10319 /* 26037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10320 /* 26040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10321 /* 26043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10322 /* 26046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10323 /* 26050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10324 /* 26054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10325 /* 26058 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8034:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10326 /* 26058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
10327 /* 26061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10328 /* 26063 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10329 /* 26065 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10330 /* 26067 */ GIR_RootConstrainSelectedInstOperands,
10331 /* 26068 */ // GIR_Coverage, 563,
10332 /* 26068 */ GIR_EraseRootFromParent_Done,
10333 /* 26069 */ // Label 773: @26069
10334 /* 26069 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(26114), // Rule ID 564 //
10335 /* 26074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10336 /* 26077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
10337 /* 26082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10338 /* 26085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10339 /* 26088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10340 /* 26091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10341 /* 26095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10342 /* 26099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10343 /* 26103 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8037:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10344 /* 26103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
10345 /* 26106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10346 /* 26108 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10347 /* 26110 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10348 /* 26112 */ GIR_RootConstrainSelectedInstOperands,
10349 /* 26113 */ // GIR_Coverage, 564,
10350 /* 26113 */ GIR_EraseRootFromParent_Done,
10351 /* 26114 */ // Label 774: @26114
10352 /* 26114 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(26159), // Rule ID 565 //
10353 /* 26119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10354 /* 26122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
10355 /* 26127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10356 /* 26130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10357 /* 26133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10358 /* 26136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10359 /* 26140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10360 /* 26144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10361 /* 26148 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8039:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10362 /* 26148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
10363 /* 26151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10364 /* 26153 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10365 /* 26155 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10366 /* 26157 */ GIR_RootConstrainSelectedInstOperands,
10367 /* 26158 */ // GIR_Coverage, 565,
10368 /* 26158 */ GIR_EraseRootFromParent_Done,
10369 /* 26159 */ // Label 775: @26159
10370 /* 26159 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(26204), // Rule ID 566 //
10371 /* 26164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10372 /* 26167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
10373 /* 26172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10374 /* 26175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10375 /* 26178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10376 /* 26181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10377 /* 26185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10378 /* 26189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10379 /* 26193 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8040:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10380 /* 26193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
10381 /* 26196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10382 /* 26198 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10383 /* 26200 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10384 /* 26202 */ GIR_RootConstrainSelectedInstOperands,
10385 /* 26203 */ // GIR_Coverage, 566,
10386 /* 26203 */ GIR_EraseRootFromParent_Done,
10387 /* 26204 */ // Label 776: @26204
10388 /* 26204 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(26249), // Rule ID 567 //
10389 /* 26209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10390 /* 26212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
10391 /* 26217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10392 /* 26220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10393 /* 26223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10394 /* 26226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10395 /* 26230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10396 /* 26234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10397 /* 26238 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8038:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10398 /* 26238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
10399 /* 26241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10400 /* 26243 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10401 /* 26245 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10402 /* 26247 */ GIR_RootConstrainSelectedInstOperands,
10403 /* 26248 */ // GIR_Coverage, 567,
10404 /* 26248 */ GIR_EraseRootFromParent_Done,
10405 /* 26249 */ // Label 777: @26249
10406 /* 26249 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(26294), // Rule ID 676 //
10407 /* 26254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10408 /* 26257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
10409 /* 26262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10410 /* 26265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10411 /* 26268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10412 /* 26271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10413 /* 26275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10414 /* 26279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10415 /* 26283 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8172:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10416 /* 26283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
10417 /* 26286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10418 /* 26288 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10419 /* 26290 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10420 /* 26292 */ GIR_RootConstrainSelectedInstOperands,
10421 /* 26293 */ // GIR_Coverage, 676,
10422 /* 26293 */ GIR_EraseRootFromParent_Done,
10423 /* 26294 */ // Label 778: @26294
10424 /* 26294 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(26339), // Rule ID 677 //
10425 /* 26299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10426 /* 26302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
10427 /* 26307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10428 /* 26310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10429 /* 26313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10430 /* 26316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10431 /* 26320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10432 /* 26324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10433 /* 26328 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8173:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10434 /* 26328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
10435 /* 26331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10436 /* 26333 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10437 /* 26335 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10438 /* 26337 */ GIR_RootConstrainSelectedInstOperands,
10439 /* 26338 */ // GIR_Coverage, 677,
10440 /* 26338 */ GIR_EraseRootFromParent_Done,
10441 /* 26339 */ // Label 779: @26339
10442 /* 26339 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(26384), // Rule ID 678 //
10443 /* 26344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10444 /* 26347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
10445 /* 26352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10446 /* 26355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10447 /* 26358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10448 /* 26361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10449 /* 26365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10450 /* 26369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10451 /* 26373 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8171:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10452 /* 26373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
10453 /* 26376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10454 /* 26378 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10455 /* 26380 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10456 /* 26382 */ GIR_RootConstrainSelectedInstOperands,
10457 /* 26383 */ // GIR_Coverage, 678,
10458 /* 26383 */ GIR_EraseRootFromParent_Done,
10459 /* 26384 */ // Label 780: @26384
10460 /* 26384 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(26429), // Rule ID 679 //
10461 /* 26389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10462 /* 26392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
10463 /* 26397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10464 /* 26400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10465 /* 26403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10466 /* 26406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10467 /* 26410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10468 /* 26414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10469 /* 26418 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8175:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10470 /* 26418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
10471 /* 26421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10472 /* 26423 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10473 /* 26425 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10474 /* 26427 */ GIR_RootConstrainSelectedInstOperands,
10475 /* 26428 */ // GIR_Coverage, 679,
10476 /* 26428 */ GIR_EraseRootFromParent_Done,
10477 /* 26429 */ // Label 781: @26429
10478 /* 26429 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(26474), // Rule ID 680 //
10479 /* 26434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10480 /* 26437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
10481 /* 26442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10482 /* 26445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10483 /* 26448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10484 /* 26451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10485 /* 26455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10486 /* 26459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10487 /* 26463 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8176:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10488 /* 26463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
10489 /* 26466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10490 /* 26468 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10491 /* 26470 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10492 /* 26472 */ GIR_RootConstrainSelectedInstOperands,
10493 /* 26473 */ // GIR_Coverage, 680,
10494 /* 26473 */ GIR_EraseRootFromParent_Done,
10495 /* 26474 */ // Label 782: @26474
10496 /* 26474 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(26519), // Rule ID 681 //
10497 /* 26479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10498 /* 26482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
10499 /* 26487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10500 /* 26490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10501 /* 26493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10502 /* 26496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10503 /* 26500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10504 /* 26504 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10505 /* 26508 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8174:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10506 /* 26508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
10507 /* 26511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10508 /* 26513 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10509 /* 26515 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10510 /* 26517 */ GIR_RootConstrainSelectedInstOperands,
10511 /* 26518 */ // GIR_Coverage, 681,
10512 /* 26518 */ GIR_EraseRootFromParent_Done,
10513 /* 26519 */ // Label 783: @26519
10514 /* 26519 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(26564), // Rule ID 696 //
10515 /* 26524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10516 /* 26527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
10517 /* 26532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10518 /* 26535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10519 /* 26538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10520 /* 26541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10521 /* 26545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10522 /* 26549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10523 /* 26553 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8214:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10524 /* 26553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
10525 /* 26556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10526 /* 26558 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10527 /* 26560 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10528 /* 26562 */ GIR_RootConstrainSelectedInstOperands,
10529 /* 26563 */ // GIR_Coverage, 696,
10530 /* 26563 */ GIR_EraseRootFromParent_Done,
10531 /* 26564 */ // Label 784: @26564
10532 /* 26564 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(26609), // Rule ID 697 //
10533 /* 26569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10534 /* 26572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
10535 /* 26577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10536 /* 26580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10537 /* 26583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10538 /* 26586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10539 /* 26590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10540 /* 26594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10541 /* 26598 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8213:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10542 /* 26598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
10543 /* 26601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10544 /* 26603 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10545 /* 26605 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10546 /* 26607 */ GIR_RootConstrainSelectedInstOperands,
10547 /* 26608 */ // GIR_Coverage, 697,
10548 /* 26608 */ GIR_EraseRootFromParent_Done,
10549 /* 26609 */ // Label 785: @26609
10550 /* 26609 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(26654), // Rule ID 722 //
10551 /* 26614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10552 /* 26617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
10553 /* 26622 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10554 /* 26625 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10555 /* 26628 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10556 /* 26631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10557 /* 26635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10558 /* 26639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10559 /* 26643 */ // (intrinsic_wo_chain:{ *:[v8f16] } 8239:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10560 /* 26643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
10561 /* 26646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10562 /* 26648 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10563 /* 26650 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10564 /* 26652 */ GIR_RootConstrainSelectedInstOperands,
10565 /* 26653 */ // GIR_Coverage, 722,
10566 /* 26653 */ GIR_EraseRootFromParent_Done,
10567 /* 26654 */ // Label 786: @26654
10568 /* 26654 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(26699), // Rule ID 723 //
10569 /* 26659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10570 /* 26662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
10571 /* 26667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10572 /* 26670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10573 /* 26673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10574 /* 26676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10575 /* 26680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10576 /* 26684 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10577 /* 26688 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8240:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10578 /* 26688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
10579 /* 26691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10580 /* 26693 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10581 /* 26695 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10582 /* 26697 */ GIR_RootConstrainSelectedInstOperands,
10583 /* 26698 */ // GIR_Coverage, 723,
10584 /* 26698 */ GIR_EraseRootFromParent_Done,
10585 /* 26699 */ // Label 787: @26699
10586 /* 26699 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(26744), // Rule ID 750 //
10587 /* 26704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10588 /* 26707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
10589 /* 26712 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10590 /* 26715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10591 /* 26718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10592 /* 26721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10593 /* 26725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10594 /* 26729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10595 /* 26733 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10596 /* 26733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
10597 /* 26736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10598 /* 26738 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10599 /* 26740 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10600 /* 26742 */ GIR_RootConstrainSelectedInstOperands,
10601 /* 26743 */ // GIR_Coverage, 750,
10602 /* 26743 */ GIR_EraseRootFromParent_Done,
10603 /* 26744 */ // Label 788: @26744
10604 /* 26744 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(26789), // Rule ID 751 //
10605 /* 26749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10606 /* 26752 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
10607 /* 26757 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10608 /* 26760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10609 /* 26763 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10610 /* 26766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10611 /* 26770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10612 /* 26774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10613 /* 26778 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10614 /* 26778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
10615 /* 26781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10616 /* 26783 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10617 /* 26785 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10618 /* 26787 */ GIR_RootConstrainSelectedInstOperands,
10619 /* 26788 */ // GIR_Coverage, 751,
10620 /* 26788 */ GIR_EraseRootFromParent_Done,
10621 /* 26789 */ // Label 789: @26789
10622 /* 26789 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(26834), // Rule ID 752 //
10623 /* 26794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10624 /* 26797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
10625 /* 26802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10626 /* 26805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10627 /* 26808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10628 /* 26811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10629 /* 26815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10630 /* 26819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10631 /* 26823 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10632 /* 26823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
10633 /* 26826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10634 /* 26828 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10635 /* 26830 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10636 /* 26832 */ GIR_RootConstrainSelectedInstOperands,
10637 /* 26833 */ // GIR_Coverage, 752,
10638 /* 26833 */ GIR_EraseRootFromParent_Done,
10639 /* 26834 */ // Label 790: @26834
10640 /* 26834 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(26879), // Rule ID 753 //
10641 /* 26839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10642 /* 26842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
10643 /* 26847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10644 /* 26850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10645 /* 26853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10646 /* 26856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10647 /* 26860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10648 /* 26864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10649 /* 26868 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10650 /* 26868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
10651 /* 26871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10652 /* 26873 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10653 /* 26875 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10654 /* 26877 */ GIR_RootConstrainSelectedInstOperands,
10655 /* 26878 */ // GIR_Coverage, 753,
10656 /* 26878 */ GIR_EraseRootFromParent_Done,
10657 /* 26879 */ // Label 791: @26879
10658 /* 26879 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(26924), // Rule ID 754 //
10659 /* 26884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10660 /* 26887 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
10661 /* 26892 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10662 /* 26895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10663 /* 26898 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10664 /* 26901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10665 /* 26905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10666 /* 26909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10667 /* 26913 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8270:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10668 /* 26913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
10669 /* 26916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10670 /* 26918 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10671 /* 26920 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10672 /* 26922 */ GIR_RootConstrainSelectedInstOperands,
10673 /* 26923 */ // GIR_Coverage, 754,
10674 /* 26923 */ GIR_EraseRootFromParent_Done,
10675 /* 26924 */ // Label 792: @26924
10676 /* 26924 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(26969), // Rule ID 755 //
10677 /* 26929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10678 /* 26932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
10679 /* 26937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10680 /* 26940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10681 /* 26943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10682 /* 26946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10683 /* 26950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10684 /* 26954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10685 /* 26958 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8269:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10686 /* 26958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
10687 /* 26961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10688 /* 26963 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10689 /* 26965 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10690 /* 26967 */ GIR_RootConstrainSelectedInstOperands,
10691 /* 26968 */ // GIR_Coverage, 755,
10692 /* 26968 */ GIR_EraseRootFromParent_Done,
10693 /* 26969 */ // Label 793: @26969
10694 /* 26969 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(27014), // Rule ID 756 //
10695 /* 26974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10696 /* 26977 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
10697 /* 26982 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10698 /* 26985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10699 /* 26988 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10700 /* 26991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10701 /* 26995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10702 /* 26999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10703 /* 27003 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10704 /* 27003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
10705 /* 27006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10706 /* 27008 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10707 /* 27010 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10708 /* 27012 */ GIR_RootConstrainSelectedInstOperands,
10709 /* 27013 */ // GIR_Coverage, 756,
10710 /* 27013 */ GIR_EraseRootFromParent_Done,
10711 /* 27014 */ // Label 794: @27014
10712 /* 27014 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(27059), // Rule ID 757 //
10713 /* 27019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10714 /* 27022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
10715 /* 27027 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10716 /* 27030 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10717 /* 27033 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10718 /* 27036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10719 /* 27040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10720 /* 27044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10721 /* 27048 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10722 /* 27048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
10723 /* 27051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10724 /* 27053 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10725 /* 27055 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10726 /* 27057 */ GIR_RootConstrainSelectedInstOperands,
10727 /* 27058 */ // GIR_Coverage, 757,
10728 /* 27058 */ GIR_EraseRootFromParent_Done,
10729 /* 27059 */ // Label 795: @27059
10730 /* 27059 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(27104), // Rule ID 768 //
10731 /* 27064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10732 /* 27067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
10733 /* 27072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10734 /* 27075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10735 /* 27078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10736 /* 27081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10737 /* 27085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10738 /* 27089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10739 /* 27093 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8282:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10740 /* 27093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
10741 /* 27096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10742 /* 27098 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10743 /* 27100 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10744 /* 27102 */ GIR_RootConstrainSelectedInstOperands,
10745 /* 27103 */ // GIR_Coverage, 768,
10746 /* 27103 */ GIR_EraseRootFromParent_Done,
10747 /* 27104 */ // Label 796: @27104
10748 /* 27104 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(27149), // Rule ID 769 //
10749 /* 27109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10750 /* 27112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
10751 /* 27117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10752 /* 27120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10753 /* 27123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10754 /* 27126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10755 /* 27130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10756 /* 27134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10757 /* 27138 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8281:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10758 /* 27138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
10759 /* 27141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10760 /* 27143 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10761 /* 27145 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10762 /* 27147 */ GIR_RootConstrainSelectedInstOperands,
10763 /* 27148 */ // GIR_Coverage, 769,
10764 /* 27148 */ GIR_EraseRootFromParent_Done,
10765 /* 27149 */ // Label 797: @27149
10766 /* 27149 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(27194), // Rule ID 770 //
10767 /* 27154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10768 /* 27157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
10769 /* 27162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10770 /* 27165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10771 /* 27168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10772 /* 27171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10773 /* 27175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10774 /* 27179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10775 /* 27183 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8284:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10776 /* 27183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
10777 /* 27186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10778 /* 27188 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10779 /* 27190 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10780 /* 27192 */ GIR_RootConstrainSelectedInstOperands,
10781 /* 27193 */ // GIR_Coverage, 770,
10782 /* 27193 */ GIR_EraseRootFromParent_Done,
10783 /* 27194 */ // Label 798: @27194
10784 /* 27194 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(27239), // Rule ID 771 //
10785 /* 27199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10786 /* 27202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
10787 /* 27207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10788 /* 27210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10789 /* 27213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10790 /* 27216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10791 /* 27220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10792 /* 27224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10793 /* 27228 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8283:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10794 /* 27228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
10795 /* 27231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10796 /* 27233 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10797 /* 27235 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10798 /* 27237 */ GIR_RootConstrainSelectedInstOperands,
10799 /* 27238 */ // GIR_Coverage, 771,
10800 /* 27238 */ GIR_EraseRootFromParent_Done,
10801 /* 27239 */ // Label 799: @27239
10802 /* 27239 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(27284), // Rule ID 772 //
10803 /* 27244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10804 /* 27247 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
10805 /* 27252 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10806 /* 27255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10807 /* 27258 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10808 /* 27261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10809 /* 27265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10810 /* 27269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10811 /* 27273 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10812 /* 27273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
10813 /* 27276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10814 /* 27278 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10815 /* 27280 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10816 /* 27282 */ GIR_RootConstrainSelectedInstOperands,
10817 /* 27283 */ // GIR_Coverage, 772,
10818 /* 27283 */ GIR_EraseRootFromParent_Done,
10819 /* 27284 */ // Label 800: @27284
10820 /* 27284 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(27329), // Rule ID 773 //
10821 /* 27289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10822 /* 27292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
10823 /* 27297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10824 /* 27300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10825 /* 27303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10826 /* 27306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10827 /* 27310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10828 /* 27314 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10829 /* 27318 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8285:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10830 /* 27318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
10831 /* 27321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10832 /* 27323 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10833 /* 27325 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10834 /* 27327 */ GIR_RootConstrainSelectedInstOperands,
10835 /* 27328 */ // GIR_Coverage, 773,
10836 /* 27328 */ GIR_EraseRootFromParent_Done,
10837 /* 27329 */ // Label 801: @27329
10838 /* 27329 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(27374), // Rule ID 774 //
10839 /* 27334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10840 /* 27337 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
10841 /* 27342 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10842 /* 27345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10843 /* 27348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10844 /* 27351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10845 /* 27355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10846 /* 27359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10847 /* 27363 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10848 /* 27363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
10849 /* 27366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10850 /* 27368 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10851 /* 27370 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10852 /* 27372 */ GIR_RootConstrainSelectedInstOperands,
10853 /* 27373 */ // GIR_Coverage, 774,
10854 /* 27373 */ GIR_EraseRootFromParent_Done,
10855 /* 27374 */ // Label 802: @27374
10856 /* 27374 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(27419), // Rule ID 775 //
10857 /* 27379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10858 /* 27382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
10859 /* 27387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10860 /* 27390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10861 /* 27393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10862 /* 27396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10863 /* 27400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10864 /* 27404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10865 /* 27408 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8287:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10866 /* 27408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
10867 /* 27411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10868 /* 27413 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10869 /* 27415 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10870 /* 27417 */ GIR_RootConstrainSelectedInstOperands,
10871 /* 27418 */ // GIR_Coverage, 775,
10872 /* 27418 */ GIR_EraseRootFromParent_Done,
10873 /* 27419 */ // Label 803: @27419
10874 /* 27419 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(27464), // Rule ID 776 //
10875 /* 27424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10876 /* 27427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
10877 /* 27432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10878 /* 27435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10879 /* 27438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10880 /* 27441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10881 /* 27445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10882 /* 27449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10883 /* 27453 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8290:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10884 /* 27453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
10885 /* 27456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10886 /* 27458 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10887 /* 27460 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10888 /* 27462 */ GIR_RootConstrainSelectedInstOperands,
10889 /* 27463 */ // GIR_Coverage, 776,
10890 /* 27463 */ GIR_EraseRootFromParent_Done,
10891 /* 27464 */ // Label 804: @27464
10892 /* 27464 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(27509), // Rule ID 777 //
10893 /* 27469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10894 /* 27472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
10895 /* 27477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10896 /* 27480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10897 /* 27483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10898 /* 27486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10899 /* 27490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10900 /* 27494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10901 /* 27498 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8289:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10902 /* 27498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
10903 /* 27501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10904 /* 27503 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10905 /* 27505 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10906 /* 27507 */ GIR_RootConstrainSelectedInstOperands,
10907 /* 27508 */ // GIR_Coverage, 777,
10908 /* 27508 */ GIR_EraseRootFromParent_Done,
10909 /* 27509 */ // Label 805: @27509
10910 /* 27509 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(27554), // Rule ID 778 //
10911 /* 27514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10912 /* 27517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
10913 /* 27522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10914 /* 27525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10915 /* 27528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10916 /* 27531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10917 /* 27535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10918 /* 27539 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10919 /* 27543 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8292:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10920 /* 27543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
10921 /* 27546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10922 /* 27548 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10923 /* 27550 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10924 /* 27552 */ GIR_RootConstrainSelectedInstOperands,
10925 /* 27553 */ // GIR_Coverage, 778,
10926 /* 27553 */ GIR_EraseRootFromParent_Done,
10927 /* 27554 */ // Label 806: @27554
10928 /* 27554 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(27599), // Rule ID 779 //
10929 /* 27559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10930 /* 27562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
10931 /* 27567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10932 /* 27570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10933 /* 27573 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10934 /* 27576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10935 /* 27580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10936 /* 27584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10937 /* 27588 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8291:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10938 /* 27588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
10939 /* 27591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10940 /* 27593 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10941 /* 27595 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10942 /* 27597 */ GIR_RootConstrainSelectedInstOperands,
10943 /* 27598 */ // GIR_Coverage, 779,
10944 /* 27598 */ GIR_EraseRootFromParent_Done,
10945 /* 27599 */ // Label 807: @27599
10946 /* 27599 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(27644), // Rule ID 784 //
10947 /* 27604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10948 /* 27607 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10949 /* 27612 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10950 /* 27615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10951 /* 27618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10952 /* 27621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10953 /* 27625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10954 /* 27629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10955 /* 27633 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8298:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10956 /* 27633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
10957 /* 27636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10958 /* 27638 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10959 /* 27640 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10960 /* 27642 */ GIR_RootConstrainSelectedInstOperands,
10961 /* 27643 */ // GIR_Coverage, 784,
10962 /* 27643 */ GIR_EraseRootFromParent_Done,
10963 /* 27644 */ // Label 808: @27644
10964 /* 27644 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(27689), // Rule ID 785 //
10965 /* 27649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10966 /* 27652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10967 /* 27657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10968 /* 27660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10969 /* 27663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10970 /* 27666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10971 /* 27670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10972 /* 27674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10973 /* 27678 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8297:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10974 /* 27678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
10975 /* 27681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10976 /* 27683 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10977 /* 27685 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10978 /* 27687 */ GIR_RootConstrainSelectedInstOperands,
10979 /* 27688 */ // GIR_Coverage, 785,
10980 /* 27688 */ GIR_EraseRootFromParent_Done,
10981 /* 27689 */ // Label 809: @27689
10982 /* 27689 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(27734), // Rule ID 786 //
10983 /* 27694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10984 /* 27697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
10985 /* 27702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10986 /* 27705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10987 /* 27708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10988 /* 27711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10989 /* 27715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10990 /* 27719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10991 /* 27723 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8300:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10992 /* 27723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
10993 /* 27726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10994 /* 27728 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10995 /* 27730 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10996 /* 27732 */ GIR_RootConstrainSelectedInstOperands,
10997 /* 27733 */ // GIR_Coverage, 786,
10998 /* 27733 */ GIR_EraseRootFromParent_Done,
10999 /* 27734 */ // Label 810: @27734
11000 /* 27734 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(27779), // Rule ID 787 //
11001 /* 27739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11002 /* 27742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
11003 /* 27747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11004 /* 27750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11005 /* 27753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11006 /* 27756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11007 /* 27760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11008 /* 27764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11009 /* 27768 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8299:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11010 /* 27768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
11011 /* 27771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11012 /* 27773 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11013 /* 27775 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11014 /* 27777 */ GIR_RootConstrainSelectedInstOperands,
11015 /* 27778 */ // GIR_Coverage, 787,
11016 /* 27778 */ GIR_EraseRootFromParent_Done,
11017 /* 27779 */ // Label 811: @27779
11018 /* 27779 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(27824), // Rule ID 788 //
11019 /* 27784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11020 /* 27787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
11021 /* 27792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11022 /* 27795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11023 /* 27798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11024 /* 27801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11025 /* 27805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11026 /* 27809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11027 /* 27813 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8302:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11028 /* 27813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
11029 /* 27816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11030 /* 27818 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11031 /* 27820 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11032 /* 27822 */ GIR_RootConstrainSelectedInstOperands,
11033 /* 27823 */ // GIR_Coverage, 788,
11034 /* 27823 */ GIR_EraseRootFromParent_Done,
11035 /* 27824 */ // Label 812: @27824
11036 /* 27824 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(27869), // Rule ID 789 //
11037 /* 27829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11038 /* 27832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
11039 /* 27837 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11040 /* 27840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11041 /* 27843 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11042 /* 27846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11043 /* 27850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11044 /* 27854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11045 /* 27858 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8301:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11046 /* 27858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
11047 /* 27861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11048 /* 27863 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11049 /* 27865 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11050 /* 27867 */ GIR_RootConstrainSelectedInstOperands,
11051 /* 27868 */ // GIR_Coverage, 789,
11052 /* 27868 */ GIR_EraseRootFromParent_Done,
11053 /* 27869 */ // Label 813: @27869
11054 /* 27869 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(27914), // Rule ID 790 //
11055 /* 27874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11056 /* 27877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
11057 /* 27882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11058 /* 27885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11059 /* 27888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11060 /* 27891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11061 /* 27895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11062 /* 27899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11063 /* 27903 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8304:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11064 /* 27903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
11065 /* 27906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11066 /* 27908 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11067 /* 27910 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11068 /* 27912 */ GIR_RootConstrainSelectedInstOperands,
11069 /* 27913 */ // GIR_Coverage, 790,
11070 /* 27913 */ GIR_EraseRootFromParent_Done,
11071 /* 27914 */ // Label 814: @27914
11072 /* 27914 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(27959), // Rule ID 791 //
11073 /* 27919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11074 /* 27922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
11075 /* 27927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11076 /* 27930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11077 /* 27933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11078 /* 27936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11079 /* 27940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11080 /* 27944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11081 /* 27948 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8303:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11082 /* 27948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
11083 /* 27951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11084 /* 27953 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11085 /* 27955 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11086 /* 27957 */ GIR_RootConstrainSelectedInstOperands,
11087 /* 27958 */ // GIR_Coverage, 791,
11088 /* 27958 */ GIR_EraseRootFromParent_Done,
11089 /* 27959 */ // Label 815: @27959
11090 /* 27959 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(28004), // Rule ID 792 //
11091 /* 27964 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11092 /* 27967 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
11093 /* 27972 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11094 /* 27975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11095 /* 27978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11096 /* 27981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11097 /* 27985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11098 /* 27989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11099 /* 27993 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8306:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11100 /* 27993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
11101 /* 27996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11102 /* 27998 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11103 /* 28000 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11104 /* 28002 */ GIR_RootConstrainSelectedInstOperands,
11105 /* 28003 */ // GIR_Coverage, 792,
11106 /* 28003 */ GIR_EraseRootFromParent_Done,
11107 /* 28004 */ // Label 816: @28004
11108 /* 28004 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(28049), // Rule ID 793 //
11109 /* 28009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11110 /* 28012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
11111 /* 28017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11112 /* 28020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11113 /* 28023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11114 /* 28026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11115 /* 28030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11116 /* 28034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11117 /* 28038 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8305:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11118 /* 28038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
11119 /* 28041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11120 /* 28043 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11121 /* 28045 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11122 /* 28047 */ GIR_RootConstrainSelectedInstOperands,
11123 /* 28048 */ // GIR_Coverage, 793,
11124 /* 28048 */ GIR_EraseRootFromParent_Done,
11125 /* 28049 */ // Label 817: @28049
11126 /* 28049 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(28094), // Rule ID 798 //
11127 /* 28054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11128 /* 28057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
11129 /* 28062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11130 /* 28065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11131 /* 28068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11132 /* 28071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11133 /* 28075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11134 /* 28079 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11135 /* 28083 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8311:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11136 /* 28083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
11137 /* 28086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11138 /* 28088 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11139 /* 28090 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11140 /* 28092 */ GIR_RootConstrainSelectedInstOperands,
11141 /* 28093 */ // GIR_Coverage, 798,
11142 /* 28093 */ GIR_EraseRootFromParent_Done,
11143 /* 28094 */ // Label 818: @28094
11144 /* 28094 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(28139), // Rule ID 799 //
11145 /* 28099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11146 /* 28102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
11147 /* 28107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11148 /* 28110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11149 /* 28113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11150 /* 28116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11151 /* 28120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11152 /* 28124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11153 /* 28128 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8312:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11154 /* 28128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
11155 /* 28131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11156 /* 28133 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11157 /* 28135 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11158 /* 28137 */ GIR_RootConstrainSelectedInstOperands,
11159 /* 28138 */ // GIR_Coverage, 799,
11160 /* 28138 */ GIR_EraseRootFromParent_Done,
11161 /* 28139 */ // Label 819: @28139
11162 /* 28139 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(28184), // Rule ID 804 //
11163 /* 28144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11164 /* 28147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
11165 /* 28152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11166 /* 28155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11167 /* 28158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11168 /* 28161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11169 /* 28165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11170 /* 28169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11171 /* 28173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8318:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11172 /* 28173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
11173 /* 28176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11174 /* 28178 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11175 /* 28180 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11176 /* 28182 */ GIR_RootConstrainSelectedInstOperands,
11177 /* 28183 */ // GIR_Coverage, 804,
11178 /* 28183 */ GIR_EraseRootFromParent_Done,
11179 /* 28184 */ // Label 820: @28184
11180 /* 28184 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(28229), // Rule ID 805 //
11181 /* 28189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11182 /* 28192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
11183 /* 28197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11184 /* 28200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11185 /* 28203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11186 /* 28206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11187 /* 28210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11188 /* 28214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11189 /* 28218 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8319:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11190 /* 28218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
11191 /* 28221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11192 /* 28223 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11193 /* 28225 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11194 /* 28227 */ GIR_RootConstrainSelectedInstOperands,
11195 /* 28228 */ // GIR_Coverage, 805,
11196 /* 28228 */ GIR_EraseRootFromParent_Done,
11197 /* 28229 */ // Label 821: @28229
11198 /* 28229 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(28274), // Rule ID 806 //
11199 /* 28234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11200 /* 28237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
11201 /* 28242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11202 /* 28245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11203 /* 28248 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11204 /* 28251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11205 /* 28255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11206 /* 28259 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11207 /* 28263 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8317:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11208 /* 28263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
11209 /* 28266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11210 /* 28268 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11211 /* 28270 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11212 /* 28272 */ GIR_RootConstrainSelectedInstOperands,
11213 /* 28273 */ // GIR_Coverage, 806,
11214 /* 28273 */ GIR_EraseRootFromParent_Done,
11215 /* 28274 */ // Label 822: @28274
11216 /* 28274 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(28319), // Rule ID 807 //
11217 /* 28279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11218 /* 28282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
11219 /* 28287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11220 /* 28290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11221 /* 28293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11222 /* 28296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11223 /* 28300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11224 /* 28304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11225 /* 28308 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8321:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11226 /* 28308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
11227 /* 28311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11228 /* 28313 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11229 /* 28315 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11230 /* 28317 */ GIR_RootConstrainSelectedInstOperands,
11231 /* 28318 */ // GIR_Coverage, 807,
11232 /* 28318 */ GIR_EraseRootFromParent_Done,
11233 /* 28319 */ // Label 823: @28319
11234 /* 28319 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(28364), // Rule ID 808 //
11235 /* 28324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11236 /* 28327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
11237 /* 28332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11238 /* 28335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11239 /* 28338 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11240 /* 28341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11241 /* 28345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11242 /* 28349 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11243 /* 28353 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8322:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11244 /* 28353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
11245 /* 28356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11246 /* 28358 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11247 /* 28360 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11248 /* 28362 */ GIR_RootConstrainSelectedInstOperands,
11249 /* 28363 */ // GIR_Coverage, 808,
11250 /* 28363 */ GIR_EraseRootFromParent_Done,
11251 /* 28364 */ // Label 824: @28364
11252 /* 28364 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(28409), // Rule ID 809 //
11253 /* 28369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11254 /* 28372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
11255 /* 28377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11256 /* 28380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11257 /* 28383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11258 /* 28386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11259 /* 28390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11260 /* 28394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11261 /* 28398 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8320:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11262 /* 28398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
11263 /* 28401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11264 /* 28403 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11265 /* 28405 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11266 /* 28407 */ GIR_RootConstrainSelectedInstOperands,
11267 /* 28408 */ // GIR_Coverage, 809,
11268 /* 28408 */ GIR_EraseRootFromParent_Done,
11269 /* 28409 */ // Label 825: @28409
11270 /* 28409 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(28454), // Rule ID 810 //
11271 /* 28414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11272 /* 28417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
11273 /* 28422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11274 /* 28425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11275 /* 28428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11276 /* 28431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11277 /* 28435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11278 /* 28439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11279 /* 28443 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8324:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11280 /* 28443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
11281 /* 28446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11282 /* 28448 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11283 /* 28450 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11284 /* 28452 */ GIR_RootConstrainSelectedInstOperands,
11285 /* 28453 */ // GIR_Coverage, 810,
11286 /* 28453 */ GIR_EraseRootFromParent_Done,
11287 /* 28454 */ // Label 826: @28454
11288 /* 28454 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(28499), // Rule ID 811 //
11289 /* 28459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11290 /* 28462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
11291 /* 28467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11292 /* 28470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11293 /* 28473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11294 /* 28476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11295 /* 28480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11296 /* 28484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11297 /* 28488 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8325:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11298 /* 28488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
11299 /* 28491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11300 /* 28493 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11301 /* 28495 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11302 /* 28497 */ GIR_RootConstrainSelectedInstOperands,
11303 /* 28498 */ // GIR_Coverage, 811,
11304 /* 28498 */ GIR_EraseRootFromParent_Done,
11305 /* 28499 */ // Label 827: @28499
11306 /* 28499 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(28544), // Rule ID 812 //
11307 /* 28504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11308 /* 28507 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
11309 /* 28512 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11310 /* 28515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11311 /* 28518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11312 /* 28521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11313 /* 28525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11314 /* 28529 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11315 /* 28533 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8323:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11316 /* 28533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
11317 /* 28536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11318 /* 28538 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11319 /* 28540 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11320 /* 28542 */ GIR_RootConstrainSelectedInstOperands,
11321 /* 28543 */ // GIR_Coverage, 812,
11322 /* 28543 */ GIR_EraseRootFromParent_Done,
11323 /* 28544 */ // Label 828: @28544
11324 /* 28544 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(28589), // Rule ID 813 //
11325 /* 28549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11326 /* 28552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
11327 /* 28557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11328 /* 28560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11329 /* 28563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11330 /* 28566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11331 /* 28570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11332 /* 28574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11333 /* 28578 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8327:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11334 /* 28578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
11335 /* 28581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11336 /* 28583 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11337 /* 28585 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11338 /* 28587 */ GIR_RootConstrainSelectedInstOperands,
11339 /* 28588 */ // GIR_Coverage, 813,
11340 /* 28588 */ GIR_EraseRootFromParent_Done,
11341 /* 28589 */ // Label 829: @28589
11342 /* 28589 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(28634), // Rule ID 814 //
11343 /* 28594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11344 /* 28597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
11345 /* 28602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11346 /* 28605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11347 /* 28608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11348 /* 28611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11349 /* 28615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11350 /* 28619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11351 /* 28623 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8328:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11352 /* 28623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
11353 /* 28626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11354 /* 28628 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11355 /* 28630 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11356 /* 28632 */ GIR_RootConstrainSelectedInstOperands,
11357 /* 28633 */ // GIR_Coverage, 814,
11358 /* 28633 */ GIR_EraseRootFromParent_Done,
11359 /* 28634 */ // Label 830: @28634
11360 /* 28634 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(28679), // Rule ID 815 //
11361 /* 28639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11362 /* 28642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
11363 /* 28647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11364 /* 28650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11365 /* 28653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11366 /* 28656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11367 /* 28660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11368 /* 28664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11369 /* 28668 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8326:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11370 /* 28668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
11371 /* 28671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11372 /* 28673 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11373 /* 28675 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11374 /* 28677 */ GIR_RootConstrainSelectedInstOperands,
11375 /* 28678 */ // GIR_Coverage, 815,
11376 /* 28678 */ GIR_EraseRootFromParent_Done,
11377 /* 28679 */ // Label 831: @28679
11378 /* 28679 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(28724), // Rule ID 868 //
11379 /* 28684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11380 /* 28687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
11381 /* 28692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11382 /* 28695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11383 /* 28698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11384 /* 28701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11385 /* 28705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11386 /* 28709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11387 /* 28713 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8382:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11388 /* 28713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
11389 /* 28716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11390 /* 28718 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11391 /* 28720 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11392 /* 28722 */ GIR_RootConstrainSelectedInstOperands,
11393 /* 28723 */ // GIR_Coverage, 868,
11394 /* 28723 */ GIR_EraseRootFromParent_Done,
11395 /* 28724 */ // Label 832: @28724
11396 /* 28724 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(28769), // Rule ID 869 //
11397 /* 28729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11398 /* 28732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
11399 /* 28737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11400 /* 28740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11401 /* 28743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11402 /* 28746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11403 /* 28750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11404 /* 28754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11405 /* 28758 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8384:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11406 /* 28758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
11407 /* 28761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11408 /* 28763 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11409 /* 28765 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11410 /* 28767 */ GIR_RootConstrainSelectedInstOperands,
11411 /* 28768 */ // GIR_Coverage, 869,
11412 /* 28768 */ GIR_EraseRootFromParent_Done,
11413 /* 28769 */ // Label 833: @28769
11414 /* 28769 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(28814), // Rule ID 870 //
11415 /* 28774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11416 /* 28777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
11417 /* 28782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11418 /* 28785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11419 /* 28788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11420 /* 28791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11421 /* 28795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11422 /* 28799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11423 /* 28803 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8385:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11424 /* 28803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
11425 /* 28806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11426 /* 28808 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11427 /* 28810 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11428 /* 28812 */ GIR_RootConstrainSelectedInstOperands,
11429 /* 28813 */ // GIR_Coverage, 870,
11430 /* 28813 */ GIR_EraseRootFromParent_Done,
11431 /* 28814 */ // Label 834: @28814
11432 /* 28814 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(28859), // Rule ID 871 //
11433 /* 28819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11434 /* 28822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
11435 /* 28827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11436 /* 28830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11437 /* 28833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11438 /* 28836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11439 /* 28840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11440 /* 28844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11441 /* 28848 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8383:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11442 /* 28848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
11443 /* 28851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11444 /* 28853 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11445 /* 28855 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11446 /* 28857 */ GIR_RootConstrainSelectedInstOperands,
11447 /* 28858 */ // GIR_Coverage, 871,
11448 /* 28858 */ GIR_EraseRootFromParent_Done,
11449 /* 28859 */ // Label 835: @28859
11450 /* 28859 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(28904), // Rule ID 888 //
11451 /* 28864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11452 /* 28867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
11453 /* 28872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11454 /* 28875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11455 /* 28878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11456 /* 28881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11457 /* 28885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11458 /* 28889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11459 /* 28893 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8402:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11460 /* 28893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
11461 /* 28896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11462 /* 28898 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11463 /* 28900 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11464 /* 28902 */ GIR_RootConstrainSelectedInstOperands,
11465 /* 28903 */ // GIR_Coverage, 888,
11466 /* 28903 */ GIR_EraseRootFromParent_Done,
11467 /* 28904 */ // Label 836: @28904
11468 /* 28904 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(28949), // Rule ID 889 //
11469 /* 28909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11470 /* 28912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
11471 /* 28917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11472 /* 28920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11473 /* 28923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11474 /* 28926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11475 /* 28930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11476 /* 28934 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11477 /* 28938 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8404:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11478 /* 28938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
11479 /* 28941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11480 /* 28943 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11481 /* 28945 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11482 /* 28947 */ GIR_RootConstrainSelectedInstOperands,
11483 /* 28948 */ // GIR_Coverage, 889,
11484 /* 28948 */ GIR_EraseRootFromParent_Done,
11485 /* 28949 */ // Label 837: @28949
11486 /* 28949 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(28994), // Rule ID 890 //
11487 /* 28954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11488 /* 28957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
11489 /* 28962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11490 /* 28965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11491 /* 28968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11492 /* 28971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11493 /* 28975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11494 /* 28979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11495 /* 28983 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8405:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11496 /* 28983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
11497 /* 28986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11498 /* 28988 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11499 /* 28990 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11500 /* 28992 */ GIR_RootConstrainSelectedInstOperands,
11501 /* 28993 */ // GIR_Coverage, 890,
11502 /* 28993 */ GIR_EraseRootFromParent_Done,
11503 /* 28994 */ // Label 838: @28994
11504 /* 28994 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(29039), // Rule ID 891 //
11505 /* 28999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11506 /* 29002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
11507 /* 29007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11508 /* 29010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11509 /* 29013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11510 /* 29016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11511 /* 29020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11512 /* 29024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11513 /* 29028 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8403:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11514 /* 29028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
11515 /* 29031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11516 /* 29033 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11517 /* 29035 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11518 /* 29037 */ GIR_RootConstrainSelectedInstOperands,
11519 /* 29038 */ // GIR_Coverage, 891,
11520 /* 29038 */ GIR_EraseRootFromParent_Done,
11521 /* 29039 */ // Label 839: @29039
11522 /* 29039 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(29084), // Rule ID 924 //
11523 /* 29044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11524 /* 29047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
11525 /* 29052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11526 /* 29055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11527 /* 29058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11528 /* 29061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11529 /* 29065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11530 /* 29069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11531 /* 29073 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8444:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11532 /* 29073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
11533 /* 29076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11534 /* 29078 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11535 /* 29080 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11536 /* 29082 */ GIR_RootConstrainSelectedInstOperands,
11537 /* 29083 */ // GIR_Coverage, 924,
11538 /* 29083 */ GIR_EraseRootFromParent_Done,
11539 /* 29084 */ // Label 840: @29084
11540 /* 29084 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(29129), // Rule ID 925 //
11541 /* 29089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11542 /* 29092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
11543 /* 29097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11544 /* 29100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11545 /* 29103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11546 /* 29106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11547 /* 29110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11548 /* 29114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11549 /* 29118 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8445:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11550 /* 29118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
11551 /* 29121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11552 /* 29123 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11553 /* 29125 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11554 /* 29127 */ GIR_RootConstrainSelectedInstOperands,
11555 /* 29128 */ // GIR_Coverage, 925,
11556 /* 29128 */ GIR_EraseRootFromParent_Done,
11557 /* 29129 */ // Label 841: @29129
11558 /* 29129 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(29174), // Rule ID 926 //
11559 /* 29134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11560 /* 29137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
11561 /* 29142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11562 /* 29145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11563 /* 29148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11564 /* 29151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11565 /* 29155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11566 /* 29159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11567 /* 29163 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8455:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11568 /* 29163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
11569 /* 29166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11570 /* 29168 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11571 /* 29170 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11572 /* 29172 */ GIR_RootConstrainSelectedInstOperands,
11573 /* 29173 */ // GIR_Coverage, 926,
11574 /* 29173 */ GIR_EraseRootFromParent_Done,
11575 /* 29174 */ // Label 842: @29174
11576 /* 29174 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(29219), // Rule ID 927 //
11577 /* 29179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11578 /* 29182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
11579 /* 29187 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11580 /* 29190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11581 /* 29193 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11582 /* 29196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11583 /* 29200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11584 /* 29204 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11585 /* 29208 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8456:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11586 /* 29208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
11587 /* 29211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11588 /* 29213 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11589 /* 29215 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11590 /* 29217 */ GIR_RootConstrainSelectedInstOperands,
11591 /* 29218 */ // GIR_Coverage, 927,
11592 /* 29218 */ GIR_EraseRootFromParent_Done,
11593 /* 29219 */ // Label 843: @29219
11594 /* 29219 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(29264), // Rule ID 1005 //
11595 /* 29224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11596 /* 29227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
11597 /* 29232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11598 /* 29235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11599 /* 29238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11600 /* 29241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11601 /* 29245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11602 /* 29249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11603 /* 29253 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8569:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11604 /* 29253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
11605 /* 29256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11606 /* 29258 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11607 /* 29260 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11608 /* 29262 */ GIR_RootConstrainSelectedInstOperands,
11609 /* 29263 */ // GIR_Coverage, 1005,
11610 /* 29263 */ GIR_EraseRootFromParent_Done,
11611 /* 29264 */ // Label 844: @29264
11612 /* 29264 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(29309), // Rule ID 1006 //
11613 /* 29269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11614 /* 29272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
11615 /* 29277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11616 /* 29280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11617 /* 29283 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11618 /* 29286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11619 /* 29290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11620 /* 29294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11621 /* 29298 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8571:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11622 /* 29298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
11623 /* 29301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11624 /* 29303 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11625 /* 29305 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11626 /* 29307 */ GIR_RootConstrainSelectedInstOperands,
11627 /* 29308 */ // GIR_Coverage, 1006,
11628 /* 29308 */ GIR_EraseRootFromParent_Done,
11629 /* 29309 */ // Label 845: @29309
11630 /* 29309 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(29354), // Rule ID 1007 //
11631 /* 29314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11632 /* 29317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
11633 /* 29322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11634 /* 29325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11635 /* 29328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11636 /* 29331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11637 /* 29335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11638 /* 29339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11639 /* 29343 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8572:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11640 /* 29343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
11641 /* 29346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11642 /* 29348 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11643 /* 29350 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11644 /* 29352 */ GIR_RootConstrainSelectedInstOperands,
11645 /* 29353 */ // GIR_Coverage, 1007,
11646 /* 29353 */ GIR_EraseRootFromParent_Done,
11647 /* 29354 */ // Label 846: @29354
11648 /* 29354 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(29399), // Rule ID 1008 //
11649 /* 29359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11650 /* 29362 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
11651 /* 29367 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11652 /* 29370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11653 /* 29373 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11654 /* 29376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11655 /* 29380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11656 /* 29384 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11657 /* 29388 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8570:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11658 /* 29388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
11659 /* 29391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11660 /* 29393 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11661 /* 29395 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11662 /* 29397 */ GIR_RootConstrainSelectedInstOperands,
11663 /* 29398 */ // GIR_Coverage, 1008,
11664 /* 29398 */ GIR_EraseRootFromParent_Done,
11665 /* 29399 */ // Label 847: @29399
11666 /* 29399 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(29444), // Rule ID 1021 //
11667 /* 29404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11668 /* 29407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
11669 /* 29412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11670 /* 29415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11671 /* 29418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11672 /* 29421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11673 /* 29425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11674 /* 29429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11675 /* 29433 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8585:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11676 /* 29433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
11677 /* 29436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11678 /* 29438 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11679 /* 29440 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11680 /* 29442 */ GIR_RootConstrainSelectedInstOperands,
11681 /* 29443 */ // GIR_Coverage, 1021,
11682 /* 29443 */ GIR_EraseRootFromParent_Done,
11683 /* 29444 */ // Label 848: @29444
11684 /* 29444 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(29489), // Rule ID 1022 //
11685 /* 29449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11686 /* 29452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
11687 /* 29457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11688 /* 29460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11689 /* 29463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11690 /* 29466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11691 /* 29470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11692 /* 29474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11693 /* 29478 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8587:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11694 /* 29478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
11695 /* 29481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11696 /* 29483 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11697 /* 29485 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11698 /* 29487 */ GIR_RootConstrainSelectedInstOperands,
11699 /* 29488 */ // GIR_Coverage, 1022,
11700 /* 29488 */ GIR_EraseRootFromParent_Done,
11701 /* 29489 */ // Label 849: @29489
11702 /* 29489 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(29534), // Rule ID 1023 //
11703 /* 29494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11704 /* 29497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
11705 /* 29502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11706 /* 29505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11707 /* 29508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11708 /* 29511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11709 /* 29515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11710 /* 29519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11711 /* 29523 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8588:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11712 /* 29523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
11713 /* 29526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11714 /* 29528 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11715 /* 29530 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11716 /* 29532 */ GIR_RootConstrainSelectedInstOperands,
11717 /* 29533 */ // GIR_Coverage, 1023,
11718 /* 29533 */ GIR_EraseRootFromParent_Done,
11719 /* 29534 */ // Label 850: @29534
11720 /* 29534 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(29579), // Rule ID 1024 //
11721 /* 29539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11722 /* 29542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
11723 /* 29547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11724 /* 29550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11725 /* 29553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11726 /* 29556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11727 /* 29560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11728 /* 29564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11729 /* 29568 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8586:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11730 /* 29568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
11731 /* 29571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11732 /* 29573 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11733 /* 29575 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11734 /* 29577 */ GIR_RootConstrainSelectedInstOperands,
11735 /* 29578 */ // GIR_Coverage, 1024,
11736 /* 29578 */ GIR_EraseRootFromParent_Done,
11737 /* 29579 */ // Label 851: @29579
11738 /* 29579 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(29624), // Rule ID 1033 //
11739 /* 29584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11740 /* 29587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
11741 /* 29592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11742 /* 29595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11743 /* 29598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11744 /* 29601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11745 /* 29605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11746 /* 29609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11747 /* 29613 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8606:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11748 /* 29613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
11749 /* 29616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11750 /* 29618 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11751 /* 29620 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11752 /* 29622 */ GIR_RootConstrainSelectedInstOperands,
11753 /* 29623 */ // GIR_Coverage, 1033,
11754 /* 29623 */ GIR_EraseRootFromParent_Done,
11755 /* 29624 */ // Label 852: @29624
11756 /* 29624 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(29669), // Rule ID 1034 //
11757 /* 29629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11758 /* 29632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
11759 /* 29637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11760 /* 29640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11761 /* 29643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11762 /* 29646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11763 /* 29650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11764 /* 29654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11765 /* 29658 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8608:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11766 /* 29658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
11767 /* 29661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11768 /* 29663 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11769 /* 29665 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11770 /* 29667 */ GIR_RootConstrainSelectedInstOperands,
11771 /* 29668 */ // GIR_Coverage, 1034,
11772 /* 29668 */ GIR_EraseRootFromParent_Done,
11773 /* 29669 */ // Label 853: @29669
11774 /* 29669 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(29714), // Rule ID 1035 //
11775 /* 29674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11776 /* 29677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
11777 /* 29682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11778 /* 29685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11779 /* 29688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11780 /* 29691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11781 /* 29695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11782 /* 29699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11783 /* 29703 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8609:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11784 /* 29703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
11785 /* 29706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11786 /* 29708 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11787 /* 29710 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11788 /* 29712 */ GIR_RootConstrainSelectedInstOperands,
11789 /* 29713 */ // GIR_Coverage, 1035,
11790 /* 29713 */ GIR_EraseRootFromParent_Done,
11791 /* 29714 */ // Label 854: @29714
11792 /* 29714 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(29759), // Rule ID 1036 //
11793 /* 29719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11794 /* 29722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
11795 /* 29727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11796 /* 29730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11797 /* 29733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11798 /* 29736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11799 /* 29740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11800 /* 29744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11801 /* 29748 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8607:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11802 /* 29748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
11803 /* 29751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11804 /* 29753 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11805 /* 29755 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11806 /* 29757 */ GIR_RootConstrainSelectedInstOperands,
11807 /* 29758 */ // GIR_Coverage, 1036,
11808 /* 29758 */ GIR_EraseRootFromParent_Done,
11809 /* 29759 */ // Label 855: @29759
11810 /* 29759 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(29804), // Rule ID 1037 //
11811 /* 29764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11812 /* 29767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
11813 /* 29772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11814 /* 29775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11815 /* 29778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11816 /* 29781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11817 /* 29785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11818 /* 29789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11819 /* 29793 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8610:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11820 /* 29793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
11821 /* 29796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11822 /* 29798 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11823 /* 29800 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11824 /* 29802 */ GIR_RootConstrainSelectedInstOperands,
11825 /* 29803 */ // GIR_Coverage, 1037,
11826 /* 29803 */ GIR_EraseRootFromParent_Done,
11827 /* 29804 */ // Label 856: @29804
11828 /* 29804 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(29849), // Rule ID 1038 //
11829 /* 29809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11830 /* 29812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11831 /* 29817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11832 /* 29820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11833 /* 29823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11834 /* 29826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11835 /* 29830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11836 /* 29834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11837 /* 29838 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8612:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11838 /* 29838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
11839 /* 29841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11840 /* 29843 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11841 /* 29845 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11842 /* 29847 */ GIR_RootConstrainSelectedInstOperands,
11843 /* 29848 */ // GIR_Coverage, 1038,
11844 /* 29848 */ GIR_EraseRootFromParent_Done,
11845 /* 29849 */ // Label 857: @29849
11846 /* 29849 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(29894), // Rule ID 1039 //
11847 /* 29854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11848 /* 29857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11849 /* 29862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11850 /* 29865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11851 /* 29868 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11852 /* 29871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11853 /* 29875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11854 /* 29879 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11855 /* 29883 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8613:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11856 /* 29883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
11857 /* 29886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11858 /* 29888 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11859 /* 29890 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11860 /* 29892 */ GIR_RootConstrainSelectedInstOperands,
11861 /* 29893 */ // GIR_Coverage, 1039,
11862 /* 29893 */ GIR_EraseRootFromParent_Done,
11863 /* 29894 */ // Label 858: @29894
11864 /* 29894 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(29939), // Rule ID 1040 //
11865 /* 29899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11866 /* 29902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11867 /* 29907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11868 /* 29910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11869 /* 29913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11870 /* 29916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11871 /* 29920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11872 /* 29924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11873 /* 29928 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8611:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11874 /* 29928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
11875 /* 29931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11876 /* 29933 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11877 /* 29935 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11878 /* 29937 */ GIR_RootConstrainSelectedInstOperands,
11879 /* 29938 */ // GIR_Coverage, 1040,
11880 /* 29938 */ GIR_EraseRootFromParent_Done,
11881 /* 29939 */ // Label 859: @29939
11882 /* 29939 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(29984), // Rule ID 1041 //
11883 /* 29944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11884 /* 29947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11885 /* 29952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11886 /* 29955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11887 /* 29958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11888 /* 29961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11889 /* 29965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11890 /* 29969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11891 /* 29973 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8614:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11892 /* 29973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
11893 /* 29976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11894 /* 29978 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11895 /* 29980 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11896 /* 29982 */ GIR_RootConstrainSelectedInstOperands,
11897 /* 29983 */ // GIR_Coverage, 1041,
11898 /* 29983 */ GIR_EraseRootFromParent_Done,
11899 /* 29984 */ // Label 860: @29984
11900 /* 29984 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(30029), // Rule ID 1042 //
11901 /* 29989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11902 /* 29992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11903 /* 29997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11904 /* 30000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11905 /* 30003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11906 /* 30006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11907 /* 30010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11908 /* 30014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11909 /* 30018 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8616:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11910 /* 30018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
11911 /* 30021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11912 /* 30023 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11913 /* 30025 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11914 /* 30027 */ GIR_RootConstrainSelectedInstOperands,
11915 /* 30028 */ // GIR_Coverage, 1042,
11916 /* 30028 */ GIR_EraseRootFromParent_Done,
11917 /* 30029 */ // Label 861: @30029
11918 /* 30029 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(30074), // Rule ID 1043 //
11919 /* 30034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11920 /* 30037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11921 /* 30042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11922 /* 30045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11923 /* 30048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11924 /* 30051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11925 /* 30055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11926 /* 30059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11927 /* 30063 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8617:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11928 /* 30063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
11929 /* 30066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11930 /* 30068 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11931 /* 30070 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11932 /* 30072 */ GIR_RootConstrainSelectedInstOperands,
11933 /* 30073 */ // GIR_Coverage, 1043,
11934 /* 30073 */ GIR_EraseRootFromParent_Done,
11935 /* 30074 */ // Label 862: @30074
11936 /* 30074 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(30119), // Rule ID 1044 //
11937 /* 30079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11938 /* 30082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11939 /* 30087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11940 /* 30090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11941 /* 30093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11942 /* 30096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11943 /* 30100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11944 /* 30104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11945 /* 30108 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8615:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11946 /* 30108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
11947 /* 30111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11948 /* 30113 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11949 /* 30115 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11950 /* 30117 */ GIR_RootConstrainSelectedInstOperands,
11951 /* 30118 */ // GIR_Coverage, 1044,
11952 /* 30118 */ GIR_EraseRootFromParent_Done,
11953 /* 30119 */ // Label 863: @30119
11954 /* 30119 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(30164), // Rule ID 1045 //
11955 /* 30124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11956 /* 30127 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11957 /* 30132 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11958 /* 30135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11959 /* 30138 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11960 /* 30141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11961 /* 30145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11962 /* 30149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11963 /* 30153 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8618:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11964 /* 30153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
11965 /* 30156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11966 /* 30158 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11967 /* 30160 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11968 /* 30162 */ GIR_RootConstrainSelectedInstOperands,
11969 /* 30163 */ // GIR_Coverage, 1045,
11970 /* 30163 */ GIR_EraseRootFromParent_Done,
11971 /* 30164 */ // Label 864: @30164
11972 /* 30164 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(30209), // Rule ID 1046 //
11973 /* 30169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11974 /* 30172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11975 /* 30177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11976 /* 30180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11977 /* 30183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11978 /* 30186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11979 /* 30190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11980 /* 30194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11981 /* 30198 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8620:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11982 /* 30198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
11983 /* 30201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11984 /* 30203 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11985 /* 30205 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11986 /* 30207 */ GIR_RootConstrainSelectedInstOperands,
11987 /* 30208 */ // GIR_Coverage, 1046,
11988 /* 30208 */ GIR_EraseRootFromParent_Done,
11989 /* 30209 */ // Label 865: @30209
11990 /* 30209 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(30254), // Rule ID 1047 //
11991 /* 30214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11992 /* 30217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11993 /* 30222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11994 /* 30225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11995 /* 30228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11996 /* 30231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11997 /* 30235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11998 /* 30239 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11999 /* 30243 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8621:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12000 /* 30243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
12001 /* 30246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12002 /* 30248 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
12003 /* 30250 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
12004 /* 30252 */ GIR_RootConstrainSelectedInstOperands,
12005 /* 30253 */ // GIR_Coverage, 1047,
12006 /* 30253 */ GIR_EraseRootFromParent_Done,
12007 /* 30254 */ // Label 866: @30254
12008 /* 30254 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(30299), // Rule ID 1048 //
12009 /* 30259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12010 /* 30262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
12011 /* 30267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12012 /* 30270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12013 /* 30273 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12014 /* 30276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12015 /* 30280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12016 /* 30284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12017 /* 30288 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8619:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12018 /* 30288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
12019 /* 30291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12020 /* 30293 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
12021 /* 30295 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
12022 /* 30297 */ GIR_RootConstrainSelectedInstOperands,
12023 /* 30298 */ // GIR_Coverage, 1048,
12024 /* 30298 */ GIR_EraseRootFromParent_Done,
12025 /* 30299 */ // Label 867: @30299
12026 /* 30299 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(30347), // Rule ID 1246 //
12027 /* 30304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12028 /* 30307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
12029 /* 30312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12030 /* 30315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12031 /* 30318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12032 /* 30321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12033 /* 30325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12034 /* 30329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12035 /* 30333 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7980:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12036 /* 30333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
12037 /* 30336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12038 /* 30338 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12039 /* 30340 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12040 /* 30342 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12041 /* 30345 */ GIR_RootConstrainSelectedInstOperands,
12042 /* 30346 */ // GIR_Coverage, 1246,
12043 /* 30346 */ GIR_EraseRootFromParent_Done,
12044 /* 30347 */ // Label 868: @30347
12045 /* 30347 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(30395), // Rule ID 1248 //
12046 /* 30352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12047 /* 30355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
12048 /* 30360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12049 /* 30363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12050 /* 30366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12051 /* 30369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12052 /* 30373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12053 /* 30377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12054 /* 30381 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8002:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12055 /* 30381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
12056 /* 30384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12057 /* 30386 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12058 /* 30388 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12059 /* 30390 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12060 /* 30393 */ GIR_RootConstrainSelectedInstOperands,
12061 /* 30394 */ // GIR_Coverage, 1248,
12062 /* 30394 */ GIR_EraseRootFromParent_Done,
12063 /* 30395 */ // Label 869: @30395
12064 /* 30395 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(30440), // Rule ID 1269 //
12065 /* 30400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12066 /* 30403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
12067 /* 30408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12068 /* 30411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12069 /* 30414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12070 /* 30417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12071 /* 30421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12072 /* 30425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12073 /* 30429 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8530:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12074 /* 30429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
12075 /* 30432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12076 /* 30434 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12077 /* 30436 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12078 /* 30438 */ GIR_RootConstrainSelectedInstOperands,
12079 /* 30439 */ // GIR_Coverage, 1269,
12080 /* 30439 */ GIR_EraseRootFromParent_Done,
12081 /* 30440 */ // Label 870: @30440
12082 /* 30440 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30485), // Rule ID 1270 //
12083 /* 30445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12084 /* 30448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
12085 /* 30453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12086 /* 30456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12087 /* 30459 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12088 /* 30462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12089 /* 30466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12090 /* 30470 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12091 /* 30474 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8532:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12092 /* 30474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
12093 /* 30477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12094 /* 30479 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12095 /* 30481 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12096 /* 30483 */ GIR_RootConstrainSelectedInstOperands,
12097 /* 30484 */ // GIR_Coverage, 1270,
12098 /* 30484 */ GIR_EraseRootFromParent_Done,
12099 /* 30485 */ // Label 871: @30485
12100 /* 30485 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30530), // Rule ID 1271 //
12101 /* 30490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12102 /* 30493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
12103 /* 30498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12104 /* 30501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12105 /* 30504 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12106 /* 30507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12107 /* 30511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12108 /* 30515 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12109 /* 30519 */ // (intrinsic_wo_chain:{ *:[i32] } 8534:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12110 /* 30519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
12111 /* 30522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12112 /* 30524 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12113 /* 30526 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12114 /* 30528 */ GIR_RootConstrainSelectedInstOperands,
12115 /* 30529 */ // GIR_Coverage, 1271,
12116 /* 30529 */ GIR_EraseRootFromParent_Done,
12117 /* 30530 */ // Label 872: @30530
12118 /* 30530 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30575), // Rule ID 1273 //
12119 /* 30535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12120 /* 30538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
12121 /* 30543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12122 /* 30546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12123 /* 30549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12124 /* 30552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12125 /* 30556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12126 /* 30560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12127 /* 30564 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8536:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12128 /* 30564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
12129 /* 30567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12130 /* 30569 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12131 /* 30571 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12132 /* 30573 */ GIR_RootConstrainSelectedInstOperands,
12133 /* 30574 */ // GIR_Coverage, 1273,
12134 /* 30574 */ GIR_EraseRootFromParent_Done,
12135 /* 30575 */ // Label 873: @30575
12136 /* 30575 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30623), // Rule ID 1284 //
12137 /* 30580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12138 /* 30583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
12139 /* 30588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12140 /* 30591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12141 /* 30594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12142 /* 30597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12143 /* 30601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12144 /* 30605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12145 /* 30609 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8600:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12146 /* 30609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
12147 /* 30612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12148 /* 30614 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12149 /* 30616 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12150 /* 30618 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12151 /* 30621 */ GIR_RootConstrainSelectedInstOperands,
12152 /* 30622 */ // GIR_Coverage, 1284,
12153 /* 30622 */ GIR_EraseRootFromParent_Done,
12154 /* 30623 */ // Label 874: @30623
12155 /* 30623 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(30671), // Rule ID 1286 //
12156 /* 30628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12157 /* 30631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
12158 /* 30636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12159 /* 30639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12160 /* 30642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12161 /* 30645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12162 /* 30649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12163 /* 30653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12164 /* 30657 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8625:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12165 /* 30657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
12166 /* 30660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12167 /* 30662 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12168 /* 30664 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12169 /* 30666 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12170 /* 30669 */ GIR_RootConstrainSelectedInstOperands,
12171 /* 30670 */ // GIR_Coverage, 1286,
12172 /* 30670 */ GIR_EraseRootFromParent_Done,
12173 /* 30671 */ // Label 875: @30671
12174 /* 30671 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(30716), // Rule ID 1296 //
12175 /* 30676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12176 /* 30679 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
12177 /* 30684 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12178 /* 30687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12179 /* 30690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12180 /* 30693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12181 /* 30697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12182 /* 30701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12183 /* 30705 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8505:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12184 /* 30705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
12185 /* 30708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12186 /* 30710 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12187 /* 30712 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12188 /* 30714 */ GIR_RootConstrainSelectedInstOperands,
12189 /* 30715 */ // GIR_Coverage, 1296,
12190 /* 30715 */ GIR_EraseRootFromParent_Done,
12191 /* 30716 */ // Label 876: @30716
12192 /* 30716 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(30761), // Rule ID 1297 //
12193 /* 30721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12194 /* 30724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
12195 /* 30729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12196 /* 30732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12197 /* 30735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12198 /* 30738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12199 /* 30742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12200 /* 30746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12201 /* 30750 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8506:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12202 /* 30750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
12203 /* 30753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12204 /* 30755 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12205 /* 30757 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12206 /* 30759 */ GIR_RootConstrainSelectedInstOperands,
12207 /* 30760 */ // GIR_Coverage, 1297,
12208 /* 30760 */ GIR_EraseRootFromParent_Done,
12209 /* 30761 */ // Label 877: @30761
12210 /* 30761 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(30806), // Rule ID 1316 //
12211 /* 30766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12212 /* 30769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
12213 /* 30774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12214 /* 30777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12215 /* 30780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12216 /* 30783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12217 /* 30787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12218 /* 30791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12219 /* 30795 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8477:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12220 /* 30795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
12221 /* 30798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12222 /* 30800 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12223 /* 30802 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12224 /* 30804 */ GIR_RootConstrainSelectedInstOperands,
12225 /* 30805 */ // GIR_Coverage, 1316,
12226 /* 30805 */ GIR_EraseRootFromParent_Done,
12227 /* 30806 */ // Label 878: @30806
12228 /* 30806 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(30851), // Rule ID 1322 //
12229 /* 30811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12230 /* 30814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
12231 /* 30819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12232 /* 30822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12233 /* 30825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12234 /* 30828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12235 /* 30832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12236 /* 30836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12237 /* 30840 */ // (intrinsic_wo_chain:{ *:[i32] } 8430:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12238 /* 30840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
12239 /* 30843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12240 /* 30845 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12241 /* 30847 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12242 /* 30849 */ GIR_RootConstrainSelectedInstOperands,
12243 /* 30850 */ // GIR_Coverage, 1322,
12244 /* 30850 */ GIR_EraseRootFromParent_Done,
12245 /* 30851 */ // Label 879: @30851
12246 /* 30851 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(30896), // Rule ID 1335 //
12247 /* 30856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12248 /* 30859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
12249 /* 30864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12250 /* 30867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12251 /* 30870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12252 /* 30873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12253 /* 30877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12254 /* 30881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12255 /* 30885 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7982:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12256 /* 30885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
12257 /* 30888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12258 /* 30890 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12259 /* 30892 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12260 /* 30894 */ GIR_RootConstrainSelectedInstOperands,
12261 /* 30895 */ // GIR_Coverage, 1335,
12262 /* 30895 */ GIR_EraseRootFromParent_Done,
12263 /* 30896 */ // Label 880: @30896
12264 /* 30896 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(30941), // Rule ID 1336 //
12265 /* 30901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12266 /* 30904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
12267 /* 30909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12268 /* 30912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12269 /* 30915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12270 /* 30918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12271 /* 30922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12272 /* 30926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12273 /* 30930 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7983:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12274 /* 30930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
12275 /* 30933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12276 /* 30935 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12277 /* 30937 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12278 /* 30939 */ GIR_RootConstrainSelectedInstOperands,
12279 /* 30940 */ // GIR_Coverage, 1336,
12280 /* 30940 */ GIR_EraseRootFromParent_Done,
12281 /* 30941 */ // Label 881: @30941
12282 /* 30941 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(30986), // Rule ID 1337 //
12283 /* 30946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12284 /* 30949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
12285 /* 30954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12286 /* 30957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12287 /* 30960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12288 /* 30963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12289 /* 30967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12290 /* 30971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12291 /* 30975 */ // (intrinsic_wo_chain:{ *:[i32] } 7985:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12292 /* 30975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
12293 /* 30978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12294 /* 30980 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12295 /* 30982 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12296 /* 30984 */ GIR_RootConstrainSelectedInstOperands,
12297 /* 30985 */ // GIR_Coverage, 1337,
12298 /* 30985 */ GIR_EraseRootFromParent_Done,
12299 /* 30986 */ // Label 882: @30986
12300 /* 30986 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(31031), // Rule ID 1338 //
12301 /* 30991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12302 /* 30994 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
12303 /* 30999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12304 /* 31002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12305 /* 31005 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12306 /* 31008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12307 /* 31012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12308 /* 31016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12309 /* 31020 */ // (intrinsic_wo_chain:{ *:[i32] } 7984:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12310 /* 31020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
12311 /* 31023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12312 /* 31025 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12313 /* 31027 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12314 /* 31029 */ GIR_RootConstrainSelectedInstOperands,
12315 /* 31030 */ // GIR_Coverage, 1338,
12316 /* 31030 */ GIR_EraseRootFromParent_Done,
12317 /* 31031 */ // Label 883: @31031
12318 /* 31031 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31076), // Rule ID 1341 //
12319 /* 31036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12320 /* 31039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
12321 /* 31044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12322 /* 31047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12323 /* 31050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12324 /* 31053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12325 /* 31057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12326 /* 31061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12327 /* 31065 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8003:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12328 /* 31065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
12329 /* 31068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12330 /* 31070 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12331 /* 31072 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12332 /* 31074 */ GIR_RootConstrainSelectedInstOperands,
12333 /* 31075 */ // GIR_Coverage, 1341,
12334 /* 31075 */ GIR_EraseRootFromParent_Done,
12335 /* 31076 */ // Label 884: @31076
12336 /* 31076 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(31121), // Rule ID 1342 //
12337 /* 31081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12338 /* 31084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
12339 /* 31089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12340 /* 31092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12341 /* 31095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12342 /* 31098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12343 /* 31102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12344 /* 31106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12345 /* 31110 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8004:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12346 /* 31110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
12347 /* 31113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12348 /* 31115 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12349 /* 31117 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12350 /* 31119 */ GIR_RootConstrainSelectedInstOperands,
12351 /* 31120 */ // GIR_Coverage, 1342,
12352 /* 31120 */ GIR_EraseRootFromParent_Done,
12353 /* 31121 */ // Label 885: @31121
12354 /* 31121 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(31166), // Rule ID 1348 //
12355 /* 31126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12356 /* 31129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
12357 /* 31134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12358 /* 31137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12359 /* 31140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12360 /* 31143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12361 /* 31147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12362 /* 31151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12363 /* 31155 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8531:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12364 /* 31155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
12365 /* 31158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12366 /* 31160 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12367 /* 31162 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12368 /* 31164 */ GIR_RootConstrainSelectedInstOperands,
12369 /* 31165 */ // GIR_Coverage, 1348,
12370 /* 31165 */ GIR_EraseRootFromParent_Done,
12371 /* 31166 */ // Label 886: @31166
12372 /* 31166 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(31211), // Rule ID 1349 //
12373 /* 31171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12374 /* 31174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
12375 /* 31179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12376 /* 31182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12377 /* 31185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12378 /* 31188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12379 /* 31192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12380 /* 31196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12381 /* 31200 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8533:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12382 /* 31200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
12383 /* 31203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12384 /* 31205 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12385 /* 31207 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12386 /* 31209 */ GIR_RootConstrainSelectedInstOperands,
12387 /* 31210 */ // GIR_Coverage, 1349,
12388 /* 31210 */ GIR_EraseRootFromParent_Done,
12389 /* 31211 */ // Label 887: @31211
12390 /* 31211 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(31256), // Rule ID 1354 //
12391 /* 31216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12392 /* 31219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
12393 /* 31224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12394 /* 31227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12395 /* 31230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12396 /* 31233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12397 /* 31237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12398 /* 31241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12399 /* 31245 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8535:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12400 /* 31245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
12401 /* 31248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12402 /* 31250 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12403 /* 31252 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12404 /* 31254 */ GIR_RootConstrainSelectedInstOperands,
12405 /* 31255 */ // GIR_Coverage, 1354,
12406 /* 31255 */ GIR_EraseRootFromParent_Done,
12407 /* 31256 */ // Label 888: @31256
12408 /* 31256 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(31301), // Rule ID 1355 //
12409 /* 31261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12410 /* 31264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
12411 /* 31269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12412 /* 31272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12413 /* 31275 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12414 /* 31278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12415 /* 31282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12416 /* 31286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12417 /* 31290 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8602:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12418 /* 31290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
12419 /* 31293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12420 /* 31295 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12421 /* 31297 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12422 /* 31299 */ GIR_RootConstrainSelectedInstOperands,
12423 /* 31300 */ // GIR_Coverage, 1355,
12424 /* 31300 */ GIR_EraseRootFromParent_Done,
12425 /* 31301 */ // Label 889: @31301
12426 /* 31301 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(31346), // Rule ID 1356 //
12427 /* 31306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12428 /* 31309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
12429 /* 31314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12430 /* 31317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12431 /* 31320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12432 /* 31323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12433 /* 31327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12434 /* 31331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12435 /* 31335 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8603:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12436 /* 31335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
12437 /* 31338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12438 /* 31340 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12439 /* 31342 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12440 /* 31344 */ GIR_RootConstrainSelectedInstOperands,
12441 /* 31345 */ // GIR_Coverage, 1356,
12442 /* 31345 */ GIR_EraseRootFromParent_Done,
12443 /* 31346 */ // Label 890: @31346
12444 /* 31346 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(31391), // Rule ID 1357 //
12445 /* 31351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12446 /* 31354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
12447 /* 31359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12448 /* 31362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12449 /* 31365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12450 /* 31368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12451 /* 31372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12452 /* 31376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12453 /* 31380 */ // (intrinsic_wo_chain:{ *:[i32] } 8605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12454 /* 31380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
12455 /* 31383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12456 /* 31385 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12457 /* 31387 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12458 /* 31389 */ GIR_RootConstrainSelectedInstOperands,
12459 /* 31390 */ // GIR_Coverage, 1357,
12460 /* 31390 */ GIR_EraseRootFromParent_Done,
12461 /* 31391 */ // Label 891: @31391
12462 /* 31391 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(31436), // Rule ID 1358 //
12463 /* 31396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12464 /* 31399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
12465 /* 31404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12466 /* 31407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12467 /* 31410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12468 /* 31413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12469 /* 31417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12470 /* 31421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12471 /* 31425 */ // (intrinsic_wo_chain:{ *:[i32] } 8604:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12472 /* 31425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
12473 /* 31428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12474 /* 31430 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12475 /* 31432 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12476 /* 31434 */ GIR_RootConstrainSelectedInstOperands,
12477 /* 31435 */ // GIR_Coverage, 1358,
12478 /* 31435 */ GIR_EraseRootFromParent_Done,
12479 /* 31436 */ // Label 892: @31436
12480 /* 31436 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(31481), // Rule ID 1361 //
12481 /* 31441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12482 /* 31444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
12483 /* 31449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12484 /* 31452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12485 /* 31455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12486 /* 31458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12487 /* 31462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12488 /* 31466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12489 /* 31470 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8626:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12490 /* 31470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
12491 /* 31473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12492 /* 31475 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12493 /* 31477 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12494 /* 31479 */ GIR_RootConstrainSelectedInstOperands,
12495 /* 31480 */ // GIR_Coverage, 1361,
12496 /* 31480 */ GIR_EraseRootFromParent_Done,
12497 /* 31481 */ // Label 893: @31481
12498 /* 31481 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(31526), // Rule ID 1362 //
12499 /* 31486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12500 /* 31489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
12501 /* 31494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12502 /* 31497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12503 /* 31500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12504 /* 31503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12505 /* 31507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12506 /* 31511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12507 /* 31515 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8627:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12508 /* 31515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
12509 /* 31518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12510 /* 31520 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12511 /* 31522 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12512 /* 31524 */ GIR_RootConstrainSelectedInstOperands,
12513 /* 31525 */ // GIR_Coverage, 1362,
12514 /* 31525 */ GIR_EraseRootFromParent_Done,
12515 /* 31526 */ // Label 894: @31526
12516 /* 31526 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(31566), // Rule ID 2052 //
12517 /* 31531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12518 /* 31534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
12519 /* 31539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12520 /* 31542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12521 /* 31545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12522 /* 31548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12523 /* 31552 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7979:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12524 /* 31552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
12525 /* 31555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12526 /* 31557 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12527 /* 31559 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12528 /* 31561 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12529 /* 31564 */ GIR_RootConstrainSelectedInstOperands,
12530 /* 31565 */ // GIR_Coverage, 2052,
12531 /* 31565 */ GIR_EraseRootFromParent_Done,
12532 /* 31566 */ // Label 895: @31566
12533 /* 31566 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(31606), // Rule ID 2054 //
12534 /* 31571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12535 /* 31574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
12536 /* 31579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12537 /* 31582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12538 /* 31585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12539 /* 31588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12540 /* 31592 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8599:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12541 /* 31592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
12542 /* 31595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12543 /* 31597 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12544 /* 31599 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12545 /* 31601 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12546 /* 31604 */ GIR_RootConstrainSelectedInstOperands,
12547 /* 31605 */ // GIR_Coverage, 2054,
12548 /* 31605 */ GIR_EraseRootFromParent_Done,
12549 /* 31606 */ // Label 896: @31606
12550 /* 31606 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(31646), // Rule ID 2058 //
12551 /* 31611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12552 /* 31614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
12553 /* 31619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12554 /* 31622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12555 /* 31625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12556 /* 31628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12557 /* 31632 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8000:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
12558 /* 31632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
12559 /* 31635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12560 /* 31637 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12561 /* 31639 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12562 /* 31641 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12563 /* 31644 */ GIR_RootConstrainSelectedInstOperands,
12564 /* 31645 */ // GIR_Coverage, 2058,
12565 /* 31645 */ GIR_EraseRootFromParent_Done,
12566 /* 31646 */ // Label 897: @31646
12567 /* 31646 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(31686), // Rule ID 2060 //
12568 /* 31651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12569 /* 31654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
12570 /* 31659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12571 /* 31662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12572 /* 31665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12573 /* 31668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12574 /* 31672 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8623:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
12575 /* 31672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
12576 /* 31675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12577 /* 31677 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12578 /* 31679 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12579 /* 31681 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12580 /* 31684 */ GIR_RootConstrainSelectedInstOperands,
12581 /* 31685 */ // GIR_Coverage, 2060,
12582 /* 31685 */ GIR_EraseRootFromParent_Done,
12583 /* 31686 */ // Label 898: @31686
12584 /* 31686 */ GIM_Reject,
12585 /* 31687 */ // Label 684: @31687
12586 /* 31687 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(34201),
12587 /* 31692 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
12588 /* 31695 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(31750), // Rule ID 501 //
12589 /* 31700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12590 /* 31703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12591 /* 31708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12592 /* 31711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12593 /* 31714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12594 /* 31717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12595 /* 31721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12596 /* 31725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12597 /* 31729 */ // MIs[0] sa
12598 /* 31729 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12599 /* 31732 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12600 /* 31737 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8503:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12601 /* 31737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
12602 /* 31740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12603 /* 31742 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12604 /* 31744 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12605 /* 31746 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12606 /* 31748 */ GIR_RootConstrainSelectedInstOperands,
12607 /* 31749 */ // GIR_Coverage, 501,
12608 /* 31749 */ GIR_EraseRootFromParent_Done,
12609 /* 31750 */ // Label 900: @31750
12610 /* 31750 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(31805), // Rule ID 502 //
12611 /* 31755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12612 /* 31758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12613 /* 31763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12614 /* 31766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12615 /* 31769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12616 /* 31772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12617 /* 31776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12618 /* 31780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12619 /* 31784 */ // MIs[0] sa
12620 /* 31784 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12621 /* 31787 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12622 /* 31792 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8504:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12623 /* 31792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
12624 /* 31795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12625 /* 31797 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12626 /* 31799 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12627 /* 31801 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12628 /* 31803 */ GIR_RootConstrainSelectedInstOperands,
12629 /* 31804 */ // GIR_Coverage, 502,
12630 /* 31804 */ GIR_EraseRootFromParent_Done,
12631 /* 31805 */ // Label 901: @31805
12632 /* 31805 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(31860), // Rule ID 507 //
12633 /* 31810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12634 /* 31813 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12635 /* 31818 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12636 /* 31821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12637 /* 31824 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12638 /* 31827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12639 /* 31831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12640 /* 31835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12641 /* 31839 */ // MIs[0] sa
12642 /* 31839 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12643 /* 31842 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12644 /* 31847 */ // (intrinsic_wo_chain:{ *:[i32] } 8016:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12645 /* 31847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
12646 /* 31850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12647 /* 31852 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12648 /* 31854 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12649 /* 31856 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12650 /* 31858 */ GIR_RootConstrainSelectedInstOperands,
12651 /* 31859 */ // GIR_Coverage, 507,
12652 /* 31859 */ GIR_EraseRootFromParent_Done,
12653 /* 31860 */ // Label 902: @31860
12654 /* 31860 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(31915), // Rule ID 508 //
12655 /* 31865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12656 /* 31868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12657 /* 31873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12658 /* 31876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12659 /* 31879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12660 /* 31882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12661 /* 31886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12662 /* 31890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12663 /* 31894 */ // MIs[0] sa
12664 /* 31894 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12665 /* 31897 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12666 /* 31902 */ // (intrinsic_wo_chain:{ *:[i32] } 8041:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12667 /* 31902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
12668 /* 31905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12669 /* 31907 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12670 /* 31909 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12671 /* 31911 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12672 /* 31913 */ GIR_RootConstrainSelectedInstOperands,
12673 /* 31914 */ // GIR_Coverage, 508,
12674 /* 31914 */ GIR_EraseRootFromParent_Done,
12675 /* 31915 */ // Label 903: @31915
12676 /* 31915 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(31970), // Rule ID 509 //
12677 /* 31920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12678 /* 31923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12679 /* 31928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12680 /* 31931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12681 /* 31934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12682 /* 31937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12683 /* 31941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12684 /* 31945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12685 /* 31949 */ // MIs[0] sa
12686 /* 31949 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12687 /* 31952 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12688 /* 31957 */ // (intrinsic_wo_chain:{ *:[i32] } 8509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12689 /* 31957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
12690 /* 31960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12691 /* 31962 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12692 /* 31964 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12693 /* 31966 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12694 /* 31968 */ GIR_RootConstrainSelectedInstOperands,
12695 /* 31969 */ // GIR_Coverage, 509,
12696 /* 31969 */ GIR_EraseRootFromParent_Done,
12697 /* 31970 */ // Label 904: @31970
12698 /* 31970 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(32025), // Rule ID 977 //
12699 /* 31975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12700 /* 31978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
12701 /* 31983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12702 /* 31986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12703 /* 31989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12704 /* 31992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12705 /* 31996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12706 /* 32000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12707 /* 32004 */ // MIs[0] n
12708 /* 32004 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12709 /* 32007 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
12710 /* 32012 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8541:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
12711 /* 32012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
12712 /* 32015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12713 /* 32017 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12714 /* 32019 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12715 /* 32021 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12716 /* 32023 */ GIR_RootConstrainSelectedInstOperands,
12717 /* 32024 */ // GIR_Coverage, 977,
12718 /* 32024 */ GIR_EraseRootFromParent_Done,
12719 /* 32025 */ // Label 905: @32025
12720 /* 32025 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(32080), // Rule ID 978 //
12721 /* 32030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12722 /* 32033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
12723 /* 32038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12724 /* 32041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12725 /* 32044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12726 /* 32047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12727 /* 32051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12728 /* 32055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12729 /* 32059 */ // MIs[0] n
12730 /* 32059 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12731 /* 32062 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
12732 /* 32067 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8543:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
12733 /* 32067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
12734 /* 32070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12735 /* 32072 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12736 /* 32074 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12737 /* 32076 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12738 /* 32078 */ GIR_RootConstrainSelectedInstOperands,
12739 /* 32079 */ // GIR_Coverage, 978,
12740 /* 32079 */ GIR_EraseRootFromParent_Done,
12741 /* 32080 */ // Label 906: @32080
12742 /* 32080 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(32135), // Rule ID 979 //
12743 /* 32085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12744 /* 32088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
12745 /* 32093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12746 /* 32096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12747 /* 32099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12748 /* 32102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12749 /* 32106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12750 /* 32110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12751 /* 32114 */ // MIs[0] n
12752 /* 32114 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12753 /* 32117 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12754 /* 32122 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8544:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
12755 /* 32122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
12756 /* 32125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12757 /* 32127 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12758 /* 32129 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12759 /* 32131 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12760 /* 32133 */ GIR_RootConstrainSelectedInstOperands,
12761 /* 32134 */ // GIR_Coverage, 979,
12762 /* 32134 */ GIR_EraseRootFromParent_Done,
12763 /* 32135 */ // Label 907: @32135
12764 /* 32135 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(32190), // Rule ID 980 //
12765 /* 32140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12766 /* 32143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
12767 /* 32148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12768 /* 32151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12769 /* 32154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12770 /* 32157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12771 /* 32161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12772 /* 32165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12773 /* 32169 */ // MIs[0] n
12774 /* 32169 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12775 /* 32172 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
12776 /* 32177 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8542:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
12777 /* 32177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
12778 /* 32180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12779 /* 32182 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12780 /* 32184 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12781 /* 32186 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12782 /* 32188 */ GIR_RootConstrainSelectedInstOperands,
12783 /* 32189 */ // GIR_Coverage, 980,
12784 /* 32189 */ GIR_EraseRootFromParent_Done,
12785 /* 32190 */ // Label 908: @32190
12786 /* 32190 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(32245), // Rule ID 1372 //
12787 /* 32195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12788 /* 32198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12789 /* 32203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12790 /* 32206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12791 /* 32209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12792 /* 32212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12793 /* 32216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12794 /* 32220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12795 /* 32224 */ // MIs[0] sa
12796 /* 32224 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12797 /* 32227 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12798 /* 32232 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8503:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12799 /* 32232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
12800 /* 32235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12801 /* 32237 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12802 /* 32239 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12803 /* 32241 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12804 /* 32243 */ GIR_RootConstrainSelectedInstOperands,
12805 /* 32244 */ // GIR_Coverage, 1372,
12806 /* 32244 */ GIR_EraseRootFromParent_Done,
12807 /* 32245 */ // Label 909: @32245
12808 /* 32245 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(32300), // Rule ID 1373 //
12809 /* 32250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12810 /* 32253 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12811 /* 32258 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12812 /* 32261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12813 /* 32264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12814 /* 32267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12815 /* 32271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12816 /* 32275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12817 /* 32279 */ // MIs[0] sa
12818 /* 32279 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12819 /* 32282 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12820 /* 32287 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8504:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12821 /* 32287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
12822 /* 32290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12823 /* 32292 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12824 /* 32294 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12825 /* 32296 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12826 /* 32298 */ GIR_RootConstrainSelectedInstOperands,
12827 /* 32299 */ // GIR_Coverage, 1373,
12828 /* 32299 */ GIR_EraseRootFromParent_Done,
12829 /* 32300 */ // Label 910: @32300
12830 /* 32300 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(32355), // Rule ID 1374 //
12831 /* 32305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12832 /* 32308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12833 /* 32313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12834 /* 32316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12835 /* 32319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12836 /* 32322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12837 /* 32326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12838 /* 32330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12839 /* 32334 */ // MIs[0] sa
12840 /* 32334 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12841 /* 32337 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12842 /* 32342 */ // (intrinsic_wo_chain:{ *:[i32] } 8509:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12843 /* 32342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
12844 /* 32345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12845 /* 32347 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12846 /* 32349 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12847 /* 32351 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12848 /* 32353 */ GIR_RootConstrainSelectedInstOperands,
12849 /* 32354 */ // GIR_Coverage, 1374,
12850 /* 32354 */ GIR_EraseRootFromParent_Done,
12851 /* 32355 */ // Label 911: @32355
12852 /* 32355 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(32410), // Rule ID 1375 //
12853 /* 32360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12854 /* 32363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12855 /* 32368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12856 /* 32371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12857 /* 32374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12858 /* 32377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12859 /* 32381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12860 /* 32385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12861 /* 32389 */ // MIs[0] sa
12862 /* 32389 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12863 /* 32392 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12864 /* 32397 */ // (intrinsic_wo_chain:{ *:[i32] } 8016:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12865 /* 32397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
12866 /* 32400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12867 /* 32402 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12868 /* 32404 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12869 /* 32406 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12870 /* 32408 */ GIR_RootConstrainSelectedInstOperands,
12871 /* 32409 */ // GIR_Coverage, 1375,
12872 /* 32409 */ GIR_EraseRootFromParent_Done,
12873 /* 32410 */ // Label 912: @32410
12874 /* 32410 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(32472), // Rule ID 1350 //
12875 /* 32415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12876 /* 32418 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12877 /* 32423 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12878 /* 32426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12879 /* 32429 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12880 /* 32432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12881 /* 32436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12882 /* 32440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12883 /* 32444 */ // MIs[0] bp
12884 /* 32444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
12885 /* 32448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12886 /* 32452 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12887 /* 32456 */ // MIs[1] Operand 1
12888 /* 32456 */ // No operand predicates
12889 /* 32456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
12890 /* 32458 */ // (intrinsic_wo_chain:{ *:[i32] } 8041:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
12891 /* 32458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
12892 /* 32461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12893 /* 32463 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12894 /* 32465 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
12895 /* 32468 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12896 /* 32470 */ GIR_RootConstrainSelectedInstOperands,
12897 /* 32471 */ // GIR_Coverage, 1350,
12898 /* 32471 */ GIR_EraseRootFromParent_Done,
12899 /* 32472 */ // Label 913: @32472
12900 /* 32472 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(32526), // Rule ID 576 //
12901 /* 32477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12902 /* 32480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
12903 /* 32485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12904 /* 32488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12905 /* 32491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12906 /* 32494 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12907 /* 32497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12908 /* 32501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12909 /* 32505 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12910 /* 32509 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12911 /* 32513 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8050:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12912 /* 32513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
12913 /* 32516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12914 /* 32518 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12915 /* 32520 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12916 /* 32522 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12917 /* 32524 */ GIR_RootConstrainSelectedInstOperands,
12918 /* 32525 */ // GIR_Coverage, 576,
12919 /* 32525 */ GIR_EraseRootFromParent_Done,
12920 /* 32526 */ // Label 914: @32526
12921 /* 32526 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(32580), // Rule ID 577 //
12922 /* 32531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12923 /* 32534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
12924 /* 32539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12925 /* 32542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12926 /* 32545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12927 /* 32548 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12928 /* 32551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12929 /* 32555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12930 /* 32559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12931 /* 32563 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12932 /* 32567 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8052:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12933 /* 32567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
12934 /* 32570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12935 /* 32572 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12936 /* 32574 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12937 /* 32576 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12938 /* 32578 */ GIR_RootConstrainSelectedInstOperands,
12939 /* 32579 */ // GIR_Coverage, 577,
12940 /* 32579 */ GIR_EraseRootFromParent_Done,
12941 /* 32580 */ // Label 915: @32580
12942 /* 32580 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(32634), // Rule ID 578 //
12943 /* 32585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12944 /* 32588 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
12945 /* 32593 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12946 /* 32596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12947 /* 32599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12948 /* 32602 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12949 /* 32605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12950 /* 32609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12951 /* 32613 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12952 /* 32617 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12953 /* 32621 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8053:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12954 /* 32621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
12955 /* 32624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12956 /* 32626 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12957 /* 32628 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12958 /* 32630 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12959 /* 32632 */ GIR_RootConstrainSelectedInstOperands,
12960 /* 32633 */ // GIR_Coverage, 578,
12961 /* 32633 */ GIR_EraseRootFromParent_Done,
12962 /* 32634 */ // Label 916: @32634
12963 /* 32634 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(32688), // Rule ID 579 //
12964 /* 32639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12965 /* 32642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
12966 /* 32647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12967 /* 32650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12968 /* 32653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12969 /* 32656 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12970 /* 32659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12971 /* 32663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12972 /* 32667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12973 /* 32671 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12974 /* 32675 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8051:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12975 /* 32675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
12976 /* 32678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12977 /* 32680 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12978 /* 32682 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12979 /* 32684 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12980 /* 32686 */ GIR_RootConstrainSelectedInstOperands,
12981 /* 32687 */ // GIR_Coverage, 579,
12982 /* 32687 */ GIR_EraseRootFromParent_Done,
12983 /* 32688 */ // Label 917: @32688
12984 /* 32688 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(32742), // Rule ID 584 //
12985 /* 32693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12986 /* 32696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
12987 /* 32701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12988 /* 32704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12989 /* 32707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12990 /* 32710 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12991 /* 32713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12992 /* 32717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12993 /* 32721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12994 /* 32725 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12995 /* 32729 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8058:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12996 /* 32729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
12997 /* 32732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12998 /* 32734 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12999 /* 32736 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13000 /* 32738 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13001 /* 32740 */ GIR_RootConstrainSelectedInstOperands,
13002 /* 32741 */ // GIR_Coverage, 584,
13003 /* 32741 */ GIR_EraseRootFromParent_Done,
13004 /* 32742 */ // Label 918: @32742
13005 /* 32742 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(32796), // Rule ID 585 //
13006 /* 32747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13007 /* 32750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
13008 /* 32755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13009 /* 32758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13010 /* 32761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13011 /* 32764 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13012 /* 32767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13013 /* 32771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13014 /* 32775 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13015 /* 32779 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13016 /* 32783 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8060:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13017 /* 32783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
13018 /* 32786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13019 /* 32788 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13020 /* 32790 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13021 /* 32792 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13022 /* 32794 */ GIR_RootConstrainSelectedInstOperands,
13023 /* 32795 */ // GIR_Coverage, 585,
13024 /* 32795 */ GIR_EraseRootFromParent_Done,
13025 /* 32796 */ // Label 919: @32796
13026 /* 32796 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(32850), // Rule ID 586 //
13027 /* 32801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13028 /* 32804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
13029 /* 32809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13030 /* 32812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13031 /* 32815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13032 /* 32818 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13033 /* 32821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13034 /* 32825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13035 /* 32829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13036 /* 32833 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13037 /* 32837 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8061:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13038 /* 32837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
13039 /* 32840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13040 /* 32842 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13041 /* 32844 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13042 /* 32846 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13043 /* 32848 */ GIR_RootConstrainSelectedInstOperands,
13044 /* 32849 */ // GIR_Coverage, 586,
13045 /* 32849 */ GIR_EraseRootFromParent_Done,
13046 /* 32850 */ // Label 920: @32850
13047 /* 32850 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(32904), // Rule ID 587 //
13048 /* 32855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13049 /* 32858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
13050 /* 32863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13051 /* 32866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13052 /* 32869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
13053 /* 32872 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
13054 /* 32875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13055 /* 32879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13056 /* 32883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13057 /* 32887 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13058 /* 32891 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8059:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
13059 /* 32891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
13060 /* 32894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13061 /* 32896 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13062 /* 32898 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13063 /* 32900 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13064 /* 32902 */ GIR_RootConstrainSelectedInstOperands,
13065 /* 32903 */ // GIR_Coverage, 587,
13066 /* 32903 */ GIR_EraseRootFromParent_Done,
13067 /* 32904 */ // Label 921: @32904
13068 /* 32904 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(32958), // Rule ID 682 //
13069 /* 32909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13070 /* 32912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
13071 /* 32917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13072 /* 32920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13073 /* 32923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13074 /* 32926 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13075 /* 32929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13076 /* 32933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13077 /* 32937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13078 /* 32941 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13079 /* 32945 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8179:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13080 /* 32945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
13081 /* 32948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13082 /* 32950 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13083 /* 32952 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13084 /* 32954 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13085 /* 32956 */ GIR_RootConstrainSelectedInstOperands,
13086 /* 32957 */ // GIR_Coverage, 682,
13087 /* 32957 */ GIR_EraseRootFromParent_Done,
13088 /* 32958 */ // Label 922: @32958
13089 /* 32958 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(33012), // Rule ID 683 //
13090 /* 32963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13091 /* 32966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
13092 /* 32971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13093 /* 32974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13094 /* 32977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13095 /* 32980 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13096 /* 32983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13097 /* 32987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13098 /* 32991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13099 /* 32995 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13100 /* 32999 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8180:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13101 /* 32999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
13102 /* 33002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13103 /* 33004 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13104 /* 33006 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13105 /* 33008 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13106 /* 33010 */ GIR_RootConstrainSelectedInstOperands,
13107 /* 33011 */ // GIR_Coverage, 683,
13108 /* 33011 */ GIR_EraseRootFromParent_Done,
13109 /* 33012 */ // Label 923: @33012
13110 /* 33012 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(33066), // Rule ID 684 //
13111 /* 33017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13112 /* 33020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
13113 /* 33025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13114 /* 33028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13115 /* 33031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13116 /* 33034 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13117 /* 33037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13118 /* 33041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13119 /* 33045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13120 /* 33049 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13121 /* 33053 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8178:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13122 /* 33053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
13123 /* 33056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13124 /* 33058 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13125 /* 33060 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13126 /* 33062 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13127 /* 33064 */ GIR_RootConstrainSelectedInstOperands,
13128 /* 33065 */ // GIR_Coverage, 684,
13129 /* 33065 */ GIR_EraseRootFromParent_Done,
13130 /* 33066 */ // Label 924: @33066
13131 /* 33066 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(33120), // Rule ID 685 //
13132 /* 33071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13133 /* 33074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
13134 /* 33079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13135 /* 33082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13136 /* 33085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13137 /* 33088 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13138 /* 33091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13139 /* 33095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13140 /* 33099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13141 /* 33103 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13142 /* 33107 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8182:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13143 /* 33107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
13144 /* 33110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13145 /* 33112 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13146 /* 33114 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13147 /* 33116 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13148 /* 33118 */ GIR_RootConstrainSelectedInstOperands,
13149 /* 33119 */ // GIR_Coverage, 685,
13150 /* 33119 */ GIR_EraseRootFromParent_Done,
13151 /* 33120 */ // Label 925: @33120
13152 /* 33120 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(33174), // Rule ID 686 //
13153 /* 33125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13154 /* 33128 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
13155 /* 33133 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13156 /* 33136 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13157 /* 33139 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13158 /* 33142 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13159 /* 33145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13160 /* 33149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13161 /* 33153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13162 /* 33157 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13163 /* 33161 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8183:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13164 /* 33161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
13165 /* 33164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13166 /* 33166 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13167 /* 33168 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13168 /* 33170 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13169 /* 33172 */ GIR_RootConstrainSelectedInstOperands,
13170 /* 33173 */ // GIR_Coverage, 686,
13171 /* 33173 */ GIR_EraseRootFromParent_Done,
13172 /* 33174 */ // Label 926: @33174
13173 /* 33174 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(33228), // Rule ID 687 //
13174 /* 33179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13175 /* 33182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
13176 /* 33187 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13177 /* 33190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13178 /* 33193 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13179 /* 33196 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13180 /* 33199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13181 /* 33203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13182 /* 33207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13183 /* 33211 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13184 /* 33215 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8181:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13185 /* 33215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
13186 /* 33218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13187 /* 33220 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13188 /* 33222 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13189 /* 33224 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13190 /* 33226 */ GIR_RootConstrainSelectedInstOperands,
13191 /* 33227 */ // GIR_Coverage, 687,
13192 /* 33227 */ GIR_EraseRootFromParent_Done,
13193 /* 33228 */ // Label 927: @33228
13194 /* 33228 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(33282), // Rule ID 688 //
13195 /* 33233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13196 /* 33236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
13197 /* 33241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13198 /* 33244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13199 /* 33247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13200 /* 33250 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13201 /* 33253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13202 /* 33257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13203 /* 33261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13204 /* 33265 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13205 /* 33269 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8199:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13206 /* 33269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
13207 /* 33272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13208 /* 33274 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13209 /* 33276 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13210 /* 33278 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13211 /* 33280 */ GIR_RootConstrainSelectedInstOperands,
13212 /* 33281 */ // GIR_Coverage, 688,
13213 /* 33281 */ GIR_EraseRootFromParent_Done,
13214 /* 33282 */ // Label 928: @33282
13215 /* 33282 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(33336), // Rule ID 689 //
13216 /* 33287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13217 /* 33290 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
13218 /* 33295 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13219 /* 33298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13220 /* 33301 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13221 /* 33304 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13222 /* 33307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13223 /* 33311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13224 /* 33315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13225 /* 33319 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13226 /* 33323 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8200:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13227 /* 33323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
13228 /* 33326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13229 /* 33328 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13230 /* 33330 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13231 /* 33332 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13232 /* 33334 */ GIR_RootConstrainSelectedInstOperands,
13233 /* 33335 */ // GIR_Coverage, 689,
13234 /* 33335 */ GIR_EraseRootFromParent_Done,
13235 /* 33336 */ // Label 929: @33336
13236 /* 33336 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(33390), // Rule ID 690 //
13237 /* 33341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13238 /* 33344 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
13239 /* 33349 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13240 /* 33352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13241 /* 33355 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13242 /* 33358 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13243 /* 33361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13244 /* 33365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13245 /* 33369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13246 /* 33373 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13247 /* 33377 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8198:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13248 /* 33377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
13249 /* 33380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13250 /* 33382 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13251 /* 33384 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13252 /* 33386 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13253 /* 33388 */ GIR_RootConstrainSelectedInstOperands,
13254 /* 33389 */ // GIR_Coverage, 690,
13255 /* 33389 */ GIR_EraseRootFromParent_Done,
13256 /* 33390 */ // Label 930: @33390
13257 /* 33390 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(33444), // Rule ID 691 //
13258 /* 33395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13259 /* 33398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
13260 /* 33403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13261 /* 33406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13262 /* 33409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13263 /* 33412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13264 /* 33415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13265 /* 33419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13266 /* 33423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13267 /* 33427 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13268 /* 33431 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8202:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13269 /* 33431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
13270 /* 33434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13271 /* 33436 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13272 /* 33438 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13273 /* 33440 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13274 /* 33442 */ GIR_RootConstrainSelectedInstOperands,
13275 /* 33443 */ // GIR_Coverage, 691,
13276 /* 33443 */ GIR_EraseRootFromParent_Done,
13277 /* 33444 */ // Label 931: @33444
13278 /* 33444 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(33498), // Rule ID 692 //
13279 /* 33449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13280 /* 33452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
13281 /* 33457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13282 /* 33460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13283 /* 33463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13284 /* 33466 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13285 /* 33469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13286 /* 33473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13287 /* 33477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13288 /* 33481 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13289 /* 33485 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13290 /* 33485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
13291 /* 33488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13292 /* 33490 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13293 /* 33492 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13294 /* 33494 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13295 /* 33496 */ GIR_RootConstrainSelectedInstOperands,
13296 /* 33497 */ // GIR_Coverage, 692,
13297 /* 33497 */ GIR_EraseRootFromParent_Done,
13298 /* 33498 */ // Label 932: @33498
13299 /* 33498 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(33552), // Rule ID 693 //
13300 /* 33503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13301 /* 33506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
13302 /* 33511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13303 /* 33514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13304 /* 33517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13305 /* 33520 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13306 /* 33523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13307 /* 33527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13308 /* 33531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13309 /* 33535 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13310 /* 33539 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8201:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13311 /* 33539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
13312 /* 33542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13313 /* 33544 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13314 /* 33546 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13315 /* 33548 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13316 /* 33550 */ GIR_RootConstrainSelectedInstOperands,
13317 /* 33551 */ // GIR_Coverage, 693,
13318 /* 33551 */ GIR_EraseRootFromParent_Done,
13319 /* 33552 */ // Label 933: @33552
13320 /* 33552 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(33606), // Rule ID 860 //
13321 /* 33557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13322 /* 33560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
13323 /* 33565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13324 /* 33568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13325 /* 33571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13326 /* 33574 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13327 /* 33577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13328 /* 33581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13329 /* 33585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13330 /* 33589 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13331 /* 33593 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8369:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13332 /* 33593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
13333 /* 33596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13334 /* 33598 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13335 /* 33600 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13336 /* 33602 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13337 /* 33604 */ GIR_RootConstrainSelectedInstOperands,
13338 /* 33605 */ // GIR_Coverage, 860,
13339 /* 33605 */ GIR_EraseRootFromParent_Done,
13340 /* 33606 */ // Label 934: @33606
13341 /* 33606 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(33660), // Rule ID 861 //
13342 /* 33611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13343 /* 33614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
13344 /* 33619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13345 /* 33622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13346 /* 33625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13347 /* 33628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13348 /* 33631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13349 /* 33635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13350 /* 33639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13351 /* 33643 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13352 /* 33647 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8370:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13353 /* 33647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
13354 /* 33650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13355 /* 33652 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13356 /* 33654 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13357 /* 33656 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13358 /* 33658 */ GIR_RootConstrainSelectedInstOperands,
13359 /* 33659 */ // GIR_Coverage, 861,
13360 /* 33659 */ GIR_EraseRootFromParent_Done,
13361 /* 33660 */ // Label 935: @33660
13362 /* 33660 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(33714), // Rule ID 862 //
13363 /* 33665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13364 /* 33668 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
13365 /* 33673 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13366 /* 33676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13367 /* 33679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13368 /* 33682 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13369 /* 33685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13370 /* 33689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13371 /* 33693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13372 /* 33697 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13373 /* 33701 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8371:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13374 /* 33701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
13375 /* 33704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13376 /* 33706 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13377 /* 33708 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13378 /* 33710 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13379 /* 33712 */ GIR_RootConstrainSelectedInstOperands,
13380 /* 33713 */ // GIR_Coverage, 862,
13381 /* 33713 */ GIR_EraseRootFromParent_Done,
13382 /* 33714 */ // Label 936: @33714
13383 /* 33714 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(33768), // Rule ID 863 //
13384 /* 33719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13385 /* 33722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
13386 /* 33727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13387 /* 33730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13388 /* 33733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13389 /* 33736 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13390 /* 33739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13391 /* 33743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13392 /* 33747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13393 /* 33751 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13394 /* 33755 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8372:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13395 /* 33755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
13396 /* 33758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13397 /* 33760 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13398 /* 33762 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13399 /* 33764 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13400 /* 33766 */ GIR_RootConstrainSelectedInstOperands,
13401 /* 33767 */ // GIR_Coverage, 863,
13402 /* 33767 */ GIR_EraseRootFromParent_Done,
13403 /* 33768 */ // Label 937: @33768
13404 /* 33768 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(33822), // Rule ID 916 //
13405 /* 33773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13406 /* 33776 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
13407 /* 33781 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13408 /* 33784 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13409 /* 33787 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13410 /* 33790 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13411 /* 33793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13412 /* 33797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13413 /* 33801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13414 /* 33805 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13415 /* 33809 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8433:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13416 /* 33809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
13417 /* 33812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13418 /* 33814 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13419 /* 33816 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13420 /* 33818 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13421 /* 33820 */ GIR_RootConstrainSelectedInstOperands,
13422 /* 33821 */ // GIR_Coverage, 916,
13423 /* 33821 */ GIR_EraseRootFromParent_Done,
13424 /* 33822 */ // Label 938: @33822
13425 /* 33822 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(33876), // Rule ID 917 //
13426 /* 33827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13427 /* 33830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
13428 /* 33835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13429 /* 33838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13430 /* 33841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13431 /* 33844 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13432 /* 33847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13433 /* 33851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13434 /* 33855 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13435 /* 33859 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13436 /* 33863 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8434:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13437 /* 33863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
13438 /* 33866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13439 /* 33868 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13440 /* 33870 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13441 /* 33872 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13442 /* 33874 */ GIR_RootConstrainSelectedInstOperands,
13443 /* 33875 */ // GIR_Coverage, 917,
13444 /* 33875 */ GIR_EraseRootFromParent_Done,
13445 /* 33876 */ // Label 939: @33876
13446 /* 33876 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(33930), // Rule ID 918 //
13447 /* 33881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13448 /* 33884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
13449 /* 33889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13450 /* 33892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13451 /* 33895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13452 /* 33898 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13453 /* 33901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13454 /* 33905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13455 /* 33909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13456 /* 33913 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13457 /* 33917 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8435:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13458 /* 33917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
13459 /* 33920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13460 /* 33922 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13461 /* 33924 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13462 /* 33926 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13463 /* 33928 */ GIR_RootConstrainSelectedInstOperands,
13464 /* 33929 */ // GIR_Coverage, 918,
13465 /* 33929 */ GIR_EraseRootFromParent_Done,
13466 /* 33930 */ // Label 940: @33930
13467 /* 33930 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(33984), // Rule ID 919 //
13468 /* 33935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13469 /* 33938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
13470 /* 33943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13471 /* 33946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13472 /* 33949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13473 /* 33952 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13474 /* 33955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13475 /* 33959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13476 /* 33963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13477 /* 33967 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13478 /* 33971 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8436:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13479 /* 33971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
13480 /* 33974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13481 /* 33976 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13482 /* 33978 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13483 /* 33980 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13484 /* 33982 */ GIR_RootConstrainSelectedInstOperands,
13485 /* 33983 */ // GIR_Coverage, 919,
13486 /* 33983 */ GIR_EraseRootFromParent_Done,
13487 /* 33984 */ // Label 941: @33984
13488 /* 33984 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(34038), // Rule ID 973 //
13489 /* 33989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13490 /* 33992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
13491 /* 33997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
13492 /* 34000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
13493 /* 34003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13494 /* 34006 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13495 /* 34009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13496 /* 34013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13497 /* 34017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13498 /* 34021 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13499 /* 34025 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8537:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13500 /* 34025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
13501 /* 34028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13502 /* 34030 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13503 /* 34032 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13504 /* 34034 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13505 /* 34036 */ GIR_RootConstrainSelectedInstOperands,
13506 /* 34037 */ // GIR_Coverage, 973,
13507 /* 34037 */ GIR_EraseRootFromParent_Done,
13508 /* 34038 */ // Label 942: @34038
13509 /* 34038 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(34092), // Rule ID 974 //
13510 /* 34043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13511 /* 34046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
13512 /* 34051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13513 /* 34054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13514 /* 34057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13515 /* 34060 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13516 /* 34063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13517 /* 34067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13518 /* 34071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13519 /* 34075 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13520 /* 34079 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8539:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13521 /* 34079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
13522 /* 34082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13523 /* 34084 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13524 /* 34086 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13525 /* 34088 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13526 /* 34090 */ GIR_RootConstrainSelectedInstOperands,
13527 /* 34091 */ // GIR_Coverage, 974,
13528 /* 34091 */ GIR_EraseRootFromParent_Done,
13529 /* 34092 */ // Label 943: @34092
13530 /* 34092 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(34146), // Rule ID 975 //
13531 /* 34097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13532 /* 34100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
13533 /* 34105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13534 /* 34108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13535 /* 34111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13536 /* 34114 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13537 /* 34117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13538 /* 34121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13539 /* 34125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13540 /* 34129 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13541 /* 34133 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8540:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13542 /* 34133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
13543 /* 34136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13544 /* 34138 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13545 /* 34140 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13546 /* 34142 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13547 /* 34144 */ GIR_RootConstrainSelectedInstOperands,
13548 /* 34145 */ // GIR_Coverage, 975,
13549 /* 34145 */ GIR_EraseRootFromParent_Done,
13550 /* 34146 */ // Label 944: @34146
13551 /* 34146 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(34200), // Rule ID 976 //
13552 /* 34151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13553 /* 34154 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
13554 /* 34159 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13555 /* 34162 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13556 /* 34165 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
13557 /* 34168 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13558 /* 34171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13559 /* 34175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13560 /* 34179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13561 /* 34183 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13562 /* 34187 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8538:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13563 /* 34187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
13564 /* 34190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13565 /* 34192 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13566 /* 34194 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13567 /* 34196 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13568 /* 34198 */ GIR_RootConstrainSelectedInstOperands,
13569 /* 34199 */ // GIR_Coverage, 976,
13570 /* 34199 */ GIR_EraseRootFromParent_Done,
13571 /* 34200 */ // Label 945: @34200
13572 /* 34200 */ GIM_Reject,
13573 /* 34201 */ // Label 899: @34201
13574 /* 34201 */ GIM_Reject,
13575 /* 34202 */ // Label 30: @34202
13576 /* 34202 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(34233), // Rule ID 378 //
13577 /* 34207 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
13578 /* 34210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
13579 /* 34215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13580 /* 34218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13581 /* 34222 */ // (intrinsic_w_chain:{ *:[i32] } 8084:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
13582 /* 34222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
13583 /* 34225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13584 /* 34227 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13585 /* 34231 */ GIR_RootConstrainSelectedInstOperands,
13586 /* 34232 */ // GIR_Coverage, 378,
13587 /* 34232 */ GIR_EraseRootFromParent_Done,
13588 /* 34233 */ // Label 946: @34233
13589 /* 34233 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(35170),
13590 /* 34238 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
13591 /* 34241 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(34282), // Rule ID 465 //
13592 /* 34246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13593 /* 34249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
13594 /* 34254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13595 /* 34257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13596 /* 34261 */ // MIs[0] mask
13597 /* 34261 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13598 /* 34264 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
13599 /* 34269 */ // (intrinsic_w_chain:{ *:[i32] } 8511:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
13600 /* 34269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
13601 /* 34272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13602 /* 34274 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13603 /* 34276 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13604 /* 34280 */ GIR_RootConstrainSelectedInstOperands,
13605 /* 34281 */ // GIR_Coverage, 465,
13606 /* 34281 */ GIR_EraseRootFromParent_Done,
13607 /* 34282 */ // Label 948: @34282
13608 /* 34282 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(34318), // Rule ID 1310 //
13609 /* 34287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13610 /* 34290 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
13611 /* 34295 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13612 /* 34298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13613 /* 34302 */ // MIs[0] mask
13614 /* 34302 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13615 /* 34305 */ // (intrinsic_w_chain:{ *:[i32] } 8511:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
13616 /* 34305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
13617 /* 34308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13618 /* 34310 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13619 /* 34312 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13620 /* 34316 */ GIR_RootConstrainSelectedInstOperands,
13621 /* 34317 */ // GIR_Coverage, 1310,
13622 /* 34317 */ GIR_EraseRootFromParent_Done,
13623 /* 34318 */ // Label 949: @34318
13624 /* 34318 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(34359), // Rule ID 466 //
13625 /* 34323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
13626 /* 34326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
13627 /* 34331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13628 /* 34334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13629 /* 34338 */ // MIs[0] mask
13630 /* 34338 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13631 /* 34341 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
13632 /* 34346 */ // (intrinsic_void 8640:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
13633 /* 34346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
13634 /* 34349 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13635 /* 34351 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13636 /* 34353 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13637 /* 34357 */ GIR_RootConstrainSelectedInstOperands,
13638 /* 34358 */ // GIR_Coverage, 466,
13639 /* 34358 */ GIR_EraseRootFromParent_Done,
13640 /* 34359 */ // Label 950: @34359
13641 /* 34359 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(34395), // Rule ID 1321 //
13642 /* 34364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13643 /* 34367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
13644 /* 34372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13645 /* 34375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13646 /* 34379 */ // MIs[0] mask
13647 /* 34379 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13648 /* 34382 */ // (intrinsic_void 8640:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
13649 /* 34382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
13650 /* 34385 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
13651 /* 34387 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13652 /* 34389 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13653 /* 34393 */ GIR_RootConstrainSelectedInstOperands,
13654 /* 34394 */ // GIR_Coverage, 1321,
13655 /* 34394 */ GIR_EraseRootFromParent_Done,
13656 /* 34395 */ // Label 951: @34395
13657 /* 34395 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(34438), // Rule ID 387 //
13658 /* 34400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13659 /* 34403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
13660 /* 34408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13661 /* 34411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13662 /* 34414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13663 /* 34418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13664 /* 34422 */ // (intrinsic_w_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
13665 /* 34422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
13666 /* 34425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13667 /* 34427 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13668 /* 34429 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13669 /* 34432 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13670 /* 34436 */ GIR_RootConstrainSelectedInstOperands,
13671 /* 34437 */ // GIR_Coverage, 387,
13672 /* 34437 */ GIR_EraseRootFromParent_Done,
13673 /* 34438 */ // Label 952: @34438
13674 /* 34438 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(34481), // Rule ID 388 //
13675 /* 34443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13676 /* 34446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13677 /* 34451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13678 /* 34454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13679 /* 34457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13680 /* 34461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13681 /* 34465 */ // (intrinsic_w_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
13682 /* 34465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
13683 /* 34468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13684 /* 34470 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13685 /* 34472 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13686 /* 34475 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13687 /* 34479 */ GIR_RootConstrainSelectedInstOperands,
13688 /* 34480 */ // GIR_Coverage, 388,
13689 /* 34480 */ GIR_EraseRootFromParent_Done,
13690 /* 34481 */ // Label 953: @34481
13691 /* 34481 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(34524), // Rule ID 474 //
13692 /* 34486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13693 /* 34489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13694 /* 34494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13695 /* 34497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13696 /* 34500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13697 /* 34504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13698 /* 34508 */ // (intrinsic_w_chain:{ *:[v4i8] } 7973:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
13699 /* 34508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
13700 /* 34511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13701 /* 34513 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13702 /* 34515 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13703 /* 34518 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13704 /* 34522 */ GIR_RootConstrainSelectedInstOperands,
13705 /* 34523 */ // GIR_Coverage, 474,
13706 /* 34523 */ GIR_EraseRootFromParent_Done,
13707 /* 34524 */ // Label 954: @34524
13708 /* 34524 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(34567), // Rule ID 1253 //
13709 /* 34529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13710 /* 34532 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
13711 /* 34537 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13712 /* 34540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13713 /* 34543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13714 /* 34547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13715 /* 34551 */ // (intrinsic_w_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
13716 /* 34551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
13717 /* 34554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13718 /* 34556 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13719 /* 34558 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13720 /* 34561 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13721 /* 34565 */ GIR_RootConstrainSelectedInstOperands,
13722 /* 34566 */ // GIR_Coverage, 1253,
13723 /* 34566 */ GIR_EraseRootFromParent_Done,
13724 /* 34567 */ // Label 955: @34567
13725 /* 34567 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(34610), // Rule ID 1254 //
13726 /* 34572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13727 /* 34575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13728 /* 34580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13729 /* 34583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13730 /* 34586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13731 /* 34590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13732 /* 34594 */ // (intrinsic_w_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
13733 /* 34594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
13734 /* 34597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13735 /* 34599 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13736 /* 34601 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13737 /* 34604 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13738 /* 34608 */ GIR_RootConstrainSelectedInstOperands,
13739 /* 34609 */ // GIR_Coverage, 1254,
13740 /* 34609 */ GIR_EraseRootFromParent_Done,
13741 /* 34610 */ // Label 956: @34610
13742 /* 34610 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(34653), // Rule ID 1334 //
13743 /* 34615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13744 /* 34618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13745 /* 34623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13746 /* 34626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13747 /* 34629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13748 /* 34633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13749 /* 34637 */ // (intrinsic_w_chain:{ *:[v4i8] } 7973:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
13750 /* 34637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
13751 /* 34640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13752 /* 34642 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13753 /* 34644 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13754 /* 34647 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13755 /* 34651 */ GIR_RootConstrainSelectedInstOperands,
13756 /* 34652 */ // GIR_Coverage, 1334,
13757 /* 34652 */ GIR_EraseRootFromParent_Done,
13758 /* 34653 */ // Label 957: @34653
13759 /* 34653 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(34696), // Rule ID 441 //
13760 /* 34658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13761 /* 34661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13762 /* 34666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13763 /* 34669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13764 /* 34672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13765 /* 34676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13766 /* 34680 */ // (intrinsic_void 8150:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13767 /* 34680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
13768 /* 34683 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13769 /* 34685 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13770 /* 34687 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13771 /* 34690 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13772 /* 34694 */ GIR_RootConstrainSelectedInstOperands,
13773 /* 34695 */ // GIR_Coverage, 441,
13774 /* 34695 */ GIR_EraseRootFromParent_Done,
13775 /* 34696 */ // Label 958: @34696
13776 /* 34696 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(34739), // Rule ID 442 //
13777 /* 34701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13778 /* 34704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13779 /* 34709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13780 /* 34712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13781 /* 34715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13782 /* 34719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13783 /* 34723 */ // (intrinsic_void 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13784 /* 34723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
13785 /* 34726 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13786 /* 34728 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13787 /* 34730 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13788 /* 34733 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13789 /* 34737 */ GIR_RootConstrainSelectedInstOperands,
13790 /* 34738 */ // GIR_Coverage, 442,
13791 /* 34738 */ GIR_EraseRootFromParent_Done,
13792 /* 34739 */ // Label 959: @34739
13793 /* 34739 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(34782), // Rule ID 443 //
13794 /* 34744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13795 /* 34747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13796 /* 34752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13797 /* 34755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13798 /* 34758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13799 /* 34762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13800 /* 34766 */ // (intrinsic_void 8151:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13801 /* 34766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
13802 /* 34769 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13803 /* 34771 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13804 /* 34773 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13805 /* 34776 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13806 /* 34780 */ GIR_RootConstrainSelectedInstOperands,
13807 /* 34781 */ // GIR_Coverage, 443,
13808 /* 34781 */ GIR_EraseRootFromParent_Done,
13809 /* 34782 */ // Label 960: @34782
13810 /* 34782 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(34825), // Rule ID 447 //
13811 /* 34787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13812 /* 34790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13813 /* 34795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13814 /* 34798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13815 /* 34801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13816 /* 34805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13817 /* 34809 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13818 /* 34809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
13819 /* 34812 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13820 /* 34814 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13821 /* 34816 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13822 /* 34819 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13823 /* 34823 */ GIR_RootConstrainSelectedInstOperands,
13824 /* 34824 */ // GIR_Coverage, 447,
13825 /* 34824 */ GIR_EraseRootFromParent_Done,
13826 /* 34825 */ // Label 961: @34825
13827 /* 34825 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(34868), // Rule ID 448 //
13828 /* 34830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13829 /* 34833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13830 /* 34838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13831 /* 34841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13832 /* 34844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13833 /* 34848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13834 /* 34852 */ // (intrinsic_void 8143:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13835 /* 34852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
13836 /* 34855 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13837 /* 34857 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13838 /* 34859 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13839 /* 34862 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13840 /* 34866 */ GIR_RootConstrainSelectedInstOperands,
13841 /* 34867 */ // GIR_Coverage, 448,
13842 /* 34867 */ GIR_EraseRootFromParent_Done,
13843 /* 34868 */ // Label 962: @34868
13844 /* 34868 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(34911), // Rule ID 449 //
13845 /* 34873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13846 /* 34876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13847 /* 34881 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13848 /* 34884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13849 /* 34887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13850 /* 34891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13851 /* 34895 */ // (intrinsic_void 8142:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13852 /* 34895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
13853 /* 34898 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13854 /* 34900 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13855 /* 34902 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13856 /* 34905 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13857 /* 34909 */ GIR_RootConstrainSelectedInstOperands,
13858 /* 34910 */ // GIR_Coverage, 449,
13859 /* 34910 */ GIR_EraseRootFromParent_Done,
13860 /* 34911 */ // Label 963: @34911
13861 /* 34911 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(34954), // Rule ID 1325 //
13862 /* 34916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13863 /* 34919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13864 /* 34924 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13865 /* 34927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13866 /* 34930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13867 /* 34934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13868 /* 34938 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13869 /* 34938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
13870 /* 34941 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13871 /* 34943 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13872 /* 34945 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13873 /* 34948 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13874 /* 34952 */ GIR_RootConstrainSelectedInstOperands,
13875 /* 34953 */ // GIR_Coverage, 1325,
13876 /* 34953 */ GIR_EraseRootFromParent_Done,
13877 /* 34954 */ // Label 964: @34954
13878 /* 34954 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(34997), // Rule ID 1326 //
13879 /* 34959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13880 /* 34962 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13881 /* 34967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13882 /* 34970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13883 /* 34973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13884 /* 34977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13885 /* 34981 */ // (intrinsic_void 8143:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13886 /* 34981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
13887 /* 34984 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13888 /* 34986 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13889 /* 34988 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13890 /* 34991 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13891 /* 34995 */ GIR_RootConstrainSelectedInstOperands,
13892 /* 34996 */ // GIR_Coverage, 1326,
13893 /* 34996 */ GIR_EraseRootFromParent_Done,
13894 /* 34997 */ // Label 965: @34997
13895 /* 34997 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(35040), // Rule ID 1327 //
13896 /* 35002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13897 /* 35005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13898 /* 35010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13899 /* 35013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13900 /* 35016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13901 /* 35020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13902 /* 35024 */ // (intrinsic_void 8142:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13903 /* 35024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
13904 /* 35027 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13905 /* 35029 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13906 /* 35031 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13907 /* 35034 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13908 /* 35038 */ GIR_RootConstrainSelectedInstOperands,
13909 /* 35039 */ // GIR_Coverage, 1327,
13910 /* 35039 */ GIR_EraseRootFromParent_Done,
13911 /* 35040 */ // Label 966: @35040
13912 /* 35040 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(35083), // Rule ID 1331 //
13913 /* 35045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13914 /* 35048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13915 /* 35053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13916 /* 35056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13917 /* 35059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13918 /* 35063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13919 /* 35067 */ // (intrinsic_void 8150:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13920 /* 35067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
13921 /* 35070 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13922 /* 35072 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13923 /* 35074 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13924 /* 35077 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13925 /* 35081 */ GIR_RootConstrainSelectedInstOperands,
13926 /* 35082 */ // GIR_Coverage, 1331,
13927 /* 35082 */ GIR_EraseRootFromParent_Done,
13928 /* 35083 */ // Label 967: @35083
13929 /* 35083 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(35126), // Rule ID 1332 //
13930 /* 35088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13931 /* 35091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13932 /* 35096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13933 /* 35099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13934 /* 35102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13935 /* 35106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13936 /* 35110 */ // (intrinsic_void 8152:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13937 /* 35110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13938 /* 35113 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13939 /* 35115 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13940 /* 35117 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13941 /* 35120 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13942 /* 35124 */ GIR_RootConstrainSelectedInstOperands,
13943 /* 35125 */ // GIR_Coverage, 1332,
13944 /* 35125 */ GIR_EraseRootFromParent_Done,
13945 /* 35126 */ // Label 968: @35126
13946 /* 35126 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35169), // Rule ID 1333 //
13947 /* 35131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13948 /* 35134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13949 /* 35139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13950 /* 35142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13951 /* 35145 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13952 /* 35149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13953 /* 35153 */ // (intrinsic_void 8151:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13954 /* 35153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13955 /* 35156 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13956 /* 35158 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13957 /* 35160 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13958 /* 35163 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13959 /* 35167 */ GIR_RootConstrainSelectedInstOperands,
13960 /* 35168 */ // GIR_Coverage, 1333,
13961 /* 35168 */ GIR_EraseRootFromParent_Done,
13962 /* 35169 */ // Label 969: @35169
13963 /* 35169 */ GIM_Reject,
13964 /* 35170 */ // Label 947: @35170
13965 /* 35170 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(39295),
13966 /* 35175 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
13967 /* 35178 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(35242), // Rule ID 406 //
13968 /* 35183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13969 /* 35186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13970 /* 35191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13971 /* 35194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13972 /* 35197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13973 /* 35200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13974 /* 35204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13975 /* 35208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13976 /* 35212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13977 /* 35216 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13978 /* 35220 */ // MIs[1] Operand 1
13979 /* 35220 */ // No operand predicates
13980 /* 35220 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13981 /* 35222 */ // (intrinsic_w_chain:{ *:[v2i16] } 8528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13982 /* 35222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
13983 /* 35225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13984 /* 35227 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13985 /* 35229 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13986 /* 35232 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13987 /* 35235 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13988 /* 35240 */ GIR_RootConstrainSelectedInstOperands,
13989 /* 35241 */ // GIR_Coverage, 406,
13990 /* 35241 */ GIR_EraseRootFromParent_Done,
13991 /* 35242 */ // Label 971: @35242
13992 /* 35242 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35306), // Rule ID 411 //
13993 /* 35247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13994 /* 35250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13995 /* 35255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13996 /* 35258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13997 /* 35261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13998 /* 35264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13999 /* 35268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14000 /* 35272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14001 /* 35276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14002 /* 35280 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14003 /* 35284 */ // MIs[1] Operand 1
14004 /* 35284 */ // No operand predicates
14005 /* 35284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14006 /* 35286 */ // (intrinsic_w_chain:{ *:[i32] } 8529:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
14007 /* 35286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
14008 /* 35289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14009 /* 35291 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14010 /* 35293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
14011 /* 35296 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14012 /* 35299 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14013 /* 35304 */ GIR_RootConstrainSelectedInstOperands,
14014 /* 35305 */ // GIR_Coverage, 411,
14015 /* 35305 */ GIR_EraseRootFromParent_Done,
14016 /* 35306 */ // Label 972: @35306
14017 /* 35306 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(35370), // Rule ID 1262 //
14018 /* 35311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14019 /* 35314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14020 /* 35319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14021 /* 35322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14022 /* 35325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14023 /* 35328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14024 /* 35332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14025 /* 35336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14026 /* 35340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14027 /* 35344 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
14028 /* 35348 */ // MIs[1] Operand 1
14029 /* 35348 */ // No operand predicates
14030 /* 35348 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14031 /* 35350 */ // (intrinsic_w_chain:{ *:[v2i16] } 8528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
14032 /* 35350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
14033 /* 35353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14034 /* 35355 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14035 /* 35357 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
14036 /* 35360 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14037 /* 35363 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14038 /* 35368 */ GIR_RootConstrainSelectedInstOperands,
14039 /* 35369 */ // GIR_Coverage, 1262,
14040 /* 35369 */ GIR_EraseRootFromParent_Done,
14041 /* 35370 */ // Label 973: @35370
14042 /* 35370 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(35434), // Rule ID 1267 //
14043 /* 35375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14044 /* 35378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14045 /* 35383 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14046 /* 35386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14047 /* 35389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14048 /* 35392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14049 /* 35396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14050 /* 35400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14051 /* 35404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14052 /* 35408 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14053 /* 35412 */ // MIs[1] Operand 1
14054 /* 35412 */ // No operand predicates
14055 /* 35412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14056 /* 35414 */ // (intrinsic_w_chain:{ *:[i32] } 8529:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
14057 /* 35414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
14058 /* 35417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14059 /* 35419 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14060 /* 35421 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
14061 /* 35424 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14062 /* 35427 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14063 /* 35432 */ GIR_RootConstrainSelectedInstOperands,
14064 /* 35433 */ // GIR_Coverage, 1267,
14065 /* 35433 */ GIR_EraseRootFromParent_Done,
14066 /* 35434 */ // Label 974: @35434
14067 /* 35434 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(35489), // Rule ID 2069 //
14068 /* 35439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14069 /* 35442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14070 /* 35447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14071 /* 35450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14072 /* 35453 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14073 /* 35456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14074 /* 35460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14075 /* 35464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14076 /* 35468 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
14077 /* 35472 */ // MIs[1] Operand 1
14078 /* 35472 */ // No operand predicates
14079 /* 35472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14080 /* 35474 */ // (intrinsic_w_chain:{ *:[v2i16] } 8526:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
14081 /* 35474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
14082 /* 35477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14083 /* 35479 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14084 /* 35481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14085 /* 35484 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14086 /* 35487 */ GIR_RootConstrainSelectedInstOperands,
14087 /* 35488 */ // GIR_Coverage, 2069,
14088 /* 35488 */ GIR_EraseRootFromParent_Done,
14089 /* 35489 */ // Label 975: @35489
14090 /* 35489 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(35544), // Rule ID 2075 //
14091 /* 35494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14092 /* 35497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14093 /* 35502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14094 /* 35505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14095 /* 35508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14096 /* 35511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14097 /* 35515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14098 /* 35519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14099 /* 35523 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
14100 /* 35527 */ // MIs[1] Operand 1
14101 /* 35527 */ // No operand predicates
14102 /* 35527 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14103 /* 35529 */ // (intrinsic_w_chain:{ *:[v4i8] } 8527:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
14104 /* 35529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
14105 /* 35532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14106 /* 35534 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14107 /* 35536 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14108 /* 35539 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14109 /* 35542 */ GIR_RootConstrainSelectedInstOperands,
14110 /* 35543 */ // GIR_Coverage, 2075,
14111 /* 35543 */ GIR_EraseRootFromParent_Done,
14112 /* 35544 */ // Label 976: @35544
14113 /* 35544 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(35596), // Rule ID 383 //
14114 /* 35549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14115 /* 35552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
14116 /* 35557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14117 /* 35560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14118 /* 35563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14119 /* 35566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14120 /* 35570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14121 /* 35574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14122 /* 35578 */ // (intrinsic_w_chain:{ *:[i32] } 7981:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14123 /* 35578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
14124 /* 35581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14125 /* 35583 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14126 /* 35585 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14127 /* 35587 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14128 /* 35590 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14129 /* 35594 */ GIR_RootConstrainSelectedInstOperands,
14130 /* 35595 */ // GIR_Coverage, 383,
14131 /* 35595 */ GIR_EraseRootFromParent_Done,
14132 /* 35596 */ // Label 977: @35596
14133 /* 35596 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(35648), // Rule ID 384 //
14134 /* 35601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14135 /* 35604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14136 /* 35609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14137 /* 35612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14138 /* 35615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14139 /* 35618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14140 /* 35622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14141 /* 35626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14142 /* 35630 */ // (intrinsic_w_chain:{ *:[i32] } 8601:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14143 /* 35630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
14144 /* 35633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14145 /* 35635 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14146 /* 35637 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14147 /* 35639 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14148 /* 35642 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14149 /* 35646 */ GIR_RootConstrainSelectedInstOperands,
14150 /* 35647 */ // GIR_Coverage, 384,
14151 /* 35647 */ GIR_EraseRootFromParent_Done,
14152 /* 35648 */ // Label 978: @35648
14153 /* 35648 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(35700), // Rule ID 391 //
14154 /* 35653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14155 /* 35656 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14156 /* 35661 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14157 /* 35664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14158 /* 35667 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14159 /* 35670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14160 /* 35674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14161 /* 35678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14162 /* 35682 */ // (intrinsic_w_chain:{ *:[v2i16] } 8507:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14163 /* 35682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
14164 /* 35685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14165 /* 35687 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14166 /* 35689 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14167 /* 35691 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14168 /* 35694 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14169 /* 35698 */ GIR_RootConstrainSelectedInstOperands,
14170 /* 35699 */ // GIR_Coverage, 391,
14171 /* 35699 */ GIR_EraseRootFromParent_Done,
14172 /* 35700 */ // Label 979: @35700
14173 /* 35700 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(35752), // Rule ID 392 //
14174 /* 35705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14175 /* 35708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14176 /* 35713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14177 /* 35716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14178 /* 35719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14179 /* 35722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14180 /* 35726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14181 /* 35730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14182 /* 35734 */ // (intrinsic_w_chain:{ *:[v4i8] } 8508:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14183 /* 35734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
14184 /* 35737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14185 /* 35739 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14186 /* 35741 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14187 /* 35743 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14188 /* 35746 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14189 /* 35750 */ GIR_RootConstrainSelectedInstOperands,
14190 /* 35751 */ // GIR_Coverage, 392,
14191 /* 35751 */ GIR_EraseRootFromParent_Done,
14192 /* 35752 */ // Label 980: @35752
14193 /* 35752 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(35804), // Rule ID 403 //
14194 /* 35757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14195 /* 35760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14196 /* 35765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14197 /* 35768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14198 /* 35771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14199 /* 35774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14200 /* 35778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14201 /* 35782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14202 /* 35786 */ // (intrinsic_w_chain:{ *:[v4i8] } 8527:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14203 /* 35786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
14204 /* 35789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14205 /* 35791 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14206 /* 35793 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14207 /* 35795 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14208 /* 35798 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14209 /* 35802 */ GIR_RootConstrainSelectedInstOperands,
14210 /* 35803 */ // GIR_Coverage, 403,
14211 /* 35803 */ GIR_EraseRootFromParent_Done,
14212 /* 35804 */ // Label 981: @35804
14213 /* 35804 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(35856), // Rule ID 405 //
14214 /* 35809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14215 /* 35812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14216 /* 35817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14217 /* 35820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14218 /* 35823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14219 /* 35826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14220 /* 35830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14221 /* 35834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14222 /* 35838 */ // (intrinsic_w_chain:{ *:[v2i16] } 8526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14223 /* 35838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
14224 /* 35841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14225 /* 35843 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14226 /* 35845 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14227 /* 35847 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14228 /* 35850 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14229 /* 35854 */ GIR_RootConstrainSelectedInstOperands,
14230 /* 35855 */ // GIR_Coverage, 405,
14231 /* 35855 */ GIR_EraseRootFromParent_Done,
14232 /* 35856 */ // Label 982: @35856
14233 /* 35856 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(35908), // Rule ID 407 //
14234 /* 35861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14235 /* 35864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14236 /* 35869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14237 /* 35872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14238 /* 35875 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14239 /* 35878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14240 /* 35882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14241 /* 35886 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14242 /* 35890 */ // (intrinsic_w_chain:{ *:[v2i16] } 8528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14243 /* 35890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
14244 /* 35893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14245 /* 35895 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14246 /* 35897 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14247 /* 35899 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14248 /* 35902 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14249 /* 35906 */ GIR_RootConstrainSelectedInstOperands,
14250 /* 35907 */ // GIR_Coverage, 407,
14251 /* 35907 */ GIR_EraseRootFromParent_Done,
14252 /* 35908 */ // Label 983: @35908
14253 /* 35908 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(35960), // Rule ID 412 //
14254 /* 35913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14255 /* 35916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14256 /* 35921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14257 /* 35924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14258 /* 35927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14259 /* 35930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14260 /* 35934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14261 /* 35938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14262 /* 35942 */ // (intrinsic_w_chain:{ *:[i32] } 8529:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14263 /* 35942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
14264 /* 35945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14265 /* 35947 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14266 /* 35949 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14267 /* 35951 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14268 /* 35954 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14269 /* 35958 */ GIR_RootConstrainSelectedInstOperands,
14270 /* 35959 */ // GIR_Coverage, 412,
14271 /* 35959 */ GIR_EraseRootFromParent_Done,
14272 /* 35960 */ // Label 984: @35960
14273 /* 35960 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(36012), // Rule ID 415 //
14274 /* 35965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14275 /* 35968 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14276 /* 35973 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14277 /* 35976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14278 /* 35979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14279 /* 35982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14280 /* 35986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14281 /* 35990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14282 /* 35994 */ // (intrinsic_w_chain:{ *:[v2i16] } 8449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14283 /* 35994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
14284 /* 35997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14285 /* 35999 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14286 /* 36001 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14287 /* 36003 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14288 /* 36006 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14289 /* 36010 */ GIR_RootConstrainSelectedInstOperands,
14290 /* 36011 */ // GIR_Coverage, 415,
14291 /* 36011 */ GIR_EraseRootFromParent_Done,
14292 /* 36012 */ // Label 985: @36012
14293 /* 36012 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(36064), // Rule ID 416 //
14294 /* 36017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14295 /* 36020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14296 /* 36025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14297 /* 36028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14298 /* 36031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14299 /* 36034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14300 /* 36038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14301 /* 36042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14302 /* 36046 */ // (intrinsic_w_chain:{ *:[v2i16] } 8450:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14303 /* 36046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
14304 /* 36049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14305 /* 36051 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14306 /* 36053 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14307 /* 36055 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14308 /* 36058 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14309 /* 36062 */ GIR_RootConstrainSelectedInstOperands,
14310 /* 36063 */ // GIR_Coverage, 416,
14311 /* 36063 */ GIR_EraseRootFromParent_Done,
14312 /* 36064 */ // Label 986: @36064
14313 /* 36064 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(36116), // Rule ID 417 //
14314 /* 36069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14315 /* 36072 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14316 /* 36077 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14317 /* 36080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14318 /* 36083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14319 /* 36086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14320 /* 36090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14321 /* 36094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14322 /* 36098 */ // (intrinsic_w_chain:{ *:[i32] } 8447:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14323 /* 36098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
14324 /* 36101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14325 /* 36103 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14326 /* 36105 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14327 /* 36107 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14328 /* 36110 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14329 /* 36114 */ GIR_RootConstrainSelectedInstOperands,
14330 /* 36115 */ // GIR_Coverage, 417,
14331 /* 36115 */ GIR_EraseRootFromParent_Done,
14332 /* 36116 */ // Label 987: @36116
14333 /* 36116 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(36168), // Rule ID 418 //
14334 /* 36121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14335 /* 36124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14336 /* 36129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14337 /* 36132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14338 /* 36135 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14339 /* 36138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14340 /* 36142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14341 /* 36146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14342 /* 36150 */ // (intrinsic_w_chain:{ *:[i32] } 8448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14343 /* 36150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
14344 /* 36153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14345 /* 36155 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14346 /* 36157 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14347 /* 36159 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14348 /* 36162 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14349 /* 36166 */ GIR_RootConstrainSelectedInstOperands,
14350 /* 36167 */ // GIR_Coverage, 418,
14351 /* 36167 */ GIR_EraseRootFromParent_Done,
14352 /* 36168 */ // Label 988: @36168
14353 /* 36168 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(36220), // Rule ID 419 //
14354 /* 36173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14355 /* 36176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14356 /* 36181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14357 /* 36184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14358 /* 36187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14359 /* 36190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14360 /* 36194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14361 /* 36198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14362 /* 36202 */ // (intrinsic_w_chain:{ *:[v2i16] } 8451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14363 /* 36202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
14364 /* 36205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14365 /* 36207 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14366 /* 36209 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14367 /* 36211 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14368 /* 36214 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14369 /* 36218 */ GIR_RootConstrainSelectedInstOperands,
14370 /* 36219 */ // GIR_Coverage, 419,
14371 /* 36219 */ GIR_EraseRootFromParent_Done,
14372 /* 36220 */ // Label 989: @36220
14373 /* 36220 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(36269), // Rule ID 444 //
14374 /* 36225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14375 /* 36228 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14376 /* 36233 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14377 /* 36236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14378 /* 36239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14379 /* 36242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14380 /* 36246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14381 /* 36250 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14382 /* 36254 */ // (intrinsic_w_chain:{ *:[i32] } 8147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14383 /* 36254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
14384 /* 36257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14385 /* 36259 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14386 /* 36261 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14387 /* 36263 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14388 /* 36267 */ GIR_RootConstrainSelectedInstOperands,
14389 /* 36268 */ // GIR_Coverage, 444,
14390 /* 36268 */ GIR_EraseRootFromParent_Done,
14391 /* 36269 */ // Label 990: @36269
14392 /* 36269 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(36318), // Rule ID 445 //
14393 /* 36274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14394 /* 36277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14395 /* 36282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14396 /* 36285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14397 /* 36288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14398 /* 36291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14399 /* 36295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14400 /* 36299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14401 /* 36303 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14402 /* 36303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
14403 /* 36306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14404 /* 36308 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14405 /* 36310 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14406 /* 36312 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14407 /* 36316 */ GIR_RootConstrainSelectedInstOperands,
14408 /* 36317 */ // GIR_Coverage, 445,
14409 /* 36317 */ GIR_EraseRootFromParent_Done,
14410 /* 36318 */ // Label 991: @36318
14411 /* 36318 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(36367), // Rule ID 446 //
14412 /* 36323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14413 /* 36326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14414 /* 36331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14415 /* 36334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14416 /* 36337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14417 /* 36340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14418 /* 36344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14419 /* 36348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14420 /* 36352 */ // (intrinsic_w_chain:{ *:[i32] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14421 /* 36352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
14422 /* 36355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14423 /* 36357 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14424 /* 36359 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14425 /* 36361 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14426 /* 36365 */ GIR_RootConstrainSelectedInstOperands,
14427 /* 36366 */ // GIR_Coverage, 446,
14428 /* 36366 */ GIR_EraseRootFromParent_Done,
14429 /* 36367 */ // Label 992: @36367
14430 /* 36367 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(36416), // Rule ID 456 //
14431 /* 36372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14432 /* 36375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
14433 /* 36380 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14434 /* 36383 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14435 /* 36386 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14436 /* 36389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14437 /* 36393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14438 /* 36397 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14439 /* 36401 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14440 /* 36401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
14441 /* 36404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14442 /* 36406 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14443 /* 36408 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14444 /* 36410 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14445 /* 36414 */ GIR_RootConstrainSelectedInstOperands,
14446 /* 36415 */ // GIR_Coverage, 456,
14447 /* 36415 */ GIR_EraseRootFromParent_Done,
14448 /* 36416 */ // Label 993: @36416
14449 /* 36416 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(36465), // Rule ID 457 //
14450 /* 36421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14451 /* 36424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
14452 /* 36429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14453 /* 36432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14454 /* 36435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14455 /* 36438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14456 /* 36442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14457 /* 36446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14458 /* 36450 */ // (intrinsic_w_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14459 /* 36450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
14460 /* 36453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14461 /* 36455 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14462 /* 36457 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14463 /* 36459 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14464 /* 36463 */ GIR_RootConstrainSelectedInstOperands,
14465 /* 36464 */ // GIR_Coverage, 457,
14466 /* 36464 */ GIR_EraseRootFromParent_Done,
14467 /* 36465 */ // Label 994: @36465
14468 /* 36465 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(36514), // Rule ID 461 //
14469 /* 36470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14470 /* 36473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
14471 /* 36478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14472 /* 36481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14473 /* 36484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14474 /* 36487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14475 /* 36491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14476 /* 36495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14477 /* 36499 */ // (intrinsic_w_chain:{ *:[i32] } 8349:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
14478 /* 36499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
14479 /* 36502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14480 /* 36504 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
14481 /* 36506 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14482 /* 36508 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14483 /* 36512 */ GIR_RootConstrainSelectedInstOperands,
14484 /* 36513 */ // GIR_Coverage, 461,
14485 /* 36513 */ GIR_EraseRootFromParent_Done,
14486 /* 36514 */ // Label 995: @36514
14487 /* 36514 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(36566), // Rule ID 467 //
14488 /* 36519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14489 /* 36522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
14490 /* 36527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14491 /* 36530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14492 /* 36533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14493 /* 36536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14494 /* 36540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14495 /* 36544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14496 /* 36548 */ // (intrinsic_w_chain:{ *:[v2i16] } 7999:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14497 /* 36548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
14498 /* 36551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14499 /* 36553 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14500 /* 36555 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14501 /* 36557 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14502 /* 36560 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14503 /* 36564 */ GIR_RootConstrainSelectedInstOperands,
14504 /* 36565 */ // GIR_Coverage, 467,
14505 /* 36565 */ GIR_EraseRootFromParent_Done,
14506 /* 36566 */ // Label 996: @36566
14507 /* 36566 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(36618), // Rule ID 468 //
14508 /* 36571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14509 /* 36574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14510 /* 36579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14511 /* 36582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14512 /* 36585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14513 /* 36588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14514 /* 36592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14515 /* 36596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14516 /* 36600 */ // (intrinsic_w_chain:{ *:[v2i16] } 8001:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14517 /* 36600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
14518 /* 36603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14519 /* 36605 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14520 /* 36607 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14521 /* 36609 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14522 /* 36612 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14523 /* 36616 */ GIR_RootConstrainSelectedInstOperands,
14524 /* 36617 */ // GIR_Coverage, 468,
14525 /* 36617 */ GIR_EraseRootFromParent_Done,
14526 /* 36618 */ // Label 997: @36618
14527 /* 36618 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36670), // Rule ID 469 //
14528 /* 36623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14529 /* 36626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
14530 /* 36631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14531 /* 36634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14532 /* 36637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14533 /* 36640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14534 /* 36644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14535 /* 36648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14536 /* 36652 */ // (intrinsic_w_chain:{ *:[v2i16] } 8622:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14537 /* 36652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
14538 /* 36655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14539 /* 36657 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14540 /* 36659 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14541 /* 36661 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14542 /* 36664 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14543 /* 36668 */ GIR_RootConstrainSelectedInstOperands,
14544 /* 36669 */ // GIR_Coverage, 469,
14545 /* 36669 */ GIR_EraseRootFromParent_Done,
14546 /* 36670 */ // Label 998: @36670
14547 /* 36670 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(36722), // Rule ID 470 //
14548 /* 36675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14549 /* 36678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14550 /* 36683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14551 /* 36686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14552 /* 36689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14553 /* 36692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14554 /* 36696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14555 /* 36700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14556 /* 36704 */ // (intrinsic_w_chain:{ *:[v2i16] } 8624:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14557 /* 36704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
14558 /* 36707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14559 /* 36709 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14560 /* 36711 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14561 /* 36713 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14562 /* 36716 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14563 /* 36720 */ GIR_RootConstrainSelectedInstOperands,
14564 /* 36721 */ // GIR_Coverage, 470,
14565 /* 36721 */ GIR_EraseRootFromParent_Done,
14566 /* 36722 */ // Label 999: @36722
14567 /* 36722 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36774), // Rule ID 471 //
14568 /* 36727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14569 /* 36730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14570 /* 36735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14571 /* 36738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14572 /* 36741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14573 /* 36744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14574 /* 36748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14575 /* 36752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14576 /* 36756 */ // (intrinsic_w_chain:{ *:[i32] } 8144:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14577 /* 36756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
14578 /* 36759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14579 /* 36761 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14580 /* 36763 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14581 /* 36765 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14582 /* 36768 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14583 /* 36772 */ GIR_RootConstrainSelectedInstOperands,
14584 /* 36773 */ // GIR_Coverage, 471,
14585 /* 36773 */ GIR_EraseRootFromParent_Done,
14586 /* 36774 */ // Label 1000: @36774
14587 /* 36774 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36826), // Rule ID 472 //
14588 /* 36779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14589 /* 36782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14590 /* 36787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14591 /* 36790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14592 /* 36793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14593 /* 36796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14594 /* 36800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14595 /* 36804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14596 /* 36808 */ // (intrinsic_w_chain:{ *:[i32] } 8146:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14597 /* 36808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
14598 /* 36811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14599 /* 36813 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14600 /* 36815 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14601 /* 36817 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14602 /* 36820 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14603 /* 36824 */ GIR_RootConstrainSelectedInstOperands,
14604 /* 36825 */ // GIR_Coverage, 472,
14605 /* 36825 */ GIR_EraseRootFromParent_Done,
14606 /* 36826 */ // Label 1001: @36826
14607 /* 36826 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36878), // Rule ID 473 //
14608 /* 36831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14609 /* 36834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14610 /* 36839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14611 /* 36842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14612 /* 36845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14613 /* 36848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14614 /* 36852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14615 /* 36856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14616 /* 36860 */ // (intrinsic_w_chain:{ *:[i32] } 8145:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14617 /* 36860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
14618 /* 36863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14619 /* 36865 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14620 /* 36867 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14621 /* 36869 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14622 /* 36872 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14623 /* 36876 */ GIR_RootConstrainSelectedInstOperands,
14624 /* 36877 */ // GIR_Coverage, 473,
14625 /* 36877 */ GIR_EraseRootFromParent_Done,
14626 /* 36878 */ // Label 1002: @36878
14627 /* 36878 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36930), // Rule ID 487 //
14628 /* 36883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14629 /* 36886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14630 /* 36891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14631 /* 36894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14632 /* 36897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14633 /* 36900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14634 /* 36904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14635 /* 36908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14636 /* 36912 */ // (intrinsic_w_chain:{ *:[v2i16] } 8446:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14637 /* 36912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
14638 /* 36915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14639 /* 36917 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14640 /* 36919 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14641 /* 36921 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14642 /* 36924 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14643 /* 36928 */ GIR_RootConstrainSelectedInstOperands,
14644 /* 36929 */ // GIR_Coverage, 487,
14645 /* 36929 */ GIR_EraseRootFromParent_Done,
14646 /* 36930 */ // Label 1003: @36930
14647 /* 36930 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36982), // Rule ID 488 //
14648 /* 36935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14649 /* 36938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14650 /* 36943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14651 /* 36946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14652 /* 36949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14653 /* 36952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14654 /* 36956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14655 /* 36960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14656 /* 36964 */ // (intrinsic_w_chain:{ *:[i32] } 8454:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14657 /* 36964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
14658 /* 36967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14659 /* 36969 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14660 /* 36971 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14661 /* 36973 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14662 /* 36976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14663 /* 36980 */ GIR_RootConstrainSelectedInstOperands,
14664 /* 36981 */ // GIR_Coverage, 488,
14665 /* 36981 */ GIR_EraseRootFromParent_Done,
14666 /* 36982 */ // Label 1004: @36982
14667 /* 36982 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(37034), // Rule ID 489 //
14668 /* 36987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14669 /* 36990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14670 /* 36995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14671 /* 36998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14672 /* 37001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14673 /* 37004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14674 /* 37008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14675 /* 37012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14676 /* 37016 */ // (intrinsic_w_chain:{ *:[i32] } 8452:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14677 /* 37016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
14678 /* 37019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14679 /* 37021 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14680 /* 37023 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14681 /* 37025 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14682 /* 37028 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14683 /* 37032 */ GIR_RootConstrainSelectedInstOperands,
14684 /* 37033 */ // GIR_Coverage, 489,
14685 /* 37033 */ GIR_EraseRootFromParent_Done,
14686 /* 37034 */ // Label 1005: @37034
14687 /* 37034 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(37086), // Rule ID 490 //
14688 /* 37039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14689 /* 37042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14690 /* 37047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14691 /* 37050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14692 /* 37053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14693 /* 37056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14694 /* 37060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14695 /* 37064 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14696 /* 37068 */ // (intrinsic_w_chain:{ *:[v2i16] } 8453:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14697 /* 37068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
14698 /* 37071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14699 /* 37073 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14700 /* 37075 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14701 /* 37077 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14702 /* 37080 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14703 /* 37084 */ GIR_RootConstrainSelectedInstOperands,
14704 /* 37085 */ // GIR_Coverage, 490,
14705 /* 37085 */ GIR_EraseRootFromParent_Done,
14706 /* 37086 */ // Label 1006: @37086
14707 /* 37086 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(37135), // Rule ID 500 //
14708 /* 37091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14709 /* 37094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14710 /* 37099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14711 /* 37102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14712 /* 37105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14713 /* 37108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14714 /* 37112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14715 /* 37116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14716 /* 37120 */ // (intrinsic_w_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14717 /* 37120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
14718 /* 37123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14719 /* 37125 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14720 /* 37127 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14721 /* 37129 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14722 /* 37133 */ GIR_RootConstrainSelectedInstOperands,
14723 /* 37134 */ // GIR_Coverage, 500,
14724 /* 37134 */ GIR_EraseRootFromParent_Done,
14725 /* 37135 */ // Label 1007: @37135
14726 /* 37135 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(37187), // Rule ID 1247 //
14727 /* 37140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14728 /* 37143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
14729 /* 37148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14730 /* 37151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14731 /* 37154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14732 /* 37157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14733 /* 37161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14734 /* 37165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14735 /* 37169 */ // (intrinsic_w_chain:{ *:[i32] } 7981:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14736 /* 37169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
14737 /* 37172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14738 /* 37174 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14739 /* 37176 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14740 /* 37178 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14741 /* 37181 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14742 /* 37185 */ GIR_RootConstrainSelectedInstOperands,
14743 /* 37186 */ // GIR_Coverage, 1247,
14744 /* 37186 */ GIR_EraseRootFromParent_Done,
14745 /* 37187 */ // Label 1008: @37187
14746 /* 37187 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(37236), // Rule ID 1255 //
14747 /* 37192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14748 /* 37195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
14749 /* 37200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14750 /* 37203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14751 /* 37206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14752 /* 37209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14753 /* 37213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14754 /* 37217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14755 /* 37221 */ // (intrinsic_w_chain:{ *:[i32] } 8349:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
14756 /* 37221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
14757 /* 37224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14758 /* 37226 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
14759 /* 37228 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14760 /* 37230 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14761 /* 37234 */ GIR_RootConstrainSelectedInstOperands,
14762 /* 37235 */ // GIR_Coverage, 1255,
14763 /* 37235 */ GIR_EraseRootFromParent_Done,
14764 /* 37236 */ // Label 1009: @37236
14765 /* 37236 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(37288), // Rule ID 1263 //
14766 /* 37241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14767 /* 37244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14768 /* 37249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14769 /* 37252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14770 /* 37255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14771 /* 37258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14772 /* 37262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14773 /* 37266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14774 /* 37270 */ // (intrinsic_w_chain:{ *:[v2i16] } 8526:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14775 /* 37270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
14776 /* 37273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14777 /* 37275 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14778 /* 37277 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14779 /* 37279 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14780 /* 37282 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14781 /* 37286 */ GIR_RootConstrainSelectedInstOperands,
14782 /* 37287 */ // GIR_Coverage, 1263,
14783 /* 37287 */ GIR_EraseRootFromParent_Done,
14784 /* 37288 */ // Label 1010: @37288
14785 /* 37288 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(37340), // Rule ID 1264 //
14786 /* 37293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14787 /* 37296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14788 /* 37301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14789 /* 37304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14790 /* 37307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14791 /* 37310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14792 /* 37314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14793 /* 37318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14794 /* 37322 */ // (intrinsic_w_chain:{ *:[v2i16] } 8528:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14795 /* 37322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
14796 /* 37325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14797 /* 37327 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14798 /* 37329 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14799 /* 37331 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14800 /* 37334 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14801 /* 37338 */ GIR_RootConstrainSelectedInstOperands,
14802 /* 37339 */ // GIR_Coverage, 1264,
14803 /* 37339 */ GIR_EraseRootFromParent_Done,
14804 /* 37340 */ // Label 1011: @37340
14805 /* 37340 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(37392), // Rule ID 1265 //
14806 /* 37345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14807 /* 37348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14808 /* 37353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14809 /* 37356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14810 /* 37359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14811 /* 37362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14812 /* 37366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14813 /* 37370 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14814 /* 37374 */ // (intrinsic_w_chain:{ *:[v4i8] } 8527:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14815 /* 37374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
14816 /* 37377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14817 /* 37379 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14818 /* 37381 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14819 /* 37383 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14820 /* 37386 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14821 /* 37390 */ GIR_RootConstrainSelectedInstOperands,
14822 /* 37391 */ // GIR_Coverage, 1265,
14823 /* 37391 */ GIR_EraseRootFromParent_Done,
14824 /* 37392 */ // Label 1012: @37392
14825 /* 37392 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(37444), // Rule ID 1266 //
14826 /* 37397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14827 /* 37400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14828 /* 37405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14829 /* 37408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14830 /* 37411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14831 /* 37414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14832 /* 37418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14833 /* 37422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14834 /* 37426 */ // (intrinsic_w_chain:{ *:[i32] } 8529:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14835 /* 37426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
14836 /* 37429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14837 /* 37431 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14838 /* 37433 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14839 /* 37435 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14840 /* 37438 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14841 /* 37442 */ GIR_RootConstrainSelectedInstOperands,
14842 /* 37443 */ // GIR_Coverage, 1266,
14843 /* 37443 */ GIR_EraseRootFromParent_Done,
14844 /* 37444 */ // Label 1013: @37444
14845 /* 37444 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(37496), // Rule ID 1285 //
14846 /* 37449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14847 /* 37452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14848 /* 37457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14849 /* 37460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14850 /* 37463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14851 /* 37466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14852 /* 37470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14853 /* 37474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14854 /* 37478 */ // (intrinsic_w_chain:{ *:[i32] } 8601:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14855 /* 37478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
14856 /* 37481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14857 /* 37483 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14858 /* 37485 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14859 /* 37487 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14860 /* 37490 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14861 /* 37494 */ GIR_RootConstrainSelectedInstOperands,
14862 /* 37495 */ // GIR_Coverage, 1285,
14863 /* 37495 */ GIR_EraseRootFromParent_Done,
14864 /* 37496 */ // Label 1014: @37496
14865 /* 37496 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(37548), // Rule ID 1291 //
14866 /* 37501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14867 /* 37504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14868 /* 37509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14869 /* 37512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14870 /* 37515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14871 /* 37518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14872 /* 37522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14873 /* 37526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14874 /* 37530 */ // (intrinsic_w_chain:{ *:[i32] } 8447:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14875 /* 37530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
14876 /* 37533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14877 /* 37535 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14878 /* 37537 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14879 /* 37539 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14880 /* 37542 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14881 /* 37546 */ GIR_RootConstrainSelectedInstOperands,
14882 /* 37547 */ // GIR_Coverage, 1291,
14883 /* 37547 */ GIR_EraseRootFromParent_Done,
14884 /* 37548 */ // Label 1015: @37548
14885 /* 37548 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(37600), // Rule ID 1292 //
14886 /* 37553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14887 /* 37556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14888 /* 37561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14889 /* 37564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14890 /* 37567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14891 /* 37570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14892 /* 37574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14893 /* 37578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14894 /* 37582 */ // (intrinsic_w_chain:{ *:[i32] } 8448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14895 /* 37582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
14896 /* 37585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14897 /* 37587 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14898 /* 37589 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14899 /* 37591 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14900 /* 37594 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14901 /* 37598 */ GIR_RootConstrainSelectedInstOperands,
14902 /* 37599 */ // GIR_Coverage, 1292,
14903 /* 37599 */ GIR_EraseRootFromParent_Done,
14904 /* 37600 */ // Label 1016: @37600
14905 /* 37600 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37652), // Rule ID 1293 //
14906 /* 37605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14907 /* 37608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14908 /* 37613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14909 /* 37616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14910 /* 37619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14911 /* 37622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14912 /* 37626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14913 /* 37630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14914 /* 37634 */ // (intrinsic_w_chain:{ *:[v2i16] } 8449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14915 /* 37634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
14916 /* 37637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14917 /* 37639 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14918 /* 37641 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14919 /* 37643 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14920 /* 37646 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14921 /* 37650 */ GIR_RootConstrainSelectedInstOperands,
14922 /* 37651 */ // GIR_Coverage, 1293,
14923 /* 37651 */ GIR_EraseRootFromParent_Done,
14924 /* 37652 */ // Label 1017: @37652
14925 /* 37652 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(37704), // Rule ID 1294 //
14926 /* 37657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14927 /* 37660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14928 /* 37665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14929 /* 37668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14930 /* 37671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14931 /* 37674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14932 /* 37678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14933 /* 37682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14934 /* 37686 */ // (intrinsic_w_chain:{ *:[v2i16] } 8450:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14935 /* 37686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
14936 /* 37689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14937 /* 37691 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14938 /* 37693 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14939 /* 37695 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14940 /* 37698 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14941 /* 37702 */ GIR_RootConstrainSelectedInstOperands,
14942 /* 37703 */ // GIR_Coverage, 1294,
14943 /* 37703 */ GIR_EraseRootFromParent_Done,
14944 /* 37704 */ // Label 1018: @37704
14945 /* 37704 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(37756), // Rule ID 1295 //
14946 /* 37709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14947 /* 37712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14948 /* 37717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14949 /* 37720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14950 /* 37723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14951 /* 37726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14952 /* 37730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14953 /* 37734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14954 /* 37738 */ // (intrinsic_w_chain:{ *:[v2i16] } 8451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14955 /* 37738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
14956 /* 37741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14957 /* 37743 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14958 /* 37745 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14959 /* 37747 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14960 /* 37750 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14961 /* 37754 */ GIR_RootConstrainSelectedInstOperands,
14962 /* 37755 */ // GIR_Coverage, 1295,
14963 /* 37755 */ GIR_EraseRootFromParent_Done,
14964 /* 37756 */ // Label 1019: @37756
14965 /* 37756 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(37808), // Rule ID 1298 //
14966 /* 37761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14967 /* 37764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14968 /* 37769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14969 /* 37772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14970 /* 37775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14971 /* 37778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14972 /* 37782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14973 /* 37786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14974 /* 37790 */ // (intrinsic_w_chain:{ *:[v4i8] } 8508:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14975 /* 37790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
14976 /* 37793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14977 /* 37795 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14978 /* 37797 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14979 /* 37799 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14980 /* 37802 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14981 /* 37806 */ GIR_RootConstrainSelectedInstOperands,
14982 /* 37807 */ // GIR_Coverage, 1298,
14983 /* 37807 */ GIR_EraseRootFromParent_Done,
14984 /* 37808 */ // Label 1020: @37808
14985 /* 37808 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(37860), // Rule ID 1299 //
14986 /* 37813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14987 /* 37816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14988 /* 37821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14989 /* 37824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14990 /* 37827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14991 /* 37830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14992 /* 37834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14993 /* 37838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14994 /* 37842 */ // (intrinsic_w_chain:{ *:[v2i16] } 8507:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14995 /* 37842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14996 /* 37845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14997 /* 37847 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14998 /* 37849 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14999 /* 37851 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
15000 /* 37854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15001 /* 37858 */ GIR_RootConstrainSelectedInstOperands,
15002 /* 37859 */ // GIR_Coverage, 1299,
15003 /* 37859 */ GIR_EraseRootFromParent_Done,
15004 /* 37860 */ // Label 1021: @37860
15005 /* 37860 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37909), // Rule ID 1317 //
15006 /* 37865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15007 /* 37868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
15008 /* 37873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15009 /* 37876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15010 /* 37879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15011 /* 37882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15012 /* 37886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15013 /* 37890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15014 /* 37894 */ // (intrinsic_w_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15015 /* 37894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
15016 /* 37897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15017 /* 37899 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15018 /* 37901 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15019 /* 37903 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15020 /* 37907 */ GIR_RootConstrainSelectedInstOperands,
15021 /* 37908 */ // GIR_Coverage, 1317,
15022 /* 37908 */ GIR_EraseRootFromParent_Done,
15023 /* 37909 */ // Label 1022: @37909
15024 /* 37909 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37958), // Rule ID 1318 //
15025 /* 37914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15026 /* 37917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
15027 /* 37922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
15028 /* 37925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15029 /* 37928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15030 /* 37931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15031 /* 37935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15032 /* 37939 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15033 /* 37943 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15034 /* 37943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
15035 /* 37946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15036 /* 37948 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15037 /* 37950 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15038 /* 37952 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15039 /* 37956 */ GIR_RootConstrainSelectedInstOperands,
15040 /* 37957 */ // GIR_Coverage, 1318,
15041 /* 37957 */ GIR_EraseRootFromParent_Done,
15042 /* 37958 */ // Label 1023: @37958
15043 /* 37958 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(38007), // Rule ID 1328 //
15044 /* 37963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15045 /* 37966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
15046 /* 37971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15047 /* 37974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15048 /* 37977 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15049 /* 37980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15050 /* 37984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15051 /* 37988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15052 /* 37992 */ // (intrinsic_w_chain:{ *:[i32] } 8147:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15053 /* 37992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
15054 /* 37995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15055 /* 37997 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15056 /* 37999 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15057 /* 38001 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15058 /* 38005 */ GIR_RootConstrainSelectedInstOperands,
15059 /* 38006 */ // GIR_Coverage, 1328,
15060 /* 38006 */ GIR_EraseRootFromParent_Done,
15061 /* 38007 */ // Label 1024: @38007
15062 /* 38007 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(38056), // Rule ID 1329 //
15063 /* 38012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15064 /* 38015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
15065 /* 38020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15066 /* 38023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15067 /* 38026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15068 /* 38029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15069 /* 38033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15070 /* 38037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15071 /* 38041 */ // (intrinsic_w_chain:{ *:[i32] } 8149:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15072 /* 38041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
15073 /* 38044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15074 /* 38046 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15075 /* 38048 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15076 /* 38050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15077 /* 38054 */ GIR_RootConstrainSelectedInstOperands,
15078 /* 38055 */ // GIR_Coverage, 1329,
15079 /* 38055 */ GIR_EraseRootFromParent_Done,
15080 /* 38056 */ // Label 1025: @38056
15081 /* 38056 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(38105), // Rule ID 1330 //
15082 /* 38061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15083 /* 38064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
15084 /* 38069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15085 /* 38072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15086 /* 38075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15087 /* 38078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15088 /* 38082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15089 /* 38086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15090 /* 38090 */ // (intrinsic_w_chain:{ *:[i32] } 8148:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15091 /* 38090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
15092 /* 38093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15093 /* 38095 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15094 /* 38097 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15095 /* 38099 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15096 /* 38103 */ GIR_RootConstrainSelectedInstOperands,
15097 /* 38104 */ // GIR_Coverage, 1330,
15098 /* 38104 */ GIR_EraseRootFromParent_Done,
15099 /* 38105 */ // Label 1026: @38105
15100 /* 38105 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(38157), // Rule ID 1339 //
15101 /* 38110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15102 /* 38113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
15103 /* 38118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15104 /* 38121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15105 /* 38124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15106 /* 38127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15107 /* 38131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15108 /* 38135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15109 /* 38139 */ // (intrinsic_w_chain:{ *:[v2i16] } 7999:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15110 /* 38139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
15111 /* 38142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15112 /* 38144 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15113 /* 38146 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15114 /* 38148 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15115 /* 38151 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15116 /* 38155 */ GIR_RootConstrainSelectedInstOperands,
15117 /* 38156 */ // GIR_Coverage, 1339,
15118 /* 38156 */ GIR_EraseRootFromParent_Done,
15119 /* 38157 */ // Label 1027: @38157
15120 /* 38157 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(38209), // Rule ID 1340 //
15121 /* 38162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15122 /* 38165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
15123 /* 38170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15124 /* 38173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15125 /* 38176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15126 /* 38179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15127 /* 38183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15128 /* 38187 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15129 /* 38191 */ // (intrinsic_w_chain:{ *:[v2i16] } 8001:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15130 /* 38191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
15131 /* 38194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15132 /* 38196 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15133 /* 38198 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15134 /* 38200 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15135 /* 38203 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15136 /* 38207 */ GIR_RootConstrainSelectedInstOperands,
15137 /* 38208 */ // GIR_Coverage, 1340,
15138 /* 38208 */ GIR_EraseRootFromParent_Done,
15139 /* 38209 */ // Label 1028: @38209
15140 /* 38209 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(38261), // Rule ID 1351 //
15141 /* 38214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15142 /* 38217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
15143 /* 38222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15144 /* 38225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15145 /* 38228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15146 /* 38231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15147 /* 38235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15148 /* 38239 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15149 /* 38243 */ // (intrinsic_w_chain:{ *:[i32] } 8144:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15150 /* 38243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
15151 /* 38246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15152 /* 38248 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15153 /* 38250 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15154 /* 38252 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15155 /* 38255 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15156 /* 38259 */ GIR_RootConstrainSelectedInstOperands,
15157 /* 38260 */ // GIR_Coverage, 1351,
15158 /* 38260 */ GIR_EraseRootFromParent_Done,
15159 /* 38261 */ // Label 1029: @38261
15160 /* 38261 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(38313), // Rule ID 1352 //
15161 /* 38266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15162 /* 38269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
15163 /* 38274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15164 /* 38277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15165 /* 38280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15166 /* 38283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15167 /* 38287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15168 /* 38291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15169 /* 38295 */ // (intrinsic_w_chain:{ *:[i32] } 8146:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15170 /* 38295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
15171 /* 38298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15172 /* 38300 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15173 /* 38302 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15174 /* 38304 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15175 /* 38307 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15176 /* 38311 */ GIR_RootConstrainSelectedInstOperands,
15177 /* 38312 */ // GIR_Coverage, 1352,
15178 /* 38312 */ GIR_EraseRootFromParent_Done,
15179 /* 38313 */ // Label 1030: @38313
15180 /* 38313 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(38365), // Rule ID 1353 //
15181 /* 38318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15182 /* 38321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
15183 /* 38326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15184 /* 38329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15185 /* 38332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15186 /* 38335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15187 /* 38339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15188 /* 38343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15189 /* 38347 */ // (intrinsic_w_chain:{ *:[i32] } 8145:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15190 /* 38347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
15191 /* 38350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15192 /* 38352 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15193 /* 38354 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15194 /* 38356 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15195 /* 38359 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15196 /* 38363 */ GIR_RootConstrainSelectedInstOperands,
15197 /* 38364 */ // GIR_Coverage, 1353,
15198 /* 38364 */ GIR_EraseRootFromParent_Done,
15199 /* 38365 */ // Label 1031: @38365
15200 /* 38365 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(38417), // Rule ID 1359 //
15201 /* 38370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15202 /* 38373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
15203 /* 38378 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15204 /* 38381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15205 /* 38384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15206 /* 38387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15207 /* 38391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15208 /* 38395 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15209 /* 38399 */ // (intrinsic_w_chain:{ *:[v2i16] } 8622:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15210 /* 38399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
15211 /* 38402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15212 /* 38404 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15213 /* 38406 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15214 /* 38408 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15215 /* 38411 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15216 /* 38415 */ GIR_RootConstrainSelectedInstOperands,
15217 /* 38416 */ // GIR_Coverage, 1359,
15218 /* 38416 */ GIR_EraseRootFromParent_Done,
15219 /* 38417 */ // Label 1032: @38417
15220 /* 38417 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(38469), // Rule ID 1360 //
15221 /* 38422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15222 /* 38425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
15223 /* 38430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15224 /* 38433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15225 /* 38436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15226 /* 38439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15227 /* 38443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15228 /* 38447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15229 /* 38451 */ // (intrinsic_w_chain:{ *:[v2i16] } 8624:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15230 /* 38451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
15231 /* 38454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15232 /* 38456 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15233 /* 38458 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15234 /* 38460 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15235 /* 38463 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15236 /* 38467 */ GIR_RootConstrainSelectedInstOperands,
15237 /* 38468 */ // GIR_Coverage, 1360,
15238 /* 38468 */ GIR_EraseRootFromParent_Done,
15239 /* 38469 */ // Label 1033: @38469
15240 /* 38469 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(38521), // Rule ID 1367 //
15241 /* 38474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15242 /* 38477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
15243 /* 38482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15244 /* 38485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15245 /* 38488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15246 /* 38491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15247 /* 38495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15248 /* 38499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15249 /* 38503 */ // (intrinsic_w_chain:{ *:[v2i16] } 8446:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15250 /* 38503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
15251 /* 38506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15252 /* 38508 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15253 /* 38510 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15254 /* 38512 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15255 /* 38515 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15256 /* 38519 */ GIR_RootConstrainSelectedInstOperands,
15257 /* 38520 */ // GIR_Coverage, 1367,
15258 /* 38520 */ GIR_EraseRootFromParent_Done,
15259 /* 38521 */ // Label 1034: @38521
15260 /* 38521 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(38573), // Rule ID 1368 //
15261 /* 38526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15262 /* 38529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
15263 /* 38534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15264 /* 38537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15265 /* 38540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15266 /* 38543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15267 /* 38547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15268 /* 38551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15269 /* 38555 */ // (intrinsic_w_chain:{ *:[i32] } 8452:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15270 /* 38555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
15271 /* 38558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15272 /* 38560 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15273 /* 38562 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15274 /* 38564 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15275 /* 38567 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15276 /* 38571 */ GIR_RootConstrainSelectedInstOperands,
15277 /* 38572 */ // GIR_Coverage, 1368,
15278 /* 38572 */ GIR_EraseRootFromParent_Done,
15279 /* 38573 */ // Label 1035: @38573
15280 /* 38573 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(38625), // Rule ID 1369 //
15281 /* 38578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15282 /* 38581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
15283 /* 38586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15284 /* 38589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15285 /* 38592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15286 /* 38595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15287 /* 38599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15288 /* 38603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15289 /* 38607 */ // (intrinsic_w_chain:{ *:[v2i16] } 8453:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15290 /* 38607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
15291 /* 38610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15292 /* 38612 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15293 /* 38614 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15294 /* 38616 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15295 /* 38619 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15296 /* 38623 */ GIR_RootConstrainSelectedInstOperands,
15297 /* 38624 */ // GIR_Coverage, 1369,
15298 /* 38624 */ GIR_EraseRootFromParent_Done,
15299 /* 38625 */ // Label 1036: @38625
15300 /* 38625 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(38677), // Rule ID 1370 //
15301 /* 38630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15302 /* 38633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
15303 /* 38638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15304 /* 38641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15305 /* 38644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15306 /* 38647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15307 /* 38651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15308 /* 38655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15309 /* 38659 */ // (intrinsic_w_chain:{ *:[i32] } 8454:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15310 /* 38659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
15311 /* 38662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15312 /* 38664 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15313 /* 38666 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15314 /* 38668 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15315 /* 38671 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15316 /* 38675 */ GIR_RootConstrainSelectedInstOperands,
15317 /* 38676 */ // GIR_Coverage, 1370,
15318 /* 38676 */ GIR_EraseRootFromParent_Done,
15319 /* 38677 */ // Label 1037: @38677
15320 /* 38677 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(38726), // Rule ID 1371 //
15321 /* 38682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15322 /* 38685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
15323 /* 38690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
15324 /* 38693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15325 /* 38696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15326 /* 38699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15327 /* 38703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15328 /* 38707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15329 /* 38711 */ // (intrinsic_w_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15330 /* 38711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
15331 /* 38714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15332 /* 38716 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15333 /* 38718 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15334 /* 38720 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15335 /* 38724 */ GIR_RootConstrainSelectedInstOperands,
15336 /* 38725 */ // GIR_Coverage, 1371,
15337 /* 38725 */ GIR_EraseRootFromParent_Done,
15338 /* 38726 */ // Label 1038: @38726
15339 /* 38726 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(38770), // Rule ID 2056 //
15340 /* 38731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
15341 /* 38734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
15342 /* 38739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15343 /* 38742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15344 /* 38745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15345 /* 38748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15346 /* 38752 */ // (intrinsic_w_chain:{ *:[v2i16] } 8443:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
15347 /* 38752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
15348 /* 38755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15349 /* 38757 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15350 /* 38759 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15351 /* 38761 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15352 /* 38764 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15353 /* 38768 */ GIR_RootConstrainSelectedInstOperands,
15354 /* 38769 */ // GIR_Coverage, 2056,
15355 /* 38769 */ GIR_EraseRootFromParent_Done,
15356 /* 38770 */ // Label 1039: @38770
15357 /* 38770 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(38814), // Rule ID 2062 //
15358 /* 38775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15359 /* 38778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
15360 /* 38783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15361 /* 38786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15362 /* 38789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15363 /* 38792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15364 /* 38796 */ // (intrinsic_w_chain:{ *:[i32] } 7998:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
15365 /* 38796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
15366 /* 38799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15367 /* 38801 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15368 /* 38803 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15369 /* 38805 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
15370 /* 38808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15371 /* 38812 */ GIR_RootConstrainSelectedInstOperands,
15372 /* 38813 */ // GIR_Coverage, 2062,
15373 /* 38813 */ GIR_EraseRootFromParent_Done,
15374 /* 38814 */ // Label 1040: @38814
15375 /* 38814 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(38858), // Rule ID 2064 //
15376 /* 38819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15377 /* 38822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
15378 /* 38827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15379 /* 38830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15380 /* 38833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15381 /* 38836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15382 /* 38840 */ // (intrinsic_w_chain:{ *:[i32] } 8013:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
15383 /* 38840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
15384 /* 38843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15385 /* 38845 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15386 /* 38847 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15387 /* 38849 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15388 /* 38852 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15389 /* 38856 */ GIR_RootConstrainSelectedInstOperands,
15390 /* 38857 */ // GIR_Coverage, 2064,
15391 /* 38857 */ GIR_EraseRootFromParent_Done,
15392 /* 38858 */ // Label 1041: @38858
15393 /* 38858 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(38904), // Rule ID 511 //
15394 /* 38863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15395 /* 38866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
15396 /* 38871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15397 /* 38874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15398 /* 38877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15399 /* 38881 */ // MIs[0] ptr
15400 /* 38881 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15401 /* 38885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15402 /* 38889 */ // (intrinsic_w_chain:{ *:[v2i64] } 8363:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15403 /* 38889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
15404 /* 38892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15405 /* 38894 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15406 /* 38896 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15407 /* 38898 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15408 /* 38902 */ GIR_RootConstrainSelectedInstOperands,
15409 /* 38903 */ // GIR_Coverage, 511,
15410 /* 38903 */ GIR_EraseRootFromParent_Done,
15411 /* 38904 */ // Label 1042: @38904
15412 /* 38904 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(38950), // Rule ID 512 //
15413 /* 38909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15414 /* 38912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
15415 /* 38917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15416 /* 38920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15417 /* 38923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15418 /* 38927 */ // MIs[0] ptr
15419 /* 38927 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15420 /* 38931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15421 /* 38935 */ // (intrinsic_w_chain:{ *:[v4i32] } 8364:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15422 /* 38935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
15423 /* 38938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15424 /* 38940 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15425 /* 38942 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15426 /* 38944 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15427 /* 38948 */ GIR_RootConstrainSelectedInstOperands,
15428 /* 38949 */ // GIR_Coverage, 512,
15429 /* 38949 */ GIR_EraseRootFromParent_Done,
15430 /* 38950 */ // Label 1043: @38950
15431 /* 38950 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(38992), // Rule ID 458 //
15432 /* 38955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15433 /* 38958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
15434 /* 38963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15435 /* 38966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15436 /* 38969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15437 /* 38973 */ // MIs[0] base
15438 /* 38973 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15439 /* 38977 */ // (intrinsic_w_chain:{ *:[i32] } 8367:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15440 /* 38977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
15441 /* 38980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15442 /* 38982 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15443 /* 38984 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15444 /* 38986 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15445 /* 38990 */ GIR_RootConstrainSelectedInstOperands,
15446 /* 38991 */ // GIR_Coverage, 458,
15447 /* 38991 */ GIR_EraseRootFromParent_Done,
15448 /* 38992 */ // Label 1044: @38992
15449 /* 38992 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(39034), // Rule ID 459 //
15450 /* 38997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15451 /* 39000 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
15452 /* 39005 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15453 /* 39008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15454 /* 39011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15455 /* 39015 */ // MIs[0] base
15456 /* 39015 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15457 /* 39019 */ // (intrinsic_w_chain:{ *:[i32] } 8365:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15458 /* 39019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
15459 /* 39022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15460 /* 39024 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15461 /* 39026 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15462 /* 39028 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15463 /* 39032 */ GIR_RootConstrainSelectedInstOperands,
15464 /* 39033 */ // GIR_Coverage, 459,
15465 /* 39033 */ GIR_EraseRootFromParent_Done,
15466 /* 39034 */ // Label 1045: @39034
15467 /* 39034 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(39076), // Rule ID 460 //
15468 /* 39039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15469 /* 39042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
15470 /* 39047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15471 /* 39050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15472 /* 39053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15473 /* 39057 */ // MIs[0] base
15474 /* 39057 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15475 /* 39061 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15476 /* 39061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
15477 /* 39064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15478 /* 39066 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15479 /* 39068 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15480 /* 39070 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15481 /* 39074 */ GIR_RootConstrainSelectedInstOperands,
15482 /* 39075 */ // GIR_Coverage, 460,
15483 /* 39075 */ GIR_EraseRootFromParent_Done,
15484 /* 39076 */ // Label 1046: @39076
15485 /* 39076 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(39118), // Rule ID 1300 //
15486 /* 39081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15487 /* 39084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
15488 /* 39089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15489 /* 39092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15490 /* 39095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15491 /* 39099 */ // MIs[0] base
15492 /* 39099 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15493 /* 39103 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15494 /* 39103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
15495 /* 39106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15496 /* 39108 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15497 /* 39110 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15498 /* 39112 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15499 /* 39116 */ GIR_RootConstrainSelectedInstOperands,
15500 /* 39117 */ // GIR_Coverage, 1300,
15501 /* 39117 */ GIR_EraseRootFromParent_Done,
15502 /* 39118 */ // Label 1047: @39118
15503 /* 39118 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(39160), // Rule ID 1301 //
15504 /* 39123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15505 /* 39126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
15506 /* 39131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15507 /* 39134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15508 /* 39137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15509 /* 39141 */ // MIs[0] base
15510 /* 39141 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15511 /* 39145 */ // (intrinsic_w_chain:{ *:[i32] } 8365:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15512 /* 39145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
15513 /* 39148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15514 /* 39150 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15515 /* 39152 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15516 /* 39154 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15517 /* 39158 */ GIR_RootConstrainSelectedInstOperands,
15518 /* 39159 */ // GIR_Coverage, 1301,
15519 /* 39159 */ GIR_EraseRootFromParent_Done,
15520 /* 39160 */ // Label 1048: @39160
15521 /* 39160 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(39202), // Rule ID 1302 //
15522 /* 39165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15523 /* 39168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
15524 /* 39173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15525 /* 39176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15526 /* 39179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15527 /* 39183 */ // MIs[0] base
15528 /* 39183 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15529 /* 39187 */ // (intrinsic_w_chain:{ *:[i32] } 8367:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15530 /* 39187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
15531 /* 39190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15532 /* 39192 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15533 /* 39194 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15534 /* 39196 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15535 /* 39200 */ GIR_RootConstrainSelectedInstOperands,
15536 /* 39201 */ // GIR_Coverage, 1302,
15537 /* 39201 */ GIR_EraseRootFromParent_Done,
15538 /* 39202 */ // Label 1049: @39202
15539 /* 39202 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(39248), // Rule ID 513 //
15540 /* 39207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15541 /* 39210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
15542 /* 39215 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
15543 /* 39218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15544 /* 39221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15545 /* 39225 */ // MIs[0] ptr
15546 /* 39225 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15547 /* 39229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15548 /* 39233 */ // (intrinsic_void 8597:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15549 /* 39233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
15550 /* 39236 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
15551 /* 39238 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15552 /* 39240 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15553 /* 39242 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15554 /* 39246 */ GIR_RootConstrainSelectedInstOperands,
15555 /* 39247 */ // GIR_Coverage, 513,
15556 /* 39247 */ GIR_EraseRootFromParent_Done,
15557 /* 39248 */ // Label 1050: @39248
15558 /* 39248 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(39294), // Rule ID 514 //
15559 /* 39253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15560 /* 39256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
15561 /* 39261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
15562 /* 39264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15563 /* 39267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15564 /* 39271 */ // MIs[0] ptr
15565 /* 39271 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15566 /* 39275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15567 /* 39279 */ // (intrinsic_void 8598:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15568 /* 39279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
15569 /* 39282 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
15570 /* 39284 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15571 /* 39286 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15572 /* 39288 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15573 /* 39292 */ GIR_RootConstrainSelectedInstOperands,
15574 /* 39293 */ // GIR_Coverage, 514,
15575 /* 39293 */ GIR_EraseRootFromParent_Done,
15576 /* 39294 */ // Label 1051: @39294
15577 /* 39294 */ GIM_Reject,
15578 /* 39295 */ // Label 970: @39295
15579 /* 39295 */ GIM_Reject,
15580 /* 39296 */ // Label 31: @39296
15581 /* 39296 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(39361), // Rule ID 1685 //
15582 /* 39301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15583 /* 39304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15584 /* 39307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15585 /* 39310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15586 /* 39314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15587 /* 39318 */ // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
15588 /* 39318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15589 /* 39321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15590 /* 39325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15591 /* 39330 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15592 /* 39332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15593 /* 39335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15594 /* 39337 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15595 /* 39340 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15596 /* 39342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15597 /* 39345 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15598 /* 39350 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15599 /* 39355 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15600 /* 39360 */ // GIR_Coverage, 1685,
15601 /* 39360 */ GIR_EraseRootFromParent_Done,
15602 /* 39361 */ // Label 1052: @39361
15603 /* 39361 */ GIM_Reject,
15604 /* 39362 */ // Label 32: @39362
15605 /* 39362 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(39425), // Rule ID 1678 //
15606 /* 39367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15607 /* 39370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15608 /* 39373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15609 /* 39376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15610 /* 39380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15611 /* 39384 */ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
15612 /* 39384 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15613 /* 39387 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15614 /* 39391 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15615 /* 39396 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
15616 /* 39402 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15617 /* 39407 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15618 /* 39412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
15619 /* 39415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15620 /* 39417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15621 /* 39420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15622 /* 39423 */ GIR_RootConstrainSelectedInstOperands,
15623 /* 39424 */ // GIR_Coverage, 1678,
15624 /* 39424 */ GIR_EraseRootFromParent_Done,
15625 /* 39425 */ // Label 1053: @39425
15626 /* 39425 */ GIM_Reject,
15627 /* 39426 */ // Label 33: @39426
15628 /* 39426 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(39486),
15629 /* 39431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15630 /* 39434 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(39460), // Rule ID 2289 //
15631 /* 39439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15632 /* 39442 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
15633 /* 39446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15634 /* 39450 */ // MIs[0] Operand 1
15635 /* 39450 */ // No operand predicates
15636 /* 39450 */ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
15637 /* 39450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
15638 /* 39453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15639 /* 39455 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
15640 /* 39458 */ GIR_RootConstrainSelectedInstOperands,
15641 /* 39459 */ // GIR_Coverage, 2289,
15642 /* 39459 */ GIR_EraseRootFromParent_Done,
15643 /* 39460 */ // Label 1055: @39460
15644 /* 39460 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(39485), // Rule ID 1980 //
15645 /* 39465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15646 /* 39468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15647 /* 39472 */ // MIs[0] Operand 1
15648 /* 39472 */ // No operand predicates
15649 /* 39472 */ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
15650 /* 39472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
15651 /* 39475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15652 /* 39477 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
15653 /* 39480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
15654 /* 39483 */ GIR_RootConstrainSelectedInstOperands,
15655 /* 39484 */ // GIR_Coverage, 1980,
15656 /* 39484 */ GIR_EraseRootFromParent_Done,
15657 /* 39485 */ // Label 1056: @39485
15658 /* 39485 */ GIM_Reject,
15659 /* 39486 */ // Label 1054: @39486
15660 /* 39486 */ GIM_Reject,
15661 /* 39487 */ // Label 34: @39487
15662 /* 39487 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(40950),
15663 /* 39492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15664 /* 39495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15665 /* 39498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15666 /* 39502 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(39607), // Rule ID 1734 //
15667 /* 39507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15668 /* 39511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
15669 /* 39515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15670 /* 39519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15671 /* 39523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15672 /* 39528 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15673 /* 39532 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15674 /* 39536 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15675 /* 39540 */ // MIs[2] Operand 1
15676 /* 39540 */ // No operand predicates
15677 /* 39540 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15678 /* 39542 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15679 /* 39542 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15680 /* 39545 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
15681 /* 39549 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15682 /* 39554 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15683 /* 39558 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15684 /* 39561 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15685 /* 39563 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15686 /* 39566 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15687 /* 39570 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15688 /* 39575 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15689 /* 39577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15690 /* 39580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15691 /* 39582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15692 /* 39585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15693 /* 39588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15694 /* 39591 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15695 /* 39596 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15696 /* 39601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15697 /* 39606 */ // GIR_Coverage, 1734,
15698 /* 39606 */ GIR_EraseRootFromParent_Done,
15699 /* 39607 */ // Label 1058: @39607
15700 /* 39607 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(39712), // Rule ID 1730 //
15701 /* 39612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15702 /* 39616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15703 /* 39620 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15704 /* 39624 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15705 /* 39628 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15706 /* 39633 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15707 /* 39637 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15708 /* 39641 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15709 /* 39645 */ // MIs[2] Operand 1
15710 /* 39645 */ // No operand predicates
15711 /* 39645 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15712 /* 39647 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15713 /* 39647 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15714 /* 39650 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
15715 /* 39654 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15716 /* 39659 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15717 /* 39663 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15718 /* 39666 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15719 /* 39668 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15720 /* 39671 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15721 /* 39675 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15722 /* 39680 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15723 /* 39682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15724 /* 39685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15725 /* 39687 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15726 /* 39690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15727 /* 39693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15728 /* 39696 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15729 /* 39701 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15730 /* 39706 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15731 /* 39711 */ // GIR_Coverage, 1730,
15732 /* 39711 */ GIR_EraseRootFromParent_Done,
15733 /* 39712 */ // Label 1059: @39712
15734 /* 39712 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(39817), // Rule ID 1726 //
15735 /* 39717 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15736 /* 39721 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15737 /* 39725 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15738 /* 39729 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15739 /* 39733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15740 /* 39738 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15741 /* 39742 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15742 /* 39746 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15743 /* 39750 */ // MIs[2] Operand 1
15744 /* 39750 */ // No operand predicates
15745 /* 39750 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15746 /* 39752 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15747 /* 39752 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15748 /* 39755 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
15749 /* 39759 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15750 /* 39764 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15751 /* 39768 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15752 /* 39771 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15753 /* 39773 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15754 /* 39776 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15755 /* 39780 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15756 /* 39785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15757 /* 39787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15758 /* 39790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15759 /* 39792 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15760 /* 39795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15761 /* 39798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15762 /* 39801 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15763 /* 39806 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15764 /* 39811 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15765 /* 39816 */ // GIR_Coverage, 1726,
15766 /* 39816 */ GIR_EraseRootFromParent_Done,
15767 /* 39817 */ // Label 1060: @39817
15768 /* 39817 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(39916), // Rule ID 1716 //
15769 /* 39822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15770 /* 39826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
15771 /* 39830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15772 /* 39834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15773 /* 39838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15774 /* 39843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15775 /* 39848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15776 /* 39850 */ // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15777 /* 39850 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15778 /* 39853 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
15779 /* 39857 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15780 /* 39862 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15781 /* 39866 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15782 /* 39870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15783 /* 39872 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15784 /* 39875 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15785 /* 39879 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15786 /* 39884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15787 /* 39886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15788 /* 39889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15789 /* 39891 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15790 /* 39894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15791 /* 39897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15792 /* 39900 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15793 /* 39905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15794 /* 39910 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15795 /* 39915 */ // GIR_Coverage, 1716,
15796 /* 39915 */ GIR_EraseRootFromParent_Done,
15797 /* 39916 */ // Label 1061: @39916
15798 /* 39916 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(40015), // Rule ID 1736 //
15799 /* 39921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15800 /* 39925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
15801 /* 39929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15802 /* 39933 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15803 /* 39937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15804 /* 39942 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15805 /* 39947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15806 /* 39949 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15807 /* 39949 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15808 /* 39952 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
15809 /* 39956 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15810 /* 39961 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15811 /* 39965 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15812 /* 39969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15813 /* 39971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15814 /* 39974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15815 /* 39978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15816 /* 39983 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15817 /* 39985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15818 /* 39988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15819 /* 39990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15820 /* 39993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15821 /* 39996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15822 /* 39999 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15823 /* 40004 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15824 /* 40009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15825 /* 40014 */ // GIR_Coverage, 1736,
15826 /* 40014 */ GIR_EraseRootFromParent_Done,
15827 /* 40015 */ // Label 1062: @40015
15828 /* 40015 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(40114), // Rule ID 1732 //
15829 /* 40020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15830 /* 40024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15831 /* 40028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15832 /* 40032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15833 /* 40036 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15834 /* 40041 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15835 /* 40046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15836 /* 40048 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15837 /* 40048 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15838 /* 40051 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
15839 /* 40055 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15840 /* 40060 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15841 /* 40064 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15842 /* 40068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15843 /* 40070 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15844 /* 40073 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15845 /* 40077 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15846 /* 40082 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15847 /* 40084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15848 /* 40087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15849 /* 40089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15850 /* 40092 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15851 /* 40095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15852 /* 40098 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15853 /* 40103 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15854 /* 40108 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15855 /* 40113 */ // GIR_Coverage, 1732,
15856 /* 40113 */ GIR_EraseRootFromParent_Done,
15857 /* 40114 */ // Label 1063: @40114
15858 /* 40114 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(40222), // Rule ID 1720 //
15859 /* 40119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6),
15860 /* 40122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15861 /* 40126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15862 /* 40130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15863 /* 40134 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15864 /* 40138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15865 /* 40143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15866 /* 40148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15867 /* 40150 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15868 /* 40150 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15869 /* 40153 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
15870 /* 40157 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15871 /* 40162 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15872 /* 40166 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15873 /* 40170 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
15874 /* 40173 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
15875 /* 40176 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15876 /* 40178 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15877 /* 40181 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15878 /* 40185 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15879 /* 40190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15880 /* 40192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15881 /* 40195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15882 /* 40197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15883 /* 40200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15884 /* 40203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15885 /* 40206 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15886 /* 40211 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15887 /* 40216 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15888 /* 40221 */ // GIR_Coverage, 1720,
15889 /* 40221 */ GIR_EraseRootFromParent_Done,
15890 /* 40222 */ // Label 1064: @40222
15891 /* 40222 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(40324), // Rule ID 1931 //
15892 /* 40227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15893 /* 40230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15894 /* 40234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15895 /* 40238 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15896 /* 40242 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15897 /* 40246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15898 /* 40251 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15899 /* 40256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15900 /* 40258 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15901 /* 40258 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15902 /* 40261 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
15903 /* 40265 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15904 /* 40270 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15905 /* 40274 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15906 /* 40278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15907 /* 40280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15908 /* 40283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15909 /* 40287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15910 /* 40292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15911 /* 40294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15912 /* 40297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15913 /* 40299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15914 /* 40302 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15915 /* 40305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15916 /* 40308 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15917 /* 40313 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15918 /* 40318 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15919 /* 40323 */ // GIR_Coverage, 1931,
15920 /* 40323 */ GIR_EraseRootFromParent_Done,
15921 /* 40324 */ // Label 1065: @40324
15922 /* 40324 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(40426), // Rule ID 1932 //
15923 /* 40329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15924 /* 40332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15925 /* 40336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
15926 /* 40340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15927 /* 40344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15928 /* 40348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15929 /* 40353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15930 /* 40358 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15931 /* 40360 */ // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15932 /* 40360 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15933 /* 40363 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
15934 /* 40367 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15935 /* 40372 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15936 /* 40376 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15937 /* 40380 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15938 /* 40382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15939 /* 40385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15940 /* 40389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15941 /* 40394 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15942 /* 40396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15943 /* 40399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15944 /* 40401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15945 /* 40404 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15946 /* 40407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15947 /* 40410 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15948 /* 40415 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15949 /* 40420 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15950 /* 40425 */ // GIR_Coverage, 1932,
15951 /* 40425 */ GIR_EraseRootFromParent_Done,
15952 /* 40426 */ // Label 1066: @40426
15953 /* 40426 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(40525), // Rule ID 1728 //
15954 /* 40431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15955 /* 40435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15956 /* 40439 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15957 /* 40443 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15958 /* 40447 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15959 /* 40452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15960 /* 40457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15961 /* 40459 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15962 /* 40459 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15963 /* 40462 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15964 /* 40466 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15965 /* 40471 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15966 /* 40475 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15967 /* 40479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15968 /* 40481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15969 /* 40484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15970 /* 40488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15971 /* 40493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15972 /* 40495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15973 /* 40498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15974 /* 40500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15975 /* 40503 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15976 /* 40506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15977 /* 40509 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15978 /* 40514 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15979 /* 40519 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15980 /* 40524 */ // GIR_Coverage, 1728,
15981 /* 40524 */ GIR_EraseRootFromParent_Done,
15982 /* 40525 */ // Label 1067: @40525
15983 /* 40525 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(40627), // Rule ID 1934 //
15984 /* 40530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15985 /* 40533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15986 /* 40537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
15987 /* 40541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15988 /* 40545 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15989 /* 40549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15990 /* 40554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15991 /* 40559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15992 /* 40561 */ // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15993 /* 40561 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15994 /* 40564 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
15995 /* 40568 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15996 /* 40573 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15997 /* 40577 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15998 /* 40581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15999 /* 40583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16000 /* 40586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16001 /* 40590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16002 /* 40595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16003 /* 40597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16004 /* 40600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16005 /* 40602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16006 /* 40605 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16007 /* 40608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16008 /* 40611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16009 /* 40616 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16010 /* 40621 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16011 /* 40626 */ // GIR_Coverage, 1934,
16012 /* 40626 */ GIR_EraseRootFromParent_Done,
16013 /* 40627 */ // Label 1068: @40627
16014 /* 40627 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(40726), // Rule ID 1718 //
16015 /* 40632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16016 /* 40636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
16017 /* 40640 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16018 /* 40644 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16019 /* 40648 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16020 /* 40653 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16021 /* 40658 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16022 /* 40660 */ // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16023 /* 40660 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16024 /* 40663 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
16025 /* 40667 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16026 /* 40672 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16027 /* 40676 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16028 /* 40680 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16029 /* 40682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16030 /* 40685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16031 /* 40689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16032 /* 40694 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16033 /* 40696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16034 /* 40699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16035 /* 40701 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16036 /* 40704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16037 /* 40707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16038 /* 40710 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16039 /* 40715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16040 /* 40720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16041 /* 40725 */ // GIR_Coverage, 1718,
16042 /* 40725 */ GIR_EraseRootFromParent_Done,
16043 /* 40726 */ // Label 1069: @40726
16044 /* 40726 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(40828), // Rule ID 1933 //
16045 /* 40731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
16046 /* 40734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16047 /* 40738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
16048 /* 40742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16049 /* 40746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16050 /* 40750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16051 /* 40755 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16052 /* 40760 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16053 /* 40762 */ // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16054 /* 40762 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16055 /* 40765 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
16056 /* 40769 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16057 /* 40774 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16058 /* 40778 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16059 /* 40782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16060 /* 40784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16061 /* 40787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16062 /* 40791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16063 /* 40796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16064 /* 40798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16065 /* 40801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16066 /* 40803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16067 /* 40806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16068 /* 40809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16069 /* 40812 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16070 /* 40817 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16071 /* 40822 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16072 /* 40827 */ // GIR_Coverage, 1933,
16073 /* 40827 */ GIR_EraseRootFromParent_Done,
16074 /* 40828 */ // Label 1070: @40828
16075 /* 40828 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(40930), // Rule ID 1935 //
16076 /* 40833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
16077 /* 40836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16078 /* 40840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
16079 /* 40844 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16080 /* 40848 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16081 /* 40852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16082 /* 40857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16083 /* 40862 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16084 /* 40864 */ // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16085 /* 40864 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16086 /* 40867 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
16087 /* 40871 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16088 /* 40876 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16089 /* 40880 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16090 /* 40884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16091 /* 40886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16092 /* 40889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16093 /* 40893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16094 /* 40898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16095 /* 40900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16096 /* 40903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16097 /* 40905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16098 /* 40908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16099 /* 40911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16100 /* 40914 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16101 /* 40919 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16102 /* 40924 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16103 /* 40929 */ // GIR_Coverage, 1935,
16104 /* 40929 */ GIR_EraseRootFromParent_Done,
16105 /* 40930 */ // Label 1071: @40930
16106 /* 40930 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(40949), // Rule ID 1688 //
16107 /* 40935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16108 /* 40938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16109 /* 40942 */ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
16110 /* 40942 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
16111 /* 40947 */ GIR_RootConstrainSelectedInstOperands,
16112 /* 40948 */ // GIR_Coverage, 1688,
16113 /* 40948 */ GIR_Done,
16114 /* 40949 */ // Label 1072: @40949
16115 /* 40949 */ GIM_Reject,
16116 /* 40950 */ // Label 1057: @40950
16117 /* 40950 */ GIM_Reject,
16118 /* 40951 */ // Label 35: @40951
16119 /* 40951 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1075*/ GIMT_Encode4(41298),
16120 /* 40962 */ /*GILLT_s32*//*Label 1073*/ GIMT_Encode4(40970),
16121 /* 40966 */ /*GILLT_s64*//*Label 1074*/ GIMT_Encode4(41196),
16122 /* 40970 */ // Label 1073: @40970
16123 /* 40970 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(41195),
16124 /* 40975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16125 /* 40978 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(41014), // Rule ID 106 //
16126 /* 40983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16127 /* 40986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16128 /* 40990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16129 /* 40994 */ // MIs[0] Operand 2
16130 /* 40994 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16131 /* 41005 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16132 /* 41005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
16133 /* 41008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16134 /* 41010 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16135 /* 41012 */ GIR_RootConstrainSelectedInstOperands,
16136 /* 41013 */ // GIR_Coverage, 106,
16137 /* 41013 */ GIR_EraseRootFromParent_Done,
16138 /* 41014 */ // Label 1077: @41014
16139 /* 41014 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(41050), // Rule ID 107 //
16140 /* 41019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16141 /* 41022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16142 /* 41026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16143 /* 41030 */ // MIs[0] Operand 2
16144 /* 41030 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16145 /* 41041 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16146 /* 41041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
16147 /* 41044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16148 /* 41046 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16149 /* 41048 */ GIR_RootConstrainSelectedInstOperands,
16150 /* 41049 */ // GIR_Coverage, 107,
16151 /* 41049 */ GIR_EraseRootFromParent_Done,
16152 /* 41050 */ // Label 1078: @41050
16153 /* 41050 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(41086), // Rule ID 1125 //
16154 /* 41055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16155 /* 41058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16156 /* 41062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16157 /* 41066 */ // MIs[0] Operand 2
16158 /* 41066 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16159 /* 41077 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16160 /* 41077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
16161 /* 41080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16162 /* 41082 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16163 /* 41084 */ GIR_RootConstrainSelectedInstOperands,
16164 /* 41085 */ // GIR_Coverage, 1125,
16165 /* 41085 */ GIR_EraseRootFromParent_Done,
16166 /* 41086 */ // Label 1079: @41086
16167 /* 41086 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(41122), // Rule ID 1126 //
16168 /* 41091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16169 /* 41094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16170 /* 41098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16171 /* 41102 */ // MIs[0] Operand 2
16172 /* 41102 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16173 /* 41113 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16174 /* 41113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
16175 /* 41116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16176 /* 41118 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16177 /* 41120 */ GIR_RootConstrainSelectedInstOperands,
16178 /* 41121 */ // GIR_Coverage, 1126,
16179 /* 41121 */ GIR_EraseRootFromParent_Done,
16180 /* 41122 */ // Label 1080: @41122
16181 /* 41122 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(41158), // Rule ID 2038 //
16182 /* 41127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16183 /* 41130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16184 /* 41134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16185 /* 41138 */ // MIs[0] Operand 2
16186 /* 41138 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16187 /* 41149 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) => (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
16188 /* 41149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
16189 /* 41152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16190 /* 41154 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
16191 /* 41156 */ GIR_RootConstrainSelectedInstOperands,
16192 /* 41157 */ // GIR_Coverage, 2038,
16193 /* 41157 */ GIR_EraseRootFromParent_Done,
16194 /* 41158 */ // Label 1081: @41158
16195 /* 41158 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(41194), // Rule ID 2039 //
16196 /* 41163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16197 /* 41166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16198 /* 41170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16199 /* 41174 */ // MIs[0] Operand 2
16200 /* 41174 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16201 /* 41185 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) => (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
16202 /* 41185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
16203 /* 41188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16204 /* 41190 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
16205 /* 41192 */ GIR_RootConstrainSelectedInstOperands,
16206 /* 41193 */ // GIR_Coverage, 2039,
16207 /* 41193 */ GIR_EraseRootFromParent_Done,
16208 /* 41194 */ // Label 1082: @41194
16209 /* 41194 */ GIM_Reject,
16210 /* 41195 */ // Label 1076: @41195
16211 /* 41195 */ GIM_Reject,
16212 /* 41196 */ // Label 1074: @41196
16213 /* 41196 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(41297),
16214 /* 41201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16215 /* 41204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16216 /* 41208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16217 /* 41212 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(41240), // Rule ID 285 //
16218 /* 41217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
16219 /* 41220 */ // MIs[0] Operand 2
16220 /* 41220 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16221 /* 41231 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) => (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
16222 /* 41231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
16223 /* 41234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16224 /* 41236 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16225 /* 41238 */ GIR_RootConstrainSelectedInstOperands,
16226 /* 41239 */ // GIR_Coverage, 285,
16227 /* 41239 */ GIR_EraseRootFromParent_Done,
16228 /* 41240 */ // Label 1084: @41240
16229 /* 41240 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(41268), // Rule ID 286 //
16230 /* 41245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
16231 /* 41248 */ // MIs[0] Operand 2
16232 /* 41248 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16233 /* 41259 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) => (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
16234 /* 41259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
16235 /* 41262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16236 /* 41264 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16237 /* 41266 */ GIR_RootConstrainSelectedInstOperands,
16238 /* 41267 */ // GIR_Coverage, 286,
16239 /* 41267 */ GIR_EraseRootFromParent_Done,
16240 /* 41268 */ // Label 1085: @41268
16241 /* 41268 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(41296), // Rule ID 1691 //
16242 /* 41273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16243 /* 41276 */ // MIs[0] Operand 2
16244 /* 41276 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
16245 /* 41287 */ // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) => (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
16246 /* 41287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
16247 /* 41290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16248 /* 41292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16249 /* 41294 */ GIR_RootConstrainSelectedInstOperands,
16250 /* 41295 */ // GIR_Coverage, 1691,
16251 /* 41295 */ GIR_EraseRootFromParent_Done,
16252 /* 41296 */ // Label 1086: @41296
16253 /* 41296 */ GIM_Reject,
16254 /* 41297 */ // Label 1083: @41297
16255 /* 41297 */ GIM_Reject,
16256 /* 41298 */ // Label 1075: @41298
16257 /* 41298 */ GIM_Reject,
16258 /* 41299 */ // Label 36: @41299
16259 /* 41299 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(41499),
16260 /* 41304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
16261 /* 41307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16262 /* 41310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16263 /* 41314 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(41370), // Rule ID 304 //
16264 /* 41319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
16265 /* 41322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16266 /* 41326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16267 /* 41330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16268 /* 41334 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16269 /* 41338 */ // MIs[1] Operand 1
16270 /* 41338 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16271 /* 41343 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16272 /* 41348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16273 /* 41353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16274 /* 41355 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16275 /* 41355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
16276 /* 41358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16277 /* 41360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
16278 /* 41364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
16279 /* 41368 */ GIR_RootConstrainSelectedInstOperands,
16280 /* 41369 */ // GIR_Coverage, 304,
16281 /* 41369 */ GIR_EraseRootFromParent_Done,
16282 /* 41370 */ // Label 1088: @41370
16283 /* 41370 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(41426), // Rule ID 306 //
16284 /* 41375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
16285 /* 41378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16286 /* 41382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16287 /* 41386 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16288 /* 41390 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16289 /* 41394 */ // MIs[1] Operand 1
16290 /* 41394 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16291 /* 41399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16292 /* 41404 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16293 /* 41409 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16294 /* 41411 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16295 /* 41411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
16296 /* 41414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16297 /* 41416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
16298 /* 41420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
16299 /* 41424 */ GIR_RootConstrainSelectedInstOperands,
16300 /* 41425 */ // GIR_Coverage, 306,
16301 /* 41425 */ GIR_EraseRootFromParent_Done,
16302 /* 41426 */ // Label 1089: @41426
16303 /* 41426 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(41498),
16304 /* 41431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16305 /* 41435 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(41474), // Rule ID 1686 //
16306 /* 41440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16307 /* 41443 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
16308 /* 41443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16309 /* 41446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
16310 /* 41450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16311 /* 41455 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
16312 /* 41459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16313 /* 41461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
16314 /* 41464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16315 /* 41466 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16316 /* 41469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
16317 /* 41472 */ GIR_RootConstrainSelectedInstOperands,
16318 /* 41473 */ // GIR_Coverage, 1686,
16319 /* 41473 */ GIR_EraseRootFromParent_Done,
16320 /* 41474 */ // Label 1091: @41474
16321 /* 41474 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(41497), // Rule ID 1689 //
16322 /* 41479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips),
16323 /* 41482 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
16324 /* 41482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
16325 /* 41485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16326 /* 41487 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16327 /* 41489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16328 /* 41492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
16329 /* 41495 */ GIR_RootConstrainSelectedInstOperands,
16330 /* 41496 */ // GIR_Coverage, 1689,
16331 /* 41496 */ GIR_EraseRootFromParent_Done,
16332 /* 41497 */ // Label 1092: @41497
16333 /* 41497 */ GIM_Reject,
16334 /* 41498 */ // Label 1090: @41498
16335 /* 41498 */ GIM_Reject,
16336 /* 41499 */ // Label 1087: @41499
16337 /* 41499 */ GIM_Reject,
16338 /* 41500 */ // Label 37: @41500
16339 /* 41500 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1099*/ GIMT_Encode4(43296),
16340 /* 41511 */ /*GILLT_s32*//*Label 1093*/ GIMT_Encode4(41543),
16341 /* 41515 */ /*GILLT_s64*//*Label 1094*/ GIMT_Encode4(41805), GIMT_Encode4(0),
16342 /* 41523 */ /*GILLT_v16s8*//*Label 1095*/ GIMT_Encode4(41946), GIMT_Encode4(0),
16343 /* 41531 */ /*GILLT_v8s16*//*Label 1096*/ GIMT_Encode4(42598),
16344 /* 41535 */ /*GILLT_v4s32*//*Label 1097*/ GIMT_Encode4(42994),
16345 /* 41539 */ /*GILLT_v2s64*//*Label 1098*/ GIMT_Encode4(43262),
16346 /* 41543 */ // Label 1093: @41543
16347 /* 41543 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(41804),
16348 /* 41548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16349 /* 41551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16350 /* 41554 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(41596), // Rule ID 55 //
16351 /* 41559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16352 /* 41562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16353 /* 41566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16354 /* 41570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16355 /* 41574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16356 /* 41578 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16357 /* 41582 */ // MIs[1] Operand 1
16358 /* 41582 */ // No operand predicates
16359 /* 41582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16360 /* 41584 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16361 /* 41584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
16362 /* 41587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16363 /* 41589 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16364 /* 41591 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16365 /* 41594 */ GIR_RootConstrainSelectedInstOperands,
16366 /* 41595 */ // GIR_Coverage, 55,
16367 /* 41595 */ GIR_EraseRootFromParent_Done,
16368 /* 41596 */ // Label 1101: @41596
16369 /* 41596 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(41638), // Rule ID 1962 //
16370 /* 41601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16371 /* 41604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16372 /* 41608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16373 /* 41612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16374 /* 41616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16375 /* 41620 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16376 /* 41624 */ // MIs[1] Operand 1
16377 /* 41624 */ // No operand predicates
16378 /* 41624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16379 /* 41626 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16380 /* 41626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
16381 /* 41629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16382 /* 41631 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16383 /* 41633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16384 /* 41636 */ GIR_RootConstrainSelectedInstOperands,
16385 /* 41637 */ // GIR_Coverage, 1962,
16386 /* 41637 */ GIR_EraseRootFromParent_Done,
16387 /* 41638 */ // Label 1102: @41638
16388 /* 41638 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(41680), // Rule ID 2301 //
16389 /* 41643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16390 /* 41646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16391 /* 41650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16392 /* 41654 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16393 /* 41658 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16394 /* 41662 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16395 /* 41666 */ // MIs[1] Operand 1
16396 /* 41666 */ // No operand predicates
16397 /* 41666 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16398 /* 41668 */ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16399 /* 41668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
16400 /* 41671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16401 /* 41673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16402 /* 41675 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16403 /* 41678 */ GIR_RootConstrainSelectedInstOperands,
16404 /* 41679 */ // GIR_Coverage, 2301,
16405 /* 41679 */ GIR_EraseRootFromParent_Done,
16406 /* 41680 */ // Label 1103: @41680
16407 /* 41680 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(41722), // Rule ID 2302 //
16408 /* 41685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16409 /* 41688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16410 /* 41692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16411 /* 41696 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16412 /* 41700 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16413 /* 41704 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16414 /* 41708 */ // MIs[1] Operand 1
16415 /* 41708 */ // No operand predicates
16416 /* 41708 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16417 /* 41710 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16418 /* 41710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
16419 /* 41713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16420 /* 41715 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16421 /* 41717 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16422 /* 41720 */ GIR_RootConstrainSelectedInstOperands,
16423 /* 41721 */ // GIR_Coverage, 2302,
16424 /* 41721 */ GIR_EraseRootFromParent_Done,
16425 /* 41722 */ // Label 1104: @41722
16426 /* 41722 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(41749), // Rule ID 61 //
16427 /* 41727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16428 /* 41730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16429 /* 41734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16430 /* 41738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16431 /* 41742 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16432 /* 41742 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
16433 /* 41747 */ GIR_RootConstrainSelectedInstOperands,
16434 /* 41748 */ // GIR_Coverage, 61,
16435 /* 41748 */ GIR_Done,
16436 /* 41749 */ // Label 1105: @41749
16437 /* 41749 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(41776), // Rule ID 1965 //
16438 /* 41754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16439 /* 41757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16440 /* 41761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16441 /* 41765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16442 /* 41769 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16443 /* 41769 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
16444 /* 41774 */ GIR_RootConstrainSelectedInstOperands,
16445 /* 41775 */ // GIR_Coverage, 1965,
16446 /* 41775 */ GIR_Done,
16447 /* 41776 */ // Label 1106: @41776
16448 /* 41776 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(41803), // Rule ID 2303 //
16449 /* 41781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16450 /* 41784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16451 /* 41788 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16452 /* 41792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16453 /* 41796 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16454 /* 41796 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
16455 /* 41801 */ GIR_RootConstrainSelectedInstOperands,
16456 /* 41802 */ // GIR_Coverage, 2303,
16457 /* 41802 */ GIR_Done,
16458 /* 41803 */ // Label 1107: @41803
16459 /* 41803 */ GIM_Reject,
16460 /* 41804 */ // Label 1100: @41804
16461 /* 41804 */ GIM_Reject,
16462 /* 41805 */ // Label 1094: @41805
16463 /* 41805 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(41945),
16464 /* 41810 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16465 /* 41813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16466 /* 41816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16467 /* 41820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16468 /* 41824 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(41858), // Rule ID 234 //
16469 /* 41829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16470 /* 41832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16471 /* 41836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16472 /* 41840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16473 /* 41844 */ // MIs[1] Operand 1
16474 /* 41844 */ // No operand predicates
16475 /* 41844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16476 /* 41846 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16477 /* 41846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
16478 /* 41849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16479 /* 41851 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16480 /* 41853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16481 /* 41856 */ GIR_RootConstrainSelectedInstOperands,
16482 /* 41857 */ // GIR_Coverage, 234,
16483 /* 41857 */ GIR_EraseRootFromParent_Done,
16484 /* 41858 */ // Label 1109: @41858
16485 /* 41858 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(41925), // Rule ID 1679 //
16486 /* 41863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16487 /* 41866 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16488 /* 41870 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16489 /* 41874 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16490 /* 41878 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16491 /* 41883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16492 /* 41885 */ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16493 /* 41885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16494 /* 41888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16495 /* 41892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16496 /* 41897 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16497 /* 41903 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16498 /* 41908 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16499 /* 41913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
16500 /* 41916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16501 /* 41918 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16502 /* 41920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16503 /* 41923 */ GIR_RootConstrainSelectedInstOperands,
16504 /* 41924 */ // GIR_Coverage, 1679,
16505 /* 41924 */ GIR_EraseRootFromParent_Done,
16506 /* 41925 */ // Label 1110: @41925
16507 /* 41925 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(41944), // Rule ID 240 //
16508 /* 41930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16509 /* 41933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16510 /* 41937 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16511 /* 41937 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
16512 /* 41942 */ GIR_RootConstrainSelectedInstOperands,
16513 /* 41943 */ // GIR_Coverage, 240,
16514 /* 41943 */ GIR_Done,
16515 /* 41944 */ // Label 1111: @41944
16516 /* 41944 */ GIM_Reject,
16517 /* 41945 */ // Label 1108: @41945
16518 /* 41945 */ GIM_Reject,
16519 /* 41946 */ // Label 1095: @41946
16520 /* 41946 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(42597),
16521 /* 41951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16522 /* 41954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16523 /* 41957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16524 /* 41961 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(42267), // Rule ID 2635 //
16525 /* 41966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16526 /* 41969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16527 /* 41973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16528 /* 41977 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16529 /* 41981 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16530 /* 41985 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16531 /* 41989 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16532 /* 41993 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16533 /* 41996 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16534 /* 42000 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16535 /* 42004 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16536 /* 42008 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16537 /* 42012 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16538 /* 42016 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16539 /* 42020 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16540 /* 42024 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16541 /* 42028 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16542 /* 42032 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16543 /* 42036 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16544 /* 42040 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16545 /* 42044 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16546 /* 42048 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16547 /* 42052 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16548 /* 42056 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16549 /* 42060 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16550 /* 42064 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16551 /* 42068 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16552 /* 42072 */ // MIs[3] Operand 1
16553 /* 42072 */ // No operand predicates
16554 /* 42072 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16555 /* 42076 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16556 /* 42080 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16557 /* 42084 */ // MIs[4] Operand 1
16558 /* 42084 */ // No operand predicates
16559 /* 42084 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16560 /* 42088 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16561 /* 42092 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16562 /* 42096 */ // MIs[5] Operand 1
16563 /* 42096 */ // No operand predicates
16564 /* 42096 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16565 /* 42100 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16566 /* 42104 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16567 /* 42108 */ // MIs[6] Operand 1
16568 /* 42108 */ // No operand predicates
16569 /* 42108 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16570 /* 42112 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16571 /* 42116 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16572 /* 42120 */ // MIs[7] Operand 1
16573 /* 42120 */ // No operand predicates
16574 /* 42120 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16575 /* 42124 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16576 /* 42128 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16577 /* 42132 */ // MIs[8] Operand 1
16578 /* 42132 */ // No operand predicates
16579 /* 42132 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16580 /* 42136 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16581 /* 42140 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16582 /* 42144 */ // MIs[9] Operand 1
16583 /* 42144 */ // No operand predicates
16584 /* 42144 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16585 /* 42148 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16586 /* 42152 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16587 /* 42156 */ // MIs[10] Operand 1
16588 /* 42156 */ // No operand predicates
16589 /* 42156 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16590 /* 42160 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16591 /* 42164 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16592 /* 42168 */ // MIs[11] Operand 1
16593 /* 42168 */ // No operand predicates
16594 /* 42168 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16595 /* 42172 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16596 /* 42176 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16597 /* 42180 */ // MIs[12] Operand 1
16598 /* 42180 */ // No operand predicates
16599 /* 42180 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16600 /* 42184 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16601 /* 42188 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16602 /* 42192 */ // MIs[13] Operand 1
16603 /* 42192 */ // No operand predicates
16604 /* 42192 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16605 /* 42196 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16606 /* 42200 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16607 /* 42204 */ // MIs[14] Operand 1
16608 /* 42204 */ // No operand predicates
16609 /* 42204 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16610 /* 42208 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16611 /* 42212 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16612 /* 42216 */ // MIs[15] Operand 1
16613 /* 42216 */ // No operand predicates
16614 /* 42216 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16615 /* 42220 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16616 /* 42224 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16617 /* 42228 */ // MIs[16] Operand 1
16618 /* 42228 */ // No operand predicates
16619 /* 42228 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16620 /* 42232 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16621 /* 42236 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16622 /* 42240 */ // MIs[17] Operand 1
16623 /* 42240 */ // No operand predicates
16624 /* 42240 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16625 /* 42244 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16626 /* 42248 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16627 /* 42252 */ // MIs[18] Operand 1
16628 /* 42252 */ // No operand predicates
16629 /* 42252 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16630 /* 42254 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16631 /* 42254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16632 /* 42257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16633 /* 42259 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16634 /* 42261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16635 /* 42265 */ GIR_RootConstrainSelectedInstOperands,
16636 /* 42266 */ // GIR_Coverage, 2635,
16637 /* 42266 */ GIR_EraseRootFromParent_Done,
16638 /* 42267 */ // Label 1113: @42267
16639 /* 42267 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(42573), // Rule ID 2200 //
16640 /* 42272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16641 /* 42275 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16642 /* 42279 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16643 /* 42283 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16644 /* 42287 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16645 /* 42291 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16646 /* 42295 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16647 /* 42299 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16648 /* 42302 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16649 /* 42306 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16650 /* 42310 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16651 /* 42314 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16652 /* 42318 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16653 /* 42322 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16654 /* 42326 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16655 /* 42330 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16656 /* 42334 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16657 /* 42338 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16658 /* 42342 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16659 /* 42346 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16660 /* 42350 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16661 /* 42354 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16662 /* 42358 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16663 /* 42362 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16664 /* 42366 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16665 /* 42370 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16666 /* 42374 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16667 /* 42378 */ // MIs[3] Operand 1
16668 /* 42378 */ // No operand predicates
16669 /* 42378 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16670 /* 42382 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16671 /* 42386 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16672 /* 42390 */ // MIs[4] Operand 1
16673 /* 42390 */ // No operand predicates
16674 /* 42390 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16675 /* 42394 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16676 /* 42398 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16677 /* 42402 */ // MIs[5] Operand 1
16678 /* 42402 */ // No operand predicates
16679 /* 42402 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16680 /* 42406 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16681 /* 42410 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16682 /* 42414 */ // MIs[6] Operand 1
16683 /* 42414 */ // No operand predicates
16684 /* 42414 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16685 /* 42418 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16686 /* 42422 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16687 /* 42426 */ // MIs[7] Operand 1
16688 /* 42426 */ // No operand predicates
16689 /* 42426 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16690 /* 42430 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16691 /* 42434 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16692 /* 42438 */ // MIs[8] Operand 1
16693 /* 42438 */ // No operand predicates
16694 /* 42438 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16695 /* 42442 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16696 /* 42446 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16697 /* 42450 */ // MIs[9] Operand 1
16698 /* 42450 */ // No operand predicates
16699 /* 42450 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16700 /* 42454 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16701 /* 42458 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16702 /* 42462 */ // MIs[10] Operand 1
16703 /* 42462 */ // No operand predicates
16704 /* 42462 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16705 /* 42466 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16706 /* 42470 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16707 /* 42474 */ // MIs[11] Operand 1
16708 /* 42474 */ // No operand predicates
16709 /* 42474 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16710 /* 42478 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16711 /* 42482 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16712 /* 42486 */ // MIs[12] Operand 1
16713 /* 42486 */ // No operand predicates
16714 /* 42486 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16715 /* 42490 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16716 /* 42494 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16717 /* 42498 */ // MIs[13] Operand 1
16718 /* 42498 */ // No operand predicates
16719 /* 42498 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16720 /* 42502 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16721 /* 42506 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16722 /* 42510 */ // MIs[14] Operand 1
16723 /* 42510 */ // No operand predicates
16724 /* 42510 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16725 /* 42514 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16726 /* 42518 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16727 /* 42522 */ // MIs[15] Operand 1
16728 /* 42522 */ // No operand predicates
16729 /* 42522 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16730 /* 42526 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16731 /* 42530 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16732 /* 42534 */ // MIs[16] Operand 1
16733 /* 42534 */ // No operand predicates
16734 /* 42534 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16735 /* 42538 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16736 /* 42542 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16737 /* 42546 */ // MIs[17] Operand 1
16738 /* 42546 */ // No operand predicates
16739 /* 42546 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16740 /* 42550 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16741 /* 42554 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16742 /* 42558 */ // MIs[18] Operand 1
16743 /* 42558 */ // No operand predicates
16744 /* 42558 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16745 /* 42560 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16746 /* 42560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16747 /* 42563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16748 /* 42565 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16749 /* 42567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16750 /* 42571 */ GIR_RootConstrainSelectedInstOperands,
16751 /* 42572 */ // GIR_Coverage, 2200,
16752 /* 42572 */ GIR_EraseRootFromParent_Done,
16753 /* 42573 */ // Label 1114: @42573
16754 /* 42573 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(42596), // Rule ID 981 //
16755 /* 42578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16756 /* 42581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16757 /* 42585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16758 /* 42589 */ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
16759 /* 42589 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16760 /* 42594 */ GIR_RootConstrainSelectedInstOperands,
16761 /* 42595 */ // GIR_Coverage, 981,
16762 /* 42595 */ GIR_Done,
16763 /* 42596 */ // Label 1115: @42596
16764 /* 42596 */ GIM_Reject,
16765 /* 42597 */ // Label 1112: @42597
16766 /* 42597 */ GIM_Reject,
16767 /* 42598 */ // Label 1096: @42598
16768 /* 42598 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(42993),
16769 /* 42603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16770 /* 42606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16771 /* 42609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16772 /* 42613 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(42791), // Rule ID 2636 //
16773 /* 42618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16774 /* 42621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16775 /* 42625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16776 /* 42629 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16777 /* 42633 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16778 /* 42637 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16779 /* 42641 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16780 /* 42645 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16781 /* 42648 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16782 /* 42652 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16783 /* 42656 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16784 /* 42660 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16785 /* 42664 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16786 /* 42668 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16787 /* 42672 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16788 /* 42676 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16789 /* 42680 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16790 /* 42684 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16791 /* 42688 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16792 /* 42692 */ // MIs[3] Operand 1
16793 /* 42692 */ // No operand predicates
16794 /* 42692 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16795 /* 42696 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16796 /* 42700 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16797 /* 42704 */ // MIs[4] Operand 1
16798 /* 42704 */ // No operand predicates
16799 /* 42704 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16800 /* 42708 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16801 /* 42712 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16802 /* 42716 */ // MIs[5] Operand 1
16803 /* 42716 */ // No operand predicates
16804 /* 42716 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16805 /* 42720 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16806 /* 42724 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16807 /* 42728 */ // MIs[6] Operand 1
16808 /* 42728 */ // No operand predicates
16809 /* 42728 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16810 /* 42732 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16811 /* 42736 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16812 /* 42740 */ // MIs[7] Operand 1
16813 /* 42740 */ // No operand predicates
16814 /* 42740 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16815 /* 42744 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16816 /* 42748 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16817 /* 42752 */ // MIs[8] Operand 1
16818 /* 42752 */ // No operand predicates
16819 /* 42752 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16820 /* 42756 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16821 /* 42760 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16822 /* 42764 */ // MIs[9] Operand 1
16823 /* 42764 */ // No operand predicates
16824 /* 42764 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16825 /* 42768 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16826 /* 42772 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16827 /* 42776 */ // MIs[10] Operand 1
16828 /* 42776 */ // No operand predicates
16829 /* 42776 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16830 /* 42778 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16831 /* 42778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16832 /* 42781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16833 /* 42783 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16834 /* 42785 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16835 /* 42789 */ GIR_RootConstrainSelectedInstOperands,
16836 /* 42790 */ // GIR_Coverage, 2636,
16837 /* 42790 */ GIR_EraseRootFromParent_Done,
16838 /* 42791 */ // Label 1117: @42791
16839 /* 42791 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(42969), // Rule ID 2201 //
16840 /* 42796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16841 /* 42799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16842 /* 42803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16843 /* 42807 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16844 /* 42811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16845 /* 42815 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16846 /* 42819 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16847 /* 42823 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16848 /* 42826 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16849 /* 42830 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16850 /* 42834 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16851 /* 42838 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16852 /* 42842 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16853 /* 42846 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16854 /* 42850 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16855 /* 42854 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16856 /* 42858 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16857 /* 42862 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16858 /* 42866 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16859 /* 42870 */ // MIs[3] Operand 1
16860 /* 42870 */ // No operand predicates
16861 /* 42870 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16862 /* 42874 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16863 /* 42878 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16864 /* 42882 */ // MIs[4] Operand 1
16865 /* 42882 */ // No operand predicates
16866 /* 42882 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16867 /* 42886 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16868 /* 42890 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16869 /* 42894 */ // MIs[5] Operand 1
16870 /* 42894 */ // No operand predicates
16871 /* 42894 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16872 /* 42898 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16873 /* 42902 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16874 /* 42906 */ // MIs[6] Operand 1
16875 /* 42906 */ // No operand predicates
16876 /* 42906 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16877 /* 42910 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16878 /* 42914 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16879 /* 42918 */ // MIs[7] Operand 1
16880 /* 42918 */ // No operand predicates
16881 /* 42918 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16882 /* 42922 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16883 /* 42926 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16884 /* 42930 */ // MIs[8] Operand 1
16885 /* 42930 */ // No operand predicates
16886 /* 42930 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16887 /* 42934 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16888 /* 42938 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16889 /* 42942 */ // MIs[9] Operand 1
16890 /* 42942 */ // No operand predicates
16891 /* 42942 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16892 /* 42946 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16893 /* 42950 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16894 /* 42954 */ // MIs[10] Operand 1
16895 /* 42954 */ // No operand predicates
16896 /* 42954 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16897 /* 42956 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16898 /* 42956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16899 /* 42959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16900 /* 42961 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16901 /* 42963 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16902 /* 42967 */ GIR_RootConstrainSelectedInstOperands,
16903 /* 42968 */ // GIR_Coverage, 2201,
16904 /* 42968 */ GIR_EraseRootFromParent_Done,
16905 /* 42969 */ // Label 1118: @42969
16906 /* 42969 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(42992), // Rule ID 982 //
16907 /* 42974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16908 /* 42977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16909 /* 42981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16910 /* 42985 */ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16911 /* 42985 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16912 /* 42990 */ GIR_RootConstrainSelectedInstOperands,
16913 /* 42991 */ // GIR_Coverage, 982,
16914 /* 42991 */ GIR_Done,
16915 /* 42992 */ // Label 1119: @42992
16916 /* 42992 */ GIM_Reject,
16917 /* 42993 */ // Label 1116: @42993
16918 /* 42993 */ GIM_Reject,
16919 /* 42994 */ // Label 1097: @42994
16920 /* 42994 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(43261),
16921 /* 42999 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16922 /* 43002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16923 /* 43005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16924 /* 43009 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(43123), // Rule ID 2637 //
16925 /* 43014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16926 /* 43017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16927 /* 43021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16928 /* 43025 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16929 /* 43029 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16930 /* 43033 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16931 /* 43037 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16932 /* 43041 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16933 /* 43044 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16934 /* 43048 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16935 /* 43052 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16936 /* 43056 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16937 /* 43060 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16938 /* 43064 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16939 /* 43068 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16940 /* 43072 */ // MIs[3] Operand 1
16941 /* 43072 */ // No operand predicates
16942 /* 43072 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16943 /* 43076 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16944 /* 43080 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16945 /* 43084 */ // MIs[4] Operand 1
16946 /* 43084 */ // No operand predicates
16947 /* 43084 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16948 /* 43088 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16949 /* 43092 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16950 /* 43096 */ // MIs[5] Operand 1
16951 /* 43096 */ // No operand predicates
16952 /* 43096 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16953 /* 43100 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16954 /* 43104 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16955 /* 43108 */ // MIs[6] Operand 1
16956 /* 43108 */ // No operand predicates
16957 /* 43108 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16958 /* 43110 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16959 /* 43110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16960 /* 43113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16961 /* 43115 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16962 /* 43117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16963 /* 43121 */ GIR_RootConstrainSelectedInstOperands,
16964 /* 43122 */ // GIR_Coverage, 2637,
16965 /* 43122 */ GIR_EraseRootFromParent_Done,
16966 /* 43123 */ // Label 1121: @43123
16967 /* 43123 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(43237), // Rule ID 2202 //
16968 /* 43128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16969 /* 43131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16970 /* 43135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16971 /* 43139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16972 /* 43143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16973 /* 43147 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16974 /* 43151 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16975 /* 43155 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16976 /* 43158 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16977 /* 43162 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16978 /* 43166 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16979 /* 43170 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16980 /* 43174 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16981 /* 43178 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16982 /* 43182 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16983 /* 43186 */ // MIs[3] Operand 1
16984 /* 43186 */ // No operand predicates
16985 /* 43186 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16986 /* 43190 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16987 /* 43194 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16988 /* 43198 */ // MIs[4] Operand 1
16989 /* 43198 */ // No operand predicates
16990 /* 43198 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16991 /* 43202 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16992 /* 43206 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16993 /* 43210 */ // MIs[5] Operand 1
16994 /* 43210 */ // No operand predicates
16995 /* 43210 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16996 /* 43214 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16997 /* 43218 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16998 /* 43222 */ // MIs[6] Operand 1
16999 /* 43222 */ // No operand predicates
17000 /* 43222 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17001 /* 43224 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17002 /* 43224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
17003 /* 43227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17004 /* 43229 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17005 /* 43231 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17006 /* 43235 */ GIR_RootConstrainSelectedInstOperands,
17007 /* 43236 */ // GIR_Coverage, 2202,
17008 /* 43236 */ GIR_EraseRootFromParent_Done,
17009 /* 43237 */ // Label 1122: @43237
17010 /* 43237 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(43260), // Rule ID 983 //
17011 /* 43242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17012 /* 43245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17013 /* 43249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17014 /* 43253 */ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17015 /* 43253 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
17016 /* 43258 */ GIR_RootConstrainSelectedInstOperands,
17017 /* 43259 */ // GIR_Coverage, 983,
17018 /* 43259 */ GIR_Done,
17019 /* 43260 */ // Label 1123: @43260
17020 /* 43260 */ GIM_Reject,
17021 /* 43261 */ // Label 1120: @43261
17022 /* 43261 */ GIM_Reject,
17023 /* 43262 */ // Label 1098: @43262
17024 /* 43262 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(43295), // Rule ID 984 //
17025 /* 43267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17026 /* 43270 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17027 /* 43273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17028 /* 43276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17029 /* 43280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17030 /* 43284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17031 /* 43288 */ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17032 /* 43288 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
17033 /* 43293 */ GIR_RootConstrainSelectedInstOperands,
17034 /* 43294 */ // GIR_Coverage, 984,
17035 /* 43294 */ GIR_Done,
17036 /* 43295 */ // Label 1124: @43295
17037 /* 43295 */ GIM_Reject,
17038 /* 43296 */ // Label 1099: @43296
17039 /* 43296 */ GIM_Reject,
17040 /* 43297 */ // Label 38: @43297
17041 /* 43297 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1131*/ GIMT_Encode4(45093),
17042 /* 43308 */ /*GILLT_s32*//*Label 1125*/ GIMT_Encode4(43340),
17043 /* 43312 */ /*GILLT_s64*//*Label 1126*/ GIMT_Encode4(43602), GIMT_Encode4(0),
17044 /* 43320 */ /*GILLT_v16s8*//*Label 1127*/ GIMT_Encode4(43743), GIMT_Encode4(0),
17045 /* 43328 */ /*GILLT_v8s16*//*Label 1128*/ GIMT_Encode4(44395),
17046 /* 43332 */ /*GILLT_v4s32*//*Label 1129*/ GIMT_Encode4(44791),
17047 /* 43336 */ /*GILLT_v2s64*//*Label 1130*/ GIMT_Encode4(45059),
17048 /* 43340 */ // Label 1125: @43340
17049 /* 43340 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(43601),
17050 /* 43345 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17051 /* 43348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17052 /* 43351 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(43393), // Rule ID 57 //
17053 /* 43356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17054 /* 43359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17055 /* 43363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17056 /* 43367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17057 /* 43371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17058 /* 43375 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17059 /* 43379 */ // MIs[1] Operand 1
17060 /* 43379 */ // No operand predicates
17061 /* 43379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17062 /* 43381 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17063 /* 43381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
17064 /* 43384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17065 /* 43386 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17066 /* 43388 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17067 /* 43391 */ GIR_RootConstrainSelectedInstOperands,
17068 /* 43392 */ // GIR_Coverage, 57,
17069 /* 43392 */ GIR_EraseRootFromParent_Done,
17070 /* 43393 */ // Label 1133: @43393
17071 /* 43393 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(43435), // Rule ID 1963 //
17072 /* 43398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17073 /* 43401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17074 /* 43405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17075 /* 43409 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17076 /* 43413 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17077 /* 43417 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17078 /* 43421 */ // MIs[1] Operand 1
17079 /* 43421 */ // No operand predicates
17080 /* 43421 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17081 /* 43423 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17082 /* 43423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
17083 /* 43426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
17084 /* 43428 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17085 /* 43430 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17086 /* 43433 */ GIR_RootConstrainSelectedInstOperands,
17087 /* 43434 */ // GIR_Coverage, 1963,
17088 /* 43434 */ GIR_EraseRootFromParent_Done,
17089 /* 43435 */ // Label 1134: @43435
17090 /* 43435 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(43477), // Rule ID 2304 //
17091 /* 43440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17092 /* 43443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
17093 /* 43447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
17094 /* 43451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17095 /* 43455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17096 /* 43459 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
17097 /* 43463 */ // MIs[1] Operand 1
17098 /* 43463 */ // No operand predicates
17099 /* 43463 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17100 /* 43465 */ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
17101 /* 43465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
17102 /* 43468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17103 /* 43470 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17104 /* 43472 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17105 /* 43475 */ GIR_RootConstrainSelectedInstOperands,
17106 /* 43476 */ // GIR_Coverage, 2304,
17107 /* 43476 */ GIR_EraseRootFromParent_Done,
17108 /* 43477 */ // Label 1135: @43477
17109 /* 43477 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(43519), // Rule ID 2305 //
17110 /* 43482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17111 /* 43485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17112 /* 43489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17113 /* 43493 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17114 /* 43497 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17115 /* 43501 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17116 /* 43505 */ // MIs[1] Operand 1
17117 /* 43505 */ // No operand predicates
17118 /* 43505 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17119 /* 43507 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17120 /* 43507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
17121 /* 43510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17122 /* 43512 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17123 /* 43514 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17124 /* 43517 */ GIR_RootConstrainSelectedInstOperands,
17125 /* 43518 */ // GIR_Coverage, 2305,
17126 /* 43518 */ GIR_EraseRootFromParent_Done,
17127 /* 43519 */ // Label 1136: @43519
17128 /* 43519 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(43546), // Rule ID 63 //
17129 /* 43524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17130 /* 43527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17131 /* 43531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17132 /* 43535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17133 /* 43539 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17134 /* 43539 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
17135 /* 43544 */ GIR_RootConstrainSelectedInstOperands,
17136 /* 43545 */ // GIR_Coverage, 63,
17137 /* 43545 */ GIR_Done,
17138 /* 43546 */ // Label 1137: @43546
17139 /* 43546 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(43573), // Rule ID 1967 //
17140 /* 43551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17141 /* 43554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17142 /* 43558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17143 /* 43562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17144 /* 43566 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
17145 /* 43566 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
17146 /* 43571 */ GIR_RootConstrainSelectedInstOperands,
17147 /* 43572 */ // GIR_Coverage, 1967,
17148 /* 43572 */ GIR_Done,
17149 /* 43573 */ // Label 1138: @43573
17150 /* 43573 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(43600), // Rule ID 2306 //
17151 /* 43578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17152 /* 43581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17153 /* 43585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17154 /* 43589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17155 /* 43593 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
17156 /* 43593 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
17157 /* 43598 */ GIR_RootConstrainSelectedInstOperands,
17158 /* 43599 */ // GIR_Coverage, 2306,
17159 /* 43599 */ GIR_Done,
17160 /* 43600 */ // Label 1139: @43600
17161 /* 43600 */ GIM_Reject,
17162 /* 43601 */ // Label 1132: @43601
17163 /* 43601 */ GIM_Reject,
17164 /* 43602 */ // Label 1126: @43602
17165 /* 43602 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(43742),
17166 /* 43607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17167 /* 43610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17168 /* 43613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17169 /* 43617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17170 /* 43621 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(43655), // Rule ID 236 //
17171 /* 43626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17172 /* 43629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17173 /* 43633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17174 /* 43637 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17175 /* 43641 */ // MIs[1] Operand 1
17176 /* 43641 */ // No operand predicates
17177 /* 43641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17178 /* 43643 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17179 /* 43643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
17180 /* 43646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17181 /* 43648 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17182 /* 43650 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17183 /* 43653 */ GIR_RootConstrainSelectedInstOperands,
17184 /* 43654 */ // GIR_Coverage, 236,
17185 /* 43654 */ GIR_EraseRootFromParent_Done,
17186 /* 43655 */ // Label 1141: @43655
17187 /* 43655 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(43722), // Rule ID 1680 //
17188 /* 43660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17189 /* 43663 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17190 /* 43667 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17191 /* 43671 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17192 /* 43675 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17193 /* 43680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17194 /* 43682 */ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17195 /* 43682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17196 /* 43685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17197 /* 43689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17198 /* 43694 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17199 /* 43700 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17200 /* 43705 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17201 /* 43710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
17202 /* 43713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17203 /* 43715 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17204 /* 43717 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17205 /* 43720 */ GIR_RootConstrainSelectedInstOperands,
17206 /* 43721 */ // GIR_Coverage, 1680,
17207 /* 43721 */ GIR_EraseRootFromParent_Done,
17208 /* 43722 */ // Label 1142: @43722
17209 /* 43722 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(43741), // Rule ID 244 //
17210 /* 43727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17211 /* 43730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17212 /* 43734 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17213 /* 43734 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
17214 /* 43739 */ GIR_RootConstrainSelectedInstOperands,
17215 /* 43740 */ // GIR_Coverage, 244,
17216 /* 43740 */ GIR_Done,
17217 /* 43741 */ // Label 1143: @43741
17218 /* 43741 */ GIM_Reject,
17219 /* 43742 */ // Label 1140: @43742
17220 /* 43742 */ GIM_Reject,
17221 /* 43743 */ // Label 1127: @43743
17222 /* 43743 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(44394),
17223 /* 43748 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17224 /* 43751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17225 /* 43754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17226 /* 43758 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(44064), // Rule ID 2651 //
17227 /* 43763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17228 /* 43766 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17229 /* 43770 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17230 /* 43774 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17231 /* 43778 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17232 /* 43782 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17233 /* 43786 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17234 /* 43790 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17235 /* 43793 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17236 /* 43797 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17237 /* 43801 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17238 /* 43805 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17239 /* 43809 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17240 /* 43813 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17241 /* 43817 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17242 /* 43821 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17243 /* 43825 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17244 /* 43829 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17245 /* 43833 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17246 /* 43837 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17247 /* 43841 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17248 /* 43845 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17249 /* 43849 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17250 /* 43853 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17251 /* 43857 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17252 /* 43861 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17253 /* 43865 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17254 /* 43869 */ // MIs[3] Operand 1
17255 /* 43869 */ // No operand predicates
17256 /* 43869 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17257 /* 43873 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17258 /* 43877 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17259 /* 43881 */ // MIs[4] Operand 1
17260 /* 43881 */ // No operand predicates
17261 /* 43881 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17262 /* 43885 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17263 /* 43889 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17264 /* 43893 */ // MIs[5] Operand 1
17265 /* 43893 */ // No operand predicates
17266 /* 43893 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17267 /* 43897 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17268 /* 43901 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17269 /* 43905 */ // MIs[6] Operand 1
17270 /* 43905 */ // No operand predicates
17271 /* 43905 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17272 /* 43909 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17273 /* 43913 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17274 /* 43917 */ // MIs[7] Operand 1
17275 /* 43917 */ // No operand predicates
17276 /* 43917 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17277 /* 43921 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17278 /* 43925 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17279 /* 43929 */ // MIs[8] Operand 1
17280 /* 43929 */ // No operand predicates
17281 /* 43929 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17282 /* 43933 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17283 /* 43937 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17284 /* 43941 */ // MIs[9] Operand 1
17285 /* 43941 */ // No operand predicates
17286 /* 43941 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17287 /* 43945 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17288 /* 43949 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17289 /* 43953 */ // MIs[10] Operand 1
17290 /* 43953 */ // No operand predicates
17291 /* 43953 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17292 /* 43957 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17293 /* 43961 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17294 /* 43965 */ // MIs[11] Operand 1
17295 /* 43965 */ // No operand predicates
17296 /* 43965 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17297 /* 43969 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17298 /* 43973 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17299 /* 43977 */ // MIs[12] Operand 1
17300 /* 43977 */ // No operand predicates
17301 /* 43977 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17302 /* 43981 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17303 /* 43985 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17304 /* 43989 */ // MIs[13] Operand 1
17305 /* 43989 */ // No operand predicates
17306 /* 43989 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17307 /* 43993 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17308 /* 43997 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17309 /* 44001 */ // MIs[14] Operand 1
17310 /* 44001 */ // No operand predicates
17311 /* 44001 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17312 /* 44005 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17313 /* 44009 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17314 /* 44013 */ // MIs[15] Operand 1
17315 /* 44013 */ // No operand predicates
17316 /* 44013 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17317 /* 44017 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17318 /* 44021 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17319 /* 44025 */ // MIs[16] Operand 1
17320 /* 44025 */ // No operand predicates
17321 /* 44025 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17322 /* 44029 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17323 /* 44033 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17324 /* 44037 */ // MIs[17] Operand 1
17325 /* 44037 */ // No operand predicates
17326 /* 44037 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17327 /* 44041 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17328 /* 44045 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17329 /* 44049 */ // MIs[18] Operand 1
17330 /* 44049 */ // No operand predicates
17331 /* 44049 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17332 /* 44051 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17333 /* 44051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17334 /* 44054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17335 /* 44056 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17336 /* 44058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17337 /* 44062 */ GIR_RootConstrainSelectedInstOperands,
17338 /* 44063 */ // GIR_Coverage, 2651,
17339 /* 44063 */ GIR_EraseRootFromParent_Done,
17340 /* 44064 */ // Label 1145: @44064
17341 /* 44064 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(44370), // Rule ID 2208 //
17342 /* 44069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17343 /* 44072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17344 /* 44076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17345 /* 44080 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17346 /* 44084 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17347 /* 44088 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17348 /* 44092 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17349 /* 44096 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17350 /* 44099 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17351 /* 44103 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17352 /* 44107 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17353 /* 44111 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17354 /* 44115 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17355 /* 44119 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17356 /* 44123 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17357 /* 44127 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17358 /* 44131 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17359 /* 44135 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17360 /* 44139 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17361 /* 44143 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17362 /* 44147 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17363 /* 44151 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17364 /* 44155 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17365 /* 44159 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17366 /* 44163 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17367 /* 44167 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17368 /* 44171 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17369 /* 44175 */ // MIs[3] Operand 1
17370 /* 44175 */ // No operand predicates
17371 /* 44175 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17372 /* 44179 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17373 /* 44183 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17374 /* 44187 */ // MIs[4] Operand 1
17375 /* 44187 */ // No operand predicates
17376 /* 44187 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17377 /* 44191 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17378 /* 44195 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17379 /* 44199 */ // MIs[5] Operand 1
17380 /* 44199 */ // No operand predicates
17381 /* 44199 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17382 /* 44203 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17383 /* 44207 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17384 /* 44211 */ // MIs[6] Operand 1
17385 /* 44211 */ // No operand predicates
17386 /* 44211 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17387 /* 44215 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17388 /* 44219 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17389 /* 44223 */ // MIs[7] Operand 1
17390 /* 44223 */ // No operand predicates
17391 /* 44223 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17392 /* 44227 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17393 /* 44231 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17394 /* 44235 */ // MIs[8] Operand 1
17395 /* 44235 */ // No operand predicates
17396 /* 44235 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17397 /* 44239 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17398 /* 44243 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17399 /* 44247 */ // MIs[9] Operand 1
17400 /* 44247 */ // No operand predicates
17401 /* 44247 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17402 /* 44251 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17403 /* 44255 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17404 /* 44259 */ // MIs[10] Operand 1
17405 /* 44259 */ // No operand predicates
17406 /* 44259 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17407 /* 44263 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17408 /* 44267 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17409 /* 44271 */ // MIs[11] Operand 1
17410 /* 44271 */ // No operand predicates
17411 /* 44271 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17412 /* 44275 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17413 /* 44279 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17414 /* 44283 */ // MIs[12] Operand 1
17415 /* 44283 */ // No operand predicates
17416 /* 44283 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17417 /* 44287 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17418 /* 44291 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17419 /* 44295 */ // MIs[13] Operand 1
17420 /* 44295 */ // No operand predicates
17421 /* 44295 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17422 /* 44299 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17423 /* 44303 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17424 /* 44307 */ // MIs[14] Operand 1
17425 /* 44307 */ // No operand predicates
17426 /* 44307 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17427 /* 44311 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17428 /* 44315 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17429 /* 44319 */ // MIs[15] Operand 1
17430 /* 44319 */ // No operand predicates
17431 /* 44319 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17432 /* 44323 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17433 /* 44327 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17434 /* 44331 */ // MIs[16] Operand 1
17435 /* 44331 */ // No operand predicates
17436 /* 44331 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17437 /* 44335 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17438 /* 44339 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17439 /* 44343 */ // MIs[17] Operand 1
17440 /* 44343 */ // No operand predicates
17441 /* 44343 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17442 /* 44347 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17443 /* 44351 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17444 /* 44355 */ // MIs[18] Operand 1
17445 /* 44355 */ // No operand predicates
17446 /* 44355 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17447 /* 44357 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17448 /* 44357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17449 /* 44360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17450 /* 44362 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17451 /* 44364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17452 /* 44368 */ GIR_RootConstrainSelectedInstOperands,
17453 /* 44369 */ // GIR_Coverage, 2208,
17454 /* 44369 */ GIR_EraseRootFromParent_Done,
17455 /* 44370 */ // Label 1146: @44370
17456 /* 44370 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(44393), // Rule ID 1013 //
17457 /* 44375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17458 /* 44378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17459 /* 44382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17460 /* 44386 */ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17461 /* 44386 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17462 /* 44391 */ GIR_RootConstrainSelectedInstOperands,
17463 /* 44392 */ // GIR_Coverage, 1013,
17464 /* 44392 */ GIR_Done,
17465 /* 44393 */ // Label 1147: @44393
17466 /* 44393 */ GIM_Reject,
17467 /* 44394 */ // Label 1144: @44394
17468 /* 44394 */ GIM_Reject,
17469 /* 44395 */ // Label 1128: @44395
17470 /* 44395 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(44790),
17471 /* 44400 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17472 /* 44403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17473 /* 44406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17474 /* 44410 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(44588), // Rule ID 2652 //
17475 /* 44415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17476 /* 44418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17477 /* 44422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17478 /* 44426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17479 /* 44430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17480 /* 44434 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17481 /* 44438 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17482 /* 44442 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17483 /* 44445 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17484 /* 44449 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17485 /* 44453 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17486 /* 44457 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17487 /* 44461 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17488 /* 44465 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17489 /* 44469 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17490 /* 44473 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17491 /* 44477 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17492 /* 44481 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17493 /* 44485 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17494 /* 44489 */ // MIs[3] Operand 1
17495 /* 44489 */ // No operand predicates
17496 /* 44489 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17497 /* 44493 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17498 /* 44497 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17499 /* 44501 */ // MIs[4] Operand 1
17500 /* 44501 */ // No operand predicates
17501 /* 44501 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17502 /* 44505 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17503 /* 44509 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17504 /* 44513 */ // MIs[5] Operand 1
17505 /* 44513 */ // No operand predicates
17506 /* 44513 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17507 /* 44517 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17508 /* 44521 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17509 /* 44525 */ // MIs[6] Operand 1
17510 /* 44525 */ // No operand predicates
17511 /* 44525 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17512 /* 44529 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17513 /* 44533 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17514 /* 44537 */ // MIs[7] Operand 1
17515 /* 44537 */ // No operand predicates
17516 /* 44537 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17517 /* 44541 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17518 /* 44545 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17519 /* 44549 */ // MIs[8] Operand 1
17520 /* 44549 */ // No operand predicates
17521 /* 44549 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17522 /* 44553 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17523 /* 44557 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17524 /* 44561 */ // MIs[9] Operand 1
17525 /* 44561 */ // No operand predicates
17526 /* 44561 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17527 /* 44565 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17528 /* 44569 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17529 /* 44573 */ // MIs[10] Operand 1
17530 /* 44573 */ // No operand predicates
17531 /* 44573 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17532 /* 44575 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17533 /* 44575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17534 /* 44578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17535 /* 44580 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17536 /* 44582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17537 /* 44586 */ GIR_RootConstrainSelectedInstOperands,
17538 /* 44587 */ // GIR_Coverage, 2652,
17539 /* 44587 */ GIR_EraseRootFromParent_Done,
17540 /* 44588 */ // Label 1149: @44588
17541 /* 44588 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(44766), // Rule ID 2209 //
17542 /* 44593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17543 /* 44596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17544 /* 44600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17545 /* 44604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17546 /* 44608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17547 /* 44612 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17548 /* 44616 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17549 /* 44620 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17550 /* 44623 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17551 /* 44627 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17552 /* 44631 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17553 /* 44635 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17554 /* 44639 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17555 /* 44643 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17556 /* 44647 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17557 /* 44651 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17558 /* 44655 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17559 /* 44659 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17560 /* 44663 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17561 /* 44667 */ // MIs[3] Operand 1
17562 /* 44667 */ // No operand predicates
17563 /* 44667 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17564 /* 44671 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17565 /* 44675 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17566 /* 44679 */ // MIs[4] Operand 1
17567 /* 44679 */ // No operand predicates
17568 /* 44679 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17569 /* 44683 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17570 /* 44687 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17571 /* 44691 */ // MIs[5] Operand 1
17572 /* 44691 */ // No operand predicates
17573 /* 44691 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17574 /* 44695 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17575 /* 44699 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17576 /* 44703 */ // MIs[6] Operand 1
17577 /* 44703 */ // No operand predicates
17578 /* 44703 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17579 /* 44707 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17580 /* 44711 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17581 /* 44715 */ // MIs[7] Operand 1
17582 /* 44715 */ // No operand predicates
17583 /* 44715 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17584 /* 44719 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17585 /* 44723 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17586 /* 44727 */ // MIs[8] Operand 1
17587 /* 44727 */ // No operand predicates
17588 /* 44727 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17589 /* 44731 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17590 /* 44735 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17591 /* 44739 */ // MIs[9] Operand 1
17592 /* 44739 */ // No operand predicates
17593 /* 44739 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17594 /* 44743 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17595 /* 44747 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17596 /* 44751 */ // MIs[10] Operand 1
17597 /* 44751 */ // No operand predicates
17598 /* 44751 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17599 /* 44753 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17600 /* 44753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17601 /* 44756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17602 /* 44758 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17603 /* 44760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17604 /* 44764 */ GIR_RootConstrainSelectedInstOperands,
17605 /* 44765 */ // GIR_Coverage, 2209,
17606 /* 44765 */ GIR_EraseRootFromParent_Done,
17607 /* 44766 */ // Label 1150: @44766
17608 /* 44766 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(44789), // Rule ID 1014 //
17609 /* 44771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17610 /* 44774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17611 /* 44778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17612 /* 44782 */ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
17613 /* 44782 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17614 /* 44787 */ GIR_RootConstrainSelectedInstOperands,
17615 /* 44788 */ // GIR_Coverage, 1014,
17616 /* 44788 */ GIR_Done,
17617 /* 44789 */ // Label 1151: @44789
17618 /* 44789 */ GIM_Reject,
17619 /* 44790 */ // Label 1148: @44790
17620 /* 44790 */ GIM_Reject,
17621 /* 44791 */ // Label 1129: @44791
17622 /* 44791 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(45058),
17623 /* 44796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17624 /* 44799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17625 /* 44802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17626 /* 44806 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(44920), // Rule ID 2653 //
17627 /* 44811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17628 /* 44814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17629 /* 44818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17630 /* 44822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17631 /* 44826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17632 /* 44830 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17633 /* 44834 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17634 /* 44838 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17635 /* 44841 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17636 /* 44845 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17637 /* 44849 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17638 /* 44853 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17639 /* 44857 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17640 /* 44861 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17641 /* 44865 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17642 /* 44869 */ // MIs[3] Operand 1
17643 /* 44869 */ // No operand predicates
17644 /* 44869 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17645 /* 44873 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17646 /* 44877 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17647 /* 44881 */ // MIs[4] Operand 1
17648 /* 44881 */ // No operand predicates
17649 /* 44881 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17650 /* 44885 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17651 /* 44889 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17652 /* 44893 */ // MIs[5] Operand 1
17653 /* 44893 */ // No operand predicates
17654 /* 44893 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17655 /* 44897 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17656 /* 44901 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17657 /* 44905 */ // MIs[6] Operand 1
17658 /* 44905 */ // No operand predicates
17659 /* 44905 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17660 /* 44907 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17661 /* 44907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17662 /* 44910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17663 /* 44912 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17664 /* 44914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17665 /* 44918 */ GIR_RootConstrainSelectedInstOperands,
17666 /* 44919 */ // GIR_Coverage, 2653,
17667 /* 44919 */ GIR_EraseRootFromParent_Done,
17668 /* 44920 */ // Label 1153: @44920
17669 /* 44920 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(45034), // Rule ID 2210 //
17670 /* 44925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17671 /* 44928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17672 /* 44932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17673 /* 44936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17674 /* 44940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17675 /* 44944 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17676 /* 44948 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17677 /* 44952 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17678 /* 44955 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17679 /* 44959 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17680 /* 44963 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17681 /* 44967 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17682 /* 44971 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17683 /* 44975 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17684 /* 44979 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17685 /* 44983 */ // MIs[3] Operand 1
17686 /* 44983 */ // No operand predicates
17687 /* 44983 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17688 /* 44987 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17689 /* 44991 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17690 /* 44995 */ // MIs[4] Operand 1
17691 /* 44995 */ // No operand predicates
17692 /* 44995 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17693 /* 44999 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17694 /* 45003 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17695 /* 45007 */ // MIs[5] Operand 1
17696 /* 45007 */ // No operand predicates
17697 /* 45007 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17698 /* 45011 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17699 /* 45015 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17700 /* 45019 */ // MIs[6] Operand 1
17701 /* 45019 */ // No operand predicates
17702 /* 45019 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17703 /* 45021 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17704 /* 45021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17705 /* 45024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17706 /* 45026 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17707 /* 45028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17708 /* 45032 */ GIR_RootConstrainSelectedInstOperands,
17709 /* 45033 */ // GIR_Coverage, 2210,
17710 /* 45033 */ GIR_EraseRootFromParent_Done,
17711 /* 45034 */ // Label 1154: @45034
17712 /* 45034 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(45057), // Rule ID 1015 //
17713 /* 45039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17714 /* 45042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17715 /* 45046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17716 /* 45050 */ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17717 /* 45050 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17718 /* 45055 */ GIR_RootConstrainSelectedInstOperands,
17719 /* 45056 */ // GIR_Coverage, 1015,
17720 /* 45056 */ GIR_Done,
17721 /* 45057 */ // Label 1155: @45057
17722 /* 45057 */ GIM_Reject,
17723 /* 45058 */ // Label 1152: @45058
17724 /* 45058 */ GIM_Reject,
17725 /* 45059 */ // Label 1130: @45059
17726 /* 45059 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(45092), // Rule ID 1016 //
17727 /* 45064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17728 /* 45067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17729 /* 45070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17730 /* 45073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17731 /* 45077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17732 /* 45081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17733 /* 45085 */ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17734 /* 45085 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
17735 /* 45090 */ GIR_RootConstrainSelectedInstOperands,
17736 /* 45091 */ // GIR_Coverage, 1016,
17737 /* 45091 */ GIR_Done,
17738 /* 45092 */ // Label 1156: @45092
17739 /* 45092 */ GIM_Reject,
17740 /* 45093 */ // Label 1131: @45093
17741 /* 45093 */ GIM_Reject,
17742 /* 45094 */ // Label 39: @45094
17743 /* 45094 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1163*/ GIMT_Encode4(46848),
17744 /* 45105 */ /*GILLT_s32*//*Label 1157*/ GIMT_Encode4(45137),
17745 /* 45109 */ /*GILLT_s64*//*Label 1158*/ GIMT_Encode4(45357), GIMT_Encode4(0),
17746 /* 45117 */ /*GILLT_v16s8*//*Label 1159*/ GIMT_Encode4(45498), GIMT_Encode4(0),
17747 /* 45125 */ /*GILLT_v8s16*//*Label 1160*/ GIMT_Encode4(46150),
17748 /* 45129 */ /*GILLT_v4s32*//*Label 1161*/ GIMT_Encode4(46546),
17749 /* 45133 */ /*GILLT_v2s64*//*Label 1162*/ GIMT_Encode4(46814),
17750 /* 45137 */ // Label 1157: @45137
17751 /* 45137 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(45356),
17752 /* 45142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17753 /* 45145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17754 /* 45148 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(45190), // Rule ID 59 //
17755 /* 45153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17756 /* 45156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17757 /* 45160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17758 /* 45164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17759 /* 45168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17760 /* 45172 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17761 /* 45176 */ // MIs[1] Operand 1
17762 /* 45176 */ // No operand predicates
17763 /* 45176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17764 /* 45178 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17765 /* 45178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
17766 /* 45181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17767 /* 45183 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17768 /* 45185 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17769 /* 45188 */ GIR_RootConstrainSelectedInstOperands,
17770 /* 45189 */ // GIR_Coverage, 59,
17771 /* 45189 */ GIR_EraseRootFromParent_Done,
17772 /* 45190 */ // Label 1165: @45190
17773 /* 45190 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(45232), // Rule ID 1964 //
17774 /* 45195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17775 /* 45198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17776 /* 45202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17777 /* 45206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17778 /* 45210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17779 /* 45214 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17780 /* 45218 */ // MIs[1] Operand 1
17781 /* 45218 */ // No operand predicates
17782 /* 45218 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17783 /* 45220 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17784 /* 45220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
17785 /* 45223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
17786 /* 45225 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17787 /* 45227 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17788 /* 45230 */ GIR_RootConstrainSelectedInstOperands,
17789 /* 45231 */ // GIR_Coverage, 1964,
17790 /* 45231 */ GIR_EraseRootFromParent_Done,
17791 /* 45232 */ // Label 1166: @45232
17792 /* 45232 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(45274), // Rule ID 2307 //
17793 /* 45237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17794 /* 45240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17795 /* 45244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17796 /* 45248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17797 /* 45252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17798 /* 45256 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17799 /* 45260 */ // MIs[1] Operand 1
17800 /* 45260 */ // No operand predicates
17801 /* 45260 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17802 /* 45262 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17803 /* 45262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
17804 /* 45265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17805 /* 45267 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17806 /* 45269 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17807 /* 45272 */ GIR_RootConstrainSelectedInstOperands,
17808 /* 45273 */ // GIR_Coverage, 2307,
17809 /* 45273 */ GIR_EraseRootFromParent_Done,
17810 /* 45274 */ // Label 1167: @45274
17811 /* 45274 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(45301), // Rule ID 65 //
17812 /* 45279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17813 /* 45282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17814 /* 45286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17815 /* 45290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17816 /* 45294 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17817 /* 45294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
17818 /* 45299 */ GIR_RootConstrainSelectedInstOperands,
17819 /* 45300 */ // GIR_Coverage, 65,
17820 /* 45300 */ GIR_Done,
17821 /* 45301 */ // Label 1168: @45301
17822 /* 45301 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(45328), // Rule ID 1966 //
17823 /* 45306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17824 /* 45309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17825 /* 45313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17826 /* 45317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17827 /* 45321 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
17828 /* 45321 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
17829 /* 45326 */ GIR_RootConstrainSelectedInstOperands,
17830 /* 45327 */ // GIR_Coverage, 1966,
17831 /* 45327 */ GIR_Done,
17832 /* 45328 */ // Label 1169: @45328
17833 /* 45328 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(45355), // Rule ID 2308 //
17834 /* 45333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17835 /* 45336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17836 /* 45340 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17837 /* 45344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17838 /* 45348 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
17839 /* 45348 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
17840 /* 45353 */ GIR_RootConstrainSelectedInstOperands,
17841 /* 45354 */ // GIR_Coverage, 2308,
17842 /* 45354 */ GIR_Done,
17843 /* 45355 */ // Label 1170: @45355
17844 /* 45355 */ GIM_Reject,
17845 /* 45356 */ // Label 1164: @45356
17846 /* 45356 */ GIM_Reject,
17847 /* 45357 */ // Label 1158: @45357
17848 /* 45357 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(45497),
17849 /* 45362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17850 /* 45365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17851 /* 45368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17852 /* 45372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17853 /* 45376 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(45410), // Rule ID 238 //
17854 /* 45381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17855 /* 45384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17856 /* 45388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17857 /* 45392 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17858 /* 45396 */ // MIs[1] Operand 1
17859 /* 45396 */ // No operand predicates
17860 /* 45396 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17861 /* 45398 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17862 /* 45398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
17863 /* 45401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17864 /* 45403 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17865 /* 45405 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17866 /* 45408 */ GIR_RootConstrainSelectedInstOperands,
17867 /* 45409 */ // GIR_Coverage, 238,
17868 /* 45409 */ GIR_EraseRootFromParent_Done,
17869 /* 45410 */ // Label 1172: @45410
17870 /* 45410 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(45477), // Rule ID 1681 //
17871 /* 45415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17872 /* 45418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17873 /* 45422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17874 /* 45426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17875 /* 45430 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17876 /* 45435 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17877 /* 45437 */ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17878 /* 45437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17879 /* 45440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17880 /* 45444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17881 /* 45449 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17882 /* 45455 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17883 /* 45460 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17884 /* 45465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17885 /* 45468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17886 /* 45470 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17887 /* 45472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17888 /* 45475 */ GIR_RootConstrainSelectedInstOperands,
17889 /* 45476 */ // GIR_Coverage, 1681,
17890 /* 45476 */ GIR_EraseRootFromParent_Done,
17891 /* 45477 */ // Label 1173: @45477
17892 /* 45477 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(45496), // Rule ID 242 //
17893 /* 45482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17894 /* 45485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17895 /* 45489 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17896 /* 45489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17897 /* 45494 */ GIR_RootConstrainSelectedInstOperands,
17898 /* 45495 */ // GIR_Coverage, 242,
17899 /* 45495 */ GIR_Done,
17900 /* 45496 */ // Label 1174: @45496
17901 /* 45496 */ GIM_Reject,
17902 /* 45497 */ // Label 1171: @45497
17903 /* 45497 */ GIM_Reject,
17904 /* 45498 */ // Label 1159: @45498
17905 /* 45498 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(46149),
17906 /* 45503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17907 /* 45506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17908 /* 45509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17909 /* 45513 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(45819), // Rule ID 2655 //
17910 /* 45518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17911 /* 45521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17912 /* 45525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17913 /* 45529 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17914 /* 45533 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17915 /* 45537 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17916 /* 45541 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17917 /* 45545 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17918 /* 45548 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17919 /* 45552 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17920 /* 45556 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17921 /* 45560 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17922 /* 45564 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17923 /* 45568 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17924 /* 45572 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17925 /* 45576 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17926 /* 45580 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17927 /* 45584 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17928 /* 45588 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17929 /* 45592 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17930 /* 45596 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17931 /* 45600 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17932 /* 45604 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17933 /* 45608 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17934 /* 45612 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17935 /* 45616 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17936 /* 45620 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17937 /* 45624 */ // MIs[3] Operand 1
17938 /* 45624 */ // No operand predicates
17939 /* 45624 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17940 /* 45628 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17941 /* 45632 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17942 /* 45636 */ // MIs[4] Operand 1
17943 /* 45636 */ // No operand predicates
17944 /* 45636 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17945 /* 45640 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17946 /* 45644 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17947 /* 45648 */ // MIs[5] Operand 1
17948 /* 45648 */ // No operand predicates
17949 /* 45648 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17950 /* 45652 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17951 /* 45656 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17952 /* 45660 */ // MIs[6] Operand 1
17953 /* 45660 */ // No operand predicates
17954 /* 45660 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17955 /* 45664 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17956 /* 45668 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17957 /* 45672 */ // MIs[7] Operand 1
17958 /* 45672 */ // No operand predicates
17959 /* 45672 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17960 /* 45676 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17961 /* 45680 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17962 /* 45684 */ // MIs[8] Operand 1
17963 /* 45684 */ // No operand predicates
17964 /* 45684 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17965 /* 45688 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17966 /* 45692 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17967 /* 45696 */ // MIs[9] Operand 1
17968 /* 45696 */ // No operand predicates
17969 /* 45696 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17970 /* 45700 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17971 /* 45704 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17972 /* 45708 */ // MIs[10] Operand 1
17973 /* 45708 */ // No operand predicates
17974 /* 45708 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17975 /* 45712 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17976 /* 45716 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17977 /* 45720 */ // MIs[11] Operand 1
17978 /* 45720 */ // No operand predicates
17979 /* 45720 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17980 /* 45724 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17981 /* 45728 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17982 /* 45732 */ // MIs[12] Operand 1
17983 /* 45732 */ // No operand predicates
17984 /* 45732 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17985 /* 45736 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17986 /* 45740 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17987 /* 45744 */ // MIs[13] Operand 1
17988 /* 45744 */ // No operand predicates
17989 /* 45744 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17990 /* 45748 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17991 /* 45752 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17992 /* 45756 */ // MIs[14] Operand 1
17993 /* 45756 */ // No operand predicates
17994 /* 45756 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17995 /* 45760 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17996 /* 45764 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17997 /* 45768 */ // MIs[15] Operand 1
17998 /* 45768 */ // No operand predicates
17999 /* 45768 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
18000 /* 45772 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18001 /* 45776 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18002 /* 45780 */ // MIs[16] Operand 1
18003 /* 45780 */ // No operand predicates
18004 /* 45780 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
18005 /* 45784 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18006 /* 45788 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18007 /* 45792 */ // MIs[17] Operand 1
18008 /* 45792 */ // No operand predicates
18009 /* 45792 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
18010 /* 45796 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18011 /* 45800 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18012 /* 45804 */ // MIs[18] Operand 1
18013 /* 45804 */ // No operand predicates
18014 /* 45804 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
18015 /* 45806 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
18016 /* 45806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18017 /* 45809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18018 /* 45811 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18019 /* 45813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
18020 /* 45817 */ GIR_RootConstrainSelectedInstOperands,
18021 /* 45818 */ // GIR_Coverage, 2655,
18022 /* 45818 */ GIR_EraseRootFromParent_Done,
18023 /* 45819 */ // Label 1176: @45819
18024 /* 45819 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(46125), // Rule ID 2212 //
18025 /* 45824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18026 /* 45827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18027 /* 45831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18028 /* 45835 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
18029 /* 45839 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
18030 /* 45843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18031 /* 45847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18032 /* 45851 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
18033 /* 45854 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18034 /* 45858 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18035 /* 45862 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18036 /* 45866 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18037 /* 45870 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18038 /* 45874 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18039 /* 45878 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18040 /* 45882 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18041 /* 45886 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
18042 /* 45890 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
18043 /* 45894 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
18044 /* 45898 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
18045 /* 45902 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
18046 /* 45906 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
18047 /* 45910 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
18048 /* 45914 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
18049 /* 45918 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18050 /* 45922 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18051 /* 45926 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18052 /* 45930 */ // MIs[3] Operand 1
18053 /* 45930 */ // No operand predicates
18054 /* 45930 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18055 /* 45934 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18056 /* 45938 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18057 /* 45942 */ // MIs[4] Operand 1
18058 /* 45942 */ // No operand predicates
18059 /* 45942 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18060 /* 45946 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18061 /* 45950 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18062 /* 45954 */ // MIs[5] Operand 1
18063 /* 45954 */ // No operand predicates
18064 /* 45954 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18065 /* 45958 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18066 /* 45962 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18067 /* 45966 */ // MIs[6] Operand 1
18068 /* 45966 */ // No operand predicates
18069 /* 45966 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18070 /* 45970 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18071 /* 45974 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18072 /* 45978 */ // MIs[7] Operand 1
18073 /* 45978 */ // No operand predicates
18074 /* 45978 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18075 /* 45982 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18076 /* 45986 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18077 /* 45990 */ // MIs[8] Operand 1
18078 /* 45990 */ // No operand predicates
18079 /* 45990 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18080 /* 45994 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18081 /* 45998 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18082 /* 46002 */ // MIs[9] Operand 1
18083 /* 46002 */ // No operand predicates
18084 /* 46002 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18085 /* 46006 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18086 /* 46010 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18087 /* 46014 */ // MIs[10] Operand 1
18088 /* 46014 */ // No operand predicates
18089 /* 46014 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
18090 /* 46018 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18091 /* 46022 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18092 /* 46026 */ // MIs[11] Operand 1
18093 /* 46026 */ // No operand predicates
18094 /* 46026 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
18095 /* 46030 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18096 /* 46034 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18097 /* 46038 */ // MIs[12] Operand 1
18098 /* 46038 */ // No operand predicates
18099 /* 46038 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
18100 /* 46042 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18101 /* 46046 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18102 /* 46050 */ // MIs[13] Operand 1
18103 /* 46050 */ // No operand predicates
18104 /* 46050 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
18105 /* 46054 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18106 /* 46058 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18107 /* 46062 */ // MIs[14] Operand 1
18108 /* 46062 */ // No operand predicates
18109 /* 46062 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
18110 /* 46066 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18111 /* 46070 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18112 /* 46074 */ // MIs[15] Operand 1
18113 /* 46074 */ // No operand predicates
18114 /* 46074 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
18115 /* 46078 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18116 /* 46082 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18117 /* 46086 */ // MIs[16] Operand 1
18118 /* 46086 */ // No operand predicates
18119 /* 46086 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
18120 /* 46090 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18121 /* 46094 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18122 /* 46098 */ // MIs[17] Operand 1
18123 /* 46098 */ // No operand predicates
18124 /* 46098 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
18125 /* 46102 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18126 /* 46106 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18127 /* 46110 */ // MIs[18] Operand 1
18128 /* 46110 */ // No operand predicates
18129 /* 46110 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
18130 /* 46112 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
18131 /* 46112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18132 /* 46115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18133 /* 46117 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18134 /* 46119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18135 /* 46123 */ GIR_RootConstrainSelectedInstOperands,
18136 /* 46124 */ // GIR_Coverage, 2212,
18137 /* 46124 */ GIR_EraseRootFromParent_Done,
18138 /* 46125 */ // Label 1177: @46125
18139 /* 46125 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(46148), // Rule ID 997 //
18140 /* 46130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18141 /* 46133 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
18142 /* 46137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
18143 /* 46141 */ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
18144 /* 46141 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18145 /* 46146 */ GIR_RootConstrainSelectedInstOperands,
18146 /* 46147 */ // GIR_Coverage, 997,
18147 /* 46147 */ GIR_Done,
18148 /* 46148 */ // Label 1178: @46148
18149 /* 46148 */ GIM_Reject,
18150 /* 46149 */ // Label 1175: @46149
18151 /* 46149 */ GIM_Reject,
18152 /* 46150 */ // Label 1160: @46150
18153 /* 46150 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(46545),
18154 /* 46155 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18155 /* 46158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18156 /* 46161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18157 /* 46165 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(46343), // Rule ID 2656 //
18158 /* 46170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18159 /* 46173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18160 /* 46177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18161 /* 46181 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
18162 /* 46185 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
18163 /* 46189 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18164 /* 46193 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18165 /* 46197 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
18166 /* 46200 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18167 /* 46204 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18168 /* 46208 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18169 /* 46212 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18170 /* 46216 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18171 /* 46220 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18172 /* 46224 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18173 /* 46228 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18174 /* 46232 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18175 /* 46236 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18176 /* 46240 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18177 /* 46244 */ // MIs[3] Operand 1
18178 /* 46244 */ // No operand predicates
18179 /* 46244 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18180 /* 46248 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18181 /* 46252 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18182 /* 46256 */ // MIs[4] Operand 1
18183 /* 46256 */ // No operand predicates
18184 /* 46256 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18185 /* 46260 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18186 /* 46264 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18187 /* 46268 */ // MIs[5] Operand 1
18188 /* 46268 */ // No operand predicates
18189 /* 46268 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18190 /* 46272 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18191 /* 46276 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18192 /* 46280 */ // MIs[6] Operand 1
18193 /* 46280 */ // No operand predicates
18194 /* 46280 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18195 /* 46284 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18196 /* 46288 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18197 /* 46292 */ // MIs[7] Operand 1
18198 /* 46292 */ // No operand predicates
18199 /* 46292 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18200 /* 46296 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18201 /* 46300 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18202 /* 46304 */ // MIs[8] Operand 1
18203 /* 46304 */ // No operand predicates
18204 /* 46304 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18205 /* 46308 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18206 /* 46312 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18207 /* 46316 */ // MIs[9] Operand 1
18208 /* 46316 */ // No operand predicates
18209 /* 46316 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18210 /* 46320 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18211 /* 46324 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18212 /* 46328 */ // MIs[10] Operand 1
18213 /* 46328 */ // No operand predicates
18214 /* 46328 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
18215 /* 46330 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
18216 /* 46330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18217 /* 46333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18218 /* 46335 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18219 /* 46337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
18220 /* 46341 */ GIR_RootConstrainSelectedInstOperands,
18221 /* 46342 */ // GIR_Coverage, 2656,
18222 /* 46342 */ GIR_EraseRootFromParent_Done,
18223 /* 46343 */ // Label 1180: @46343
18224 /* 46343 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(46521), // Rule ID 2213 //
18225 /* 46348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18226 /* 46351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18227 /* 46355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18228 /* 46359 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
18229 /* 46363 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
18230 /* 46367 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18231 /* 46371 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18232 /* 46375 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
18233 /* 46378 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18234 /* 46382 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18235 /* 46386 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18236 /* 46390 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18237 /* 46394 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18238 /* 46398 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18239 /* 46402 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18240 /* 46406 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18241 /* 46410 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18242 /* 46414 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18243 /* 46418 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18244 /* 46422 */ // MIs[3] Operand 1
18245 /* 46422 */ // No operand predicates
18246 /* 46422 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18247 /* 46426 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18248 /* 46430 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18249 /* 46434 */ // MIs[4] Operand 1
18250 /* 46434 */ // No operand predicates
18251 /* 46434 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18252 /* 46438 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18253 /* 46442 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18254 /* 46446 */ // MIs[5] Operand 1
18255 /* 46446 */ // No operand predicates
18256 /* 46446 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18257 /* 46450 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18258 /* 46454 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18259 /* 46458 */ // MIs[6] Operand 1
18260 /* 46458 */ // No operand predicates
18261 /* 46458 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18262 /* 46462 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18263 /* 46466 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18264 /* 46470 */ // MIs[7] Operand 1
18265 /* 46470 */ // No operand predicates
18266 /* 46470 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18267 /* 46474 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18268 /* 46478 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18269 /* 46482 */ // MIs[8] Operand 1
18270 /* 46482 */ // No operand predicates
18271 /* 46482 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18272 /* 46486 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18273 /* 46490 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18274 /* 46494 */ // MIs[9] Operand 1
18275 /* 46494 */ // No operand predicates
18276 /* 46494 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18277 /* 46498 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18278 /* 46502 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18279 /* 46506 */ // MIs[10] Operand 1
18280 /* 46506 */ // No operand predicates
18281 /* 46506 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
18282 /* 46508 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
18283 /* 46508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18284 /* 46511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18285 /* 46513 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18286 /* 46515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18287 /* 46519 */ GIR_RootConstrainSelectedInstOperands,
18288 /* 46520 */ // GIR_Coverage, 2213,
18289 /* 46520 */ GIR_EraseRootFromParent_Done,
18290 /* 46521 */ // Label 1181: @46521
18291 /* 46521 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(46544), // Rule ID 998 //
18292 /* 46526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18293 /* 46529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18294 /* 46533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18295 /* 46537 */ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
18296 /* 46537 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18297 /* 46542 */ GIR_RootConstrainSelectedInstOperands,
18298 /* 46543 */ // GIR_Coverage, 998,
18299 /* 46543 */ GIR_Done,
18300 /* 46544 */ // Label 1182: @46544
18301 /* 46544 */ GIM_Reject,
18302 /* 46545 */ // Label 1179: @46545
18303 /* 46545 */ GIM_Reject,
18304 /* 46546 */ // Label 1161: @46546
18305 /* 46546 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(46813),
18306 /* 46551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
18307 /* 46554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18308 /* 46557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
18309 /* 46561 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(46675), // Rule ID 2657 //
18310 /* 46566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18311 /* 46569 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18312 /* 46573 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18313 /* 46577 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18314 /* 46581 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18315 /* 46585 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18316 /* 46589 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18317 /* 46593 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
18318 /* 46596 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18319 /* 46600 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18320 /* 46604 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18321 /* 46608 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18322 /* 46612 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18323 /* 46616 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18324 /* 46620 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18325 /* 46624 */ // MIs[3] Operand 1
18326 /* 46624 */ // No operand predicates
18327 /* 46624 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18328 /* 46628 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18329 /* 46632 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18330 /* 46636 */ // MIs[4] Operand 1
18331 /* 46636 */ // No operand predicates
18332 /* 46636 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18333 /* 46640 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18334 /* 46644 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18335 /* 46648 */ // MIs[5] Operand 1
18336 /* 46648 */ // No operand predicates
18337 /* 46648 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18338 /* 46652 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18339 /* 46656 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18340 /* 46660 */ // MIs[6] Operand 1
18341 /* 46660 */ // No operand predicates
18342 /* 46660 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
18343 /* 46662 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
18344 /* 46662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
18345 /* 46665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18346 /* 46667 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18347 /* 46669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
18348 /* 46673 */ GIR_RootConstrainSelectedInstOperands,
18349 /* 46674 */ // GIR_Coverage, 2657,
18350 /* 46674 */ GIR_EraseRootFromParent_Done,
18351 /* 46675 */ // Label 1184: @46675
18352 /* 46675 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(46789), // Rule ID 2214 //
18353 /* 46680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18354 /* 46683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18355 /* 46687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18356 /* 46691 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
18357 /* 46695 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
18358 /* 46699 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18359 /* 46703 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18360 /* 46707 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
18361 /* 46710 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18362 /* 46714 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18363 /* 46718 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18364 /* 46722 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18365 /* 46726 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18366 /* 46730 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18367 /* 46734 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18368 /* 46738 */ // MIs[3] Operand 1
18369 /* 46738 */ // No operand predicates
18370 /* 46738 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18371 /* 46742 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18372 /* 46746 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18373 /* 46750 */ // MIs[4] Operand 1
18374 /* 46750 */ // No operand predicates
18375 /* 46750 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18376 /* 46754 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18377 /* 46758 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18378 /* 46762 */ // MIs[5] Operand 1
18379 /* 46762 */ // No operand predicates
18380 /* 46762 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18381 /* 46766 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18382 /* 46770 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
18383 /* 46774 */ // MIs[6] Operand 1
18384 /* 46774 */ // No operand predicates
18385 /* 46774 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
18386 /* 46776 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
18387 /* 46776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
18388 /* 46779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18389 /* 46781 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18390 /* 46783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18391 /* 46787 */ GIR_RootConstrainSelectedInstOperands,
18392 /* 46788 */ // GIR_Coverage, 2214,
18393 /* 46788 */ GIR_EraseRootFromParent_Done,
18394 /* 46789 */ // Label 1185: @46789
18395 /* 46789 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(46812), // Rule ID 999 //
18396 /* 46794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18397 /* 46797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
18398 /* 46801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
18399 /* 46805 */ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
18400 /* 46805 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
18401 /* 46810 */ GIR_RootConstrainSelectedInstOperands,
18402 /* 46811 */ // GIR_Coverage, 999,
18403 /* 46811 */ GIR_Done,
18404 /* 46812 */ // Label 1186: @46812
18405 /* 46812 */ GIM_Reject,
18406 /* 46813 */ // Label 1183: @46813
18407 /* 46813 */ GIM_Reject,
18408 /* 46814 */ // Label 1162: @46814
18409 /* 46814 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(46847), // Rule ID 1000 //
18410 /* 46819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18411 /* 46822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
18412 /* 46825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
18413 /* 46828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
18414 /* 46832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
18415 /* 46836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
18416 /* 46840 */ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
18417 /* 46840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
18418 /* 46845 */ GIR_RootConstrainSelectedInstOperands,
18419 /* 46846 */ // GIR_Coverage, 1000,
18420 /* 46846 */ GIR_Done,
18421 /* 46847 */ // Label 1187: @46847
18422 /* 46847 */ GIM_Reject,
18423 /* 46848 */ // Label 1163: @46848
18424 /* 46848 */ GIM_Reject,
18425 /* 46849 */ // Label 40: @46849
18426 /* 46849 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(47136),
18427 /* 46860 */ /*GILLT_s32*//*Label 1188*/ GIMT_Encode4(46868),
18428 /* 46864 */ /*GILLT_s64*//*Label 1189*/ GIMT_Encode4(46995),
18429 /* 46868 */ // Label 1188: @46868
18430 /* 46868 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(46994),
18431 /* 46873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18432 /* 46876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18433 /* 46879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18434 /* 46883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18435 /* 46887 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(46921), // Rule ID 67 //
18436 /* 46892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
18437 /* 46895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18438 /* 46899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18439 /* 46903 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
18440 /* 46907 */ // MIs[1] Operand 1
18441 /* 46907 */ // No operand predicates
18442 /* 46907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18443 /* 46909 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
18444 /* 46909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
18445 /* 46912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18446 /* 46914 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18447 /* 46916 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18448 /* 46919 */ GIR_RootConstrainSelectedInstOperands,
18449 /* 46920 */ // GIR_Coverage, 67,
18450 /* 46920 */ GIR_EraseRootFromParent_Done,
18451 /* 46921 */ // Label 1192: @46921
18452 /* 46921 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(46955), // Rule ID 1105 //
18453 /* 46926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18454 /* 46929 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18455 /* 46933 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18456 /* 46937 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
18457 /* 46941 */ // MIs[1] Operand 1
18458 /* 46941 */ // No operand predicates
18459 /* 46941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18460 /* 46943 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
18461 /* 46943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
18462 /* 46946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18463 /* 46948 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18464 /* 46950 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18465 /* 46953 */ GIR_RootConstrainSelectedInstOperands,
18466 /* 46954 */ // GIR_Coverage, 1105,
18467 /* 46954 */ GIR_EraseRootFromParent_Done,
18468 /* 46955 */ // Label 1193: @46955
18469 /* 46955 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(46974), // Rule ID 68 //
18470 /* 46960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
18471 /* 46963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18472 /* 46967 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18473 /* 46967 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
18474 /* 46972 */ GIR_RootConstrainSelectedInstOperands,
18475 /* 46973 */ // GIR_Coverage, 68,
18476 /* 46973 */ GIR_Done,
18477 /* 46974 */ // Label 1194: @46974
18478 /* 46974 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(46993), // Rule ID 1106 //
18479 /* 46979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18480 /* 46982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18481 /* 46986 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18482 /* 46986 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
18483 /* 46991 */ GIR_RootConstrainSelectedInstOperands,
18484 /* 46992 */ // GIR_Coverage, 1106,
18485 /* 46992 */ GIR_Done,
18486 /* 46993 */ // Label 1195: @46993
18487 /* 46993 */ GIM_Reject,
18488 /* 46994 */ // Label 1191: @46994
18489 /* 46994 */ GIM_Reject,
18490 /* 46995 */ // Label 1189: @46995
18491 /* 46995 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(47135),
18492 /* 47000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
18493 /* 47003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18494 /* 47006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18495 /* 47010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18496 /* 47014 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(47048), // Rule ID 246 //
18497 /* 47019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
18498 /* 47022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18499 /* 47026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18500 /* 47030 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
18501 /* 47034 */ // MIs[1] Operand 1
18502 /* 47034 */ // No operand predicates
18503 /* 47034 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18504 /* 47036 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
18505 /* 47036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
18506 /* 47039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18507 /* 47041 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18508 /* 47043 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18509 /* 47046 */ GIR_RootConstrainSelectedInstOperands,
18510 /* 47047 */ // GIR_Coverage, 246,
18511 /* 47047 */ GIR_EraseRootFromParent_Done,
18512 /* 47048 */ // Label 1197: @47048
18513 /* 47048 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(47115), // Rule ID 1682 //
18514 /* 47053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
18515 /* 47056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18516 /* 47060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18517 /* 47064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
18518 /* 47068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18519 /* 47073 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18520 /* 47075 */ // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
18521 /* 47075 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18522 /* 47078 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18523 /* 47082 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18524 /* 47087 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
18525 /* 47093 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
18526 /* 47098 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
18527 /* 47103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
18528 /* 47106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18529 /* 47108 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18530 /* 47110 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18531 /* 47113 */ GIR_RootConstrainSelectedInstOperands,
18532 /* 47114 */ // GIR_Coverage, 1682,
18533 /* 47114 */ GIR_EraseRootFromParent_Done,
18534 /* 47115 */ // Label 1198: @47115
18535 /* 47115 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(47134), // Rule ID 247 //
18536 /* 47120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
18537 /* 47123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18538 /* 47127 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18539 /* 47127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
18540 /* 47132 */ GIR_RootConstrainSelectedInstOperands,
18541 /* 47133 */ // GIR_Coverage, 247,
18542 /* 47133 */ GIR_Done,
18543 /* 47134 */ // Label 1199: @47134
18544 /* 47134 */ GIM_Reject,
18545 /* 47135 */ // Label 1196: @47135
18546 /* 47135 */ GIM_Reject,
18547 /* 47136 */ // Label 1190: @47136
18548 /* 47136 */ GIM_Reject,
18549 /* 47137 */ // Label 41: @47137
18550 /* 47137 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(49667),
18551 /* 47142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18552 /* 47145 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1203*/ GIMT_Encode4(47330),
18553 /* 47156 */ /*GILLT_s32*//*Label 1201*/ GIMT_Encode4(47164),
18554 /* 47160 */ /*GILLT_s64*//*Label 1202*/ GIMT_Encode4(47247),
18555 /* 47164 */ // Label 1201: @47164
18556 /* 47164 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(47246),
18557 /* 47169 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18558 /* 47172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18559 /* 47176 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(47209), // Rule ID 1438 //
18560 /* 47181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18561 /* 47184 */ // MIs[0] Operand 1
18562 /* 47184 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18563 /* 47189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18564 /* 47193 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18565 /* 47197 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18566 /* 47197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
18567 /* 47200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18568 /* 47202 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18569 /* 47204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18570 /* 47207 */ GIR_RootConstrainSelectedInstOperands,
18571 /* 47208 */ // GIR_Coverage, 1438,
18572 /* 47208 */ GIR_EraseRootFromParent_Done,
18573 /* 47209 */ // Label 1205: @47209
18574 /* 47209 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(47245), // Rule ID 1439 //
18575 /* 47214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18576 /* 47217 */ // MIs[0] Operand 1
18577 /* 47217 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18578 /* 47222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18579 /* 47226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18580 /* 47230 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
18581 /* 47230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18582 /* 47233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18583 /* 47235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18584 /* 47241 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18585 /* 47243 */ GIR_RootConstrainSelectedInstOperands,
18586 /* 47244 */ // GIR_Coverage, 1439,
18587 /* 47244 */ GIR_EraseRootFromParent_Done,
18588 /* 47245 */ // Label 1206: @47245
18589 /* 47245 */ GIM_Reject,
18590 /* 47246 */ // Label 1204: @47246
18591 /* 47246 */ GIM_Reject,
18592 /* 47247 */ // Label 1202: @47247
18593 /* 47247 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(47329),
18594 /* 47252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18595 /* 47255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18596 /* 47259 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(47292), // Rule ID 1664 //
18597 /* 47264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18598 /* 47267 */ // MIs[0] Operand 1
18599 /* 47267 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18600 /* 47272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18601 /* 47276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18602 /* 47280 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
18603 /* 47280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18604 /* 47283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18605 /* 47285 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18606 /* 47287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18607 /* 47290 */ GIR_RootConstrainSelectedInstOperands,
18608 /* 47291 */ // GIR_Coverage, 1664,
18609 /* 47291 */ GIR_EraseRootFromParent_Done,
18610 /* 47292 */ // Label 1208: @47292
18611 /* 47292 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(47328), // Rule ID 1665 //
18612 /* 47297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18613 /* 47300 */ // MIs[0] Operand 1
18614 /* 47300 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18615 /* 47305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18616 /* 47309 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18617 /* 47313 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
18618 /* 47313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18619 /* 47316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18620 /* 47318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18621 /* 47324 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18622 /* 47326 */ GIR_RootConstrainSelectedInstOperands,
18623 /* 47327 */ // GIR_Coverage, 1665,
18624 /* 47327 */ GIR_EraseRootFromParent_Done,
18625 /* 47328 */ // Label 1209: @47328
18626 /* 47328 */ GIM_Reject,
18627 /* 47329 */ // Label 1207: @47329
18628 /* 47329 */ GIM_Reject,
18629 /* 47330 */ // Label 1203: @47330
18630 /* 47330 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1212*/ GIMT_Encode4(47713),
18631 /* 47341 */ /*GILLT_s32*//*Label 1210*/ GIMT_Encode4(47349),
18632 /* 47345 */ /*GILLT_s64*//*Label 1211*/ GIMT_Encode4(47635),
18633 /* 47349 */ // Label 1210: @47349
18634 /* 47349 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(47634),
18635 /* 47354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18636 /* 47357 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(47394), // Rule ID 2014 //
18637 /* 47362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18638 /* 47365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18639 /* 47369 */ // MIs[0] Operand 1
18640 /* 47369 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18641 /* 47374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18642 /* 47378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18643 /* 47382 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18644 /* 47382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
18645 /* 47385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18646 /* 47387 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18647 /* 47389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18648 /* 47392 */ GIR_RootConstrainSelectedInstOperands,
18649 /* 47393 */ // GIR_Coverage, 2014,
18650 /* 47393 */ GIR_EraseRootFromParent_Done,
18651 /* 47394 */ // Label 1214: @47394
18652 /* 47394 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(47484), // Rule ID 2016 //
18653 /* 47399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18654 /* 47402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18655 /* 47406 */ // MIs[0] Operand 1
18656 /* 47406 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18657 /* 47411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18658 /* 47415 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709518847u),
18659 /* 47426 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18660 /* 47426 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18661 /* 47429 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18662 /* 47433 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18663 /* 47438 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18664 /* 47441 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18665 /* 47443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18666 /* 47446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
18667 /* 47450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18668 /* 47455 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18669 /* 47459 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
18670 /* 47469 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18671 /* 47471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18672 /* 47474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18673 /* 47476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18674 /* 47479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18675 /* 47482 */ GIR_RootConstrainSelectedInstOperands,
18676 /* 47483 */ // GIR_Coverage, 2016,
18677 /* 47483 */ GIR_EraseRootFromParent_Done,
18678 /* 47484 */ // Label 1215: @47484
18679 /* 47484 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(47521), // Rule ID 2335 //
18680 /* 47489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18681 /* 47492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18682 /* 47496 */ // MIs[0] Operand 1
18683 /* 47496 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18684 /* 47501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18685 /* 47505 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18686 /* 47509 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18687 /* 47509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
18688 /* 47512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18689 /* 47514 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18690 /* 47516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18691 /* 47519 */ GIR_RootConstrainSelectedInstOperands,
18692 /* 47520 */ // GIR_Coverage, 2335,
18693 /* 47520 */ GIR_EraseRootFromParent_Done,
18694 /* 47521 */ // Label 1216: @47521
18695 /* 47521 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(47561), // Rule ID 2336 //
18696 /* 47526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18697 /* 47529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18698 /* 47533 */ // MIs[0] Operand 1
18699 /* 47533 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18700 /* 47538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18701 /* 47542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18702 /* 47546 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
18703 /* 47546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18704 /* 47549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18705 /* 47551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18706 /* 47557 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18707 /* 47559 */ GIR_RootConstrainSelectedInstOperands,
18708 /* 47560 */ // GIR_Coverage, 2336,
18709 /* 47560 */ GIR_EraseRootFromParent_Done,
18710 /* 47561 */ // Label 1217: @47561
18711 /* 47561 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(47597), // Rule ID 49 //
18712 /* 47566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18713 /* 47569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18714 /* 47573 */ // MIs[0] Operand 1
18715 /* 47573 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18716 /* 47578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18717 /* 47582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18718 /* 47586 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18719 /* 47586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
18720 /* 47589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18721 /* 47591 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18722 /* 47593 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18723 /* 47595 */ GIR_RootConstrainSelectedInstOperands,
18724 /* 47596 */ // GIR_Coverage, 49,
18725 /* 47596 */ GIR_EraseRootFromParent_Done,
18726 /* 47597 */ // Label 1218: @47597
18727 /* 47597 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(47633), // Rule ID 50 //
18728 /* 47602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18729 /* 47605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18730 /* 47609 */ // MIs[0] Operand 1
18731 /* 47609 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18732 /* 47614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18733 /* 47618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18734 /* 47622 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18735 /* 47622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18736 /* 47625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18737 /* 47627 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18738 /* 47629 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18739 /* 47631 */ GIR_RootConstrainSelectedInstOperands,
18740 /* 47632 */ // GIR_Coverage, 50,
18741 /* 47632 */ GIR_EraseRootFromParent_Done,
18742 /* 47633 */ // Label 1219: @47633
18743 /* 47633 */ GIM_Reject,
18744 /* 47634 */ // Label 1213: @47634
18745 /* 47634 */ GIM_Reject,
18746 /* 47635 */ // Label 1211: @47635
18747 /* 47635 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(47712),
18748 /* 47640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18749 /* 47643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18750 /* 47647 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(47679), // Rule ID 228 //
18751 /* 47652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18752 /* 47655 */ // MIs[0] Operand 1
18753 /* 47655 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18754 /* 47660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18755 /* 47664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18756 /* 47668 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18757 /* 47668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18758 /* 47671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18759 /* 47673 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18760 /* 47675 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18761 /* 47677 */ GIR_RootConstrainSelectedInstOperands,
18762 /* 47678 */ // GIR_Coverage, 228,
18763 /* 47678 */ GIR_EraseRootFromParent_Done,
18764 /* 47679 */ // Label 1221: @47679
18765 /* 47679 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(47711), // Rule ID 229 //
18766 /* 47684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18767 /* 47687 */ // MIs[0] Operand 1
18768 /* 47687 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18769 /* 47692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18770 /* 47696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18771 /* 47700 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18772 /* 47700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18773 /* 47703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18774 /* 47705 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18775 /* 47707 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18776 /* 47709 */ GIR_RootConstrainSelectedInstOperands,
18777 /* 47710 */ // GIR_Coverage, 229,
18778 /* 47710 */ GIR_EraseRootFromParent_Done,
18779 /* 47711 */ // Label 1222: @47711
18780 /* 47711 */ GIM_Reject,
18781 /* 47712 */ // Label 1220: @47712
18782 /* 47712 */ GIM_Reject,
18783 /* 47713 */ // Label 1212: @47713
18784 /* 47713 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1225*/ GIMT_Encode4(48630),
18785 /* 47724 */ /*GILLT_s32*//*Label 1223*/ GIMT_Encode4(47732),
18786 /* 47728 */ /*GILLT_s64*//*Label 1224*/ GIMT_Encode4(48213),
18787 /* 47732 */ // Label 1223: @47732
18788 /* 47732 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(48212),
18789 /* 47737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18790 /* 47740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18791 /* 47744 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(47776), // Rule ID 1099 //
18792 /* 47749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18793 /* 47752 */ // MIs[0] Operand 1
18794 /* 47752 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18795 /* 47757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18796 /* 47761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18797 /* 47765 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18798 /* 47765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18799 /* 47768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18800 /* 47770 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18801 /* 47772 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18802 /* 47774 */ GIR_RootConstrainSelectedInstOperands,
18803 /* 47775 */ // GIR_Coverage, 1099,
18804 /* 47775 */ GIR_EraseRootFromParent_Done,
18805 /* 47776 */ // Label 1227: @47776
18806 /* 47776 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(47808), // Rule ID 1100 //
18807 /* 47781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18808 /* 47784 */ // MIs[0] Operand 1
18809 /* 47784 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18810 /* 47789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18811 /* 47793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18812 /* 47797 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18813 /* 47797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18814 /* 47800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18815 /* 47802 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18816 /* 47804 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18817 /* 47806 */ GIR_RootConstrainSelectedInstOperands,
18818 /* 47807 */ // GIR_Coverage, 1100,
18819 /* 47807 */ GIR_EraseRootFromParent_Done,
18820 /* 47808 */ // Label 1228: @47808
18821 /* 47808 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(47864), // Rule ID 1440 //
18822 /* 47813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18823 /* 47816 */ // MIs[0] Operand 1
18824 /* 47816 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18825 /* 47821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18826 /* 47825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18827 /* 47829 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18828 /* 47829 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18829 /* 47832 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18830 /* 47836 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18831 /* 47841 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18832 /* 47845 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18833 /* 47849 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18834 /* 47851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
18835 /* 47854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18836 /* 47856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18837 /* 47859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18838 /* 47862 */ GIR_RootConstrainSelectedInstOperands,
18839 /* 47863 */ // GIR_Coverage, 1440,
18840 /* 47863 */ GIR_EraseRootFromParent_Done,
18841 /* 47864 */ // Label 1229: @47864
18842 /* 47864 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(47923), // Rule ID 1441 //
18843 /* 47869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18844 /* 47872 */ // MIs[0] Operand 1
18845 /* 47872 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18846 /* 47877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18847 /* 47881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18848 /* 47885 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18849 /* 47885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18850 /* 47888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18851 /* 47892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18852 /* 47897 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18853 /* 47901 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18854 /* 47905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18855 /* 47907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18856 /* 47910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18857 /* 47912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18858 /* 47918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18859 /* 47921 */ GIR_RootConstrainSelectedInstOperands,
18860 /* 47922 */ // GIR_Coverage, 1441,
18861 /* 47922 */ GIR_EraseRootFromParent_Done,
18862 /* 47923 */ // Label 1230: @47923
18863 /* 47923 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(47979), // Rule ID 1442 //
18864 /* 47928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18865 /* 47931 */ // MIs[0] Operand 1
18866 /* 47931 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18867 /* 47936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18868 /* 47940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18869 /* 47944 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18870 /* 47944 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18871 /* 47947 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18872 /* 47951 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18873 /* 47956 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18874 /* 47960 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18875 /* 47964 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18876 /* 47966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18877 /* 47969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18878 /* 47971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18879 /* 47974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18880 /* 47977 */ GIR_RootConstrainSelectedInstOperands,
18881 /* 47978 */ // GIR_Coverage, 1442,
18882 /* 47978 */ GIR_EraseRootFromParent_Done,
18883 /* 47979 */ // Label 1231: @47979
18884 /* 47979 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(48035), // Rule ID 1443 //
18885 /* 47984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18886 /* 47987 */ // MIs[0] Operand 1
18887 /* 47987 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18888 /* 47992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18889 /* 47996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18890 /* 48000 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18891 /* 48000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18892 /* 48003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18893 /* 48007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18894 /* 48012 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18895 /* 48016 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18896 /* 48020 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18897 /* 48022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18898 /* 48025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18899 /* 48027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18900 /* 48030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18901 /* 48033 */ GIR_RootConstrainSelectedInstOperands,
18902 /* 48034 */ // GIR_Coverage, 1443,
18903 /* 48034 */ GIR_EraseRootFromParent_Done,
18904 /* 48035 */ // Label 1232: @48035
18905 /* 48035 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(48067), // Rule ID 1444 //
18906 /* 48040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18907 /* 48043 */ // MIs[0] Operand 1
18908 /* 48043 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18909 /* 48048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18910 /* 48052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18911 /* 48056 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18912 /* 48056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
18913 /* 48059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18914 /* 48061 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18915 /* 48063 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18916 /* 48065 */ GIR_RootConstrainSelectedInstOperands,
18917 /* 48066 */ // GIR_Coverage, 1444,
18918 /* 48066 */ GIR_EraseRootFromParent_Done,
18919 /* 48067 */ // Label 1233: @48067
18920 /* 48067 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(48099), // Rule ID 1445 //
18921 /* 48072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18922 /* 48075 */ // MIs[0] Operand 1
18923 /* 48075 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18924 /* 48080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18925 /* 48084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18926 /* 48088 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18927 /* 48088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18928 /* 48091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18929 /* 48093 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18930 /* 48095 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18931 /* 48097 */ GIR_RootConstrainSelectedInstOperands,
18932 /* 48098 */ // GIR_Coverage, 1445,
18933 /* 48098 */ GIR_EraseRootFromParent_Done,
18934 /* 48099 */ // Label 1234: @48099
18935 /* 48099 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(48155), // Rule ID 1446 //
18936 /* 48104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18937 /* 48107 */ // MIs[0] Operand 1
18938 /* 48107 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18939 /* 48112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18940 /* 48116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18941 /* 48120 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18942 /* 48120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18943 /* 48123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18944 /* 48127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18945 /* 48132 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18946 /* 48136 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18947 /* 48140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18948 /* 48142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18949 /* 48145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18950 /* 48147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18951 /* 48150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18952 /* 48153 */ GIR_RootConstrainSelectedInstOperands,
18953 /* 48154 */ // GIR_Coverage, 1446,
18954 /* 48154 */ GIR_EraseRootFromParent_Done,
18955 /* 48155 */ // Label 1235: @48155
18956 /* 48155 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(48211), // Rule ID 1447 //
18957 /* 48160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18958 /* 48163 */ // MIs[0] Operand 1
18959 /* 48163 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18960 /* 48168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18961 /* 48172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18962 /* 48176 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18963 /* 48176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18964 /* 48179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18965 /* 48183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18966 /* 48188 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18967 /* 48192 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18968 /* 48196 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18969 /* 48198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18970 /* 48201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18971 /* 48203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18972 /* 48206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18973 /* 48209 */ GIR_RootConstrainSelectedInstOperands,
18974 /* 48210 */ // GIR_Coverage, 1447,
18975 /* 48210 */ GIR_EraseRootFromParent_Done,
18976 /* 48211 */ // Label 1236: @48211
18977 /* 48211 */ GIM_Reject,
18978 /* 48212 */ // Label 1226: @48212
18979 /* 48212 */ GIM_Reject,
18980 /* 48213 */ // Label 1224: @48213
18981 /* 48213 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(48629),
18982 /* 48218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18983 /* 48221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18984 /* 48225 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(48281), // Rule ID 1666 //
18985 /* 48230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18986 /* 48233 */ // MIs[0] Operand 1
18987 /* 48233 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18988 /* 48238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18989 /* 48242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18990 /* 48246 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
18991 /* 48246 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18992 /* 48249 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18993 /* 48253 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18994 /* 48258 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18995 /* 48262 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18996 /* 48266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18997 /* 48268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18998 /* 48271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18999 /* 48273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19000 /* 48276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19001 /* 48279 */ GIR_RootConstrainSelectedInstOperands,
19002 /* 48280 */ // GIR_Coverage, 1666,
19003 /* 48280 */ GIR_EraseRootFromParent_Done,
19004 /* 48281 */ // Label 1238: @48281
19005 /* 48281 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(48340), // Rule ID 1667 //
19006 /* 48286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19007 /* 48289 */ // MIs[0] Operand 1
19008 /* 48289 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19009 /* 48294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19010 /* 48298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19011 /* 48302 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
19012 /* 48302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19013 /* 48305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19014 /* 48309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19015 /* 48314 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19016 /* 48318 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19017 /* 48322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19018 /* 48324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19019 /* 48327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19020 /* 48329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19021 /* 48335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19022 /* 48338 */ GIR_RootConstrainSelectedInstOperands,
19023 /* 48339 */ // GIR_Coverage, 1667,
19024 /* 48339 */ GIR_EraseRootFromParent_Done,
19025 /* 48340 */ // Label 1239: @48340
19026 /* 48340 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(48396), // Rule ID 1668 //
19027 /* 48345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19028 /* 48348 */ // MIs[0] Operand 1
19029 /* 48348 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19030 /* 48353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19031 /* 48357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19032 /* 48361 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
19033 /* 48361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19034 /* 48364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19035 /* 48368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19036 /* 48373 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19037 /* 48377 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19038 /* 48381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19039 /* 48383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19040 /* 48386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19041 /* 48388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19042 /* 48391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19043 /* 48394 */ GIR_RootConstrainSelectedInstOperands,
19044 /* 48395 */ // GIR_Coverage, 1668,
19045 /* 48395 */ GIR_EraseRootFromParent_Done,
19046 /* 48396 */ // Label 1240: @48396
19047 /* 48396 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(48452), // Rule ID 1669 //
19048 /* 48401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19049 /* 48404 */ // MIs[0] Operand 1
19050 /* 48404 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19051 /* 48409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19052 /* 48413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19053 /* 48417 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
19054 /* 48417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19055 /* 48420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19056 /* 48424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19057 /* 48429 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19058 /* 48433 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19059 /* 48437 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19060 /* 48439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19061 /* 48442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19062 /* 48444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19063 /* 48447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19064 /* 48450 */ GIR_RootConstrainSelectedInstOperands,
19065 /* 48451 */ // GIR_Coverage, 1669,
19066 /* 48451 */ GIR_EraseRootFromParent_Done,
19067 /* 48452 */ // Label 1241: @48452
19068 /* 48452 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(48484), // Rule ID 1670 //
19069 /* 48457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19070 /* 48460 */ // MIs[0] Operand 1
19071 /* 48460 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19072 /* 48465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19073 /* 48469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19074 /* 48473 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
19075 /* 48473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19076 /* 48476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19077 /* 48478 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19078 /* 48480 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19079 /* 48482 */ GIR_RootConstrainSelectedInstOperands,
19080 /* 48483 */ // GIR_Coverage, 1670,
19081 /* 48483 */ GIR_EraseRootFromParent_Done,
19082 /* 48484 */ // Label 1242: @48484
19083 /* 48484 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(48516), // Rule ID 1671 //
19084 /* 48489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19085 /* 48492 */ // MIs[0] Operand 1
19086 /* 48492 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19087 /* 48497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19088 /* 48501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19089 /* 48505 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
19090 /* 48505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19091 /* 48508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19092 /* 48510 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19093 /* 48512 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19094 /* 48514 */ GIR_RootConstrainSelectedInstOperands,
19095 /* 48515 */ // GIR_Coverage, 1671,
19096 /* 48515 */ GIR_EraseRootFromParent_Done,
19097 /* 48516 */ // Label 1243: @48516
19098 /* 48516 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(48572), // Rule ID 1672 //
19099 /* 48521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19100 /* 48524 */ // MIs[0] Operand 1
19101 /* 48524 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19102 /* 48529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19103 /* 48533 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19104 /* 48537 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
19105 /* 48537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19106 /* 48540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19107 /* 48544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19108 /* 48549 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19109 /* 48553 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19110 /* 48557 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19111 /* 48559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19112 /* 48562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19113 /* 48564 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19114 /* 48567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19115 /* 48570 */ GIR_RootConstrainSelectedInstOperands,
19116 /* 48571 */ // GIR_Coverage, 1672,
19117 /* 48571 */ GIR_EraseRootFromParent_Done,
19118 /* 48572 */ // Label 1244: @48572
19119 /* 48572 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(48628), // Rule ID 1673 //
19120 /* 48577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19121 /* 48580 */ // MIs[0] Operand 1
19122 /* 48580 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19123 /* 48585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19124 /* 48589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19125 /* 48593 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
19126 /* 48593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19127 /* 48596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19128 /* 48600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19129 /* 48605 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19130 /* 48609 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19131 /* 48613 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19132 /* 48615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19133 /* 48618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19134 /* 48620 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19135 /* 48623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19136 /* 48626 */ GIR_RootConstrainSelectedInstOperands,
19137 /* 48627 */ // GIR_Coverage, 1673,
19138 /* 48627 */ GIR_EraseRootFromParent_Done,
19139 /* 48628 */ // Label 1245: @48628
19140 /* 48628 */ GIM_Reject,
19141 /* 48629 */ // Label 1237: @48629
19142 /* 48629 */ GIM_Reject,
19143 /* 48630 */ // Label 1225: @48630
19144 /* 48630 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(49666),
19145 /* 48635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19146 /* 48638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19147 /* 48641 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(48701), // Rule ID 2013 //
19148 /* 48646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19149 /* 48649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19150 /* 48653 */ // MIs[0] Operand 1
19151 /* 48653 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19152 /* 48658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19153 /* 48662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19154 /* 48666 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19155 /* 48666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19156 /* 48669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19157 /* 48673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19158 /* 48678 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19159 /* 48682 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19160 /* 48686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19161 /* 48688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
19162 /* 48691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19163 /* 48693 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19164 /* 48696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19165 /* 48699 */ GIR_RootConstrainSelectedInstOperands,
19166 /* 48700 */ // GIR_Coverage, 2013,
19167 /* 48700 */ GIR_EraseRootFromParent_Done,
19168 /* 48701 */ // Label 1247: @48701
19169 /* 48701 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(48778), // Rule ID 2015 //
19170 /* 48706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19171 /* 48709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19172 /* 48713 */ // MIs[0] Operand 1
19173 /* 48713 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19174 /* 48718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19175 /* 48722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19176 /* 48726 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19177 /* 48726 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19178 /* 48729 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19179 /* 48733 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19180 /* 48738 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19181 /* 48741 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19182 /* 48743 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19183 /* 48746 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19184 /* 48750 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19185 /* 48755 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19186 /* 48759 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19187 /* 48763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19188 /* 48765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19189 /* 48768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19190 /* 48770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19191 /* 48773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19192 /* 48776 */ GIR_RootConstrainSelectedInstOperands,
19193 /* 48777 */ // GIR_Coverage, 2015,
19194 /* 48777 */ GIR_EraseRootFromParent_Done,
19195 /* 48778 */ // Label 1248: @48778
19196 /* 48778 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(48814), // Rule ID 2017 //
19197 /* 48783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19198 /* 48786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19199 /* 48790 */ // MIs[0] Operand 1
19200 /* 48790 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19201 /* 48795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19202 /* 48799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19203 /* 48803 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
19204 /* 48803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19205 /* 48806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19206 /* 48808 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19207 /* 48810 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19208 /* 48812 */ GIR_RootConstrainSelectedInstOperands,
19209 /* 48813 */ // GIR_Coverage, 2017,
19210 /* 48813 */ GIR_EraseRootFromParent_Done,
19211 /* 48814 */ // Label 1249: @48814
19212 /* 48814 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(48891), // Rule ID 2018 //
19213 /* 48819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19214 /* 48822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19215 /* 48826 */ // MIs[0] Operand 1
19216 /* 48826 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19217 /* 48831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19218 /* 48835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19219 /* 48839 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
19220 /* 48839 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19221 /* 48842 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
19222 /* 48846 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19223 /* 48851 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19224 /* 48854 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19225 /* 48856 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19226 /* 48859 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19227 /* 48863 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19228 /* 48868 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19229 /* 48872 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19230 /* 48876 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19231 /* 48878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19232 /* 48881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19233 /* 48883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19234 /* 48886 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19235 /* 48889 */ GIR_RootConstrainSelectedInstOperands,
19236 /* 48890 */ // GIR_Coverage, 2018,
19237 /* 48890 */ GIR_EraseRootFromParent_Done,
19238 /* 48891 */ // Label 1250: @48891
19239 /* 48891 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(48927), // Rule ID 2019 //
19240 /* 48896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19241 /* 48899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19242 /* 48903 */ // MIs[0] Operand 1
19243 /* 48903 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
19244 /* 48908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19245 /* 48912 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19246 /* 48916 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
19247 /* 48916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19248 /* 48919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19249 /* 48921 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
19250 /* 48923 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
19251 /* 48925 */ GIR_RootConstrainSelectedInstOperands,
19252 /* 48926 */ // GIR_Coverage, 2019,
19253 /* 48926 */ GIR_EraseRootFromParent_Done,
19254 /* 48927 */ // Label 1251: @48927
19255 /* 48927 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(49004), // Rule ID 2021 //
19256 /* 48932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19257 /* 48935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19258 /* 48939 */ // MIs[0] Operand 1
19259 /* 48939 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19260 /* 48944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19261 /* 48948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19262 /* 48952 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
19263 /* 48952 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19264 /* 48955 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19265 /* 48959 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19266 /* 48964 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19267 /* 48968 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19268 /* 48972 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19269 /* 48974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19270 /* 48977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19271 /* 48981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19272 /* 48986 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
19273 /* 48989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19274 /* 48991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19275 /* 48994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19276 /* 48996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19277 /* 48999 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19278 /* 49002 */ GIR_RootConstrainSelectedInstOperands,
19279 /* 49003 */ // GIR_Coverage, 2021,
19280 /* 49003 */ GIR_EraseRootFromParent_Done,
19281 /* 49004 */ // Label 1252: @49004
19282 /* 49004 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(49081), // Rule ID 2022 //
19283 /* 49009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19284 /* 49012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19285 /* 49016 */ // MIs[0] Operand 1
19286 /* 49016 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19287 /* 49021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19288 /* 49025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19289 /* 49029 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19290 /* 49029 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19291 /* 49032 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19292 /* 49036 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19293 /* 49041 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19294 /* 49044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19295 /* 49046 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19296 /* 49049 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19297 /* 49053 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19298 /* 49058 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19299 /* 49062 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19300 /* 49066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19301 /* 49068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19302 /* 49071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19303 /* 49073 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19304 /* 49076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19305 /* 49079 */ GIR_RootConstrainSelectedInstOperands,
19306 /* 49080 */ // GIR_Coverage, 2022,
19307 /* 49080 */ GIR_EraseRootFromParent_Done,
19308 /* 49081 */ // Label 1253: @49081
19309 /* 49081 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(49117), // Rule ID 2023 //
19310 /* 49086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19311 /* 49089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19312 /* 49093 */ // MIs[0] Operand 1
19313 /* 49093 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19314 /* 49098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19315 /* 49102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19316 /* 49106 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
19317 /* 49106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19318 /* 49109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19319 /* 49111 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19320 /* 49113 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19321 /* 49115 */ GIR_RootConstrainSelectedInstOperands,
19322 /* 49116 */ // GIR_Coverage, 2023,
19323 /* 49116 */ GIR_EraseRootFromParent_Done,
19324 /* 49117 */ // Label 1254: @49117
19325 /* 49117 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(49194), // Rule ID 2024 //
19326 /* 49122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19327 /* 49125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19328 /* 49129 */ // MIs[0] Operand 1
19329 /* 49129 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19330 /* 49134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19331 /* 49138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19332 /* 49142 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19333 /* 49142 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19334 /* 49145 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19335 /* 49149 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19336 /* 49154 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19337 /* 49157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19338 /* 49159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19339 /* 49162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19340 /* 49166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19341 /* 49171 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19342 /* 49175 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19343 /* 49179 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19344 /* 49181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19345 /* 49184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19346 /* 49186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19347 /* 49189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19348 /* 49192 */ GIR_RootConstrainSelectedInstOperands,
19349 /* 49193 */ // GIR_Coverage, 2024,
19350 /* 49193 */ GIR_EraseRootFromParent_Done,
19351 /* 49194 */ // Label 1255: @49194
19352 /* 49194 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(49230), // Rule ID 2025 //
19353 /* 49199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19354 /* 49202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19355 /* 49206 */ // MIs[0] Operand 1
19356 /* 49206 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
19357 /* 49211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19358 /* 49215 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19359 /* 49219 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
19360 /* 49219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19361 /* 49222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19362 /* 49224 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
19363 /* 49226 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
19364 /* 49228 */ GIR_RootConstrainSelectedInstOperands,
19365 /* 49229 */ // GIR_Coverage, 2025,
19366 /* 49229 */ GIR_EraseRootFromParent_Done,
19367 /* 49230 */ // Label 1256: @49230
19368 /* 49230 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(49290), // Rule ID 2337 //
19369 /* 49235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19370 /* 49238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19371 /* 49242 */ // MIs[0] Operand 1
19372 /* 49242 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19373 /* 49247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19374 /* 49251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19375 /* 49255 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19376 /* 49255 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19377 /* 49258 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
19378 /* 49262 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19379 /* 49267 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19380 /* 49271 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19381 /* 49275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19382 /* 49277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
19383 /* 49280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19384 /* 49282 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19385 /* 49285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19386 /* 49288 */ GIR_RootConstrainSelectedInstOperands,
19387 /* 49289 */ // GIR_Coverage, 2337,
19388 /* 49289 */ GIR_EraseRootFromParent_Done,
19389 /* 49290 */ // Label 1257: @49290
19390 /* 49290 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(49353), // Rule ID 2338 //
19391 /* 49295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19392 /* 49298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19393 /* 49302 */ // MIs[0] Operand 1
19394 /* 49302 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19395 /* 49307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19396 /* 49311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19397 /* 49315 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
19398 /* 49315 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19399 /* 49318 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
19400 /* 49322 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19401 /* 49327 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19402 /* 49331 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19403 /* 49335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19404 /* 49337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19405 /* 49340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19406 /* 49342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19407 /* 49348 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19408 /* 49351 */ GIR_RootConstrainSelectedInstOperands,
19409 /* 49352 */ // GIR_Coverage, 2338,
19410 /* 49352 */ GIR_EraseRootFromParent_Done,
19411 /* 49353 */ // Label 1258: @49353
19412 /* 49353 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(49413), // Rule ID 2339 //
19413 /* 49358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19414 /* 49361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19415 /* 49365 */ // MIs[0] Operand 1
19416 /* 49365 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19417 /* 49370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19418 /* 49374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19419 /* 49378 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
19420 /* 49378 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19421 /* 49381 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19422 /* 49385 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19423 /* 49390 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19424 /* 49394 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19425 /* 49398 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19426 /* 49400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19427 /* 49403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19428 /* 49405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19429 /* 49408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19430 /* 49411 */ GIR_RootConstrainSelectedInstOperands,
19431 /* 49412 */ // GIR_Coverage, 2339,
19432 /* 49412 */ GIR_EraseRootFromParent_Done,
19433 /* 49413 */ // Label 1259: @49413
19434 /* 49413 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(49473), // Rule ID 2340 //
19435 /* 49418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19436 /* 49421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19437 /* 49425 */ // MIs[0] Operand 1
19438 /* 49425 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19439 /* 49430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19440 /* 49434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19441 /* 49438 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
19442 /* 49438 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19443 /* 49441 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19444 /* 49445 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19445 /* 49450 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19446 /* 49454 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19447 /* 49458 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19448 /* 49460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19449 /* 49463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19450 /* 49465 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19451 /* 49468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19452 /* 49471 */ GIR_RootConstrainSelectedInstOperands,
19453 /* 49472 */ // GIR_Coverage, 2340,
19454 /* 49472 */ GIR_EraseRootFromParent_Done,
19455 /* 49473 */ // Label 1260: @49473
19456 /* 49473 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(49509), // Rule ID 2341 //
19457 /* 49478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19458 /* 49481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19459 /* 49485 */ // MIs[0] Operand 1
19460 /* 49485 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19461 /* 49490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19462 /* 49494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19463 /* 49498 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
19464 /* 49498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19465 /* 49501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19466 /* 49503 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19467 /* 49505 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19468 /* 49507 */ GIR_RootConstrainSelectedInstOperands,
19469 /* 49508 */ // GIR_Coverage, 2341,
19470 /* 49508 */ GIR_EraseRootFromParent_Done,
19471 /* 49509 */ // Label 1261: @49509
19472 /* 49509 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(49545), // Rule ID 2342 //
19473 /* 49514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19474 /* 49517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19475 /* 49521 */ // MIs[0] Operand 1
19476 /* 49521 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19477 /* 49526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19478 /* 49530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19479 /* 49534 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
19480 /* 49534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19481 /* 49537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19482 /* 49539 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19483 /* 49541 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19484 /* 49543 */ GIR_RootConstrainSelectedInstOperands,
19485 /* 49544 */ // GIR_Coverage, 2342,
19486 /* 49544 */ GIR_EraseRootFromParent_Done,
19487 /* 49545 */ // Label 1262: @49545
19488 /* 49545 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(49605), // Rule ID 2343 //
19489 /* 49550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19490 /* 49553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19491 /* 49557 */ // MIs[0] Operand 1
19492 /* 49557 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19493 /* 49562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19494 /* 49566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19495 /* 49570 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19496 /* 49570 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19497 /* 49573 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19498 /* 49577 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19499 /* 49582 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19500 /* 49586 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19501 /* 49590 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19502 /* 49592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19503 /* 49595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19504 /* 49597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19505 /* 49600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19506 /* 49603 */ GIR_RootConstrainSelectedInstOperands,
19507 /* 49604 */ // GIR_Coverage, 2343,
19508 /* 49604 */ GIR_EraseRootFromParent_Done,
19509 /* 49605 */ // Label 1263: @49605
19510 /* 49605 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(49665), // Rule ID 2344 //
19511 /* 49610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19512 /* 49613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19513 /* 49617 */ // MIs[0] Operand 1
19514 /* 49617 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19515 /* 49622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19516 /* 49626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19517 /* 49630 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19518 /* 49630 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19519 /* 49633 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19520 /* 49637 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19521 /* 49642 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19522 /* 49646 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19523 /* 49650 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19524 /* 49652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19525 /* 49655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19526 /* 49657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19527 /* 49660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19528 /* 49663 */ GIR_RootConstrainSelectedInstOperands,
19529 /* 49664 */ // GIR_Coverage, 2344,
19530 /* 49664 */ GIR_EraseRootFromParent_Done,
19531 /* 49665 */ // Label 1264: @49665
19532 /* 49665 */ GIM_Reject,
19533 /* 49666 */ // Label 1246: @49666
19534 /* 49666 */ GIM_Reject,
19535 /* 49667 */ // Label 1200: @49667
19536 /* 49667 */ GIM_Reject,
19537 /* 49668 */ // Label 42: @49668
19538 /* 49668 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(50667),
19539 /* 49673 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19540 /* 49676 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(50171),
19541 /* 49687 */ /*GILLT_s32*//*Label 1266*/ GIMT_Encode4(49695),
19542 /* 49691 */ /*GILLT_s64*//*Label 1267*/ GIMT_Encode4(49933),
19543 /* 49695 */ // Label 1266: @49695
19544 /* 49695 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(49932),
19545 /* 49700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19546 /* 49703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
19547 /* 49707 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(49739), // Rule ID 336 //
19548 /* 49712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19549 /* 49715 */ // MIs[0] Operand 1
19550 /* 49715 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19551 /* 49720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19552 /* 49724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19553 /* 49728 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19554 /* 49728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
19555 /* 49731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19556 /* 49733 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19557 /* 49735 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19558 /* 49737 */ GIR_RootConstrainSelectedInstOperands,
19559 /* 49738 */ // GIR_Coverage, 336,
19560 /* 49738 */ GIR_EraseRootFromParent_Done,
19561 /* 49739 */ // Label 1270: @49739
19562 /* 49739 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(49771), // Rule ID 337 //
19563 /* 49744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19564 /* 49747 */ // MIs[0] Operand 1
19565 /* 49747 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19566 /* 49752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19567 /* 49756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19568 /* 49760 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19569 /* 49760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
19570 /* 49763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19571 /* 49765 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19572 /* 49767 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19573 /* 49769 */ GIR_RootConstrainSelectedInstOperands,
19574 /* 49770 */ // GIR_Coverage, 337,
19575 /* 49770 */ GIR_EraseRootFromParent_Done,
19576 /* 49771 */ // Label 1271: @49771
19577 /* 49771 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(49803), // Rule ID 338 //
19578 /* 49776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19579 /* 49779 */ // MIs[0] Operand 1
19580 /* 49779 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19581 /* 49784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19582 /* 49788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19583 /* 49792 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19584 /* 49792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
19585 /* 49795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19586 /* 49797 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19587 /* 49799 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19588 /* 49801 */ GIR_RootConstrainSelectedInstOperands,
19589 /* 49802 */ // GIR_Coverage, 338,
19590 /* 49802 */ GIR_EraseRootFromParent_Done,
19591 /* 49803 */ // Label 1272: @49803
19592 /* 49803 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(49835), // Rule ID 339 //
19593 /* 49808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19594 /* 49811 */ // MIs[0] Operand 1
19595 /* 49811 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19596 /* 49816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19597 /* 49820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19598 /* 49824 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19599 /* 49824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
19600 /* 49827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19601 /* 49829 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19602 /* 49831 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19603 /* 49833 */ GIR_RootConstrainSelectedInstOperands,
19604 /* 49834 */ // GIR_Coverage, 339,
19605 /* 49834 */ GIR_EraseRootFromParent_Done,
19606 /* 49835 */ // Label 1273: @49835
19607 /* 49835 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(49867), // Rule ID 340 //
19608 /* 49840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19609 /* 49843 */ // MIs[0] Operand 1
19610 /* 49843 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19611 /* 49848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19612 /* 49852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19613 /* 49856 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19614 /* 49856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
19615 /* 49859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19616 /* 49861 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19617 /* 49863 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19618 /* 49865 */ GIR_RootConstrainSelectedInstOperands,
19619 /* 49866 */ // GIR_Coverage, 340,
19620 /* 49866 */ GIR_EraseRootFromParent_Done,
19621 /* 49867 */ // Label 1274: @49867
19622 /* 49867 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(49899), // Rule ID 341 //
19623 /* 49872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19624 /* 49875 */ // MIs[0] Operand 1
19625 /* 49875 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19626 /* 49880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19627 /* 49884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19628 /* 49888 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19629 /* 49888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
19630 /* 49891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19631 /* 49893 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19632 /* 49895 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19633 /* 49897 */ GIR_RootConstrainSelectedInstOperands,
19634 /* 49898 */ // GIR_Coverage, 341,
19635 /* 49898 */ GIR_EraseRootFromParent_Done,
19636 /* 49899 */ // Label 1275: @49899
19637 /* 49899 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(49931), // Rule ID 342 //
19638 /* 49904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19639 /* 49907 */ // MIs[0] Operand 1
19640 /* 49907 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19641 /* 49912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19642 /* 49916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19643 /* 49920 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19644 /* 49920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
19645 /* 49923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19646 /* 49925 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19647 /* 49927 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19648 /* 49929 */ GIR_RootConstrainSelectedInstOperands,
19649 /* 49930 */ // GIR_Coverage, 342,
19650 /* 49930 */ GIR_EraseRootFromParent_Done,
19651 /* 49931 */ // Label 1276: @49931
19652 /* 49931 */ GIM_Reject,
19653 /* 49932 */ // Label 1269: @49932
19654 /* 49932 */ GIM_Reject,
19655 /* 49933 */ // Label 1267: @49933
19656 /* 49933 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(50170),
19657 /* 49938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19658 /* 49941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
19659 /* 49945 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(49977), // Rule ID 343 //
19660 /* 49950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19661 /* 49953 */ // MIs[0] Operand 1
19662 /* 49953 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19663 /* 49958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19664 /* 49962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19665 /* 49966 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19666 /* 49966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
19667 /* 49969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19668 /* 49971 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19669 /* 49973 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19670 /* 49975 */ GIR_RootConstrainSelectedInstOperands,
19671 /* 49976 */ // GIR_Coverage, 343,
19672 /* 49976 */ GIR_EraseRootFromParent_Done,
19673 /* 49977 */ // Label 1278: @49977
19674 /* 49977 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(50009), // Rule ID 344 //
19675 /* 49982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19676 /* 49985 */ // MIs[0] Operand 1
19677 /* 49985 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19678 /* 49990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19679 /* 49994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19680 /* 49998 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19681 /* 49998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
19682 /* 50001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19683 /* 50003 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19684 /* 50005 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19685 /* 50007 */ GIR_RootConstrainSelectedInstOperands,
19686 /* 50008 */ // GIR_Coverage, 344,
19687 /* 50008 */ GIR_EraseRootFromParent_Done,
19688 /* 50009 */ // Label 1279: @50009
19689 /* 50009 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(50041), // Rule ID 345 //
19690 /* 50014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19691 /* 50017 */ // MIs[0] Operand 1
19692 /* 50017 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19693 /* 50022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19694 /* 50026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19695 /* 50030 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19696 /* 50030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
19697 /* 50033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19698 /* 50035 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19699 /* 50037 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19700 /* 50039 */ GIR_RootConstrainSelectedInstOperands,
19701 /* 50040 */ // GIR_Coverage, 345,
19702 /* 50040 */ GIR_EraseRootFromParent_Done,
19703 /* 50041 */ // Label 1280: @50041
19704 /* 50041 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(50073), // Rule ID 346 //
19705 /* 50046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19706 /* 50049 */ // MIs[0] Operand 1
19707 /* 50049 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19708 /* 50054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19709 /* 50058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19710 /* 50062 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19711 /* 50062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
19712 /* 50065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19713 /* 50067 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19714 /* 50069 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19715 /* 50071 */ GIR_RootConstrainSelectedInstOperands,
19716 /* 50072 */ // GIR_Coverage, 346,
19717 /* 50072 */ GIR_EraseRootFromParent_Done,
19718 /* 50073 */ // Label 1281: @50073
19719 /* 50073 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(50105), // Rule ID 347 //
19720 /* 50078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19721 /* 50081 */ // MIs[0] Operand 1
19722 /* 50081 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19723 /* 50086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19724 /* 50090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19725 /* 50094 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19726 /* 50094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
19727 /* 50097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19728 /* 50099 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19729 /* 50101 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19730 /* 50103 */ GIR_RootConstrainSelectedInstOperands,
19731 /* 50104 */ // GIR_Coverage, 347,
19732 /* 50104 */ GIR_EraseRootFromParent_Done,
19733 /* 50105 */ // Label 1282: @50105
19734 /* 50105 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(50137), // Rule ID 348 //
19735 /* 50110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19736 /* 50113 */ // MIs[0] Operand 1
19737 /* 50113 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19738 /* 50118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19739 /* 50122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19740 /* 50126 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19741 /* 50126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
19742 /* 50129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19743 /* 50131 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19744 /* 50133 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19745 /* 50135 */ GIR_RootConstrainSelectedInstOperands,
19746 /* 50136 */ // GIR_Coverage, 348,
19747 /* 50136 */ GIR_EraseRootFromParent_Done,
19748 /* 50137 */ // Label 1283: @50137
19749 /* 50137 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(50169), // Rule ID 349 //
19750 /* 50142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19751 /* 50145 */ // MIs[0] Operand 1
19752 /* 50145 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19753 /* 50150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19754 /* 50154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19755 /* 50158 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19756 /* 50158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
19757 /* 50161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19758 /* 50163 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19759 /* 50165 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19760 /* 50167 */ GIR_RootConstrainSelectedInstOperands,
19761 /* 50168 */ // GIR_Coverage, 349,
19762 /* 50168 */ GIR_EraseRootFromParent_Done,
19763 /* 50169 */ // Label 1284: @50169
19764 /* 50169 */ GIM_Reject,
19765 /* 50170 */ // Label 1277: @50170
19766 /* 50170 */ GIM_Reject,
19767 /* 50171 */ // Label 1268: @50171
19768 /* 50171 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1287*/ GIMT_Encode4(50666),
19769 /* 50182 */ /*GILLT_s32*//*Label 1285*/ GIMT_Encode4(50190),
19770 /* 50186 */ /*GILLT_s64*//*Label 1286*/ GIMT_Encode4(50428),
19771 /* 50190 */ // Label 1285: @50190
19772 /* 50190 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(50427),
19773 /* 50195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19774 /* 50198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
19775 /* 50202 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(50234), // Rule ID 1216 //
19776 /* 50207 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19777 /* 50210 */ // MIs[0] Operand 1
19778 /* 50210 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19779 /* 50215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19780 /* 50219 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19781 /* 50223 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19782 /* 50223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
19783 /* 50226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19784 /* 50228 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19785 /* 50230 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19786 /* 50232 */ GIR_RootConstrainSelectedInstOperands,
19787 /* 50233 */ // GIR_Coverage, 1216,
19788 /* 50233 */ GIR_EraseRootFromParent_Done,
19789 /* 50234 */ // Label 1289: @50234
19790 /* 50234 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(50266), // Rule ID 1217 //
19791 /* 50239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19792 /* 50242 */ // MIs[0] Operand 1
19793 /* 50242 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19794 /* 50247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19795 /* 50251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19796 /* 50255 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19797 /* 50255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
19798 /* 50258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19799 /* 50260 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19800 /* 50262 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19801 /* 50264 */ GIR_RootConstrainSelectedInstOperands,
19802 /* 50265 */ // GIR_Coverage, 1217,
19803 /* 50265 */ GIR_EraseRootFromParent_Done,
19804 /* 50266 */ // Label 1290: @50266
19805 /* 50266 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(50298), // Rule ID 1218 //
19806 /* 50271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19807 /* 50274 */ // MIs[0] Operand 1
19808 /* 50274 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19809 /* 50279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19810 /* 50283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19811 /* 50287 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19812 /* 50287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
19813 /* 50290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19814 /* 50292 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19815 /* 50294 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19816 /* 50296 */ GIR_RootConstrainSelectedInstOperands,
19817 /* 50297 */ // GIR_Coverage, 1218,
19818 /* 50297 */ GIR_EraseRootFromParent_Done,
19819 /* 50298 */ // Label 1291: @50298
19820 /* 50298 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(50330), // Rule ID 1219 //
19821 /* 50303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19822 /* 50306 */ // MIs[0] Operand 1
19823 /* 50306 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19824 /* 50311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19825 /* 50315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19826 /* 50319 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19827 /* 50319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
19828 /* 50322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19829 /* 50324 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19830 /* 50326 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19831 /* 50328 */ GIR_RootConstrainSelectedInstOperands,
19832 /* 50329 */ // GIR_Coverage, 1219,
19833 /* 50329 */ GIR_EraseRootFromParent_Done,
19834 /* 50330 */ // Label 1292: @50330
19835 /* 50330 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(50362), // Rule ID 1220 //
19836 /* 50335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19837 /* 50338 */ // MIs[0] Operand 1
19838 /* 50338 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19839 /* 50343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19840 /* 50347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19841 /* 50351 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19842 /* 50351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
19843 /* 50354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19844 /* 50356 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19845 /* 50358 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19846 /* 50360 */ GIR_RootConstrainSelectedInstOperands,
19847 /* 50361 */ // GIR_Coverage, 1220,
19848 /* 50361 */ GIR_EraseRootFromParent_Done,
19849 /* 50362 */ // Label 1293: @50362
19850 /* 50362 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(50394), // Rule ID 1221 //
19851 /* 50367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19852 /* 50370 */ // MIs[0] Operand 1
19853 /* 50370 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19854 /* 50375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19855 /* 50379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19856 /* 50383 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19857 /* 50383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
19858 /* 50386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19859 /* 50388 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19860 /* 50390 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19861 /* 50392 */ GIR_RootConstrainSelectedInstOperands,
19862 /* 50393 */ // GIR_Coverage, 1221,
19863 /* 50393 */ GIR_EraseRootFromParent_Done,
19864 /* 50394 */ // Label 1294: @50394
19865 /* 50394 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(50426), // Rule ID 1222 //
19866 /* 50399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19867 /* 50402 */ // MIs[0] Operand 1
19868 /* 50402 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19869 /* 50407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19870 /* 50411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19871 /* 50415 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19872 /* 50415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
19873 /* 50418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19874 /* 50420 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19875 /* 50422 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19876 /* 50424 */ GIR_RootConstrainSelectedInstOperands,
19877 /* 50425 */ // GIR_Coverage, 1222,
19878 /* 50425 */ GIR_EraseRootFromParent_Done,
19879 /* 50426 */ // Label 1295: @50426
19880 /* 50426 */ GIM_Reject,
19881 /* 50427 */ // Label 1288: @50427
19882 /* 50427 */ GIM_Reject,
19883 /* 50428 */ // Label 1286: @50428
19884 /* 50428 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(50665),
19885 /* 50433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19886 /* 50436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
19887 /* 50440 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(50472), // Rule ID 1223 //
19888 /* 50445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19889 /* 50448 */ // MIs[0] Operand 1
19890 /* 50448 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19891 /* 50453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19892 /* 50457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19893 /* 50461 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19894 /* 50461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
19895 /* 50464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19896 /* 50466 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19897 /* 50468 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19898 /* 50470 */ GIR_RootConstrainSelectedInstOperands,
19899 /* 50471 */ // GIR_Coverage, 1223,
19900 /* 50471 */ GIR_EraseRootFromParent_Done,
19901 /* 50472 */ // Label 1297: @50472
19902 /* 50472 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(50504), // Rule ID 1224 //
19903 /* 50477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19904 /* 50480 */ // MIs[0] Operand 1
19905 /* 50480 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19906 /* 50485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19907 /* 50489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19908 /* 50493 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19909 /* 50493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
19910 /* 50496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19911 /* 50498 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19912 /* 50500 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19913 /* 50502 */ GIR_RootConstrainSelectedInstOperands,
19914 /* 50503 */ // GIR_Coverage, 1224,
19915 /* 50503 */ GIR_EraseRootFromParent_Done,
19916 /* 50504 */ // Label 1298: @50504
19917 /* 50504 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(50536), // Rule ID 1225 //
19918 /* 50509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19919 /* 50512 */ // MIs[0] Operand 1
19920 /* 50512 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19921 /* 50517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19922 /* 50521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19923 /* 50525 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19924 /* 50525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
19925 /* 50528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19926 /* 50530 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19927 /* 50532 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19928 /* 50534 */ GIR_RootConstrainSelectedInstOperands,
19929 /* 50535 */ // GIR_Coverage, 1225,
19930 /* 50535 */ GIR_EraseRootFromParent_Done,
19931 /* 50536 */ // Label 1299: @50536
19932 /* 50536 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(50568), // Rule ID 1226 //
19933 /* 50541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19934 /* 50544 */ // MIs[0] Operand 1
19935 /* 50544 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19936 /* 50549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19937 /* 50553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19938 /* 50557 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19939 /* 50557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
19940 /* 50560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19941 /* 50562 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19942 /* 50564 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19943 /* 50566 */ GIR_RootConstrainSelectedInstOperands,
19944 /* 50567 */ // GIR_Coverage, 1226,
19945 /* 50567 */ GIR_EraseRootFromParent_Done,
19946 /* 50568 */ // Label 1300: @50568
19947 /* 50568 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(50600), // Rule ID 1227 //
19948 /* 50573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19949 /* 50576 */ // MIs[0] Operand 1
19950 /* 50576 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19951 /* 50581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19952 /* 50585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19953 /* 50589 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19954 /* 50589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
19955 /* 50592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19956 /* 50594 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19957 /* 50596 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19958 /* 50598 */ GIR_RootConstrainSelectedInstOperands,
19959 /* 50599 */ // GIR_Coverage, 1227,
19960 /* 50599 */ GIR_EraseRootFromParent_Done,
19961 /* 50600 */ // Label 1301: @50600
19962 /* 50600 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(50632), // Rule ID 1228 //
19963 /* 50605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19964 /* 50608 */ // MIs[0] Operand 1
19965 /* 50608 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19966 /* 50613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19967 /* 50617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19968 /* 50621 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19969 /* 50621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
19970 /* 50624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19971 /* 50626 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19972 /* 50628 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19973 /* 50630 */ GIR_RootConstrainSelectedInstOperands,
19974 /* 50631 */ // GIR_Coverage, 1228,
19975 /* 50631 */ GIR_EraseRootFromParent_Done,
19976 /* 50632 */ // Label 1302: @50632
19977 /* 50632 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(50664), // Rule ID 1229 //
19978 /* 50637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19979 /* 50640 */ // MIs[0] Operand 1
19980 /* 50640 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19981 /* 50645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19982 /* 50649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19983 /* 50653 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19984 /* 50653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
19985 /* 50656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19986 /* 50658 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19987 /* 50660 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19988 /* 50662 */ GIR_RootConstrainSelectedInstOperands,
19989 /* 50663 */ // GIR_Coverage, 1229,
19990 /* 50663 */ GIR_EraseRootFromParent_Done,
19991 /* 50664 */ // Label 1303: @50664
19992 /* 50664 */ GIM_Reject,
19993 /* 50665 */ // Label 1296: @50665
19994 /* 50665 */ GIM_Reject,
19995 /* 50666 */ // Label 1287: @50666
19996 /* 50666 */ GIM_Reject,
19997 /* 50667 */ // Label 1265: @50667
19998 /* 50667 */ GIM_Reject,
19999 /* 50668 */ // Label 43: @50668
20000 /* 50668 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(62797),
20001 /* 50679 */ /*GILLT_s32*//*Label 1304*/ GIMT_Encode4(50711),
20002 /* 50683 */ /*GILLT_s64*//*Label 1305*/ GIMT_Encode4(57388), GIMT_Encode4(0),
20003 /* 50691 */ /*GILLT_v16s8*//*Label 1306*/ GIMT_Encode4(62507), GIMT_Encode4(0),
20004 /* 50699 */ /*GILLT_v8s16*//*Label 1307*/ GIMT_Encode4(62602),
20005 /* 50703 */ /*GILLT_v4s32*//*Label 1308*/ GIMT_Encode4(62649),
20006 /* 50707 */ /*GILLT_v2s64*//*Label 1309*/ GIMT_Encode4(62723),
20007 /* 50711 */ // Label 1304: @50711
20008 /* 50711 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(50787), // Rule ID 1746 //
20009 /* 50716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20010 /* 50719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20011 /* 50722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20012 /* 50725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20013 /* 50728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20014 /* 50732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20015 /* 50736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20016 /* 50740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20017 /* 50744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20018 /* 50748 */ // MIs[1] Operand 1
20019 /* 50748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20020 /* 50753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20021 /* 50758 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20022 /* 50762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20023 /* 50766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20024 /* 50770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20025 /* 50772 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20026 /* 50772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20027 /* 50775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20028 /* 50777 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20029 /* 50779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20030 /* 50783 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20031 /* 50785 */ GIR_RootConstrainSelectedInstOperands,
20032 /* 50786 */ // GIR_Coverage, 1746,
20033 /* 50786 */ GIR_EraseRootFromParent_Done,
20034 /* 50787 */ // Label 1311: @50787
20035 /* 50787 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(50863), // Rule ID 1750 //
20036 /* 50792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20037 /* 50795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20038 /* 50798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20039 /* 50801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20040 /* 50804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20041 /* 50808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20042 /* 50812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20043 /* 50816 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20044 /* 50820 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20045 /* 50824 */ // MIs[1] Operand 1
20046 /* 50824 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20047 /* 50829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20048 /* 50834 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20049 /* 50838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20050 /* 50842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20051 /* 50846 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20052 /* 50848 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20053 /* 50848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20054 /* 50851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20055 /* 50853 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20056 /* 50855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20057 /* 50859 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20058 /* 50861 */ GIR_RootConstrainSelectedInstOperands,
20059 /* 50862 */ // GIR_Coverage, 1750,
20060 /* 50862 */ GIR_EraseRootFromParent_Done,
20061 /* 50863 */ // Label 1312: @50863
20062 /* 50863 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(50939), // Rule ID 1778 //
20063 /* 50868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20064 /* 50871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20065 /* 50874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20066 /* 50877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20067 /* 50880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20068 /* 50884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20069 /* 50888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20070 /* 50892 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20071 /* 50896 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20072 /* 50900 */ // MIs[1] Operand 1
20073 /* 50900 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20074 /* 50905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20075 /* 50910 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20076 /* 50914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20077 /* 50918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20078 /* 50922 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20079 /* 50924 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
20080 /* 50924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
20081 /* 50927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20082 /* 50929 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20083 /* 50931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20084 /* 50935 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20085 /* 50937 */ GIR_RootConstrainSelectedInstOperands,
20086 /* 50938 */ // GIR_Coverage, 1778,
20087 /* 50938 */ GIR_EraseRootFromParent_Done,
20088 /* 50939 */ // Label 1313: @50939
20089 /* 50939 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(51015), // Rule ID 1789 //
20090 /* 50944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20091 /* 50947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20092 /* 50950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20093 /* 50953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20094 /* 50956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20095 /* 50960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20096 /* 50964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20097 /* 50968 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20098 /* 50972 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20099 /* 50976 */ // MIs[1] Operand 1
20100 /* 50976 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20101 /* 50981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20102 /* 50986 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20103 /* 50990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20104 /* 50994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20105 /* 50998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20106 /* 51000 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
20107 /* 51000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20108 /* 51003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20109 /* 51005 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20110 /* 51007 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20111 /* 51011 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20112 /* 51013 */ GIR_RootConstrainSelectedInstOperands,
20113 /* 51014 */ // GIR_Coverage, 1789,
20114 /* 51014 */ GIR_EraseRootFromParent_Done,
20115 /* 51015 */ // Label 1314: @51015
20116 /* 51015 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(51091), // Rule ID 1802 //
20117 /* 51020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20118 /* 51023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20119 /* 51026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20120 /* 51029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20121 /* 51032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20122 /* 51036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20123 /* 51040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20124 /* 51044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20125 /* 51048 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20126 /* 51052 */ // MIs[1] Operand 1
20127 /* 51052 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20128 /* 51057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20129 /* 51062 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20130 /* 51066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20131 /* 51070 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20132 /* 51074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20133 /* 51076 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20134 /* 51076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20135 /* 51079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20136 /* 51081 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20137 /* 51083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20138 /* 51087 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20139 /* 51089 */ GIR_RootConstrainSelectedInstOperands,
20140 /* 51090 */ // GIR_Coverage, 1802,
20141 /* 51090 */ GIR_EraseRootFromParent_Done,
20142 /* 51091 */ // Label 1315: @51091
20143 /* 51091 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(51167), // Rule ID 1805 //
20144 /* 51096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20145 /* 51099 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20146 /* 51102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20147 /* 51105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20148 /* 51108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20149 /* 51112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20150 /* 51116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20151 /* 51120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20152 /* 51124 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20153 /* 51128 */ // MIs[1] Operand 1
20154 /* 51128 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20155 /* 51133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20156 /* 51138 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20157 /* 51142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20158 /* 51146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20159 /* 51150 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20160 /* 51152 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20161 /* 51152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20162 /* 51155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20163 /* 51157 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20164 /* 51159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20165 /* 51163 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20166 /* 51165 */ GIR_RootConstrainSelectedInstOperands,
20167 /* 51166 */ // GIR_Coverage, 1805,
20168 /* 51166 */ GIR_EraseRootFromParent_Done,
20169 /* 51167 */ // Label 1316: @51167
20170 /* 51167 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(51243), // Rule ID 1815 //
20171 /* 51172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20172 /* 51175 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20173 /* 51178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20174 /* 51181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20175 /* 51184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20176 /* 51188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20177 /* 51192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20178 /* 51196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20179 /* 51200 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20180 /* 51204 */ // MIs[1] Operand 1
20181 /* 51204 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20182 /* 51209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20183 /* 51214 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20184 /* 51218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20185 /* 51222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20186 /* 51226 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20187 /* 51228 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
20188 /* 51228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
20189 /* 51231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20190 /* 51233 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20191 /* 51235 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20192 /* 51239 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20193 /* 51241 */ GIR_RootConstrainSelectedInstOperands,
20194 /* 51242 */ // GIR_Coverage, 1815,
20195 /* 51242 */ GIR_EraseRootFromParent_Done,
20196 /* 51243 */ // Label 1317: @51243
20197 /* 51243 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(51319), // Rule ID 1818 //
20198 /* 51248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20199 /* 51251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20200 /* 51254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20201 /* 51257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20202 /* 51260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20203 /* 51264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20204 /* 51268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20205 /* 51272 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20206 /* 51276 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20207 /* 51280 */ // MIs[1] Operand 1
20208 /* 51280 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20209 /* 51285 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20210 /* 51290 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20211 /* 51294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20212 /* 51298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20213 /* 51302 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20214 /* 51304 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
20215 /* 51304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20216 /* 51307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20217 /* 51309 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20218 /* 51311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20219 /* 51315 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20220 /* 51317 */ GIR_RootConstrainSelectedInstOperands,
20221 /* 51318 */ // GIR_Coverage, 1818,
20222 /* 51318 */ GIR_EraseRootFromParent_Done,
20223 /* 51319 */ // Label 1318: @51319
20224 /* 51319 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(51395), // Rule ID 2007 //
20225 /* 51324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20226 /* 51327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20227 /* 51330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20228 /* 51333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20229 /* 51336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20230 /* 51340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20231 /* 51344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20232 /* 51348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20233 /* 51352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20234 /* 51356 */ // MIs[1] Operand 1
20235 /* 51356 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20236 /* 51361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20237 /* 51366 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20238 /* 51370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20239 /* 51374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20240 /* 51378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20241 /* 51380 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20242 /* 51380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
20243 /* 51383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20244 /* 51385 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20245 /* 51387 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20246 /* 51389 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20247 /* 51393 */ GIR_RootConstrainSelectedInstOperands,
20248 /* 51394 */ // GIR_Coverage, 2007,
20249 /* 51394 */ GIR_EraseRootFromParent_Done,
20250 /* 51395 */ // Label 1319: @51395
20251 /* 51395 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(51471), // Rule ID 2010 //
20252 /* 51400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20253 /* 51403 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20254 /* 51406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20255 /* 51409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20256 /* 51412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20257 /* 51416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20258 /* 51420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20259 /* 51424 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20260 /* 51428 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20261 /* 51432 */ // MIs[1] Operand 1
20262 /* 51432 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20263 /* 51437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20264 /* 51442 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20265 /* 51446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20266 /* 51450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20267 /* 51454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20268 /* 51456 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20269 /* 51456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
20270 /* 51459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20271 /* 51461 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20272 /* 51463 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20273 /* 51465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20274 /* 51469 */ GIR_RootConstrainSelectedInstOperands,
20275 /* 51470 */ // GIR_Coverage, 2010,
20276 /* 51470 */ GIR_EraseRootFromParent_Done,
20277 /* 51471 */ // Label 1320: @51471
20278 /* 51471 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(51547), // Rule ID 2356 //
20279 /* 51476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20280 /* 51479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20281 /* 51482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20282 /* 51485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20283 /* 51488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20284 /* 51492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20285 /* 51496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20286 /* 51500 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20287 /* 51504 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20288 /* 51508 */ // MIs[1] Operand 1
20289 /* 51508 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20290 /* 51513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20291 /* 51518 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20292 /* 51522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20293 /* 51526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20294 /* 51530 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20295 /* 51532 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20296 /* 51532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20297 /* 51535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20298 /* 51537 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20299 /* 51539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20300 /* 51543 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20301 /* 51545 */ GIR_RootConstrainSelectedInstOperands,
20302 /* 51546 */ // GIR_Coverage, 2356,
20303 /* 51546 */ GIR_EraseRootFromParent_Done,
20304 /* 51547 */ // Label 1321: @51547
20305 /* 51547 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(51623), // Rule ID 2360 //
20306 /* 51552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
20307 /* 51555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20308 /* 51558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20309 /* 51561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20310 /* 51564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20311 /* 51568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20312 /* 51572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20313 /* 51576 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20314 /* 51580 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20315 /* 51584 */ // MIs[1] Operand 1
20316 /* 51584 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20317 /* 51589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20318 /* 51594 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20319 /* 51598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20320 /* 51602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20321 /* 51606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20322 /* 51608 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20323 /* 51608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20324 /* 51611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20325 /* 51613 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20326 /* 51615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20327 /* 51619 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20328 /* 51621 */ GIR_RootConstrainSelectedInstOperands,
20329 /* 51622 */ // GIR_Coverage, 2360,
20330 /* 51622 */ GIR_EraseRootFromParent_Done,
20331 /* 51623 */ // Label 1322: @51623
20332 /* 51623 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(51699), // Rule ID 2370 //
20333 /* 51628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20334 /* 51631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20335 /* 51634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20336 /* 51637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20337 /* 51640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20338 /* 51644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20339 /* 51648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20340 /* 51652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20341 /* 51656 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20342 /* 51660 */ // MIs[1] Operand 1
20343 /* 51660 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20344 /* 51665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20345 /* 51670 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20346 /* 51674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20347 /* 51678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20348 /* 51682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20349 /* 51684 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20350 /* 51684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20351 /* 51687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20352 /* 51689 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20353 /* 51691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20354 /* 51695 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20355 /* 51697 */ GIR_RootConstrainSelectedInstOperands,
20356 /* 51698 */ // GIR_Coverage, 2370,
20357 /* 51698 */ GIR_EraseRootFromParent_Done,
20358 /* 51699 */ // Label 1323: @51699
20359 /* 51699 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(51775), // Rule ID 2374 //
20360 /* 51704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20361 /* 51707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20362 /* 51710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20363 /* 51713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20364 /* 51716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20365 /* 51720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20366 /* 51724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20367 /* 51728 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20368 /* 51732 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20369 /* 51736 */ // MIs[1] Operand 1
20370 /* 51736 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20371 /* 51741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20372 /* 51746 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20373 /* 51750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20374 /* 51754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20375 /* 51758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20376 /* 51760 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20377 /* 51760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20378 /* 51763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20379 /* 51765 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20380 /* 51767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20381 /* 51771 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20382 /* 51773 */ GIR_RootConstrainSelectedInstOperands,
20383 /* 51774 */ // GIR_Coverage, 2374,
20384 /* 51774 */ GIR_EraseRootFromParent_Done,
20385 /* 51775 */ // Label 1324: @51775
20386 /* 51775 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(51851), // Rule ID 2417 //
20387 /* 51780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20388 /* 51783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20389 /* 51786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20390 /* 51789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20391 /* 51792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20392 /* 51796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20393 /* 51800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20394 /* 51804 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20395 /* 51808 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20396 /* 51812 */ // MIs[1] Operand 1
20397 /* 51812 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20398 /* 51817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20399 /* 51822 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20400 /* 51826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20401 /* 51830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20402 /* 51834 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20403 /* 51836 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20404 /* 51836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20405 /* 51839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20406 /* 51841 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20407 /* 51843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20408 /* 51847 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20409 /* 51849 */ GIR_RootConstrainSelectedInstOperands,
20410 /* 51850 */ // GIR_Coverage, 2417,
20411 /* 51850 */ GIR_EraseRootFromParent_Done,
20412 /* 51851 */ // Label 1325: @51851
20413 /* 51851 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(51927), // Rule ID 2420 //
20414 /* 51856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20415 /* 51859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20416 /* 51862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20417 /* 51865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20418 /* 51868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20419 /* 51872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20420 /* 51876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20421 /* 51880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20422 /* 51884 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20423 /* 51888 */ // MIs[1] Operand 1
20424 /* 51888 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20425 /* 51893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20426 /* 51898 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20427 /* 51902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20428 /* 51906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20429 /* 51910 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20430 /* 51912 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20431 /* 51912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20432 /* 51915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20433 /* 51917 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20434 /* 51919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20435 /* 51923 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20436 /* 51925 */ GIR_RootConstrainSelectedInstOperands,
20437 /* 51926 */ // GIR_Coverage, 2420,
20438 /* 51926 */ GIR_EraseRootFromParent_Done,
20439 /* 51927 */ // Label 1326: @51927
20440 /* 51927 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(52025), // Rule ID 1737 //
20441 /* 51932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20442 /* 51935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20443 /* 51938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20444 /* 51941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20445 /* 51944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20446 /* 51948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20447 /* 51952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20448 /* 51956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20449 /* 51960 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20450 /* 51964 */ // MIs[1] Operand 1
20451 /* 51964 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20452 /* 51969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20453 /* 51974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20454 /* 51979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20455 /* 51983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20456 /* 51987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20457 /* 51989 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20458 /* 51989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20459 /* 51992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20460 /* 51996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20461 /* 52001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20462 /* 52005 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20463 /* 52009 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20464 /* 52011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20465 /* 52014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20466 /* 52016 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20467 /* 52018 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20468 /* 52021 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20469 /* 52023 */ GIR_RootConstrainSelectedInstOperands,
20470 /* 52024 */ // GIR_Coverage, 1737,
20471 /* 52024 */ GIR_EraseRootFromParent_Done,
20472 /* 52025 */ // Label 1327: @52025
20473 /* 52025 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(52123), // Rule ID 1738 //
20474 /* 52030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20475 /* 52033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20476 /* 52036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20477 /* 52039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20478 /* 52042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20479 /* 52046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20480 /* 52050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20481 /* 52054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20482 /* 52058 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20483 /* 52062 */ // MIs[1] Operand 1
20484 /* 52062 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20485 /* 52067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20486 /* 52072 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20487 /* 52077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20488 /* 52081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20489 /* 52085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20490 /* 52087 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20491 /* 52087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20492 /* 52090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20493 /* 52094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20494 /* 52099 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20495 /* 52103 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20496 /* 52107 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20497 /* 52109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20498 /* 52112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20499 /* 52114 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20500 /* 52116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20501 /* 52119 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20502 /* 52121 */ GIR_RootConstrainSelectedInstOperands,
20503 /* 52122 */ // GIR_Coverage, 1738,
20504 /* 52122 */ GIR_EraseRootFromParent_Done,
20505 /* 52123 */ // Label 1328: @52123
20506 /* 52123 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(52221), // Rule ID 1741 //
20507 /* 52128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20508 /* 52131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20509 /* 52134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20510 /* 52137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20511 /* 52140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20512 /* 52144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20513 /* 52148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20514 /* 52152 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20515 /* 52156 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20516 /* 52160 */ // MIs[1] Operand 1
20517 /* 52160 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20518 /* 52165 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20519 /* 52170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20520 /* 52175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20521 /* 52179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20522 /* 52183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20523 /* 52185 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20524 /* 52185 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20525 /* 52188 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20526 /* 52192 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20527 /* 52197 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20528 /* 52201 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20529 /* 52205 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20530 /* 52207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20531 /* 52210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20532 /* 52212 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20533 /* 52214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20534 /* 52217 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20535 /* 52219 */ GIR_RootConstrainSelectedInstOperands,
20536 /* 52220 */ // GIR_Coverage, 1741,
20537 /* 52220 */ GIR_EraseRootFromParent_Done,
20538 /* 52221 */ // Label 1329: @52221
20539 /* 52221 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(52319), // Rule ID 1742 //
20540 /* 52226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20541 /* 52229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20542 /* 52232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20543 /* 52235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20544 /* 52238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20545 /* 52242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20546 /* 52246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20547 /* 52250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20548 /* 52254 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20549 /* 52258 */ // MIs[1] Operand 1
20550 /* 52258 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20551 /* 52263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20552 /* 52268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20553 /* 52273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20554 /* 52277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20555 /* 52281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20556 /* 52283 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20557 /* 52283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20558 /* 52286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20559 /* 52290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20560 /* 52295 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20561 /* 52299 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20562 /* 52303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20563 /* 52305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20564 /* 52308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20565 /* 52310 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20566 /* 52312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20567 /* 52315 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20568 /* 52317 */ GIR_RootConstrainSelectedInstOperands,
20569 /* 52318 */ // GIR_Coverage, 1742,
20570 /* 52318 */ GIR_EraseRootFromParent_Done,
20571 /* 52319 */ // Label 1330: @52319
20572 /* 52319 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(52417), // Rule ID 1745 //
20573 /* 52324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20574 /* 52327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20575 /* 52330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20576 /* 52333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20577 /* 52336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20578 /* 52340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20579 /* 52344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20580 /* 52348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20581 /* 52352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20582 /* 52356 */ // MIs[1] Operand 1
20583 /* 52356 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20584 /* 52361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20585 /* 52366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20586 /* 52371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20587 /* 52375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20588 /* 52379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20589 /* 52381 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20590 /* 52381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20591 /* 52384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20592 /* 52388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20593 /* 52393 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20594 /* 52397 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20595 /* 52401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20596 /* 52403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20597 /* 52406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20598 /* 52408 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20599 /* 52410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20600 /* 52413 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20601 /* 52415 */ GIR_RootConstrainSelectedInstOperands,
20602 /* 52416 */ // GIR_Coverage, 1745,
20603 /* 52416 */ GIR_EraseRootFromParent_Done,
20604 /* 52417 */ // Label 1331: @52417
20605 /* 52417 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(52515), // Rule ID 1748 //
20606 /* 52422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20607 /* 52425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20608 /* 52428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20609 /* 52431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20610 /* 52434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20611 /* 52438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20612 /* 52442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20613 /* 52446 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20614 /* 52450 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20615 /* 52454 */ // MIs[1] Operand 1
20616 /* 52454 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20617 /* 52459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20618 /* 52464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20619 /* 52469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20620 /* 52473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20621 /* 52477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20622 /* 52479 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20623 /* 52479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20624 /* 52482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20625 /* 52486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20626 /* 52491 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20627 /* 52495 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20628 /* 52499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20629 /* 52501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20630 /* 52504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20631 /* 52506 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20632 /* 52508 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20633 /* 52511 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20634 /* 52513 */ GIR_RootConstrainSelectedInstOperands,
20635 /* 52514 */ // GIR_Coverage, 1748,
20636 /* 52514 */ GIR_EraseRootFromParent_Done,
20637 /* 52515 */ // Label 1332: @52515
20638 /* 52515 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(52613), // Rule ID 1759 //
20639 /* 52520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20640 /* 52523 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20641 /* 52526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20642 /* 52529 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20643 /* 52532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20644 /* 52536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20645 /* 52540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20646 /* 52544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20647 /* 52548 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20648 /* 52552 */ // MIs[1] Operand 1
20649 /* 52552 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20650 /* 52557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20651 /* 52562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20652 /* 52567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20653 /* 52571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20654 /* 52575 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20655 /* 52577 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20656 /* 52577 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20657 /* 52580 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20658 /* 52584 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20659 /* 52589 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20660 /* 52593 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20661 /* 52597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20662 /* 52599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20663 /* 52602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20664 /* 52604 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20665 /* 52606 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20666 /* 52609 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20667 /* 52611 */ GIR_RootConstrainSelectedInstOperands,
20668 /* 52612 */ // GIR_Coverage, 1759,
20669 /* 52612 */ GIR_EraseRootFromParent_Done,
20670 /* 52613 */ // Label 1333: @52613
20671 /* 52613 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(52711), // Rule ID 1760 //
20672 /* 52618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20673 /* 52621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20674 /* 52624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20675 /* 52627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20676 /* 52630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20677 /* 52634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20678 /* 52638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20679 /* 52642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20680 /* 52646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20681 /* 52650 */ // MIs[1] Operand 1
20682 /* 52650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20683 /* 52655 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20684 /* 52660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20685 /* 52665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20686 /* 52669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20687 /* 52673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20688 /* 52675 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20689 /* 52675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20690 /* 52678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20691 /* 52682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20692 /* 52687 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20693 /* 52691 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20694 /* 52695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20695 /* 52697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20696 /* 52700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20697 /* 52702 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20698 /* 52704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20699 /* 52707 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20700 /* 52709 */ GIR_RootConstrainSelectedInstOperands,
20701 /* 52710 */ // GIR_Coverage, 1760,
20702 /* 52710 */ GIR_EraseRootFromParent_Done,
20703 /* 52711 */ // Label 1334: @52711
20704 /* 52711 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(52809), // Rule ID 1763 //
20705 /* 52716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20706 /* 52719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20707 /* 52722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20708 /* 52725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20709 /* 52728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20710 /* 52732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20711 /* 52736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20712 /* 52740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20713 /* 52744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20714 /* 52748 */ // MIs[1] Operand 1
20715 /* 52748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20716 /* 52753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20717 /* 52758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20718 /* 52763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20719 /* 52767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20720 /* 52771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20721 /* 52773 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20722 /* 52773 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20723 /* 52776 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20724 /* 52780 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20725 /* 52785 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20726 /* 52789 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20727 /* 52793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20728 /* 52795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20729 /* 52798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20730 /* 52800 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20731 /* 52802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20732 /* 52805 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20733 /* 52807 */ GIR_RootConstrainSelectedInstOperands,
20734 /* 52808 */ // GIR_Coverage, 1763,
20735 /* 52808 */ GIR_EraseRootFromParent_Done,
20736 /* 52809 */ // Label 1335: @52809
20737 /* 52809 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(52907), // Rule ID 1764 //
20738 /* 52814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20739 /* 52817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20740 /* 52820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20741 /* 52823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20742 /* 52826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20743 /* 52830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20744 /* 52834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20745 /* 52838 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20746 /* 52842 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20747 /* 52846 */ // MIs[1] Operand 1
20748 /* 52846 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20749 /* 52851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20750 /* 52856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20751 /* 52861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20752 /* 52865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20753 /* 52869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20754 /* 52871 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20755 /* 52871 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20756 /* 52874 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20757 /* 52878 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20758 /* 52883 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20759 /* 52887 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20760 /* 52891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20761 /* 52893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20762 /* 52896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20763 /* 52898 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20764 /* 52900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20765 /* 52903 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20766 /* 52905 */ GIR_RootConstrainSelectedInstOperands,
20767 /* 52906 */ // GIR_Coverage, 1764,
20768 /* 52906 */ GIR_EraseRootFromParent_Done,
20769 /* 52907 */ // Label 1336: @52907
20770 /* 52907 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(53005), // Rule ID 1777 //
20771 /* 52912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20772 /* 52915 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20773 /* 52918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20774 /* 52921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20775 /* 52924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20776 /* 52928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20777 /* 52932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20778 /* 52936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20779 /* 52940 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20780 /* 52944 */ // MIs[1] Operand 1
20781 /* 52944 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20782 /* 52949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20783 /* 52954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20784 /* 52959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20785 /* 52963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20786 /* 52967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20787 /* 52969 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20788 /* 52969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20789 /* 52972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20790 /* 52976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20791 /* 52981 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20792 /* 52985 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20793 /* 52989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20794 /* 52991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
20795 /* 52994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20796 /* 52996 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20797 /* 52998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20798 /* 53001 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20799 /* 53003 */ GIR_RootConstrainSelectedInstOperands,
20800 /* 53004 */ // GIR_Coverage, 1777,
20801 /* 53004 */ GIR_EraseRootFromParent_Done,
20802 /* 53005 */ // Label 1337: @53005
20803 /* 53005 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(53103), // Rule ID 1787 //
20804 /* 53010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20805 /* 53013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20806 /* 53016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20807 /* 53019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20808 /* 53022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20809 /* 53026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20810 /* 53030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20811 /* 53034 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20812 /* 53038 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20813 /* 53042 */ // MIs[1] Operand 1
20814 /* 53042 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20815 /* 53047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20816 /* 53052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20817 /* 53057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20818 /* 53061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20819 /* 53065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20820 /* 53067 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20821 /* 53067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20822 /* 53070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20823 /* 53074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20824 /* 53079 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20825 /* 53083 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20826 /* 53087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20827 /* 53089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20828 /* 53092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20829 /* 53094 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20830 /* 53096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20831 /* 53099 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20832 /* 53101 */ GIR_RootConstrainSelectedInstOperands,
20833 /* 53102 */ // GIR_Coverage, 1787,
20834 /* 53102 */ GIR_EraseRootFromParent_Done,
20835 /* 53103 */ // Label 1338: @53103
20836 /* 53103 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(53201), // Rule ID 1793 //
20837 /* 53108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20838 /* 53111 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20839 /* 53114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20840 /* 53117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20841 /* 53120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20842 /* 53124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20843 /* 53128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20844 /* 53132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20845 /* 53136 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20846 /* 53140 */ // MIs[1] Operand 1
20847 /* 53140 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20848 /* 53145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20849 /* 53150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20850 /* 53155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20851 /* 53159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20852 /* 53163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20853 /* 53165 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20854 /* 53165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20855 /* 53168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20856 /* 53172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20857 /* 53177 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20858 /* 53181 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20859 /* 53185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20860 /* 53187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20861 /* 53190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20862 /* 53192 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20863 /* 53194 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20864 /* 53197 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20865 /* 53199 */ GIR_RootConstrainSelectedInstOperands,
20866 /* 53200 */ // GIR_Coverage, 1793,
20867 /* 53200 */ GIR_EraseRootFromParent_Done,
20868 /* 53201 */ // Label 1339: @53201
20869 /* 53201 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(53299), // Rule ID 1794 //
20870 /* 53206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20871 /* 53209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20872 /* 53212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20873 /* 53215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20874 /* 53218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20875 /* 53222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20876 /* 53226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20877 /* 53230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20878 /* 53234 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20879 /* 53238 */ // MIs[1] Operand 1
20880 /* 53238 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20881 /* 53243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20882 /* 53248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20883 /* 53253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20884 /* 53257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20885 /* 53261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20886 /* 53263 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20887 /* 53263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20888 /* 53266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20889 /* 53270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20890 /* 53275 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20891 /* 53279 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20892 /* 53283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20893 /* 53285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20894 /* 53288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20895 /* 53290 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20896 /* 53292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20897 /* 53295 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20898 /* 53297 */ GIR_RootConstrainSelectedInstOperands,
20899 /* 53298 */ // GIR_Coverage, 1794,
20900 /* 53298 */ GIR_EraseRootFromParent_Done,
20901 /* 53299 */ // Label 1340: @53299
20902 /* 53299 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(53397), // Rule ID 1797 //
20903 /* 53304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20904 /* 53307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20905 /* 53310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20906 /* 53313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20907 /* 53316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20908 /* 53320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20909 /* 53324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20910 /* 53328 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20911 /* 53332 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20912 /* 53336 */ // MIs[1] Operand 1
20913 /* 53336 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20914 /* 53341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20915 /* 53346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20916 /* 53351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20917 /* 53355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20918 /* 53359 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20919 /* 53361 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20920 /* 53361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20921 /* 53364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20922 /* 53368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20923 /* 53373 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20924 /* 53377 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20925 /* 53381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20926 /* 53383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20927 /* 53386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20928 /* 53388 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20929 /* 53390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20930 /* 53393 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20931 /* 53395 */ GIR_RootConstrainSelectedInstOperands,
20932 /* 53396 */ // GIR_Coverage, 1797,
20933 /* 53396 */ GIR_EraseRootFromParent_Done,
20934 /* 53397 */ // Label 1341: @53397
20935 /* 53397 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(53495), // Rule ID 1798 //
20936 /* 53402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20937 /* 53405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20938 /* 53408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20939 /* 53411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20940 /* 53414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20941 /* 53418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20942 /* 53422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20943 /* 53426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20944 /* 53430 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20945 /* 53434 */ // MIs[1] Operand 1
20946 /* 53434 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20947 /* 53439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20948 /* 53444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20949 /* 53449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20950 /* 53453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20951 /* 53457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20952 /* 53459 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20953 /* 53459 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20954 /* 53462 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20955 /* 53466 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20956 /* 53471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20957 /* 53475 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20958 /* 53479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20959 /* 53481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20960 /* 53484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20961 /* 53486 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20962 /* 53488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20963 /* 53491 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20964 /* 53493 */ GIR_RootConstrainSelectedInstOperands,
20965 /* 53494 */ // GIR_Coverage, 1798,
20966 /* 53494 */ GIR_EraseRootFromParent_Done,
20967 /* 53495 */ // Label 1342: @53495
20968 /* 53495 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(53593), // Rule ID 1801 //
20969 /* 53500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20970 /* 53503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20971 /* 53506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20972 /* 53509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20973 /* 53512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20974 /* 53516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20975 /* 53520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20976 /* 53524 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20977 /* 53528 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20978 /* 53532 */ // MIs[1] Operand 1
20979 /* 53532 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20980 /* 53537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20981 /* 53542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20982 /* 53547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20983 /* 53551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20984 /* 53555 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20985 /* 53557 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20986 /* 53557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20987 /* 53560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20988 /* 53564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20989 /* 53569 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20990 /* 53573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20991 /* 53577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20992 /* 53579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20993 /* 53582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20994 /* 53584 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20995 /* 53586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20996 /* 53589 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20997 /* 53591 */ GIR_RootConstrainSelectedInstOperands,
20998 /* 53592 */ // GIR_Coverage, 1801,
20999 /* 53592 */ GIR_EraseRootFromParent_Done,
21000 /* 53593 */ // Label 1343: @53593
21001 /* 53593 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(53691), // Rule ID 1803 //
21002 /* 53598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
21003 /* 53601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21004 /* 53604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21005 /* 53607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21006 /* 53610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21007 /* 53614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21008 /* 53618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21009 /* 53622 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21010 /* 53626 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21011 /* 53630 */ // MIs[1] Operand 1
21012 /* 53630 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21013 /* 53635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21014 /* 53640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21015 /* 53645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21016 /* 53649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21017 /* 53653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21018 /* 53655 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21019 /* 53655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21020 /* 53658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21021 /* 53662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21022 /* 53667 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21023 /* 53671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21024 /* 53675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21025 /* 53677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
21026 /* 53680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21027 /* 53682 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21028 /* 53684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21029 /* 53687 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21030 /* 53689 */ GIR_RootConstrainSelectedInstOperands,
21031 /* 53690 */ // GIR_Coverage, 1803,
21032 /* 53690 */ GIR_EraseRootFromParent_Done,
21033 /* 53691 */ // Label 1344: @53691
21034 /* 53691 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(53789), // Rule ID 1806 //
21035 /* 53696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21036 /* 53699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21037 /* 53702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21038 /* 53705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21039 /* 53708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21040 /* 53712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21041 /* 53716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21042 /* 53720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21043 /* 53724 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21044 /* 53728 */ // MIs[1] Operand 1
21045 /* 53728 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21046 /* 53733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21047 /* 53738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21048 /* 53743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21049 /* 53747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21050 /* 53751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21051 /* 53753 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21052 /* 53753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21053 /* 53756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21054 /* 53760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21055 /* 53765 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21056 /* 53769 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21057 /* 53773 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21058 /* 53775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21059 /* 53778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21060 /* 53780 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21061 /* 53782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21062 /* 53785 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21063 /* 53787 */ GIR_RootConstrainSelectedInstOperands,
21064 /* 53788 */ // GIR_Coverage, 1806,
21065 /* 53788 */ GIR_EraseRootFromParent_Done,
21066 /* 53789 */ // Label 1345: @53789
21067 /* 53789 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(53887), // Rule ID 1807 //
21068 /* 53794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21069 /* 53797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21070 /* 53800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21071 /* 53803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21072 /* 53806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21073 /* 53810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21074 /* 53814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21075 /* 53818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21076 /* 53822 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21077 /* 53826 */ // MIs[1] Operand 1
21078 /* 53826 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21079 /* 53831 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21080 /* 53836 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21081 /* 53841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21082 /* 53845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21083 /* 53849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21084 /* 53851 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21085 /* 53851 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21086 /* 53854 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21087 /* 53858 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21088 /* 53863 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21089 /* 53867 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21090 /* 53871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21091 /* 53873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21092 /* 53876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21093 /* 53878 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21094 /* 53880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21095 /* 53883 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21096 /* 53885 */ GIR_RootConstrainSelectedInstOperands,
21097 /* 53886 */ // GIR_Coverage, 1807,
21098 /* 53886 */ GIR_EraseRootFromParent_Done,
21099 /* 53887 */ // Label 1346: @53887
21100 /* 53887 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(53985), // Rule ID 1810 //
21101 /* 53892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21102 /* 53895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21103 /* 53898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21104 /* 53901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21105 /* 53904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21106 /* 53908 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21107 /* 53912 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21108 /* 53916 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21109 /* 53920 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21110 /* 53924 */ // MIs[1] Operand 1
21111 /* 53924 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21112 /* 53929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21113 /* 53934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21114 /* 53939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21115 /* 53943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21116 /* 53947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21117 /* 53949 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
21118 /* 53949 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21119 /* 53952 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21120 /* 53956 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21121 /* 53961 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21122 /* 53965 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21123 /* 53969 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21124 /* 53971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21125 /* 53974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21126 /* 53976 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21127 /* 53978 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21128 /* 53981 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21129 /* 53983 */ GIR_RootConstrainSelectedInstOperands,
21130 /* 53984 */ // GIR_Coverage, 1810,
21131 /* 53984 */ GIR_EraseRootFromParent_Done,
21132 /* 53985 */ // Label 1347: @53985
21133 /* 53985 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(54083), // Rule ID 1811 //
21134 /* 53990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21135 /* 53993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21136 /* 53996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21137 /* 53999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21138 /* 54002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21139 /* 54006 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21140 /* 54010 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21141 /* 54014 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21142 /* 54018 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21143 /* 54022 */ // MIs[1] Operand 1
21144 /* 54022 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21145 /* 54027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21146 /* 54032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21147 /* 54037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21148 /* 54041 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21149 /* 54045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21150 /* 54047 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
21151 /* 54047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21152 /* 54050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21153 /* 54054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21154 /* 54059 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21155 /* 54063 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21156 /* 54067 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21157 /* 54069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21158 /* 54072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21159 /* 54074 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21160 /* 54076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21161 /* 54079 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21162 /* 54081 */ GIR_RootConstrainSelectedInstOperands,
21163 /* 54082 */ // GIR_Coverage, 1811,
21164 /* 54082 */ GIR_EraseRootFromParent_Done,
21165 /* 54083 */ // Label 1348: @54083
21166 /* 54083 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(54181), // Rule ID 1814 //
21167 /* 54088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21168 /* 54091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21169 /* 54094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21170 /* 54097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21171 /* 54100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21172 /* 54104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21173 /* 54108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21174 /* 54112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21175 /* 54116 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21176 /* 54120 */ // MIs[1] Operand 1
21177 /* 54120 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21178 /* 54125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21179 /* 54130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21180 /* 54135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21181 /* 54139 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21182 /* 54143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21183 /* 54145 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21184 /* 54145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21185 /* 54148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21186 /* 54152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21187 /* 54157 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21188 /* 54161 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21189 /* 54165 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21190 /* 54167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
21191 /* 54170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21192 /* 54172 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21193 /* 54174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21194 /* 54177 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21195 /* 54179 */ GIR_RootConstrainSelectedInstOperands,
21196 /* 54180 */ // GIR_Coverage, 1814,
21197 /* 54180 */ GIR_EraseRootFromParent_Done,
21198 /* 54181 */ // Label 1349: @54181
21199 /* 54181 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(54279), // Rule ID 1816 //
21200 /* 54186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21201 /* 54189 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21202 /* 54192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21203 /* 54195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21204 /* 54198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21205 /* 54202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21206 /* 54206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21207 /* 54210 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21208 /* 54214 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21209 /* 54218 */ // MIs[1] Operand 1
21210 /* 54218 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21211 /* 54223 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21212 /* 54228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21213 /* 54233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21214 /* 54237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21215 /* 54241 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21216 /* 54243 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21217 /* 54243 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21218 /* 54246 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21219 /* 54250 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21220 /* 54255 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21221 /* 54259 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21222 /* 54263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21223 /* 54265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
21224 /* 54268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21225 /* 54270 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21226 /* 54272 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21227 /* 54275 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21228 /* 54277 */ GIR_RootConstrainSelectedInstOperands,
21229 /* 54278 */ // GIR_Coverage, 1816,
21230 /* 54278 */ GIR_EraseRootFromParent_Done,
21231 /* 54279 */ // Label 1350: @54279
21232 /* 54279 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(54360), // Rule ID 1999 //
21233 /* 54284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21234 /* 54287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21235 /* 54290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21236 /* 54293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21237 /* 54296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21238 /* 54300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21239 /* 54304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21240 /* 54308 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21241 /* 54312 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21242 /* 54316 */ // MIs[1] Operand 1
21243 /* 54316 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21244 /* 54321 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21245 /* 54326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21246 /* 54331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21247 /* 54335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21248 /* 54339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21249 /* 54341 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
21250 /* 54341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
21251 /* 54344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21252 /* 54346 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21253 /* 54348 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21254 /* 54350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21255 /* 54354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21256 /* 54358 */ GIR_RootConstrainSelectedInstOperands,
21257 /* 54359 */ // GIR_Coverage, 1999,
21258 /* 54359 */ GIR_EraseRootFromParent_Done,
21259 /* 54360 */ // Label 1351: @54360
21260 /* 54360 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(54441), // Rule ID 2000 //
21261 /* 54365 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21262 /* 54368 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21263 /* 54371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21264 /* 54374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21265 /* 54377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21266 /* 54381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21267 /* 54385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21268 /* 54389 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21269 /* 54393 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21270 /* 54397 */ // MIs[1] Operand 1
21271 /* 54397 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
21272 /* 54402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21273 /* 54407 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21274 /* 54412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21275 /* 54416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21276 /* 54420 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21277 /* 54422 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21278 /* 54422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
21279 /* 54425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21280 /* 54427 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21281 /* 54429 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21282 /* 54431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21283 /* 54435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21284 /* 54439 */ GIR_RootConstrainSelectedInstOperands,
21285 /* 54440 */ // GIR_Coverage, 2000,
21286 /* 54440 */ GIR_EraseRootFromParent_Done,
21287 /* 54441 */ // Label 1352: @54441
21288 /* 54441 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(54522), // Rule ID 2001 //
21289 /* 54446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21290 /* 54449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21291 /* 54452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21292 /* 54455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21293 /* 54458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21294 /* 54462 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21295 /* 54466 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21296 /* 54470 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21297 /* 54474 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21298 /* 54478 */ // MIs[1] Operand 1
21299 /* 54478 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21300 /* 54483 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21301 /* 54488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21302 /* 54493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21303 /* 54497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21304 /* 54501 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21305 /* 54503 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
21306 /* 54503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
21307 /* 54506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21308 /* 54508 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21309 /* 54510 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21310 /* 54512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21311 /* 54516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21312 /* 54520 */ GIR_RootConstrainSelectedInstOperands,
21313 /* 54521 */ // GIR_Coverage, 2001,
21314 /* 54521 */ GIR_EraseRootFromParent_Done,
21315 /* 54522 */ // Label 1353: @54522
21316 /* 54522 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(54603), // Rule ID 2002 //
21317 /* 54527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21318 /* 54530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21319 /* 54533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21320 /* 54536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21321 /* 54539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21322 /* 54543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21323 /* 54547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21324 /* 54551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21325 /* 54555 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21326 /* 54559 */ // MIs[1] Operand 1
21327 /* 54559 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
21328 /* 54564 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21329 /* 54569 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21330 /* 54574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21331 /* 54578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21332 /* 54582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21333 /* 54584 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21334 /* 54584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
21335 /* 54587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21336 /* 54589 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21337 /* 54591 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21338 /* 54593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21339 /* 54597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21340 /* 54601 */ GIR_RootConstrainSelectedInstOperands,
21341 /* 54602 */ // GIR_Coverage, 2002,
21342 /* 54602 */ GIR_EraseRootFromParent_Done,
21343 /* 54603 */ // Label 1354: @54603
21344 /* 54603 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(54684), // Rule ID 2004 //
21345 /* 54608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21346 /* 54611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21347 /* 54614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21348 /* 54617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21349 /* 54620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21350 /* 54624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21351 /* 54628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21352 /* 54632 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21353 /* 54636 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21354 /* 54640 */ // MIs[1] Operand 1
21355 /* 54640 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21356 /* 54645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21357 /* 54650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21358 /* 54655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21359 /* 54659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21360 /* 54663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21361 /* 54665 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21362 /* 54665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
21363 /* 54668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21364 /* 54670 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21365 /* 54672 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21366 /* 54674 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21367 /* 54678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21368 /* 54682 */ GIR_RootConstrainSelectedInstOperands,
21369 /* 54683 */ // GIR_Coverage, 2004,
21370 /* 54683 */ GIR_EraseRootFromParent_Done,
21371 /* 54684 */ // Label 1355: @54684
21372 /* 54684 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(54765), // Rule ID 2005 //
21373 /* 54689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21374 /* 54692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21375 /* 54695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21376 /* 54698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21377 /* 54701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21378 /* 54705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21379 /* 54709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21380 /* 54713 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21381 /* 54717 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21382 /* 54721 */ // MIs[1] Operand 1
21383 /* 54721 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21384 /* 54726 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21385 /* 54731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21386 /* 54736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21387 /* 54740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21388 /* 54744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21389 /* 54746 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21390 /* 54746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
21391 /* 54749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21392 /* 54751 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21393 /* 54753 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21394 /* 54755 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21395 /* 54759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21396 /* 54763 */ GIR_RootConstrainSelectedInstOperands,
21397 /* 54764 */ // GIR_Coverage, 2005,
21398 /* 54764 */ GIR_EraseRootFromParent_Done,
21399 /* 54765 */ // Label 1356: @54765
21400 /* 54765 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(54846), // Rule ID 2006 //
21401 /* 54770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21402 /* 54773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21403 /* 54776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21404 /* 54779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21405 /* 54782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21406 /* 54786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21407 /* 54790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21408 /* 54794 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21409 /* 54798 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21410 /* 54802 */ // MIs[1] Operand 1
21411 /* 54802 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21412 /* 54807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21413 /* 54812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21414 /* 54817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21415 /* 54821 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21416 /* 54825 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21417 /* 54827 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21418 /* 54827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
21419 /* 54830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21420 /* 54832 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21421 /* 54834 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21422 /* 54836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21423 /* 54840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21424 /* 54844 */ GIR_RootConstrainSelectedInstOperands,
21425 /* 54845 */ // GIR_Coverage, 2006,
21426 /* 54845 */ GIR_EraseRootFromParent_Done,
21427 /* 54846 */ // Label 1357: @54846
21428 /* 54846 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(54927), // Rule ID 2009 //
21429 /* 54851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21430 /* 54854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21431 /* 54857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21432 /* 54860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21433 /* 54863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21434 /* 54867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21435 /* 54871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21436 /* 54875 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21437 /* 54879 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21438 /* 54883 */ // MIs[1] Operand 1
21439 /* 54883 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21440 /* 54888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21441 /* 54893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21442 /* 54898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21443 /* 54902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21444 /* 54906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21445 /* 54908 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21446 /* 54908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
21447 /* 54911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21448 /* 54913 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21449 /* 54915 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21450 /* 54917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21451 /* 54921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21452 /* 54925 */ GIR_RootConstrainSelectedInstOperands,
21453 /* 54926 */ // GIR_Coverage, 2009,
21454 /* 54926 */ GIR_EraseRootFromParent_Done,
21455 /* 54927 */ // Label 1358: @54927
21456 /* 54927 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(55025), // Rule ID 2347 //
21457 /* 54932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21458 /* 54935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21459 /* 54938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21460 /* 54941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21461 /* 54944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21462 /* 54948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21463 /* 54952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21464 /* 54956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21465 /* 54960 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21466 /* 54964 */ // MIs[1] Operand 1
21467 /* 54964 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21468 /* 54969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21469 /* 54974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21470 /* 54979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21471 /* 54983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21472 /* 54987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21473 /* 54989 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21474 /* 54989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21475 /* 54992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21476 /* 54996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21477 /* 55001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21478 /* 55005 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21479 /* 55009 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21480 /* 55011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21481 /* 55014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21482 /* 55016 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21483 /* 55018 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21484 /* 55021 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21485 /* 55023 */ GIR_RootConstrainSelectedInstOperands,
21486 /* 55024 */ // GIR_Coverage, 2347,
21487 /* 55024 */ GIR_EraseRootFromParent_Done,
21488 /* 55025 */ // Label 1359: @55025
21489 /* 55025 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(55123), // Rule ID 2348 //
21490 /* 55030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21491 /* 55033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21492 /* 55036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21493 /* 55039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21494 /* 55042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21495 /* 55046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21496 /* 55050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21497 /* 55054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21498 /* 55058 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21499 /* 55062 */ // MIs[1] Operand 1
21500 /* 55062 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21501 /* 55067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21502 /* 55072 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21503 /* 55077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21504 /* 55081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21505 /* 55085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21506 /* 55087 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21507 /* 55087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21508 /* 55090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21509 /* 55094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21510 /* 55099 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21511 /* 55103 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21512 /* 55107 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21513 /* 55109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21514 /* 55112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21515 /* 55114 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21516 /* 55116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21517 /* 55119 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21518 /* 55121 */ GIR_RootConstrainSelectedInstOperands,
21519 /* 55122 */ // GIR_Coverage, 2348,
21520 /* 55122 */ GIR_EraseRootFromParent_Done,
21521 /* 55123 */ // Label 1360: @55123
21522 /* 55123 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(55221), // Rule ID 2351 //
21523 /* 55128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21524 /* 55131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21525 /* 55134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21526 /* 55137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21527 /* 55140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21528 /* 55144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21529 /* 55148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21530 /* 55152 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21531 /* 55156 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21532 /* 55160 */ // MIs[1] Operand 1
21533 /* 55160 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21534 /* 55165 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21535 /* 55170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21536 /* 55175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21537 /* 55179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21538 /* 55183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21539 /* 55185 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21540 /* 55185 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21541 /* 55188 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21542 /* 55192 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21543 /* 55197 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21544 /* 55201 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21545 /* 55205 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21546 /* 55207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21547 /* 55210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21548 /* 55212 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21549 /* 55214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21550 /* 55217 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21551 /* 55219 */ GIR_RootConstrainSelectedInstOperands,
21552 /* 55220 */ // GIR_Coverage, 2351,
21553 /* 55220 */ GIR_EraseRootFromParent_Done,
21554 /* 55221 */ // Label 1361: @55221
21555 /* 55221 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(55319), // Rule ID 2352 //
21556 /* 55226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21557 /* 55229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21558 /* 55232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21559 /* 55235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21560 /* 55238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21561 /* 55242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21562 /* 55246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21563 /* 55250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21564 /* 55254 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21565 /* 55258 */ // MIs[1] Operand 1
21566 /* 55258 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21567 /* 55263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21568 /* 55268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21569 /* 55273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21570 /* 55277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21571 /* 55281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21572 /* 55283 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21573 /* 55283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21574 /* 55286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21575 /* 55290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21576 /* 55295 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21577 /* 55299 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21578 /* 55303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21579 /* 55305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21580 /* 55308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21581 /* 55310 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21582 /* 55312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21583 /* 55315 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21584 /* 55317 */ GIR_RootConstrainSelectedInstOperands,
21585 /* 55318 */ // GIR_Coverage, 2352,
21586 /* 55318 */ GIR_EraseRootFromParent_Done,
21587 /* 55319 */ // Label 1362: @55319
21588 /* 55319 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(55417), // Rule ID 2355 //
21589 /* 55324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21590 /* 55327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21591 /* 55330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21592 /* 55333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21593 /* 55336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21594 /* 55340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21595 /* 55344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21596 /* 55348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21597 /* 55352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21598 /* 55356 */ // MIs[1] Operand 1
21599 /* 55356 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21600 /* 55361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21601 /* 55366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21602 /* 55371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21603 /* 55375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21604 /* 55379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21605 /* 55381 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21606 /* 55381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21607 /* 55384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21608 /* 55388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21609 /* 55393 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21610 /* 55397 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21611 /* 55401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21612 /* 55403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21613 /* 55406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21614 /* 55408 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21615 /* 55410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21616 /* 55413 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21617 /* 55415 */ GIR_RootConstrainSelectedInstOperands,
21618 /* 55416 */ // GIR_Coverage, 2355,
21619 /* 55416 */ GIR_EraseRootFromParent_Done,
21620 /* 55417 */ // Label 1363: @55417
21621 /* 55417 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(55515), // Rule ID 2358 //
21622 /* 55422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
21623 /* 55425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21624 /* 55428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21625 /* 55431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21626 /* 55434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21627 /* 55438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21628 /* 55442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21629 /* 55446 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21630 /* 55450 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21631 /* 55454 */ // MIs[1] Operand 1
21632 /* 55454 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21633 /* 55459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21634 /* 55464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21635 /* 55469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21636 /* 55473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21637 /* 55477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21638 /* 55479 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21639 /* 55479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21640 /* 55482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21641 /* 55486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21642 /* 55491 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21643 /* 55495 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21644 /* 55499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21645 /* 55501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21646 /* 55504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21647 /* 55506 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21648 /* 55508 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21649 /* 55511 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21650 /* 55513 */ GIR_RootConstrainSelectedInstOperands,
21651 /* 55514 */ // GIR_Coverage, 2358,
21652 /* 55514 */ GIR_EraseRootFromParent_Done,
21653 /* 55515 */ // Label 1364: @55515
21654 /* 55515 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(55613), // Rule ID 2361 //
21655 /* 55520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21656 /* 55523 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21657 /* 55526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21658 /* 55529 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21659 /* 55532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21660 /* 55536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21661 /* 55540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21662 /* 55544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21663 /* 55548 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21664 /* 55552 */ // MIs[1] Operand 1
21665 /* 55552 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21666 /* 55557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21667 /* 55562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21668 /* 55567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21669 /* 55571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21670 /* 55575 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21671 /* 55577 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21672 /* 55577 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21673 /* 55580 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21674 /* 55584 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21675 /* 55589 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21676 /* 55593 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21677 /* 55597 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21678 /* 55599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21679 /* 55602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21680 /* 55604 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21681 /* 55606 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21682 /* 55609 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21683 /* 55611 */ GIR_RootConstrainSelectedInstOperands,
21684 /* 55612 */ // GIR_Coverage, 2361,
21685 /* 55612 */ GIR_EraseRootFromParent_Done,
21686 /* 55613 */ // Label 1365: @55613
21687 /* 55613 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(55711), // Rule ID 2362 //
21688 /* 55618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21689 /* 55621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21690 /* 55624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21691 /* 55627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21692 /* 55630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21693 /* 55634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21694 /* 55638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21695 /* 55642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21696 /* 55646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21697 /* 55650 */ // MIs[1] Operand 1
21698 /* 55650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21699 /* 55655 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21700 /* 55660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21701 /* 55665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21702 /* 55669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21703 /* 55673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21704 /* 55675 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21705 /* 55675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21706 /* 55678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21707 /* 55682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21708 /* 55687 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21709 /* 55691 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21710 /* 55695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21711 /* 55697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21712 /* 55700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21713 /* 55702 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21714 /* 55704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21715 /* 55707 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21716 /* 55709 */ GIR_RootConstrainSelectedInstOperands,
21717 /* 55710 */ // GIR_Coverage, 2362,
21718 /* 55710 */ GIR_EraseRootFromParent_Done,
21719 /* 55711 */ // Label 1366: @55711
21720 /* 55711 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(55809), // Rule ID 2365 //
21721 /* 55716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21722 /* 55719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21723 /* 55722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21724 /* 55725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21725 /* 55728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21726 /* 55732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21727 /* 55736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21728 /* 55740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21729 /* 55744 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21730 /* 55748 */ // MIs[1] Operand 1
21731 /* 55748 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21732 /* 55753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21733 /* 55758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21734 /* 55763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21735 /* 55767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21736 /* 55771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21737 /* 55773 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21738 /* 55773 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21739 /* 55776 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21740 /* 55780 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21741 /* 55785 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21742 /* 55789 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21743 /* 55793 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21744 /* 55795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21745 /* 55798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21746 /* 55800 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21747 /* 55802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21748 /* 55805 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21749 /* 55807 */ GIR_RootConstrainSelectedInstOperands,
21750 /* 55808 */ // GIR_Coverage, 2365,
21751 /* 55808 */ GIR_EraseRootFromParent_Done,
21752 /* 55809 */ // Label 1367: @55809
21753 /* 55809 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(55907), // Rule ID 2366 //
21754 /* 55814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21755 /* 55817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21756 /* 55820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21757 /* 55823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21758 /* 55826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21759 /* 55830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21760 /* 55834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21761 /* 55838 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21762 /* 55842 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21763 /* 55846 */ // MIs[1] Operand 1
21764 /* 55846 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21765 /* 55851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21766 /* 55856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21767 /* 55861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21768 /* 55865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21769 /* 55869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21770 /* 55871 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21771 /* 55871 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21772 /* 55874 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21773 /* 55878 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21774 /* 55883 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21775 /* 55887 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21776 /* 55891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21777 /* 55893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21778 /* 55896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21779 /* 55898 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21780 /* 55900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21781 /* 55903 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21782 /* 55905 */ GIR_RootConstrainSelectedInstOperands,
21783 /* 55906 */ // GIR_Coverage, 2366,
21784 /* 55906 */ GIR_EraseRootFromParent_Done,
21785 /* 55907 */ // Label 1368: @55907
21786 /* 55907 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(56005), // Rule ID 2369 //
21787 /* 55912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21788 /* 55915 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21789 /* 55918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21790 /* 55921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21791 /* 55924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21792 /* 55928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21793 /* 55932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21794 /* 55936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21795 /* 55940 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21796 /* 55944 */ // MIs[1] Operand 1
21797 /* 55944 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21798 /* 55949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21799 /* 55954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21800 /* 55959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21801 /* 55963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21802 /* 55967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21803 /* 55969 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21804 /* 55969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21805 /* 55972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21806 /* 55976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21807 /* 55981 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21808 /* 55985 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21809 /* 55989 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21810 /* 55991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21811 /* 55994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21812 /* 55996 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21813 /* 55998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21814 /* 56001 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21815 /* 56003 */ GIR_RootConstrainSelectedInstOperands,
21816 /* 56004 */ // GIR_Coverage, 2369,
21817 /* 56004 */ GIR_EraseRootFromParent_Done,
21818 /* 56005 */ // Label 1369: @56005
21819 /* 56005 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(56103), // Rule ID 2372 //
21820 /* 56010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21821 /* 56013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21822 /* 56016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21823 /* 56019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21824 /* 56022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21825 /* 56026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21826 /* 56030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21827 /* 56034 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21828 /* 56038 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21829 /* 56042 */ // MIs[1] Operand 1
21830 /* 56042 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21831 /* 56047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21832 /* 56052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21833 /* 56057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21834 /* 56061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21835 /* 56065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21836 /* 56067 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21837 /* 56067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21838 /* 56070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21839 /* 56074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21840 /* 56079 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21841 /* 56083 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21842 /* 56087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21843 /* 56089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21844 /* 56092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21845 /* 56094 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21846 /* 56096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21847 /* 56099 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21848 /* 56101 */ GIR_RootConstrainSelectedInstOperands,
21849 /* 56102 */ // GIR_Coverage, 2372,
21850 /* 56102 */ GIR_EraseRootFromParent_Done,
21851 /* 56103 */ // Label 1370: @56103
21852 /* 56103 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(56201), // Rule ID 2408 //
21853 /* 56108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21854 /* 56111 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21855 /* 56114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21856 /* 56117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21857 /* 56120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21858 /* 56124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21859 /* 56128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21860 /* 56132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21861 /* 56136 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21862 /* 56140 */ // MIs[1] Operand 1
21863 /* 56140 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21864 /* 56145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21865 /* 56150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21866 /* 56155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21867 /* 56159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21868 /* 56163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21869 /* 56165 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21870 /* 56165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21871 /* 56168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21872 /* 56172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21873 /* 56177 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21874 /* 56181 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21875 /* 56185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21876 /* 56187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21877 /* 56190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21878 /* 56192 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21879 /* 56194 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21880 /* 56197 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21881 /* 56199 */ GIR_RootConstrainSelectedInstOperands,
21882 /* 56200 */ // GIR_Coverage, 2408,
21883 /* 56200 */ GIR_EraseRootFromParent_Done,
21884 /* 56201 */ // Label 1371: @56201
21885 /* 56201 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(56299), // Rule ID 2409 //
21886 /* 56206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21887 /* 56209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21888 /* 56212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21889 /* 56215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21890 /* 56218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21891 /* 56222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21892 /* 56226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21893 /* 56230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21894 /* 56234 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21895 /* 56238 */ // MIs[1] Operand 1
21896 /* 56238 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21897 /* 56243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21898 /* 56248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21899 /* 56253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21900 /* 56257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21901 /* 56261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21902 /* 56263 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21903 /* 56263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21904 /* 56266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21905 /* 56270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21906 /* 56275 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21907 /* 56279 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21908 /* 56283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21909 /* 56285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21910 /* 56288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21911 /* 56290 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21912 /* 56292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21913 /* 56295 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21914 /* 56297 */ GIR_RootConstrainSelectedInstOperands,
21915 /* 56298 */ // GIR_Coverage, 2409,
21916 /* 56298 */ GIR_EraseRootFromParent_Done,
21917 /* 56299 */ // Label 1372: @56299
21918 /* 56299 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(56397), // Rule ID 2412 //
21919 /* 56304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21920 /* 56307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21921 /* 56310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21922 /* 56313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21923 /* 56316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21924 /* 56320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21925 /* 56324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21926 /* 56328 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21927 /* 56332 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21928 /* 56336 */ // MIs[1] Operand 1
21929 /* 56336 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21930 /* 56341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21931 /* 56346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21932 /* 56351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21933 /* 56355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21934 /* 56359 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21935 /* 56361 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21936 /* 56361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21937 /* 56364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21938 /* 56368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21939 /* 56373 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21940 /* 56377 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21941 /* 56381 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21942 /* 56383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21943 /* 56386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21944 /* 56388 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21945 /* 56390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21946 /* 56393 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21947 /* 56395 */ GIR_RootConstrainSelectedInstOperands,
21948 /* 56396 */ // GIR_Coverage, 2412,
21949 /* 56396 */ GIR_EraseRootFromParent_Done,
21950 /* 56397 */ // Label 1373: @56397
21951 /* 56397 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(56495), // Rule ID 2413 //
21952 /* 56402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21953 /* 56405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21954 /* 56408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21955 /* 56411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21956 /* 56414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21957 /* 56418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21958 /* 56422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21959 /* 56426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21960 /* 56430 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21961 /* 56434 */ // MIs[1] Operand 1
21962 /* 56434 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21963 /* 56439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21964 /* 56444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21965 /* 56449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21966 /* 56453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21967 /* 56457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21968 /* 56459 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21969 /* 56459 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21970 /* 56462 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21971 /* 56466 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21972 /* 56471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21973 /* 56475 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21974 /* 56479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21975 /* 56481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21976 /* 56484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21977 /* 56486 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21978 /* 56488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21979 /* 56491 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21980 /* 56493 */ GIR_RootConstrainSelectedInstOperands,
21981 /* 56494 */ // GIR_Coverage, 2413,
21982 /* 56494 */ GIR_EraseRootFromParent_Done,
21983 /* 56495 */ // Label 1374: @56495
21984 /* 56495 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(56593), // Rule ID 2416 //
21985 /* 56500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21986 /* 56503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21987 /* 56506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21988 /* 56509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21989 /* 56512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21990 /* 56516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21991 /* 56520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21992 /* 56524 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21993 /* 56528 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21994 /* 56532 */ // MIs[1] Operand 1
21995 /* 56532 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21996 /* 56537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21997 /* 56542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21998 /* 56547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21999 /* 56551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22000 /* 56555 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22001 /* 56557 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
22002 /* 56557 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22003 /* 56560 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22004 /* 56564 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22005 /* 56569 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22006 /* 56573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22007 /* 56577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22008 /* 56579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
22009 /* 56582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22010 /* 56584 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22011 /* 56586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22012 /* 56589 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22013 /* 56591 */ GIR_RootConstrainSelectedInstOperands,
22014 /* 56592 */ // GIR_Coverage, 2416,
22015 /* 56592 */ GIR_EraseRootFromParent_Done,
22016 /* 56593 */ // Label 1375: @56593
22017 /* 56593 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(56691), // Rule ID 2418 //
22018 /* 56598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22019 /* 56601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22020 /* 56604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22021 /* 56607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22022 /* 56610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22023 /* 56614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22024 /* 56618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22025 /* 56622 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22026 /* 56626 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22027 /* 56630 */ // MIs[1] Operand 1
22028 /* 56630 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22029 /* 56635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22030 /* 56640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22031 /* 56645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22032 /* 56649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22033 /* 56653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22034 /* 56655 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
22035 /* 56655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22036 /* 56658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22037 /* 56662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22038 /* 56667 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22039 /* 56671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22040 /* 56675 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22041 /* 56677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
22042 /* 56680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22043 /* 56682 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22044 /* 56684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22045 /* 56687 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22046 /* 56689 */ GIR_RootConstrainSelectedInstOperands,
22047 /* 56690 */ // GIR_Coverage, 2418,
22048 /* 56690 */ GIR_EraseRootFromParent_Done,
22049 /* 56691 */ // Label 1376: @56691
22050 /* 56691 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(56731), // Rule ID 319 //
22051 /* 56696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
22052 /* 56699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22053 /* 56702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22054 /* 56705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22055 /* 56708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22056 /* 56712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22057 /* 56716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22058 /* 56720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22059 /* 56724 */ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
22060 /* 56724 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
22061 /* 56729 */ GIR_RootConstrainSelectedInstOperands,
22062 /* 56730 */ // GIR_Coverage, 319,
22063 /* 56730 */ GIR_Done,
22064 /* 56731 */ // Label 1377: @56731
22065 /* 56731 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(56771), // Rule ID 321 //
22066 /* 56736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
22067 /* 56739 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22068 /* 56742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22069 /* 56745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22070 /* 56748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22071 /* 56752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22072 /* 56756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22073 /* 56760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22074 /* 56764 */ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
22075 /* 56764 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
22076 /* 56769 */ GIR_RootConstrainSelectedInstOperands,
22077 /* 56770 */ // GIR_Coverage, 321,
22078 /* 56770 */ GIR_Done,
22079 /* 56771 */ // Label 1378: @56771
22080 /* 56771 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(56817), // Rule ID 358 //
22081 /* 56776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
22082 /* 56779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22083 /* 56782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22084 /* 56785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22085 /* 56788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22086 /* 56792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
22087 /* 56796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22088 /* 56800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22089 /* 56804 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22090 /* 56804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
22091 /* 56807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22092 /* 56809 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22093 /* 56811 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22094 /* 56813 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22095 /* 56815 */ GIR_RootConstrainSelectedInstOperands,
22096 /* 56816 */ // GIR_Coverage, 358,
22097 /* 56816 */ GIR_EraseRootFromParent_Done,
22098 /* 56817 */ // Label 1379: @56817
22099 /* 56817 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(56863), // Rule ID 1236 //
22100 /* 56822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22101 /* 56825 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22102 /* 56828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22103 /* 56831 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22104 /* 56834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22105 /* 56838 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
22106 /* 56842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22107 /* 56846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22108 /* 56850 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22109 /* 56850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
22110 /* 56853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22111 /* 56855 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22112 /* 56857 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22113 /* 56859 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22114 /* 56861 */ GIR_RootConstrainSelectedInstOperands,
22115 /* 56862 */ // GIR_Coverage, 1236,
22116 /* 56862 */ GIR_EraseRootFromParent_Done,
22117 /* 56863 */ // Label 1380: @56863
22118 /* 56863 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(56909), // Rule ID 1749 //
22119 /* 56868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
22120 /* 56871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22121 /* 56874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22122 /* 56877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22123 /* 56880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22124 /* 56884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22125 /* 56888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22126 /* 56892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22127 /* 56896 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22128 /* 56896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
22129 /* 56899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22130 /* 56901 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22131 /* 56903 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22132 /* 56905 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22133 /* 56907 */ GIR_RootConstrainSelectedInstOperands,
22134 /* 56908 */ // GIR_Coverage, 1749,
22135 /* 56908 */ GIR_EraseRootFromParent_Done,
22136 /* 56909 */ // Label 1381: @56909
22137 /* 56909 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(56955), // Rule ID 1788 //
22138 /* 56914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22139 /* 56917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22140 /* 56920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22141 /* 56923 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22142 /* 56926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22143 /* 56930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22144 /* 56934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22145 /* 56938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22146 /* 56942 */ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
22147 /* 56942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
22148 /* 56945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22149 /* 56947 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22150 /* 56949 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22151 /* 56951 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22152 /* 56953 */ GIR_RootConstrainSelectedInstOperands,
22153 /* 56954 */ // GIR_Coverage, 1788,
22154 /* 56954 */ GIR_EraseRootFromParent_Done,
22155 /* 56955 */ // Label 1382: @56955
22156 /* 56955 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(57001), // Rule ID 1804 //
22157 /* 56960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
22158 /* 56963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22159 /* 56966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22160 /* 56969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22161 /* 56972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22162 /* 56976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22163 /* 56980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22164 /* 56984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22165 /* 56988 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
22166 /* 56988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
22167 /* 56991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22168 /* 56993 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22169 /* 56995 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22170 /* 56997 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22171 /* 56999 */ GIR_RootConstrainSelectedInstOperands,
22172 /* 57000 */ // GIR_Coverage, 1804,
22173 /* 57000 */ GIR_EraseRootFromParent_Done,
22174 /* 57001 */ // Label 1383: @57001
22175 /* 57001 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(57047), // Rule ID 1817 //
22176 /* 57006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22177 /* 57009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22178 /* 57012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22179 /* 57015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22180 /* 57018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22181 /* 57022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22182 /* 57026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22183 /* 57030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22184 /* 57034 */ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
22185 /* 57034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
22186 /* 57037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22187 /* 57039 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22188 /* 57041 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22189 /* 57043 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22190 /* 57045 */ GIR_RootConstrainSelectedInstOperands,
22191 /* 57046 */ // GIR_Coverage, 1817,
22192 /* 57046 */ GIR_EraseRootFromParent_Done,
22193 /* 57047 */ // Label 1384: @57047
22194 /* 57047 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(57093), // Rule ID 2011 //
22195 /* 57052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
22196 /* 57055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22197 /* 57058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22198 /* 57061 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22199 /* 57064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22200 /* 57068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22201 /* 57072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22202 /* 57076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22203 /* 57080 */ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
22204 /* 57080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
22205 /* 57083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
22206 /* 57085 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
22207 /* 57087 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
22208 /* 57089 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
22209 /* 57091 */ GIR_RootConstrainSelectedInstOperands,
22210 /* 57092 */ // GIR_Coverage, 2011,
22211 /* 57092 */ GIR_EraseRootFromParent_Done,
22212 /* 57093 */ // Label 1385: @57093
22213 /* 57093 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(57139), // Rule ID 2359 //
22214 /* 57098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
22215 /* 57101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22216 /* 57104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22217 /* 57107 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22218 /* 57110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22219 /* 57114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22220 /* 57118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22221 /* 57122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22222 /* 57126 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22223 /* 57126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
22224 /* 57129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22225 /* 57131 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22226 /* 57133 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22227 /* 57135 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22228 /* 57137 */ GIR_RootConstrainSelectedInstOperands,
22229 /* 57138 */ // GIR_Coverage, 2359,
22230 /* 57138 */ GIR_EraseRootFromParent_Done,
22231 /* 57139 */ // Label 1386: @57139
22232 /* 57139 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(57185), // Rule ID 2373 //
22233 /* 57144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22234 /* 57147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22235 /* 57150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22236 /* 57153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22237 /* 57156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22238 /* 57160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22239 /* 57164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22240 /* 57168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22241 /* 57172 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22242 /* 57172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
22243 /* 57175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22244 /* 57177 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22245 /* 57179 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22246 /* 57181 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22247 /* 57183 */ GIR_RootConstrainSelectedInstOperands,
22248 /* 57184 */ // GIR_Coverage, 2373,
22249 /* 57184 */ GIR_EraseRootFromParent_Done,
22250 /* 57185 */ // Label 1387: @57185
22251 /* 57185 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(57231), // Rule ID 2419 //
22252 /* 57190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22253 /* 57193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22254 /* 57196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22255 /* 57199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22256 /* 57202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22257 /* 57206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22258 /* 57210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22259 /* 57214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22260 /* 57218 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
22261 /* 57218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
22262 /* 57221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22263 /* 57223 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22264 /* 57225 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22265 /* 57227 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22266 /* 57229 */ GIR_RootConstrainSelectedInstOperands,
22267 /* 57230 */ // GIR_Coverage, 2419,
22268 /* 57230 */ GIR_EraseRootFromParent_Done,
22269 /* 57231 */ // Label 1388: @57231
22270 /* 57231 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(57309), // Rule ID 1878 //
22271 /* 57236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
22272 /* 57239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22273 /* 57242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22274 /* 57245 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22275 /* 57248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22276 /* 57252 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
22277 /* 57252 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
22278 /* 57255 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
22279 /* 57259 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22280 /* 57264 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22281 /* 57268 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22282 /* 57272 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22283 /* 57274 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22284 /* 57277 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
22285 /* 57281 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22286 /* 57286 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22287 /* 57290 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22288 /* 57294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22289 /* 57296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
22290 /* 57299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22291 /* 57301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22292 /* 57304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22293 /* 57307 */ GIR_RootConstrainSelectedInstOperands,
22294 /* 57308 */ // GIR_Coverage, 1878,
22295 /* 57308 */ GIR_EraseRootFromParent_Done,
22296 /* 57309 */ // Label 1389: @57309
22297 /* 57309 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(57387), // Rule ID 2436 //
22298 /* 57314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22299 /* 57317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22300 /* 57320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22301 /* 57323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22302 /* 57326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22303 /* 57330 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
22304 /* 57330 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
22305 /* 57333 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
22306 /* 57337 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22307 /* 57342 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22308 /* 57346 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22309 /* 57350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22310 /* 57352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22311 /* 57355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
22312 /* 57359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22313 /* 57364 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22314 /* 57368 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22315 /* 57372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22316 /* 57374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
22317 /* 57377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22318 /* 57379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22319 /* 57382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22320 /* 57385 */ GIR_RootConstrainSelectedInstOperands,
22321 /* 57386 */ // GIR_Coverage, 2436,
22322 /* 57386 */ GIR_EraseRootFromParent_Done,
22323 /* 57387 */ // Label 1390: @57387
22324 /* 57387 */ GIM_Reject,
22325 /* 57388 */ // Label 1305: @57388
22326 /* 57388 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(57464), // Rule ID 1776 //
22327 /* 57393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22328 /* 57396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22329 /* 57399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22330 /* 57402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22331 /* 57405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22332 /* 57409 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22333 /* 57413 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22334 /* 57417 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22335 /* 57421 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22336 /* 57425 */ // MIs[1] Operand 1
22337 /* 57425 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22338 /* 57430 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22339 /* 57435 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22340 /* 57439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22341 /* 57443 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22342 /* 57447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22343 /* 57449 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
22344 /* 57449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22345 /* 57452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22346 /* 57454 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22347 /* 57456 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22348 /* 57460 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22349 /* 57462 */ GIR_RootConstrainSelectedInstOperands,
22350 /* 57463 */ // GIR_Coverage, 1776,
22351 /* 57463 */ GIR_EraseRootFromParent_Done,
22352 /* 57464 */ // Label 1391: @57464
22353 /* 57464 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(57540), // Rule ID 1780 //
22354 /* 57469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22355 /* 57472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22356 /* 57475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22357 /* 57478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22358 /* 57481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22359 /* 57485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22360 /* 57489 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22361 /* 57493 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22362 /* 57497 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22363 /* 57501 */ // MIs[1] Operand 1
22364 /* 57501 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22365 /* 57506 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22366 /* 57511 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22367 /* 57515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22368 /* 57519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22369 /* 57523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22370 /* 57525 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
22371 /* 57525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
22372 /* 57528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22373 /* 57530 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22374 /* 57532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22375 /* 57536 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22376 /* 57538 */ GIR_RootConstrainSelectedInstOperands,
22377 /* 57539 */ // GIR_Coverage, 1780,
22378 /* 57539 */ GIR_EraseRootFromParent_Done,
22379 /* 57540 */ // Label 1392: @57540
22380 /* 57540 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(57616), // Rule ID 1786 //
22381 /* 57545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22382 /* 57548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22383 /* 57551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22384 /* 57554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22385 /* 57557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22386 /* 57561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22387 /* 57565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22388 /* 57569 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22389 /* 57573 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22390 /* 57577 */ // MIs[1] Operand 1
22391 /* 57577 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22392 /* 57582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22393 /* 57587 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22394 /* 57591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22395 /* 57595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22396 /* 57599 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22397 /* 57601 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
22398 /* 57601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22399 /* 57604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22400 /* 57606 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22401 /* 57608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22402 /* 57612 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22403 /* 57614 */ GIR_RootConstrainSelectedInstOperands,
22404 /* 57615 */ // GIR_Coverage, 1786,
22405 /* 57615 */ GIR_EraseRootFromParent_Done,
22406 /* 57616 */ // Label 1393: @57616
22407 /* 57616 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(57692), // Rule ID 1792 //
22408 /* 57621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22409 /* 57624 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22410 /* 57627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22411 /* 57630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22412 /* 57633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22413 /* 57637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22414 /* 57641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22415 /* 57645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22416 /* 57649 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22417 /* 57653 */ // MIs[1] Operand 1
22418 /* 57653 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22419 /* 57658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22420 /* 57663 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22421 /* 57667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22422 /* 57671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22423 /* 57675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22424 /* 57677 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
22425 /* 57677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22426 /* 57680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22427 /* 57682 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22428 /* 57684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22429 /* 57688 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22430 /* 57690 */ GIR_RootConstrainSelectedInstOperands,
22431 /* 57691 */ // GIR_Coverage, 1792,
22432 /* 57691 */ GIR_EraseRootFromParent_Done,
22433 /* 57692 */ // Label 1394: @57692
22434 /* 57692 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(57768), // Rule ID 1828 //
22435 /* 57697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22436 /* 57700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22437 /* 57703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22438 /* 57706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22439 /* 57709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22440 /* 57713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22441 /* 57717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22442 /* 57721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22443 /* 57725 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22444 /* 57729 */ // MIs[1] Operand 1
22445 /* 57729 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22446 /* 57734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22447 /* 57739 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22448 /* 57743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22449 /* 57747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22450 /* 57751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22451 /* 57753 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22452 /* 57753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22453 /* 57756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22454 /* 57758 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22455 /* 57760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22456 /* 57764 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22457 /* 57766 */ GIR_RootConstrainSelectedInstOperands,
22458 /* 57767 */ // GIR_Coverage, 1828,
22459 /* 57767 */ GIR_EraseRootFromParent_Done,
22460 /* 57768 */ // Label 1395: @57768
22461 /* 57768 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(57844), // Rule ID 1831 //
22462 /* 57773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22463 /* 57776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22464 /* 57779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22465 /* 57782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22466 /* 57785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22467 /* 57789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22468 /* 57793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22469 /* 57797 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22470 /* 57801 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22471 /* 57805 */ // MIs[1] Operand 1
22472 /* 57805 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22473 /* 57810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22474 /* 57815 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22475 /* 57819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22476 /* 57823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22477 /* 57827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22478 /* 57829 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22479 /* 57829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22480 /* 57832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22481 /* 57834 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22482 /* 57836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22483 /* 57840 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22484 /* 57842 */ GIR_RootConstrainSelectedInstOperands,
22485 /* 57843 */ // GIR_Coverage, 1831,
22486 /* 57843 */ GIR_EraseRootFromParent_Done,
22487 /* 57844 */ // Label 1396: @57844
22488 /* 57844 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(57920), // Rule ID 1849 //
22489 /* 57849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22490 /* 57852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22491 /* 57855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22492 /* 57858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22493 /* 57861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22494 /* 57865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22495 /* 57869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22496 /* 57873 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22497 /* 57877 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22498 /* 57881 */ // MIs[1] Operand 1
22499 /* 57881 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22500 /* 57886 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22501 /* 57891 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22502 /* 57895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22503 /* 57899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22504 /* 57903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22505 /* 57905 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22506 /* 57905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22507 /* 57908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22508 /* 57910 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22509 /* 57912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22510 /* 57916 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22511 /* 57918 */ GIR_RootConstrainSelectedInstOperands,
22512 /* 57919 */ // GIR_Coverage, 1849,
22513 /* 57919 */ GIR_EraseRootFromParent_Done,
22514 /* 57920 */ // Label 1397: @57920
22515 /* 57920 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(57996), // Rule ID 1851 //
22516 /* 57925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22517 /* 57928 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22518 /* 57931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22519 /* 57934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22520 /* 57937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22521 /* 57941 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22522 /* 57945 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22523 /* 57949 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22524 /* 57953 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22525 /* 57957 */ // MIs[1] Operand 1
22526 /* 57957 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22527 /* 57962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22528 /* 57967 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22529 /* 57971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22530 /* 57975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22531 /* 57979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22532 /* 57981 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22533 /* 57981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
22534 /* 57984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22535 /* 57986 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22536 /* 57988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22537 /* 57992 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22538 /* 57994 */ GIR_RootConstrainSelectedInstOperands,
22539 /* 57995 */ // GIR_Coverage, 1851,
22540 /* 57995 */ GIR_EraseRootFromParent_Done,
22541 /* 57996 */ // Label 1398: @57996
22542 /* 57996 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(58072), // Rule ID 1854 //
22543 /* 58001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22544 /* 58004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22545 /* 58007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22546 /* 58010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22547 /* 58013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22548 /* 58017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22549 /* 58021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22550 /* 58025 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22551 /* 58029 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22552 /* 58033 */ // MIs[1] Operand 1
22553 /* 58033 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22554 /* 58038 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22555 /* 58043 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22556 /* 58047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22557 /* 58051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22558 /* 58055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22559 /* 58057 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22560 /* 58057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22561 /* 58060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22562 /* 58062 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22563 /* 58064 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22564 /* 58068 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22565 /* 58070 */ GIR_RootConstrainSelectedInstOperands,
22566 /* 58071 */ // GIR_Coverage, 1854,
22567 /* 58071 */ GIR_EraseRootFromParent_Done,
22568 /* 58072 */ // Label 1399: @58072
22569 /* 58072 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(58148), // Rule ID 1857 //
22570 /* 58077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22571 /* 58080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22572 /* 58083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22573 /* 58086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22574 /* 58089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22575 /* 58093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22576 /* 58097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22577 /* 58101 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22578 /* 58105 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22579 /* 58109 */ // MIs[1] Operand 1
22580 /* 58109 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22581 /* 58114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22582 /* 58119 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22583 /* 58123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22584 /* 58127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22585 /* 58131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22586 /* 58133 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22587 /* 58133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22588 /* 58136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22589 /* 58138 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22590 /* 58140 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22591 /* 58144 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22592 /* 58146 */ GIR_RootConstrainSelectedInstOperands,
22593 /* 58147 */ // GIR_Coverage, 1857,
22594 /* 58147 */ GIR_EraseRootFromParent_Done,
22595 /* 58148 */ // Label 1400: @58148
22596 /* 58148 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(58224), // Rule ID 2430 //
22597 /* 58153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
22598 /* 58156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22599 /* 58159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22600 /* 58162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22601 /* 58165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22602 /* 58169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22603 /* 58173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22604 /* 58177 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22605 /* 58181 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22606 /* 58185 */ // MIs[1] Operand 1
22607 /* 58185 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22608 /* 58190 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22609 /* 58195 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22610 /* 58199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22611 /* 58203 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22612 /* 58207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22613 /* 58209 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22614 /* 58209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22615 /* 58212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22616 /* 58214 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22617 /* 58216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22618 /* 58220 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22619 /* 58222 */ GIR_RootConstrainSelectedInstOperands,
22620 /* 58223 */ // GIR_Coverage, 2430,
22621 /* 58223 */ GIR_EraseRootFromParent_Done,
22622 /* 58224 */ // Label 1401: @58224
22623 /* 58224 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(58300), // Rule ID 2433 //
22624 /* 58229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
22625 /* 58232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22626 /* 58235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22627 /* 58238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22628 /* 58241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22629 /* 58245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22630 /* 58249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22631 /* 58253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22632 /* 58257 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22633 /* 58261 */ // MIs[1] Operand 1
22634 /* 58261 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22635 /* 58266 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22636 /* 58271 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22637 /* 58275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22638 /* 58279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22639 /* 58283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22640 /* 58285 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22641 /* 58285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22642 /* 58288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22643 /* 58290 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22644 /* 58292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22645 /* 58296 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22646 /* 58298 */ GIR_RootConstrainSelectedInstOperands,
22647 /* 58299 */ // GIR_Coverage, 2433,
22648 /* 58299 */ GIR_EraseRootFromParent_Done,
22649 /* 58300 */ // Label 1402: @58300
22650 /* 58300 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(58398), // Rule ID 1751 //
22651 /* 58305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22652 /* 58308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22653 /* 58311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22654 /* 58314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22655 /* 58317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22656 /* 58321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22657 /* 58325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22658 /* 58329 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22659 /* 58333 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22660 /* 58337 */ // MIs[1] Operand 1
22661 /* 58337 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22662 /* 58342 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22663 /* 58347 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22664 /* 58352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22665 /* 58356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22666 /* 58360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22667 /* 58362 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22668 /* 58362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22669 /* 58365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22670 /* 58369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22671 /* 58374 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22672 /* 58378 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22673 /* 58382 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22674 /* 58384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22675 /* 58387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22676 /* 58389 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22677 /* 58391 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22678 /* 58394 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22679 /* 58396 */ GIR_RootConstrainSelectedInstOperands,
22680 /* 58397 */ // GIR_Coverage, 1751,
22681 /* 58397 */ GIR_EraseRootFromParent_Done,
22682 /* 58398 */ // Label 1403: @58398
22683 /* 58398 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(58496), // Rule ID 1752 //
22684 /* 58403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22685 /* 58406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22686 /* 58409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22687 /* 58412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22688 /* 58415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22689 /* 58419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22690 /* 58423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22691 /* 58427 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22692 /* 58431 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22693 /* 58435 */ // MIs[1] Operand 1
22694 /* 58435 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22695 /* 58440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22696 /* 58445 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22697 /* 58450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22698 /* 58454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22699 /* 58458 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22700 /* 58460 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22701 /* 58460 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22702 /* 58463 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22703 /* 58467 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22704 /* 58472 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22705 /* 58476 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22706 /* 58480 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22707 /* 58482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22708 /* 58485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22709 /* 58487 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22710 /* 58489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22711 /* 58492 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22712 /* 58494 */ GIR_RootConstrainSelectedInstOperands,
22713 /* 58495 */ // GIR_Coverage, 1752,
22714 /* 58495 */ GIR_EraseRootFromParent_Done,
22715 /* 58496 */ // Label 1404: @58496
22716 /* 58496 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(58594), // Rule ID 1755 //
22717 /* 58501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22718 /* 58504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22719 /* 58507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22720 /* 58510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22721 /* 58513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22722 /* 58517 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22723 /* 58521 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22724 /* 58525 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22725 /* 58529 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22726 /* 58533 */ // MIs[1] Operand 1
22727 /* 58533 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22728 /* 58538 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22729 /* 58543 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22730 /* 58548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22731 /* 58552 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22732 /* 58556 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22733 /* 58558 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22734 /* 58558 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22735 /* 58561 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22736 /* 58565 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22737 /* 58570 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22738 /* 58574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22739 /* 58578 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22740 /* 58580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22741 /* 58583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22742 /* 58585 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22743 /* 58587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22744 /* 58590 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22745 /* 58592 */ GIR_RootConstrainSelectedInstOperands,
22746 /* 58593 */ // GIR_Coverage, 1755,
22747 /* 58593 */ GIR_EraseRootFromParent_Done,
22748 /* 58594 */ // Label 1405: @58594
22749 /* 58594 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(58692), // Rule ID 1756 //
22750 /* 58599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22751 /* 58602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22752 /* 58605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22753 /* 58608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22754 /* 58611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22755 /* 58615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22756 /* 58619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22757 /* 58623 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22758 /* 58627 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22759 /* 58631 */ // MIs[1] Operand 1
22760 /* 58631 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22761 /* 58636 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22762 /* 58641 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22763 /* 58646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22764 /* 58650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22765 /* 58654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22766 /* 58656 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22767 /* 58656 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22768 /* 58659 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22769 /* 58663 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22770 /* 58668 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22771 /* 58672 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22772 /* 58676 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22773 /* 58678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22774 /* 58681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22775 /* 58683 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22776 /* 58685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22777 /* 58688 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22778 /* 58690 */ GIR_RootConstrainSelectedInstOperands,
22779 /* 58691 */ // GIR_Coverage, 1756,
22780 /* 58691 */ GIR_EraseRootFromParent_Done,
22781 /* 58692 */ // Label 1406: @58692
22782 /* 58692 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(58790), // Rule ID 1767 //
22783 /* 58697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22784 /* 58700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22785 /* 58703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22786 /* 58706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22787 /* 58709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22788 /* 58713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22789 /* 58717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22790 /* 58721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22791 /* 58725 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22792 /* 58729 */ // MIs[1] Operand 1
22793 /* 58729 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22794 /* 58734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22795 /* 58739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22796 /* 58744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22797 /* 58748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22798 /* 58752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22799 /* 58754 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22800 /* 58754 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22801 /* 58757 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22802 /* 58761 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22803 /* 58766 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22804 /* 58770 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22805 /* 58774 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22806 /* 58776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22807 /* 58779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22808 /* 58781 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22809 /* 58783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22810 /* 58786 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22811 /* 58788 */ GIR_RootConstrainSelectedInstOperands,
22812 /* 58789 */ // GIR_Coverage, 1767,
22813 /* 58789 */ GIR_EraseRootFromParent_Done,
22814 /* 58790 */ // Label 1407: @58790
22815 /* 58790 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(58888), // Rule ID 1768 //
22816 /* 58795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22817 /* 58798 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22818 /* 58801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22819 /* 58804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22820 /* 58807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22821 /* 58811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22822 /* 58815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22823 /* 58819 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22824 /* 58823 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22825 /* 58827 */ // MIs[1] Operand 1
22826 /* 58827 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22827 /* 58832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22828 /* 58837 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22829 /* 58842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22830 /* 58846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22831 /* 58850 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22832 /* 58852 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22833 /* 58852 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22834 /* 58855 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22835 /* 58859 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22836 /* 58864 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22837 /* 58868 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22838 /* 58872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22839 /* 58874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22840 /* 58877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22841 /* 58879 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22842 /* 58881 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22843 /* 58884 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22844 /* 58886 */ GIR_RootConstrainSelectedInstOperands,
22845 /* 58887 */ // GIR_Coverage, 1768,
22846 /* 58887 */ GIR_EraseRootFromParent_Done,
22847 /* 58888 */ // Label 1408: @58888
22848 /* 58888 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(58986), // Rule ID 1771 //
22849 /* 58893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22850 /* 58896 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22851 /* 58899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22852 /* 58902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22853 /* 58905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22854 /* 58909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22855 /* 58913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22856 /* 58917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22857 /* 58921 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22858 /* 58925 */ // MIs[1] Operand 1
22859 /* 58925 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22860 /* 58930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22861 /* 58935 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22862 /* 58940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22863 /* 58944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22864 /* 58948 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22865 /* 58950 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22866 /* 58950 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22867 /* 58953 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22868 /* 58957 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22869 /* 58962 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22870 /* 58966 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22871 /* 58970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22872 /* 58972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22873 /* 58975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22874 /* 58977 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22875 /* 58979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22876 /* 58982 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22877 /* 58984 */ GIR_RootConstrainSelectedInstOperands,
22878 /* 58985 */ // GIR_Coverage, 1771,
22879 /* 58985 */ GIR_EraseRootFromParent_Done,
22880 /* 58986 */ // Label 1409: @58986
22881 /* 58986 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(59084), // Rule ID 1772 //
22882 /* 58991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22883 /* 58994 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22884 /* 58997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22885 /* 59000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22886 /* 59003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22887 /* 59007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22888 /* 59011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22889 /* 59015 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22890 /* 59019 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22891 /* 59023 */ // MIs[1] Operand 1
22892 /* 59023 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22893 /* 59028 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22894 /* 59033 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22895 /* 59038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22896 /* 59042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22897 /* 59046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22898 /* 59048 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22899 /* 59048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22900 /* 59051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22901 /* 59055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22902 /* 59060 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22903 /* 59064 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22904 /* 59068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22905 /* 59070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22906 /* 59073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22907 /* 59075 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22908 /* 59077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22909 /* 59080 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22910 /* 59082 */ GIR_RootConstrainSelectedInstOperands,
22911 /* 59083 */ // GIR_Coverage, 1772,
22912 /* 59083 */ GIR_EraseRootFromParent_Done,
22913 /* 59084 */ // Label 1410: @59084
22914 /* 59084 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(59182), // Rule ID 1775 //
22915 /* 59089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22916 /* 59092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22917 /* 59095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22918 /* 59098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22919 /* 59101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22920 /* 59105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22921 /* 59109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22922 /* 59113 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22923 /* 59117 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22924 /* 59121 */ // MIs[1] Operand 1
22925 /* 59121 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22926 /* 59126 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22927 /* 59131 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22928 /* 59136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22929 /* 59140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22930 /* 59144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22931 /* 59146 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22932 /* 59146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22933 /* 59149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22934 /* 59153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22935 /* 59158 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22936 /* 59162 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22937 /* 59166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22938 /* 59168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22939 /* 59171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22940 /* 59173 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22941 /* 59175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22942 /* 59178 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22943 /* 59180 */ GIR_RootConstrainSelectedInstOperands,
22944 /* 59181 */ // GIR_Coverage, 1775,
22945 /* 59181 */ GIR_EraseRootFromParent_Done,
22946 /* 59182 */ // Label 1411: @59182
22947 /* 59182 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(59280), // Rule ID 1779 //
22948 /* 59187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22949 /* 59190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22950 /* 59193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22951 /* 59196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22952 /* 59199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22953 /* 59203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22954 /* 59207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22955 /* 59211 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22956 /* 59215 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22957 /* 59219 */ // MIs[1] Operand 1
22958 /* 59219 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22959 /* 59224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22960 /* 59229 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22961 /* 59234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22962 /* 59238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22963 /* 59242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22964 /* 59244 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22965 /* 59244 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22966 /* 59247 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22967 /* 59251 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22968 /* 59256 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22969 /* 59260 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22970 /* 59264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22971 /* 59266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
22972 /* 59269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22973 /* 59271 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22974 /* 59273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22975 /* 59276 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22976 /* 59278 */ GIR_RootConstrainSelectedInstOperands,
22977 /* 59279 */ // GIR_Coverage, 1779,
22978 /* 59279 */ GIR_EraseRootFromParent_Done,
22979 /* 59280 */ // Label 1412: @59280
22980 /* 59280 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(59378), // Rule ID 1784 //
22981 /* 59285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22982 /* 59288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22983 /* 59291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22984 /* 59294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22985 /* 59297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22986 /* 59301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22987 /* 59305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22988 /* 59309 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22989 /* 59313 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22990 /* 59317 */ // MIs[1] Operand 1
22991 /* 59317 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22992 /* 59322 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22993 /* 59327 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22994 /* 59332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22995 /* 59336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22996 /* 59340 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22997 /* 59342 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22998 /* 59342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22999 /* 59345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23000 /* 59349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23001 /* 59354 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23002 /* 59358 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23003 /* 59362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23004 /* 59364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
23005 /* 59367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23006 /* 59369 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23007 /* 59371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23008 /* 59374 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23009 /* 59376 */ GIR_RootConstrainSelectedInstOperands,
23010 /* 59377 */ // GIR_Coverage, 1784,
23011 /* 59377 */ GIR_EraseRootFromParent_Done,
23012 /* 59378 */ // Label 1413: @59378
23013 /* 59378 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(59476), // Rule ID 1790 //
23014 /* 59383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23015 /* 59386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23016 /* 59389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23017 /* 59392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23018 /* 59395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23019 /* 59399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23020 /* 59403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23021 /* 59407 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23022 /* 59411 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23023 /* 59415 */ // MIs[1] Operand 1
23024 /* 59415 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23025 /* 59420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23026 /* 59425 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23027 /* 59430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23028 /* 59434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23029 /* 59438 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23030 /* 59440 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
23031 /* 59440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23032 /* 59443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23033 /* 59447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23034 /* 59452 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23035 /* 59456 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23036 /* 59460 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23037 /* 59462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
23038 /* 59465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23039 /* 59467 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23040 /* 59469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23041 /* 59472 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23042 /* 59474 */ GIR_RootConstrainSelectedInstOperands,
23043 /* 59475 */ // GIR_Coverage, 1790,
23044 /* 59475 */ GIR_EraseRootFromParent_Done,
23045 /* 59476 */ // Label 1414: @59476
23046 /* 59476 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(59574), // Rule ID 1819 //
23047 /* 59481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23048 /* 59484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23049 /* 59487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23050 /* 59490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23051 /* 59493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23052 /* 59497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23053 /* 59501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23054 /* 59505 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23055 /* 59509 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23056 /* 59513 */ // MIs[1] Operand 1
23057 /* 59513 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23058 /* 59518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23059 /* 59523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23060 /* 59528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23061 /* 59532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23062 /* 59536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23063 /* 59538 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23064 /* 59538 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23065 /* 59541 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23066 /* 59545 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23067 /* 59550 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23068 /* 59554 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23069 /* 59558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23070 /* 59560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23071 /* 59563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23072 /* 59565 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23073 /* 59567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23074 /* 59570 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23075 /* 59572 */ GIR_RootConstrainSelectedInstOperands,
23076 /* 59573 */ // GIR_Coverage, 1819,
23077 /* 59573 */ GIR_EraseRootFromParent_Done,
23078 /* 59574 */ // Label 1415: @59574
23079 /* 59574 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(59672), // Rule ID 1820 //
23080 /* 59579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23081 /* 59582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23082 /* 59585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23083 /* 59588 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23084 /* 59591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23085 /* 59595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23086 /* 59599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23087 /* 59603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23088 /* 59607 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23089 /* 59611 */ // MIs[1] Operand 1
23090 /* 59611 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23091 /* 59616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23092 /* 59621 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23093 /* 59626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23094 /* 59630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23095 /* 59634 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23096 /* 59636 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23097 /* 59636 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23098 /* 59639 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23099 /* 59643 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23100 /* 59648 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23101 /* 59652 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23102 /* 59656 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23103 /* 59658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23104 /* 59661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23105 /* 59663 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23106 /* 59665 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23107 /* 59668 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23108 /* 59670 */ GIR_RootConstrainSelectedInstOperands,
23109 /* 59671 */ // GIR_Coverage, 1820,
23110 /* 59671 */ GIR_EraseRootFromParent_Done,
23111 /* 59672 */ // Label 1416: @59672
23112 /* 59672 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(59770), // Rule ID 1823 //
23113 /* 59677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23114 /* 59680 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23115 /* 59683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23116 /* 59686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23117 /* 59689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23118 /* 59693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23119 /* 59697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23120 /* 59701 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23121 /* 59705 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23122 /* 59709 */ // MIs[1] Operand 1
23123 /* 59709 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23124 /* 59714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23125 /* 59719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23126 /* 59724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23127 /* 59728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23128 /* 59732 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23129 /* 59734 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23130 /* 59734 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23131 /* 59737 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23132 /* 59741 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23133 /* 59746 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23134 /* 59750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23135 /* 59754 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23136 /* 59756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23137 /* 59759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23138 /* 59761 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23139 /* 59763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23140 /* 59766 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23141 /* 59768 */ GIR_RootConstrainSelectedInstOperands,
23142 /* 59769 */ // GIR_Coverage, 1823,
23143 /* 59769 */ GIR_EraseRootFromParent_Done,
23144 /* 59770 */ // Label 1417: @59770
23145 /* 59770 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(59868), // Rule ID 1824 //
23146 /* 59775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23147 /* 59778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23148 /* 59781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23149 /* 59784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23150 /* 59787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23151 /* 59791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23152 /* 59795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23153 /* 59799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23154 /* 59803 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23155 /* 59807 */ // MIs[1] Operand 1
23156 /* 59807 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23157 /* 59812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23158 /* 59817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23159 /* 59822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23160 /* 59826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23161 /* 59830 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23162 /* 59832 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23163 /* 59832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23164 /* 59835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23165 /* 59839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23166 /* 59844 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23167 /* 59848 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23168 /* 59852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23169 /* 59854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23170 /* 59857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23171 /* 59859 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23172 /* 59861 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23173 /* 59864 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23174 /* 59866 */ GIR_RootConstrainSelectedInstOperands,
23175 /* 59867 */ // GIR_Coverage, 1824,
23176 /* 59867 */ GIR_EraseRootFromParent_Done,
23177 /* 59868 */ // Label 1418: @59868
23178 /* 59868 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(59966), // Rule ID 1827 //
23179 /* 59873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23180 /* 59876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23181 /* 59879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23182 /* 59882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23183 /* 59885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23184 /* 59889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23185 /* 59893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23186 /* 59897 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23187 /* 59901 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23188 /* 59905 */ // MIs[1] Operand 1
23189 /* 59905 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23190 /* 59910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23191 /* 59915 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23192 /* 59920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23193 /* 59924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23194 /* 59928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23195 /* 59930 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23196 /* 59930 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23197 /* 59933 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23198 /* 59937 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23199 /* 59942 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23200 /* 59946 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23201 /* 59950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23202 /* 59952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23203 /* 59955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23204 /* 59957 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23205 /* 59959 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23206 /* 59962 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23207 /* 59964 */ GIR_RootConstrainSelectedInstOperands,
23208 /* 59965 */ // GIR_Coverage, 1827,
23209 /* 59965 */ GIR_EraseRootFromParent_Done,
23210 /* 59966 */ // Label 1419: @59966
23211 /* 59966 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(60064), // Rule ID 1829 //
23212 /* 59971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23213 /* 59974 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23214 /* 59977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23215 /* 59980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23216 /* 59983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23217 /* 59987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23218 /* 59991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23219 /* 59995 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23220 /* 59999 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23221 /* 60003 */ // MIs[1] Operand 1
23222 /* 60003 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23223 /* 60008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23224 /* 60013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23225 /* 60018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23226 /* 60022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23227 /* 60026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23228 /* 60028 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23229 /* 60028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23230 /* 60031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23231 /* 60035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23232 /* 60040 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23233 /* 60044 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23234 /* 60048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23235 /* 60050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
23236 /* 60053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23237 /* 60055 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23238 /* 60057 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23239 /* 60060 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23240 /* 60062 */ GIR_RootConstrainSelectedInstOperands,
23241 /* 60063 */ // GIR_Coverage, 1829,
23242 /* 60063 */ GIR_EraseRootFromParent_Done,
23243 /* 60064 */ // Label 1420: @60064
23244 /* 60064 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(60162), // Rule ID 1832 //
23245 /* 60069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23246 /* 60072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23247 /* 60075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23248 /* 60078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23249 /* 60081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23250 /* 60085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23251 /* 60089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23252 /* 60093 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23253 /* 60097 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23254 /* 60101 */ // MIs[1] Operand 1
23255 /* 60101 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23256 /* 60106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23257 /* 60111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23258 /* 60116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23259 /* 60120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23260 /* 60124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23261 /* 60126 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23262 /* 60126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23263 /* 60129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23264 /* 60133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23265 /* 60138 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23266 /* 60142 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23267 /* 60146 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23268 /* 60148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23269 /* 60151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23270 /* 60153 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23271 /* 60155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23272 /* 60158 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23273 /* 60160 */ GIR_RootConstrainSelectedInstOperands,
23274 /* 60161 */ // GIR_Coverage, 1832,
23275 /* 60161 */ GIR_EraseRootFromParent_Done,
23276 /* 60162 */ // Label 1421: @60162
23277 /* 60162 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(60260), // Rule ID 1833 //
23278 /* 60167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23279 /* 60170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23280 /* 60173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23281 /* 60176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23282 /* 60179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23283 /* 60183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23284 /* 60187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23285 /* 60191 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23286 /* 60195 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23287 /* 60199 */ // MIs[1] Operand 1
23288 /* 60199 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23289 /* 60204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23290 /* 60209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23291 /* 60214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23292 /* 60218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23293 /* 60222 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23294 /* 60224 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23295 /* 60224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23296 /* 60227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23297 /* 60231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23298 /* 60236 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23299 /* 60240 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23300 /* 60244 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23301 /* 60246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23302 /* 60249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23303 /* 60251 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23304 /* 60253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23305 /* 60256 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23306 /* 60258 */ GIR_RootConstrainSelectedInstOperands,
23307 /* 60259 */ // GIR_Coverage, 1833,
23308 /* 60259 */ GIR_EraseRootFromParent_Done,
23309 /* 60260 */ // Label 1422: @60260
23310 /* 60260 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(60358), // Rule ID 1836 //
23311 /* 60265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23312 /* 60268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23313 /* 60271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23314 /* 60274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23315 /* 60277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23316 /* 60281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23317 /* 60285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23318 /* 60289 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23319 /* 60293 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23320 /* 60297 */ // MIs[1] Operand 1
23321 /* 60297 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23322 /* 60302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23323 /* 60307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23324 /* 60312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23325 /* 60316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23326 /* 60320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23327 /* 60322 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
23328 /* 60322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23329 /* 60325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23330 /* 60329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23331 /* 60334 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23332 /* 60338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23333 /* 60342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23334 /* 60344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23335 /* 60347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23336 /* 60349 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23337 /* 60351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23338 /* 60354 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23339 /* 60356 */ GIR_RootConstrainSelectedInstOperands,
23340 /* 60357 */ // GIR_Coverage, 1836,
23341 /* 60357 */ GIR_EraseRootFromParent_Done,
23342 /* 60358 */ // Label 1423: @60358
23343 /* 60358 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(60456), // Rule ID 1837 //
23344 /* 60363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23345 /* 60366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23346 /* 60369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23347 /* 60372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23348 /* 60375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23349 /* 60379 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23350 /* 60383 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23351 /* 60387 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23352 /* 60391 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23353 /* 60395 */ // MIs[1] Operand 1
23354 /* 60395 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23355 /* 60400 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23356 /* 60405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23357 /* 60410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23358 /* 60414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23359 /* 60418 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23360 /* 60420 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
23361 /* 60420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23362 /* 60423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23363 /* 60427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23364 /* 60432 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23365 /* 60436 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23366 /* 60440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23367 /* 60442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23368 /* 60445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23369 /* 60447 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23370 /* 60449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23371 /* 60452 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23372 /* 60454 */ GIR_RootConstrainSelectedInstOperands,
23373 /* 60455 */ // GIR_Coverage, 1837,
23374 /* 60455 */ GIR_EraseRootFromParent_Done,
23375 /* 60456 */ // Label 1424: @60456
23376 /* 60456 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(60554), // Rule ID 1840 //
23377 /* 60461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23378 /* 60464 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23379 /* 60467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23380 /* 60470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23381 /* 60473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23382 /* 60477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23383 /* 60481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23384 /* 60485 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23385 /* 60489 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23386 /* 60493 */ // MIs[1] Operand 1
23387 /* 60493 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23388 /* 60498 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23389 /* 60503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23390 /* 60508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23391 /* 60512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23392 /* 60516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23393 /* 60518 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23394 /* 60518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23395 /* 60521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
23396 /* 60525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23397 /* 60530 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23398 /* 60534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23399 /* 60538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23400 /* 60540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23401 /* 60543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23402 /* 60545 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23403 /* 60547 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23404 /* 60550 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23405 /* 60552 */ GIR_RootConstrainSelectedInstOperands,
23406 /* 60553 */ // GIR_Coverage, 1840,
23407 /* 60553 */ GIR_EraseRootFromParent_Done,
23408 /* 60554 */ // Label 1425: @60554
23409 /* 60554 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(60652), // Rule ID 1841 //
23410 /* 60559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23411 /* 60562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23412 /* 60565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23413 /* 60568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23414 /* 60571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23415 /* 60575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23416 /* 60579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23417 /* 60583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23418 /* 60587 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23419 /* 60591 */ // MIs[1] Operand 1
23420 /* 60591 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23421 /* 60596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23422 /* 60601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23423 /* 60606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23424 /* 60610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23425 /* 60614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23426 /* 60616 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23427 /* 60616 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23428 /* 60619 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
23429 /* 60623 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23430 /* 60628 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23431 /* 60632 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23432 /* 60636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23433 /* 60638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23434 /* 60641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23435 /* 60643 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23436 /* 60645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23437 /* 60648 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23438 /* 60650 */ GIR_RootConstrainSelectedInstOperands,
23439 /* 60651 */ // GIR_Coverage, 1841,
23440 /* 60651 */ GIR_EraseRootFromParent_Done,
23441 /* 60652 */ // Label 1426: @60652
23442 /* 60652 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(60750), // Rule ID 1844 //
23443 /* 60657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23444 /* 60660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23445 /* 60663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23446 /* 60666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23447 /* 60669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23448 /* 60673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23449 /* 60677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23450 /* 60681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23451 /* 60685 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23452 /* 60689 */ // MIs[1] Operand 1
23453 /* 60689 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23454 /* 60694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23455 /* 60699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23456 /* 60704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23457 /* 60708 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23458 /* 60712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23459 /* 60714 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23460 /* 60714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23461 /* 60717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
23462 /* 60721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23463 /* 60726 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23464 /* 60730 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23465 /* 60734 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23466 /* 60736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23467 /* 60739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23468 /* 60741 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23469 /* 60743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23470 /* 60746 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23471 /* 60748 */ GIR_RootConstrainSelectedInstOperands,
23472 /* 60749 */ // GIR_Coverage, 1844,
23473 /* 60749 */ GIR_EraseRootFromParent_Done,
23474 /* 60750 */ // Label 1427: @60750
23475 /* 60750 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(60848), // Rule ID 1845 //
23476 /* 60755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23477 /* 60758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23478 /* 60761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23479 /* 60764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23480 /* 60767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23481 /* 60771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23482 /* 60775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23483 /* 60779 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23484 /* 60783 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23485 /* 60787 */ // MIs[1] Operand 1
23486 /* 60787 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23487 /* 60792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23488 /* 60797 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23489 /* 60802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23490 /* 60806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23491 /* 60810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23492 /* 60812 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23493 /* 60812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23494 /* 60815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
23495 /* 60819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23496 /* 60824 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23497 /* 60828 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23498 /* 60832 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23499 /* 60834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23500 /* 60837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23501 /* 60839 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23502 /* 60841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23503 /* 60844 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23504 /* 60846 */ GIR_RootConstrainSelectedInstOperands,
23505 /* 60847 */ // GIR_Coverage, 1845,
23506 /* 60847 */ GIR_EraseRootFromParent_Done,
23507 /* 60848 */ // Label 1428: @60848
23508 /* 60848 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(60946), // Rule ID 1848 //
23509 /* 60853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23510 /* 60856 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23511 /* 60859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23512 /* 60862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23513 /* 60865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23514 /* 60869 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23515 /* 60873 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23516 /* 60877 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23517 /* 60881 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23518 /* 60885 */ // MIs[1] Operand 1
23519 /* 60885 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23520 /* 60890 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23521 /* 60895 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23522 /* 60900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23523 /* 60904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23524 /* 60908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23525 /* 60910 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23526 /* 60910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23527 /* 60913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23528 /* 60917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23529 /* 60922 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23530 /* 60926 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23531 /* 60930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23532 /* 60932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23533 /* 60935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23534 /* 60937 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23535 /* 60939 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23536 /* 60942 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23537 /* 60944 */ GIR_RootConstrainSelectedInstOperands,
23538 /* 60945 */ // GIR_Coverage, 1848,
23539 /* 60945 */ GIR_EraseRootFromParent_Done,
23540 /* 60946 */ // Label 1429: @60946
23541 /* 60946 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(61044), // Rule ID 1850 //
23542 /* 60951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23543 /* 60954 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23544 /* 60957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23545 /* 60960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23546 /* 60963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23547 /* 60967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23548 /* 60971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23549 /* 60975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23550 /* 60979 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23551 /* 60983 */ // MIs[1] Operand 1
23552 /* 60983 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23553 /* 60988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23554 /* 60993 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23555 /* 60998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23556 /* 61002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23557 /* 61006 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23558 /* 61008 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23559 /* 61008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23560 /* 61011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23561 /* 61015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23562 /* 61020 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23563 /* 61024 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23564 /* 61028 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23565 /* 61030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
23566 /* 61033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23567 /* 61035 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23568 /* 61037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23569 /* 61040 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23570 /* 61042 */ GIR_RootConstrainSelectedInstOperands,
23571 /* 61043 */ // GIR_Coverage, 1850,
23572 /* 61043 */ GIR_EraseRootFromParent_Done,
23573 /* 61044 */ // Label 1430: @61044
23574 /* 61044 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(61142), // Rule ID 1852 //
23575 /* 61049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23576 /* 61052 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23577 /* 61055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23578 /* 61058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23579 /* 61061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23580 /* 61065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23581 /* 61069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23582 /* 61073 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23583 /* 61077 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23584 /* 61081 */ // MIs[1] Operand 1
23585 /* 61081 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23586 /* 61086 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23587 /* 61091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23588 /* 61096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23589 /* 61100 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23590 /* 61104 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23591 /* 61106 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23592 /* 61106 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23593 /* 61109 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23594 /* 61113 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23595 /* 61118 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23596 /* 61122 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23597 /* 61126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23598 /* 61128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23599 /* 61131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23600 /* 61133 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23601 /* 61135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23602 /* 61138 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23603 /* 61140 */ GIR_RootConstrainSelectedInstOperands,
23604 /* 61141 */ // GIR_Coverage, 1852,
23605 /* 61141 */ GIR_EraseRootFromParent_Done,
23606 /* 61142 */ // Label 1431: @61142
23607 /* 61142 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(61240), // Rule ID 1855 //
23608 /* 61147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23609 /* 61150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23610 /* 61153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23611 /* 61156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23612 /* 61159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23613 /* 61163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23614 /* 61167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23615 /* 61171 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23616 /* 61175 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23617 /* 61179 */ // MIs[1] Operand 1
23618 /* 61179 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23619 /* 61184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23620 /* 61189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23621 /* 61194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23622 /* 61198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23623 /* 61202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23624 /* 61204 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23625 /* 61204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23626 /* 61207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23627 /* 61211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23628 /* 61216 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23629 /* 61220 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23630 /* 61224 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23631 /* 61226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
23632 /* 61229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23633 /* 61231 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23634 /* 61233 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23635 /* 61236 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23636 /* 61238 */ GIR_RootConstrainSelectedInstOperands,
23637 /* 61239 */ // GIR_Coverage, 1855,
23638 /* 61239 */ GIR_EraseRootFromParent_Done,
23639 /* 61240 */ // Label 1432: @61240
23640 /* 61240 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(61338), // Rule ID 2421 //
23641 /* 61245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23642 /* 61248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23643 /* 61251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23644 /* 61254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23645 /* 61257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23646 /* 61261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23647 /* 61265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23648 /* 61269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23649 /* 61273 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23650 /* 61277 */ // MIs[1] Operand 1
23651 /* 61277 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23652 /* 61282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23653 /* 61287 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23654 /* 61292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23655 /* 61296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23656 /* 61300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23657 /* 61302 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23658 /* 61302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23659 /* 61305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23660 /* 61309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23661 /* 61314 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23662 /* 61318 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23663 /* 61322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23664 /* 61324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23665 /* 61327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23666 /* 61329 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23667 /* 61331 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23668 /* 61334 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23669 /* 61336 */ GIR_RootConstrainSelectedInstOperands,
23670 /* 61337 */ // GIR_Coverage, 2421,
23671 /* 61337 */ GIR_EraseRootFromParent_Done,
23672 /* 61338 */ // Label 1433: @61338
23673 /* 61338 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(61436), // Rule ID 2422 //
23674 /* 61343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23675 /* 61346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23676 /* 61349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23677 /* 61352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23678 /* 61355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23679 /* 61359 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23680 /* 61363 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23681 /* 61367 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23682 /* 61371 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23683 /* 61375 */ // MIs[1] Operand 1
23684 /* 61375 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23685 /* 61380 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23686 /* 61385 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23687 /* 61390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23688 /* 61394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23689 /* 61398 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23690 /* 61400 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23691 /* 61400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23692 /* 61403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23693 /* 61407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23694 /* 61412 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23695 /* 61416 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23696 /* 61420 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23697 /* 61422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23698 /* 61425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23699 /* 61427 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23700 /* 61429 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23701 /* 61432 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23702 /* 61434 */ GIR_RootConstrainSelectedInstOperands,
23703 /* 61435 */ // GIR_Coverage, 2422,
23704 /* 61435 */ GIR_EraseRootFromParent_Done,
23705 /* 61436 */ // Label 1434: @61436
23706 /* 61436 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(61534), // Rule ID 2425 //
23707 /* 61441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23708 /* 61444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23709 /* 61447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23710 /* 61450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23711 /* 61453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23712 /* 61457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23713 /* 61461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23714 /* 61465 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23715 /* 61469 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23716 /* 61473 */ // MIs[1] Operand 1
23717 /* 61473 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23718 /* 61478 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23719 /* 61483 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23720 /* 61488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23721 /* 61492 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23722 /* 61496 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23723 /* 61498 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23724 /* 61498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23725 /* 61501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23726 /* 61505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23727 /* 61510 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23728 /* 61514 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23729 /* 61518 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23730 /* 61520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23731 /* 61523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23732 /* 61525 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23733 /* 61527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23734 /* 61530 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23735 /* 61532 */ GIR_RootConstrainSelectedInstOperands,
23736 /* 61533 */ // GIR_Coverage, 2425,
23737 /* 61533 */ GIR_EraseRootFromParent_Done,
23738 /* 61534 */ // Label 1435: @61534
23739 /* 61534 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(61632), // Rule ID 2426 //
23740 /* 61539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23741 /* 61542 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23742 /* 61545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23743 /* 61548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23744 /* 61551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23745 /* 61555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23746 /* 61559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23747 /* 61563 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23748 /* 61567 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23749 /* 61571 */ // MIs[1] Operand 1
23750 /* 61571 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23751 /* 61576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23752 /* 61581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23753 /* 61586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23754 /* 61590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23755 /* 61594 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23756 /* 61596 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23757 /* 61596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23758 /* 61599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23759 /* 61603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23760 /* 61608 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23761 /* 61612 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23762 /* 61616 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23763 /* 61618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23764 /* 61621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23765 /* 61623 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23766 /* 61625 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23767 /* 61628 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23768 /* 61630 */ GIR_RootConstrainSelectedInstOperands,
23769 /* 61631 */ // GIR_Coverage, 2426,
23770 /* 61631 */ GIR_EraseRootFromParent_Done,
23771 /* 61632 */ // Label 1436: @61632
23772 /* 61632 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(61730), // Rule ID 2429 //
23773 /* 61637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23774 /* 61640 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23775 /* 61643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23776 /* 61646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23777 /* 61649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23778 /* 61653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23779 /* 61657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23780 /* 61661 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23781 /* 61665 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23782 /* 61669 */ // MIs[1] Operand 1
23783 /* 61669 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23784 /* 61674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23785 /* 61679 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23786 /* 61684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23787 /* 61688 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23788 /* 61692 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23789 /* 61694 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23790 /* 61694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23791 /* 61697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23792 /* 61701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23793 /* 61706 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23794 /* 61710 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23795 /* 61714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23796 /* 61716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23797 /* 61719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23798 /* 61721 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23799 /* 61723 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23800 /* 61726 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23801 /* 61728 */ GIR_RootConstrainSelectedInstOperands,
23802 /* 61729 */ // GIR_Coverage, 2429,
23803 /* 61729 */ GIR_EraseRootFromParent_Done,
23804 /* 61730 */ // Label 1437: @61730
23805 /* 61730 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(61828), // Rule ID 2431 //
23806 /* 61735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
23807 /* 61738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23808 /* 61741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23809 /* 61744 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23810 /* 61747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23811 /* 61751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23812 /* 61755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23813 /* 61759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23814 /* 61763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23815 /* 61767 */ // MIs[1] Operand 1
23816 /* 61767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23817 /* 61772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23818 /* 61777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23819 /* 61782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23820 /* 61786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23821 /* 61790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23822 /* 61792 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23823 /* 61792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23824 /* 61795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23825 /* 61799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23826 /* 61804 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23827 /* 61808 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23828 /* 61812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23829 /* 61814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
23830 /* 61817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23831 /* 61819 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23832 /* 61821 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23833 /* 61824 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23834 /* 61826 */ GIR_RootConstrainSelectedInstOperands,
23835 /* 61827 */ // GIR_Coverage, 2431,
23836 /* 61827 */ GIR_EraseRootFromParent_Done,
23837 /* 61828 */ // Label 1438: @61828
23838 /* 61828 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(61868), // Rule ID 320 //
23839 /* 61833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
23840 /* 61836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23841 /* 61839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23842 /* 61842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23843 /* 61845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23844 /* 61849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23845 /* 61853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23846 /* 61857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23847 /* 61861 */ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
23848 /* 61861 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
23849 /* 61866 */ GIR_RootConstrainSelectedInstOperands,
23850 /* 61867 */ // GIR_Coverage, 320,
23851 /* 61867 */ GIR_Done,
23852 /* 61868 */ // Label 1439: @61868
23853 /* 61868 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(61908), // Rule ID 322 //
23854 /* 61873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32),
23855 /* 61876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23856 /* 61879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23857 /* 61882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23858 /* 61885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23859 /* 61889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23860 /* 61893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23861 /* 61897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23862 /* 61901 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
23863 /* 61901 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
23864 /* 61906 */ GIR_RootConstrainSelectedInstOperands,
23865 /* 61907 */ // GIR_Coverage, 322,
23866 /* 61907 */ GIR_Done,
23867 /* 61908 */ // Label 1440: @61908
23868 /* 61908 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(61948), // Rule ID 323 //
23869 /* 61913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32),
23870 /* 61916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23871 /* 61919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23872 /* 61922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23873 /* 61925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23874 /* 61929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23875 /* 61933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23876 /* 61937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23877 /* 61941 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
23878 /* 61941 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
23879 /* 61946 */ GIR_RootConstrainSelectedInstOperands,
23880 /* 61947 */ // GIR_Coverage, 323,
23881 /* 61947 */ GIR_Done,
23882 /* 61948 */ // Label 1441: @61948
23883 /* 61948 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(61994), // Rule ID 357 //
23884 /* 61953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23885 /* 61956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23886 /* 61959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23887 /* 61962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23888 /* 61965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23889 /* 61969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
23890 /* 61973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23891 /* 61977 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23892 /* 61981 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23893 /* 61981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D),
23894 /* 61984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23895 /* 61986 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
23896 /* 61988 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
23897 /* 61990 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23898 /* 61992 */ GIR_RootConstrainSelectedInstOperands,
23899 /* 61993 */ // GIR_Coverage, 357,
23900 /* 61993 */ GIR_EraseRootFromParent_Done,
23901 /* 61994 */ // Label 1442: @61994
23902 /* 61994 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(62040), // Rule ID 1237 //
23903 /* 61999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
23904 /* 62002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23905 /* 62005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23906 /* 62008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23907 /* 62011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23908 /* 62015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
23909 /* 62019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23910 /* 62023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23911 /* 62027 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D_MMR6:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23912 /* 62027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D_MMR6),
23913 /* 62030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23914 /* 62032 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
23915 /* 62034 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
23916 /* 62036 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23917 /* 62038 */ GIR_RootConstrainSelectedInstOperands,
23918 /* 62039 */ // GIR_Coverage, 1237,
23919 /* 62039 */ GIR_EraseRootFromParent_Done,
23920 /* 62040 */ // Label 1443: @62040
23921 /* 62040 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(62086), // Rule ID 1785 //
23922 /* 62045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23923 /* 62048 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23924 /* 62051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23925 /* 62054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23926 /* 62057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23927 /* 62061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23928 /* 62065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23929 /* 62069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23930 /* 62073 */ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
23931 /* 62073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
23932 /* 62076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23933 /* 62078 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23934 /* 62080 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23935 /* 62082 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23936 /* 62084 */ GIR_RootConstrainSelectedInstOperands,
23937 /* 62085 */ // GIR_Coverage, 1785,
23938 /* 62085 */ GIR_EraseRootFromParent_Done,
23939 /* 62086 */ // Label 1444: @62086
23940 /* 62086 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(62132), // Rule ID 1791 //
23941 /* 62091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23942 /* 62094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23943 /* 62097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23944 /* 62100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23945 /* 62103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23946 /* 62107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23947 /* 62111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23948 /* 62115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23949 /* 62119 */ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
23950 /* 62119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
23951 /* 62122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23952 /* 62124 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23953 /* 62126 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23954 /* 62128 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23955 /* 62130 */ GIR_RootConstrainSelectedInstOperands,
23956 /* 62131 */ // GIR_Coverage, 1791,
23957 /* 62131 */ GIR_EraseRootFromParent_Done,
23958 /* 62132 */ // Label 1445: @62132
23959 /* 62132 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(62178), // Rule ID 1830 //
23960 /* 62137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23961 /* 62140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23962 /* 62143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23963 /* 62146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23964 /* 62149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23965 /* 62153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23966 /* 62157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23967 /* 62161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23968 /* 62165 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
23969 /* 62165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
23970 /* 62168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23971 /* 62170 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23972 /* 62172 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23973 /* 62174 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23974 /* 62176 */ GIR_RootConstrainSelectedInstOperands,
23975 /* 62177 */ // GIR_Coverage, 1830,
23976 /* 62177 */ GIR_EraseRootFromParent_Done,
23977 /* 62178 */ // Label 1446: @62178
23978 /* 62178 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(62224), // Rule ID 1853 //
23979 /* 62183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23980 /* 62186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23981 /* 62189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23982 /* 62192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23983 /* 62195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23984 /* 62199 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23985 /* 62203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23986 /* 62207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23987 /* 62211 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
23988 /* 62211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23989 /* 62214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23990 /* 62216 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23991 /* 62218 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23992 /* 62220 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23993 /* 62222 */ GIR_RootConstrainSelectedInstOperands,
23994 /* 62223 */ // GIR_Coverage, 1853,
23995 /* 62223 */ GIR_EraseRootFromParent_Done,
23996 /* 62224 */ // Label 1447: @62224
23997 /* 62224 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(62270), // Rule ID 1856 //
23998 /* 62229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23999 /* 62232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24000 /* 62235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24001 /* 62238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24002 /* 62241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24003 /* 62245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24004 /* 62249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24005 /* 62253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24006 /* 62257 */ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
24007 /* 62257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
24008 /* 62260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24009 /* 62262 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
24010 /* 62264 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
24011 /* 62266 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
24012 /* 62268 */ GIR_RootConstrainSelectedInstOperands,
24013 /* 62269 */ // GIR_Coverage, 1856,
24014 /* 62269 */ GIR_EraseRootFromParent_Done,
24015 /* 62270 */ // Label 1448: @62270
24016 /* 62270 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(62316), // Rule ID 2432 //
24017 /* 62275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6),
24018 /* 62278 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24019 /* 62281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24020 /* 62284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24021 /* 62287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24022 /* 62291 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24023 /* 62295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24024 /* 62299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24025 /* 62303 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
24026 /* 62303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
24027 /* 62306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24028 /* 62308 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
24029 /* 62310 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
24030 /* 62312 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
24031 /* 62314 */ GIR_RootConstrainSelectedInstOperands,
24032 /* 62315 */ // GIR_Coverage, 2432,
24033 /* 62315 */ GIR_EraseRootFromParent_Done,
24034 /* 62316 */ // Label 1449: @62316
24035 /* 62316 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(62394), // Rule ID 1909 //
24036 /* 62321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
24037 /* 62324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24038 /* 62327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24039 /* 62330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24040 /* 62333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24041 /* 62337 */ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
24042 /* 62337 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
24043 /* 62340 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
24044 /* 62344 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24045 /* 62349 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
24046 /* 62353 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
24047 /* 62357 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24048 /* 62359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24049 /* 62362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
24050 /* 62366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24051 /* 62371 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
24052 /* 62375 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
24053 /* 62379 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24054 /* 62381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
24055 /* 62384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24056 /* 62386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24057 /* 62389 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24058 /* 62392 */ GIR_RootConstrainSelectedInstOperands,
24059 /* 62393 */ // GIR_Coverage, 1909,
24060 /* 62393 */ GIR_EraseRootFromParent_Done,
24061 /* 62394 */ // Label 1450: @62394
24062 /* 62394 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(62506), // Rule ID 1920 //
24063 /* 62399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
24064 /* 62402 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24065 /* 62405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24066 /* 62408 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24067 /* 62411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24068 /* 62415 */ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
24069 /* 62415 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
24070 /* 62418 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
24071 /* 62422 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24072 /* 62427 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
24073 /* 62431 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
24074 /* 62433 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
24075 /* 62436 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
24076 /* 62440 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24077 /* 62445 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
24078 /* 62449 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
24079 /* 62452 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
24080 /* 62454 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
24081 /* 62457 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
24082 /* 62461 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24083 /* 62466 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
24084 /* 62470 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24085 /* 62472 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24086 /* 62475 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
24087 /* 62479 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24088 /* 62484 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
24089 /* 62488 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24090 /* 62491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24091 /* 62493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
24092 /* 62496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24093 /* 62498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24094 /* 62501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
24095 /* 62504 */ GIR_RootConstrainSelectedInstOperands,
24096 /* 62505 */ // GIR_Coverage, 1920,
24097 /* 62505 */ GIR_EraseRootFromParent_Done,
24098 /* 62506 */ // Label 1451: @62506
24099 /* 62506 */ GIM_Reject,
24100 /* 62507 */ // Label 1306: @62507
24101 /* 62507 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(62601),
24102 /* 62512 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24103 /* 62515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24104 /* 62518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24105 /* 62521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24106 /* 62525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24107 /* 62529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24108 /* 62533 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24109 /* 62537 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(62558), // Rule ID 592 //
24110 /* 62542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24111 /* 62545 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24112 /* 62545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
24113 /* 62548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24114 /* 62550 */ GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
24115 /* 62552 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
24116 /* 62554 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
24117 /* 62556 */ GIR_RootConstrainSelectedInstOperands,
24118 /* 62557 */ // GIR_Coverage, 592,
24119 /* 62557 */ GIR_EraseRootFromParent_Done,
24120 /* 62558 */ // Label 1453: @62558
24121 /* 62558 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(62579), // Rule ID 594 //
24122 /* 62563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24123 /* 62566 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24124 /* 62566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
24125 /* 62569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24126 /* 62571 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
24127 /* 62573 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24128 /* 62575 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
24129 /* 62577 */ GIR_RootConstrainSelectedInstOperands,
24130 /* 62578 */ // GIR_Coverage, 594,
24131 /* 62578 */ GIR_EraseRootFromParent_Done,
24132 /* 62579 */ // Label 1454: @62579
24133 /* 62579 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(62600), // Rule ID 604 //
24134 /* 62584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24135 /* 62587 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24136 /* 62587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
24137 /* 62590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24138 /* 62592 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24139 /* 62594 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24140 /* 62596 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24141 /* 62598 */ GIR_RootConstrainSelectedInstOperands,
24142 /* 62599 */ // GIR_Coverage, 604,
24143 /* 62599 */ GIR_EraseRootFromParent_Done,
24144 /* 62600 */ // Label 1455: @62600
24145 /* 62600 */ GIM_Reject,
24146 /* 62601 */ // Label 1452: @62601
24147 /* 62601 */ GIM_Reject,
24148 /* 62602 */ // Label 1307: @62602
24149 /* 62602 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(62648), // Rule ID 605 //
24150 /* 62607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24151 /* 62610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24152 /* 62613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24153 /* 62616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24154 /* 62619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24155 /* 62623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24156 /* 62627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24157 /* 62631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24158 /* 62635 */ // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24159 /* 62635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
24160 /* 62638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24161 /* 62640 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24162 /* 62642 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24163 /* 62644 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24164 /* 62646 */ GIR_RootConstrainSelectedInstOperands,
24165 /* 62647 */ // GIR_Coverage, 605,
24166 /* 62647 */ GIR_EraseRootFromParent_Done,
24167 /* 62648 */ // Label 1456: @62648
24168 /* 62648 */ GIM_Reject,
24169 /* 62649 */ // Label 1308: @62649
24170 /* 62649 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(62722),
24171 /* 62654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24172 /* 62657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24173 /* 62660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24174 /* 62663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24175 /* 62667 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24176 /* 62671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24177 /* 62675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24178 /* 62679 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(62700), // Rule ID 606 //
24179 /* 62684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24180 /* 62687 */ // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24181 /* 62687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
24182 /* 62690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24183 /* 62692 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24184 /* 62694 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24185 /* 62696 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24186 /* 62698 */ GIR_RootConstrainSelectedInstOperands,
24187 /* 62699 */ // GIR_Coverage, 606,
24188 /* 62699 */ GIR_EraseRootFromParent_Done,
24189 /* 62700 */ // Label 1458: @62700
24190 /* 62700 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(62721), // Rule ID 608 //
24191 /* 62705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24192 /* 62708 */ // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24193 /* 62708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
24194 /* 62711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24195 /* 62713 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24196 /* 62715 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24197 /* 62717 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24198 /* 62719 */ GIR_RootConstrainSelectedInstOperands,
24199 /* 62720 */ // GIR_Coverage, 608,
24200 /* 62720 */ GIR_EraseRootFromParent_Done,
24201 /* 62721 */ // Label 1459: @62721
24202 /* 62721 */ GIM_Reject,
24203 /* 62722 */ // Label 1457: @62722
24204 /* 62722 */ GIM_Reject,
24205 /* 62723 */ // Label 1309: @62723
24206 /* 62723 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(62796),
24207 /* 62728 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24208 /* 62731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24209 /* 62734 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24210 /* 62737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24211 /* 62741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24212 /* 62745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24213 /* 62749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24214 /* 62753 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(62774), // Rule ID 607 //
24215 /* 62758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24216 /* 62761 */ // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24217 /* 62761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
24218 /* 62764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24219 /* 62766 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24220 /* 62768 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24221 /* 62770 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24222 /* 62772 */ GIR_RootConstrainSelectedInstOperands,
24223 /* 62773 */ // GIR_Coverage, 607,
24224 /* 62773 */ GIR_EraseRootFromParent_Done,
24225 /* 62774 */ // Label 1461: @62774
24226 /* 62774 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(62795), // Rule ID 609 //
24227 /* 62779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24228 /* 62782 */ // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24229 /* 62782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
24230 /* 62785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24231 /* 62787 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24232 /* 62789 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24233 /* 62791 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24234 /* 62793 */ GIR_RootConstrainSelectedInstOperands,
24235 /* 62794 */ // GIR_Coverage, 609,
24236 /* 62794 */ GIR_EraseRootFromParent_Done,
24237 /* 62795 */ // Label 1462: @62795
24238 /* 62795 */ GIM_Reject,
24239 /* 62796 */ // Label 1460: @62796
24240 /* 62796 */ GIM_Reject,
24241 /* 62797 */ // Label 1310: @62797
24242 /* 62797 */ GIM_Reject,
24243 /* 62798 */ // Label 44: @62798
24244 /* 62798 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1465*/ GIMT_Encode4(62906),
24245 /* 62809 */ /*GILLT_s32*//*Label 1463*/ GIMT_Encode4(62817),
24246 /* 62813 */ /*GILLT_s64*//*Label 1464*/ GIMT_Encode4(62872),
24247 /* 62817 */ // Label 1463: @62817
24248 /* 62817 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(62871),
24249 /* 62822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24250 /* 62825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24251 /* 62828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24252 /* 62832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24253 /* 62836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24254 /* 62840 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(62855), // Rule ID 355 //
24255 /* 62845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24256 /* 62848 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24257 /* 62848 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
24258 /* 62853 */ GIR_RootConstrainSelectedInstOperands,
24259 /* 62854 */ // GIR_Coverage, 355,
24260 /* 62854 */ GIR_Done,
24261 /* 62855 */ // Label 1467: @62855
24262 /* 62855 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(62870), // Rule ID 1204 //
24263 /* 62860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
24264 /* 62863 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24265 /* 62863 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
24266 /* 62868 */ GIR_RootConstrainSelectedInstOperands,
24267 /* 62869 */ // GIR_Coverage, 1204,
24268 /* 62869 */ GIR_Done,
24269 /* 62870 */ // Label 1468: @62870
24270 /* 62870 */ GIM_Reject,
24271 /* 62871 */ // Label 1466: @62871
24272 /* 62871 */ GIM_Reject,
24273 /* 62872 */ // Label 1464: @62872
24274 /* 62872 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(62905), // Rule ID 370 //
24275 /* 62877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
24276 /* 62880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24277 /* 62883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24278 /* 62886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24279 /* 62890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24280 /* 62894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24281 /* 62898 */ // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
24282 /* 62898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
24283 /* 62903 */ GIR_RootConstrainSelectedInstOperands,
24284 /* 62904 */ // GIR_Coverage, 370,
24285 /* 62904 */ GIR_Done,
24286 /* 62905 */ // Label 1469: @62905
24287 /* 62905 */ GIM_Reject,
24288 /* 62906 */ // Label 1465: @62906
24289 /* 62906 */ GIM_Reject,
24290 /* 62907 */ // Label 45: @62907
24291 /* 62907 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1472*/ GIMT_Encode4(63015),
24292 /* 62918 */ /*GILLT_s32*//*Label 1470*/ GIMT_Encode4(62926),
24293 /* 62922 */ /*GILLT_s64*//*Label 1471*/ GIMT_Encode4(62981),
24294 /* 62926 */ // Label 1470: @62926
24295 /* 62926 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(62980),
24296 /* 62931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24297 /* 62934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24298 /* 62937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24299 /* 62941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24300 /* 62945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24301 /* 62949 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(62964), // Rule ID 354 //
24302 /* 62954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24303 /* 62957 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24304 /* 62957 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
24305 /* 62962 */ GIR_RootConstrainSelectedInstOperands,
24306 /* 62963 */ // GIR_Coverage, 354,
24307 /* 62963 */ GIR_Done,
24308 /* 62964 */ // Label 1474: @62964
24309 /* 62964 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(62979), // Rule ID 1203 //
24310 /* 62969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
24311 /* 62972 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24312 /* 62972 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
24313 /* 62977 */ GIR_RootConstrainSelectedInstOperands,
24314 /* 62978 */ // GIR_Coverage, 1203,
24315 /* 62978 */ GIR_Done,
24316 /* 62979 */ // Label 1475: @62979
24317 /* 62979 */ GIM_Reject,
24318 /* 62980 */ // Label 1473: @62980
24319 /* 62980 */ GIM_Reject,
24320 /* 62981 */ // Label 1471: @62981
24321 /* 62981 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(63014), // Rule ID 369 //
24322 /* 62986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
24323 /* 62989 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24324 /* 62992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24325 /* 62995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24326 /* 62999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24327 /* 63003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24328 /* 63007 */ // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
24329 /* 63007 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
24330 /* 63012 */ GIR_RootConstrainSelectedInstOperands,
24331 /* 63013 */ // GIR_Coverage, 369,
24332 /* 63013 */ GIR_Done,
24333 /* 63014 */ // Label 1476: @63014
24334 /* 63014 */ GIM_Reject,
24335 /* 63015 */ // Label 1472: @63015
24336 /* 63015 */ GIM_Reject,
24337 /* 63016 */ // Label 46: @63016
24338 /* 63016 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1481*/ GIMT_Encode4(64318),
24339 /* 63027 */ /*GILLT_s32*//*Label 1477*/ GIMT_Encode4(63059),
24340 /* 63031 */ /*GILLT_s64*//*Label 1478*/ GIMT_Encode4(63385), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
24341 /* 63051 */ /*GILLT_v4s32*//*Label 1479*/ GIMT_Encode4(64010),
24342 /* 63055 */ /*GILLT_v2s64*//*Label 1480*/ GIMT_Encode4(64164),
24343 /* 63059 */ // Label 1477: @63059
24344 /* 63059 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(63384),
24345 /* 63064 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24346 /* 63067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24347 /* 63070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24348 /* 63074 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(63131), // Rule ID 178 //
24349 /* 63079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24350 /* 63082 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24351 /* 63086 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24352 /* 63090 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24353 /* 63094 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24354 /* 63098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24355 /* 63103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24356 /* 63108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24357 /* 63112 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24358 /* 63114 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24359 /* 63114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24360 /* 63117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24361 /* 63119 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24362 /* 63121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24363 /* 63125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24364 /* 63129 */ GIR_RootConstrainSelectedInstOperands,
24365 /* 63130 */ // GIR_Coverage, 178,
24366 /* 63130 */ GIR_EraseRootFromParent_Done,
24367 /* 63131 */ // Label 1483: @63131
24368 /* 63131 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(63188), // Rule ID 177 //
24369 /* 63136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24370 /* 63139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24371 /* 63143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24372 /* 63147 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24373 /* 63151 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24374 /* 63155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24375 /* 63160 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24376 /* 63165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24377 /* 63169 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24378 /* 63171 */ // (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24379 /* 63171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24380 /* 63174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24381 /* 63176 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24382 /* 63178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24383 /* 63182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24384 /* 63186 */ GIR_RootConstrainSelectedInstOperands,
24385 /* 63187 */ // GIR_Coverage, 177,
24386 /* 63187 */ GIR_EraseRootFromParent_Done,
24387 /* 63188 */ // Label 1484: @63188
24388 /* 63188 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(63245), // Rule ID 2491 //
24389 /* 63193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24390 /* 63196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24391 /* 63200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24392 /* 63204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24393 /* 63208 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24394 /* 63212 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24395 /* 63216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24396 /* 63221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24397 /* 63226 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24398 /* 63228 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24399 /* 63228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24400 /* 63231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24401 /* 63233 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24402 /* 63235 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24403 /* 63239 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24404 /* 63243 */ GIR_RootConstrainSelectedInstOperands,
24405 /* 63244 */ // GIR_Coverage, 2491,
24406 /* 63244 */ GIR_EraseRootFromParent_Done,
24407 /* 63245 */ // Label 1485: @63245
24408 /* 63245 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(63302), // Rule ID 2490 //
24409 /* 63250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24410 /* 63253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24411 /* 63257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24412 /* 63261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24413 /* 63265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24414 /* 63269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24415 /* 63273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24416 /* 63278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24417 /* 63283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24418 /* 63285 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24419 /* 63285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24420 /* 63288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24421 /* 63290 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24422 /* 63292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24423 /* 63296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24424 /* 63300 */ GIR_RootConstrainSelectedInstOperands,
24425 /* 63301 */ // GIR_Coverage, 2490,
24426 /* 63301 */ GIR_EraseRootFromParent_Done,
24427 /* 63302 */ // Label 1486: @63302
24428 /* 63302 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(63329), // Rule ID 152 //
24429 /* 63307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24430 /* 63310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24431 /* 63314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24432 /* 63318 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24433 /* 63318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
24434 /* 63323 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24435 /* 63327 */ GIR_RootConstrainSelectedInstOperands,
24436 /* 63328 */ // GIR_Coverage, 152,
24437 /* 63328 */ GIR_Done,
24438 /* 63329 */ // Label 1487: @63329
24439 /* 63329 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(63356), // Rule ID 1154 //
24440 /* 63334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24441 /* 63337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24442 /* 63341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24443 /* 63345 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24444 /* 63345 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
24445 /* 63350 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24446 /* 63354 */ GIR_RootConstrainSelectedInstOperands,
24447 /* 63355 */ // GIR_Coverage, 1154,
24448 /* 63355 */ GIR_Done,
24449 /* 63356 */ // Label 1488: @63356
24450 /* 63356 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(63383), // Rule ID 1211 //
24451 /* 63361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24452 /* 63364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24453 /* 63368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24454 /* 63372 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24455 /* 63372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
24456 /* 63375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24457 /* 63377 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24458 /* 63379 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24459 /* 63381 */ GIR_RootConstrainSelectedInstOperands,
24460 /* 63382 */ // GIR_Coverage, 1211,
24461 /* 63382 */ GIR_EraseRootFromParent_Done,
24462 /* 63383 */ // Label 1489: @63383
24463 /* 63383 */ GIM_Reject,
24464 /* 63384 */ // Label 1482: @63384
24465 /* 63384 */ GIM_Reject,
24466 /* 63385 */ // Label 1478: @63385
24467 /* 63385 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(64009),
24468 /* 63390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24469 /* 63393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24470 /* 63396 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(63457), // Rule ID 186 //
24471 /* 63401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24472 /* 63404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24473 /* 63408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24474 /* 63412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24475 /* 63416 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24476 /* 63420 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24477 /* 63424 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24478 /* 63429 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24479 /* 63434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24480 /* 63438 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24481 /* 63440 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24482 /* 63440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24483 /* 63443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24484 /* 63445 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24485 /* 63447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24486 /* 63451 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24487 /* 63455 */ GIR_RootConstrainSelectedInstOperands,
24488 /* 63456 */ // GIR_Coverage, 186,
24489 /* 63456 */ GIR_EraseRootFromParent_Done,
24490 /* 63457 */ // Label 1491: @63457
24491 /* 63457 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(63518), // Rule ID 194 //
24492 /* 63462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24493 /* 63465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24494 /* 63469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24495 /* 63473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24496 /* 63477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24497 /* 63481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24498 /* 63485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24499 /* 63490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24500 /* 63495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24501 /* 63499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24502 /* 63501 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24503 /* 63501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24504 /* 63504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24505 /* 63506 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24506 /* 63508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24507 /* 63512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24508 /* 63516 */ GIR_RootConstrainSelectedInstOperands,
24509 /* 63517 */ // GIR_Coverage, 194,
24510 /* 63517 */ GIR_EraseRootFromParent_Done,
24511 /* 63518 */ // Label 1492: @63518
24512 /* 63518 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(63579), // Rule ID 185 //
24513 /* 63523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24514 /* 63526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24515 /* 63530 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24516 /* 63534 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24517 /* 63538 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24518 /* 63542 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24519 /* 63546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24520 /* 63551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24521 /* 63556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24522 /* 63560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24523 /* 63562 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24524 /* 63562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24525 /* 63565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24526 /* 63567 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24527 /* 63569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24528 /* 63573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24529 /* 63577 */ GIR_RootConstrainSelectedInstOperands,
24530 /* 63578 */ // GIR_Coverage, 185,
24531 /* 63578 */ GIR_EraseRootFromParent_Done,
24532 /* 63579 */ // Label 1493: @63579
24533 /* 63579 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(63640), // Rule ID 193 //
24534 /* 63584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24535 /* 63587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24536 /* 63591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24537 /* 63595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24538 /* 63599 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24539 /* 63603 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24540 /* 63607 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24541 /* 63612 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24542 /* 63617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24543 /* 63621 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24544 /* 63623 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24545 /* 63623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24546 /* 63626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24547 /* 63628 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24548 /* 63630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24549 /* 63634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24550 /* 63638 */ GIR_RootConstrainSelectedInstOperands,
24551 /* 63639 */ // GIR_Coverage, 193,
24552 /* 63639 */ GIR_EraseRootFromParent_Done,
24553 /* 63640 */ // Label 1494: @63640
24554 /* 63640 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(63701), // Rule ID 2495 //
24555 /* 63645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24556 /* 63648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24557 /* 63652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24558 /* 63656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24559 /* 63660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24560 /* 63664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24561 /* 63668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24562 /* 63672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24563 /* 63677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24564 /* 63682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24565 /* 63684 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24566 /* 63684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24567 /* 63687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24568 /* 63689 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24569 /* 63691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24570 /* 63695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24571 /* 63699 */ GIR_RootConstrainSelectedInstOperands,
24572 /* 63700 */ // GIR_Coverage, 2495,
24573 /* 63700 */ GIR_EraseRootFromParent_Done,
24574 /* 63701 */ // Label 1495: @63701
24575 /* 63701 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(63762), // Rule ID 2499 //
24576 /* 63706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24577 /* 63709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24578 /* 63713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24579 /* 63717 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24580 /* 63721 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24581 /* 63725 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24582 /* 63729 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24583 /* 63733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24584 /* 63738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24585 /* 63743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24586 /* 63745 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24587 /* 63745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24588 /* 63748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24589 /* 63750 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24590 /* 63752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24591 /* 63756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24592 /* 63760 */ GIR_RootConstrainSelectedInstOperands,
24593 /* 63761 */ // GIR_Coverage, 2499,
24594 /* 63761 */ GIR_EraseRootFromParent_Done,
24595 /* 63762 */ // Label 1496: @63762
24596 /* 63762 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(63823), // Rule ID 2494 //
24597 /* 63767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24598 /* 63770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24599 /* 63774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24600 /* 63778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24601 /* 63782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24602 /* 63786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24603 /* 63790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24604 /* 63794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24605 /* 63799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24606 /* 63804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24607 /* 63806 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24608 /* 63806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24609 /* 63809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24610 /* 63811 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24611 /* 63813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24612 /* 63817 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24613 /* 63821 */ GIR_RootConstrainSelectedInstOperands,
24614 /* 63822 */ // GIR_Coverage, 2494,
24615 /* 63822 */ GIR_EraseRootFromParent_Done,
24616 /* 63823 */ // Label 1497: @63823
24617 /* 63823 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(63884), // Rule ID 2498 //
24618 /* 63828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24619 /* 63831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24620 /* 63835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24621 /* 63839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24622 /* 63843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24623 /* 63847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24624 /* 63851 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24625 /* 63855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24626 /* 63860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24627 /* 63865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24628 /* 63867 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24629 /* 63867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24630 /* 63870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24631 /* 63872 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24632 /* 63874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24633 /* 63878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24634 /* 63882 */ GIR_RootConstrainSelectedInstOperands,
24635 /* 63883 */ // GIR_Coverage, 2498,
24636 /* 63883 */ GIR_EraseRootFromParent_Done,
24637 /* 63884 */ // Label 1498: @63884
24638 /* 63884 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(63915), // Rule ID 154 //
24639 /* 63889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24640 /* 63892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24641 /* 63896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24642 /* 63900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24643 /* 63904 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24644 /* 63904 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
24645 /* 63909 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24646 /* 63913 */ GIR_RootConstrainSelectedInstOperands,
24647 /* 63914 */ // GIR_Coverage, 154,
24648 /* 63914 */ GIR_Done,
24649 /* 63915 */ // Label 1499: @63915
24650 /* 63915 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(63946), // Rule ID 156 //
24651 /* 63920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
24652 /* 63923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24653 /* 63927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24654 /* 63931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24655 /* 63935 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24656 /* 63935 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
24657 /* 63940 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24658 /* 63944 */ GIR_RootConstrainSelectedInstOperands,
24659 /* 63945 */ // GIR_Coverage, 156,
24660 /* 63945 */ GIR_Done,
24661 /* 63946 */ // Label 1500: @63946
24662 /* 63946 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(63977), // Rule ID 1158 //
24663 /* 63951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
24664 /* 63954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24665 /* 63958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24666 /* 63962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24667 /* 63966 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24668 /* 63966 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
24669 /* 63971 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24670 /* 63975 */ GIR_RootConstrainSelectedInstOperands,
24671 /* 63976 */ // GIR_Coverage, 1158,
24672 /* 63976 */ GIR_Done,
24673 /* 63977 */ // Label 1501: @63977
24674 /* 63977 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(64008), // Rule ID 1159 //
24675 /* 63982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
24676 /* 63985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24677 /* 63989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24678 /* 63993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24679 /* 63997 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24680 /* 63997 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
24681 /* 64002 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24682 /* 64006 */ GIR_RootConstrainSelectedInstOperands,
24683 /* 64007 */ // GIR_Coverage, 1159,
24684 /* 64007 */ GIR_Done,
24685 /* 64008 */ // Label 1502: @64008
24686 /* 64008 */ GIM_Reject,
24687 /* 64009 */ // Label 1490: @64009
24688 /* 64009 */ GIM_Reject,
24689 /* 64010 */ // Label 1479: @64010
24690 /* 64010 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(64163),
24691 /* 64015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24692 /* 64018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24693 /* 64021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24694 /* 64025 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(64082), // Rule ID 2633 //
24695 /* 64030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24696 /* 64033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24697 /* 64037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24698 /* 64041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24699 /* 64045 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24700 /* 64049 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24701 /* 64054 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24702 /* 64059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24703 /* 64063 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24704 /* 64065 */ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24705 /* 64065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24706 /* 64068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24707 /* 64070 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24708 /* 64072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24709 /* 64076 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24710 /* 64080 */ GIR_RootConstrainSelectedInstOperands,
24711 /* 64081 */ // GIR_Coverage, 2633,
24712 /* 64081 */ GIR_EraseRootFromParent_Done,
24713 /* 64082 */ // Label 1504: @64082
24714 /* 64082 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(64139), // Rule ID 2119 //
24715 /* 64087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24716 /* 64090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24717 /* 64094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24718 /* 64098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24719 /* 64102 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24720 /* 64106 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24721 /* 64110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24722 /* 64115 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24723 /* 64120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24724 /* 64122 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24725 /* 64122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24726 /* 64125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24727 /* 64127 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24728 /* 64129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24729 /* 64133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24730 /* 64137 */ GIR_RootConstrainSelectedInstOperands,
24731 /* 64138 */ // GIR_Coverage, 2119,
24732 /* 64138 */ GIR_EraseRootFromParent_Done,
24733 /* 64139 */ // Label 1505: @64139
24734 /* 64139 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(64162), // Rule ID 694 //
24735 /* 64144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24736 /* 64147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24737 /* 64151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24738 /* 64155 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24739 /* 64155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
24740 /* 64160 */ GIR_RootConstrainSelectedInstOperands,
24741 /* 64161 */ // GIR_Coverage, 694,
24742 /* 64161 */ GIR_Done,
24743 /* 64162 */ // Label 1506: @64162
24744 /* 64162 */ GIM_Reject,
24745 /* 64163 */ // Label 1503: @64163
24746 /* 64163 */ GIM_Reject,
24747 /* 64164 */ // Label 1480: @64164
24748 /* 64164 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(64317),
24749 /* 64169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24750 /* 64172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24751 /* 64175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24752 /* 64179 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(64236), // Rule ID 2634 //
24753 /* 64184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24754 /* 64187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24755 /* 64191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24756 /* 64195 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24757 /* 64199 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24758 /* 64203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24759 /* 64208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24760 /* 64213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24761 /* 64217 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24762 /* 64219 */ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24763 /* 64219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24764 /* 64222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24765 /* 64224 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24766 /* 64226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24767 /* 64230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24768 /* 64234 */ GIR_RootConstrainSelectedInstOperands,
24769 /* 64235 */ // GIR_Coverage, 2634,
24770 /* 64235 */ GIR_EraseRootFromParent_Done,
24771 /* 64236 */ // Label 1508: @64236
24772 /* 64236 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(64293), // Rule ID 2120 //
24773 /* 64241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24774 /* 64244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24775 /* 64248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24776 /* 64252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24777 /* 64256 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24778 /* 64260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24779 /* 64264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24780 /* 64269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24781 /* 64274 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24782 /* 64276 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24783 /* 64276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24784 /* 64279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24785 /* 64281 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24786 /* 64283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24787 /* 64287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24788 /* 64291 */ GIR_RootConstrainSelectedInstOperands,
24789 /* 64292 */ // GIR_Coverage, 2120,
24790 /* 64292 */ GIR_EraseRootFromParent_Done,
24791 /* 64293 */ // Label 1509: @64293
24792 /* 64293 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(64316), // Rule ID 695 //
24793 /* 64298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24794 /* 64301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24795 /* 64305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24796 /* 64309 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24797 /* 64309 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
24798 /* 64314 */ GIR_RootConstrainSelectedInstOperands,
24799 /* 64315 */ // GIR_Coverage, 695,
24800 /* 64315 */ GIR_Done,
24801 /* 64316 */ // Label 1510: @64316
24802 /* 64316 */ GIM_Reject,
24803 /* 64317 */ // Label 1507: @64317
24804 /* 64317 */ GIM_Reject,
24805 /* 64318 */ // Label 1481: @64318
24806 /* 64318 */ GIM_Reject,
24807 /* 64319 */ // Label 47: @64319
24808 /* 64319 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1515*/ GIMT_Encode4(65141),
24809 /* 64330 */ /*GILLT_s32*//*Label 1511*/ GIMT_Encode4(64362),
24810 /* 64334 */ /*GILLT_s64*//*Label 1512*/ GIMT_Encode4(64574), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
24811 /* 64354 */ /*GILLT_v4s32*//*Label 1513*/ GIMT_Encode4(64955),
24812 /* 64358 */ /*GILLT_v2s64*//*Label 1514*/ GIMT_Encode4(65048),
24813 /* 64362 */ // Label 1511: @64362
24814 /* 64362 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(64573),
24815 /* 64367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24816 /* 64370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24817 /* 64373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24818 /* 64377 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(64434), // Rule ID 182 //
24819 /* 64382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24820 /* 64385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24821 /* 64389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24822 /* 64393 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24823 /* 64397 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24824 /* 64401 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24825 /* 64406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24826 /* 64411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24827 /* 64415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24828 /* 64417 */ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24829 /* 64417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
24830 /* 64420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24831 /* 64422 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24832 /* 64424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24833 /* 64428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24834 /* 64432 */ GIR_RootConstrainSelectedInstOperands,
24835 /* 64433 */ // GIR_Coverage, 182,
24836 /* 64433 */ GIR_EraseRootFromParent_Done,
24837 /* 64434 */ // Label 1517: @64434
24838 /* 64434 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(64491), // Rule ID 181 //
24839 /* 64439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24840 /* 64442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24841 /* 64446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24842 /* 64450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24843 /* 64454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24844 /* 64458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24845 /* 64463 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24846 /* 64468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24847 /* 64472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24848 /* 64474 */ // (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24849 /* 64474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
24850 /* 64477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24851 /* 64479 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24852 /* 64481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24853 /* 64485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24854 /* 64489 */ GIR_RootConstrainSelectedInstOperands,
24855 /* 64490 */ // GIR_Coverage, 181,
24856 /* 64490 */ GIR_EraseRootFromParent_Done,
24857 /* 64491 */ // Label 1518: @64491
24858 /* 64491 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(64518), // Rule ID 170 //
24859 /* 64496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24860 /* 64499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24861 /* 64503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24862 /* 64507 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24863 /* 64507 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
24864 /* 64512 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24865 /* 64516 */ GIR_RootConstrainSelectedInstOperands,
24866 /* 64517 */ // GIR_Coverage, 170,
24867 /* 64517 */ GIR_Done,
24868 /* 64518 */ // Label 1519: @64518
24869 /* 64518 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(64545), // Rule ID 1157 //
24870 /* 64523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24871 /* 64526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24872 /* 64530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24873 /* 64534 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24874 /* 64534 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
24875 /* 64539 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24876 /* 64543 */ GIR_RootConstrainSelectedInstOperands,
24877 /* 64544 */ // GIR_Coverage, 1157,
24878 /* 64544 */ GIR_Done,
24879 /* 64545 */ // Label 1520: @64545
24880 /* 64545 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(64572), // Rule ID 1212 //
24881 /* 64550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24882 /* 64553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24883 /* 64557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24884 /* 64561 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24885 /* 64561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
24886 /* 64564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24887 /* 64566 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24888 /* 64568 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24889 /* 64570 */ GIR_RootConstrainSelectedInstOperands,
24890 /* 64571 */ // GIR_Coverage, 1212,
24891 /* 64571 */ GIR_EraseRootFromParent_Done,
24892 /* 64572 */ // Label 1521: @64572
24893 /* 64572 */ GIM_Reject,
24894 /* 64573 */ // Label 1516: @64573
24895 /* 64573 */ GIM_Reject,
24896 /* 64574 */ // Label 1512: @64574
24897 /* 64574 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(64954),
24898 /* 64579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24899 /* 64582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24900 /* 64585 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(64646), // Rule ID 190 //
24901 /* 64590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24902 /* 64593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24903 /* 64597 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24904 /* 64601 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24905 /* 64605 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24906 /* 64609 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24907 /* 64613 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24908 /* 64618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24909 /* 64623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24910 /* 64627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24911 /* 64629 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24912 /* 64629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
24913 /* 64632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24914 /* 64634 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24915 /* 64636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24916 /* 64640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24917 /* 64644 */ GIR_RootConstrainSelectedInstOperands,
24918 /* 64645 */ // GIR_Coverage, 190,
24919 /* 64645 */ GIR_EraseRootFromParent_Done,
24920 /* 64646 */ // Label 1523: @64646
24921 /* 64646 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(64707), // Rule ID 198 //
24922 /* 64651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24923 /* 64654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24924 /* 64658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24925 /* 64662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24926 /* 64666 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24927 /* 64670 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24928 /* 64674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24929 /* 64679 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24930 /* 64684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24931 /* 64688 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24932 /* 64690 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24933 /* 64690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
24934 /* 64693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24935 /* 64695 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24936 /* 64697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24937 /* 64701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24938 /* 64705 */ GIR_RootConstrainSelectedInstOperands,
24939 /* 64706 */ // GIR_Coverage, 198,
24940 /* 64706 */ GIR_EraseRootFromParent_Done,
24941 /* 64707 */ // Label 1524: @64707
24942 /* 64707 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(64768), // Rule ID 189 //
24943 /* 64712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24944 /* 64715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24945 /* 64719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24946 /* 64723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24947 /* 64727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24948 /* 64731 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24949 /* 64735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24950 /* 64740 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24951 /* 64745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24952 /* 64749 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24953 /* 64751 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24954 /* 64751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
24955 /* 64754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24956 /* 64756 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24957 /* 64758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24958 /* 64762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24959 /* 64766 */ GIR_RootConstrainSelectedInstOperands,
24960 /* 64767 */ // GIR_Coverage, 189,
24961 /* 64767 */ GIR_EraseRootFromParent_Done,
24962 /* 64768 */ // Label 1525: @64768
24963 /* 64768 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(64829), // Rule ID 197 //
24964 /* 64773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24965 /* 64776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24966 /* 64780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24967 /* 64784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24968 /* 64788 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24969 /* 64792 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24970 /* 64796 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24971 /* 64801 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24972 /* 64806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24973 /* 64810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24974 /* 64812 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24975 /* 64812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
24976 /* 64815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24977 /* 64817 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24978 /* 64819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24979 /* 64823 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24980 /* 64827 */ GIR_RootConstrainSelectedInstOperands,
24981 /* 64828 */ // GIR_Coverage, 197,
24982 /* 64828 */ GIR_EraseRootFromParent_Done,
24983 /* 64829 */ // Label 1526: @64829
24984 /* 64829 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(64860), // Rule ID 172 //
24985 /* 64834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24986 /* 64837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24987 /* 64841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24988 /* 64845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24989 /* 64849 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24990 /* 64849 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
24991 /* 64854 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24992 /* 64858 */ GIR_RootConstrainSelectedInstOperands,
24993 /* 64859 */ // GIR_Coverage, 172,
24994 /* 64859 */ GIR_Done,
24995 /* 64860 */ // Label 1527: @64860
24996 /* 64860 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(64891), // Rule ID 174 //
24997 /* 64865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
24998 /* 64868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24999 /* 64872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25000 /* 64876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25001 /* 64880 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25002 /* 64880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
25003 /* 64885 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25004 /* 64889 */ GIR_RootConstrainSelectedInstOperands,
25005 /* 64890 */ // GIR_Coverage, 174,
25006 /* 64890 */ GIR_Done,
25007 /* 64891 */ // Label 1528: @64891
25008 /* 64891 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(64922), // Rule ID 1164 //
25009 /* 64896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
25010 /* 64899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25011 /* 64903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25012 /* 64907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25013 /* 64911 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25014 /* 64911 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
25015 /* 64916 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25016 /* 64920 */ GIR_RootConstrainSelectedInstOperands,
25017 /* 64921 */ // GIR_Coverage, 1164,
25018 /* 64921 */ GIR_Done,
25019 /* 64922 */ // Label 1529: @64922
25020 /* 64922 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(64953), // Rule ID 1165 //
25021 /* 64927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
25022 /* 64930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25023 /* 64934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25024 /* 64938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25025 /* 64942 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25026 /* 64942 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
25027 /* 64947 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25028 /* 64951 */ GIR_RootConstrainSelectedInstOperands,
25029 /* 64952 */ // GIR_Coverage, 1165,
25030 /* 64952 */ GIR_Done,
25031 /* 64953 */ // Label 1530: @64953
25032 /* 64953 */ GIM_Reject,
25033 /* 64954 */ // Label 1522: @64954
25034 /* 64954 */ GIM_Reject,
25035 /* 64955 */ // Label 1513: @64955
25036 /* 64955 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(65047),
25037 /* 64960 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25038 /* 64963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25039 /* 64966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25040 /* 64970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25041 /* 64974 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(65027), // Rule ID 2117 //
25042 /* 64979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
25043 /* 64982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25044 /* 64986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25045 /* 64990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25046 /* 64994 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
25047 /* 64998 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25048 /* 65003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25049 /* 65008 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25050 /* 65010 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25051 /* 65010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
25052 /* 65013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25053 /* 65015 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
25054 /* 65017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
25055 /* 65021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
25056 /* 65025 */ GIR_RootConstrainSelectedInstOperands,
25057 /* 65026 */ // GIR_Coverage, 2117,
25058 /* 65026 */ GIR_EraseRootFromParent_Done,
25059 /* 65027 */ // Label 1532: @65027
25060 /* 65027 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(65046), // Rule ID 782 //
25061 /* 65032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25062 /* 65035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25063 /* 65039 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25064 /* 65039 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
25065 /* 65044 */ GIR_RootConstrainSelectedInstOperands,
25066 /* 65045 */ // GIR_Coverage, 782,
25067 /* 65045 */ GIR_Done,
25068 /* 65046 */ // Label 1533: @65046
25069 /* 65046 */ GIM_Reject,
25070 /* 65047 */ // Label 1531: @65047
25071 /* 65047 */ GIM_Reject,
25072 /* 65048 */ // Label 1514: @65048
25073 /* 65048 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(65140),
25074 /* 65053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25075 /* 65056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25076 /* 65059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25077 /* 65063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25078 /* 65067 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(65120), // Rule ID 2118 //
25079 /* 65072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
25080 /* 65075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25081 /* 65079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25082 /* 65083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25083 /* 65087 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
25084 /* 65091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25085 /* 65096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25086 /* 65101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25087 /* 65103 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25088 /* 65103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
25089 /* 65106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25090 /* 65108 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
25091 /* 65110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
25092 /* 65114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
25093 /* 65118 */ GIR_RootConstrainSelectedInstOperands,
25094 /* 65119 */ // GIR_Coverage, 2118,
25095 /* 65119 */ GIR_EraseRootFromParent_Done,
25096 /* 65120 */ // Label 1535: @65120
25097 /* 65120 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(65139), // Rule ID 783 //
25098 /* 65125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25099 /* 65128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25100 /* 65132 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25101 /* 65132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
25102 /* 65137 */ GIR_RootConstrainSelectedInstOperands,
25103 /* 65138 */ // GIR_Coverage, 783,
25104 /* 65138 */ GIR_Done,
25105 /* 65139 */ // Label 1536: @65139
25106 /* 65139 */ GIM_Reject,
25107 /* 65140 */ // Label 1534: @65140
25108 /* 65140 */ GIM_Reject,
25109 /* 65141 */ // Label 1515: @65141
25110 /* 65141 */ GIM_Reject,
25111 /* 65142 */ // Label 48: @65142
25112 /* 65142 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1541*/ GIMT_Encode4(65660),
25113 /* 65153 */ /*GILLT_s32*//*Label 1537*/ GIMT_Encode4(65185),
25114 /* 65157 */ /*GILLT_s64*//*Label 1538*/ GIMT_Encode4(65267), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25115 /* 65177 */ /*GILLT_v4s32*//*Label 1539*/ GIMT_Encode4(65404),
25116 /* 65181 */ /*GILLT_v2s64*//*Label 1540*/ GIMT_Encode4(65532),
25117 /* 65185 */ // Label 1537: @65185
25118 /* 65185 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(65266),
25119 /* 65190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25120 /* 65193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25121 /* 65196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25122 /* 65200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25123 /* 65204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25124 /* 65208 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(65227), // Rule ID 164 //
25125 /* 65213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
25126 /* 65216 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25127 /* 65216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
25128 /* 65221 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25129 /* 65225 */ GIR_RootConstrainSelectedInstOperands,
25130 /* 65226 */ // GIR_Coverage, 164,
25131 /* 65226 */ GIR_Done,
25132 /* 65227 */ // Label 1543: @65227
25133 /* 65227 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(65246), // Rule ID 1156 //
25134 /* 65232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25135 /* 65235 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25136 /* 65235 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
25137 /* 65240 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25138 /* 65244 */ GIR_RootConstrainSelectedInstOperands,
25139 /* 65245 */ // GIR_Coverage, 1156,
25140 /* 65245 */ GIR_Done,
25141 /* 65246 */ // Label 1544: @65246
25142 /* 65246 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(65265), // Rule ID 1213 //
25143 /* 65251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25144 /* 65254 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
25145 /* 65254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
25146 /* 65257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25147 /* 65259 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
25148 /* 65261 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
25149 /* 65263 */ GIR_RootConstrainSelectedInstOperands,
25150 /* 65264 */ // GIR_Coverage, 1213,
25151 /* 65264 */ GIR_EraseRootFromParent_Done,
25152 /* 65265 */ // Label 1545: @65265
25153 /* 65265 */ GIM_Reject,
25154 /* 65266 */ // Label 1542: @65266
25155 /* 65266 */ GIM_Reject,
25156 /* 65267 */ // Label 1538: @65267
25157 /* 65267 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(65403),
25158 /* 65272 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25159 /* 65275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25160 /* 65278 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(65309), // Rule ID 166 //
25161 /* 65283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25162 /* 65286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25163 /* 65290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25164 /* 65294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25165 /* 65298 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25166 /* 65298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
25167 /* 65303 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25168 /* 65307 */ GIR_RootConstrainSelectedInstOperands,
25169 /* 65308 */ // GIR_Coverage, 166,
25170 /* 65308 */ GIR_Done,
25171 /* 65309 */ // Label 1547: @65309
25172 /* 65309 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(65340), // Rule ID 168 //
25173 /* 65314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
25174 /* 65317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25175 /* 65321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25176 /* 65325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25177 /* 65329 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25178 /* 65329 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
25179 /* 65334 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25180 /* 65338 */ GIR_RootConstrainSelectedInstOperands,
25181 /* 65339 */ // GIR_Coverage, 168,
25182 /* 65339 */ GIR_Done,
25183 /* 65340 */ // Label 1548: @65340
25184 /* 65340 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(65371), // Rule ID 1162 //
25185 /* 65345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
25186 /* 65348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25187 /* 65352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25188 /* 65356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25189 /* 65360 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25190 /* 65360 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
25191 /* 65365 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25192 /* 65369 */ GIR_RootConstrainSelectedInstOperands,
25193 /* 65370 */ // GIR_Coverage, 1162,
25194 /* 65370 */ GIR_Done,
25195 /* 65371 */ // Label 1549: @65371
25196 /* 65371 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(65402), // Rule ID 1163 //
25197 /* 65376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
25198 /* 65379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25199 /* 65383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25200 /* 65387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25201 /* 65391 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25202 /* 65391 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
25203 /* 65396 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25204 /* 65400 */ GIR_RootConstrainSelectedInstOperands,
25205 /* 65401 */ // GIR_Coverage, 1163,
25206 /* 65401 */ GIR_Done,
25207 /* 65402 */ // Label 1550: @65402
25208 /* 65402 */ GIM_Reject,
25209 /* 65403 */ // Label 1546: @65403
25210 /* 65403 */ GIM_Reject,
25211 /* 65404 */ // Label 1539: @65404
25212 /* 65404 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(65531),
25213 /* 65409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25214 /* 65412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25215 /* 65415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25216 /* 65419 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(65463), // Rule ID 2536 //
25217 /* 65424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25218 /* 65427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25219 /* 65431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25220 /* 65435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25221 /* 65439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25222 /* 65444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25223 /* 65448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25224 /* 65450 */ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25225 /* 65450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
25226 /* 65453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25227 /* 65455 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
25228 /* 65457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25229 /* 65461 */ GIR_RootConstrainSelectedInstOperands,
25230 /* 65462 */ // GIR_Coverage, 2536,
25231 /* 65462 */ GIR_EraseRootFromParent_Done,
25232 /* 65463 */ // Label 1552: @65463
25233 /* 65463 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(65507), // Rule ID 724 //
25234 /* 65468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25235 /* 65471 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25236 /* 65475 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25237 /* 65479 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25238 /* 65483 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25239 /* 65487 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25240 /* 65492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25241 /* 65494 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25242 /* 65494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
25243 /* 65497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25244 /* 65499 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
25245 /* 65501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25246 /* 65505 */ GIR_RootConstrainSelectedInstOperands,
25247 /* 65506 */ // GIR_Coverage, 724,
25248 /* 65506 */ GIR_EraseRootFromParent_Done,
25249 /* 65507 */ // Label 1553: @65507
25250 /* 65507 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(65530), // Rule ID 760 //
25251 /* 65512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25252 /* 65515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25253 /* 65519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25254 /* 65523 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25255 /* 65523 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
25256 /* 65528 */ GIR_RootConstrainSelectedInstOperands,
25257 /* 65529 */ // GIR_Coverage, 760,
25258 /* 65529 */ GIR_Done,
25259 /* 65530 */ // Label 1554: @65530
25260 /* 65530 */ GIM_Reject,
25261 /* 65531 */ // Label 1551: @65531
25262 /* 65531 */ GIM_Reject,
25263 /* 65532 */ // Label 1540: @65532
25264 /* 65532 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(65659),
25265 /* 65537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25266 /* 65540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25267 /* 65543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25268 /* 65547 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(65591), // Rule ID 2537 //
25269 /* 65552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25270 /* 65555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25271 /* 65559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25272 /* 65563 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25273 /* 65567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25274 /* 65572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25275 /* 65576 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25276 /* 65578 */ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25277 /* 65578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
25278 /* 65581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25279 /* 65583 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
25280 /* 65585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25281 /* 65589 */ GIR_RootConstrainSelectedInstOperands,
25282 /* 65590 */ // GIR_Coverage, 2537,
25283 /* 65590 */ GIR_EraseRootFromParent_Done,
25284 /* 65591 */ // Label 1556: @65591
25285 /* 65591 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(65635), // Rule ID 725 //
25286 /* 65596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25287 /* 65599 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25288 /* 65603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25289 /* 65607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25290 /* 65611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25291 /* 65615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25292 /* 65620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25293 /* 65622 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25294 /* 65622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
25295 /* 65625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25296 /* 65627 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
25297 /* 65629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25298 /* 65633 */ GIR_RootConstrainSelectedInstOperands,
25299 /* 65634 */ // GIR_Coverage, 725,
25300 /* 65634 */ GIR_EraseRootFromParent_Done,
25301 /* 65635 */ // Label 1557: @65635
25302 /* 65635 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(65658), // Rule ID 761 //
25303 /* 65640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25304 /* 65643 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25305 /* 65647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25306 /* 65651 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25307 /* 65651 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
25308 /* 65656 */ GIR_RootConstrainSelectedInstOperands,
25309 /* 65657 */ // GIR_Coverage, 761,
25310 /* 65657 */ GIR_Done,
25311 /* 65658 */ // Label 1558: @65658
25312 /* 65658 */ GIM_Reject,
25313 /* 65659 */ // Label 1555: @65659
25314 /* 65659 */ GIM_Reject,
25315 /* 65660 */ // Label 1541: @65660
25316 /* 65660 */ GIM_Reject,
25317 /* 65661 */ // Label 49: @65661
25318 /* 65661 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1561*/ GIMT_Encode4(65762),
25319 /* 65672 */ /*GILLT_v4s32*//*Label 1559*/ GIMT_Encode4(65680),
25320 /* 65676 */ /*GILLT_v2s64*//*Label 1560*/ GIMT_Encode4(65721),
25321 /* 65680 */ // Label 1559: @65680
25322 /* 65680 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(65720), // Rule ID 748 //
25323 /* 65685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25324 /* 65688 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25325 /* 65691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25326 /* 65694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25327 /* 65697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25328 /* 65701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25329 /* 65705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25330 /* 65709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25331 /* 65713 */ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25332 /* 65713 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
25333 /* 65718 */ GIR_RootConstrainSelectedInstOperands,
25334 /* 65719 */ // GIR_Coverage, 748,
25335 /* 65719 */ GIR_Done,
25336 /* 65720 */ // Label 1562: @65720
25337 /* 65720 */ GIM_Reject,
25338 /* 65721 */ // Label 1560: @65721
25339 /* 65721 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(65761), // Rule ID 749 //
25340 /* 65726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25341 /* 65729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25342 /* 65732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25343 /* 65735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
25344 /* 65738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25345 /* 65742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25346 /* 65746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25347 /* 65750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25348 /* 65754 */ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25349 /* 65754 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
25350 /* 65759 */ GIR_RootConstrainSelectedInstOperands,
25351 /* 65760 */ // GIR_Coverage, 749,
25352 /* 65760 */ GIR_Done,
25353 /* 65761 */ // Label 1563: @65761
25354 /* 65761 */ GIM_Reject,
25355 /* 65762 */ // Label 1561: @65762
25356 /* 65762 */ GIM_Reject,
25357 /* 65763 */ // Label 50: @65763
25358 /* 65763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1568*/ GIMT_Encode4(66093),
25359 /* 65774 */ /*GILLT_s32*//*Label 1564*/ GIMT_Encode4(65806),
25360 /* 65778 */ /*GILLT_s64*//*Label 1565*/ GIMT_Encode4(65888), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25361 /* 65798 */ /*GILLT_v4s32*//*Label 1566*/ GIMT_Encode4(66025),
25362 /* 65802 */ /*GILLT_v2s64*//*Label 1567*/ GIMT_Encode4(66059),
25363 /* 65806 */ // Label 1564: @65806
25364 /* 65806 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(65887),
25365 /* 65811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25366 /* 65814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25367 /* 65817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25368 /* 65821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25369 /* 65825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25370 /* 65829 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(65848), // Rule ID 158 //
25371 /* 65834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
25372 /* 65837 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25373 /* 65837 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
25374 /* 65842 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25375 /* 65846 */ GIR_RootConstrainSelectedInstOperands,
25376 /* 65847 */ // GIR_Coverage, 158,
25377 /* 65847 */ GIR_Done,
25378 /* 65848 */ // Label 1570: @65848
25379 /* 65848 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(65867), // Rule ID 1155 //
25380 /* 65853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25381 /* 65856 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25382 /* 65856 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
25383 /* 65861 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25384 /* 65865 */ GIR_RootConstrainSelectedInstOperands,
25385 /* 65866 */ // GIR_Coverage, 1155,
25386 /* 65866 */ GIR_Done,
25387 /* 65867 */ // Label 1571: @65867
25388 /* 65867 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(65886), // Rule ID 1214 //
25389 /* 65872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25390 /* 65875 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
25391 /* 65875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
25392 /* 65878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25393 /* 65880 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
25394 /* 65882 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
25395 /* 65884 */ GIR_RootConstrainSelectedInstOperands,
25396 /* 65885 */ // GIR_Coverage, 1214,
25397 /* 65885 */ GIR_EraseRootFromParent_Done,
25398 /* 65886 */ // Label 1572: @65886
25399 /* 65886 */ GIM_Reject,
25400 /* 65887 */ // Label 1569: @65887
25401 /* 65887 */ GIM_Reject,
25402 /* 65888 */ // Label 1565: @65888
25403 /* 65888 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(66024),
25404 /* 65893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25405 /* 65896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25406 /* 65899 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(65930), // Rule ID 160 //
25407 /* 65904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25408 /* 65907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25409 /* 65911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25410 /* 65915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25411 /* 65919 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25412 /* 65919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
25413 /* 65924 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25414 /* 65928 */ GIR_RootConstrainSelectedInstOperands,
25415 /* 65929 */ // GIR_Coverage, 160,
25416 /* 65929 */ GIR_Done,
25417 /* 65930 */ // Label 1574: @65930
25418 /* 65930 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(65961), // Rule ID 162 //
25419 /* 65935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
25420 /* 65938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25421 /* 65942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25422 /* 65946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25423 /* 65950 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25424 /* 65950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
25425 /* 65955 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25426 /* 65959 */ GIR_RootConstrainSelectedInstOperands,
25427 /* 65960 */ // GIR_Coverage, 162,
25428 /* 65960 */ GIR_Done,
25429 /* 65961 */ // Label 1575: @65961
25430 /* 65961 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(65992), // Rule ID 1160 //
25431 /* 65966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
25432 /* 65969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25433 /* 65973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25434 /* 65977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25435 /* 65981 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25436 /* 65981 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
25437 /* 65986 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25438 /* 65990 */ GIR_RootConstrainSelectedInstOperands,
25439 /* 65991 */ // GIR_Coverage, 1160,
25440 /* 65991 */ GIR_Done,
25441 /* 65992 */ // Label 1576: @65992
25442 /* 65992 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(66023), // Rule ID 1161 //
25443 /* 65997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
25444 /* 66000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25445 /* 66004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25446 /* 66008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25447 /* 66012 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25448 /* 66012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
25449 /* 66017 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25450 /* 66021 */ GIR_RootConstrainSelectedInstOperands,
25451 /* 66022 */ // GIR_Coverage, 1161,
25452 /* 66022 */ GIR_Done,
25453 /* 66023 */ // Label 1577: @66023
25454 /* 66023 */ GIM_Reject,
25455 /* 66024 */ // Label 1573: @66024
25456 /* 66024 */ GIM_Reject,
25457 /* 66025 */ // Label 1566: @66025
25458 /* 66025 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(66058), // Rule ID 720 //
25459 /* 66030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25460 /* 66033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25461 /* 66036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25462 /* 66039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25463 /* 66043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25464 /* 66047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25465 /* 66051 */ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25466 /* 66051 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
25467 /* 66056 */ GIR_RootConstrainSelectedInstOperands,
25468 /* 66057 */ // GIR_Coverage, 720,
25469 /* 66057 */ GIR_Done,
25470 /* 66058 */ // Label 1578: @66058
25471 /* 66058 */ GIM_Reject,
25472 /* 66059 */ // Label 1567: @66059
25473 /* 66059 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(66092), // Rule ID 721 //
25474 /* 66064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25475 /* 66067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25476 /* 66070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25477 /* 66073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25478 /* 66077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25479 /* 66081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25480 /* 66085 */ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25481 /* 66085 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
25482 /* 66090 */ GIR_RootConstrainSelectedInstOperands,
25483 /* 66091 */ // GIR_Coverage, 721,
25484 /* 66091 */ GIR_Done,
25485 /* 66092 */ // Label 1579: @66092
25486 /* 66092 */ GIM_Reject,
25487 /* 66093 */ // Label 1568: @66093
25488 /* 66093 */ GIM_Reject,
25489 /* 66094 */ // Label 51: @66094
25490 /* 66094 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(66167),
25491 /* 66105 */ /*GILLT_v4s32*//*Label 1580*/ GIMT_Encode4(66113),
25492 /* 66109 */ /*GILLT_v2s64*//*Label 1581*/ GIMT_Encode4(66140),
25493 /* 66113 */ // Label 1580: @66113
25494 /* 66113 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(66139), // Rule ID 726 //
25495 /* 66118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25496 /* 66121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25497 /* 66124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25498 /* 66128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25499 /* 66132 */ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
25500 /* 66132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
25501 /* 66137 */ GIR_RootConstrainSelectedInstOperands,
25502 /* 66138 */ // GIR_Coverage, 726,
25503 /* 66138 */ GIR_Done,
25504 /* 66139 */ // Label 1583: @66139
25505 /* 66139 */ GIM_Reject,
25506 /* 66140 */ // Label 1581: @66140
25507 /* 66140 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(66166), // Rule ID 727 //
25508 /* 66145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25509 /* 66148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25510 /* 66151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25511 /* 66155 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25512 /* 66159 */ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
25513 /* 66159 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
25514 /* 66164 */ GIR_RootConstrainSelectedInstOperands,
25515 /* 66165 */ // GIR_Coverage, 727,
25516 /* 66165 */ GIR_Done,
25517 /* 66166 */ // Label 1584: @66166
25518 /* 66166 */ GIM_Reject,
25519 /* 66167 */ // Label 1582: @66167
25520 /* 66167 */ GIM_Reject,
25521 /* 66168 */ // Label 52: @66168
25522 /* 66168 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1587*/ GIMT_Encode4(66241),
25523 /* 66179 */ /*GILLT_v4s32*//*Label 1585*/ GIMT_Encode4(66187),
25524 /* 66183 */ /*GILLT_v2s64*//*Label 1586*/ GIMT_Encode4(66214),
25525 /* 66187 */ // Label 1585: @66187
25526 /* 66187 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(66213), // Rule ID 746 //
25527 /* 66192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25528 /* 66195 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25529 /* 66198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25530 /* 66202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25531 /* 66206 */ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25532 /* 66206 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
25533 /* 66211 */ GIR_RootConstrainSelectedInstOperands,
25534 /* 66212 */ // GIR_Coverage, 746,
25535 /* 66212 */ GIR_Done,
25536 /* 66213 */ // Label 1588: @66213
25537 /* 66213 */ GIM_Reject,
25538 /* 66214 */ // Label 1586: @66214
25539 /* 66214 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(66240), // Rule ID 747 //
25540 /* 66219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25541 /* 66222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25542 /* 66225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25543 /* 66229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25544 /* 66233 */ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25545 /* 66233 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
25546 /* 66238 */ GIR_RootConstrainSelectedInstOperands,
25547 /* 66239 */ // GIR_Coverage, 747,
25548 /* 66239 */ GIR_Done,
25549 /* 66240 */ // Label 1589: @66240
25550 /* 66240 */ GIM_Reject,
25551 /* 66241 */ // Label 1587: @66241
25552 /* 66241 */ GIM_Reject,
25553 /* 66242 */ // Label 53: @66242
25554 /* 66242 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1592*/ GIMT_Encode4(66434),
25555 /* 66253 */ /*GILLT_s32*//*Label 1590*/ GIMT_Encode4(66261),
25556 /* 66257 */ /*GILLT_s64*//*Label 1591*/ GIMT_Encode4(66324),
25557 /* 66261 */ // Label 1590: @66261
25558 /* 66261 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(66323),
25559 /* 66266 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25560 /* 66269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25561 /* 66273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25562 /* 66277 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(66292), // Rule ID 126 //
25563 /* 66282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat),
25564 /* 66285 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25565 /* 66285 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
25566 /* 66290 */ GIR_RootConstrainSelectedInstOperands,
25567 /* 66291 */ // GIR_Coverage, 126,
25568 /* 66291 */ GIR_Done,
25569 /* 66292 */ // Label 1594: @66292
25570 /* 66292 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(66307), // Rule ID 1176 //
25571 /* 66297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25572 /* 66300 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25573 /* 66300 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
25574 /* 66305 */ GIR_RootConstrainSelectedInstOperands,
25575 /* 66306 */ // GIR_Coverage, 1176,
25576 /* 66306 */ GIR_Done,
25577 /* 66307 */ // Label 1595: @66307
25578 /* 66307 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(66322), // Rule ID 1215 //
25579 /* 66312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25580 /* 66315 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25581 /* 66315 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
25582 /* 66320 */ GIR_RootConstrainSelectedInstOperands,
25583 /* 66321 */ // GIR_Coverage, 1215,
25584 /* 66321 */ GIR_Done,
25585 /* 66322 */ // Label 1596: @66322
25586 /* 66322 */ GIM_Reject,
25587 /* 66323 */ // Label 1593: @66323
25588 /* 66323 */ GIM_Reject,
25589 /* 66324 */ // Label 1591: @66324
25590 /* 66324 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(66433),
25591 /* 66329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25592 /* 66332 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(66359), // Rule ID 127 //
25593 /* 66337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25594 /* 66340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25595 /* 66344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25596 /* 66348 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25597 /* 66348 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
25598 /* 66353 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25599 /* 66357 */ GIR_RootConstrainSelectedInstOperands,
25600 /* 66358 */ // GIR_Coverage, 127,
25601 /* 66358 */ GIR_Done,
25602 /* 66359 */ // Label 1598: @66359
25603 /* 66359 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(66386), // Rule ID 128 //
25604 /* 66364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
25605 /* 66367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25606 /* 66371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25607 /* 66375 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25608 /* 66375 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
25609 /* 66380 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25610 /* 66384 */ GIR_RootConstrainSelectedInstOperands,
25611 /* 66385 */ // GIR_Coverage, 128,
25612 /* 66385 */ GIR_Done,
25613 /* 66386 */ // Label 1599: @66386
25614 /* 66386 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(66409), // Rule ID 1177 //
25615 /* 66391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
25616 /* 66394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25617 /* 66398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25618 /* 66402 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25619 /* 66402 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
25620 /* 66407 */ GIR_RootConstrainSelectedInstOperands,
25621 /* 66408 */ // GIR_Coverage, 1177,
25622 /* 66408 */ GIR_Done,
25623 /* 66409 */ // Label 1600: @66409
25624 /* 66409 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(66432), // Rule ID 1178 //
25625 /* 66414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
25626 /* 66417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25627 /* 66421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25628 /* 66425 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25629 /* 66425 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
25630 /* 66430 */ GIR_RootConstrainSelectedInstOperands,
25631 /* 66431 */ // GIR_Coverage, 1178,
25632 /* 66431 */ GIR_Done,
25633 /* 66432 */ // Label 1601: @66432
25634 /* 66432 */ GIM_Reject,
25635 /* 66433 */ // Label 1597: @66433
25636 /* 66433 */ GIM_Reject,
25637 /* 66434 */ // Label 1592: @66434
25638 /* 66434 */ GIM_Reject,
25639 /* 66435 */ // Label 54: @66435
25640 /* 66435 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1604*/ GIMT_Encode4(66628),
25641 /* 66446 */ /*GILLT_s32*//*Label 1602*/ GIMT_Encode4(66454),
25642 /* 66450 */ /*GILLT_s64*//*Label 1603*/ GIMT_Encode4(66481),
25643 /* 66454 */ // Label 1602: @66454
25644 /* 66454 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(66480), // Rule ID 1080 //
25645 /* 66459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25646 /* 66462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25647 /* 66465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25648 /* 66469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25649 /* 66473 */ // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
25650 /* 66473 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_W_PSEUDO),
25651 /* 66478 */ GIR_RootConstrainSelectedInstOperands,
25652 /* 66479 */ // GIR_Coverage, 1080,
25653 /* 66479 */ GIR_Done,
25654 /* 66480 */ // Label 1605: @66480
25655 /* 66480 */ GIM_Reject,
25656 /* 66481 */ // Label 1603: @66481
25657 /* 66481 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(66507), // Rule ID 1082 //
25658 /* 66486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25659 /* 66489 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25660 /* 66492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25661 /* 66496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25662 /* 66500 */ // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
25663 /* 66500 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_D_PSEUDO),
25664 /* 66505 */ GIR_RootConstrainSelectedInstOperands,
25665 /* 66506 */ // GIR_Coverage, 1082,
25666 /* 66506 */ GIR_Done,
25667 /* 66507 */ // Label 1606: @66507
25668 /* 66507 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(66537), // Rule ID 1528 //
25669 /* 66512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips),
25670 /* 66515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25671 /* 66518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25672 /* 66522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25673 /* 66526 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25674 /* 66526 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
25675 /* 66531 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25676 /* 66535 */ GIR_RootConstrainSelectedInstOperands,
25677 /* 66536 */ // GIR_Coverage, 1528,
25678 /* 66536 */ GIR_Done,
25679 /* 66537 */ // Label 1607: @66537
25680 /* 66537 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(66567), // Rule ID 1543 //
25681 /* 66542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips),
25682 /* 66545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25683 /* 66548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25684 /* 66552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25685 /* 66556 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25686 /* 66556 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
25687 /* 66561 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25688 /* 66565 */ GIR_RootConstrainSelectedInstOperands,
25689 /* 66566 */ // GIR_Coverage, 1543,
25690 /* 66566 */ GIR_Done,
25691 /* 66567 */ // Label 1608: @66567
25692 /* 66567 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(66597), // Rule ID 2402 //
25693 /* 66572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat),
25694 /* 66575 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25695 /* 66578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25696 /* 66582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25697 /* 66586 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25698 /* 66586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
25699 /* 66591 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25700 /* 66595 */ GIR_RootConstrainSelectedInstOperands,
25701 /* 66596 */ // GIR_Coverage, 2402,
25702 /* 66596 */ GIR_Done,
25703 /* 66597 */ // Label 1609: @66597
25704 /* 66597 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(66627), // Rule ID 2404 //
25705 /* 66602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit),
25706 /* 66605 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25707 /* 66608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25708 /* 66612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25709 /* 66616 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25710 /* 66616 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
25711 /* 66621 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25712 /* 66625 */ GIR_RootConstrainSelectedInstOperands,
25713 /* 66626 */ // GIR_Coverage, 2404,
25714 /* 66626 */ GIR_Done,
25715 /* 66627 */ // Label 1610: @66627
25716 /* 66627 */ GIM_Reject,
25717 /* 66628 */ // Label 1604: @66628
25718 /* 66628 */ GIM_Reject,
25719 /* 66629 */ // Label 55: @66629
25720 /* 66629 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1613*/ GIMT_Encode4(66807),
25721 /* 66640 */ /*GILLT_s16*//*Label 1611*/ GIMT_Encode4(66648),
25722 /* 66644 */ /*GILLT_s32*//*Label 1612*/ GIMT_Encode4(66701),
25723 /* 66648 */ // Label 1611: @66648
25724 /* 66648 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(66674), // Rule ID 1081 //
25725 /* 66653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25726 /* 66656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25727 /* 66659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25728 /* 66663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25729 /* 66667 */ // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
25730 /* 66667 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_W_PSEUDO),
25731 /* 66672 */ GIR_RootConstrainSelectedInstOperands,
25732 /* 66673 */ // GIR_Coverage, 1081,
25733 /* 66673 */ GIR_Done,
25734 /* 66674 */ // Label 1614: @66674
25735 /* 66674 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(66700), // Rule ID 1083 //
25736 /* 66679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25737 /* 66682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25738 /* 66685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25739 /* 66689 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25740 /* 66693 */ // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
25741 /* 66693 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_D_PSEUDO),
25742 /* 66698 */ GIR_RootConstrainSelectedInstOperands,
25743 /* 66699 */ // GIR_Coverage, 1083,
25744 /* 66699 */ GIR_Done,
25745 /* 66700 */ // Label 1615: @66700
25746 /* 66700 */ GIM_Reject,
25747 /* 66701 */ // Label 1612: @66701
25748 /* 66701 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(66806),
25749 /* 66706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25750 /* 66709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25751 /* 66713 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(66736), // Rule ID 1526 //
25752 /* 66718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips),
25753 /* 66721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25754 /* 66725 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25755 /* 66725 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
25756 /* 66730 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25757 /* 66734 */ GIR_RootConstrainSelectedInstOperands,
25758 /* 66735 */ // GIR_Coverage, 1526,
25759 /* 66735 */ GIR_Done,
25760 /* 66736 */ // Label 1617: @66736
25761 /* 66736 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(66759), // Rule ID 1541 //
25762 /* 66741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips),
25763 /* 66744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25764 /* 66748 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25765 /* 66748 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
25766 /* 66753 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25767 /* 66757 */ GIR_RootConstrainSelectedInstOperands,
25768 /* 66758 */ // GIR_Coverage, 1541,
25769 /* 66758 */ GIR_Done,
25770 /* 66759 */ // Label 1618: @66759
25771 /* 66759 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(66782), // Rule ID 2401 //
25772 /* 66764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat),
25773 /* 66767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25774 /* 66771 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25775 /* 66771 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
25776 /* 66776 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25777 /* 66780 */ GIR_RootConstrainSelectedInstOperands,
25778 /* 66781 */ // GIR_Coverage, 2401,
25779 /* 66781 */ GIR_Done,
25780 /* 66782 */ // Label 1619: @66782
25781 /* 66782 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(66805), // Rule ID 2403 //
25782 /* 66787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit),
25783 /* 66790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25784 /* 66794 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25785 /* 66794 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
25786 /* 66799 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25787 /* 66803 */ GIR_RootConstrainSelectedInstOperands,
25788 /* 66804 */ // GIR_Coverage, 2403,
25789 /* 66804 */ GIR_Done,
25790 /* 66805 */ // Label 1620: @66805
25791 /* 66805 */ GIM_Reject,
25792 /* 66806 */ // Label 1616: @66806
25793 /* 66806 */ GIM_Reject,
25794 /* 66807 */ // Label 1613: @66807
25795 /* 66807 */ GIM_Reject,
25796 /* 66808 */ // Label 56: @66808
25797 /* 66808 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1623*/ GIMT_Encode4(66881),
25798 /* 66819 */ /*GILLT_v4s32*//*Label 1621*/ GIMT_Encode4(66827),
25799 /* 66823 */ /*GILLT_v2s64*//*Label 1622*/ GIMT_Encode4(66854),
25800 /* 66827 */ // Label 1621: @66827
25801 /* 66827 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(66853), // Rule ID 800 //
25802 /* 66832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25803 /* 66835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25804 /* 66838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25805 /* 66842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25806 /* 66846 */ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25807 /* 66846 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
25808 /* 66851 */ GIR_RootConstrainSelectedInstOperands,
25809 /* 66852 */ // GIR_Coverage, 800,
25810 /* 66852 */ GIR_Done,
25811 /* 66853 */ // Label 1624: @66853
25812 /* 66853 */ GIM_Reject,
25813 /* 66854 */ // Label 1622: @66854
25814 /* 66854 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(66880), // Rule ID 801 //
25815 /* 66859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25816 /* 66862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25817 /* 66865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25818 /* 66869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25819 /* 66873 */ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25820 /* 66873 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
25821 /* 66878 */ GIR_RootConstrainSelectedInstOperands,
25822 /* 66879 */ // GIR_Coverage, 801,
25823 /* 66879 */ GIR_Done,
25824 /* 66880 */ // Label 1625: @66880
25825 /* 66880 */ GIM_Reject,
25826 /* 66881 */ // Label 1623: @66881
25827 /* 66881 */ GIM_Reject,
25828 /* 66882 */ // Label 57: @66882
25829 /* 66882 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1628*/ GIMT_Encode4(66955),
25830 /* 66893 */ /*GILLT_v4s32*//*Label 1626*/ GIMT_Encode4(66901),
25831 /* 66897 */ /*GILLT_v2s64*//*Label 1627*/ GIMT_Encode4(66928),
25832 /* 66901 */ // Label 1626: @66901
25833 /* 66901 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(66927), // Rule ID 802 //
25834 /* 66906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25835 /* 66909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25836 /* 66912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25837 /* 66916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25838 /* 66920 */ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25839 /* 66920 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
25840 /* 66925 */ GIR_RootConstrainSelectedInstOperands,
25841 /* 66926 */ // GIR_Coverage, 802,
25842 /* 66926 */ GIR_Done,
25843 /* 66927 */ // Label 1629: @66927
25844 /* 66927 */ GIM_Reject,
25845 /* 66928 */ // Label 1627: @66928
25846 /* 66928 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(66954), // Rule ID 803 //
25847 /* 66933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25848 /* 66936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25849 /* 66939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25850 /* 66943 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25851 /* 66947 */ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25852 /* 66947 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
25853 /* 66952 */ GIR_RootConstrainSelectedInstOperands,
25854 /* 66953 */ // GIR_Coverage, 803,
25855 /* 66953 */ GIR_Done,
25856 /* 66954 */ // Label 1630: @66954
25857 /* 66954 */ GIM_Reject,
25858 /* 66955 */ // Label 1628: @66955
25859 /* 66955 */ GIM_Reject,
25860 /* 66956 */ // Label 58: @66956
25861 /* 66956 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1635*/ GIMT_Encode4(67216),
25862 /* 66967 */ /*GILLT_s32*//*Label 1631*/ GIMT_Encode4(66999),
25863 /* 66971 */ /*GILLT_s64*//*Label 1632*/ GIMT_Encode4(67083), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25864 /* 66991 */ /*GILLT_v4s32*//*Label 1633*/ GIMT_Encode4(67162),
25865 /* 66995 */ /*GILLT_v2s64*//*Label 1634*/ GIMT_Encode4(67189),
25866 /* 66999 */ // Label 1631: @66999
25867 /* 66999 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(67022), // Rule ID 1518 //
25868 /* 67004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25869 /* 67007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25870 /* 67011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25871 /* 67015 */ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
25872 /* 67015 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
25873 /* 67020 */ GIR_RootConstrainSelectedInstOperands,
25874 /* 67021 */ // GIR_Coverage, 1518,
25875 /* 67021 */ GIR_Done,
25876 /* 67022 */ // Label 1636: @67022
25877 /* 67022 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(67082), // Rule ID 1534 //
25878 /* 67027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat),
25879 /* 67030 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25880 /* 67033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25881 /* 67037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25882 /* 67041 */ // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
25883 /* 67041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25884 /* 67044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
25885 /* 67048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25886 /* 67053 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25887 /* 67057 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25888 /* 67059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25889 /* 67062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
25890 /* 67064 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
25891 /* 67071 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
25892 /* 67076 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
25893 /* 67081 */ // GIR_Coverage, 1534,
25894 /* 67081 */ GIR_EraseRootFromParent_Done,
25895 /* 67082 */ // Label 1637: @67082
25896 /* 67082 */ GIM_Reject,
25897 /* 67083 */ // Label 1632: @67083
25898 /* 67083 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(67109), // Rule ID 1523 //
25899 /* 67088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSingleFloat_NotFP64bit),
25900 /* 67091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25901 /* 67094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25902 /* 67098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25903 /* 67102 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25904 /* 67102 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
25905 /* 67107 */ GIR_RootConstrainSelectedInstOperands,
25906 /* 67108 */ // GIR_Coverage, 1523,
25907 /* 67108 */ GIR_Done,
25908 /* 67109 */ // Label 1638: @67109
25909 /* 67109 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(67135), // Rule ID 1532 //
25910 /* 67114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat),
25911 /* 67117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25912 /* 67120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25913 /* 67124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25914 /* 67128 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25915 /* 67128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
25916 /* 67133 */ GIR_RootConstrainSelectedInstOperands,
25917 /* 67134 */ // GIR_Coverage, 1532,
25918 /* 67134 */ GIR_Done,
25919 /* 67135 */ // Label 1639: @67135
25920 /* 67135 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(67161), // Rule ID 1536 //
25921 /* 67140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat),
25922 /* 67143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25923 /* 67146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25924 /* 67150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25925 /* 67154 */ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
25926 /* 67154 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
25927 /* 67159 */ GIR_RootConstrainSelectedInstOperands,
25928 /* 67160 */ // GIR_Coverage, 1536,
25929 /* 67160 */ GIR_Done,
25930 /* 67161 */ // Label 1640: @67161
25931 /* 67161 */ GIM_Reject,
25932 /* 67162 */ // Label 1633: @67162
25933 /* 67162 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(67188), // Rule ID 732 //
25934 /* 67167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25935 /* 67170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25936 /* 67173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25937 /* 67177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25938 /* 67181 */ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25939 /* 67181 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
25940 /* 67186 */ GIR_RootConstrainSelectedInstOperands,
25941 /* 67187 */ // GIR_Coverage, 732,
25942 /* 67187 */ GIR_Done,
25943 /* 67188 */ // Label 1641: @67188
25944 /* 67188 */ GIM_Reject,
25945 /* 67189 */ // Label 1634: @67189
25946 /* 67189 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(67215), // Rule ID 733 //
25947 /* 67194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25948 /* 67197 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25949 /* 67200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25950 /* 67204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25951 /* 67208 */ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25952 /* 67208 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
25953 /* 67213 */ GIR_RootConstrainSelectedInstOperands,
25954 /* 67214 */ // GIR_Coverage, 733,
25955 /* 67214 */ GIR_Done,
25956 /* 67215 */ // Label 1642: @67215
25957 /* 67215 */ GIM_Reject,
25958 /* 67216 */ // Label 1635: @67216
25959 /* 67216 */ GIM_Reject,
25960 /* 67217 */ // Label 59: @67217
25961 /* 67217 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1645*/ GIMT_Encode4(67290),
25962 /* 67228 */ /*GILLT_v4s32*//*Label 1643*/ GIMT_Encode4(67236),
25963 /* 67232 */ /*GILLT_v2s64*//*Label 1644*/ GIMT_Encode4(67263),
25964 /* 67236 */ // Label 1643: @67236
25965 /* 67236 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(67262), // Rule ID 734 //
25966 /* 67241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25967 /* 67244 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25968 /* 67247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25969 /* 67251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25970 /* 67255 */ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25971 /* 67255 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
25972 /* 67260 */ GIR_RootConstrainSelectedInstOperands,
25973 /* 67261 */ // GIR_Coverage, 734,
25974 /* 67261 */ GIR_Done,
25975 /* 67262 */ // Label 1646: @67262
25976 /* 67262 */ GIM_Reject,
25977 /* 67263 */ // Label 1644: @67263
25978 /* 67263 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(67289), // Rule ID 735 //
25979 /* 67268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25980 /* 67271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25981 /* 67274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25982 /* 67278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25983 /* 67282 */ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25984 /* 67282 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
25985 /* 67287 */ GIR_RootConstrainSelectedInstOperands,
25986 /* 67288 */ // GIR_Coverage, 735,
25987 /* 67288 */ GIR_Done,
25988 /* 67289 */ // Label 1647: @67289
25989 /* 67289 */ GIM_Reject,
25990 /* 67290 */ // Label 1645: @67290
25991 /* 67290 */ GIM_Reject,
25992 /* 67291 */ // Label 60: @67291
25993 /* 67291 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(9), /*)*//*default:*//*Label 1651*/ GIMT_Encode4(67440),
25994 /* 67302 */ /*GILLT_s64*//*Label 1648*/ GIMT_Encode4(67330), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25995 /* 67322 */ /*GILLT_v4s32*//*Label 1649*/ GIMT_Encode4(67386),
25996 /* 67326 */ /*GILLT_v2s64*//*Label 1650*/ GIMT_Encode4(67413),
25997 /* 67330 */ // Label 1648: @67330
25998 /* 67330 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(67385),
25999 /* 67335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26000 /* 67338 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(67361), // Rule ID 1174 //
26001 /* 67343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
26002 /* 67346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26003 /* 67350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
26004 /* 67354 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
26005 /* 67354 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
26006 /* 67359 */ GIR_RootConstrainSelectedInstOperands,
26007 /* 67360 */ // GIR_Coverage, 1174,
26008 /* 67360 */ GIR_Done,
26009 /* 67361 */ // Label 1653: @67361
26010 /* 67361 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(67384), // Rule ID 1175 //
26011 /* 67366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
26012 /* 67369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26013 /* 67373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26014 /* 67377 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
26015 /* 67377 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
26016 /* 67382 */ GIR_RootConstrainSelectedInstOperands,
26017 /* 67383 */ // GIR_Coverage, 1175,
26018 /* 67383 */ GIR_Done,
26019 /* 67384 */ // Label 1654: @67384
26020 /* 67384 */ GIM_Reject,
26021 /* 67385 */ // Label 1652: @67385
26022 /* 67385 */ GIM_Reject,
26023 /* 67386 */ // Label 1649: @67386
26024 /* 67386 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(67412), // Rule ID 1066 //
26025 /* 67391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26026 /* 67394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26027 /* 67397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26028 /* 67401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26029 /* 67405 */ // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
26030 /* 67405 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
26031 /* 67410 */ GIR_RootConstrainSelectedInstOperands,
26032 /* 67411 */ // GIR_Coverage, 1066,
26033 /* 67411 */ GIR_Done,
26034 /* 67412 */ // Label 1655: @67412
26035 /* 67412 */ GIM_Reject,
26036 /* 67413 */ // Label 1650: @67413
26037 /* 67413 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(67439), // Rule ID 1067 //
26038 /* 67418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26039 /* 67421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26040 /* 67424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26041 /* 67428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26042 /* 67432 */ // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
26043 /* 67432 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
26044 /* 67437 */ GIR_RootConstrainSelectedInstOperands,
26045 /* 67438 */ // GIR_Coverage, 1067,
26046 /* 67438 */ GIR_Done,
26047 /* 67439 */ // Label 1656: @67439
26048 /* 67439 */ GIM_Reject,
26049 /* 67440 */ // Label 1651: @67440
26050 /* 67440 */ GIM_Reject,
26051 /* 67441 */ // Label 61: @67441
26052 /* 67441 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1659*/ GIMT_Encode4(67514),
26053 /* 67452 */ /*GILLT_s32*//*Label 1657*/ GIMT_Encode4(67460),
26054 /* 67456 */ /*GILLT_s64*//*Label 1658*/ GIMT_Encode4(67487),
26055 /* 67460 */ // Label 1657: @67460
26056 /* 67460 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(67486), // Rule ID 1889 //
26057 /* 67465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26058 /* 67468 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26059 /* 67471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26060 /* 67475 */ // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
26061 /* 67475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26062 /* 67478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
26063 /* 67480 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26064 /* 67482 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26065 /* 67484 */ GIR_RootConstrainSelectedInstOperands,
26066 /* 67485 */ // GIR_Coverage, 1889,
26067 /* 67485 */ GIR_EraseRootFromParent_Done,
26068 /* 67486 */ // Label 1660: @67486
26069 /* 67486 */ GIM_Reject,
26070 /* 67487 */ // Label 1658: @67487
26071 /* 67487 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(67513), // Rule ID 1890 //
26072 /* 67492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26073 /* 67495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26074 /* 67498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26075 /* 67502 */ // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
26076 /* 67502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26077 /* 67505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
26078 /* 67507 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26079 /* 67509 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26080 /* 67511 */ GIR_RootConstrainSelectedInstOperands,
26081 /* 67512 */ // GIR_Coverage, 1890,
26082 /* 67512 */ GIR_EraseRootFromParent_Done,
26083 /* 67513 */ // Label 1661: @67513
26084 /* 67513 */ GIM_Reject,
26085 /* 67514 */ // Label 1659: @67514
26086 /* 67514 */ GIM_Reject,
26087 /* 67515 */ // Label 62: @67515
26088 /* 67515 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1664*/ GIMT_Encode4(67586),
26089 /* 67526 */ /*GILLT_s32*//*Label 1662*/ GIMT_Encode4(67534),
26090 /* 67530 */ /*GILLT_s64*//*Label 1663*/ GIMT_Encode4(67560),
26091 /* 67534 */ // Label 1662: @67534
26092 /* 67534 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(67559), // Rule ID 1886 //
26093 /* 67539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26094 /* 67542 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26095 /* 67545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26096 /* 67548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26097 /* 67552 */ // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26098 /* 67552 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26099 /* 67557 */ GIR_RootConstrainSelectedInstOperands,
26100 /* 67558 */ // GIR_Coverage, 1886,
26101 /* 67558 */ GIR_Done,
26102 /* 67559 */ // Label 1665: @67559
26103 /* 67559 */ GIM_Reject,
26104 /* 67560 */ // Label 1663: @67560
26105 /* 67560 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(67585), // Rule ID 1888 //
26106 /* 67565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26107 /* 67568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26108 /* 67571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26109 /* 67574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26110 /* 67578 */ // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26111 /* 67578 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26112 /* 67583 */ GIR_RootConstrainSelectedInstOperands,
26113 /* 67584 */ // GIR_Coverage, 1888,
26114 /* 67584 */ GIR_Done,
26115 /* 67585 */ // Label 1666: @67585
26116 /* 67585 */ GIM_Reject,
26117 /* 67586 */ // Label 1664: @67586
26118 /* 67586 */ GIM_Reject,
26119 /* 67587 */ // Label 63: @67587
26120 /* 67587 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1669*/ GIMT_Encode4(67658),
26121 /* 67598 */ /*GILLT_s32*//*Label 1667*/ GIMT_Encode4(67606),
26122 /* 67602 */ /*GILLT_s64*//*Label 1668*/ GIMT_Encode4(67632),
26123 /* 67606 */ // Label 1667: @67606
26124 /* 67606 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(67631), // Rule ID 1882 //
26125 /* 67611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26126 /* 67614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26127 /* 67617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26128 /* 67620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26129 /* 67624 */ // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26130 /* 67624 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
26131 /* 67629 */ GIR_RootConstrainSelectedInstOperands,
26132 /* 67630 */ // GIR_Coverage, 1882,
26133 /* 67630 */ GIR_Done,
26134 /* 67631 */ // Label 1670: @67631
26135 /* 67631 */ GIM_Reject,
26136 /* 67632 */ // Label 1668: @67632
26137 /* 67632 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(67657), // Rule ID 1884 //
26138 /* 67637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26139 /* 67640 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26140 /* 67643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26141 /* 67646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26142 /* 67650 */ // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26143 /* 67650 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
26144 /* 67655 */ GIR_RootConstrainSelectedInstOperands,
26145 /* 67656 */ // GIR_Coverage, 1884,
26146 /* 67656 */ GIR_Done,
26147 /* 67657 */ // Label 1671: @67657
26148 /* 67657 */ GIM_Reject,
26149 /* 67658 */ // Label 1669: @67658
26150 /* 67658 */ GIM_Reject,
26151 /* 67659 */ // Label 64: @67659
26152 /* 67659 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1674*/ GIMT_Encode4(67730),
26153 /* 67670 */ /*GILLT_s32*//*Label 1672*/ GIMT_Encode4(67678),
26154 /* 67674 */ /*GILLT_s64*//*Label 1673*/ GIMT_Encode4(67704),
26155 /* 67678 */ // Label 1672: @67678
26156 /* 67678 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(67703), // Rule ID 1885 //
26157 /* 67683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26158 /* 67686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26159 /* 67689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26160 /* 67692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26161 /* 67696 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26162 /* 67696 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26163 /* 67701 */ GIR_RootConstrainSelectedInstOperands,
26164 /* 67702 */ // GIR_Coverage, 1885,
26165 /* 67702 */ GIR_Done,
26166 /* 67703 */ // Label 1675: @67703
26167 /* 67703 */ GIM_Reject,
26168 /* 67704 */ // Label 1673: @67704
26169 /* 67704 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(67729), // Rule ID 1887 //
26170 /* 67709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26171 /* 67712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26172 /* 67715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26173 /* 67718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26174 /* 67722 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26175 /* 67722 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26176 /* 67727 */ GIR_RootConstrainSelectedInstOperands,
26177 /* 67728 */ // GIR_Coverage, 1887,
26178 /* 67728 */ GIR_Done,
26179 /* 67729 */ // Label 1676: @67729
26180 /* 67729 */ GIM_Reject,
26181 /* 67730 */ // Label 1674: @67730
26182 /* 67730 */ GIM_Reject,
26183 /* 67731 */ // Label 65: @67731
26184 /* 67731 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1679*/ GIMT_Encode4(67802),
26185 /* 67742 */ /*GILLT_s32*//*Label 1677*/ GIMT_Encode4(67750),
26186 /* 67746 */ /*GILLT_s64*//*Label 1678*/ GIMT_Encode4(67776),
26187 /* 67750 */ // Label 1677: @67750
26188 /* 67750 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(67775), // Rule ID 1881 //
26189 /* 67755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26190 /* 67758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26191 /* 67761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26192 /* 67764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26193 /* 67768 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26194 /* 67768 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
26195 /* 67773 */ GIR_RootConstrainSelectedInstOperands,
26196 /* 67774 */ // GIR_Coverage, 1881,
26197 /* 67774 */ GIR_Done,
26198 /* 67775 */ // Label 1680: @67775
26199 /* 67775 */ GIM_Reject,
26200 /* 67776 */ // Label 1678: @67776
26201 /* 67776 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(67801), // Rule ID 1883 //
26202 /* 67781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26203 /* 67784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26204 /* 67787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26205 /* 67790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26206 /* 67794 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26207 /* 67794 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
26208 /* 67799 */ GIR_RootConstrainSelectedInstOperands,
26209 /* 67800 */ // GIR_Coverage, 1883,
26210 /* 67800 */ GIR_Done,
26211 /* 67801 */ // Label 1681: @67801
26212 /* 67801 */ GIM_Reject,
26213 /* 67802 */ // Label 1679: @67802
26214 /* 67802 */ GIM_Reject,
26215 /* 67803 */ // Label 66: @67803
26216 /* 67803 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1686*/ GIMT_Encode4(67970),
26217 /* 67814 */ /*GILLT_v16s8*//*Label 1682*/ GIMT_Encode4(67834), GIMT_Encode4(0),
26218 /* 67822 */ /*GILLT_v8s16*//*Label 1683*/ GIMT_Encode4(67868),
26219 /* 67826 */ /*GILLT_v4s32*//*Label 1684*/ GIMT_Encode4(67902),
26220 /* 67830 */ /*GILLT_v2s64*//*Label 1685*/ GIMT_Encode4(67936),
26221 /* 67834 */ // Label 1682: @67834
26222 /* 67834 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(67867), // Rule ID 892 //
26223 /* 67839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26224 /* 67842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26225 /* 67845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26226 /* 67848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26227 /* 67852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26228 /* 67856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26229 /* 67860 */ // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26230 /* 67860 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
26231 /* 67865 */ GIR_RootConstrainSelectedInstOperands,
26232 /* 67866 */ // GIR_Coverage, 892,
26233 /* 67866 */ GIR_Done,
26234 /* 67867 */ // Label 1687: @67867
26235 /* 67867 */ GIM_Reject,
26236 /* 67868 */ // Label 1683: @67868
26237 /* 67868 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(67901), // Rule ID 893 //
26238 /* 67873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26239 /* 67876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26240 /* 67879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26241 /* 67882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26242 /* 67886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26243 /* 67890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26244 /* 67894 */ // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26245 /* 67894 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
26246 /* 67899 */ GIR_RootConstrainSelectedInstOperands,
26247 /* 67900 */ // GIR_Coverage, 893,
26248 /* 67900 */ GIR_Done,
26249 /* 67901 */ // Label 1688: @67901
26250 /* 67901 */ GIM_Reject,
26251 /* 67902 */ // Label 1684: @67902
26252 /* 67902 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(67935), // Rule ID 894 //
26253 /* 67907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26254 /* 67910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26255 /* 67913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26256 /* 67916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26257 /* 67920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26258 /* 67924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26259 /* 67928 */ // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26260 /* 67928 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
26261 /* 67933 */ GIR_RootConstrainSelectedInstOperands,
26262 /* 67934 */ // GIR_Coverage, 894,
26263 /* 67934 */ GIR_Done,
26264 /* 67935 */ // Label 1689: @67935
26265 /* 67935 */ GIM_Reject,
26266 /* 67936 */ // Label 1685: @67936
26267 /* 67936 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(67969), // Rule ID 895 //
26268 /* 67941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26269 /* 67944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26270 /* 67947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26271 /* 67950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26272 /* 67954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26273 /* 67958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26274 /* 67962 */ // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26275 /* 67962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
26276 /* 67967 */ GIR_RootConstrainSelectedInstOperands,
26277 /* 67968 */ // GIR_Coverage, 895,
26278 /* 67968 */ GIR_Done,
26279 /* 67969 */ // Label 1690: @67969
26280 /* 67969 */ GIM_Reject,
26281 /* 67970 */ // Label 1686: @67970
26282 /* 67970 */ GIM_Reject,
26283 /* 67971 */ // Label 67: @67971
26284 /* 67971 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1695*/ GIMT_Encode4(68138),
26285 /* 67982 */ /*GILLT_v16s8*//*Label 1691*/ GIMT_Encode4(68002), GIMT_Encode4(0),
26286 /* 67990 */ /*GILLT_v8s16*//*Label 1692*/ GIMT_Encode4(68036),
26287 /* 67994 */ /*GILLT_v4s32*//*Label 1693*/ GIMT_Encode4(68070),
26288 /* 67998 */ /*GILLT_v2s64*//*Label 1694*/ GIMT_Encode4(68104),
26289 /* 68002 */ // Label 1691: @68002
26290 /* 68002 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(68035), // Rule ID 872 //
26291 /* 68007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26292 /* 68010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26293 /* 68013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26294 /* 68016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26295 /* 68020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26296 /* 68024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26297 /* 68028 */ // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26298 /* 68028 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
26299 /* 68033 */ GIR_RootConstrainSelectedInstOperands,
26300 /* 68034 */ // GIR_Coverage, 872,
26301 /* 68034 */ GIR_Done,
26302 /* 68035 */ // Label 1696: @68035
26303 /* 68035 */ GIM_Reject,
26304 /* 68036 */ // Label 1692: @68036
26305 /* 68036 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(68069), // Rule ID 873 //
26306 /* 68041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26307 /* 68044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26308 /* 68047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26309 /* 68050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26310 /* 68054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26311 /* 68058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26312 /* 68062 */ // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26313 /* 68062 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
26314 /* 68067 */ GIR_RootConstrainSelectedInstOperands,
26315 /* 68068 */ // GIR_Coverage, 873,
26316 /* 68068 */ GIR_Done,
26317 /* 68069 */ // Label 1697: @68069
26318 /* 68069 */ GIM_Reject,
26319 /* 68070 */ // Label 1693: @68070
26320 /* 68070 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(68103), // Rule ID 874 //
26321 /* 68075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26322 /* 68078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26323 /* 68081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26324 /* 68084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26325 /* 68088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26326 /* 68092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26327 /* 68096 */ // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26328 /* 68096 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
26329 /* 68101 */ GIR_RootConstrainSelectedInstOperands,
26330 /* 68102 */ // GIR_Coverage, 874,
26331 /* 68102 */ GIR_Done,
26332 /* 68103 */ // Label 1698: @68103
26333 /* 68103 */ GIM_Reject,
26334 /* 68104 */ // Label 1694: @68104
26335 /* 68104 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(68137), // Rule ID 875 //
26336 /* 68109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26337 /* 68112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26338 /* 68115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26339 /* 68118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26340 /* 68122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26341 /* 68126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26342 /* 68130 */ // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26343 /* 68130 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
26344 /* 68135 */ GIR_RootConstrainSelectedInstOperands,
26345 /* 68136 */ // GIR_Coverage, 875,
26346 /* 68136 */ GIR_Done,
26347 /* 68137 */ // Label 1699: @68137
26348 /* 68137 */ GIM_Reject,
26349 /* 68138 */ // Label 1695: @68138
26350 /* 68138 */ GIM_Reject,
26351 /* 68139 */ // Label 68: @68139
26352 /* 68139 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1704*/ GIMT_Encode4(68306),
26353 /* 68150 */ /*GILLT_v16s8*//*Label 1700*/ GIMT_Encode4(68170), GIMT_Encode4(0),
26354 /* 68158 */ /*GILLT_v8s16*//*Label 1701*/ GIMT_Encode4(68204),
26355 /* 68162 */ /*GILLT_v4s32*//*Label 1702*/ GIMT_Encode4(68238),
26356 /* 68166 */ /*GILLT_v2s64*//*Label 1703*/ GIMT_Encode4(68272),
26357 /* 68170 */ // Label 1700: @68170
26358 /* 68170 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(68203), // Rule ID 896 //
26359 /* 68175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26360 /* 68178 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26361 /* 68181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26362 /* 68184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26363 /* 68188 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26364 /* 68192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26365 /* 68196 */ // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26366 /* 68196 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
26367 /* 68201 */ GIR_RootConstrainSelectedInstOperands,
26368 /* 68202 */ // GIR_Coverage, 896,
26369 /* 68202 */ GIR_Done,
26370 /* 68203 */ // Label 1705: @68203
26371 /* 68203 */ GIM_Reject,
26372 /* 68204 */ // Label 1701: @68204
26373 /* 68204 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(68237), // Rule ID 897 //
26374 /* 68209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26375 /* 68212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26376 /* 68215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26377 /* 68218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26378 /* 68222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26379 /* 68226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26380 /* 68230 */ // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26381 /* 68230 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
26382 /* 68235 */ GIR_RootConstrainSelectedInstOperands,
26383 /* 68236 */ // GIR_Coverage, 897,
26384 /* 68236 */ GIR_Done,
26385 /* 68237 */ // Label 1706: @68237
26386 /* 68237 */ GIM_Reject,
26387 /* 68238 */ // Label 1702: @68238
26388 /* 68238 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(68271), // Rule ID 898 //
26389 /* 68243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26390 /* 68246 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26391 /* 68249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26392 /* 68252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26393 /* 68256 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26394 /* 68260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26395 /* 68264 */ // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26396 /* 68264 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
26397 /* 68269 */ GIR_RootConstrainSelectedInstOperands,
26398 /* 68270 */ // GIR_Coverage, 898,
26399 /* 68270 */ GIR_Done,
26400 /* 68271 */ // Label 1707: @68271
26401 /* 68271 */ GIM_Reject,
26402 /* 68272 */ // Label 1703: @68272
26403 /* 68272 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(68305), // Rule ID 899 //
26404 /* 68277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26405 /* 68280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26406 /* 68283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26407 /* 68286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26408 /* 68290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26409 /* 68294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26410 /* 68298 */ // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26411 /* 68298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
26412 /* 68303 */ GIR_RootConstrainSelectedInstOperands,
26413 /* 68304 */ // GIR_Coverage, 899,
26414 /* 68304 */ GIR_Done,
26415 /* 68305 */ // Label 1708: @68305
26416 /* 68305 */ GIM_Reject,
26417 /* 68306 */ // Label 1704: @68306
26418 /* 68306 */ GIM_Reject,
26419 /* 68307 */ // Label 69: @68307
26420 /* 68307 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1713*/ GIMT_Encode4(68474),
26421 /* 68318 */ /*GILLT_v16s8*//*Label 1709*/ GIMT_Encode4(68338), GIMT_Encode4(0),
26422 /* 68326 */ /*GILLT_v8s16*//*Label 1710*/ GIMT_Encode4(68372),
26423 /* 68330 */ /*GILLT_v4s32*//*Label 1711*/ GIMT_Encode4(68406),
26424 /* 68334 */ /*GILLT_v2s64*//*Label 1712*/ GIMT_Encode4(68440),
26425 /* 68338 */ // Label 1709: @68338
26426 /* 68338 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(68371), // Rule ID 876 //
26427 /* 68343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26428 /* 68346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26429 /* 68349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26430 /* 68352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26431 /* 68356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26432 /* 68360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26433 /* 68364 */ // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26434 /* 68364 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
26435 /* 68369 */ GIR_RootConstrainSelectedInstOperands,
26436 /* 68370 */ // GIR_Coverage, 876,
26437 /* 68370 */ GIR_Done,
26438 /* 68371 */ // Label 1714: @68371
26439 /* 68371 */ GIM_Reject,
26440 /* 68372 */ // Label 1710: @68372
26441 /* 68372 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(68405), // Rule ID 877 //
26442 /* 68377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26443 /* 68380 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26444 /* 68383 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26445 /* 68386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26446 /* 68390 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26447 /* 68394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26448 /* 68398 */ // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26449 /* 68398 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
26450 /* 68403 */ GIR_RootConstrainSelectedInstOperands,
26451 /* 68404 */ // GIR_Coverage, 877,
26452 /* 68404 */ GIR_Done,
26453 /* 68405 */ // Label 1715: @68405
26454 /* 68405 */ GIM_Reject,
26455 /* 68406 */ // Label 1711: @68406
26456 /* 68406 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(68439), // Rule ID 878 //
26457 /* 68411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26458 /* 68414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26459 /* 68417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26460 /* 68420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26461 /* 68424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26462 /* 68428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26463 /* 68432 */ // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26464 /* 68432 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
26465 /* 68437 */ GIR_RootConstrainSelectedInstOperands,
26466 /* 68438 */ // GIR_Coverage, 878,
26467 /* 68438 */ GIR_Done,
26468 /* 68439 */ // Label 1716: @68439
26469 /* 68439 */ GIM_Reject,
26470 /* 68440 */ // Label 1712: @68440
26471 /* 68440 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(68473), // Rule ID 879 //
26472 /* 68445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26473 /* 68448 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26474 /* 68451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26475 /* 68454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26476 /* 68458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26477 /* 68462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26478 /* 68466 */ // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26479 /* 68466 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
26480 /* 68471 */ GIR_RootConstrainSelectedInstOperands,
26481 /* 68472 */ // GIR_Coverage, 879,
26482 /* 68472 */ GIR_Done,
26483 /* 68473 */ // Label 1717: @68473
26484 /* 68473 */ GIM_Reject,
26485 /* 68474 */ // Label 1713: @68474
26486 /* 68474 */ GIM_Reject,
26487 /* 68475 */ // Label 70: @68475
26488 /* 68475 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(68598),
26489 /* 68480 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
26490 /* 68483 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(68504), // Rule ID 91 //
26491 /* 68488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC),
26492 /* 68491 */ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
26493 /* 68491 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
26494 /* 68496 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26495 /* 68502 */ GIR_RootConstrainSelectedInstOperands,
26496 /* 68503 */ // GIR_Coverage, 91,
26497 /* 68503 */ GIR_Done,
26498 /* 68504 */ // Label 1719: @68504
26499 /* 68504 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(68525), // Rule ID 98 //
26500 /* 68509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
26501 /* 68512 */ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
26502 /* 68512 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
26503 /* 68517 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26504 /* 68523 */ GIR_RootConstrainSelectedInstOperands,
26505 /* 68524 */ // GIR_Coverage, 98,
26506 /* 68524 */ GIR_Done,
26507 /* 68525 */ // Label 1720: @68525
26508 /* 68525 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(68546), // Rule ID 1128 //
26509 /* 68530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC),
26510 /* 68533 */ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
26511 /* 68533 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
26512 /* 68538 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26513 /* 68544 */ GIR_RootConstrainSelectedInstOperands,
26514 /* 68545 */ // GIR_Coverage, 1128,
26515 /* 68545 */ GIR_Done,
26516 /* 68546 */ // Label 1721: @68546
26517 /* 68546 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(68567), // Rule ID 1137 //
26518 /* 68551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC),
26519 /* 68554 */ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
26520 /* 68554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
26521 /* 68559 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26522 /* 68565 */ GIR_RootConstrainSelectedInstOperands,
26523 /* 68566 */ // GIR_Coverage, 1137,
26524 /* 68566 */ GIR_Done,
26525 /* 68567 */ // Label 1722: @68567
26526 /* 68567 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(68582), // Rule ID 1194 //
26527 /* 68572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
26528 /* 68575 */ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
26529 /* 68575 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
26530 /* 68580 */ GIR_RootConstrainSelectedInstOperands,
26531 /* 68581 */ // GIR_Coverage, 1194,
26532 /* 68581 */ GIR_Done,
26533 /* 68582 */ // Label 1723: @68582
26534 /* 68582 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(68597), // Rule ID 1994 //
26535 /* 68587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
26536 /* 68590 */ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
26537 /* 68590 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
26538 /* 68595 */ GIR_RootConstrainSelectedInstOperands,
26539 /* 68596 */ // GIR_Coverage, 1994,
26540 /* 68596 */ GIR_Done,
26541 /* 68597 */ // Label 1724: @68597
26542 /* 68597 */ GIM_Reject,
26543 /* 68598 */ // Label 1718: @68598
26544 /* 68598 */ GIM_Reject,
26545 /* 68599 */ // Label 71: @68599
26546 /* 68599 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1729*/ GIMT_Encode4(69162),
26547 /* 68610 */ /*GILLT_v16s8*//*Label 1725*/ GIMT_Encode4(68630), GIMT_Encode4(0),
26548 /* 68618 */ /*GILLT_v8s16*//*Label 1726*/ GIMT_Encode4(68723),
26549 /* 68622 */ /*GILLT_v4s32*//*Label 1727*/ GIMT_Encode4(68816),
26550 /* 68626 */ /*GILLT_v2s64*//*Label 1728*/ GIMT_Encode4(68989),
26551 /* 68630 */ // Label 1725: @68630
26552 /* 68630 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(68722),
26553 /* 68635 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26554 /* 68638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26555 /* 68641 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(68681), // Rule ID 842 //
26556 /* 68646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26557 /* 68649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26558 /* 68652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26559 /* 68656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26560 /* 68660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26561 /* 68664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26562 /* 68668 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26563 /* 68668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
26564 /* 68671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26565 /* 68673 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26566 /* 68675 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26567 /* 68677 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26568 /* 68679 */ GIR_RootConstrainSelectedInstOperands,
26569 /* 68680 */ // GIR_Coverage, 842,
26570 /* 68680 */ GIR_EraseRootFromParent_Done,
26571 /* 68681 */ // Label 1731: @68681
26572 /* 68681 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(68721), // Rule ID 848 //
26573 /* 68686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26574 /* 68689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26575 /* 68692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26576 /* 68696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26577 /* 68700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26578 /* 68704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26579 /* 68708 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26580 /* 68708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
26581 /* 68711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26582 /* 68713 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26583 /* 68715 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26584 /* 68717 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26585 /* 68719 */ GIR_RootConstrainSelectedInstOperands,
26586 /* 68720 */ // GIR_Coverage, 848,
26587 /* 68720 */ GIR_EraseRootFromParent_Done,
26588 /* 68721 */ // Label 1732: @68721
26589 /* 68721 */ GIM_Reject,
26590 /* 68722 */ // Label 1730: @68722
26591 /* 68722 */ GIM_Reject,
26592 /* 68723 */ // Label 1726: @68723
26593 /* 68723 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(68815),
26594 /* 68728 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26595 /* 68731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26596 /* 68734 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(68774), // Rule ID 843 //
26597 /* 68739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26598 /* 68742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26599 /* 68745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26600 /* 68749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26601 /* 68753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26602 /* 68757 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26603 /* 68761 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26604 /* 68761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
26605 /* 68764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26606 /* 68766 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26607 /* 68768 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26608 /* 68770 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26609 /* 68772 */ GIR_RootConstrainSelectedInstOperands,
26610 /* 68773 */ // GIR_Coverage, 843,
26611 /* 68773 */ GIR_EraseRootFromParent_Done,
26612 /* 68774 */ // Label 1734: @68774
26613 /* 68774 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(68814), // Rule ID 849 //
26614 /* 68779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26615 /* 68782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26616 /* 68785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26617 /* 68789 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26618 /* 68793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26619 /* 68797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26620 /* 68801 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26621 /* 68801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
26622 /* 68804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26623 /* 68806 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26624 /* 68808 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26625 /* 68810 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26626 /* 68812 */ GIR_RootConstrainSelectedInstOperands,
26627 /* 68813 */ // GIR_Coverage, 849,
26628 /* 68813 */ GIR_EraseRootFromParent_Done,
26629 /* 68814 */ // Label 1735: @68814
26630 /* 68814 */ GIM_Reject,
26631 /* 68815 */ // Label 1733: @68815
26632 /* 68815 */ GIM_Reject,
26633 /* 68816 */ // Label 1727: @68816
26634 /* 68816 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(68988),
26635 /* 68821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26636 /* 68824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26637 /* 68827 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(68867), // Rule ID 844 //
26638 /* 68832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26639 /* 68835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26640 /* 68838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26641 /* 68842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26642 /* 68846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26643 /* 68850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26644 /* 68854 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26645 /* 68854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
26646 /* 68857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26647 /* 68859 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26648 /* 68861 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26649 /* 68863 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26650 /* 68865 */ GIR_RootConstrainSelectedInstOperands,
26651 /* 68866 */ // GIR_Coverage, 844,
26652 /* 68866 */ GIR_EraseRootFromParent_Done,
26653 /* 68867 */ // Label 1737: @68867
26654 /* 68867 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(68907), // Rule ID 846 //
26655 /* 68872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26656 /* 68875 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26657 /* 68878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26658 /* 68882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26659 /* 68886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26660 /* 68890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26661 /* 68894 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26662 /* 68894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
26663 /* 68897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26664 /* 68899 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26665 /* 68901 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26666 /* 68903 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26667 /* 68905 */ GIR_RootConstrainSelectedInstOperands,
26668 /* 68906 */ // GIR_Coverage, 846,
26669 /* 68906 */ GIR_EraseRootFromParent_Done,
26670 /* 68907 */ // Label 1738: @68907
26671 /* 68907 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(68947), // Rule ID 850 //
26672 /* 68912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26673 /* 68915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26674 /* 68918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26675 /* 68922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26676 /* 68926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26677 /* 68930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26678 /* 68934 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26679 /* 68934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
26680 /* 68937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26681 /* 68939 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26682 /* 68941 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26683 /* 68943 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26684 /* 68945 */ GIR_RootConstrainSelectedInstOperands,
26685 /* 68946 */ // GIR_Coverage, 850,
26686 /* 68946 */ GIR_EraseRootFromParent_Done,
26687 /* 68947 */ // Label 1739: @68947
26688 /* 68947 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(68987), // Rule ID 852 //
26689 /* 68952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26690 /* 68955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26691 /* 68958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26692 /* 68962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26693 /* 68966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26694 /* 68970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26695 /* 68974 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26696 /* 68974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
26697 /* 68977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26698 /* 68979 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26699 /* 68981 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26700 /* 68983 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26701 /* 68985 */ GIR_RootConstrainSelectedInstOperands,
26702 /* 68986 */ // GIR_Coverage, 852,
26703 /* 68986 */ GIR_EraseRootFromParent_Done,
26704 /* 68987 */ // Label 1740: @68987
26705 /* 68987 */ GIM_Reject,
26706 /* 68988 */ // Label 1736: @68988
26707 /* 68988 */ GIM_Reject,
26708 /* 68989 */ // Label 1728: @68989
26709 /* 68989 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(69161),
26710 /* 68994 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26711 /* 68997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26712 /* 69000 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(69040), // Rule ID 845 //
26713 /* 69005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26714 /* 69008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26715 /* 69011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26716 /* 69015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26717 /* 69019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26718 /* 69023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26719 /* 69027 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26720 /* 69027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
26721 /* 69030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26722 /* 69032 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26723 /* 69034 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26724 /* 69036 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26725 /* 69038 */ GIR_RootConstrainSelectedInstOperands,
26726 /* 69039 */ // GIR_Coverage, 845,
26727 /* 69039 */ GIR_EraseRootFromParent_Done,
26728 /* 69040 */ // Label 1742: @69040
26729 /* 69040 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(69080), // Rule ID 847 //
26730 /* 69045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26731 /* 69048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26732 /* 69051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26733 /* 69055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26734 /* 69059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26735 /* 69063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26736 /* 69067 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26737 /* 69067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
26738 /* 69070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26739 /* 69072 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26740 /* 69074 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26741 /* 69076 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26742 /* 69078 */ GIR_RootConstrainSelectedInstOperands,
26743 /* 69079 */ // GIR_Coverage, 847,
26744 /* 69079 */ GIR_EraseRootFromParent_Done,
26745 /* 69080 */ // Label 1743: @69080
26746 /* 69080 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(69120), // Rule ID 851 //
26747 /* 69085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26748 /* 69088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26749 /* 69091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26750 /* 69095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26751 /* 69099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26752 /* 69103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26753 /* 69107 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26754 /* 69107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
26755 /* 69110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26756 /* 69112 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26757 /* 69114 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26758 /* 69116 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26759 /* 69118 */ GIR_RootConstrainSelectedInstOperands,
26760 /* 69119 */ // GIR_Coverage, 851,
26761 /* 69119 */ GIR_EraseRootFromParent_Done,
26762 /* 69120 */ // Label 1744: @69120
26763 /* 69120 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(69160), // Rule ID 853 //
26764 /* 69125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26765 /* 69128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26766 /* 69131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26767 /* 69135 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26768 /* 69139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26769 /* 69143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26770 /* 69147 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26771 /* 69147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
26772 /* 69150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26773 /* 69152 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26774 /* 69154 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26775 /* 69156 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26776 /* 69158 */ GIR_RootConstrainSelectedInstOperands,
26777 /* 69159 */ // GIR_Coverage, 853,
26778 /* 69159 */ GIR_EraseRootFromParent_Done,
26779 /* 69160 */ // Label 1745: @69160
26780 /* 69160 */ GIM_Reject,
26781 /* 69161 */ // Label 1741: @69161
26782 /* 69161 */ GIM_Reject,
26783 /* 69162 */ // Label 1729: @69162
26784 /* 69162 */ GIM_Reject,
26785 /* 69163 */ // Label 72: @69163
26786 /* 69163 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(69214), // Rule ID 2121 //
26787 /* 69168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
26788 /* 69171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26789 /* 69174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26790 /* 69177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26791 /* 69180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26792 /* 69184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26793 /* 69188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26794 /* 69192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26795 /* 69196 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
26796 /* 69200 */ // MIs[1] Operand 1
26797 /* 69200 */ // No operand predicates
26798 /* 69200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26799 /* 69202 */ // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
26800 /* 69202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
26801 /* 69205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26802 /* 69207 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
26803 /* 69209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
26804 /* 69212 */ GIR_RootConstrainSelectedInstOperands,
26805 /* 69213 */ // GIR_Coverage, 2121,
26806 /* 69213 */ GIR_EraseRootFromParent_Done,
26807 /* 69214 */ // Label 1746: @69214
26808 /* 69214 */ GIM_Reject,
26809 /* 69215 */ // Label 73: @69215
26810 /* 69215 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1753*/ GIMT_Encode4(69719),
26811 /* 69226 */ /*GILLT_s32*//*Label 1747*/ GIMT_Encode4(69258),
26812 /* 69230 */ /*GILLT_s64*//*Label 1748*/ GIMT_Encode4(69467), GIMT_Encode4(0),
26813 /* 69238 */ /*GILLT_v16s8*//*Label 1749*/ GIMT_Encode4(69611), GIMT_Encode4(0),
26814 /* 69246 */ /*GILLT_v8s16*//*Label 1750*/ GIMT_Encode4(69638),
26815 /* 69250 */ /*GILLT_v4s32*//*Label 1751*/ GIMT_Encode4(69665),
26816 /* 69254 */ /*GILLT_v2s64*//*Label 1752*/ GIMT_Encode4(69692),
26817 /* 69258 */ // Label 1747: @69258
26818 /* 69258 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(69466),
26819 /* 69263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26820 /* 69266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26821 /* 69270 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(69316), // Rule ID 109 //
26822 /* 69275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26823 /* 69278 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26824 /* 69282 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26825 /* 69286 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26826 /* 69290 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26827 /* 69294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26828 /* 69299 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26829 /* 69303 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26830 /* 69305 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26831 /* 69305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
26832 /* 69308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26833 /* 69310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26834 /* 69314 */ GIR_RootConstrainSelectedInstOperands,
26835 /* 69315 */ // GIR_Coverage, 109,
26836 /* 69315 */ GIR_EraseRootFromParent_Done,
26837 /* 69316 */ // Label 1755: @69316
26838 /* 69316 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(69362), // Rule ID 334 //
26839 /* 69321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26840 /* 69324 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26841 /* 69328 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26842 /* 69332 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26843 /* 69336 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26844 /* 69340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26845 /* 69345 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26846 /* 69349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26847 /* 69351 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26848 /* 69351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
26849 /* 69354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26850 /* 69356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26851 /* 69360 */ GIR_RootConstrainSelectedInstOperands,
26852 /* 69361 */ // GIR_Coverage, 334,
26853 /* 69361 */ GIR_EraseRootFromParent_Done,
26854 /* 69362 */ // Label 1756: @69362
26855 /* 69362 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(69408), // Rule ID 1124 //
26856 /* 69367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26857 /* 69370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26858 /* 69374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26859 /* 69378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26860 /* 69382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26861 /* 69386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26862 /* 69391 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26863 /* 69395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26864 /* 69397 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26865 /* 69397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
26866 /* 69400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26867 /* 69402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26868 /* 69406 */ GIR_RootConstrainSelectedInstOperands,
26869 /* 69407 */ // GIR_Coverage, 1124,
26870 /* 69407 */ GIR_EraseRootFromParent_Done,
26871 /* 69408 */ // Label 1757: @69408
26872 /* 69408 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(69427), // Rule ID 108 //
26873 /* 69413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26874 /* 69416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26875 /* 69420 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26876 /* 69420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
26877 /* 69425 */ GIR_RootConstrainSelectedInstOperands,
26878 /* 69426 */ // GIR_Coverage, 108,
26879 /* 69426 */ GIR_Done,
26880 /* 69427 */ // Label 1758: @69427
26881 /* 69427 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(69446), // Rule ID 335 //
26882 /* 69432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26883 /* 69435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26884 /* 69439 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26885 /* 69439 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
26886 /* 69444 */ GIR_RootConstrainSelectedInstOperands,
26887 /* 69445 */ // GIR_Coverage, 335,
26888 /* 69445 */ GIR_Done,
26889 /* 69446 */ // Label 1759: @69446
26890 /* 69446 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(69465), // Rule ID 1123 //
26891 /* 69451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26892 /* 69454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26893 /* 69458 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26894 /* 69458 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
26895 /* 69463 */ GIR_RootConstrainSelectedInstOperands,
26896 /* 69464 */ // GIR_Coverage, 1123,
26897 /* 69464 */ GIR_Done,
26898 /* 69465 */ // Label 1760: @69465
26899 /* 69465 */ GIM_Reject,
26900 /* 69466 */ // Label 1754: @69466
26901 /* 69466 */ GIM_Reject,
26902 /* 69467 */ // Label 1748: @69467
26903 /* 69467 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(69610),
26904 /* 69472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26905 /* 69475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26906 /* 69479 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(69525), // Rule ID 288 //
26907 /* 69484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26908 /* 69487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26909 /* 69491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26910 /* 69495 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26911 /* 69499 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26912 /* 69503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26913 /* 69508 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26914 /* 69512 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26915 /* 69514 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26916 /* 69514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
26917 /* 69517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26918 /* 69519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26919 /* 69523 */ GIR_RootConstrainSelectedInstOperands,
26920 /* 69524 */ // GIR_Coverage, 288,
26921 /* 69524 */ GIR_EraseRootFromParent_Done,
26922 /* 69525 */ // Label 1762: @69525
26923 /* 69525 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(69571), // Rule ID 363 //
26924 /* 69530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26925 /* 69533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26926 /* 69537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26927 /* 69541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26928 /* 69545 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26929 /* 69549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26930 /* 69554 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26931 /* 69558 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26932 /* 69560 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26933 /* 69560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
26934 /* 69563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26935 /* 69565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26936 /* 69569 */ GIR_RootConstrainSelectedInstOperands,
26937 /* 69570 */ // GIR_Coverage, 363,
26938 /* 69570 */ GIR_EraseRootFromParent_Done,
26939 /* 69571 */ // Label 1763: @69571
26940 /* 69571 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(69590), // Rule ID 287 //
26941 /* 69576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26942 /* 69579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26943 /* 69583 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26944 /* 69583 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
26945 /* 69588 */ GIR_RootConstrainSelectedInstOperands,
26946 /* 69589 */ // GIR_Coverage, 287,
26947 /* 69589 */ GIR_Done,
26948 /* 69590 */ // Label 1764: @69590
26949 /* 69590 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(69609), // Rule ID 364 //
26950 /* 69595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26951 /* 69598 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26952 /* 69602 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26953 /* 69602 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
26954 /* 69607 */ GIR_RootConstrainSelectedInstOperands,
26955 /* 69608 */ // GIR_Coverage, 364,
26956 /* 69608 */ GIR_Done,
26957 /* 69609 */ // Label 1765: @69609
26958 /* 69609 */ GIM_Reject,
26959 /* 69610 */ // Label 1761: @69610
26960 /* 69610 */ GIM_Reject,
26961 /* 69611 */ // Label 1749: @69611
26962 /* 69611 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(69637), // Rule ID 936 //
26963 /* 69616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26964 /* 69619 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26965 /* 69622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26966 /* 69626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26967 /* 69630 */ // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
26968 /* 69630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
26969 /* 69635 */ GIR_RootConstrainSelectedInstOperands,
26970 /* 69636 */ // GIR_Coverage, 936,
26971 /* 69636 */ GIR_Done,
26972 /* 69637 */ // Label 1766: @69637
26973 /* 69637 */ GIM_Reject,
26974 /* 69638 */ // Label 1750: @69638
26975 /* 69638 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(69664), // Rule ID 937 //
26976 /* 69643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26977 /* 69646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26978 /* 69649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26979 /* 69653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26980 /* 69657 */ // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
26981 /* 69657 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
26982 /* 69662 */ GIR_RootConstrainSelectedInstOperands,
26983 /* 69663 */ // GIR_Coverage, 937,
26984 /* 69663 */ GIR_Done,
26985 /* 69664 */ // Label 1767: @69664
26986 /* 69664 */ GIM_Reject,
26987 /* 69665 */ // Label 1751: @69665
26988 /* 69665 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(69691), // Rule ID 938 //
26989 /* 69670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26990 /* 69673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26991 /* 69676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26992 /* 69680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26993 /* 69684 */ // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
26994 /* 69684 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
26995 /* 69689 */ GIR_RootConstrainSelectedInstOperands,
26996 /* 69690 */ // GIR_Coverage, 938,
26997 /* 69690 */ GIR_Done,
26998 /* 69691 */ // Label 1768: @69691
26999 /* 69691 */ GIM_Reject,
27000 /* 69692 */ // Label 1752: @69692
27001 /* 69692 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(69718), // Rule ID 939 //
27002 /* 69697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27003 /* 69700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27004 /* 69703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27005 /* 69707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27006 /* 69711 */ // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
27007 /* 69711 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
27008 /* 69716 */ GIR_RootConstrainSelectedInstOperands,
27009 /* 69717 */ // GIR_Coverage, 939,
27010 /* 69717 */ GIR_Done,
27011 /* 69718 */ // Label 1769: @69718
27012 /* 69718 */ GIM_Reject,
27013 /* 69719 */ // Label 1753: @69719
27014 /* 69719 */ GIM_Reject,
27015 /* 69720 */ // Label 74: @69720
27016 /* 69720 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1776*/ GIMT_Encode4(69925),
27017 /* 69731 */ /*GILLT_s32*//*Label 1770*/ GIMT_Encode4(69763),
27018 /* 69735 */ /*GILLT_s64*//*Label 1771*/ GIMT_Encode4(69790), GIMT_Encode4(0),
27019 /* 69743 */ /*GILLT_v16s8*//*Label 1772*/ GIMT_Encode4(69817), GIMT_Encode4(0),
27020 /* 69751 */ /*GILLT_v8s16*//*Label 1773*/ GIMT_Encode4(69844),
27021 /* 69755 */ /*GILLT_v4s32*//*Label 1774*/ GIMT_Encode4(69871),
27022 /* 69759 */ /*GILLT_v2s64*//*Label 1775*/ GIMT_Encode4(69898),
27023 /* 69763 */ // Label 1770: @69763
27024 /* 69763 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(69789), // Rule ID 302 //
27025 /* 69768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
27026 /* 69771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27027 /* 69774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27028 /* 69778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27029 /* 69782 */ // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
27030 /* 69782 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
27031 /* 69787 */ GIR_RootConstrainSelectedInstOperands,
27032 /* 69788 */ // GIR_Coverage, 302,
27033 /* 69788 */ GIR_Done,
27034 /* 69789 */ // Label 1777: @69789
27035 /* 69789 */ GIM_Reject,
27036 /* 69790 */ // Label 1771: @69790
27037 /* 69790 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(69816), // Rule ID 303 //
27038 /* 69795 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
27039 /* 69798 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27040 /* 69801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27041 /* 69805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27042 /* 69809 */ // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
27043 /* 69809 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
27044 /* 69814 */ GIR_RootConstrainSelectedInstOperands,
27045 /* 69815 */ // GIR_Coverage, 303,
27046 /* 69815 */ GIR_Done,
27047 /* 69816 */ // Label 1778: @69816
27048 /* 69816 */ GIM_Reject,
27049 /* 69817 */ // Label 1772: @69817
27050 /* 69817 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(69843), // Rule ID 958 //
27051 /* 69822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27052 /* 69825 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
27053 /* 69828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
27054 /* 69832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
27055 /* 69836 */ // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
27056 /* 69836 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
27057 /* 69841 */ GIR_RootConstrainSelectedInstOperands,
27058 /* 69842 */ // GIR_Coverage, 958,
27059 /* 69842 */ GIR_Done,
27060 /* 69843 */ // Label 1779: @69843
27061 /* 69843 */ GIM_Reject,
27062 /* 69844 */ // Label 1773: @69844
27063 /* 69844 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(69870), // Rule ID 959 //
27064 /* 69849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27065 /* 69852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
27066 /* 69855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
27067 /* 69859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
27068 /* 69863 */ // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
27069 /* 69863 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
27070 /* 69868 */ GIR_RootConstrainSelectedInstOperands,
27071 /* 69869 */ // GIR_Coverage, 959,
27072 /* 69869 */ GIR_Done,
27073 /* 69870 */ // Label 1780: @69870
27074 /* 69870 */ GIM_Reject,
27075 /* 69871 */ // Label 1774: @69871
27076 /* 69871 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(69897), // Rule ID 960 //
27077 /* 69876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27078 /* 69879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27079 /* 69882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27080 /* 69886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27081 /* 69890 */ // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
27082 /* 69890 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
27083 /* 69895 */ GIR_RootConstrainSelectedInstOperands,
27084 /* 69896 */ // GIR_Coverage, 960,
27085 /* 69896 */ GIR_Done,
27086 /* 69897 */ // Label 1781: @69897
27087 /* 69897 */ GIM_Reject,
27088 /* 69898 */ // Label 1775: @69898
27089 /* 69898 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(69924), // Rule ID 961 //
27090 /* 69903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27091 /* 69906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27092 /* 69909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27093 /* 69913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27094 /* 69917 */ // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
27095 /* 69917 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
27096 /* 69922 */ GIR_RootConstrainSelectedInstOperands,
27097 /* 69923 */ // GIR_Coverage, 961,
27098 /* 69923 */ GIR_Done,
27099 /* 69924 */ // Label 1782: @69924
27100 /* 69924 */ GIM_Reject,
27101 /* 69925 */ // Label 1776: @69925
27102 /* 69925 */ GIM_Reject,
27103 /* 69926 */ // Label 75: @69926
27104 /* 69926 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1785*/ GIMT_Encode4(70089),
27105 /* 69937 */ /*GILLT_s32*//*Label 1783*/ GIMT_Encode4(69945),
27106 /* 69941 */ /*GILLT_s64*//*Label 1784*/ GIMT_Encode4(70041),
27107 /* 69945 */ // Label 1783: @69945
27108 /* 69945 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(70040),
27109 /* 69950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27110 /* 69953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27111 /* 69957 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27112 /* 69961 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(70000), // Rule ID 1450 //
27113 /* 69966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
27114 /* 69969 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
27115 /* 69969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27116 /* 69972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
27117 /* 69976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27118 /* 69981 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27119 /* 69985 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27120 /* 69987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
27121 /* 69990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27122 /* 69992 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27123 /* 69995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
27124 /* 69998 */ GIR_RootConstrainSelectedInstOperands,
27125 /* 69999 */ // GIR_Coverage, 1450,
27126 /* 69999 */ GIR_EraseRootFromParent_Done,
27127 /* 70000 */ // Label 1787: @70000
27128 /* 70000 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(70039), // Rule ID 2318 //
27129 /* 70005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
27130 /* 70008 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
27131 /* 70008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27132 /* 70011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
27133 /* 70015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27134 /* 70020 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27135 /* 70024 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27136 /* 70026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
27137 /* 70029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27138 /* 70031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27139 /* 70034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
27140 /* 70037 */ GIR_RootConstrainSelectedInstOperands,
27141 /* 70038 */ // GIR_Coverage, 2318,
27142 /* 70038 */ GIR_EraseRootFromParent_Done,
27143 /* 70039 */ // Label 1788: @70039
27144 /* 70039 */ GIM_Reject,
27145 /* 70040 */ // Label 1786: @70040
27146 /* 70040 */ GIM_Reject,
27147 /* 70041 */ // Label 1784: @70041
27148 /* 70041 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(70088), // Rule ID 1692 //
27149 /* 70046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc),
27150 /* 70049 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27151 /* 70052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27152 /* 70056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27153 /* 70060 */ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
27154 /* 70060 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
27155 /* 70063 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
27156 /* 70067 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27157 /* 70072 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27158 /* 70076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27159 /* 70078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
27160 /* 70081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27161 /* 70083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27162 /* 70086 */ GIR_RootConstrainSelectedInstOperands,
27163 /* 70087 */ // GIR_Coverage, 1692,
27164 /* 70087 */ GIR_EraseRootFromParent_Done,
27165 /* 70088 */ // Label 1789: @70088
27166 /* 70088 */ GIM_Reject,
27167 /* 70089 */ // Label 1785: @70089
27168 /* 70089 */ GIM_Reject,
27169 /* 70090 */ // Label 76: @70090
27170 /* 70090 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1794*/ GIMT_Encode4(70361),
27171 /* 70101 */ /*GILLT_s32*//*Label 1790*/ GIMT_Encode4(70133),
27172 /* 70105 */ /*GILLT_s64*//*Label 1791*/ GIMT_Encode4(70189), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
27173 /* 70125 */ /*GILLT_v4s32*//*Label 1792*/ GIMT_Encode4(70307),
27174 /* 70129 */ /*GILLT_v2s64*//*Label 1793*/ GIMT_Encode4(70334),
27175 /* 70133 */ // Label 1790: @70133
27176 /* 70133 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(70188),
27177 /* 70138 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27178 /* 70141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27179 /* 70145 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27180 /* 70149 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(70168), // Rule ID 130 //
27181 /* 70154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27182 /* 70157 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27183 /* 70157 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
27184 /* 70162 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27185 /* 70166 */ GIR_RootConstrainSelectedInstOperands,
27186 /* 70167 */ // GIR_Coverage, 130,
27187 /* 70167 */ GIR_Done,
27188 /* 70168 */ // Label 1796: @70168
27189 /* 70168 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(70187), // Rule ID 1185 //
27190 /* 70173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
27191 /* 70176 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27192 /* 70176 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
27193 /* 70181 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27194 /* 70185 */ GIR_RootConstrainSelectedInstOperands,
27195 /* 70186 */ // GIR_Coverage, 1185,
27196 /* 70186 */ GIR_Done,
27197 /* 70187 */ // Label 1797: @70187
27198 /* 70187 */ GIM_Reject,
27199 /* 70188 */ // Label 1795: @70188
27200 /* 70188 */ GIM_Reject,
27201 /* 70189 */ // Label 1791: @70189
27202 /* 70189 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(70306),
27203 /* 70194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27204 /* 70197 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(70224), // Rule ID 132 //
27205 /* 70202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27206 /* 70205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27207 /* 70209 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27208 /* 70213 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27209 /* 70213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
27210 /* 70218 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27211 /* 70222 */ GIR_RootConstrainSelectedInstOperands,
27212 /* 70223 */ // GIR_Coverage, 132,
27213 /* 70223 */ GIR_Done,
27214 /* 70224 */ // Label 1799: @70224
27215 /* 70224 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(70251), // Rule ID 134 //
27216 /* 70229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27217 /* 70232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27218 /* 70236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27219 /* 70240 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27220 /* 70240 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
27221 /* 70245 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27222 /* 70249 */ GIR_RootConstrainSelectedInstOperands,
27223 /* 70250 */ // GIR_Coverage, 134,
27224 /* 70250 */ GIR_Done,
27225 /* 70251 */ // Label 1800: @70251
27226 /* 70251 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(70278), // Rule ID 1172 //
27227 /* 70256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit),
27228 /* 70259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27229 /* 70263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27230 /* 70267 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27231 /* 70267 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
27232 /* 70272 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27233 /* 70276 */ GIR_RootConstrainSelectedInstOperands,
27234 /* 70277 */ // GIR_Coverage, 1172,
27235 /* 70277 */ GIR_Done,
27236 /* 70278 */ // Label 1801: @70278
27237 /* 70278 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(70305), // Rule ID 1173 //
27238 /* 70283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat),
27239 /* 70286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27240 /* 70290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27241 /* 70294 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27242 /* 70294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
27243 /* 70299 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27244 /* 70303 */ GIR_RootConstrainSelectedInstOperands,
27245 /* 70304 */ // GIR_Coverage, 1173,
27246 /* 70304 */ GIR_Done,
27247 /* 70305 */ // Label 1802: @70305
27248 /* 70305 */ GIM_Reject,
27249 /* 70306 */ // Label 1798: @70306
27250 /* 70306 */ GIM_Reject,
27251 /* 70307 */ // Label 1792: @70307
27252 /* 70307 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(70333), // Rule ID 780 //
27253 /* 70312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27254 /* 70315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27255 /* 70318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27256 /* 70322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27257 /* 70326 */ // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
27258 /* 70326 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
27259 /* 70331 */ GIR_RootConstrainSelectedInstOperands,
27260 /* 70332 */ // GIR_Coverage, 780,
27261 /* 70332 */ GIR_Done,
27262 /* 70333 */ // Label 1803: @70333
27263 /* 70333 */ GIM_Reject,
27264 /* 70334 */ // Label 1793: @70334
27265 /* 70334 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(70360), // Rule ID 781 //
27266 /* 70339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27267 /* 70342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27268 /* 70345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27269 /* 70349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27270 /* 70353 */ // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
27271 /* 70353 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
27272 /* 70358 */ GIR_RootConstrainSelectedInstOperands,
27273 /* 70359 */ // GIR_Coverage, 781,
27274 /* 70359 */ GIR_Done,
27275 /* 70360 */ // Label 1804: @70360
27276 /* 70360 */ GIM_Reject,
27277 /* 70361 */ // Label 1794: @70361
27278 /* 70361 */ GIM_Reject,
27279 /* 70362 */ // Label 77: @70362
27280 /* 70362 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1807*/ GIMT_Encode4(70435),
27281 /* 70373 */ /*GILLT_v4s32*//*Label 1805*/ GIMT_Encode4(70381),
27282 /* 70377 */ /*GILLT_v2s64*//*Label 1806*/ GIMT_Encode4(70408),
27283 /* 70381 */ // Label 1805: @70381
27284 /* 70381 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(70407), // Rule ID 762 //
27285 /* 70386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27286 /* 70389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27287 /* 70392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27288 /* 70396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27289 /* 70400 */ // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
27290 /* 70400 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
27291 /* 70405 */ GIR_RootConstrainSelectedInstOperands,
27292 /* 70406 */ // GIR_Coverage, 762,
27293 /* 70406 */ GIR_Done,
27294 /* 70407 */ // Label 1808: @70407
27295 /* 70407 */ GIM_Reject,
27296 /* 70408 */ // Label 1806: @70408
27297 /* 70408 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(70434), // Rule ID 763 //
27298 /* 70413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27299 /* 70416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27300 /* 70419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27301 /* 70423 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27302 /* 70427 */ // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
27303 /* 70427 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
27304 /* 70432 */ GIR_RootConstrainSelectedInstOperands,
27305 /* 70433 */ // GIR_Coverage, 763,
27306 /* 70433 */ GIR_Done,
27307 /* 70434 */ // Label 1809: @70434
27308 /* 70434 */ GIM_Reject,
27309 /* 70435 */ // Label 1807: @70435
27310 /* 70435 */ GIM_Reject,
27311 /* 70436 */ // Label 78: @70436
27312 /* 70436 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1812*/ GIMT_Encode4(71290),
27313 /* 70447 */ /*GILLT_s32*//*Label 1810*/ GIMT_Encode4(70455),
27314 /* 70451 */ /*GILLT_s64*//*Label 1811*/ GIMT_Encode4(70727),
27315 /* 70455 */ // Label 1810: @70455
27316 /* 70455 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(70726),
27317 /* 70460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27318 /* 70463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27319 /* 70466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27320 /* 70470 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(70527), // Rule ID 176 //
27321 /* 70475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27322 /* 70478 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27323 /* 70482 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27324 /* 70486 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27325 /* 70490 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27326 /* 70494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27327 /* 70499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27328 /* 70504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27329 /* 70508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27330 /* 70510 */ // (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27331 /* 70510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27332 /* 70513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27333 /* 70515 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27334 /* 70517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27335 /* 70521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27336 /* 70525 */ GIR_RootConstrainSelectedInstOperands,
27337 /* 70526 */ // GIR_Coverage, 176,
27338 /* 70526 */ GIR_EraseRootFromParent_Done,
27339 /* 70527 */ // Label 1814: @70527
27340 /* 70527 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(70584), // Rule ID 175 //
27341 /* 70532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27342 /* 70535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27343 /* 70539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27344 /* 70543 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27345 /* 70547 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27346 /* 70551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27347 /* 70556 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27348 /* 70561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27349 /* 70565 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27350 /* 70567 */ // (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27351 /* 70567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27352 /* 70570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27353 /* 70572 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27354 /* 70574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27355 /* 70578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27356 /* 70582 */ GIR_RootConstrainSelectedInstOperands,
27357 /* 70583 */ // GIR_Coverage, 175,
27358 /* 70583 */ GIR_EraseRootFromParent_Done,
27359 /* 70584 */ // Label 1815: @70584
27360 /* 70584 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(70641), // Rule ID 2489 //
27361 /* 70589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27362 /* 70592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27363 /* 70596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27364 /* 70600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27365 /* 70604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27366 /* 70608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27367 /* 70612 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27368 /* 70617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27369 /* 70622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27370 /* 70624 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27371 /* 70624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27372 /* 70627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27373 /* 70629 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27374 /* 70631 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27375 /* 70635 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27376 /* 70639 */ GIR_RootConstrainSelectedInstOperands,
27377 /* 70640 */ // GIR_Coverage, 2489,
27378 /* 70640 */ GIR_EraseRootFromParent_Done,
27379 /* 70641 */ // Label 1816: @70641
27380 /* 70641 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(70698), // Rule ID 2488 //
27381 /* 70646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27382 /* 70649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27383 /* 70653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27384 /* 70657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27385 /* 70661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27386 /* 70665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27387 /* 70669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27388 /* 70674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27389 /* 70679 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27390 /* 70681 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27391 /* 70681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27392 /* 70684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27393 /* 70686 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27394 /* 70688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27395 /* 70692 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27396 /* 70696 */ GIR_RootConstrainSelectedInstOperands,
27397 /* 70697 */ // GIR_Coverage, 2488,
27398 /* 70697 */ GIR_EraseRootFromParent_Done,
27399 /* 70698 */ // Label 1817: @70698
27400 /* 70698 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(70725), // Rule ID 151 //
27401 /* 70703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27402 /* 70706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27403 /* 70710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27404 /* 70714 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27405 /* 70714 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
27406 /* 70719 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27407 /* 70723 */ GIR_RootConstrainSelectedInstOperands,
27408 /* 70724 */ // GIR_Coverage, 151,
27409 /* 70724 */ GIR_Done,
27410 /* 70725 */ // Label 1818: @70725
27411 /* 70725 */ GIM_Reject,
27412 /* 70726 */ // Label 1813: @70726
27413 /* 70726 */ GIM_Reject,
27414 /* 70727 */ // Label 1811: @70727
27415 /* 70727 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(71289),
27416 /* 70732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27417 /* 70735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27418 /* 70738 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(70799), // Rule ID 184 //
27419 /* 70743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27420 /* 70746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27421 /* 70750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27422 /* 70754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27423 /* 70758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27424 /* 70762 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27425 /* 70766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27426 /* 70771 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27427 /* 70776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27428 /* 70780 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27429 /* 70782 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27430 /* 70782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27431 /* 70785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27432 /* 70787 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27433 /* 70789 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27434 /* 70793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27435 /* 70797 */ GIR_RootConstrainSelectedInstOperands,
27436 /* 70798 */ // GIR_Coverage, 184,
27437 /* 70798 */ GIR_EraseRootFromParent_Done,
27438 /* 70799 */ // Label 1820: @70799
27439 /* 70799 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(70860), // Rule ID 192 //
27440 /* 70804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27441 /* 70807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27442 /* 70811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27443 /* 70815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27444 /* 70819 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27445 /* 70823 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27446 /* 70827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27447 /* 70832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27448 /* 70837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27449 /* 70841 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27450 /* 70843 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27451 /* 70843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27452 /* 70846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27453 /* 70848 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27454 /* 70850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27455 /* 70854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27456 /* 70858 */ GIR_RootConstrainSelectedInstOperands,
27457 /* 70859 */ // GIR_Coverage, 192,
27458 /* 70859 */ GIR_EraseRootFromParent_Done,
27459 /* 70860 */ // Label 1821: @70860
27460 /* 70860 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(70921), // Rule ID 183 //
27461 /* 70865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27462 /* 70868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27463 /* 70872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27464 /* 70876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27465 /* 70880 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27466 /* 70884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27467 /* 70888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27468 /* 70893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27469 /* 70898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27470 /* 70902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27471 /* 70904 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27472 /* 70904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27473 /* 70907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27474 /* 70909 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27475 /* 70911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27476 /* 70915 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27477 /* 70919 */ GIR_RootConstrainSelectedInstOperands,
27478 /* 70920 */ // GIR_Coverage, 183,
27479 /* 70920 */ GIR_EraseRootFromParent_Done,
27480 /* 70921 */ // Label 1822: @70921
27481 /* 70921 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(70982), // Rule ID 191 //
27482 /* 70926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27483 /* 70929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27484 /* 70933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27485 /* 70937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27486 /* 70941 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27487 /* 70945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27488 /* 70949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27489 /* 70954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27490 /* 70959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27491 /* 70963 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27492 /* 70965 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27493 /* 70965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27494 /* 70968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27495 /* 70970 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27496 /* 70972 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27497 /* 70976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27498 /* 70980 */ GIR_RootConstrainSelectedInstOperands,
27499 /* 70981 */ // GIR_Coverage, 191,
27500 /* 70981 */ GIR_EraseRootFromParent_Done,
27501 /* 70982 */ // Label 1823: @70982
27502 /* 70982 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(71043), // Rule ID 2493 //
27503 /* 70987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27504 /* 70990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27505 /* 70994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27506 /* 70998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27507 /* 71002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27508 /* 71006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27509 /* 71010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27510 /* 71014 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27511 /* 71019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27512 /* 71024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27513 /* 71026 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27514 /* 71026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27515 /* 71029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27516 /* 71031 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27517 /* 71033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27518 /* 71037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27519 /* 71041 */ GIR_RootConstrainSelectedInstOperands,
27520 /* 71042 */ // GIR_Coverage, 2493,
27521 /* 71042 */ GIR_EraseRootFromParent_Done,
27522 /* 71043 */ // Label 1824: @71043
27523 /* 71043 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(71104), // Rule ID 2497 //
27524 /* 71048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27525 /* 71051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27526 /* 71055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27527 /* 71059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27528 /* 71063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27529 /* 71067 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27530 /* 71071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27531 /* 71075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27532 /* 71080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27533 /* 71085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27534 /* 71087 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27535 /* 71087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27536 /* 71090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27537 /* 71092 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27538 /* 71094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27539 /* 71098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27540 /* 71102 */ GIR_RootConstrainSelectedInstOperands,
27541 /* 71103 */ // GIR_Coverage, 2497,
27542 /* 71103 */ GIR_EraseRootFromParent_Done,
27543 /* 71104 */ // Label 1825: @71104
27544 /* 71104 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(71165), // Rule ID 2492 //
27545 /* 71109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27546 /* 71112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27547 /* 71116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27548 /* 71120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27549 /* 71124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27550 /* 71128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27551 /* 71132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27552 /* 71136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27553 /* 71141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27554 /* 71146 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27555 /* 71148 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27556 /* 71148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27557 /* 71151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27558 /* 71153 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27559 /* 71155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27560 /* 71159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27561 /* 71163 */ GIR_RootConstrainSelectedInstOperands,
27562 /* 71164 */ // GIR_Coverage, 2492,
27563 /* 71164 */ GIR_EraseRootFromParent_Done,
27564 /* 71165 */ // Label 1826: @71165
27565 /* 71165 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(71226), // Rule ID 2496 //
27566 /* 71170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27567 /* 71173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27568 /* 71177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27569 /* 71181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27570 /* 71185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27571 /* 71189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27572 /* 71193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27573 /* 71197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27574 /* 71202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27575 /* 71207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27576 /* 71209 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27577 /* 71209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27578 /* 71212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27579 /* 71214 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27580 /* 71216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27581 /* 71220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27582 /* 71224 */ GIR_RootConstrainSelectedInstOperands,
27583 /* 71225 */ // GIR_Coverage, 2496,
27584 /* 71225 */ GIR_EraseRootFromParent_Done,
27585 /* 71226 */ // Label 1827: @71226
27586 /* 71226 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(71257), // Rule ID 153 //
27587 /* 71231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27588 /* 71234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27589 /* 71238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27590 /* 71242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27591 /* 71246 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27592 /* 71246 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
27593 /* 71251 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27594 /* 71255 */ GIR_RootConstrainSelectedInstOperands,
27595 /* 71256 */ // GIR_Coverage, 153,
27596 /* 71256 */ GIR_Done,
27597 /* 71257 */ // Label 1828: @71257
27598 /* 71257 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(71288), // Rule ID 155 //
27599 /* 71262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27600 /* 71265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27601 /* 71269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27602 /* 71273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27603 /* 71277 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27604 /* 71277 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
27605 /* 71282 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27606 /* 71286 */ GIR_RootConstrainSelectedInstOperands,
27607 /* 71287 */ // GIR_Coverage, 155,
27608 /* 71287 */ GIR_Done,
27609 /* 71288 */ // Label 1829: @71288
27610 /* 71288 */ GIM_Reject,
27611 /* 71289 */ // Label 1819: @71289
27612 /* 71289 */ GIM_Reject,
27613 /* 71290 */ // Label 1812: @71290
27614 /* 71290 */ GIM_Reject,
27615 /* 71291 */ // Label 79: @71291
27616 /* 71291 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1832*/ GIMT_Encode4(71787),
27617 /* 71302 */ /*GILLT_s32*//*Label 1830*/ GIMT_Encode4(71310),
27618 /* 71306 */ /*GILLT_s64*//*Label 1831*/ GIMT_Encode4(71468),
27619 /* 71310 */ // Label 1830: @71310
27620 /* 71310 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(71467),
27621 /* 71315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27622 /* 71318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27623 /* 71321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27624 /* 71325 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(71382), // Rule ID 180 //
27625 /* 71330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27626 /* 71333 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27627 /* 71337 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27628 /* 71341 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27629 /* 71345 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27630 /* 71349 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27631 /* 71354 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27632 /* 71359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27633 /* 71363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27634 /* 71365 */ // (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27635 /* 71365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
27636 /* 71368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27637 /* 71370 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27638 /* 71372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27639 /* 71376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27640 /* 71380 */ GIR_RootConstrainSelectedInstOperands,
27641 /* 71381 */ // GIR_Coverage, 180,
27642 /* 71381 */ GIR_EraseRootFromParent_Done,
27643 /* 71382 */ // Label 1834: @71382
27644 /* 71382 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(71439), // Rule ID 179 //
27645 /* 71387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27646 /* 71390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27647 /* 71394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27648 /* 71398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27649 /* 71402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27650 /* 71406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27651 /* 71411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27652 /* 71416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27653 /* 71420 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27654 /* 71422 */ // (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27655 /* 71422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
27656 /* 71425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27657 /* 71427 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27658 /* 71429 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27659 /* 71433 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27660 /* 71437 */ GIR_RootConstrainSelectedInstOperands,
27661 /* 71438 */ // GIR_Coverage, 179,
27662 /* 71438 */ GIR_EraseRootFromParent_Done,
27663 /* 71439 */ // Label 1835: @71439
27664 /* 71439 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(71466), // Rule ID 169 //
27665 /* 71444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27666 /* 71447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27667 /* 71451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27668 /* 71455 */ // (strict_fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27669 /* 71455 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
27670 /* 71460 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27671 /* 71464 */ GIR_RootConstrainSelectedInstOperands,
27672 /* 71465 */ // GIR_Coverage, 169,
27673 /* 71465 */ GIR_Done,
27674 /* 71466 */ // Label 1836: @71466
27675 /* 71466 */ GIM_Reject,
27676 /* 71467 */ // Label 1833: @71467
27677 /* 71467 */ GIM_Reject,
27678 /* 71468 */ // Label 1831: @71468
27679 /* 71468 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(71786),
27680 /* 71473 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27681 /* 71476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27682 /* 71479 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(71540), // Rule ID 188 //
27683 /* 71484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27684 /* 71487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27685 /* 71491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27686 /* 71495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27687 /* 71499 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27688 /* 71503 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27689 /* 71507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27690 /* 71512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27691 /* 71517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27692 /* 71521 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27693 /* 71523 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27694 /* 71523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
27695 /* 71526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27696 /* 71528 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27697 /* 71530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27698 /* 71534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27699 /* 71538 */ GIR_RootConstrainSelectedInstOperands,
27700 /* 71539 */ // GIR_Coverage, 188,
27701 /* 71539 */ GIR_EraseRootFromParent_Done,
27702 /* 71540 */ // Label 1838: @71540
27703 /* 71540 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(71601), // Rule ID 196 //
27704 /* 71545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27705 /* 71548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27706 /* 71552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27707 /* 71556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27708 /* 71560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27709 /* 71564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27710 /* 71568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27711 /* 71573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27712 /* 71578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27713 /* 71582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27714 /* 71584 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27715 /* 71584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
27716 /* 71587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27717 /* 71589 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27718 /* 71591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27719 /* 71595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27720 /* 71599 */ GIR_RootConstrainSelectedInstOperands,
27721 /* 71600 */ // GIR_Coverage, 196,
27722 /* 71600 */ GIR_EraseRootFromParent_Done,
27723 /* 71601 */ // Label 1839: @71601
27724 /* 71601 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(71662), // Rule ID 187 //
27725 /* 71606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27726 /* 71609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27727 /* 71613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27728 /* 71617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27729 /* 71621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27730 /* 71625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27731 /* 71629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27732 /* 71634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27733 /* 71639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27734 /* 71643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27735 /* 71645 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27736 /* 71645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
27737 /* 71648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27738 /* 71650 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27739 /* 71652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27740 /* 71656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27741 /* 71660 */ GIR_RootConstrainSelectedInstOperands,
27742 /* 71661 */ // GIR_Coverage, 187,
27743 /* 71661 */ GIR_EraseRootFromParent_Done,
27744 /* 71662 */ // Label 1840: @71662
27745 /* 71662 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(71723), // Rule ID 195 //
27746 /* 71667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27747 /* 71670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27748 /* 71674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27749 /* 71678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27750 /* 71682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27751 /* 71686 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27752 /* 71690 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27753 /* 71695 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27754 /* 71700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27755 /* 71704 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27756 /* 71706 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27757 /* 71706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
27758 /* 71709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27759 /* 71711 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27760 /* 71713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27761 /* 71717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27762 /* 71721 */ GIR_RootConstrainSelectedInstOperands,
27763 /* 71722 */ // GIR_Coverage, 195,
27764 /* 71722 */ GIR_EraseRootFromParent_Done,
27765 /* 71723 */ // Label 1841: @71723
27766 /* 71723 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(71754), // Rule ID 171 //
27767 /* 71728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27768 /* 71731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27769 /* 71735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27770 /* 71739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27771 /* 71743 */ // (strict_fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27772 /* 71743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
27773 /* 71748 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27774 /* 71752 */ GIR_RootConstrainSelectedInstOperands,
27775 /* 71753 */ // GIR_Coverage, 171,
27776 /* 71753 */ GIR_Done,
27777 /* 71754 */ // Label 1842: @71754
27778 /* 71754 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(71785), // Rule ID 173 //
27779 /* 71759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27780 /* 71762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27781 /* 71766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27782 /* 71770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27783 /* 71774 */ // (strict_fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27784 /* 71774 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
27785 /* 71779 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27786 /* 71783 */ GIR_RootConstrainSelectedInstOperands,
27787 /* 71784 */ // GIR_Coverage, 173,
27788 /* 71784 */ GIR_Done,
27789 /* 71785 */ // Label 1843: @71785
27790 /* 71785 */ GIM_Reject,
27791 /* 71786 */ // Label 1837: @71786
27792 /* 71786 */ GIM_Reject,
27793 /* 71787 */ // Label 1832: @71787
27794 /* 71787 */ GIM_Reject,
27795 /* 71788 */ // Label 80: @71788
27796 /* 71788 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1846*/ GIMT_Encode4(71920),
27797 /* 71799 */ /*GILLT_s32*//*Label 1844*/ GIMT_Encode4(71807),
27798 /* 71803 */ /*GILLT_s64*//*Label 1845*/ GIMT_Encode4(71845),
27799 /* 71807 */ // Label 1844: @71807
27800 /* 71807 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(71844), // Rule ID 163 //
27801 /* 71812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27802 /* 71815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27803 /* 71818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27804 /* 71821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27805 /* 71825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27806 /* 71829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27807 /* 71833 */ // (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27808 /* 71833 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
27809 /* 71838 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27810 /* 71842 */ GIR_RootConstrainSelectedInstOperands,
27811 /* 71843 */ // GIR_Coverage, 163,
27812 /* 71843 */ GIR_Done,
27813 /* 71844 */ // Label 1847: @71844
27814 /* 71844 */ GIM_Reject,
27815 /* 71845 */ // Label 1845: @71845
27816 /* 71845 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(71919),
27817 /* 71850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27818 /* 71853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27819 /* 71856 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(71887), // Rule ID 165 //
27820 /* 71861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27821 /* 71864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27822 /* 71868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27823 /* 71872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27824 /* 71876 */ // (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27825 /* 71876 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
27826 /* 71881 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27827 /* 71885 */ GIR_RootConstrainSelectedInstOperands,
27828 /* 71886 */ // GIR_Coverage, 165,
27829 /* 71886 */ GIR_Done,
27830 /* 71887 */ // Label 1849: @71887
27831 /* 71887 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(71918), // Rule ID 167 //
27832 /* 71892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27833 /* 71895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27834 /* 71899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27835 /* 71903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27836 /* 71907 */ // (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27837 /* 71907 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
27838 /* 71912 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27839 /* 71916 */ GIR_RootConstrainSelectedInstOperands,
27840 /* 71917 */ // GIR_Coverage, 167,
27841 /* 71917 */ GIR_Done,
27842 /* 71918 */ // Label 1850: @71918
27843 /* 71918 */ GIM_Reject,
27844 /* 71919 */ // Label 1848: @71919
27845 /* 71919 */ GIM_Reject,
27846 /* 71920 */ // Label 1846: @71920
27847 /* 71920 */ GIM_Reject,
27848 /* 71921 */ // Label 81: @71921
27849 /* 71921 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1853*/ GIMT_Encode4(72053),
27850 /* 71932 */ /*GILLT_s32*//*Label 1851*/ GIMT_Encode4(71940),
27851 /* 71936 */ /*GILLT_s64*//*Label 1852*/ GIMT_Encode4(71978),
27852 /* 71940 */ // Label 1851: @71940
27853 /* 71940 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(71977), // Rule ID 157 //
27854 /* 71945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27855 /* 71948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27856 /* 71951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27857 /* 71954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27858 /* 71958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27859 /* 71962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27860 /* 71966 */ // (strict_fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27861 /* 71966 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
27862 /* 71971 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27863 /* 71975 */ GIR_RootConstrainSelectedInstOperands,
27864 /* 71976 */ // GIR_Coverage, 157,
27865 /* 71976 */ GIR_Done,
27866 /* 71977 */ // Label 1854: @71977
27867 /* 71977 */ GIM_Reject,
27868 /* 71978 */ // Label 1852: @71978
27869 /* 71978 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(72052),
27870 /* 71983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27871 /* 71986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27872 /* 71989 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(72020), // Rule ID 159 //
27873 /* 71994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27874 /* 71997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27875 /* 72001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27876 /* 72005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27877 /* 72009 */ // (strict_fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27878 /* 72009 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
27879 /* 72014 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27880 /* 72018 */ GIR_RootConstrainSelectedInstOperands,
27881 /* 72019 */ // GIR_Coverage, 159,
27882 /* 72019 */ GIR_Done,
27883 /* 72020 */ // Label 1856: @72020
27884 /* 72020 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(72051), // Rule ID 161 //
27885 /* 72025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27886 /* 72028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27887 /* 72032 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27888 /* 72036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27889 /* 72040 */ // (strict_fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27890 /* 72040 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
27891 /* 72045 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27892 /* 72049 */ GIR_RootConstrainSelectedInstOperands,
27893 /* 72050 */ // GIR_Coverage, 161,
27894 /* 72050 */ GIR_Done,
27895 /* 72051 */ // Label 1857: @72051
27896 /* 72051 */ GIM_Reject,
27897 /* 72052 */ // Label 1855: @72052
27898 /* 72052 */ GIM_Reject,
27899 /* 72053 */ // Label 1853: @72053
27900 /* 72053 */ GIM_Reject,
27901 /* 72054 */ // Label 82: @72054
27902 /* 72054 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1860*/ GIMT_Encode4(72168),
27903 /* 72065 */ /*GILLT_s32*//*Label 1858*/ GIMT_Encode4(72073),
27904 /* 72069 */ /*GILLT_s64*//*Label 1859*/ GIMT_Encode4(72104),
27905 /* 72073 */ // Label 1858: @72073
27906 /* 72073 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(72103), // Rule ID 129 //
27907 /* 72078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27908 /* 72081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27909 /* 72084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27910 /* 72088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27911 /* 72092 */ // (strict_fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27912 /* 72092 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
27913 /* 72097 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27914 /* 72101 */ GIR_RootConstrainSelectedInstOperands,
27915 /* 72102 */ // GIR_Coverage, 129,
27916 /* 72102 */ GIR_Done,
27917 /* 72103 */ // Label 1861: @72103
27918 /* 72103 */ GIM_Reject,
27919 /* 72104 */ // Label 1859: @72104
27920 /* 72104 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(72167),
27921 /* 72109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27922 /* 72112 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(72139), // Rule ID 131 //
27923 /* 72117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27924 /* 72120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27925 /* 72124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27926 /* 72128 */ // (strict_fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27927 /* 72128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
27928 /* 72133 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27929 /* 72137 */ GIR_RootConstrainSelectedInstOperands,
27930 /* 72138 */ // GIR_Coverage, 131,
27931 /* 72138 */ GIR_Done,
27932 /* 72139 */ // Label 1863: @72139
27933 /* 72139 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(72166), // Rule ID 133 //
27934 /* 72144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips),
27935 /* 72147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27936 /* 72151 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27937 /* 72155 */ // (strict_fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27938 /* 72155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
27939 /* 72160 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27940 /* 72164 */ GIR_RootConstrainSelectedInstOperands,
27941 /* 72165 */ // GIR_Coverage, 133,
27942 /* 72165 */ GIR_Done,
27943 /* 72166 */ // Label 1864: @72166
27944 /* 72166 */ GIM_Reject,
27945 /* 72167 */ // Label 1862: @72167
27946 /* 72167 */ GIM_Reject,
27947 /* 72168 */ // Label 1860: @72168
27948 /* 72168 */ GIM_Reject,
27949 /* 72169 */ // Label 83: @72169
27950 /* 72169 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(72184), // Rule ID 90 //
27951 /* 72174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
27952 /* 72177 */ // (trap) => (TRAP)
27953 /* 72177 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
27954 /* 72182 */ GIR_RootConstrainSelectedInstOperands,
27955 /* 72183 */ // GIR_Coverage, 90,
27956 /* 72183 */ GIR_Done,
27957 /* 72184 */ // Label 1865: @72184
27958 /* 72184 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(72199), // Rule ID 1139 //
27959 /* 72189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
27960 /* 72192 */ // (trap) => (TRAP_MM)
27961 /* 72192 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
27962 /* 72197 */ GIR_RootConstrainSelectedInstOperands,
27963 /* 72198 */ // GIR_Coverage, 1139,
27964 /* 72198 */ GIR_Done,
27965 /* 72199 */ // Label 1866: @72199
27966 /* 72199 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(72214), // Rule ID 2037 //
27967 /* 72204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
27968 /* 72207 */ // (trap) => (Break16)
27969 /* 72207 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
27970 /* 72212 */ GIR_RootConstrainSelectedInstOperands,
27971 /* 72213 */ // GIR_Coverage, 2037,
27972 /* 72213 */ GIR_Done,
27973 /* 72214 */ // Label 1867: @72214
27974 /* 72214 */ GIM_Reject,
27975 /* 72215 */ // Label 84: @72215
27976 /* 72215 */ GIM_Reject,
27977 /* 72216 */ }; // Size: 72216 bytes
27978 return MatchTable0;
27979}
27980#undef GIMT_Encode2
27981#undef GIMT_Encode4
27982#undef GIMT_Encode8
27983
27984
27985#endif // GET_GLOBALISEL_IMPL
27986
27987#ifdef GET_GLOBALISEL_PREDICATES_DECL
27988
27989PredicateBitset AvailableModuleFeatures;
27990mutable PredicateBitset AvailableFunctionFeatures;
27991PredicateBitset getAvailableFeatures() const {
27992 return AvailableModuleFeatures | AvailableFunctionFeatures;
27993}
27994PredicateBitset
27995computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
27996PredicateBitset
27997computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
27998 const MachineFunction *MF) const;
27999void setupGeneratedPerFunctionState(MachineFunction &MF) override;
28000
28001#endif // GET_GLOBALISEL_PREDICATES_DECL
28002
28003#ifdef GET_GLOBALISEL_PREDICATES_INIT
28004
28005AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
28006AvailableFunctionFeatures()
28007
28008#endif // GET_GLOBALISEL_PREDICATES_INIT
28009
28010