MipsGenGlobalISel.inc source code [llvm_projects/build/lib/Target/Mips/MipsGenGlobalISel.inc]

1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\| \|
3	\| Global Instruction Selector for the Mips target \|
4	\| \|
5	\| Automatically generated file, do not edit! \|
6	\| \|
7	\===----------------------------------------------------------------------===/
8
9	#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11	const unsigned MAX_SUBTARGET_PREDICATES = `45`;
12	using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14	#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16	#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18	mutable MatcherState State;
19	typedef ComplexRendererFns(MipsInstructionSelector::ComplexMatcherMemFn)(MachineOperand &) const*;
20	typedef void(MipsInstructionSelector::CustomRendererFn)(MachineInstrBuilder &, const* MachineInstr &, int) const;
21	const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22	static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23	static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
24	bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25	bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26	bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27	const uint8_t getMatchTable() const* override;
28	bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29	bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30	bool testSimplePredicate(unsigned PredicateID) const override;
31	bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33	#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35	#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37	, State(`0`),
38	ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40	#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42	#ifdef GET_GLOBALISEL_IMPL
43
44	// LLT Objects.
45	enum {
46	GILLT_s32,
47	GILLT_s64,
48	GILLT_v4s8,
49	GILLT_v16s8,
50	GILLT_v2s16,
51	GILLT_v8s16,
52	GILLT_v4s32,
53	GILLT_v2s64,
54	};
55	const static size_t NumTypeObjects = `8`;
56	const static LLT TypeObjects[] = {
57	LLT::scalar(`32`),
58	LLT::scalar(`64`),
59	LLT::vector(ElementCount::getFixed(`4`), LLT::scalar(`8`)),
60	LLT::vector(ElementCount::getFixed(`16`), LLT::scalar(`8`)),
61	LLT::vector(ElementCount::getFixed(`2`), LLT::scalar(`16`)),
62	LLT::vector(ElementCount::getFixed(`8`), LLT::scalar(`16`)),
63	LLT::vector(ElementCount::getFixed(`4`), LLT::scalar(`32`)),
64	LLT::vector(ElementCount::getFixed(`2`), LLT::scalar(`64`)),
65	};
66
67	// Bits for subtarget features that participate in instruction matching.
68	enum SubtargetFeatureBits : uint8_t {
69	Feature_IsPTR64bitBit = `23`,
70	Feature_UseCompactBranchesBit = `41`,
71	Feature_HasMips2Bit = `7`,
72	Feature_HasMips3Bit = `18`,
73	Feature_HasMips4_32Bit = `26`,
74	Feature_NotMips4_32Bit = `27`,
75	Feature_HasMips4_32r2Bit = `19`,
76	Feature_HasMips32Bit = `3`,
77	Feature_HasMips32r2Bit = `6`,
78	Feature_HasMips32r6Bit = `28`,
79	Feature_NotMips32r6Bit = `4`,
80	Feature_IsGP64bitBit = `21`,
81	Feature_HasMips64Bit = `24`,
82	Feature_HasMips64r2Bit = `22`,
83	Feature_HasMips64r6Bit = `29`,
84	Feature_NotMips64r6Bit = `5`,
85	Feature_InMips16ModeBit = `30`,
86	Feature_NotInMips16ModeBit = `0`,
87	Feature_HasCnMipsBit = `25`,
88	Feature_NotCnMipsBit = `8`,
89	Feature_IsSym32Bit = `38`,
90	Feature_IsSym64Bit = `39`,
91	Feature_IsN64Bit = `40`,
92	Feature_RelocNotPICBit = `10`,
93	Feature_RelocPICBit = `36`,
94	Feature_HasStdEncBit = `1`,
95	Feature_NotDSPBit = `12`,
96	Feature_InMicroMipsBit = `34`,
97	Feature_NotInMicroMipsBit = `2`,
98	Feature_IsLEBit = `43`,
99	Feature_IsBEBit = `44`,
100	Feature_HasEVABit = `35`,
101	Feature_HasMSABit = `33`,
102	Feature_HasMadd4Bit = `20`,
103	Feature_UseIndirectJumpsHazardBit = `13`,
104	Feature_NoIndirectJumpGuardsBit = `11`,
105	Feature_IsR5900Bit = `37`,
106	Feature_NotR5900Bit = `9`,
107	Feature_AllowFPOpFusionBit = `42`,
108	Feature_IsFP64bitBit = `17`,
109	Feature_NotFP64bitBit = `16`,
110	Feature_IsNotSingleFloatBit = `15`,
111	Feature_IsNotSoftFloatBit = `14`,
112	Feature_HasDSPBit = `31`,
113	Feature_HasDSPR2Bit = `32`,
114	};
115
116	PredicateBitset MipsInstructionSelector::
117	computeAvailableModuleFeatures(const MipsSubtarget Subtarget) const* {
118	PredicateBitset Features{};
119	if (Subtarget->isABI_N64())
120	Features.set(Feature_IsPTR64bitBit);
121	if (Subtarget->useCompactBranches())
122	Features.set(Feature_UseCompactBranchesBit);
123	if (Subtarget->hasMips2())
124	Features.set(Feature_HasMips2Bit);
125	if (Subtarget->hasMips3())
126	Features.set(Feature_HasMips3Bit);
127	if (Subtarget->hasMips4_32())
128	Features.set(Feature_HasMips4_32Bit);
129	if (!Subtarget->hasMips4_32())
130	Features.set(Feature_NotMips4_32Bit);
131	if (Subtarget->hasMips4_32r2())
132	Features.set(Feature_HasMips4_32r2Bit);
133	if (Subtarget->hasMips32())
134	Features.set(Feature_HasMips32Bit);
135	if (Subtarget->hasMips32r2())
136	Features.set(Feature_HasMips32r2Bit);
137	if (Subtarget->hasMips32r6())
138	Features.set(Feature_HasMips32r6Bit);
139	if (!Subtarget->hasMips32r6())
140	Features.set(Feature_NotMips32r6Bit);
141	if (Subtarget->isGP64bit())
142	Features.set(Feature_IsGP64bitBit);
143	if (Subtarget->hasMips64())
144	Features.set(Feature_HasMips64Bit);
145	if (Subtarget->hasMips64r2())
146	Features.set(Feature_HasMips64r2Bit);
147	if (Subtarget->hasMips64r6())
148	Features.set(Feature_HasMips64r6Bit);
149	if (!Subtarget->hasMips64r6())
150	Features.set(Feature_NotMips64r6Bit);
151	if (Subtarget->inMips16Mode())
152	Features.set(Feature_InMips16ModeBit);
153	if (!Subtarget->inMips16Mode())
154	Features.set(Feature_NotInMips16ModeBit);
155	if (Subtarget->hasCnMips())
156	Features.set(Feature_HasCnMipsBit);
157	if (!Subtarget->hasCnMips())
158	Features.set(Feature_NotCnMipsBit);
159	if (Subtarget->hasSym32())
160	Features.set(Feature_IsSym32Bit);
161	if (!Subtarget->hasSym32())
162	Features.set(Feature_IsSym64Bit);
163	if (Subtarget->isABI_N64())
164	Features.set(Feature_IsN64Bit);
165	if (!TM.isPositionIndependent())
166	Features.set(Feature_RelocNotPICBit);
167	if (TM.isPositionIndependent())
168	Features.set(Feature_RelocPICBit);
169	if (Subtarget->hasStandardEncoding())
170	Features.set(Feature_HasStdEncBit);
171	if (!Subtarget->hasDSP())
172	Features.set(Feature_NotDSPBit);
173	if (Subtarget->inMicroMipsMode())
174	Features.set(Feature_InMicroMipsBit);
175	if (!Subtarget->inMicroMipsMode())
176	Features.set(Feature_NotInMicroMipsBit);
177	if (Subtarget->isLittle())
178	Features.set(Feature_IsLEBit);
179	if (!Subtarget->isLittle())
180	Features.set(Feature_IsBEBit);
181	if (Subtarget->hasEVA())
182	Features.set(Feature_HasEVABit);
183	if (Subtarget->hasMSA())
184	Features.set(Feature_HasMSABit);
185	if (!Subtarget->disableMadd4())
186	Features.set(Feature_HasMadd4Bit);
187	if (Subtarget->useIndirectJumpsHazard())
188	Features.set(Feature_UseIndirectJumpsHazardBit);
189	if (!Subtarget->useIndirectJumpsHazard())
190	Features.set(Feature_NoIndirectJumpGuardsBit);
191	if (Subtarget->isR5900())
192	Features.set(Feature_IsR5900Bit);
193	if (!Subtarget->isR5900())
194	Features.set(Feature_NotR5900Bit);
195	if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
196	Features.set(Feature_AllowFPOpFusionBit);
197	if (Subtarget->isFP64bit())
198	Features.set(Feature_IsFP64bitBit);
199	if (!Subtarget->isFP64bit())
200	Features.set(Feature_NotFP64bitBit);
201	if (!Subtarget->isSingleFloat())
202	Features.set(Feature_IsNotSingleFloatBit);
203	if (!Subtarget->useSoftFloat())
204	Features.set(Feature_IsNotSoftFloatBit);
205	if (Subtarget->hasDSP())
206	Features.set(Feature_HasDSPBit);
207	if (Subtarget->hasDSPR2())
208	Features.set(Feature_HasDSPR2Bit);
209	return Features;
210	}
211
212	void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
213	AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
214	}
215	PredicateBitset MipsInstructionSelector::
216	computeAvailableFunctionFeatures(const MipsSubtarget Subtarget, const* MachineFunction MF) const* {
217	PredicateBitset Features{};
218	return Features;
219	}
220
221	// Feature bitsets.
222	enum {
223	GIFBS_Invalid,
224	GIFBS_HasCnMips,
225	GIFBS_HasDSP,
226	GIFBS_HasDSPR2,
227	GIFBS_HasMSA,
228	GIFBS_InMicroMips,
229	GIFBS_InMips16Mode,
230	GIFBS_NotInMips16Mode,
231	GIFBS_HasDSP_InMicroMips,
232	GIFBS_HasDSP_NotInMicroMips,
233	GIFBS_HasDSPR2_InMicroMips,
234	GIFBS_HasMSA_HasStdEnc,
235	GIFBS_HasMSA_IsBE,
236	GIFBS_HasMSA_IsLE,
237	GIFBS_HasMips32r6_HasStdEnc,
238	GIFBS_HasMips32r6_InMicroMips,
239	GIFBS_HasMips64r2_HasStdEnc,
240	GIFBS_HasMips64r6_HasStdEnc,
241	GIFBS_HasStdEnc_IsNotSoftFloat,
242	GIFBS_HasStdEnc_NotInMicroMips,
243	GIFBS_HasStdEnc_NotMips4_32,
244	GIFBS_InMicroMips_IsNotSoftFloat,
245	GIFBS_InMicroMips_NotMips32r6,
246	GIFBS_IsFP64bit_IsNotSingleFloat,
247	GIFBS_IsGP64bit_NotInMips16Mode,
248	GIFBS_IsNotSingleFloat_NotFP64bit,
249	GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
250	GIFBS_HasMSA_HasMips64_HasStdEnc,
251	GIFBS_HasMips3_HasStdEnc_IsGP64bit,
252	GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
253	GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
254	GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
255	GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
256	GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
257	GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
258	GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
259	GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
260	GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
261	GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat,
262	GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit,
263	GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
264	GIFBS_InMicroMips_NotMips32r6_RelocPIC,
265	GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
266	GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
267	GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat,
268	GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
269	GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat,
270	GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit,
271	GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
272	GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
273	GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
274	GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
275	GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
276	GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips,
277	GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32,
278	GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips,
279	GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32,
280	GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
281	GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit,
282	GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6,
283	GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode,
284	GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
285	GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
286	GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
287	GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
288	GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
289	GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
290	GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
291	GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
292	GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
293	GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
294	GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
295	GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
296	GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
297	GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
298	};
299	constexpr static PredicateBitset FeatureBitsets[] {
300	{}, // GIFBS_Invalid
301	{Feature_HasCnMipsBit, },
302	{Feature_HasDSPBit, },
303	{Feature_HasDSPR2Bit, },
304	{Feature_HasMSABit, },
305	{Feature_InMicroMipsBit, },
306	{Feature_InMips16ModeBit, },
307	{Feature_NotInMips16ModeBit, },
308	{Feature_HasDSPBit, Feature_InMicroMipsBit, },
309	{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
310	{Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
311	{Feature_HasMSABit, Feature_HasStdEncBit, },
312	{Feature_HasMSABit, Feature_IsBEBit, },
313	{Feature_HasMSABit, Feature_IsLEBit, },
314	{Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
315	{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
316	{Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
317	{Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
318	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
319	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
320	{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
321	{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
322	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
323	{Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
324	{Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
325	{Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
326	{Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
327	{Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
328	{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
329	{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
330	{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
331	{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
332	{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
333	{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
334	{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
335	{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
336	{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
337	{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
338	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
339	{Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
340	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
341	{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
342	{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
343	{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
344	{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
345	{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
346	{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
347	{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
348	{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
349	{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
350	{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
351	{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
352	{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
353	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, },
354	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, },
355	{Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
356	{Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
357	{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
358	{Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
359	{Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
360	{Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
361	{Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
362	{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
363	{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
364	{Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
365	{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
366	{Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
367	{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
368	{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
369	{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
370	{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
371	{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
372	{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
373	{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
374	{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
375	};
376
377	// ComplexPattern predicates.
378	enum {
379	GICP_Invalid,
380	};
381	// See constructor for table contents
382
383	MipsInstructionSelector::ComplexMatcherMemFn
384	MipsInstructionSelector::ComplexPredicateFns[] = {
385	nullptr, // GICP_Invalid
386	};
387
388	// PatFrag predicates.
389	enum {
390	GICXXPred_MI_Predicate_ffloor_nnan = GICXXPred_Invalid + `1`,
391	GICXXPred_MI_Predicate_or_disjoint,
392	};
393	bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
394	const MachineFunction &MF = *MI.getParent()->getParent();
395	const MachineRegisterInfo &MRI = MF.getRegInfo();
396	const auto &Operands = State.RecordedOperands;
397	(void)Operands;
398	(void)MRI;
399	switch (PredicateID) {
400	case GICXXPred_MI_Predicate_ffloor_nnan: {
401
402	return MI.getFlag(MachineInstr::FmNoNans);
403
404	}
405	case GICXXPred_MI_Predicate_or_disjoint: {
406
407	return MI.getFlag(MachineInstr::Disjoint);
408
409	}
410	}
411	llvm_unreachable("Unknown predicate");
412	return false;
413	}
414	// PatFrag predicates.
415	bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
416	const auto &Operands = State.RecordedOperands;
417	Register Reg = MO.getReg();
418	(void)Operands;
419	(void)Reg;
420	llvm_unreachable("Unknown predicate");
421	return false;
422	}
423	// PatFrag predicates.
424	enum {
425	GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + `1`,
426	GICXXPred_I64_Predicate_immSExt6,
427	GICXXPred_I64_Predicate_immSExt10,
428	GICXXPred_I64_Predicate_immSExtAddiur2,
429	GICXXPred_I64_Predicate_immSExtAddius5,
430	GICXXPred_I64_Predicate_immZExt1,
431	GICXXPred_I64_Predicate_immZExt1Ptr,
432	GICXXPred_I64_Predicate_immZExt2,
433	GICXXPred_I64_Predicate_immZExt2Lsa,
434	GICXXPred_I64_Predicate_immZExt2Ptr,
435	GICXXPred_I64_Predicate_immZExt2Shift,
436	GICXXPred_I64_Predicate_immZExt3,
437	GICXXPred_I64_Predicate_immZExt3Ptr,
438	GICXXPred_I64_Predicate_immZExt4,
439	GICXXPred_I64_Predicate_immZExt4Ptr,
440	GICXXPred_I64_Predicate_immZExt5,
441	GICXXPred_I64_Predicate_immZExt5_64,
442	GICXXPred_I64_Predicate_immZExt6,
443	GICXXPred_I64_Predicate_immZExt8,
444	GICXXPred_I64_Predicate_immZExt10,
445	GICXXPred_I64_Predicate_immZExtAndi16,
446	GICXXPred_I64_Predicate_immi32Cst7,
447	GICXXPred_I64_Predicate_immi32Cst15,
448	GICXXPred_I64_Predicate_immi32Cst31,
449	GICXXPred_I64_Predicate_timmSExt6,
450	GICXXPred_I64_Predicate_timmZExt1,
451	GICXXPred_I64_Predicate_timmZExt1Ptr,
452	GICXXPred_I64_Predicate_timmZExt2,
453	GICXXPred_I64_Predicate_timmZExt2Ptr,
454	GICXXPred_I64_Predicate_timmZExt3,
455	GICXXPred_I64_Predicate_timmZExt3Ptr,
456	GICXXPred_I64_Predicate_timmZExt4,
457	GICXXPred_I64_Predicate_timmZExt4Ptr,
458	GICXXPred_I64_Predicate_timmZExt5,
459	GICXXPred_I64_Predicate_timmZExt6,
460	GICXXPred_I64_Predicate_timmZExt8,
461	GICXXPred_I64_Predicate_timmZExt10,
462	};
463	bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
464	switch (PredicateID) {
465	case GICXXPred_I64_Predicate_immLi16: {
466	return Imm >= -`1` && Imm <= `126`;
467	}
468	case GICXXPred_I64_Predicate_immSExt6: {
469	return isInt<`6`>(Imm);
470	}
471	case GICXXPred_I64_Predicate_immSExt10: {
472	return isInt<`10`>(Imm);
473	}
474	case GICXXPred_I64_Predicate_immSExtAddiur2: {
475	return Imm == `1` \|\| Imm == -`1` \|\|
476	((Imm % `4` == `0`) &&
477	Imm < `28` && Imm > `0`);
478	}
479	case GICXXPred_I64_Predicate_immSExtAddius5: {
480	return Imm >= -`8` && Imm <= `7`;
481	}
482	case GICXXPred_I64_Predicate_immZExt1: {
483	return isUInt<`1`>(Imm);
484	}
485	case GICXXPred_I64_Predicate_immZExt1Ptr: {
486	return isUInt<`1`>(Imm);
487	}
488	case GICXXPred_I64_Predicate_immZExt2: {
489	return isUInt<`2`>(Imm);
490	}
491	case GICXXPred_I64_Predicate_immZExt2Lsa: {
492	return isUInt<`2`>(Imm - `1`);
493	}
494	case GICXXPred_I64_Predicate_immZExt2Ptr: {
495	return isUInt<`2`>(Imm);
496	}
497	case GICXXPred_I64_Predicate_immZExt2Shift: {
498	return Imm >= `1` && Imm <= `8`;
499	}
500	case GICXXPred_I64_Predicate_immZExt3: {
501	return isUInt<`3`>(Imm);
502	}
503	case GICXXPred_I64_Predicate_immZExt3Ptr: {
504	return isUInt<`3`>(Imm);
505	}
506	case GICXXPred_I64_Predicate_immZExt4: {
507	return isUInt<`4`>(Imm);
508	}
509	case GICXXPred_I64_Predicate_immZExt4Ptr: {
510	return isUInt<`4`>(Imm);
511	}
512	case GICXXPred_I64_Predicate_immZExt5: {
513	return Imm == (Imm & `0x1f`);
514	}
515	case GICXXPred_I64_Predicate_immZExt5_64: {
516	return Imm == (Imm & `0x1f`);
517	}
518	case GICXXPred_I64_Predicate_immZExt6: {
519	return Imm == (Imm & `0x3f`);
520	}
521	case GICXXPred_I64_Predicate_immZExt8: {
522	return isUInt<`8`>(Imm);
523	}
524	case GICXXPred_I64_Predicate_immZExt10: {
525	return isUInt<`10`>(Imm);
526	}
527	case GICXXPred_I64_Predicate_immZExtAndi16: {
528	return (Imm == `128` \|\| (Imm >= `1` && Imm <= `4`) \|\| Imm == `7` \|\| Imm == `8` \|\|
529	Imm == `15` \|\| Imm == `16` \|\| Imm == `31` \|\| Imm == `32` \|\| Imm == `63` \|\|
530	Imm == `64` \|\| Imm == `255` \|\| Imm == `32768` \|\| Imm == `65535` );
531	}
532	case GICXXPred_I64_Predicate_immi32Cst7: {
533	return isUInt<`32`>(Imm) && Imm == `7`;
534	}
535	case GICXXPred_I64_Predicate_immi32Cst15: {
536	return isUInt<`32`>(Imm) && Imm == `15`;
537	}
538	case GICXXPred_I64_Predicate_immi32Cst31: {
539	return isUInt<`32`>(Imm) && Imm == `31`;
540	}
541	case GICXXPred_I64_Predicate_timmSExt6: {
542	return isInt<`6`>(Imm);
543	}
544	case GICXXPred_I64_Predicate_timmZExt1: {
545	return isUInt<`1`>(Imm);
546	}
547	case GICXXPred_I64_Predicate_timmZExt1Ptr: {
548	return isUInt<`1`>(Imm);
549	}
550	case GICXXPred_I64_Predicate_timmZExt2: {
551	return isUInt<`2`>(Imm);
552	}
553	case GICXXPred_I64_Predicate_timmZExt2Ptr: {
554	return isUInt<`2`>(Imm);
555	}
556	case GICXXPred_I64_Predicate_timmZExt3: {
557	return isUInt<`3`>(Imm);
558	}
559	case GICXXPred_I64_Predicate_timmZExt3Ptr: {
560	return isUInt<`3`>(Imm);
561	}
562	case GICXXPred_I64_Predicate_timmZExt4: {
563	return isUInt<`4`>(Imm);
564	}
565	case GICXXPred_I64_Predicate_timmZExt4Ptr: {
566	return isUInt<`4`>(Imm);
567	}
568	case GICXXPred_I64_Predicate_timmZExt5: {
569	return Imm == (Imm & `0x1f`);
570	}
571	case GICXXPred_I64_Predicate_timmZExt6: {
572	return Imm == (Imm & `0x3f`);
573	}
574	case GICXXPred_I64_Predicate_timmZExt8: {
575	return isUInt<`8`>(Imm);
576	}
577	case GICXXPred_I64_Predicate_timmZExt10: {
578	return isUInt<`10`>(Imm);
579	}
580	}
581	llvm_unreachable("Unknown predicate");
582	return false;
583	}
584	// PatFrag predicates.
585	bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
586	llvm_unreachable("Unknown predicate");
587	return false;
588	}
589	// PatFrag predicates.
590	enum {
591	GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + `1`,
592	GICXXPred_APInt_Predicate_imm32ZExt16,
593	};
594	bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
595	switch (PredicateID) {
596	case GICXXPred_APInt_Predicate_imm32SExt16: {
597	return isInt<`16`>(Imm.getSExtValue());
598	}
599	case GICXXPred_APInt_Predicate_imm32ZExt16: {
600
601	return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
602
603	}
604	}
605	llvm_unreachable("Unknown predicate");
606	return false;
607	}
608	bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
609	llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
610	return false;
611	}
612	// Custom renderers.
613	enum {
614	GICR_Invalid,
615	};
616	MipsInstructionSelector::CustomRendererFn
617	MipsInstructionSelector::CustomRenderers[] = {
618	nullptr, // GICR_Invalid
619	};
620
621	bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
622	const PredicateBitset AvailableFeatures = getAvailableFeatures();
623	MachineIRBuilder B(I);
624	State.MIs.clear();
625	State.MIs.push_back(&I);
626
627	if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
628	return true;
629	}
630
631	return false;
632	}
633
634	bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
635	llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
636	}
637	#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
638	#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
639	#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
640	#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
641	#else
642	#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
643	#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
644	#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
645	#endif
646	const uint8_t MipsInstructionSelector::getMatchTable() const* {
647	constexpr static uint8_t MatchTable0[] = {
648	/ 0 / GIM_SwitchOpcode, /MI/`0`, /[/GIMT_Encode2(`55`), GIMT_Encode2(`310`), /)//default://Label 84/ GIMT_Encode4(`67984`),
649	/ 10 / /TargetOpcode::G_ADD//Label 0/ GIMT_Encode4(`1030`),
650	/ 14 / /TargetOpcode::G_SUB//Label 1/ GIMT_Encode4(`2311`),
651	/ 18 / /TargetOpcode::G_MUL//Label 2/ GIMT_Encode4(`2985`),
652	/ 22 / /TargetOpcode::G_SDIV//Label 3/ GIMT_Encode4(`3424`),
653	/ 26 / /TargetOpcode::G_UDIV//Label 4/ GIMT_Encode4(`3686`),
654	/ 30 / /TargetOpcode::G_SREM//Label 5/ GIMT_Encode4(`3948`),
655	/ 34 / /TargetOpcode::G_UREM//Label 6/ GIMT_Encode4(`4210`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
656	/ 46 / /TargetOpcode::G_AND//Label 7/ GIMT_Encode4(`4472`),
657	/ 50 / /TargetOpcode::G_OR//Label 8/ GIMT_Encode4(`5006`),
658	/ 54 / /TargetOpcode::G_XOR//Label 9/ GIMT_Encode4(`5391`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
659	/ 118 / /TargetOpcode::G_MERGE_VALUES//Label 10/ GIMT_Encode4(`6228`),
660	/ 122 / /TargetOpcode::G_BUILD_VECTOR//Label 11/ GIMT_Encode4(`6299`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
661	/ 142 / /TargetOpcode::G_BITCAST//Label 12/ GIMT_Encode4(`6634`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
662	/ 186 / /TargetOpcode::G_LOAD//Label 13/ GIMT_Encode4(`10628`),
663	/ 190 / /TargetOpcode::G_SEXTLOAD//Label 14/ GIMT_Encode4(`10692`),
664	/ 194 / /TargetOpcode::G_ZEXTLOAD//Label 15/ GIMT_Encode4(`10759`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
665	/ 230 / /TargetOpcode::G_ATOMIC_CMPXCHG//Label 16/ GIMT_Encode4(`10826`),
666	/ 234 / /TargetOpcode::G_ATOMICRMW_XCHG//Label 17/ GIMT_Encode4(`11014`),
667	/ 238 / /TargetOpcode::G_ATOMICRMW_ADD//Label 18/ GIMT_Encode4(`11180`),
668	/ 242 / /TargetOpcode::G_ATOMICRMW_SUB//Label 19/ GIMT_Encode4(`11346`),
669	/ 246 / /TargetOpcode::G_ATOMICRMW_AND//Label 20/ GIMT_Encode4(`11512`),
670	/ 250 / /TargetOpcode::G_ATOMICRMW_NAND//Label 21/ GIMT_Encode4(`11678`),
671	/ 254 / /TargetOpcode::G_ATOMICRMW_OR//Label 22/ GIMT_Encode4(`11844`),
672	/ 258 / /TargetOpcode::G_ATOMICRMW_XOR//Label 23/ GIMT_Encode4(`12010`),
673	/ 262 / /TargetOpcode::G_ATOMICRMW_MAX//Label 24/ GIMT_Encode4(`12176`),
674	/ 266 / /TargetOpcode::G_ATOMICRMW_MIN//Label 25/ GIMT_Encode4(`12342`),
675	/ 270 / /TargetOpcode::G_ATOMICRMW_UMAX//Label 26/ GIMT_Encode4(`12508`),
676	/ 274 / /TargetOpcode::G_ATOMICRMW_UMIN//Label 27/ GIMT_Encode4(`12674`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
677	/ 334 / /TargetOpcode::G_BRCOND//Label 28/ GIMT_Encode4(`12840`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
678	/ 346 / /TargetOpcode::G_INTRINSIC//Label 29/ GIMT_Encode4(`19004`),
679	/ 350 / /TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS//Label 30/ GIMT_Encode4(`32946`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
680	/ 362 / /TargetOpcode::G_ANYEXT//Label 31/ GIMT_Encode4(`37906`),
681	/ 366 / /TargetOpcode::G_TRUNC//Label 32/ GIMT_Encode4(`37971`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
682	/ 382 / /TargetOpcode::G_CONSTANT//Label 33/ GIMT_Encode4(`38034`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
683	/ 398 / /TargetOpcode::G_SEXT//Label 34/ GIMT_Encode4(`38093`),
684	/ 402 / /TargetOpcode::G_SEXT_INREG//Label 35/ GIMT_Encode4(`39550`),
685	/ 406 / /TargetOpcode::G_ZEXT//Label 36/ GIMT_Encode4(`39869`),
686	/ 410 / /TargetOpcode::G_SHL//Label 37/ GIMT_Encode4(`40066`),
687	/ 414 / /TargetOpcode::G_LSHR//Label 38/ GIMT_Encode4(`41841`),
688	/ 418 / /TargetOpcode::G_ASHR//Label 39/ GIMT_Encode4(`43616`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
689	/ 430 / /TargetOpcode::G_ROTR//Label 40/ GIMT_Encode4(`45350`), GIMT_Encode4(`0`),
690	/ 438 / /TargetOpcode::G_ICMP//Label 41/ GIMT_Encode4(`45633`),
691	/ 442 / /TargetOpcode::G_FCMP//Label 42/ GIMT_Encode4(`48127`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
692	/ 454 / /TargetOpcode::G_SELECT//Label 43/ GIMT_Encode4(`49052`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
693	/ 498 / /TargetOpcode::G_UMULH//Label 44/ GIMT_Encode4(`58786`),
694	/ 502 / /TargetOpcode::G_SMULH//Label 45/ GIMT_Encode4(`58892`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
695	/ 562 / /TargetOpcode::G_FADD//Label 46/ GIMT_Encode4(`58998`),
696	/ 566 / /TargetOpcode::G_FSUB//Label 47/ GIMT_Encode4(`60270`),
697	/ 570 / /TargetOpcode::G_FMUL//Label 48/ GIMT_Encode4(`61068`),
698	/ 574 / /TargetOpcode::G_FMA//Label 49/ GIMT_Encode4(`61578`), GIMT_Encode4(`0`),
699	/ 582 / /TargetOpcode::G_FDIV//Label 50/ GIMT_Encode4(`61678`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
700	/ 606 / /TargetOpcode::G_FEXP2//Label 51/ GIMT_Encode4(`62000`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
701	/ 618 / /TargetOpcode::G_FLOG2//Label 52/ GIMT_Encode4(`62072`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
702	/ 634 / /TargetOpcode::G_FNEG//Label 53/ GIMT_Encode4(`62144`),
703	/ 638 / /TargetOpcode::G_FPEXT//Label 54/ GIMT_Encode4(`62322`),
704	/ 642 / /TargetOpcode::G_FPTRUNC//Label 55/ GIMT_Encode4(`62437`),
705	/ 646 / /TargetOpcode::G_FPTOSI//Label 56/ GIMT_Encode4(`62544`),
706	/ 650 / /TargetOpcode::G_FPTOUI//Label 57/ GIMT_Encode4(`62616`),
707	/ 654 / /TargetOpcode::G_SITOFP//Label 58/ GIMT_Encode4(`62688`),
708	/ 658 / /TargetOpcode::G_UITOFP//Label 59/ GIMT_Encode4(`62970`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
709	/ 670 / /TargetOpcode::G_FABS//Label 60/ GIMT_Encode4(`63042`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
710	/ 682 / /TargetOpcode::G_FCANONICALIZE//Label 61/ GIMT_Encode4(`63282`),
711	/ 686 / /TargetOpcode::G_FMINNUM//Label 62/ GIMT_Encode4(`63354`),
712	/ 690 / /TargetOpcode::G_FMAXNUM//Label 63/ GIMT_Encode4(`63424`),
713	/ 694 / /TargetOpcode::G_FMINNUM_IEEE//Label 64/ GIMT_Encode4(`63494`),
714	/ 698 / /TargetOpcode::G_FMAXNUM_IEEE//Label 65/ GIMT_Encode4(`63564`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
715	/ 758 / /TargetOpcode::G_SMIN//Label 66/ GIMT_Encode4(`63634`),
716	/ 762 / /TargetOpcode::G_SMAX//Label 67/ GIMT_Encode4(`63798`),
717	/ 766 / /TargetOpcode::G_UMIN//Label 68/ GIMT_Encode4(`63962`),
718	/ 770 / /TargetOpcode::G_UMAX//Label 69/ GIMT_Encode4(`64126`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
719	/ 786 / /TargetOpcode::G_BR//Label 70/ GIMT_Encode4(`64290`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
720	/ 806 / /TargetOpcode::G_INSERT_VECTOR_ELT//Label 71/ GIMT_Encode4(`64408`),
721	/ 810 / /TargetOpcode::G_EXTRACT_VECTOR_ELT//Label 72/ GIMT_Encode4(`65000`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
722	/ 838 / /TargetOpcode::G_CTLZ//Label 73/ GIMT_Encode4(`65051`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
723	/ 850 / /TargetOpcode::G_CTPOP//Label 74/ GIMT_Encode4(`65542`),
724	/ 854 / /TargetOpcode::G_BSWAP//Label 75/ GIMT_Encode4(`65742`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
725	/ 914 / /TargetOpcode::G_FSQRT//Label 76/ GIMT_Encode4(`65903`), GIMT_Encode4(`0`),
726	/ 922 / /TargetOpcode::G_FRINT//Label 77/ GIMT_Encode4(`66167`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
727	/ 954 / /TargetOpcode::G_STRICT_FADD//Label 78/ GIMT_Encode4(`66239`),
728	/ 958 / /TargetOpcode::G_STRICT_FSUB//Label 79/ GIMT_Encode4(`67079`),
729	/ 962 / /TargetOpcode::G_STRICT_FMUL//Label 80/ GIMT_Encode4(`67569`),
730	/ 966 / /TargetOpcode::G_STRICT_FDIV//Label 81/ GIMT_Encode4(`67699`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
731	/ 978 / /TargetOpcode::G_STRICT_FSQRT//Label 82/ GIMT_Encode4(`67829`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
732	/ 1026 / /TargetOpcode::G_TRAP//Label 83/ GIMT_Encode4(`67941`),
733	/ 1030 / // Label 0: @1030
734	/ 1030 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 93/ GIMT_Encode4(`2310`),
735	/ 1041 / /GILLT_s32//Label 85/ GIMT_Encode4(`1073`),
736	/ 1045 / /GILLT_s64//Label 86/ GIMT_Encode4(`1471`),
737	/ 1049 / /GILLT_v4s8//Label 87/ GIMT_Encode4(`1636`),
738	/ 1053 / /GILLT_v16s8//Label 88/ GIMT_Encode4(`1667`),
739	/ 1057 / /GILLT_v2s16//Label 89/ GIMT_Encode4(`1820`),
740	/ 1061 / /GILLT_v8s16//Label 90/ GIMT_Encode4(`1851`),
741	/ 1065 / /GILLT_v4s32//Label 91/ GIMT_Encode4(`2004`),
742	/ 1069 / /GILLT_v2s64//Label 92/ GIMT_Encode4(`2157`),
743	/ 1073 / // Label 85: @1073
744	/ 1073 / GIM_Try, /On fail goto//Label 94/ GIMT_Encode4(`1470`),
745	/ 1078 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
746	/ 1081 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
747	/ 1084 / GIM_Try, /On fail goto//Label 95/ GIMT_Encode4(`1257`),
748	/ 1089 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
749	/ 1093 / GIM_Try_CheckFeatures, /On fail goto//Label 96/ GIMT_Encode4(`1155`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2536 //
750	/ 1100 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
751	/ 1104 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
752	/ 1108 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
753	/ 1112 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
754	/ 1116 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
755	/ 1121 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
756	/ 1125 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
757	/ 1129 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
758	/ 1133 / // MIs[2] Operand 1
759	/ 1133 / // No operand predicates
760	/ 1133 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
761	/ 1137 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
762	/* 1139 / // (add:{ :[i32] } (shl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ :[i32] }:$rt) => (LSA:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$sa)
763	/ 1139 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LSA),
764	/ 1142 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
765	/ 1144 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
766	/ 1148 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
767	/ 1150 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`2`, // sa
768	/ 1153 / GIR_RootConstrainSelectedInstOperands,
769	/ 1154 / // GIR_Coverage, 2536,
770	/ 1154 / GIR_EraseRootFromParent_Done,
771	/ 1155 / // Label 96: @1155
772	/ 1155 / GIM_Try, /On fail goto//Label 97/ GIMT_Encode4(`1256`),
773	/ 1160 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
774	/ 1164 / GIM_Try_CheckFeatures, /On fail goto//Label 98/ GIMT_Encode4(`1222`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 861 //
775	/ 1171 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
776	/ 1175 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
777	/ 1179 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
778	/ 1183 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
779	/ 1187 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
780	/ 1192 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
781	/ 1196 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
782	/ 1200 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
783	/ 1204 / // MIs[2] Operand 1
784	/ 1204 / // No operand predicates
785	/ 1204 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
786	/* 1206 / // (add:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (shl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$sa)
787	/ 1206 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LSA),
788	/ 1209 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
789	/ 1211 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
790	/ 1215 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
791	/ 1217 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`2`, // sa
792	/ 1220 / GIR_RootConstrainSelectedInstOperands,
793	/ 1221 / // GIR_Coverage, 861,
794	/ 1221 / GIR_EraseRootFromParent_Done,
795	/ 1222 / // Label 98: @1222
796	/ 1222 / GIM_Try_CheckFeatures, /On fail goto//Label 99/ GIMT_Encode4(`1255`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 40 //
797	/ 1229 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
798	/ 1233 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
799	/ 1237 / GIM_CheckAPIntImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
800	/ 1241 / // MIs[1] Operand 1
801	/ 1241 / // No operand predicates
802	/ 1241 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
803	/ 1243 / // (add:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$imm16)
804	/ 1243 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDiu),
805	/ 1246 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
806	/ 1248 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
807	/ 1250 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm16
808	/ 1253 / GIR_RootConstrainSelectedInstOperands,
809	/ 1254 / // GIR_Coverage, 40,
810	/ 1254 / GIR_EraseRootFromParent_Done,
811	/ 1255 / // Label 99: @1255
812	/ 1255 / GIM_Reject,
813	/ 1256 / // Label 97: @1256
814	/ 1256 / GIM_Reject,
815	/ 1257 / // Label 95: @1257
816	/ 1257 / GIM_Try_CheckFeatures, /On fail goto//Label 100/ GIMT_Encode4(`1298`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2294 //
817	/ 1264 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
818	/ 1268 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
819	/ 1272 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
820	/ 1276 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
821	/ 1280 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
822	/ 1284 / // MIs[1] Operand 1
823	/ 1284 / // No operand predicates
824	/ 1284 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
825	/* 1286 / // (add:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
826	/ 1286 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDIUR2_MM),
827	/ 1289 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
828	/ 1291 / GIR_RootToRootCopy, /OpIdx/`1`, // src
829	/ 1293 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
830	/ 1296 / GIR_RootConstrainSelectedInstOperands,
831	/ 1297 / // GIR_Coverage, 2294,
832	/ 1297 / GIR_EraseRootFromParent_Done,
833	/ 1298 / // Label 100: @1298
834	/ 1298 / GIM_Try_CheckFeatures, /On fail goto//Label 101/ GIMT_Encode4(`1339`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2295 //
835	/ 1305 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
836	/ 1309 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
837	/ 1313 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
838	/ 1317 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
839	/ 1321 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
840	/ 1325 / // MIs[1] Operand 1
841	/ 1325 / // No operand predicates
842	/ 1325 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
843	/* 1327 / // (add:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
844	/ 1327 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDIUS5_MM),
845	/ 1330 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
846	/ 1332 / GIR_RootToRootCopy, /OpIdx/`1`, // src
847	/ 1334 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
848	/ 1337 / GIR_RootConstrainSelectedInstOperands,
849	/ 1338 / // GIR_Coverage, 2295,
850	/ 1338 / GIR_EraseRootFromParent_Done,
851	/ 1339 / // Label 101: @1339
852	/ 1339 / GIM_Try_CheckFeatures, /On fail goto//Label 102/ GIMT_Encode4(`1365`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1229 //
853	/ 1346 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
854	/ 1350 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
855	/ 1354 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
856	/ 1358 / // (add:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (ADDU16_MMR6:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
857	/ 1358 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDU16_MMR6),
858	/ 1363 / GIR_RootConstrainSelectedInstOperands,
859	/ 1364 / // GIR_Coverage, 1229,
860	/ 1364 / GIR_Done,
861	/ 1365 / // Label 102: @1365
862	/ 1365 / GIM_Try_CheckFeatures, /On fail goto//Label 103/ GIMT_Encode4(`1391`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 46 //
863	/ 1372 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
864	/ 1376 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
865	/ 1380 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
866	/ 1384 / // (add:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
867	/ 1384 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDu),
868	/ 1389 / GIR_RootConstrainSelectedInstOperands,
869	/ 1390 / // GIR_Coverage, 46,
870	/ 1390 / GIR_Done,
871	/ 1391 / // Label 103: @1391
872	/ 1391 / GIM_Try_CheckFeatures, /On fail goto//Label 104/ GIMT_Encode4(`1417`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1081 //
873	/ 1398 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
874	/ 1402 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
875	/ 1406 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
876	/ 1410 / // (add:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (ADDU16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
877	/ 1410 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDU16_MM),
878	/ 1415 / GIR_RootConstrainSelectedInstOperands,
879	/ 1416 / // GIR_Coverage, 1081,
880	/ 1416 / GIR_Done,
881	/ 1417 / // Label 104: @1417
882	/ 1417 / GIM_Try_CheckFeatures, /On fail goto//Label 105/ GIMT_Encode4(`1443`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1093 //
883	/ 1424 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
884	/ 1428 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
885	/ 1432 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
886	/ 1436 / // (add:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDu_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
887	/ 1436 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDu_MM),
888	/ 1441 / GIR_RootConstrainSelectedInstOperands,
889	/ 1442 / // GIR_Coverage, 1093,
890	/ 1442 / GIR_Done,
891	/ 1443 / // Label 105: @1443
892	/ 1443 / GIM_Try_CheckFeatures, /On fail goto//Label 106/ GIMT_Encode4(`1469`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1954 //
893	/ 1450 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
894	/ 1454 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
895	/ 1458 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
896	/ 1462 / // (add:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (AdduRxRyRz16:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)
897	/ 1462 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AdduRxRyRz16),
898	/ 1467 / GIR_RootConstrainSelectedInstOperands,
899	/ 1468 / // GIR_Coverage, 1954,
900	/ 1468 / GIR_Done,
901	/ 1469 / // Label 106: @1469
902	/ 1469 / GIM_Reject,
903	/ 1470 / // Label 94: @1470
904	/ 1470 / GIM_Reject,
905	/ 1471 / // Label 86: @1471
906	/ 1471 / GIM_Try, /On fail goto//Label 107/ GIMT_Encode4(`1635`),
907	/ 1476 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
908	/ 1479 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
909	/ 1482 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
910	/ 1486 / GIM_Try_CheckFeatures, /On fail goto//Label 108/ GIMT_Encode4(`1548`), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 2537 //
911	/ 1493 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
912	/ 1497 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
913	/ 1501 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
914	/ 1505 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
915	/ 1509 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
916	/ 1514 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
917	/ 1518 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
918	/ 1522 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
919	/ 1526 / // MIs[2] Operand 1
920	/ 1526 / // No operand predicates
921	/ 1526 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
922	/ 1530 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
923	/* 1532 / // (add:{ :[i64] } (shl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ :[i64] }:$rt) => (DLSA:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$sa)
924	/ 1532 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DLSA),
925	/ 1535 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
926	/ 1537 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
927	/ 1541 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
928	/ 1543 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`2`, // sa
929	/ 1546 / GIR_RootConstrainSelectedInstOperands,
930	/ 1547 / // GIR_Coverage, 2537,
931	/ 1547 / GIR_EraseRootFromParent_Done,
932	/ 1548 / // Label 108: @1548
933	/ 1548 / GIM_Try, /On fail goto//Label 109/ GIMT_Encode4(`1634`),
934	/ 1553 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
935	/ 1557 / GIM_Try_CheckFeatures, /On fail goto//Label 110/ GIMT_Encode4(`1615`), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 862 //
936	/ 1564 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
937	/ 1568 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
938	/ 1572 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
939	/ 1576 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
940	/ 1580 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
941	/ 1585 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
942	/ 1589 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
943	/ 1593 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
944	/ 1597 / // MIs[2] Operand 1
945	/ 1597 / // No operand predicates
946	/ 1597 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
947	/* 1599 / // (add:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (shl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$sa)
948	/ 1599 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DLSA),
949	/ 1602 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
950	/ 1604 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
951	/ 1608 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
952	/ 1610 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`2`, // sa
953	/ 1613 / GIR_RootConstrainSelectedInstOperands,
954	/ 1614 / // GIR_Coverage, 862,
955	/ 1614 / GIR_EraseRootFromParent_Done,
956	/ 1615 / // Label 110: @1615
957	/ 1615 / GIM_Try_CheckFeatures, /On fail goto//Label 111/ GIMT_Encode4(`1633`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 229 //
958	/ 1622 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
959	/ 1626 / // (add:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DADDu:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
960	/ 1626 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DADDu),
961	/ 1631 / GIR_RootConstrainSelectedInstOperands,
962	/ 1632 / // GIR_Coverage, 229,
963	/ 1632 / GIR_Done,
964	/ 1633 / // Label 111: @1633
965	/ 1633 / GIM_Reject,
966	/ 1634 / // Label 109: @1634
967	/ 1634 / GIM_Reject,
968	/ 1635 / // Label 107: @1635
969	/ 1635 / GIM_Reject,
970	/ 1636 / // Label 87: @1636
971	/ 1636 / GIM_Try_CheckFeatures, /On fail goto//Label 112/ GIMT_Encode4(`1666`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2059 //
972	/ 1643 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
973	/ 1646 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
974	/ 1649 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
975	/ 1653 / // (add:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b) => (ADDU_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b)
976	/ 1653 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDU_QB),
977	/ 1658 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
978	/ 1664 / GIR_RootConstrainSelectedInstOperands,
979	/ 1665 / // GIR_Coverage, 2059,
980	/ 1665 / GIR_Done,
981	/ 1666 / // Label 112: @1666
982	/ 1666 / GIM_Reject,
983	/ 1667 / // Label 88: @1667
984	/ 1667 / GIM_Try, /On fail goto//Label 113/ GIMT_Encode4(`1819`),
985	/ 1672 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
986	/ 1675 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
987	/ 1678 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
988	/ 1682 / GIM_Try_CheckFeatures, /On fail goto//Label 114/ GIMT_Encode4(`1738`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2538 //
989	/ 1689 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
990	/ 1693 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
991	/ 1697 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
992	/ 1701 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
993	/ 1705 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
994	/ 1710 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
995	/ 1715 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
996	/ 1719 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
997	/* 1721 / // (add:{ :[v16i8] } (mul:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt), MSA128BOpnd:{ :[v16i8] }:$wd_in) => (MADDV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
998	/ 1721 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_B),
999	/ 1724 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1000	/ 1726 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
1001	/ 1728 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1002	/ 1732 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1003	/ 1736 / GIR_RootConstrainSelectedInstOperands,
1004	/ 1737 / // GIR_Coverage, 2538,
1005	/ 1737 / GIR_EraseRootFromParent_Done,
1006	/ 1738 / // Label 114: @1738
1007	/ 1738 / GIM_Try, /On fail goto//Label 115/ GIMT_Encode4(`1818`),
1008	/ 1743 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1009	/ 1747 / GIM_Try_CheckFeatures, /On fail goto//Label 116/ GIMT_Encode4(`1799`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 867 //
1010	/ 1754 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1011	/ 1758 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1012	/ 1762 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
1013	/ 1766 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
1014	/ 1770 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1015	/ 1775 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1016	/ 1780 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1017	/* 1782 / // (add:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, (mul:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)) => (MADDV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1018	/ 1782 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_B),
1019	/ 1785 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1020	/ 1787 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1021	/ 1789 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1022	/ 1793 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1023	/ 1797 / GIR_RootConstrainSelectedInstOperands,
1024	/ 1798 / // GIR_Coverage, 867,
1025	/ 1798 / GIR_EraseRootFromParent_Done,
1026	/ 1799 / // Label 116: @1799
1027	/ 1799 / GIM_Try_CheckFeatures, /On fail goto//Label 117/ GIMT_Encode4(`1817`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 534 //
1028	/ 1806 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1029	/ 1810 / // (add:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ADDV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1030	/ 1810 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDV_B),
1031	/ 1815 / GIR_RootConstrainSelectedInstOperands,
1032	/ 1816 / // GIR_Coverage, 534,
1033	/ 1816 / GIR_Done,
1034	/ 1817 / // Label 117: @1817
1035	/ 1817 / GIM_Reject,
1036	/ 1818 / // Label 115: @1818
1037	/ 1818 / GIM_Reject,
1038	/ 1819 / // Label 113: @1819
1039	/ 1819 / GIM_Reject,
1040	/ 1820 / // Label 89: @1820
1041	/ 1820 / GIM_Try_CheckFeatures, /On fail goto//Label 118/ GIMT_Encode4(`1850`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2053 //
1042	/ 1827 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
1043	/ 1830 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
1044	/ 1833 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
1045	/ 1837 / // (add:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (ADDQ_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)
1046	/ 1837 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDQ_PH),
1047	/ 1842 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1048	/ 1848 / GIR_RootConstrainSelectedInstOperands,
1049	/ 1849 / // GIR_Coverage, 2053,
1050	/ 1849 / GIR_Done,
1051	/ 1850 / // Label 118: @1850
1052	/ 1850 / GIM_Reject,
1053	/ 1851 / // Label 90: @1851
1054	/ 1851 / GIM_Try, /On fail goto//Label 119/ GIMT_Encode4(`2003`),
1055	/ 1856 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1056	/ 1859 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1057	/ 1862 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1058	/ 1866 / GIM_Try_CheckFeatures, /On fail goto//Label 120/ GIMT_Encode4(`1922`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2539 //
1059	/ 1873 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
1060	/ 1877 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1061	/ 1881 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
1062	/ 1885 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
1063	/ 1889 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1064	/ 1894 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1065	/ 1899 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1066	/ 1903 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1067	/* 1905 / // (add:{ :[v8i16] } (mul:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt), MSA128HOpnd:{ :[v8i16] }:$wd_in) => (MADDV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1068	/ 1905 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_H),
1069	/ 1908 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1070	/ 1910 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
1071	/ 1912 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1072	/ 1916 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1073	/ 1920 / GIR_RootConstrainSelectedInstOperands,
1074	/ 1921 / // GIR_Coverage, 2539,
1075	/ 1921 / GIR_EraseRootFromParent_Done,
1076	/ 1922 / // Label 120: @1922
1077	/ 1922 / GIM_Try, /On fail goto//Label 121/ GIMT_Encode4(`2002`),
1078	/ 1927 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1079	/ 1931 / GIM_Try_CheckFeatures, /On fail goto//Label 122/ GIMT_Encode4(`1983`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 868 //
1080	/ 1938 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1081	/ 1942 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1082	/ 1946 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
1083	/ 1950 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
1084	/ 1954 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1085	/ 1959 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1086	/ 1964 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1087	/* 1966 / // (add:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, (mul:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)) => (MADDV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1088	/ 1966 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_H),
1089	/ 1969 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1090	/ 1971 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1091	/ 1973 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1092	/ 1977 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1093	/ 1981 / GIR_RootConstrainSelectedInstOperands,
1094	/ 1982 / // GIR_Coverage, 868,
1095	/ 1982 / GIR_EraseRootFromParent_Done,
1096	/ 1983 / // Label 122: @1983
1097	/ 1983 / GIM_Try_CheckFeatures, /On fail goto//Label 123/ GIMT_Encode4(`2001`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 535 //
1098	/ 1990 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1099	/ 1994 / // (add:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ADDV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1100	/ 1994 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDV_H),
1101	/ 1999 / GIR_RootConstrainSelectedInstOperands,
1102	/ 2000 / // GIR_Coverage, 535,
1103	/ 2000 / GIR_Done,
1104	/ 2001 / // Label 123: @2001
1105	/ 2001 / GIM_Reject,
1106	/ 2002 / // Label 121: @2002
1107	/ 2002 / GIM_Reject,
1108	/ 2003 / // Label 119: @2003
1109	/ 2003 / GIM_Reject,
1110	/ 2004 / // Label 91: @2004
1111	/ 2004 / GIM_Try, /On fail goto//Label 124/ GIMT_Encode4(`2156`),
1112	/ 2009 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1113	/ 2012 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1114	/ 2015 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1115	/ 2019 / GIM_Try_CheckFeatures, /On fail goto//Label 125/ GIMT_Encode4(`2075`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2540 //
1116	/ 2026 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
1117	/ 2030 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1118	/ 2034 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
1119	/ 2038 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
1120	/ 2042 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1121	/ 2047 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1122	/ 2052 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1123	/ 2056 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1124	/* 2058 / // (add:{ :[v4i32] } (mul:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt), MSA128WOpnd:{ :[v4i32] }:$wd_in) => (MADDV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1125	/ 2058 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_W),
1126	/ 2061 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1127	/ 2063 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
1128	/ 2065 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1129	/ 2069 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1130	/ 2073 / GIR_RootConstrainSelectedInstOperands,
1131	/ 2074 / // GIR_Coverage, 2540,
1132	/ 2074 / GIR_EraseRootFromParent_Done,
1133	/ 2075 / // Label 125: @2075
1134	/ 2075 / GIM_Try, /On fail goto//Label 126/ GIMT_Encode4(`2155`),
1135	/ 2080 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1136	/ 2084 / GIM_Try_CheckFeatures, /On fail goto//Label 127/ GIMT_Encode4(`2136`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 869 //
1137	/ 2091 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1138	/ 2095 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1139	/ 2099 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
1140	/ 2103 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
1141	/ 2107 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1142	/ 2112 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1143	/ 2117 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1144	/* 2119 / // (add:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, (mul:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)) => (MADDV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1145	/ 2119 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_W),
1146	/ 2122 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1147	/ 2124 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1148	/ 2126 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1149	/ 2130 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1150	/ 2134 / GIR_RootConstrainSelectedInstOperands,
1151	/ 2135 / // GIR_Coverage, 869,
1152	/ 2135 / GIR_EraseRootFromParent_Done,
1153	/ 2136 / // Label 127: @2136
1154	/ 2136 / GIM_Try_CheckFeatures, /On fail goto//Label 128/ GIMT_Encode4(`2154`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 536 //
1155	/ 2143 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1156	/ 2147 / // (add:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ADDV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1157	/ 2147 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDV_W),
1158	/ 2152 / GIR_RootConstrainSelectedInstOperands,
1159	/ 2153 / // GIR_Coverage, 536,
1160	/ 2153 / GIR_Done,
1161	/ 2154 / // Label 128: @2154
1162	/ 2154 / GIM_Reject,
1163	/ 2155 / // Label 126: @2155
1164	/ 2155 / GIM_Reject,
1165	/ 2156 / // Label 124: @2156
1166	/ 2156 / GIM_Reject,
1167	/ 2157 / // Label 92: @2157
1168	/ 2157 / GIM_Try, /On fail goto//Label 129/ GIMT_Encode4(`2309`),
1169	/ 2162 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1170	/ 2165 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1171	/ 2168 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1172	/ 2172 / GIM_Try_CheckFeatures, /On fail goto//Label 130/ GIMT_Encode4(`2228`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2541 //
1173	/ 2179 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
1174	/ 2183 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1175	/ 2187 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
1176	/ 2191 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
1177	/ 2195 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1178	/ 2200 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1179	/ 2205 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1180	/ 2209 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1181	/* 2211 / // (add:{ :[v2i64] } (mul:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt), MSA128DOpnd:{ :[v2i64] }:$wd_in) => (MADDV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1182	/ 2211 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_D),
1183	/ 2214 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1184	/ 2216 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
1185	/ 2218 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1186	/ 2222 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1187	/ 2226 / GIR_RootConstrainSelectedInstOperands,
1188	/ 2227 / // GIR_Coverage, 2541,
1189	/ 2227 / GIR_EraseRootFromParent_Done,
1190	/ 2228 / // Label 130: @2228
1191	/ 2228 / GIM_Try, /On fail goto//Label 131/ GIMT_Encode4(`2308`),
1192	/ 2233 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1193	/ 2237 / GIM_Try_CheckFeatures, /On fail goto//Label 132/ GIMT_Encode4(`2289`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 870 //
1194	/ 2244 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1195	/ 2248 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1196	/ 2252 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
1197	/ 2256 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
1198	/ 2260 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1199	/ 2265 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1200	/ 2270 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1201	/* 2272 / // (add:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, (mul:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)) => (MADDV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1202	/ 2272 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDV_D),
1203	/ 2275 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1204	/ 2277 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1205	/ 2279 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1206	/ 2283 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1207	/ 2287 / GIR_RootConstrainSelectedInstOperands,
1208	/ 2288 / // GIR_Coverage, 870,
1209	/ 2288 / GIR_EraseRootFromParent_Done,
1210	/ 2289 / // Label 132: @2289
1211	/ 2289 / GIM_Try_CheckFeatures, /On fail goto//Label 133/ GIMT_Encode4(`2307`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 537 //
1212	/ 2296 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1213	/ 2300 / // (add:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ADDV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1214	/ 2300 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ADDV_D),
1215	/ 2305 / GIR_RootConstrainSelectedInstOperands,
1216	/ 2306 / // GIR_Coverage, 537,
1217	/ 2306 / GIR_Done,
1218	/ 2307 / // Label 133: @2307
1219	/ 2307 / GIM_Reject,
1220	/ 2308 / // Label 131: @2308
1221	/ 2308 / GIM_Reject,
1222	/ 2309 / // Label 129: @2309
1223	/ 2309 / GIM_Reject,
1224	/ 2310 / // Label 93: @2310
1225	/ 2310 / GIM_Reject,
1226	/ 2311 / // Label 1: @2311
1227	/ 2311 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 142/ GIMT_Encode4(`2984`),
1228	/ 2322 / /GILLT_s32//Label 134/ GIMT_Encode4(`2354`),
1229	/ 2326 / /GILLT_s64//Label 135/ GIMT_Encode4(`2525`),
1230	/ 2330 / /GILLT_v4s8//Label 136/ GIMT_Encode4(`2558`),
1231	/ 2334 / /GILLT_v16s8//Label 137/ GIMT_Encode4(`2589`),
1232	/ 2338 / /GILLT_v2s16//Label 138/ GIMT_Encode4(`2680`),
1233	/ 2342 / /GILLT_v8s16//Label 139/ GIMT_Encode4(`2711`),
1234	/ 2346 / /GILLT_v4s32//Label 140/ GIMT_Encode4(`2802`),
1235	/ 2350 / /GILLT_v2s64//Label 141/ GIMT_Encode4(`2893`),
1236	/ 2354 / // Label 134: @2354
1237	/ 2354 / GIM_Try, /On fail goto//Label 143/ GIMT_Encode4(`2524`),
1238	/ 2359 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1239	/ 2362 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1240	/ 2365 / GIM_Try_CheckFeatures, /On fail goto//Label 144/ GIMT_Encode4(`2393`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1953 //
1241	/ 2372 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1242	/ 2376 / GIM_CheckConstantInt8, /MI/`0`, /Op/`1`, `0`,
1243	/ 2380 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1244	/ 2384 / // (sub:{ :[i32] } 0:{ :[i32] }, CPU16Regs:{ :[i32] }:$r) => (NegRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$r)*
1245	/ 2384 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NegRxRy16),
1246	/ 2387 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
1247	/ 2389 / GIR_RootToRootCopy, /OpIdx/`2`, // r
1248	/ 2391 / GIR_RootConstrainSelectedInstOperands,
1249	/ 2392 / // GIR_Coverage, 1953,
1250	/ 2392 / GIR_EraseRootFromParent_Done,
1251	/ 2393 / // Label 144: @2393
1252	/ 2393 / GIM_Try_CheckFeatures, /On fail goto//Label 145/ GIMT_Encode4(`2419`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1231 //
1253	/ 2400 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1254	/ 2404 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1255	/ 2408 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1256	/ 2412 / // (sub:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (SUBU16_MMR6:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
1257	/ 2412 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBU16_MMR6),
1258	/ 2417 / GIR_RootConstrainSelectedInstOperands,
1259	/ 2418 / // GIR_Coverage, 1231,
1260	/ 2418 / GIR_Done,
1261	/ 2419 / // Label 145: @2419
1262	/ 2419 / GIM_Try_CheckFeatures, /On fail goto//Label 146/ GIMT_Encode4(`2445`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 47 //
1263	/ 2426 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1264	/ 2430 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1265	/ 2434 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1266	/ 2438 / // (sub:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1267	/ 2438 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBu),
1268	/ 2443 / GIR_RootConstrainSelectedInstOperands,
1269	/ 2444 / // GIR_Coverage, 47,
1270	/ 2444 / GIR_Done,
1271	/ 2445 / // Label 146: @2445
1272	/ 2445 / GIM_Try_CheckFeatures, /On fail goto//Label 147/ GIMT_Encode4(`2471`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1085 //
1273	/ 2452 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1274	/ 2456 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1275	/ 2460 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
1276	/ 2464 / // (sub:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (SUBU16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
1277	/ 2464 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBU16_MM),
1278	/ 2469 / GIR_RootConstrainSelectedInstOperands,
1279	/ 2470 / // GIR_Coverage, 1085,
1280	/ 2470 / GIR_Done,
1281	/ 2471 / // Label 147: @2471
1282	/ 2471 / GIM_Try_CheckFeatures, /On fail goto//Label 148/ GIMT_Encode4(`2497`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1094 //
1283	/ 2478 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1284	/ 2482 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1285	/ 2486 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1286	/ 2490 / // (sub:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBu_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1287	/ 2490 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBu_MM),
1288	/ 2495 / GIR_RootConstrainSelectedInstOperands,
1289	/ 2496 / // GIR_Coverage, 1094,
1290	/ 2496 / GIR_Done,
1291	/ 2497 / // Label 148: @2497
1292	/ 2497 / GIM_Try_CheckFeatures, /On fail goto//Label 149/ GIMT_Encode4(`2523`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1958 //
1293	/ 2504 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1294	/ 2508 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1295	/ 2512 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1296	/ 2516 / // (sub:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (SubuRxRyRz16:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)
1297	/ 2516 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SubuRxRyRz16),
1298	/ 2521 / GIR_RootConstrainSelectedInstOperands,
1299	/ 2522 / // GIR_Coverage, 1958,
1300	/ 2522 / GIR_Done,
1301	/ 2523 / // Label 149: @2523
1302	/ 2523 / GIM_Reject,
1303	/ 2524 / // Label 143: @2524
1304	/ 2524 / GIM_Reject,
1305	/ 2525 / // Label 135: @2525
1306	/ 2525 / GIM_Try_CheckFeatures, /On fail goto//Label 150/ GIMT_Encode4(`2557`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 230 //
1307	/ 2532 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
1308	/ 2535 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
1309	/ 2538 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1310	/ 2542 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1311	/ 2546 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1312	/ 2550 / // (sub:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DSUBu:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
1313	/ 2550 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DSUBu),
1314	/ 2555 / GIR_RootConstrainSelectedInstOperands,
1315	/ 2556 / // GIR_Coverage, 230,
1316	/ 2556 / GIR_Done,
1317	/ 2557 / // Label 150: @2557
1318	/ 2557 / GIM_Reject,
1319	/ 2558 / // Label 136: @2558
1320	/ 2558 / GIM_Try_CheckFeatures, /On fail goto//Label 151/ GIMT_Encode4(`2588`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2061 //
1321	/ 2565 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
1322	/ 2568 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
1323	/ 2571 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
1324	/ 2575 / // (sub:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b) => (SUBU_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b)
1325	/ 2575 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBU_QB),
1326	/ 2580 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1327	/ 2586 / GIR_RootConstrainSelectedInstOperands,
1328	/ 2587 / // GIR_Coverage, 2061,
1329	/ 2587 / GIR_Done,
1330	/ 2588 / // Label 151: @2588
1331	/ 2588 / GIM_Reject,
1332	/ 2589 / // Label 137: @2589
1333	/ 2589 / GIM_Try, /On fail goto//Label 152/ GIMT_Encode4(`2679`),
1334	/ 2594 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
1335	/ 2597 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
1336	/ 2600 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1337	/ 2604 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1338	/ 2608 / GIM_Try_CheckFeatures, /On fail goto//Label 153/ GIMT_Encode4(`2660`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 923 //
1339	/ 2615 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1340	/ 2619 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1341	/ 2623 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
1342	/ 2627 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
1343	/ 2631 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1344	/ 2636 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1345	/ 2641 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1346	/* 2643 / // (sub:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, (mul:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)) => (MSUBV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1347	/ 2643 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBV_B),
1348	/ 2646 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1349	/ 2648 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1350	/ 2650 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1351	/ 2654 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1352	/ 2658 / GIR_RootConstrainSelectedInstOperands,
1353	/ 2659 / // GIR_Coverage, 923,
1354	/ 2659 / GIR_EraseRootFromParent_Done,
1355	/ 2660 / // Label 153: @2660
1356	/ 2660 / GIM_Try_CheckFeatures, /On fail goto//Label 154/ GIMT_Encode4(`2678`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1052 //
1357	/ 2667 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1358	/ 2671 / // (sub:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SUBV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1359	/ 2671 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBV_B),
1360	/ 2676 / GIR_RootConstrainSelectedInstOperands,
1361	/ 2677 / // GIR_Coverage, 1052,
1362	/ 2677 / GIR_Done,
1363	/ 2678 / // Label 154: @2678
1364	/ 2678 / GIM_Reject,
1365	/ 2679 / // Label 152: @2679
1366	/ 2679 / GIM_Reject,
1367	/ 2680 / // Label 138: @2680
1368	/ 2680 / GIM_Try_CheckFeatures, /On fail goto//Label 155/ GIMT_Encode4(`2710`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2055 //
1369	/ 2687 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
1370	/ 2690 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
1371	/ 2693 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
1372	/ 2697 / // (sub:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (SUBQ_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)
1373	/ 2697 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBQ_PH),
1374	/ 2702 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1375	/ 2708 / GIR_RootConstrainSelectedInstOperands,
1376	/ 2709 / // GIR_Coverage, 2055,
1377	/ 2709 / GIR_Done,
1378	/ 2710 / // Label 155: @2710
1379	/ 2710 / GIM_Reject,
1380	/ 2711 / // Label 139: @2711
1381	/ 2711 / GIM_Try, /On fail goto//Label 156/ GIMT_Encode4(`2801`),
1382	/ 2716 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1383	/ 2719 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1384	/ 2722 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1385	/ 2726 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1386	/ 2730 / GIM_Try_CheckFeatures, /On fail goto//Label 157/ GIMT_Encode4(`2782`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 924 //
1387	/ 2737 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1388	/ 2741 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1389	/ 2745 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
1390	/ 2749 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
1391	/ 2753 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1392	/ 2758 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1393	/ 2763 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1394	/* 2765 / // (sub:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, (mul:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)) => (MSUBV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1395	/ 2765 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBV_H),
1396	/ 2768 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1397	/ 2770 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1398	/ 2772 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1399	/ 2776 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1400	/ 2780 / GIR_RootConstrainSelectedInstOperands,
1401	/ 2781 / // GIR_Coverage, 924,
1402	/ 2781 / GIR_EraseRootFromParent_Done,
1403	/ 2782 / // Label 157: @2782
1404	/ 2782 / GIM_Try_CheckFeatures, /On fail goto//Label 158/ GIMT_Encode4(`2800`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1053 //
1405	/ 2789 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1406	/ 2793 / // (sub:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SUBV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1407	/ 2793 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBV_H),
1408	/ 2798 / GIR_RootConstrainSelectedInstOperands,
1409	/ 2799 / // GIR_Coverage, 1053,
1410	/ 2799 / GIR_Done,
1411	/ 2800 / // Label 158: @2800
1412	/ 2800 / GIM_Reject,
1413	/ 2801 / // Label 156: @2801
1414	/ 2801 / GIM_Reject,
1415	/ 2802 / // Label 140: @2802
1416	/ 2802 / GIM_Try, /On fail goto//Label 159/ GIMT_Encode4(`2892`),
1417	/ 2807 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1418	/ 2810 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1419	/ 2813 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1420	/ 2817 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1421	/ 2821 / GIM_Try_CheckFeatures, /On fail goto//Label 160/ GIMT_Encode4(`2873`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 925 //
1422	/ 2828 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1423	/ 2832 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1424	/ 2836 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
1425	/ 2840 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
1426	/ 2844 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1427	/ 2849 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1428	/ 2854 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1429	/* 2856 / // (sub:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, (mul:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)) => (MSUBV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1430	/ 2856 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBV_W),
1431	/ 2859 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1432	/ 2861 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1433	/ 2863 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1434	/ 2867 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1435	/ 2871 / GIR_RootConstrainSelectedInstOperands,
1436	/ 2872 / // GIR_Coverage, 925,
1437	/ 2872 / GIR_EraseRootFromParent_Done,
1438	/ 2873 / // Label 160: @2873
1439	/ 2873 / GIM_Try_CheckFeatures, /On fail goto//Label 161/ GIMT_Encode4(`2891`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1054 //
1440	/ 2880 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1441	/ 2884 / // (sub:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SUBV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1442	/ 2884 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBV_W),
1443	/ 2889 / GIR_RootConstrainSelectedInstOperands,
1444	/ 2890 / // GIR_Coverage, 1054,
1445	/ 2890 / GIR_Done,
1446	/ 2891 / // Label 161: @2891
1447	/ 2891 / GIM_Reject,
1448	/ 2892 / // Label 159: @2892
1449	/ 2892 / GIM_Reject,
1450	/ 2893 / // Label 141: @2893
1451	/ 2893 / GIM_Try, /On fail goto//Label 162/ GIMT_Encode4(`2983`),
1452	/ 2898 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1453	/ 2901 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1454	/ 2904 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1455	/ 2908 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1456	/ 2912 / GIM_Try_CheckFeatures, /On fail goto//Label 163/ GIMT_Encode4(`2964`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 926 //
1457	/ 2919 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
1458	/ 2923 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
1459	/ 2927 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
1460	/ 2931 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
1461	/ 2935 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1462	/ 2940 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1463	/ 2945 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
1464	/* 2947 / // (sub:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, (mul:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)) => (MSUBV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1465	/ 2947 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBV_D),
1466	/ 2950 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
1467	/ 2952 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
1468	/ 2954 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
1469	/ 2958 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
1470	/ 2962 / GIR_RootConstrainSelectedInstOperands,
1471	/ 2963 / // GIR_Coverage, 926,
1472	/ 2963 / GIR_EraseRootFromParent_Done,
1473	/ 2964 / // Label 163: @2964
1474	/ 2964 / GIM_Try_CheckFeatures, /On fail goto//Label 164/ GIMT_Encode4(`2982`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1055 //
1475	/ 2971 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1476	/ 2975 / // (sub:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SUBV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1477	/ 2975 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SUBV_D),
1478	/ 2980 / GIR_RootConstrainSelectedInstOperands,
1479	/ 2981 / // GIR_Coverage, 1055,
1480	/ 2981 / GIR_Done,
1481	/ 2982 / // Label 164: @2982
1482	/ 2982 / GIM_Reject,
1483	/ 2983 / // Label 162: @2983
1484	/ 2983 / GIM_Reject,
1485	/ 2984 / // Label 142: @2984
1486	/ 2984 / GIM_Reject,
1487	/ 2985 / // Label 2: @2985
1488	/ 2985 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 172/ GIMT_Encode4(`3423`),
1489	/ 2996 / /GILLT_s32//Label 165/ GIMT_Encode4(`3028`),
1490	/ 3000 / /GILLT_s64//Label 166/ GIMT_Encode4(`3177`), GIMT_Encode4(`0`),
1491	/ 3008 / /GILLT_v16s8//Label 167/ GIMT_Encode4(`3260`),
1492	/ 3012 / /GILLT_v2s16//Label 168/ GIMT_Encode4(`3293`),
1493	/ 3016 / /GILLT_v8s16//Label 169/ GIMT_Encode4(`3324`),
1494	/ 3020 / /GILLT_v4s32//Label 170/ GIMT_Encode4(`3357`),
1495	/ 3024 / /GILLT_v2s64//Label 171/ GIMT_Encode4(`3390`),
1496	/ 3028 / // Label 165: @3028
1497	/ 3028 / GIM_Try, /On fail goto//Label 173/ GIMT_Encode4(`3176`),
1498	/ 3033 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1499	/ 3036 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1500	/ 3039 / GIM_Try, /On fail goto//Label 174/ GIMT_Encode4(`3137`),
1501	/ 3044 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1502	/ 3048 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1503	/ 3052 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1504	/ 3056 / GIM_Try_CheckFeatures, /On fail goto//Label 175/ GIMT_Encode4(`3082`), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 48 //
1505	/ 3063 / // (mul:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUL:{ :[i32] }:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
1506	/ 3063 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUL),
1507	/ 3068 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1508	/ 3074 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1509	/ 3080 / GIR_RootConstrainSelectedInstOperands,
1510	/ 3081 / // GIR_Coverage, 48,
1511	/ 3081 / GIR_Done,
1512	/ 3082 / // Label 175: @3082
1513	/ 3082 / GIM_Try_CheckFeatures, /On fail goto//Label 176/ GIMT_Encode4(`3096`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 359 //
1514	/ 3089 / // (mul:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUL_R6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1515	/ 3089 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUL_R6),
1516	/ 3094 / GIR_RootConstrainSelectedInstOperands,
1517	/ 3095 / // GIR_Coverage, 359,
1518	/ 3095 / GIR_Done,
1519	/ 3096 / // Label 176: @3096
1520	/ 3096 / GIM_Try_CheckFeatures, /On fail goto//Label 177/ GIMT_Encode4(`3122`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1095 //
1521	/ 3103 / // (mul:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUL_MM:{ :[i32] }:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
1522	/ 3103 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUL_MM),
1523	/ 3108 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1524	/ 3114 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1525	/ 3120 / GIR_RootConstrainSelectedInstOperands,
1526	/ 3121 / // GIR_Coverage, 1095,
1527	/ 3121 / GIR_Done,
1528	/ 3122 / // Label 177: @3122
1529	/ 3122 / GIM_Try_CheckFeatures, /On fail goto//Label 178/ GIMT_Encode4(`3136`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1200 //
1530	/ 3129 / // (mul:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUL_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1531	/ 3129 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUL_MMR6),
1532	/ 3134 / GIR_RootConstrainSelectedInstOperands,
1533	/ 3135 / // GIR_Coverage, 1200,
1534	/ 3135 / GIR_Done,
1535	/ 3136 / // Label 178: @3136
1536	/ 3136 / GIM_Reject,
1537	/ 3137 / // Label 174: @3137
1538	/ 3137 / GIM_Try_CheckFeatures, /On fail goto//Label 179/ GIMT_Encode4(`3175`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1956 //
1539	/ 3144 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1540	/ 3148 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1541	/ 3152 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1542	/ 3156 / // (mul:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (MultRxRyRz16:{ :[i32] }:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)*
1543	/ 3156 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MultRxRyRz16),
1544	/ 3161 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1545	/ 3167 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1546	/ 3173 / GIR_RootConstrainSelectedInstOperands,
1547	/ 3174 / // GIR_Coverage, 1956,
1548	/ 3174 / GIR_Done,
1549	/ 3175 / // Label 179: @3175
1550	/ 3175 / GIM_Reject,
1551	/ 3176 / // Label 173: @3176
1552	/ 3176 / GIM_Reject,
1553	/ 3177 / // Label 166: @3177
1554	/ 3177 / GIM_Try, /On fail goto//Label 180/ GIMT_Encode4(`3259`),
1555	/ 3182 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
1556	/ 3185 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
1557	/ 3188 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1558	/ 3192 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1559	/ 3196 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1560	/ 3200 / GIM_Try_CheckFeatures, /On fail goto//Label 181/ GIMT_Encode4(`3244`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 301 //
1561	/ 3207 / // (mul:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMUL:{ :[i64] }:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)*
1562	/ 3207 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMUL),
1563	/ 3212 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1564	/ 3218 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1565	/ 3224 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::P0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1566	/ 3230 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::P1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1567	/ 3236 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::P2), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1568	/ 3242 / GIR_RootConstrainSelectedInstOperands,
1569	/ 3243 / // GIR_Coverage, 301,
1570	/ 3243 / GIR_Done,
1571	/ 3244 / // Label 181: @3244
1572	/ 3244 / GIM_Try_CheckFeatures, /On fail goto//Label 182/ GIMT_Encode4(`3258`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 374 //
1573	/ 3251 / // (mul:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMUL_R6:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
1574	/ 3251 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMUL_R6),
1575	/ 3256 / GIR_RootConstrainSelectedInstOperands,
1576	/ 3257 / // GIR_Coverage, 374,
1577	/ 3257 / GIR_Done,
1578	/ 3258 / // Label 182: @3258
1579	/ 3258 / GIM_Reject,
1580	/ 3259 / // Label 180: @3259
1581	/ 3259 / GIM_Reject,
1582	/ 3260 / // Label 167: @3260
1583	/ 3260 / GIM_Try_CheckFeatures, /On fail goto//Label 183/ GIMT_Encode4(`3292`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 931 //
1584	/ 3267 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
1585	/ 3270 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
1586	/ 3273 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1587	/ 3277 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1588	/ 3281 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1589	/ 3285 / // (mul:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MULV_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1590	/ 3285 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MULV_B),
1591	/ 3290 / GIR_RootConstrainSelectedInstOperands,
1592	/ 3291 / // GIR_Coverage, 931,
1593	/ 3291 / GIR_Done,
1594	/ 3292 / // Label 183: @3292
1595	/ 3292 / GIM_Reject,
1596	/ 3293 / // Label 168: @3293
1597	/ 3293 / GIM_Try_CheckFeatures, /On fail goto//Label 184/ GIMT_Encode4(`3323`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2057 //
1598	/ 3300 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
1599	/ 3303 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
1600	/ 3306 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
1601	/ 3310 / // (mul:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (MUL_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)
1602	/ 3310 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUL_PH),
1603	/ 3315 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1604	/ 3321 / GIR_RootConstrainSelectedInstOperands,
1605	/ 3322 / // GIR_Coverage, 2057,
1606	/ 3322 / GIR_Done,
1607	/ 3323 / // Label 184: @3323
1608	/ 3323 / GIM_Reject,
1609	/ 3324 / // Label 169: @3324
1610	/ 3324 / GIM_Try_CheckFeatures, /On fail goto//Label 185/ GIMT_Encode4(`3356`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 932 //
1611	/ 3331 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1612	/ 3334 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1613	/ 3337 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1614	/ 3341 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1615	/ 3345 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1616	/ 3349 / // (mul:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MULV_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1617	/ 3349 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MULV_H),
1618	/ 3354 / GIR_RootConstrainSelectedInstOperands,
1619	/ 3355 / // GIR_Coverage, 932,
1620	/ 3355 / GIR_Done,
1621	/ 3356 / // Label 185: @3356
1622	/ 3356 / GIM_Reject,
1623	/ 3357 / // Label 170: @3357
1624	/ 3357 / GIM_Try_CheckFeatures, /On fail goto//Label 186/ GIMT_Encode4(`3389`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 933 //
1625	/ 3364 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1626	/ 3367 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1627	/ 3370 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1628	/ 3374 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1629	/ 3378 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1630	/ 3382 / // (mul:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MULV_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1631	/ 3382 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MULV_W),
1632	/ 3387 / GIR_RootConstrainSelectedInstOperands,
1633	/ 3388 / // GIR_Coverage, 933,
1634	/ 3388 / GIR_Done,
1635	/ 3389 / // Label 186: @3389
1636	/ 3389 / GIM_Reject,
1637	/ 3390 / // Label 171: @3390
1638	/ 3390 / GIM_Try_CheckFeatures, /On fail goto//Label 187/ GIMT_Encode4(`3422`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 934 //
1639	/ 3397 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1640	/ 3400 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1641	/ 3403 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1642	/ 3407 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1643	/ 3411 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1644	/ 3415 / // (mul:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MULV_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1645	/ 3415 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MULV_D),
1646	/ 3420 / GIR_RootConstrainSelectedInstOperands,
1647	/ 3421 / // GIR_Coverage, 934,
1648	/ 3421 / GIR_Done,
1649	/ 3422 / // Label 187: @3422
1650	/ 3422 / GIM_Reject,
1651	/ 3423 / // Label 172: @3423
1652	/ 3423 / GIM_Reject,
1653	/ 3424 / // Label 3: @3424
1654	/ 3424 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 194/ GIMT_Encode4(`3685`),
1655	/ 3435 / /GILLT_s32//Label 188/ GIMT_Encode4(`3467`),
1656	/ 3439 / /GILLT_s64//Label 189/ GIMT_Encode4(`3520`), GIMT_Encode4(`0`),
1657	/ 3447 / /GILLT_v16s8//Label 190/ GIMT_Encode4(`3553`), GIMT_Encode4(`0`),
1658	/ 3455 / /GILLT_v8s16//Label 191/ GIMT_Encode4(`3586`),
1659	/ 3459 / /GILLT_v4s32//Label 192/ GIMT_Encode4(`3619`),
1660	/ 3463 / /GILLT_v2s64//Label 193/ GIMT_Encode4(`3652`),
1661	/ 3467 / // Label 188: @3467
1662	/ 3467 / GIM_Try, /On fail goto//Label 195/ GIMT_Encode4(`3519`),
1663	/ 3472 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1664	/ 3475 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1665	/ 3478 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1666	/ 3482 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1667	/ 3486 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1668	/ 3490 / GIM_Try_CheckFeatures, /On fail goto//Label 196/ GIMT_Encode4(`3504`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 353 //
1669	/ 3497 / // (sdiv:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (DIV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1670	/ 3497 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV),
1671	/ 3502 / GIR_RootConstrainSelectedInstOperands,
1672	/ 3503 / // GIR_Coverage, 353,
1673	/ 3503 / GIR_Done,
1674	/ 3504 / // Label 196: @3504
1675	/ 3504 / GIM_Try_CheckFeatures, /On fail goto//Label 197/ GIMT_Encode4(`3518`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1193 //
1676	/ 3511 / // (sdiv:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (DIV_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1677	/ 3511 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_MMR6),
1678	/ 3516 / GIR_RootConstrainSelectedInstOperands,
1679	/ 3517 / // GIR_Coverage, 1193,
1680	/ 3517 / GIR_Done,
1681	/ 3518 / // Label 197: @3518
1682	/ 3518 / GIM_Reject,
1683	/ 3519 / // Label 195: @3519
1684	/ 3519 / GIM_Reject,
1685	/ 3520 / // Label 189: @3520
1686	/ 3520 / GIM_Try_CheckFeatures, /On fail goto//Label 198/ GIMT_Encode4(`3552`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 368 //
1687	/ 3527 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
1688	/ 3530 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
1689	/ 3533 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1690	/ 3537 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1691	/ 3541 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1692	/ 3545 / // (sdiv:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DDIV:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
1693	/ 3545 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DDIV),
1694	/ 3550 / GIR_RootConstrainSelectedInstOperands,
1695	/ 3551 / // GIR_Coverage, 368,
1696	/ 3551 / GIR_Done,
1697	/ 3552 / // Label 198: @3552
1698	/ 3552 / GIM_Reject,
1699	/ 3553 / // Label 190: @3553
1700	/ 3553 / GIM_Try_CheckFeatures, /On fail goto//Label 199/ GIMT_Encode4(`3585`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 671 //
1701	/ 3560 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
1702	/ 3563 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
1703	/ 3566 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1704	/ 3570 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1705	/ 3574 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1706	/ 3578 / // (sdiv:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DIV_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1707	/ 3578 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_S_B),
1708	/ 3583 / GIR_RootConstrainSelectedInstOperands,
1709	/ 3584 / // GIR_Coverage, 671,
1710	/ 3584 / GIR_Done,
1711	/ 3585 / // Label 199: @3585
1712	/ 3585 / GIM_Reject,
1713	/ 3586 / // Label 191: @3586
1714	/ 3586 / GIM_Try_CheckFeatures, /On fail goto//Label 200/ GIMT_Encode4(`3618`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 672 //
1715	/ 3593 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1716	/ 3596 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1717	/ 3599 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1718	/ 3603 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1719	/ 3607 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1720	/ 3611 / // (sdiv:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DIV_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1721	/ 3611 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_S_H),
1722	/ 3616 / GIR_RootConstrainSelectedInstOperands,
1723	/ 3617 / // GIR_Coverage, 672,
1724	/ 3617 / GIR_Done,
1725	/ 3618 / // Label 200: @3618
1726	/ 3618 / GIM_Reject,
1727	/ 3619 / // Label 192: @3619
1728	/ 3619 / GIM_Try_CheckFeatures, /On fail goto//Label 201/ GIMT_Encode4(`3651`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 673 //
1729	/ 3626 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1730	/ 3629 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1731	/ 3632 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1732	/ 3636 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1733	/ 3640 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1734	/ 3644 / // (sdiv:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DIV_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1735	/ 3644 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_S_W),
1736	/ 3649 / GIR_RootConstrainSelectedInstOperands,
1737	/ 3650 / // GIR_Coverage, 673,
1738	/ 3650 / GIR_Done,
1739	/ 3651 / // Label 201: @3651
1740	/ 3651 / GIM_Reject,
1741	/ 3652 / // Label 193: @3652
1742	/ 3652 / GIM_Try_CheckFeatures, /On fail goto//Label 202/ GIMT_Encode4(`3684`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 674 //
1743	/ 3659 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1744	/ 3662 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1745	/ 3665 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1746	/ 3669 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1747	/ 3673 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1748	/ 3677 / // (sdiv:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (DIV_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1749	/ 3677 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_S_D),
1750	/ 3682 / GIR_RootConstrainSelectedInstOperands,
1751	/ 3683 / // GIR_Coverage, 674,
1752	/ 3683 / GIR_Done,
1753	/ 3684 / // Label 202: @3684
1754	/ 3684 / GIM_Reject,
1755	/ 3685 / // Label 194: @3685
1756	/ 3685 / GIM_Reject,
1757	/ 3686 / // Label 4: @3686
1758	/ 3686 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 209/ GIMT_Encode4(`3947`),
1759	/ 3697 / /GILLT_s32//Label 203/ GIMT_Encode4(`3729`),
1760	/ 3701 / /GILLT_s64//Label 204/ GIMT_Encode4(`3782`), GIMT_Encode4(`0`),
1761	/ 3709 / /GILLT_v16s8//Label 205/ GIMT_Encode4(`3815`), GIMT_Encode4(`0`),
1762	/ 3717 / /GILLT_v8s16//Label 206/ GIMT_Encode4(`3848`),
1763	/ 3721 / /GILLT_v4s32//Label 207/ GIMT_Encode4(`3881`),
1764	/ 3725 / /GILLT_v2s64//Label 208/ GIMT_Encode4(`3914`),
1765	/ 3729 / // Label 203: @3729
1766	/ 3729 / GIM_Try, /On fail goto//Label 210/ GIMT_Encode4(`3781`),
1767	/ 3734 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1768	/ 3737 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1769	/ 3740 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1770	/ 3744 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1771	/ 3748 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1772	/ 3752 / GIM_Try_CheckFeatures, /On fail goto//Label 211/ GIMT_Encode4(`3766`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 354 //
1773	/ 3759 / // (udiv:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (DIVU:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1774	/ 3759 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIVU),
1775	/ 3764 / GIR_RootConstrainSelectedInstOperands,
1776	/ 3765 / // GIR_Coverage, 354,
1777	/ 3765 / GIR_Done,
1778	/ 3766 / // Label 211: @3766
1779	/ 3766 / GIM_Try_CheckFeatures, /On fail goto//Label 212/ GIMT_Encode4(`3780`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1194 //
1780	/ 3773 / // (udiv:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (DIVU_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1781	/ 3773 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIVU_MMR6),
1782	/ 3778 / GIR_RootConstrainSelectedInstOperands,
1783	/ 3779 / // GIR_Coverage, 1194,
1784	/ 3779 / GIR_Done,
1785	/ 3780 / // Label 212: @3780
1786	/ 3780 / GIM_Reject,
1787	/ 3781 / // Label 210: @3781
1788	/ 3781 / GIM_Reject,
1789	/ 3782 / // Label 204: @3782
1790	/ 3782 / GIM_Try_CheckFeatures, /On fail goto//Label 213/ GIMT_Encode4(`3814`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 369 //
1791	/ 3789 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
1792	/ 3792 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
1793	/ 3795 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1794	/ 3799 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1795	/ 3803 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1796	/ 3807 / // (udiv:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DDIVU:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
1797	/ 3807 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DDIVU),
1798	/ 3812 / GIR_RootConstrainSelectedInstOperands,
1799	/ 3813 / // GIR_Coverage, 369,
1800	/ 3813 / GIR_Done,
1801	/ 3814 / // Label 213: @3814
1802	/ 3814 / GIM_Reject,
1803	/ 3815 / // Label 205: @3815
1804	/ 3815 / GIM_Try_CheckFeatures, /On fail goto//Label 214/ GIMT_Encode4(`3847`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 675 //
1805	/ 3822 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
1806	/ 3825 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
1807	/ 3828 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1808	/ 3832 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1809	/ 3836 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1810	/ 3840 / // (udiv:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DIV_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1811	/ 3840 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_U_B),
1812	/ 3845 / GIR_RootConstrainSelectedInstOperands,
1813	/ 3846 / // GIR_Coverage, 675,
1814	/ 3846 / GIR_Done,
1815	/ 3847 / // Label 214: @3847
1816	/ 3847 / GIM_Reject,
1817	/ 3848 / // Label 206: @3848
1818	/ 3848 / GIM_Try_CheckFeatures, /On fail goto//Label 215/ GIMT_Encode4(`3880`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 676 //
1819	/ 3855 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1820	/ 3858 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1821	/ 3861 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1822	/ 3865 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1823	/ 3869 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1824	/ 3873 / // (udiv:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DIV_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1825	/ 3873 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_U_H),
1826	/ 3878 / GIR_RootConstrainSelectedInstOperands,
1827	/ 3879 / // GIR_Coverage, 676,
1828	/ 3879 / GIR_Done,
1829	/ 3880 / // Label 215: @3880
1830	/ 3880 / GIM_Reject,
1831	/ 3881 / // Label 207: @3881
1832	/ 3881 / GIM_Try_CheckFeatures, /On fail goto//Label 216/ GIMT_Encode4(`3913`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 677 //
1833	/ 3888 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1834	/ 3891 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1835	/ 3894 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1836	/ 3898 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1837	/ 3902 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1838	/ 3906 / // (udiv:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DIV_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1839	/ 3906 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_U_W),
1840	/ 3911 / GIR_RootConstrainSelectedInstOperands,
1841	/ 3912 / // GIR_Coverage, 677,
1842	/ 3912 / GIR_Done,
1843	/ 3913 / // Label 216: @3913
1844	/ 3913 / GIM_Reject,
1845	/ 3914 / // Label 208: @3914
1846	/ 3914 / GIM_Try_CheckFeatures, /On fail goto//Label 217/ GIMT_Encode4(`3946`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 678 //
1847	/ 3921 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1848	/ 3924 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1849	/ 3927 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1850	/ 3931 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1851	/ 3935 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1852	/ 3939 / // (udiv:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (DIV_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1853	/ 3939 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DIV_U_D),
1854	/ 3944 / GIR_RootConstrainSelectedInstOperands,
1855	/ 3945 / // GIR_Coverage, 678,
1856	/ 3945 / GIR_Done,
1857	/ 3946 / // Label 217: @3946
1858	/ 3946 / GIM_Reject,
1859	/ 3947 / // Label 209: @3947
1860	/ 3947 / GIM_Reject,
1861	/ 3948 / // Label 5: @3948
1862	/ 3948 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 224/ GIMT_Encode4(`4209`),
1863	/ 3959 / /GILLT_s32//Label 218/ GIMT_Encode4(`3991`),
1864	/ 3963 / /GILLT_s64//Label 219/ GIMT_Encode4(`4044`), GIMT_Encode4(`0`),
1865	/ 3971 / /GILLT_v16s8//Label 220/ GIMT_Encode4(`4077`), GIMT_Encode4(`0`),
1866	/ 3979 / /GILLT_v8s16//Label 221/ GIMT_Encode4(`4110`),
1867	/ 3983 / /GILLT_v4s32//Label 222/ GIMT_Encode4(`4143`),
1868	/ 3987 / /GILLT_v2s64//Label 223/ GIMT_Encode4(`4176`),
1869	/ 3991 / // Label 218: @3991
1870	/ 3991 / GIM_Try, /On fail goto//Label 225/ GIMT_Encode4(`4043`),
1871	/ 3996 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1872	/ 3999 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1873	/ 4002 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1874	/ 4006 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1875	/ 4010 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1876	/ 4014 / GIM_Try_CheckFeatures, /On fail goto//Label 226/ GIMT_Encode4(`4028`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 355 //
1877	/ 4021 / // (srem:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MOD:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1878	/ 4021 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD),
1879	/ 4026 / GIR_RootConstrainSelectedInstOperands,
1880	/ 4027 / // GIR_Coverage, 355,
1881	/ 4027 / GIR_Done,
1882	/ 4028 / // Label 226: @4028
1883	/ 4028 / GIM_Try_CheckFeatures, /On fail goto//Label 227/ GIMT_Encode4(`4042`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1198 //
1884	/ 4035 / // (srem:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MOD_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1885	/ 4035 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_MMR6),
1886	/ 4040 / GIR_RootConstrainSelectedInstOperands,
1887	/ 4041 / // GIR_Coverage, 1198,
1888	/ 4041 / GIR_Done,
1889	/ 4042 / // Label 227: @4042
1890	/ 4042 / GIM_Reject,
1891	/ 4043 / // Label 225: @4043
1892	/ 4043 / GIM_Reject,
1893	/ 4044 / // Label 219: @4044
1894	/ 4044 / GIM_Try_CheckFeatures, /On fail goto//Label 228/ GIMT_Encode4(`4076`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 370 //
1895	/ 4051 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
1896	/ 4054 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
1897	/ 4057 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1898	/ 4061 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1899	/ 4065 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
1900	/ 4069 / // (srem:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMOD:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
1901	/ 4069 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMOD),
1902	/ 4074 / GIR_RootConstrainSelectedInstOperands,
1903	/ 4075 / // GIR_Coverage, 370,
1904	/ 4075 / GIR_Done,
1905	/ 4076 / // Label 228: @4076
1906	/ 4076 / GIM_Reject,
1907	/ 4077 / // Label 220: @4077
1908	/ 4077 / GIM_Try_CheckFeatures, /On fail goto//Label 229/ GIMT_Encode4(`4109`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 911 //
1909	/ 4084 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
1910	/ 4087 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
1911	/ 4090 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1912	/ 4094 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1913	/ 4098 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
1914	/ 4102 / // (srem:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MOD_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
1915	/ 4102 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_S_B),
1916	/ 4107 / GIR_RootConstrainSelectedInstOperands,
1917	/ 4108 / // GIR_Coverage, 911,
1918	/ 4108 / GIR_Done,
1919	/ 4109 / // Label 229: @4109
1920	/ 4109 / GIM_Reject,
1921	/ 4110 / // Label 221: @4110
1922	/ 4110 / GIM_Try_CheckFeatures, /On fail goto//Label 230/ GIMT_Encode4(`4142`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 912 //
1923	/ 4117 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
1924	/ 4120 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
1925	/ 4123 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1926	/ 4127 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1927	/ 4131 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
1928	/ 4135 / // (srem:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MOD_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
1929	/ 4135 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_S_H),
1930	/ 4140 / GIR_RootConstrainSelectedInstOperands,
1931	/ 4141 / // GIR_Coverage, 912,
1932	/ 4141 / GIR_Done,
1933	/ 4142 / // Label 230: @4142
1934	/ 4142 / GIM_Reject,
1935	/ 4143 / // Label 222: @4143
1936	/ 4143 / GIM_Try_CheckFeatures, /On fail goto//Label 231/ GIMT_Encode4(`4175`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 913 //
1937	/ 4150 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
1938	/ 4153 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
1939	/ 4156 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1940	/ 4160 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1941	/ 4164 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
1942	/ 4168 / // (srem:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MOD_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
1943	/ 4168 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_S_W),
1944	/ 4173 / GIR_RootConstrainSelectedInstOperands,
1945	/ 4174 / // GIR_Coverage, 913,
1946	/ 4174 / GIR_Done,
1947	/ 4175 / // Label 231: @4175
1948	/ 4175 / GIM_Reject,
1949	/ 4176 / // Label 223: @4176
1950	/ 4176 / GIM_Try_CheckFeatures, /On fail goto//Label 232/ GIMT_Encode4(`4208`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 914 //
1951	/ 4183 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
1952	/ 4186 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
1953	/ 4189 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1954	/ 4193 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1955	/ 4197 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
1956	/ 4201 / // (srem:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MOD_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
1957	/ 4201 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_S_D),
1958	/ 4206 / GIR_RootConstrainSelectedInstOperands,
1959	/ 4207 / // GIR_Coverage, 914,
1960	/ 4207 / GIR_Done,
1961	/ 4208 / // Label 232: @4208
1962	/ 4208 / GIM_Reject,
1963	/ 4209 / // Label 224: @4209
1964	/ 4209 / GIM_Reject,
1965	/ 4210 / // Label 6: @4210
1966	/ 4210 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 239/ GIMT_Encode4(`4471`),
1967	/ 4221 / /GILLT_s32//Label 233/ GIMT_Encode4(`4253`),
1968	/ 4225 / /GILLT_s64//Label 234/ GIMT_Encode4(`4306`), GIMT_Encode4(`0`),
1969	/ 4233 / /GILLT_v16s8//Label 235/ GIMT_Encode4(`4339`), GIMT_Encode4(`0`),
1970	/ 4241 / /GILLT_v8s16//Label 236/ GIMT_Encode4(`4372`),
1971	/ 4245 / /GILLT_v4s32//Label 237/ GIMT_Encode4(`4405`),
1972	/ 4249 / /GILLT_v2s64//Label 238/ GIMT_Encode4(`4438`),
1973	/ 4253 / // Label 233: @4253
1974	/ 4253 / GIM_Try, /On fail goto//Label 240/ GIMT_Encode4(`4305`),
1975	/ 4258 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
1976	/ 4261 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
1977	/ 4264 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1978	/ 4268 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1979	/ 4272 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
1980	/ 4276 / GIM_Try_CheckFeatures, /On fail goto//Label 241/ GIMT_Encode4(`4290`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 356 //
1981	/ 4283 / // (urem:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MODU:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1982	/ 4283 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MODU),
1983	/ 4288 / GIR_RootConstrainSelectedInstOperands,
1984	/ 4289 / // GIR_Coverage, 356,
1985	/ 4289 / GIR_Done,
1986	/ 4290 / // Label 241: @4290
1987	/ 4290 / GIM_Try_CheckFeatures, /On fail goto//Label 242/ GIMT_Encode4(`4304`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1199 //
1988	/ 4297 / // (urem:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MODU_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
1989	/ 4297 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MODU_MMR6),
1990	/ 4302 / GIR_RootConstrainSelectedInstOperands,
1991	/ 4303 / // GIR_Coverage, 1199,
1992	/ 4303 / GIR_Done,
1993	/ 4304 / // Label 242: @4304
1994	/ 4304 / GIM_Reject,
1995	/ 4305 / // Label 240: @4305
1996	/ 4305 / GIM_Reject,
1997	/ 4306 / // Label 234: @4306
1998	/ 4306 / GIM_Try_CheckFeatures, /On fail goto//Label 243/ GIMT_Encode4(`4338`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 371 //
1999	/ 4313 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
2000	/ 4316 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
2001	/ 4319 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2002	/ 4323 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2003	/ 4327 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2004	/ 4331 / // (urem:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMODU:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
2005	/ 4331 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMODU),
2006	/ 4336 / GIR_RootConstrainSelectedInstOperands,
2007	/ 4337 / // GIR_Coverage, 371,
2008	/ 4337 / GIR_Done,
2009	/ 4338 / // Label 243: @4338
2010	/ 4338 / GIM_Reject,
2011	/ 4339 / // Label 235: @4339
2012	/ 4339 / GIM_Try_CheckFeatures, /On fail goto//Label 244/ GIMT_Encode4(`4371`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 915 //
2013	/ 4346 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
2014	/ 4349 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
2015	/ 4352 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2016	/ 4356 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2017	/ 4360 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2018	/ 4364 / // (urem:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MOD_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
2019	/ 4364 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_U_B),
2020	/ 4369 / GIR_RootConstrainSelectedInstOperands,
2021	/ 4370 / // GIR_Coverage, 915,
2022	/ 4370 / GIR_Done,
2023	/ 4371 / // Label 244: @4371
2024	/ 4371 / GIM_Reject,
2025	/ 4372 / // Label 236: @4372
2026	/ 4372 / GIM_Try_CheckFeatures, /On fail goto//Label 245/ GIMT_Encode4(`4404`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 916 //
2027	/ 4379 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
2028	/ 4382 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
2029	/ 4385 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2030	/ 4389 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2031	/ 4393 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2032	/ 4397 / // (urem:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MOD_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
2033	/ 4397 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_U_H),
2034	/ 4402 / GIR_RootConstrainSelectedInstOperands,
2035	/ 4403 / // GIR_Coverage, 916,
2036	/ 4403 / GIR_Done,
2037	/ 4404 / // Label 245: @4404
2038	/ 4404 / GIM_Reject,
2039	/ 4405 / // Label 237: @4405
2040	/ 4405 / GIM_Try_CheckFeatures, /On fail goto//Label 246/ GIMT_Encode4(`4437`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 917 //
2041	/ 4412 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
2042	/ 4415 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
2043	/ 4418 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2044	/ 4422 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2045	/ 4426 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2046	/ 4430 / // (urem:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MOD_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
2047	/ 4430 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_U_W),
2048	/ 4435 / GIR_RootConstrainSelectedInstOperands,
2049	/ 4436 / // GIR_Coverage, 917,
2050	/ 4436 / GIR_Done,
2051	/ 4437 / // Label 246: @4437
2052	/ 4437 / GIM_Reject,
2053	/ 4438 / // Label 238: @4438
2054	/ 4438 / GIM_Try_CheckFeatures, /On fail goto//Label 247/ GIMT_Encode4(`4470`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 918 //
2055	/ 4445 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
2056	/ 4448 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
2057	/ 4451 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2058	/ 4455 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2059	/ 4459 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2060	/ 4463 / // (urem:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MOD_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
2061	/ 4463 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MOD_U_D),
2062	/ 4468 / GIR_RootConstrainSelectedInstOperands,
2063	/ 4469 / // GIR_Coverage, 918,
2064	/ 4469 / GIR_Done,
2065	/ 4470 / // Label 247: @4470
2066	/ 4470 / GIM_Reject,
2067	/ 4471 / // Label 239: @4471
2068	/ 4471 / GIM_Reject,
2069	/ 4472 / // Label 7: @4472
2070	/ 4472 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 254/ GIMT_Encode4(`5005`),
2071	/ 4483 / /GILLT_s32//Label 248/ GIMT_Encode4(`4515`),
2072	/ 4487 / /GILLT_s64//Label 249/ GIMT_Encode4(`4773`), GIMT_Encode4(`0`),
2073	/ 4495 / /GILLT_v16s8//Label 250/ GIMT_Encode4(`4873`), GIMT_Encode4(`0`),
2074	/ 4503 / /GILLT_v8s16//Label 251/ GIMT_Encode4(`4906`),
2075	/ 4507 / /GILLT_v4s32//Label 252/ GIMT_Encode4(`4939`),
2076	/ 4511 / /GILLT_v2s64//Label 253/ GIMT_Encode4(`4972`),
2077	/ 4515 / // Label 248: @4515
2078	/ 4515 / GIM_Try, /On fail goto//Label 255/ GIMT_Encode4(`4772`),
2079	/ 4520 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2080	/ 4523 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
2081	/ 4526 / GIM_Try_CheckFeatures, /On fail goto//Label 256/ GIMT_Encode4(`4567`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 41 //
2082	/ 4533 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2083	/ 4537 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2084	/ 4541 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
2085	/ 4545 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2086	/ 4549 / GIM_CheckAPIntImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2087	/ 4553 / // MIs[1] Operand 1
2088	/ 4553 / // No operand predicates
2089	/ 4553 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2090	/ 4555 / // (and:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$imm16)
2091	/ 4555 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ANDi),
2092	/ 4558 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2093	/ 4560 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2094	/ 4562 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm16
2095	/ 4565 / GIR_RootConstrainSelectedInstOperands,
2096	/ 4566 / // GIR_Coverage, 41,
2097	/ 4566 / GIR_EraseRootFromParent_Done,
2098	/ 4567 / // Label 256: @4567
2099	/ 4567 / GIM_Try, /On fail goto//Label 257/ GIMT_Encode4(`4647`),
2100	/ 4572 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2101	/ 4576 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2102	/ 4580 / GIM_Try_CheckFeatures, /On fail goto//Label 258/ GIMT_Encode4(`4613`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2297 //
2103	/ 4587 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
2104	/ 4591 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2105	/ 4595 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2106	/ 4599 / // MIs[1] Operand 1
2107	/ 4599 / // No operand predicates
2108	/ 4599 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2109	/* 4601 / // (and:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2110	/ 4601 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ANDI16_MM),
2111	/ 4604 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2112	/ 4606 / GIR_RootToRootCopy, /OpIdx/`1`, // src
2113	/ 4608 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
2114	/ 4611 / GIR_RootConstrainSelectedInstOperands,
2115	/ 4612 / // GIR_Coverage, 2297,
2116	/ 4612 / GIR_EraseRootFromParent_Done,
2117	/ 4613 / // Label 258: @4613
2118	/ 4613 / GIM_Try_CheckFeatures, /On fail goto//Label 259/ GIMT_Encode4(`4646`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2461 //
2119	/ 4620 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
2120	/ 4624 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2121	/ 4628 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2122	/ 4632 / // MIs[1] Operand 1
2123	/ 4632 / // No operand predicates
2124	/ 4632 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2125	/* 4634 / // (and:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2126	/ 4634 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ANDI16_MMR6),
2127	/ 4637 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2128	/ 4639 / GIR_RootToRootCopy, /OpIdx/`1`, // src
2129	/ 4641 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
2130	/ 4644 / GIR_RootConstrainSelectedInstOperands,
2131	/ 4645 / // GIR_Coverage, 2461,
2132	/ 4645 / GIR_EraseRootFromParent_Done,
2133	/ 4646 / // Label 259: @4646
2134	/ 4646 / GIM_Reject,
2135	/ 4647 / // Label 257: @4647
2136	/ 4647 / GIM_Try_CheckFeatures, /On fail goto//Label 260/ GIMT_Encode4(`4673`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 51 //
2137	/ 4654 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2138	/ 4658 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2139	/ 4662 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2140	/ 4666 / // (and:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (AND:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2141	/ 4666 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND),
2142	/ 4671 / GIR_RootConstrainSelectedInstOperands,
2143	/ 4672 / // GIR_Coverage, 51,
2144	/ 4672 / GIR_Done,
2145	/ 4673 / // Label 260: @4673
2146	/ 4673 / GIM_Try_CheckFeatures, /On fail goto//Label 261/ GIMT_Encode4(`4699`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1082 //
2147	/ 4680 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2148	/ 4684 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2149	/ 4688 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2150	/ 4692 / // (and:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (AND16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
2151	/ 4692 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND16_MM),
2152	/ 4697 / GIR_RootConstrainSelectedInstOperands,
2153	/ 4698 / // GIR_Coverage, 1082,
2154	/ 4698 / GIR_Done,
2155	/ 4699 / // Label 261: @4699
2156	/ 4699 / GIM_Try, /On fail goto//Label 262/ GIMT_Encode4(`4745`),
2157	/ 4704 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2158	/ 4708 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2159	/ 4712 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2160	/ 4716 / GIM_Try_CheckFeatures, /On fail goto//Label 263/ GIMT_Encode4(`4730`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1098 //
2161	/ 4723 / // (and:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (AND_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2162	/ 4723 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_MM),
2163	/ 4728 / GIR_RootConstrainSelectedInstOperands,
2164	/ 4729 / // GIR_Coverage, 1098,
2165	/ 4729 / GIR_Done,
2166	/ 4730 / // Label 263: @4730
2167	/ 4730 / GIM_Try_CheckFeatures, /On fail goto//Label 264/ GIMT_Encode4(`4744`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1191 //
2168	/ 4737 / // (and:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (AND_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2169	/ 4737 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_MMR6),
2170	/ 4742 / GIR_RootConstrainSelectedInstOperands,
2171	/ 4743 / // GIR_Coverage, 1191,
2172	/ 4743 / GIR_Done,
2173	/ 4744 / // Label 264: @4744
2174	/ 4744 / GIM_Reject,
2175	/ 4745 / // Label 262: @4745
2176	/ 4745 / GIM_Try_CheckFeatures, /On fail goto//Label 265/ GIMT_Encode4(`4771`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1955 //
2177	/ 4752 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2178	/ 4756 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2179	/ 4760 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2180	/ 4764 / // (and:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (AndRxRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)
2181	/ 4764 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AndRxRxRy16),
2182	/ 4769 / GIR_RootConstrainSelectedInstOperands,
2183	/ 4770 / // GIR_Coverage, 1955,
2184	/ 4770 / GIR_Done,
2185	/ 4771 / // Label 265: @4771
2186	/ 4771 / GIM_Reject,
2187	/ 4772 / // Label 255: @4772
2188	/ 4772 / GIM_Reject,
2189	/ 4773 / // Label 249: @4773
2190	/ 4773 / GIM_Try, /On fail goto//Label 266/ GIMT_Encode4(`4872`),
2191	/ 4778 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
2192	/ 4781 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
2193	/ 4784 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2194	/ 4788 / GIM_Try_CheckFeatures, /On fail goto//Label 267/ GIMT_Encode4(`4849`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 296 //
2195	/ 4795 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
2196	/ 4799 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ADD),
2197	/ 4803 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
2198	/ 4807 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
2199	/ 4811 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2200	/ 4816 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2201	/ 4821 / GIM_CheckConstantInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`255`),
2202	/ 4832 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2203	/* 4834 / // (and:{ :[i64] } (add:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt), 255:{ :[i64] }) => (BADDu:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2204	/ 4834 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BADDu),
2205	/ 4837 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2206	/ 4839 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
2207	/ 4843 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rt
2208	/ 4847 / GIR_RootConstrainSelectedInstOperands,
2209	/ 4848 / // GIR_Coverage, 296,
2210	/ 4848 / GIR_EraseRootFromParent_Done,
2211	/ 4849 / // Label 267: @4849
2212	/ 4849 / GIM_Try_CheckFeatures, /On fail goto//Label 268/ GIMT_Encode4(`4871`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 233 //
2213	/ 4856 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2214	/ 4860 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2215	/ 4864 / // (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (AND64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
2216	/ 4864 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND64),
2217	/ 4869 / GIR_RootConstrainSelectedInstOperands,
2218	/ 4870 / // GIR_Coverage, 233,
2219	/ 4870 / GIR_Done,
2220	/ 4871 / // Label 268: @4871
2221	/ 4871 / GIM_Reject,
2222	/ 4872 / // Label 266: @4872
2223	/ 4872 / GIM_Reject,
2224	/ 4873 / // Label 250: @4873
2225	/ 4873 / GIM_Try_CheckFeatures, /On fail goto//Label 269/ GIMT_Encode4(`4905`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 542 //
2226	/ 4880 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
2227	/ 4883 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
2228	/ 4886 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2229	/ 4890 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2230	/ 4894 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2231	/ 4898 / // (and:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (AND_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
2232	/ 4898 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_V),
2233	/ 4903 / GIR_RootConstrainSelectedInstOperands,
2234	/ 4904 / // GIR_Coverage, 542,
2235	/ 4904 / GIR_Done,
2236	/ 4905 / // Label 269: @4905
2237	/ 4905 / GIM_Reject,
2238	/ 4906 / // Label 251: @4906
2239	/ 4906 / GIM_Try_CheckFeatures, /On fail goto//Label 270/ GIMT_Encode4(`4938`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 543 //
2240	/ 4913 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
2241	/ 4916 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
2242	/ 4919 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2243	/ 4923 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2244	/ 4927 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2245	/ 4931 / // (and:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
2246	/ 4931 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2247	/ 4936 / GIR_RootConstrainSelectedInstOperands,
2248	/ 4937 / // GIR_Coverage, 543,
2249	/ 4937 / GIR_Done,
2250	/ 4938 / // Label 270: @4938
2251	/ 4938 / GIM_Reject,
2252	/ 4939 / // Label 252: @4939
2253	/ 4939 / GIM_Try_CheckFeatures, /On fail goto//Label 271/ GIMT_Encode4(`4971`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 544 //
2254	/ 4946 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
2255	/ 4949 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
2256	/ 4952 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2257	/ 4956 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2258	/ 4960 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2259	/ 4964 / // (and:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
2260	/ 4964 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2261	/ 4969 / GIR_RootConstrainSelectedInstOperands,
2262	/ 4970 / // GIR_Coverage, 544,
2263	/ 4970 / GIR_Done,
2264	/ 4971 / // Label 271: @4971
2265	/ 4971 / GIM_Reject,
2266	/ 4972 / // Label 253: @4972
2267	/ 4972 / GIM_Try_CheckFeatures, /On fail goto//Label 272/ GIMT_Encode4(`5004`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 545 //
2268	/ 4979 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
2269	/ 4982 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
2270	/ 4985 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2271	/ 4989 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2272	/ 4993 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2273	/ 4997 / // (and:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
2274	/ 4997 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2275	/ 5002 / GIR_RootConstrainSelectedInstOperands,
2276	/ 5003 / // GIR_Coverage, 545,
2277	/ 5003 / GIR_Done,
2278	/ 5004 / // Label 272: @5004
2279	/ 5004 / GIM_Reject,
2280	/ 5005 / // Label 254: @5005
2281	/ 5005 / GIM_Reject,
2282	/ 5006 / // Label 8: @5006
2283	/ 5006 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 279/ GIMT_Encode4(`5390`),
2284	/ 5017 / /GILLT_s32//Label 273/ GIMT_Encode4(`5049`),
2285	/ 5021 / /GILLT_s64//Label 274/ GIMT_Encode4(`5225`), GIMT_Encode4(`0`),
2286	/ 5029 / /GILLT_v16s8//Label 275/ GIMT_Encode4(`5258`), GIMT_Encode4(`0`),
2287	/ 5037 / /GILLT_v8s16//Label 276/ GIMT_Encode4(`5291`),
2288	/ 5041 / /GILLT_v4s32//Label 277/ GIMT_Encode4(`5324`),
2289	/ 5045 / /GILLT_v2s64//Label 278/ GIMT_Encode4(`5357`),
2290	/ 5049 / // Label 273: @5049
2291	/ 5049 / GIM_Try, /On fail goto//Label 280/ GIMT_Encode4(`5224`),
2292	/ 5054 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2293	/ 5057 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
2294	/ 5060 / GIM_Try, /On fail goto//Label 281/ GIMT_Encode4(`5125`),
2295	/ 5065 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2296	/ 5069 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2297	/ 5073 / GIM_Try_CheckFeatures, /On fail goto//Label 282/ GIMT_Encode4(`5106`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 42 //
2298	/ 5080 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
2299	/ 5084 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2300	/ 5088 / GIM_CheckAPIntImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2301	/ 5092 / // MIs[1] Operand 1
2302	/ 5092 / // No operand predicates
2303	/ 5092 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2304	/ 5094 / // (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$imm16)
2305	/ 5094 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ORi),
2306	/ 5097 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2307	/ 5099 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2308	/ 5101 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm16
2309	/ 5104 / GIR_RootConstrainSelectedInstOperands,
2310	/ 5105 / // GIR_Coverage, 42,
2311	/ 5105 / GIR_EraseRootFromParent_Done,
2312	/ 5106 / // Label 282: @5106
2313	/ 5106 / GIM_Try_CheckFeatures, /On fail goto//Label 283/ GIMT_Encode4(`5124`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 52 //
2314	/ 5113 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2315	/ 5117 / // (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (OR:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2316	/ 5117 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR),
2317	/ 5122 / GIR_RootConstrainSelectedInstOperands,
2318	/ 5123 / // GIR_Coverage, 52,
2319	/ 5123 / GIR_Done,
2320	/ 5124 / // Label 283: @5124
2321	/ 5124 / GIM_Reject,
2322	/ 5125 / // Label 281: @5125
2323	/ 5125 / GIM_Try_CheckFeatures, /On fail goto//Label 284/ GIMT_Encode4(`5151`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1084 //
2324	/ 5132 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2325	/ 5136 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2326	/ 5140 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2327	/ 5144 / // (or:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (OR16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
2328	/ 5144 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR16_MM),
2329	/ 5149 / GIR_RootConstrainSelectedInstOperands,
2330	/ 5150 / // GIR_Coverage, 1084,
2331	/ 5150 / GIR_Done,
2332	/ 5151 / // Label 284: @5151
2333	/ 5151 / GIM_Try, /On fail goto//Label 285/ GIMT_Encode4(`5197`),
2334	/ 5156 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2335	/ 5160 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2336	/ 5164 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2337	/ 5168 / GIM_Try_CheckFeatures, /On fail goto//Label 286/ GIMT_Encode4(`5182`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1099 //
2338	/ 5175 / // (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (OR_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2339	/ 5175 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_MM),
2340	/ 5180 / GIR_RootConstrainSelectedInstOperands,
2341	/ 5181 / // GIR_Coverage, 1099,
2342	/ 5181 / GIR_Done,
2343	/ 5182 / // Label 286: @5182
2344	/ 5182 / GIM_Try_CheckFeatures, /On fail goto//Label 287/ GIMT_Encode4(`5196`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1204 //
2345	/ 5189 / // (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (OR_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2346	/ 5189 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_MMR6),
2347	/ 5194 / GIR_RootConstrainSelectedInstOperands,
2348	/ 5195 / // GIR_Coverage, 1204,
2349	/ 5195 / GIR_Done,
2350	/ 5196 / // Label 287: @5196
2351	/ 5196 / GIM_Reject,
2352	/ 5197 / // Label 285: @5197
2353	/ 5197 / GIM_Try_CheckFeatures, /On fail goto//Label 288/ GIMT_Encode4(`5223`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1957 //
2354	/ 5204 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2355	/ 5208 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2356	/ 5212 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2357	/ 5216 / // (or:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (OrRxRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)
2358	/ 5216 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OrRxRxRy16),
2359	/ 5221 / GIR_RootConstrainSelectedInstOperands,
2360	/ 5222 / // GIR_Coverage, 1957,
2361	/ 5222 / GIR_Done,
2362	/ 5223 / // Label 288: @5223
2363	/ 5223 / GIM_Reject,
2364	/ 5224 / // Label 280: @5224
2365	/ 5224 / GIM_Reject,
2366	/ 5225 / // Label 274: @5225
2367	/ 5225 / GIM_Try_CheckFeatures, /On fail goto//Label 289/ GIMT_Encode4(`5257`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 234 //
2368	/ 5232 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
2369	/ 5235 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
2370	/ 5238 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2371	/ 5242 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2372	/ 5246 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2373	/ 5250 / // (or:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (OR64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
2374	/ 5250 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR64),
2375	/ 5255 / GIR_RootConstrainSelectedInstOperands,
2376	/ 5256 / // GIR_Coverage, 234,
2377	/ 5256 / GIR_Done,
2378	/ 5257 / // Label 289: @5257
2379	/ 5257 / GIM_Reject,
2380	/ 5258 / // Label 275: @5258
2381	/ 5258 / GIM_Try_CheckFeatures, /On fail goto//Label 290/ GIMT_Encode4(`5290`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 948 //
2382	/ 5265 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
2383	/ 5268 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
2384	/ 5271 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2385	/ 5275 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2386	/ 5279 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2387	/ 5283 / // (or:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (OR_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
2388	/ 5283 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_V),
2389	/ 5288 / GIR_RootConstrainSelectedInstOperands,
2390	/ 5289 / // GIR_Coverage, 948,
2391	/ 5289 / GIR_Done,
2392	/ 5290 / // Label 290: @5290
2393	/ 5290 / GIM_Reject,
2394	/ 5291 / // Label 276: @5291
2395	/ 5291 / GIM_Try_CheckFeatures, /On fail goto//Label 291/ GIMT_Encode4(`5323`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 949 //
2396	/ 5298 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
2397	/ 5301 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
2398	/ 5304 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2399	/ 5308 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2400	/ 5312 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2401	/ 5316 / // (or:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
2402	/ 5316 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2403	/ 5321 / GIR_RootConstrainSelectedInstOperands,
2404	/ 5322 / // GIR_Coverage, 949,
2405	/ 5322 / GIR_Done,
2406	/ 5323 / // Label 291: @5323
2407	/ 5323 / GIM_Reject,
2408	/ 5324 / // Label 277: @5324
2409	/ 5324 / GIM_Try_CheckFeatures, /On fail goto//Label 292/ GIMT_Encode4(`5356`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 950 //
2410	/ 5331 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
2411	/ 5334 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
2412	/ 5337 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2413	/ 5341 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2414	/ 5345 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2415	/ 5349 / // (or:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
2416	/ 5349 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2417	/ 5354 / GIR_RootConstrainSelectedInstOperands,
2418	/ 5355 / // GIR_Coverage, 950,
2419	/ 5355 / GIR_Done,
2420	/ 5356 / // Label 292: @5356
2421	/ 5356 / GIM_Reject,
2422	/ 5357 / // Label 278: @5357
2423	/ 5357 / GIM_Try_CheckFeatures, /On fail goto//Label 293/ GIMT_Encode4(`5389`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 951 //
2424	/ 5364 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
2425	/ 5367 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
2426	/ 5370 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2427	/ 5374 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2428	/ 5378 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2429	/ 5382 / // (or:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
2430	/ 5382 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2431	/ 5387 / GIR_RootConstrainSelectedInstOperands,
2432	/ 5388 / // GIR_Coverage, 951,
2433	/ 5388 / GIR_Done,
2434	/ 5389 / // Label 293: @5389
2435	/ 5389 / GIM_Reject,
2436	/ 5390 / // Label 279: @5390
2437	/ 5390 / GIM_Reject,
2438	/ 5391 / // Label 9: @5391
2439	/ 5391 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 300/ GIMT_Encode4(`6227`),
2440	/ 5402 / /GILLT_s32//Label 294/ GIMT_Encode4(`5434`),
2441	/ 5406 / /GILLT_s64//Label 295/ GIMT_Encode4(`6002`), GIMT_Encode4(`0`),
2442	/ 5414 / /GILLT_v16s8//Label 296/ GIMT_Encode4(`6095`), GIMT_Encode4(`0`),
2443	/ 5422 / /GILLT_v8s16//Label 297/ GIMT_Encode4(`6128`),
2444	/ 5426 / /GILLT_v4s32//Label 298/ GIMT_Encode4(`6161`),
2445	/ 5430 / /GILLT_v2s64//Label 299/ GIMT_Encode4(`6194`),
2446	/ 5434 / // Label 294: @5434
2447	/ 5434 / GIM_Try, /On fail goto//Label 301/ GIMT_Encode4(`6001`),
2448	/ 5439 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2449	/ 5442 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
2450	/ 5445 / GIM_Try, /On fail goto//Label 302/ GIMT_Encode4(`5609`),
2451	/ 5450 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2452	/ 5454 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2453	/ 5458 / GIM_Try_CheckFeatures, /On fail goto//Label 303/ GIMT_Encode4(`5508`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 54 //
2454	/ 5465 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
2455	/ 5469 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_OR),
2456	/ 5473 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
2457	/ 5477 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
2458	/ 5481 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2459	/ 5486 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2460	/ 5491 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2461	/ 5493 / // (xor:{ :[i32] } (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt), -1:{ :[i32] }) => (NOR:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2462	/ 5493 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR),
2463	/ 5496 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2464	/ 5498 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
2465	/ 5502 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rt
2466	/ 5506 / GIR_RootConstrainSelectedInstOperands,
2467	/ 5507 / // GIR_Coverage, 54,
2468	/ 5507 / GIR_EraseRootFromParent_Done,
2469	/ 5508 / // Label 303: @5508
2470	/ 5508 / GIM_Try_CheckFeatures, /On fail goto//Label 304/ GIMT_Encode4(`5558`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1101 //
2471	/ 5515 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
2472	/ 5519 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_OR),
2473	/ 5523 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
2474	/ 5527 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
2475	/ 5531 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2476	/ 5536 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2477	/ 5541 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2478	/* 5543 / // (xor:{ :[i32] } (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt), -1:{ :[i32] }) => (NOR_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2479	/ 5543 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR_MM),
2480	/ 5546 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2481	/ 5548 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
2482	/ 5552 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rt
2483	/ 5556 / GIR_RootConstrainSelectedInstOperands,
2484	/ 5557 / // GIR_Coverage, 1101,
2485	/ 5557 / GIR_EraseRootFromParent_Done,
2486	/ 5558 / // Label 304: @5558
2487	/ 5558 / GIM_Try_CheckFeatures, /On fail goto//Label 305/ GIMT_Encode4(`5608`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1203 //
2488	/ 5565 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
2489	/ 5569 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_OR),
2490	/ 5573 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
2491	/ 5577 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
2492	/ 5581 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2493	/ 5586 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2494	/ 5591 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2495	/* 5593 / // (xor:{ :[i32] } (or:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt), -1:{ :[i32] }) => (NOR_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2496	/ 5593 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR_MMR6),
2497	/ 5596 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2498	/ 5598 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
2499	/ 5602 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rt
2500	/ 5606 / GIR_RootConstrainSelectedInstOperands,
2501	/ 5607 / // GIR_Coverage, 1203,
2502	/ 5607 / GIR_EraseRootFromParent_Done,
2503	/ 5608 / // Label 305: @5608
2504	/ 5608 / GIM_Reject,
2505	/ 5609 / // Label 302: @5609
2506	/ 5609 / GIM_Try, /On fail goto//Label 306/ GIMT_Encode4(`5659`),
2507	/ 5614 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2508	/ 5618 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2509	/ 5622 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2510	/ 5626 / GIM_Try_CheckFeatures, /On fail goto//Label 307/ GIMT_Encode4(`5642`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1230 //
2511	/ 5633 / // (xor:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, -1:{ :[i32] }) => (NOT16_MMR6:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs)*
2512	/ 5633 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOT16_MMR6),
2513	/ 5636 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2514	/ 5638 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2515	/ 5640 / GIR_RootConstrainSelectedInstOperands,
2516	/ 5641 / // GIR_Coverage, 1230,
2517	/ 5641 / GIR_EraseRootFromParent_Done,
2518	/ 5642 / // Label 307: @5642
2519	/ 5642 / GIM_Try_CheckFeatures, /On fail goto//Label 308/ GIMT_Encode4(`5658`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1083 //
2520	/ 5649 / // (xor:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, -1:{ :[i32] }) => (NOT16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs)*
2521	/ 5649 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOT16_MM),
2522	/ 5652 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2523	/ 5654 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2524	/ 5656 / GIR_RootConstrainSelectedInstOperands,
2525	/ 5657 / // GIR_Coverage, 1083,
2526	/ 5657 / GIR_EraseRootFromParent_Done,
2527	/ 5658 / // Label 308: @5658
2528	/ 5658 / GIM_Reject,
2529	/ 5659 / // Label 306: @5659
2530	/ 5659 / GIM_Try_CheckFeatures, /On fail goto//Label 309/ GIMT_Encode4(`5693`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1418 //
2531	/ 5666 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2532	/ 5670 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2533	/ 5674 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2534	/ 5678 / // (xor:{ :[i32] } GPR32:{ :[i32] }:$in, -1:{ :[i32] }) => (NOR:{ :[i32] } GPR32Opnd:{ :[i32] }:$in, ZERO:{ :[i32] })
2535	/ 5678 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR),
2536	/ 5681 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2537	/ 5683 / GIR_RootToRootCopy, /OpIdx/`1`, // in
2538	/ 5685 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
2539	/ 5691 / GIR_RootConstrainSelectedInstOperands,
2540	/ 5692 / // GIR_Coverage, 1418,
2541	/ 5692 / GIR_EraseRootFromParent_Done,
2542	/ 5693 / // Label 309: @5693
2543	/ 5693 / GIM_Try_CheckFeatures, /On fail goto//Label 310/ GIMT_Encode4(`5721`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1952 //
2544	/ 5700 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2545	/ 5704 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2546	/ 5708 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2547	/ 5712 / // (xor:{ :[i32] } CPU16Regs:{ :[i32] }:$r, -1:{ :[i32] }) => (NotRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$r)*
2548	/ 5712 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NotRxRy16),
2549	/ 5715 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
2550	/ 5717 / GIR_RootToRootCopy, /OpIdx/`1`, // r
2551	/ 5719 / GIR_RootConstrainSelectedInstOperands,
2552	/ 5720 / // GIR_Coverage, 1952,
2553	/ 5720 / GIR_EraseRootFromParent_Done,
2554	/ 5721 / // Label 310: @5721
2555	/ 5721 / GIM_Try_CheckFeatures, /On fail goto//Label 311/ GIMT_Encode4(`5749`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2292 //
2556	/ 5728 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2557	/ 5732 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2558	/ 5736 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2559	/ 5740 / // (xor:{ :[i32] } GPRMM16:{ :[i32] }:$in, -1:{ :[i32] }) => (NOT16_MM:{ :[i32] } GPRMM16:{ :[i32] }:$in)*
2560	/ 5740 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOT16_MM),
2561	/ 5743 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2562	/ 5745 / GIR_RootToRootCopy, /OpIdx/`1`, // in
2563	/ 5747 / GIR_RootConstrainSelectedInstOperands,
2564	/ 5748 / // GIR_Coverage, 2292,
2565	/ 5748 / GIR_EraseRootFromParent_Done,
2566	/ 5749 / // Label 311: @5749
2567	/ 5749 / GIM_Try_CheckFeatures, /On fail goto//Label 312/ GIMT_Encode4(`5783`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2293 //
2568	/ 5756 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2569	/ 5760 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2570	/ 5764 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2571	/ 5768 / // (xor:{ :[i32] } GPR32:{ :[i32] }:$in, -1:{ :[i32] }) => (NOR_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$in, ZERO:{ :[i32] })
2572	/ 5768 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR_MM),
2573	/ 5771 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2574	/ 5773 / GIR_RootToRootCopy, /OpIdx/`1`, // in
2575	/ 5775 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
2576	/ 5781 / GIR_RootConstrainSelectedInstOperands,
2577	/ 5782 / // GIR_Coverage, 2293,
2578	/ 5782 / GIR_EraseRootFromParent_Done,
2579	/ 5783 / // Label 312: @5783
2580	/ 5783 / GIM_Try_CheckFeatures, /On fail goto//Label 313/ GIMT_Encode4(`5811`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2464 //
2581	/ 5790 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2582	/ 5794 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2583	/ 5798 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2584	/ 5802 / // (xor:{ :[i32] } GPRMM16:{ :[i32] }:$in, -1:{ :[i32] }) => (NOT16_MMR6:{ :[i32] } GPRMM16:{ :[i32] }:$in)*
2585	/ 5802 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOT16_MMR6),
2586	/ 5805 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2587	/ 5807 / GIR_RootToRootCopy, /OpIdx/`1`, // in
2588	/ 5809 / GIR_RootConstrainSelectedInstOperands,
2589	/ 5810 / // GIR_Coverage, 2464,
2590	/ 5810 / GIR_EraseRootFromParent_Done,
2591	/ 5811 / // Label 313: @5811
2592	/ 5811 / GIM_Try, /On fail goto//Label 314/ GIMT_Encode4(`5902`),
2593	/ 5816 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2594	/ 5820 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2595	/ 5824 / GIM_Try_CheckFeatures, /On fail goto//Label 315/ GIMT_Encode4(`5850`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2465 //
2596	/ 5831 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2597	/ 5835 / // (xor:{ :[i32] } GPR32:{ :[i32] }:$in, -1:{ :[i32] }) => (NOR_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$in, ZERO:{ :[i32] })
2598	/ 5835 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR_MMR6),
2599	/ 5838 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2600	/ 5840 / GIR_RootToRootCopy, /OpIdx/`1`, // in
2601	/ 5842 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
2602	/ 5848 / GIR_RootConstrainSelectedInstOperands,
2603	/ 5849 / // GIR_Coverage, 2465,
2604	/ 5849 / GIR_EraseRootFromParent_Done,
2605	/ 5850 / // Label 315: @5850
2606	/ 5850 / GIM_Try_CheckFeatures, /On fail goto//Label 316/ GIMT_Encode4(`5883`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 43 //
2607	/ 5857 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
2608	/ 5861 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2609	/ 5865 / GIM_CheckAPIntImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2610	/ 5869 / // MIs[1] Operand 1
2611	/ 5869 / // No operand predicates
2612	/ 5869 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2613	/ 5871 / // (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$imm16)
2614	/ 5871 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
2615	/ 5874 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
2616	/ 5876 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2617	/ 5878 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm16
2618	/ 5881 / GIR_RootConstrainSelectedInstOperands,
2619	/ 5882 / // GIR_Coverage, 43,
2620	/ 5882 / GIR_EraseRootFromParent_Done,
2621	/ 5883 / // Label 316: @5883
2622	/ 5883 / GIM_Try_CheckFeatures, /On fail goto//Label 317/ GIMT_Encode4(`5901`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 53 //
2623	/ 5890 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2624	/ 5894 / // (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (XOR:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2625	/ 5894 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR),
2626	/ 5899 / GIR_RootConstrainSelectedInstOperands,
2627	/ 5900 / // GIR_Coverage, 53,
2628	/ 5900 / GIR_Done,
2629	/ 5901 / // Label 317: @5901
2630	/ 5901 / GIM_Reject,
2631	/ 5902 / // Label 314: @5902
2632	/ 5902 / GIM_Try_CheckFeatures, /On fail goto//Label 318/ GIMT_Encode4(`5928`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1086 //
2633	/ 5909 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2634	/ 5913 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2635	/ 5917 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
2636	/ 5921 / // (xor:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt) => (XOR16_MM:{ :[i32] } GPRMM16Opnd:{ :[i32] }:$rs, GPRMM16Opnd:{ :[i32] }:$rt)
2637	/ 5921 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR16_MM),
2638	/ 5926 / GIR_RootConstrainSelectedInstOperands,
2639	/ 5927 / // GIR_Coverage, 1086,
2640	/ 5927 / GIR_Done,
2641	/ 5928 / // Label 318: @5928
2642	/ 5928 / GIM_Try, /On fail goto//Label 319/ GIMT_Encode4(`5974`),
2643	/ 5933 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2644	/ 5937 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2645	/ 5941 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2646	/ 5945 / GIM_Try_CheckFeatures, /On fail goto//Label 320/ GIMT_Encode4(`5959`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1100 //
2647	/ 5952 / // (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (XOR_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2648	/ 5952 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
2649	/ 5957 / GIR_RootConstrainSelectedInstOperands,
2650	/ 5958 / // GIR_Coverage, 1100,
2651	/ 5958 / GIR_Done,
2652	/ 5959 / // Label 320: @5959
2653	/ 5959 / GIM_Try_CheckFeatures, /On fail goto//Label 321/ GIMT_Encode4(`5973`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1207 //
2654	/ 5966 / // (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (XOR_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
2655	/ 5966 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_MMR6),
2656	/ 5971 / GIR_RootConstrainSelectedInstOperands,
2657	/ 5972 / // GIR_Coverage, 1207,
2658	/ 5972 / GIR_Done,
2659	/ 5973 / // Label 321: @5973
2660	/ 5973 / GIM_Reject,
2661	/ 5974 / // Label 319: @5974
2662	/ 5974 / GIM_Try_CheckFeatures, /On fail goto//Label 322/ GIMT_Encode4(`6000`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1959 //
2663	/ 5981 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2664	/ 5985 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2665	/ 5989 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2666	/ 5993 / // (xor:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r) => (XorRxRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$l, CPU16Regs:{ :[i32] }:$r)
2667	/ 5993 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
2668	/ 5998 / GIR_RootConstrainSelectedInstOperands,
2669	/ 5999 / // GIR_Coverage, 1959,
2670	/ 5999 / GIR_Done,
2671	/ 6000 / // Label 322: @6000
2672	/ 6000 / GIM_Reject,
2673	/ 6001 / // Label 301: @6001
2674	/ 6001 / GIM_Reject,
2675	/ 6002 / // Label 295: @6002
2676	/ 6002 / GIM_Try, /On fail goto//Label 323/ GIMT_Encode4(`6094`),
2677	/ 6007 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
2678	/ 6010 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
2679	/ 6013 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2680	/ 6017 / GIM_Try_CheckFeatures, /On fail goto//Label 324/ GIMT_Encode4(`6071`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 236 //
2681	/ 6024 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
2682	/ 6028 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_OR),
2683	/ 6032 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
2684	/ 6036 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
2685	/ 6040 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2686	/ 6045 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2687	/ 6050 / GIM_CheckConstantInt8, /MI/`0`, /Op/`2`, `255`,
2688	/ 6054 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
2689	/ 6056 / // (xor:{ :[i64] } (or:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt), -1:{ :[i64] }) => (NOR64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
2690	/ 6056 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NOR64),
2691	/ 6059 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
2692	/ 6061 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
2693	/ 6065 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rt
2694	/ 6069 / GIR_RootConstrainSelectedInstOperands,
2695	/ 6070 / // GIR_Coverage, 236,
2696	/ 6070 / GIR_EraseRootFromParent_Done,
2697	/ 6071 / // Label 324: @6071
2698	/ 6071 / GIM_Try_CheckFeatures, /On fail goto//Label 325/ GIMT_Encode4(`6093`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 235 //
2699	/ 6078 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2700	/ 6082 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2701	/ 6086 / // (xor:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (XOR64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
2702	/ 6086 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR64),
2703	/ 6091 / GIR_RootConstrainSelectedInstOperands,
2704	/ 6092 / // GIR_Coverage, 235,
2705	/ 6092 / GIR_Done,
2706	/ 6093 / // Label 325: @6093
2707	/ 6093 / GIM_Reject,
2708	/ 6094 / // Label 323: @6094
2709	/ 6094 / GIM_Reject,
2710	/ 6095 / // Label 296: @6095
2711	/ 6095 / GIM_Try_CheckFeatures, /On fail goto//Label 326/ GIMT_Encode4(`6127`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1064 //
2712	/ 6102 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
2713	/ 6105 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
2714	/ 6108 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2715	/ 6112 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2716	/ 6116 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2717	/ 6120 / // (xor:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (XOR_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
2718	/ 6120 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_V),
2719	/ 6125 / GIR_RootConstrainSelectedInstOperands,
2720	/ 6126 / // GIR_Coverage, 1064,
2721	/ 6126 / GIR_Done,
2722	/ 6127 / // Label 326: @6127
2723	/ 6127 / GIM_Reject,
2724	/ 6128 / // Label 297: @6128
2725	/ 6128 / GIM_Try_CheckFeatures, /On fail goto//Label 327/ GIMT_Encode4(`6160`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1065 //
2726	/ 6135 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
2727	/ 6138 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
2728	/ 6141 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2729	/ 6145 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2730	/ 6149 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2731	/ 6153 / // (xor:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
2732	/ 6153 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2733	/ 6158 / GIR_RootConstrainSelectedInstOperands,
2734	/ 6159 / // GIR_Coverage, 1065,
2735	/ 6159 / GIR_Done,
2736	/ 6160 / // Label 327: @6160
2737	/ 6160 / GIM_Reject,
2738	/ 6161 / // Label 298: @6161
2739	/ 6161 / GIM_Try_CheckFeatures, /On fail goto//Label 328/ GIMT_Encode4(`6193`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1066 //
2740	/ 6168 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
2741	/ 6171 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
2742	/ 6174 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2743	/ 6178 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2744	/ 6182 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2745	/ 6186 / // (xor:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
2746	/ 6186 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2747	/ 6191 / GIR_RootConstrainSelectedInstOperands,
2748	/ 6192 / // GIR_Coverage, 1066,
2749	/ 6192 / GIR_Done,
2750	/ 6193 / // Label 328: @6193
2751	/ 6193 / GIM_Reject,
2752	/ 6194 / // Label 299: @6194
2753	/ 6194 / GIM_Try_CheckFeatures, /On fail goto//Label 329/ GIMT_Encode4(`6226`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1067 //
2754	/ 6201 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
2755	/ 6204 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
2756	/ 6207 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2757	/ 6211 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2758	/ 6215 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2759	/ 6219 / // (xor:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
2760	/ 6219 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2761	/ 6224 / GIR_RootConstrainSelectedInstOperands,
2762	/ 6225 / // GIR_Coverage, 1067,
2763	/ 6225 / GIR_Done,
2764	/ 6226 / // Label 329: @6226
2765	/ 6226 / GIM_Reject,
2766	/ 6227 / // Label 300: @6227
2767	/ 6227 / GIM_Reject,
2768	/ 6228 / // Label 10: @6228
2769	/ 6228 / GIM_Try, /On fail goto//Label 330/ GIMT_Encode4(`6298`),
2770	/ 6233 / GIM_CheckNumOperands, /MI/`0`, /Expected/`3`,
2771	/ 6236 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s64,
2772	/ 6239 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2773	/ 6242 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
2774	/ 6245 / GIM_Try_CheckFeatures, /On fail goto//Label 331/ GIMT_Encode4(`6271`), GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode), // Rule ID 207 //
2775	/ 6252 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
2776	/ 6256 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2777	/ 6260 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2778	/ 6264 / // (MipsBuildPairF64:{ :[f64] } GPR32Opnd:{ :[i32] }:$lo, GPR32Opnd:{ :[i32] }:$hi) => (BuildPairF64:{ :[f64] } GPR32Opnd:{ :[i32] }:$lo, GPR32Opnd:{ :[i32] }:$hi)
2779	/ 6264 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::BuildPairF64),
2780	/ 6269 / GIR_RootConstrainSelectedInstOperands,
2781	/ 6270 / // GIR_Coverage, 207,
2782	/ 6270 / GIR_Done,
2783	/ 6271 / // Label 331: @6271
2784	/ 6271 / GIM_Try_CheckFeatures, /On fail goto//Label 332/ GIMT_Encode4(`6297`), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode), // Rule ID 208 //
2785	/ 6278 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
2786	/ 6282 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2787	/ 6286 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2788	/ 6290 / // (MipsBuildPairF64:{ :[f64] } GPR32Opnd:{ :[i32] }:$lo, GPR32Opnd:{ :[i32] }:$hi) => (BuildPairF64_64:{ :[f64] } GPR32Opnd:{ :[i32] }:$lo, GPR32Opnd:{ :[i32] }:$hi)
2789	/ 6290 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::BuildPairF64_64),
2790	/ 6295 / GIR_RootConstrainSelectedInstOperands,
2791	/ 6296 / // GIR_Coverage, 208,
2792	/ 6296 / GIR_Done,
2793	/ 6297 / // Label 332: @6297
2794	/ 6297 / GIM_Reject,
2795	/ 6298 / // Label 330: @6298
2796	/ 6298 / GIM_Reject,
2797	/ 6299 / // Label 11: @6299
2798	/ 6299 / GIM_Try, /On fail goto//Label 333/ GIMT_Encode4(`6368`),
2799	/ 6304 / GIM_CheckNumOperands, /MI/`0`, /Expected/`3`,
2800	/ 6307 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
2801	/ 6310 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
2802	/ 6313 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
2803	/ 6317 / GIM_Try_CheckFeatures, /On fail goto//Label 334/ GIMT_Encode4(`6342`), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 746 //
2804	/ 6324 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
2805	/ 6328 / // MIs[0] rs
2806	/ 6328 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2807	/ 6333 / // (build_vector:{ :[v2i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rs) => (FILL_D:{ :[v2i64] } GPR64Opnd:{ :[i64] }:$rs)*
2808	/ 6333 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_D),
2809	/ 6336 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2810	/ 6338 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2811	/ 6340 / GIR_RootConstrainSelectedInstOperands,
2812	/ 6341 / // GIR_Coverage, 746,
2813	/ 6341 / GIR_EraseRootFromParent_Done,
2814	/ 6342 / // Label 334: @6342
2815	/ 6342 / GIM_Try_CheckFeatures, /On fail goto//Label 335/ GIMT_Encode4(`6367`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 748 //
2816	/ 6349 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
2817	/ 6353 / // MIs[0] fs
2818	/ 6353 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2819	/ 6358 / // (build_vector:{ :[v2f64] } FGR64:{ :[f64] }:$fs, FGR64:{ :[f64] }:$fs) => (FILL_FD_PSEUDO:{ :[v2f64] } FGR64:{ :[f64] }:$fs)*
2820	/ 6358 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2821	/ 6361 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2822	/ 6363 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
2823	/ 6365 / GIR_RootConstrainSelectedInstOperands,
2824	/ 6366 / // GIR_Coverage, 748,
2825	/ 6366 / GIR_EraseRootFromParent_Done,
2826	/ 6367 / // Label 335: @6367
2827	/ 6367 / GIM_Reject,
2828	/ 6368 / // Label 333: @6368
2829	/ 6368 / GIM_Try, /On fail goto//Label 336/ GIMT_Encode4(`6457`),
2830	/ 6373 / GIM_CheckNumOperands, /MI/`0`, /Expected/`5`,
2831	/ 6376 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
2832	/ 6379 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2833	/ 6382 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
2834	/ 6386 / GIM_Try_CheckFeatures, /On fail goto//Label 337/ GIMT_Encode4(`6421`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 745 //
2835	/ 6393 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2836	/ 6397 / // MIs[0] rs
2837	/ 6397 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2838	/ 6402 / // MIs[0] rs
2839	/ 6402 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`3`, /OtherMI/`0`, /OtherOpIdx/`1`,
2840	/ 6407 / // MIs[0] rs
2841	/ 6407 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`4`, /OtherMI/`0`, /OtherOpIdx/`1`,
2842	/* 6412 / // (build_vector:{ :[v4i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs) => (FILL_W:{ :[v4i32] } GPR32Opnd:{ :[i32] }:$rs)
2843	/ 6412 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_W),
2844	/ 6415 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2845	/ 6417 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2846	/ 6419 / GIR_RootConstrainSelectedInstOperands,
2847	/ 6420 / // GIR_Coverage, 745,
2848	/ 6420 / GIR_EraseRootFromParent_Done,
2849	/ 6421 / // Label 337: @6421
2850	/ 6421 / GIM_Try_CheckFeatures, /On fail goto//Label 338/ GIMT_Encode4(`6456`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 747 //
2851	/ 6428 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
2852	/ 6432 / // MIs[0] fs
2853	/ 6432 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2854	/ 6437 / // MIs[0] fs
2855	/ 6437 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`3`, /OtherMI/`0`, /OtherOpIdx/`1`,
2856	/ 6442 / // MIs[0] fs
2857	/ 6442 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`4`, /OtherMI/`0`, /OtherOpIdx/`1`,
2858	/ 6447 / // (build_vector:{ :[v4f32] } FGR32:{ :[f32] }:$fs, FGR32:{ :[f32] }:$fs, FGR32:{ :[f32] }:$fs, FGR32:{ :[f32] }:$fs) => (FILL_FW_PSEUDO:{ :[v4f32] } FGR32:{ :[f32] }:$fs)*
2859	/ 6447 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2860	/ 6450 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2861	/ 6452 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
2862	/ 6454 / GIR_RootConstrainSelectedInstOperands,
2863	/ 6455 / // GIR_Coverage, 747,
2864	/ 6455 / GIR_EraseRootFromParent_Done,
2865	/ 6456 / // Label 338: @6456
2866	/ 6456 / GIM_Reject,
2867	/ 6457 / // Label 336: @6457
2868	/ 6457 / GIM_Try_CheckFeatures, /On fail goto//Label 339/ GIMT_Encode4(`6525`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 744 //
2869	/ 6464 / GIM_CheckNumOperands, /MI/`0`, /Expected/`9`,
2870	/ 6467 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
2871	/ 6470 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2872	/ 6473 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
2873	/ 6477 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2874	/ 6481 / // MIs[0] rs
2875	/ 6481 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2876	/ 6486 / // MIs[0] rs
2877	/ 6486 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`3`, /OtherMI/`0`, /OtherOpIdx/`1`,
2878	/ 6491 / // MIs[0] rs
2879	/ 6491 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`4`, /OtherMI/`0`, /OtherOpIdx/`1`,
2880	/ 6496 / // MIs[0] rs
2881	/ 6496 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`5`, /OtherMI/`0`, /OtherOpIdx/`1`,
2882	/ 6501 / // MIs[0] rs
2883	/ 6501 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`6`, /OtherMI/`0`, /OtherOpIdx/`1`,
2884	/ 6506 / // MIs[0] rs
2885	/ 6506 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`7`, /OtherMI/`0`, /OtherOpIdx/`1`,
2886	/ 6511 / // MIs[0] rs
2887	/ 6511 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`8`, /OtherMI/`0`, /OtherOpIdx/`1`,
2888	/* 6516 / // (build_vector:{ :[v8i16] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs) => (FILL_H:{ :[v8i16] } GPR32Opnd:{ :[i32] }:$rs)
2889	/ 6516 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_H),
2890	/ 6519 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2891	/ 6521 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2892	/ 6523 / GIR_RootConstrainSelectedInstOperands,
2893	/ 6524 / // GIR_Coverage, 744,
2894	/ 6524 / GIR_EraseRootFromParent_Done,
2895	/ 6525 / // Label 339: @6525
2896	/ 6525 / GIM_Try_CheckFeatures, /On fail goto//Label 340/ GIMT_Encode4(`6633`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 743 //
2897	/ 6532 / GIM_CheckNumOperands, /MI/`0`, /Expected/`17`,
2898	/ 6535 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
2899	/ 6538 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
2900	/ 6541 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
2901	/ 6545 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2902	/ 6549 / // MIs[0] rs
2903	/ 6549 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`2`, /OtherMI/`0`, /OtherOpIdx/`1`,
2904	/ 6554 / // MIs[0] rs
2905	/ 6554 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`3`, /OtherMI/`0`, /OtherOpIdx/`1`,
2906	/ 6559 / // MIs[0] rs
2907	/ 6559 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`4`, /OtherMI/`0`, /OtherOpIdx/`1`,
2908	/ 6564 / // MIs[0] rs
2909	/ 6564 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`5`, /OtherMI/`0`, /OtherOpIdx/`1`,
2910	/ 6569 / // MIs[0] rs
2911	/ 6569 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`6`, /OtherMI/`0`, /OtherOpIdx/`1`,
2912	/ 6574 / // MIs[0] rs
2913	/ 6574 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`7`, /OtherMI/`0`, /OtherOpIdx/`1`,
2914	/ 6579 / // MIs[0] rs
2915	/ 6579 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`8`, /OtherMI/`0`, /OtherOpIdx/`1`,
2916	/ 6584 / // MIs[0] rs
2917	/ 6584 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`9`, /OtherMI/`0`, /OtherOpIdx/`1`,
2918	/ 6589 / // MIs[0] rs
2919	/ 6589 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`10`, /OtherMI/`0`, /OtherOpIdx/`1`,
2920	/ 6594 / // MIs[0] rs
2921	/ 6594 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`11`, /OtherMI/`0`, /OtherOpIdx/`1`,
2922	/ 6599 / // MIs[0] rs
2923	/ 6599 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`12`, /OtherMI/`0`, /OtherOpIdx/`1`,
2924	/ 6604 / // MIs[0] rs
2925	/ 6604 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`13`, /OtherMI/`0`, /OtherOpIdx/`1`,
2926	/ 6609 / // MIs[0] rs
2927	/ 6609 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`14`, /OtherMI/`0`, /OtherOpIdx/`1`,
2928	/ 6614 / // MIs[0] rs
2929	/ 6614 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`15`, /OtherMI/`0`, /OtherOpIdx/`1`,
2930	/ 6619 / // MIs[0] rs
2931	/ 6619 / GIM_CheckIsSameOperand, /MI/`0`, /OpIdx/`16`, /OtherMI/`0`, /OtherOpIdx/`1`,
2932	/* 6624 / // (build_vector:{ :[v16i8] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rs) => (FILL_B:{ :[v16i8] } GPR32Opnd:{ :[i32] }:$rs)
2933	/ 6624 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FILL_B),
2934	/ 6627 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
2935	/ 6629 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
2936	/ 6631 / GIR_RootConstrainSelectedInstOperands,
2937	/ 6632 / // GIR_Coverage, 743,
2938	/ 6632 / GIR_EraseRootFromParent_Done,
2939	/ 6633 / // Label 340: @6633
2940	/ 6633 / GIM_Reject,
2941	/ 6634 / // Label 12: @6634
2942	/ 6634 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 349/ GIMT_Encode4(`10627`),
2943	/ 6645 / /GILLT_s32//Label 341/ GIMT_Encode4(`6677`),
2944	/ 6649 / /GILLT_s64//Label 342/ GIMT_Encode4(`6946`),
2945	/ 6653 / /GILLT_v4s8//Label 343/ GIMT_Encode4(`7000`),
2946	/ 6657 / /GILLT_v16s8//Label 344/ GIMT_Encode4(`7058`),
2947	/ 6661 / /GILLT_v2s16//Label 345/ GIMT_Encode4(`7703`),
2948	/ 6665 / /GILLT_v8s16//Label 346/ GIMT_Encode4(`7761`),
2949	/ 6669 / /GILLT_v4s32//Label 347/ GIMT_Encode4(`8625`),
2950	/ 6673 / /GILLT_v2s64//Label 348/ GIMT_Encode4(`9593`),
2951	/ 6677 / // Label 341: @6677
2952	/ 6677 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`5`), /)//default://Label 353/ GIMT_Encode4(`6945`),
2953	/ 6688 / /GILLT_s32//Label 350/ GIMT_Encode4(`6708`), GIMT_Encode4(`0`),
2954	/ 6696 / /GILLT_v4s8//Label 351/ GIMT_Encode4(`6839`), GIMT_Encode4(`0`),
2955	/ 6704 / /GILLT_v2s16//Label 352/ GIMT_Encode4(`6892`),
2956	/ 6708 / // Label 350: @6708
2957	/ 6708 / GIM_Try_CheckFeatures, /On fail goto//Label 354/ GIMT_Encode4(`6730`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 138 //
2958	/ 6715 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2959	/ 6719 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
2960	/ 6723 / // (bitconvert:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs) => (MFC1:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs)
2961	/ 6723 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MFC1),
2962	/ 6728 / GIR_RootConstrainSelectedInstOperands,
2963	/ 6729 / // GIR_Coverage, 138,
2964	/ 6729 / GIR_Done,
2965	/ 6730 / // Label 354: @6730
2966	/ 6730 / GIM_Try_CheckFeatures, /On fail goto//Label 355/ GIMT_Encode4(`6752`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 139 //
2967	/ 6737 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
2968	/ 6741 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2969	/ 6745 / // (bitconvert:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt) => (MTC1:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt)
2970	/ 6745 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MTC1),
2971	/ 6750 / GIR_RootConstrainSelectedInstOperands,
2972	/ 6751 / // GIR_Coverage, 139,
2973	/ 6751 / GIR_Done,
2974	/ 6752 / // Label 355: @6752
2975	/ 6752 / GIM_Try_CheckFeatures, /On fail goto//Label 356/ GIMT_Encode4(`6774`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1181 //
2976	/ 6759 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2977	/ 6763 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
2978	/ 6767 / // (bitconvert:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs) => (MFC1_MM:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs)
2979	/ 6767 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MFC1_MM),
2980	/ 6772 / GIR_RootConstrainSelectedInstOperands,
2981	/ 6773 / // GIR_Coverage, 1181,
2982	/ 6773 / GIR_Done,
2983	/ 6774 / // Label 356: @6774
2984	/ 6774 / GIM_Try, /On fail goto//Label 357/ GIMT_Encode4(`6816`),
2985	/ 6779 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
2986	/ 6783 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
2987	/ 6787 / GIM_Try_CheckFeatures, /On fail goto//Label 358/ GIMT_Encode4(`6801`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1182 //
2988	/ 6794 / // (bitconvert:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt) => (MTC1_MM:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt)
2989	/ 6794 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MTC1_MM),
2990	/ 6799 / GIR_RootConstrainSelectedInstOperands,
2991	/ 6800 / // GIR_Coverage, 1182,
2992	/ 6800 / GIR_Done,
2993	/ 6801 / // Label 358: @6801
2994	/ 6801 / GIM_Try_CheckFeatures, /On fail goto//Label 359/ GIMT_Encode4(`6815`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1196 //
2995	/ 6808 / // (bitconvert:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt) => (MTC1_MMR6:{ :[f32] } GPR32Opnd:{ :[i32] }:$rt)
2996	/ 6808 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MTC1_MMR6),
2997	/ 6813 / GIR_RootConstrainSelectedInstOperands,
2998	/ 6814 / // GIR_Coverage, 1196,
2999	/ 6814 / GIR_Done,
3000	/ 6815 / // Label 359: @6815
3001	/ 6815 / GIM_Reject,
3002	/ 6816 / // Label 357: @6816
3003	/ 6816 / GIM_Try_CheckFeatures, /On fail goto//Label 360/ GIMT_Encode4(`6838`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1197 //
3004	/ 6823 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
3005	/ 6827 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
3006	/ 6831 / // (bitconvert:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs) => (MFC1_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs)
3007	/ 6831 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MFC1_MMR6),
3008	/ 6836 / GIR_RootConstrainSelectedInstOperands,
3009	/ 6837 / // GIR_Coverage, 1197,
3010	/ 6837 / GIR_Done,
3011	/ 6838 / // Label 360: @6838
3012	/ 6838 / GIM_Reject,
3013	/ 6839 / // Label 351: @6839
3014	/ 6839 / GIM_Try_CheckFeatures, /On fail goto//Label 361/ GIMT_Encode4(`6865`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2041 //
3015	/ 6846 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
3016	/ 6850 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3017	/ 6854 / // (bitconvert:{ :[i32] } DSPR:{ :[v4i8] }:$src) => (COPY_TO_REGCLASS:{ :[i32] } DSPR:{ :[v4i8] }:$src, GPR32:{ :[i32] })*
3018	/ 6854 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3019	/ 6859 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR32RegClassID),
3020	/ 6864 / // GIR_Coverage, 2041,
3021	/ 6864 / GIR_Done,
3022	/ 6865 / // Label 361: @6865
3023	/ 6865 / GIM_Try_CheckFeatures, /On fail goto//Label 362/ GIMT_Encode4(`6891`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2045 //
3024	/ 6872 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
3025	/ 6876 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3026	/ 6880 / // (bitconvert:{ :[f32] } DSPR:{ :[v4i8] }:$src) => (COPY_TO_REGCLASS:{ :[f32] } DSPR:{ :[v4i8] }:$src, FGR32:{ :[i32] })*
3027	/ 6880 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3028	/ 6885 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::FGR32RegClassID),
3029	/ 6890 / // GIR_Coverage, 2045,
3030	/ 6890 / GIR_Done,
3031	/ 6891 / // Label 362: @6891
3032	/ 6891 / GIM_Reject,
3033	/ 6892 / // Label 352: @6892
3034	/ 6892 / GIM_Try_CheckFeatures, /On fail goto//Label 363/ GIMT_Encode4(`6918`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2040 //
3035	/ 6899 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
3036	/ 6903 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3037	/ 6907 / // (bitconvert:{ :[i32] } DSPR:{ :[v2i16] }:$src) => (COPY_TO_REGCLASS:{ :[i32] } DSPR:{ :[v2i16] }:$src, GPR32:{ :[i32] })*
3038	/ 6907 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3039	/ 6912 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR32RegClassID),
3040	/ 6917 / // GIR_Coverage, 2040,
3041	/ 6917 / GIR_Done,
3042	/ 6918 / // Label 363: @6918
3043	/ 6918 / GIM_Try_CheckFeatures, /On fail goto//Label 364/ GIMT_Encode4(`6944`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2044 //
3044	/ 6925 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
3045	/ 6929 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3046	/ 6933 / // (bitconvert:{ :[f32] } DSPR:{ :[v2i16] }:$src) => (COPY_TO_REGCLASS:{ :[f32] } DSPR:{ :[v2i16] }:$src, FGR32:{ :[i32] })*
3047	/ 6933 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3048	/ 6938 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::FGR32RegClassID),
3049	/ 6943 / // GIR_Coverage, 2044,
3050	/ 6943 / GIR_Done,
3051	/ 6944 / // Label 364: @6944
3052	/ 6944 / GIM_Reject,
3053	/ 6945 / // Label 353: @6945
3054	/ 6945 / GIM_Reject,
3055	/ 6946 / // Label 342: @6946
3056	/ 6946 / GIM_Try, /On fail goto//Label 365/ GIMT_Encode4(`6999`),
3057	/ 6951 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
3058	/ 6954 / GIM_Try_CheckFeatures, /On fail goto//Label 366/ GIMT_Encode4(`6976`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 140 //
3059	/ 6961 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
3060	/ 6965 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
3061	/ 6969 / // (bitconvert:{ :[f64] } GPR64Opnd:{ :[i64] }:$rt) => (DMTC1:{ :[f64] } GPR64Opnd:{ :[i64] }:$rt)
3062	/ 6969 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMTC1),
3063	/ 6974 / GIR_RootConstrainSelectedInstOperands,
3064	/ 6975 / // GIR_Coverage, 140,
3065	/ 6975 / GIR_Done,
3066	/ 6976 / // Label 366: @6976
3067	/ 6976 / GIM_Try_CheckFeatures, /On fail goto//Label 367/ GIMT_Encode4(`6998`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 141 //
3068	/ 6983 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
3069	/ 6987 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
3070	/ 6991 / // (bitconvert:{ :[i64] } FGR64Opnd:{ :[f64] }:$fs) => (DMFC1:{ :[i64] } FGR64Opnd:{ :[f64] }:$fs)
3071	/ 6991 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMFC1),
3072	/ 6996 / GIR_RootConstrainSelectedInstOperands,
3073	/ 6997 / // GIR_Coverage, 141,
3074	/ 6997 / GIR_Done,
3075	/ 6998 / // Label 367: @6998
3076	/ 6998 / GIM_Reject,
3077	/ 6999 / // Label 365: @6999
3078	/ 6999 / GIM_Reject,
3079	/ 7000 / // Label 343: @7000
3080	/ 7000 / GIM_Try, /On fail goto//Label 368/ GIMT_Encode4(`7057`),
3081	/ 7005 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
3082	/ 7008 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3083	/ 7012 / GIM_Try_CheckFeatures, /On fail goto//Label 369/ GIMT_Encode4(`7034`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2043 //
3084	/ 7019 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
3085	/ 7023 / // (bitconvert:{ :[v4i8] } GPR32:{ :[i32] }:$src) => (COPY_TO_REGCLASS:{ :[v4i8] } GPR32:{ :[i32] }:$src, DSPR:{ :[i32] })*
3086	/ 7023 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3087	/ 7028 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
3088	/ 7033 / // GIR_Coverage, 2043,
3089	/ 7033 / GIR_Done,
3090	/ 7034 / // Label 369: @7034
3091	/ 7034 / GIM_Try_CheckFeatures, /On fail goto//Label 370/ GIMT_Encode4(`7056`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2047 //
3092	/ 7041 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
3093	/ 7045 / // (bitconvert:{ :[v4i8] } FGR32:{ :[f32] }:$src) => (COPY_TO_REGCLASS:{ :[v4i8] } FGR32:{ :[f32] }:$src, DSPR:{ :[i32] })*
3094	/ 7045 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3095	/ 7050 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
3096	/ 7055 / // GIR_Coverage, 2047,
3097	/ 7055 / GIR_Done,
3098	/ 7056 / // Label 370: @7056
3099	/ 7056 / GIM_Reject,
3100	/ 7057 / // Label 368: @7057
3101	/ 7057 / GIM_Reject,
3102	/ 7058 / // Label 344: @7058
3103	/ 7058 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`5`), GIMT_Encode2(`8`), /)//default://Label 374/ GIMT_Encode4(`7702`),
3104	/ 7069 / /GILLT_v8s16//Label 371/ GIMT_Encode4(`7081`),
3105	/ 7073 / /GILLT_v4s32//Label 372/ GIMT_Encode4(`7266`),
3106	/ 7077 / /GILLT_v2s64//Label 373/ GIMT_Encode4(`7437`),
3107	/ 7081 / // Label 371: @7081
3108	/ 7081 / GIM_Try, /On fail goto//Label 375/ GIMT_Encode4(`7265`),
3109	/ 7086 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
3110	/ 7090 / GIM_Try_CheckFeatures, /On fail goto//Label 376/ GIMT_Encode4(`7108`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2131 //
3111	/ 7097 / // (bitconvert:{ :[v16i8] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v8i16:{ :[v8i16] }:$src, MSA128B:{ :[i32] })*
3112	/ 7097 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3113	/ 7102 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3114	/ 7107 / // GIR_Coverage, 2131,
3115	/ 7107 / GIR_Done,
3116	/ 7108 / // Label 376: @7108
3117	/ 7108 / GIM_Try_CheckFeatures, /On fail goto//Label 377/ GIMT_Encode4(`7126`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2134 //
3118	/ 7115 / // (bitconvert:{ :[v16i8] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v8f16:{ :[v8f16] }:$src, MSA128B:{ :[i32] })*
3119	/ 7115 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3120	/ 7120 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3121	/ 7125 / // GIR_Coverage, 2134,
3122	/ 7125 / GIR_Done,
3123	/ 7126 / // Label 377: @7126
3124	/ 7126 / GIM_Try_CheckFeatures, /On fail goto//Label 378/ GIMT_Encode4(`7195`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2168 //
3125	/* 7133 / // (bitconvert:{ :[v16i8] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v8i16:{ :[v8i16] }:$src, MSA128B:{ :[i32] }), 177:{ :[i32] }), MSA128B:{ :[i32] })
3126	/ 7133 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3127	/ 7136 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3128	/ 7140 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3129	/ 7145 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3130	/ 7149 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3131	/ 7154 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3132	/ 7157 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3133	/ 7161 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3134	/ 7166 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3135	/ 7169 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3136	/ 7179 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3137	/ 7181 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3138	/ 7184 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3139	/ 7186 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3140	/ 7189 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3141	/ 7194 / // GIR_Coverage, 2168,
3142	/ 7194 / GIR_EraseRootFromParent_Done,
3143	/ 7195 / // Label 378: @7195
3144	/ 7195 / GIM_Try_CheckFeatures, /On fail goto//Label 379/ GIMT_Encode4(`7264`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2173 //
3145	/* 7202 / // (bitconvert:{ :[v16i8] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v8f16:{ :[v8f16] }:$src, MSA128B:{ :[i32] }), 177:{ :[i32] }), MSA128B:{ :[i32] })
3146	/ 7202 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3147	/ 7205 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3148	/ 7209 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3149	/ 7214 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3150	/ 7218 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3151	/ 7223 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3152	/ 7226 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3153	/ 7230 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3154	/ 7235 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3155	/ 7238 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3156	/ 7248 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3157	/ 7250 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3158	/ 7253 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3159	/ 7255 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3160	/ 7258 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3161	/ 7263 / // GIR_Coverage, 2173,
3162	/ 7263 / GIR_EraseRootFromParent_Done,
3163	/ 7264 / // Label 379: @7264
3164	/ 7264 / GIM_Reject,
3165	/ 7265 / // Label 375: @7265
3166	/ 7265 / GIM_Reject,
3167	/ 7266 / // Label 372: @7266
3168	/ 7266 / GIM_Try, /On fail goto//Label 380/ GIMT_Encode4(`7436`),
3169	/ 7271 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
3170	/ 7275 / GIM_Try_CheckFeatures, /On fail goto//Label 381/ GIMT_Encode4(`7293`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2132 //
3171	/ 7282 / // (bitconvert:{ :[v16i8] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v4i32:{ :[v4i32] }:$src, MSA128B:{ :[i32] })*
3172	/ 7282 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3173	/ 7287 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3174	/ 7292 / // GIR_Coverage, 2132,
3175	/ 7292 / GIR_Done,
3176	/ 7293 / // Label 381: @7293
3177	/ 7293 / GIM_Try_CheckFeatures, /On fail goto//Label 382/ GIMT_Encode4(`7311`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2135 //
3178	/ 7300 / // (bitconvert:{ :[v16i8] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v4f32:{ :[v4f32] }:$src, MSA128B:{ :[i32] })*
3179	/ 7300 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3180	/ 7305 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3181	/ 7310 / // GIR_Coverage, 2135,
3182	/ 7310 / GIR_Done,
3183	/ 7311 / // Label 382: @7311
3184	/ 7311 / GIM_Try_CheckFeatures, /On fail goto//Label 383/ GIMT_Encode4(`7373`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2178 //
3185	/* 7318 / // (bitconvert:{ :[v16i8] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v4i32:{ :[v4i32] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128B:{ :[i32] })
3186	/ 7318 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3187	/ 7321 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3188	/ 7325 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3189	/ 7330 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3190	/ 7334 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3191	/ 7339 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3192	/ 7342 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3193	/ 7346 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3194	/ 7351 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3195	/ 7354 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3196	/ 7357 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3197	/ 7359 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3198	/ 7362 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3199	/ 7364 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3200	/ 7367 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3201	/ 7372 / // GIR_Coverage, 2178,
3202	/ 7372 / GIR_EraseRootFromParent_Done,
3203	/ 7373 / // Label 383: @7373
3204	/ 7373 / GIM_Try_CheckFeatures, /On fail goto//Label 384/ GIMT_Encode4(`7435`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2183 //
3205	/* 7380 / // (bitconvert:{ :[v16i8] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v4f32:{ :[v4f32] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128B:{ :[i32] })
3206	/ 7380 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3207	/ 7383 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3208	/ 7387 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3209	/ 7392 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3210	/ 7396 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3211	/ 7401 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3212	/ 7404 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3213	/ 7408 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3214	/ 7413 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3215	/ 7416 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3216	/ 7419 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3217	/ 7421 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3218	/ 7424 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3219	/ 7426 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3220	/ 7429 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3221	/ 7434 / // GIR_Coverage, 2183,
3222	/ 7434 / GIR_EraseRootFromParent_Done,
3223	/ 7435 / // Label 384: @7435
3224	/ 7435 / GIM_Reject,
3225	/ 7436 / // Label 380: @7436
3226	/ 7436 / GIM_Reject,
3227	/ 7437 / // Label 373: @7437
3228	/ 7437 / GIM_Try, /On fail goto//Label 385/ GIMT_Encode4(`7701`),
3229	/ 7442 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
3230	/ 7446 / GIM_Try_CheckFeatures, /On fail goto//Label 386/ GIMT_Encode4(`7464`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2133 //
3231	/ 7453 / // (bitconvert:{ :[v16i8] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v2i64:{ :[v2i64] }:$src, MSA128B:{ :[i32] })*
3232	/ 7453 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3233	/ 7458 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3234	/ 7463 / // GIR_Coverage, 2133,
3235	/ 7463 / GIR_Done,
3236	/ 7464 / // Label 386: @7464
3237	/ 7464 / GIM_Try_CheckFeatures, /On fail goto//Label 387/ GIMT_Encode4(`7482`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2136 //
3238	/ 7471 / // (bitconvert:{ :[v16i8] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } v2f64:{ :[v2f64] }:$src, MSA128B:{ :[i32] })*
3239	/ 7471 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3240	/ 7476 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3241	/ 7481 / // GIR_Coverage, 2136,
3242	/ 7481 / GIR_Done,
3243	/ 7482 / // Label 387: @7482
3244	/ 7482 / GIM_Try_CheckFeatures, /On fail goto//Label 388/ GIMT_Encode4(`7591`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2188 //
3245	/* 7489 / // (bitconvert:{ :[v16i8] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v2i64:{ :[v2i64] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128B:{ :[i32] })
3246	/ 7489 / GIR_MakeTempReg, /TempRegID/`3`, /TypeID/GILLT_v16s8,
3247	/ 7492 / GIR_BuildMI, /InsnID/`4`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3248	/ 7496 / GIR_AddTempRegister, /InsnID/`4`, /TempRegID/`3`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3249	/ 7501 / GIR_Copy, /NewInsnID/`4`, /OldInsnID/`0`, /OpIdx/`1`, // src
3250	/ 7505 / GIR_ConstrainOperandRC, /InsnID/`4`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3251	/ 7510 / GIR_MakeTempReg, /TempRegID/`2`, /TypeID/GILLT_v16s8,
3252	/ 7513 / GIR_BuildMI, /InsnID/`3`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3253	/ 7517 / GIR_AddTempRegister, /InsnID/`3`, /TempRegID/`2`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3254	/ 7522 / GIR_AddSimpleTempRegister, /InsnID/`3`, /TempRegID/`3`,
3255	/ 7525 / GIR_AddImm8, /InsnID/`3`, /Imm/`27`,
3256	/ 7528 / GIR_ConstrainSelectedInstOperands, /InsnID/`3`,
3257	/ 7530 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3258	/ 7533 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3259	/ 7537 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3260	/ 7542 / GIR_AddSimpleTempRegister, /InsnID/`2`, /TempRegID/`2`,
3261	/ 7545 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3262	/ 7550 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3263	/ 7553 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3264	/ 7557 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3265	/ 7562 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3266	/ 7565 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3267	/ 7575 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3268	/ 7577 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3269	/ 7580 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3270	/ 7582 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3271	/ 7585 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3272	/ 7590 / // GIR_Coverage, 2188,
3273	/ 7590 / GIR_EraseRootFromParent_Done,
3274	/ 7591 / // Label 388: @7591
3275	/ 7591 / GIM_Try_CheckFeatures, /On fail goto//Label 389/ GIMT_Encode4(`7700`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2193 //
3276	/* 7598 / // (bitconvert:{ :[v16i8] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v16i8] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v2f64:{ :[v2f64] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128B:{ :[i32] })
3277	/ 7598 / GIR_MakeTempReg, /TempRegID/`3`, /TypeID/GILLT_v16s8,
3278	/ 7601 / GIR_BuildMI, /InsnID/`4`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3279	/ 7605 / GIR_AddTempRegister, /InsnID/`4`, /TempRegID/`3`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3280	/ 7610 / GIR_Copy, /NewInsnID/`4`, /OldInsnID/`0`, /OpIdx/`1`, // src
3281	/ 7614 / GIR_ConstrainOperandRC, /InsnID/`4`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3282	/ 7619 / GIR_MakeTempReg, /TempRegID/`2`, /TypeID/GILLT_v16s8,
3283	/ 7622 / GIR_BuildMI, /InsnID/`3`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3284	/ 7626 / GIR_AddTempRegister, /InsnID/`3`, /TempRegID/`2`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3285	/ 7631 / GIR_AddSimpleTempRegister, /InsnID/`3`, /TempRegID/`3`,
3286	/ 7634 / GIR_AddImm8, /InsnID/`3`, /Imm/`27`,
3287	/ 7637 / GIR_ConstrainSelectedInstOperands, /InsnID/`3`,
3288	/ 7639 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3289	/ 7642 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3290	/ 7646 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3291	/ 7651 / GIR_AddSimpleTempRegister, /InsnID/`2`, /TempRegID/`2`,
3292	/ 7654 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3293	/ 7659 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3294	/ 7662 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3295	/ 7666 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3296	/ 7671 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3297	/ 7674 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3298	/ 7684 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3299	/ 7686 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3300	/ 7689 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3301	/ 7691 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3302	/ 7694 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3303	/ 7699 / // GIR_Coverage, 2193,
3304	/ 7699 / GIR_EraseRootFromParent_Done,
3305	/ 7700 / // Label 389: @7700
3306	/ 7700 / GIM_Reject,
3307	/ 7701 / // Label 385: @7701
3308	/ 7701 / GIM_Reject,
3309	/ 7702 / // Label 374: @7702
3310	/ 7702 / GIM_Reject,
3311	/ 7703 / // Label 345: @7703
3312	/ 7703 / GIM_Try, /On fail goto//Label 390/ GIMT_Encode4(`7760`),
3313	/ 7708 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
3314	/ 7711 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
3315	/ 7715 / GIM_Try_CheckFeatures, /On fail goto//Label 391/ GIMT_Encode4(`7737`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2042 //
3316	/ 7722 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
3317	/ 7726 / // (bitconvert:{ :[v2i16] } GPR32:{ :[i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i16] } GPR32:{ :[i32] }:$src, DSPR:{ :[i32] })*
3318	/ 7726 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3319	/ 7731 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
3320	/ 7736 / // GIR_Coverage, 2042,
3321	/ 7736 / GIR_Done,
3322	/ 7737 / // Label 391: @7737
3323	/ 7737 / GIM_Try_CheckFeatures, /On fail goto//Label 392/ GIMT_Encode4(`7759`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2046 //
3324	/ 7744 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
3325	/ 7748 / // (bitconvert:{ :[v2i16] } FGR32:{ :[f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i16] } FGR32:{ :[f32] }:$src, DSPR:{ :[i32] })*
3326	/ 7748 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3327	/ 7753 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
3328	/ 7758 / // GIR_Coverage, 2046,
3329	/ 7758 / GIR_Done,
3330	/ 7759 / // Label 392: @7759
3331	/ 7759 / GIM_Reject,
3332	/ 7760 / // Label 390: @7760
3333	/ 7760 / GIM_Reject,
3334	/ 7761 / // Label 346: @7761
3335	/ 7761 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 397/ GIMT_Encode4(`8624`),
3336	/ 7772 / /GILLT_v16s8//Label 393/ GIMT_Encode4(`7792`), GIMT_Encode4(`0`),
3337	/ 7780 / /GILLT_v8s16//Label 394/ GIMT_Encode4(`7959`),
3338	/ 7784 / /GILLT_v4s32//Label 395/ GIMT_Encode4(`8006`),
3339	/ 7788 / /GILLT_v2s64//Label 396/ GIMT_Encode4(`8329`),
3340	/ 7792 / // Label 393: @7792
3341	/ 7792 / GIM_Try, /On fail goto//Label 398/ GIMT_Encode4(`7958`),
3342	/ 7797 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
3343	/ 7801 / GIM_Try_CheckFeatures, /On fail goto//Label 399/ GIMT_Encode4(`7819`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2137 //
3344	/ 7808 / // (bitconvert:{ :[v8i16] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v16i8:{ :[v16i8] }:$src, MSA128H:{ :[i32] })*
3345	/ 7808 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3346	/ 7813 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3347	/ 7818 / // GIR_Coverage, 2137,
3348	/ 7818 / GIR_Done,
3349	/ 7819 / // Label 399: @7819
3350	/ 7819 / GIM_Try_CheckFeatures, /On fail goto//Label 400/ GIMT_Encode4(`7888`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2162 //
3351	/* 7826 / // (bitconvert:{ :[v8i16] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3352	/ 7826 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3353	/ 7829 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3354	/ 7833 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3355	/ 7838 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3356	/ 7842 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3357	/ 7847 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3358	/ 7850 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3359	/ 7854 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3360	/ 7859 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3361	/ 7862 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3362	/ 7872 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3363	/ 7874 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3364	/ 7877 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3365	/ 7879 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3366	/ 7882 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3367	/ 7887 / // GIR_Coverage, 2162,
3368	/ 7887 / GIR_EraseRootFromParent_Done,
3369	/ 7888 / // Label 400: @7888
3370	/ 7888 / GIM_Try_CheckFeatures, /On fail goto//Label 401/ GIMT_Encode4(`7957`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2163 //
3371	/* 7895 / // (bitconvert:{ :[v8f16] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3372	/ 7895 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3373	/ 7898 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3374	/ 7902 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3375	/ 7907 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3376	/ 7911 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3377	/ 7916 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3378	/ 7919 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3379	/ 7923 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3380	/ 7928 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3381	/ 7931 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3382	/ 7941 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3383	/ 7943 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3384	/ 7946 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3385	/ 7948 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3386	/ 7951 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3387	/ 7956 / // GIR_Coverage, 2163,
3388	/ 7956 / GIR_EraseRootFromParent_Done,
3389	/ 7957 / // Label 401: @7957
3390	/ 7957 / GIM_Reject,
3391	/ 7958 / // Label 398: @7958
3392	/ 7958 / GIM_Reject,
3393	/ 7959 / // Label 394: @7959
3394	/ 7959 / GIM_Try, /On fail goto//Label 402/ GIMT_Encode4(`8005`),
3395	/ 7964 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
3396	/ 7968 / GIM_Try_CheckFeatures, /On fail goto//Label 403/ GIMT_Encode4(`7986`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2125 //
3397	/ 7975 / // (bitconvert:{ :[v8i16] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:{ :[v8f16] }:$src, MSA128H:{ :[i32] })*
3398	/ 7975 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3399	/ 7980 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3400	/ 7985 / // GIR_Coverage, 2125,
3401	/ 7985 / GIR_Done,
3402	/ 7986 / // Label 403: @7986
3403	/ 7986 / GIM_Try_CheckFeatures, /On fail goto//Label 404/ GIMT_Encode4(`8004`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2128 //
3404	/ 7993 / // (bitconvert:{ :[v8f16] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } v8i16:{ :[v8i16] }:$src, MSA128H:{ :[i32] })*
3405	/ 7993 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3406	/ 7998 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3407	/ 8003 / // GIR_Coverage, 2128,
3408	/ 8003 / GIR_Done,
3409	/ 8004 / // Label 404: @8004
3410	/ 8004 / GIM_Reject,
3411	/ 8005 / // Label 402: @8005
3412	/ 8005 / GIM_Reject,
3413	/ 8006 / // Label 395: @8006
3414	/ 8006 / GIM_Try, /On fail goto//Label 405/ GIMT_Encode4(`8328`),
3415	/ 8011 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
3416	/ 8015 / GIM_Try_CheckFeatures, /On fail goto//Label 406/ GIMT_Encode4(`8033`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2138 //
3417	/ 8022 / // (bitconvert:{ :[v8i16] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v4i32:{ :[v4i32] }:$src, MSA128H:{ :[i32] })*
3418	/ 8022 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3419	/ 8027 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3420	/ 8032 / // GIR_Coverage, 2138,
3421	/ 8032 / GIR_Done,
3422	/ 8033 / // Label 406: @8033
3423	/ 8033 / GIM_Try_CheckFeatures, /On fail goto//Label 407/ GIMT_Encode4(`8051`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2140 //
3424	/ 8040 / // (bitconvert:{ :[v8i16] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v4f32:{ :[v4f32] }:$src, MSA128H:{ :[i32] })*
3425	/ 8040 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3426	/ 8045 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3427	/ 8050 / // GIR_Coverage, 2140,
3428	/ 8050 / GIR_Done,
3429	/ 8051 / // Label 407: @8051
3430	/ 8051 / GIM_Try_CheckFeatures, /On fail goto//Label 408/ GIMT_Encode4(`8120`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2179 //
3431	/* 8058 / // (bitconvert:{ :[v8i16] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v4i32:{ :[v4i32] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3432	/ 8058 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3433	/ 8061 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3434	/ 8065 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3435	/ 8070 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3436	/ 8074 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3437	/ 8079 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3438	/ 8082 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3439	/ 8086 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3440	/ 8091 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3441	/ 8094 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3442	/ 8104 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3443	/ 8106 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3444	/ 8109 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3445	/ 8111 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3446	/ 8114 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3447	/ 8119 / // GIR_Coverage, 2179,
3448	/ 8119 / GIR_EraseRootFromParent_Done,
3449	/ 8120 / // Label 408: @8120
3450	/ 8120 / GIM_Try_CheckFeatures, /On fail goto//Label 409/ GIMT_Encode4(`8189`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2180 //
3451	/* 8127 / // (bitconvert:{ :[v8f16] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v4i32:{ :[v4i32] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3452	/ 8127 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3453	/ 8130 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3454	/ 8134 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3455	/ 8139 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3456	/ 8143 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3457	/ 8148 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3458	/ 8151 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3459	/ 8155 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3460	/ 8160 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3461	/ 8163 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3462	/ 8173 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3463	/ 8175 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3464	/ 8178 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3465	/ 8180 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3466	/ 8183 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3467	/ 8188 / // GIR_Coverage, 2180,
3468	/ 8188 / GIR_EraseRootFromParent_Done,
3469	/ 8189 / // Label 409: @8189
3470	/ 8189 / GIM_Try_CheckFeatures, /On fail goto//Label 410/ GIMT_Encode4(`8258`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2184 //
3471	/* 8196 / // (bitconvert:{ :[v8i16] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v4f32:{ :[v4f32] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3472	/ 8196 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3473	/ 8199 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3474	/ 8203 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3475	/ 8208 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3476	/ 8212 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3477	/ 8217 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3478	/ 8220 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3479	/ 8224 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3480	/ 8229 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3481	/ 8232 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3482	/ 8242 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3483	/ 8244 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3484	/ 8247 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3485	/ 8249 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3486	/ 8252 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3487	/ 8257 / // GIR_Coverage, 2184,
3488	/ 8257 / GIR_EraseRootFromParent_Done,
3489	/ 8258 / // Label 410: @8258
3490	/ 8258 / GIM_Try_CheckFeatures, /On fail goto//Label 411/ GIMT_Encode4(`8327`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2185 //
3491	/* 8265 / // (bitconvert:{ :[v8f16] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v4f32:{ :[v4f32] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128H:{ :[i32] })
3492	/ 8265 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3493	/ 8268 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3494	/ 8272 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3495	/ 8277 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3496	/ 8281 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3497	/ 8286 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3498	/ 8289 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3499	/ 8293 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3500	/ 8298 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3501	/ 8301 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3502	/ 8311 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3503	/ 8313 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3504	/ 8316 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3505	/ 8318 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3506	/ 8321 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3507	/ 8326 / // GIR_Coverage, 2185,
3508	/ 8326 / GIR_EraseRootFromParent_Done,
3509	/ 8327 / // Label 411: @8327
3510	/ 8327 / GIM_Reject,
3511	/ 8328 / // Label 405: @8328
3512	/ 8328 / GIM_Reject,
3513	/ 8329 / // Label 396: @8329
3514	/ 8329 / GIM_Try, /On fail goto//Label 412/ GIMT_Encode4(`8623`),
3515	/ 8334 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
3516	/ 8338 / GIM_Try_CheckFeatures, /On fail goto//Label 413/ GIMT_Encode4(`8356`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2139 //
3517	/ 8345 / // (bitconvert:{ :[v8i16] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v2i64:{ :[v2i64] }:$src, MSA128H:{ :[i32] })*
3518	/ 8345 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3519	/ 8350 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3520	/ 8355 / // GIR_Coverage, 2139,
3521	/ 8355 / GIR_Done,
3522	/ 8356 / // Label 413: @8356
3523	/ 8356 / GIM_Try_CheckFeatures, /On fail goto//Label 414/ GIMT_Encode4(`8374`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2141 //
3524	/ 8363 / // (bitconvert:{ :[v8i16] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v2f64:{ :[v2f64] }:$src, MSA128H:{ :[i32] })*
3525	/ 8363 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3526	/ 8368 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3527	/ 8373 / // GIR_Coverage, 2141,
3528	/ 8373 / GIR_Done,
3529	/ 8374 / // Label 414: @8374
3530	/ 8374 / GIM_Try_CheckFeatures, /On fail goto//Label 415/ GIMT_Encode4(`8436`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2189 //
3531	/* 8381 / // (bitconvert:{ :[v8i16] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v2i64:{ :[v2i64] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128H:{ :[i32] })
3532	/ 8381 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3533	/ 8384 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3534	/ 8388 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3535	/ 8393 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3536	/ 8397 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3537	/ 8402 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3538	/ 8405 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3539	/ 8409 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3540	/ 8414 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3541	/ 8417 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3542	/ 8420 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3543	/ 8422 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3544	/ 8425 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3545	/ 8427 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3546	/ 8430 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3547	/ 8435 / // GIR_Coverage, 2189,
3548	/ 8435 / GIR_EraseRootFromParent_Done,
3549	/ 8436 / // Label 415: @8436
3550	/ 8436 / GIM_Try_CheckFeatures, /On fail goto//Label 416/ GIMT_Encode4(`8498`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2190 //
3551	/* 8443 / // (bitconvert:{ :[v8f16] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v2i64:{ :[v2i64] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128H:{ :[i32] })
3552	/ 8443 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3553	/ 8446 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3554	/ 8450 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3555	/ 8455 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3556	/ 8459 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3557	/ 8464 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3558	/ 8467 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3559	/ 8471 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3560	/ 8476 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3561	/ 8479 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3562	/ 8482 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3563	/ 8484 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3564	/ 8487 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3565	/ 8489 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3566	/ 8492 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3567	/ 8497 / // GIR_Coverage, 2190,
3568	/ 8497 / GIR_EraseRootFromParent_Done,
3569	/ 8498 / // Label 416: @8498
3570	/ 8498 / GIM_Try_CheckFeatures, /On fail goto//Label 417/ GIMT_Encode4(`8560`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2194 //
3571	/* 8505 / // (bitconvert:{ :[v8i16] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v2f64:{ :[v2f64] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128H:{ :[i32] })
3572	/ 8505 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3573	/ 8508 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3574	/ 8512 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3575	/ 8517 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3576	/ 8521 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3577	/ 8526 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3578	/ 8529 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3579	/ 8533 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3580	/ 8538 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3581	/ 8541 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3582	/ 8544 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3583	/ 8546 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3584	/ 8549 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3585	/ 8551 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3586	/ 8554 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3587	/ 8559 / // GIR_Coverage, 2194,
3588	/ 8559 / GIR_EraseRootFromParent_Done,
3589	/ 8560 / // Label 417: @8560
3590	/ 8560 / GIM_Try_CheckFeatures, /On fail goto//Label 418/ GIMT_Encode4(`8622`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2195 //
3591	/* 8567 / // (bitconvert:{ :[v8f16] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v2f64:{ :[v2f64] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128H:{ :[i32] })
3592	/ 8567 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3593	/ 8570 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3594	/ 8574 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3595	/ 8579 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3596	/ 8583 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3597	/ 8588 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3598	/ 8591 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3599	/ 8595 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3600	/ 8600 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3601	/ 8603 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3602	/ 8606 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3603	/ 8608 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3604	/ 8611 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3605	/ 8613 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3606	/ 8616 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3607	/ 8621 / // GIR_Coverage, 2195,
3608	/ 8621 / GIR_EraseRootFromParent_Done,
3609	/ 8622 / // Label 418: @8622
3610	/ 8622 / GIM_Reject,
3611	/ 8623 / // Label 412: @8623
3612	/ 8623 / GIM_Reject,
3613	/ 8624 / // Label 397: @8624
3614	/ 8624 / GIM_Reject,
3615	/ 8625 / // Label 347: @8625
3616	/ 8625 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 423/ GIMT_Encode4(`9592`),
3617	/ 8636 / /GILLT_v16s8//Label 419/ GIMT_Encode4(`8656`), GIMT_Encode4(`0`),
3618	/ 8644 / /GILLT_v8s16//Label 420/ GIMT_Encode4(`8827`),
3619	/ 8648 / /GILLT_v4s32//Label 421/ GIMT_Encode4(`9186`),
3620	/ 8652 / /GILLT_v2s64//Label 422/ GIMT_Encode4(`9233`),
3621	/ 8656 / // Label 419: @8656
3622	/ 8656 / GIM_Try, /On fail goto//Label 424/ GIMT_Encode4(`8826`),
3623	/ 8661 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
3624	/ 8665 / GIM_Try_CheckFeatures, /On fail goto//Label 425/ GIMT_Encode4(`8683`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2142 //
3625	/ 8672 / // (bitconvert:{ :[v4i32] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v16i8:{ :[v16i8] }:$src, MSA128W:{ :[i32] })*
3626	/ 8672 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3627	/ 8677 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3628	/ 8682 / // GIR_Coverage, 2142,
3629	/ 8682 / GIR_Done,
3630	/ 8683 / // Label 425: @8683
3631	/ 8683 / GIM_Try_CheckFeatures, /On fail goto//Label 426/ GIMT_Encode4(`8701`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2152 //
3632	/ 8690 / // (bitconvert:{ :[v4f32] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v16i8:{ :[v16i8] }:$src, MSA128W:{ :[i32] })*
3633	/ 8690 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3634	/ 8695 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3635	/ 8700 / // GIR_Coverage, 2152,
3636	/ 8700 / GIR_Done,
3637	/ 8701 / // Label 426: @8701
3638	/ 8701 / GIM_Try_CheckFeatures, /On fail goto//Label 427/ GIMT_Encode4(`8763`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2164 //
3639	/* 8708 / // (bitconvert:{ :[v4i32] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] })
3640	/ 8708 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3641	/ 8711 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3642	/ 8715 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3643	/ 8720 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3644	/ 8724 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3645	/ 8729 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3646	/ 8732 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3647	/ 8736 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3648	/ 8741 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3649	/ 8744 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3650	/ 8747 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3651	/ 8749 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3652	/ 8752 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3653	/ 8754 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3654	/ 8757 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3655	/ 8762 / // GIR_Coverage, 2164,
3656	/ 8762 / GIR_EraseRootFromParent_Done,
3657	/ 8763 / // Label 427: @8763
3658	/ 8763 / GIM_Try_CheckFeatures, /On fail goto//Label 428/ GIMT_Encode4(`8825`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2165 //
3659	/* 8770 / // (bitconvert:{ :[v4f32] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] })
3660	/ 8770 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v16s8,
3661	/ 8773 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3662	/ 8777 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3663	/ 8782 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3664	/ 8786 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3665	/ 8791 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v16s8,
3666	/ 8794 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3667	/ 8798 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3668	/ 8803 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3669	/ 8806 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
3670	/ 8809 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3671	/ 8811 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3672	/ 8814 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3673	/ 8816 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3674	/ 8819 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3675	/ 8824 / // GIR_Coverage, 2165,
3676	/ 8824 / GIR_EraseRootFromParent_Done,
3677	/ 8825 / // Label 428: @8825
3678	/ 8825 / GIM_Reject,
3679	/ 8826 / // Label 424: @8826
3680	/ 8826 / GIM_Reject,
3681	/ 8827 / // Label 420: @8827
3682	/ 8827 / GIM_Try, /On fail goto//Label 429/ GIMT_Encode4(`9185`),
3683	/ 8832 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
3684	/ 8836 / GIM_Try_CheckFeatures, /On fail goto//Label 430/ GIMT_Encode4(`8854`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2143 //
3685	/ 8843 / // (bitconvert:{ :[v4i32] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v8i16:{ :[v8i16] }:$src, MSA128W:{ :[i32] })*
3686	/ 8843 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3687	/ 8848 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3688	/ 8853 / // GIR_Coverage, 2143,
3689	/ 8853 / GIR_Done,
3690	/ 8854 / // Label 430: @8854
3691	/ 8854 / GIM_Try_CheckFeatures, /On fail goto//Label 431/ GIMT_Encode4(`8872`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2145 //
3692	/ 8861 / // (bitconvert:{ :[v4i32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v8f16:{ :[v8f16] }:$src, MSA128W:{ :[i32] })*
3693	/ 8861 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3694	/ 8866 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3695	/ 8871 / // GIR_Coverage, 2145,
3696	/ 8871 / GIR_Done,
3697	/ 8872 / // Label 431: @8872
3698	/ 8872 / GIM_Try_CheckFeatures, /On fail goto//Label 432/ GIMT_Encode4(`8890`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2153 //
3699	/ 8879 / // (bitconvert:{ :[v4f32] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v8i16:{ :[v8i16] }:$src, MSA128W:{ :[i32] })*
3700	/ 8879 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3701	/ 8884 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3702	/ 8889 / // GIR_Coverage, 2153,
3703	/ 8889 / GIR_Done,
3704	/ 8890 / // Label 432: @8890
3705	/ 8890 / GIM_Try_CheckFeatures, /On fail goto//Label 433/ GIMT_Encode4(`8908`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2155 //
3706	/ 8897 / // (bitconvert:{ :[v4f32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v8f16:{ :[v8f16] }:$src, MSA128W:{ :[i32] })*
3707	/ 8897 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3708	/ 8902 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3709	/ 8907 / // GIR_Coverage, 2155,
3710	/ 8907 / GIR_Done,
3711	/ 8908 / // Label 433: @8908
3712	/ 8908 / GIM_Try_CheckFeatures, /On fail goto//Label 434/ GIMT_Encode4(`8977`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2169 //
3713	/* 8915 / // (bitconvert:{ :[v4i32] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8i16:{ :[v8i16] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3714	/ 8915 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3715	/ 8918 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3716	/ 8922 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3717	/ 8927 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3718	/ 8931 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3719	/ 8936 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3720	/ 8939 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3721	/ 8943 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3722	/ 8948 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3723	/ 8951 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3724	/ 8961 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3725	/ 8963 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3726	/ 8966 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3727	/ 8968 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3728	/ 8971 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3729	/ 8976 / // GIR_Coverage, 2169,
3730	/ 8976 / GIR_EraseRootFromParent_Done,
3731	/ 8977 / // Label 434: @8977
3732	/ 8977 / GIM_Try_CheckFeatures, /On fail goto//Label 435/ GIMT_Encode4(`9046`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2170 //
3733	/* 8984 / // (bitconvert:{ :[v4f32] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8i16:{ :[v8i16] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3734	/ 8984 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3735	/ 8987 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3736	/ 8991 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3737	/ 8996 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3738	/ 9000 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3739	/ 9005 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3740	/ 9008 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3741	/ 9012 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3742	/ 9017 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3743	/ 9020 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3744	/ 9030 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3745	/ 9032 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3746	/ 9035 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3747	/ 9037 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3748	/ 9040 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3749	/ 9045 / // GIR_Coverage, 2170,
3750	/ 9045 / GIR_EraseRootFromParent_Done,
3751	/ 9046 / // Label 435: @9046
3752	/ 9046 / GIM_Try_CheckFeatures, /On fail goto//Label 436/ GIMT_Encode4(`9115`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2174 //
3753	/* 9053 / // (bitconvert:{ :[v4i32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:{ :[v8f16] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3754	/ 9053 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3755	/ 9056 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3756	/ 9060 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3757	/ 9065 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3758	/ 9069 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3759	/ 9074 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3760	/ 9077 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3761	/ 9081 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3762	/ 9086 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3763	/ 9089 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3764	/ 9099 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3765	/ 9101 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3766	/ 9104 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3767	/ 9106 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3768	/ 9109 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3769	/ 9114 / // GIR_Coverage, 2174,
3770	/ 9114 / GIR_EraseRootFromParent_Done,
3771	/ 9115 / // Label 436: @9115
3772	/ 9115 / GIM_Try_CheckFeatures, /On fail goto//Label 437/ GIMT_Encode4(`9184`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2175 //
3773	/* 9122 / // (bitconvert:{ :[v4f32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:{ :[v8f16] }:$src, MSA128H:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3774	/ 9122 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
3775	/ 9125 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3776	/ 9129 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3777	/ 9134 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3778	/ 9138 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
3779	/ 9143 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
3780	/ 9146 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
3781	/ 9150 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3782	/ 9155 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3783	/ 9158 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3784	/ 9168 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3785	/ 9170 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3786	/ 9173 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3787	/ 9175 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3788	/ 9178 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3789	/ 9183 / // GIR_Coverage, 2175,
3790	/ 9183 / GIR_EraseRootFromParent_Done,
3791	/ 9184 / // Label 437: @9184
3792	/ 9184 / GIM_Reject,
3793	/ 9185 / // Label 429: @9185
3794	/ 9185 / GIM_Reject,
3795	/ 9186 / // Label 421: @9186
3796	/ 9186 / GIM_Try, /On fail goto//Label 438/ GIMT_Encode4(`9232`),
3797	/ 9191 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
3798	/ 9195 / GIM_Try_CheckFeatures, /On fail goto//Label 439/ GIMT_Encode4(`9213`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2126 //
3799	/ 9202 / // (bitconvert:{ :[v4i32] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v4f32:{ :[v4f32] }:$src, MSA128W:{ :[i32] })*
3800	/ 9202 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3801	/ 9207 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3802	/ 9212 / // GIR_Coverage, 2126,
3803	/ 9212 / GIR_Done,
3804	/ 9213 / // Label 439: @9213
3805	/ 9213 / GIM_Try_CheckFeatures, /On fail goto//Label 440/ GIMT_Encode4(`9231`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2129 //
3806	/ 9220 / // (bitconvert:{ :[v4f32] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v4i32:{ :[v4i32] }:$src, MSA128W:{ :[i32] })*
3807	/ 9220 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3808	/ 9225 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3809	/ 9230 / // GIR_Coverage, 2129,
3810	/ 9230 / GIR_Done,
3811	/ 9231 / // Label 440: @9231
3812	/ 9231 / GIM_Reject,
3813	/ 9232 / // Label 438: @9232
3814	/ 9232 / GIM_Reject,
3815	/ 9233 / // Label 422: @9233
3816	/ 9233 / GIM_Try, /On fail goto//Label 441/ GIMT_Encode4(`9591`),
3817	/ 9238 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
3818	/ 9242 / GIM_Try_CheckFeatures, /On fail goto//Label 442/ GIMT_Encode4(`9260`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2144 //
3819	/ 9249 / // (bitconvert:{ :[v4i32] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v2i64:{ :[v2i64] }:$src, MSA128W:{ :[i32] })*
3820	/ 9249 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3821	/ 9254 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3822	/ 9259 / // GIR_Coverage, 2144,
3823	/ 9259 / GIR_Done,
3824	/ 9260 / // Label 442: @9260
3825	/ 9260 / GIM_Try_CheckFeatures, /On fail goto//Label 443/ GIMT_Encode4(`9278`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2146 //
3826	/ 9267 / // (bitconvert:{ :[v4i32] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v2f64:{ :[v2f64] }:$src, MSA128W:{ :[i32] })*
3827	/ 9267 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3828	/ 9272 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3829	/ 9277 / // GIR_Coverage, 2146,
3830	/ 9277 / GIR_Done,
3831	/ 9278 / // Label 443: @9278
3832	/ 9278 / GIM_Try_CheckFeatures, /On fail goto//Label 444/ GIMT_Encode4(`9296`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2154 //
3833	/ 9285 / // (bitconvert:{ :[v4f32] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v2i64:{ :[v2i64] }:$src, MSA128W:{ :[i32] })*
3834	/ 9285 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3835	/ 9290 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3836	/ 9295 / // GIR_Coverage, 2154,
3837	/ 9295 / GIR_Done,
3838	/ 9296 / // Label 444: @9296
3839	/ 9296 / GIM_Try_CheckFeatures, /On fail goto//Label 445/ GIMT_Encode4(`9314`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2156 //
3840	/ 9303 / // (bitconvert:{ :[v4f32] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v2f64:{ :[v2f64] }:$src, MSA128W:{ :[i32] })*
3841	/ 9303 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3842	/ 9308 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3843	/ 9313 / // GIR_Coverage, 2156,
3844	/ 9313 / GIR_Done,
3845	/ 9314 / // Label 445: @9314
3846	/ 9314 / GIM_Try_CheckFeatures, /On fail goto//Label 446/ GIMT_Encode4(`9383`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2191 //
3847	/* 9321 / // (bitconvert:{ :[v4i32] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v2i64:{ :[v2i64] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3848	/ 9321 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3849	/ 9324 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3850	/ 9328 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3851	/ 9333 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3852	/ 9337 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3853	/ 9342 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3854	/ 9345 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3855	/ 9349 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3856	/ 9354 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3857	/ 9357 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3858	/ 9367 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3859	/ 9369 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3860	/ 9372 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3861	/ 9374 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3862	/ 9377 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3863	/ 9382 / // GIR_Coverage, 2191,
3864	/ 9382 / GIR_EraseRootFromParent_Done,
3865	/ 9383 / // Label 446: @9383
3866	/ 9383 / GIM_Try_CheckFeatures, /On fail goto//Label 447/ GIMT_Encode4(`9452`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2192 //
3867	/* 9390 / // (bitconvert:{ :[v4f32] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v2i64:{ :[v2i64] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3868	/ 9390 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3869	/ 9393 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3870	/ 9397 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3871	/ 9402 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3872	/ 9406 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3873	/ 9411 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3874	/ 9414 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3875	/ 9418 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3876	/ 9423 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3877	/ 9426 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3878	/ 9436 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3879	/ 9438 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3880	/ 9441 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3881	/ 9443 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3882	/ 9446 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3883	/ 9451 / // GIR_Coverage, 2192,
3884	/ 9451 / GIR_EraseRootFromParent_Done,
3885	/ 9452 / // Label 447: @9452
3886	/ 9452 / GIM_Try_CheckFeatures, /On fail goto//Label 448/ GIMT_Encode4(`9521`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2196 //
3887	/* 9459 / // (bitconvert:{ :[v4i32] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v2f64:{ :[v2f64] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3888	/ 9459 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3889	/ 9462 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3890	/ 9466 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3891	/ 9471 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3892	/ 9475 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3893	/ 9480 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3894	/ 9483 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3895	/ 9487 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3896	/ 9492 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3897	/ 9495 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3898	/ 9505 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3899	/ 9507 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3900	/ 9510 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3901	/ 9512 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3902	/ 9515 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3903	/ 9520 / // GIR_Coverage, 2196,
3904	/ 9520 / GIR_EraseRootFromParent_Done,
3905	/ 9521 / // Label 448: @9521
3906	/ 9521 / GIM_Try_CheckFeatures, /On fail goto//Label 449/ GIMT_Encode4(`9590`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2197 //
3907	/* 9528 / // (bitconvert:{ :[v4f32] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v2f64:{ :[v2f64] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128W:{ :[i32] })
3908	/ 9528 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3909	/ 9531 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3910	/ 9535 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3911	/ 9540 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
3912	/ 9544 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3913	/ 9549 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3914	/ 9552 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3915	/ 9556 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3916	/ 9561 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3917	/ 9564 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3918	/ 9574 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3919	/ 9576 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3920	/ 9579 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3921	/ 9581 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3922	/ 9584 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3923	/ 9589 / // GIR_Coverage, 2197,
3924	/ 9589 / GIR_EraseRootFromParent_Done,
3925	/ 9590 / // Label 449: @9590
3926	/ 9590 / GIM_Reject,
3927	/ 9591 / // Label 441: @9591
3928	/ 9591 / GIM_Reject,
3929	/ 9592 / // Label 423: @9592
3930	/ 9592 / GIM_Reject,
3931	/ 9593 / // Label 348: @9593
3932	/ 9593 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 454/ GIMT_Encode4(`10626`),
3933	/ 9604 / /GILLT_v16s8//Label 450/ GIMT_Encode4(`9624`), GIMT_Encode4(`0`),
3934	/ 9612 / /GILLT_v8s16//Label 451/ GIMT_Encode4(`9889`),
3935	/ 9616 / /GILLT_v4s32//Label 452/ GIMT_Encode4(`10220`),
3936	/ 9620 / /GILLT_v2s64//Label 453/ GIMT_Encode4(`10579`),
3937	/ 9624 / // Label 450: @9624
3938	/ 9624 / GIM_Try, /On fail goto//Label 455/ GIMT_Encode4(`9888`),
3939	/ 9629 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
3940	/ 9633 / GIM_Try_CheckFeatures, /On fail goto//Label 456/ GIMT_Encode4(`9651`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2147 //
3941	/ 9640 / // (bitconvert:{ :[v2i64] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v16i8:{ :[v16i8] }:$src, MSA128D:{ :[i32] })*
3942	/ 9640 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3943	/ 9645 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
3944	/ 9650 / // GIR_Coverage, 2147,
3945	/ 9650 / GIR_Done,
3946	/ 9651 / // Label 456: @9651
3947	/ 9651 / GIM_Try_CheckFeatures, /On fail goto//Label 457/ GIMT_Encode4(`9669`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2157 //
3948	/ 9658 / // (bitconvert:{ :[v2f64] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v16i8:{ :[v16i8] }:$src, MSA128D:{ :[i32] })*
3949	/ 9658 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3950	/ 9663 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
3951	/ 9668 / // GIR_Coverage, 2157,
3952	/ 9668 / GIR_Done,
3953	/ 9669 / // Label 457: @9669
3954	/ 9669 / GIM_Try_CheckFeatures, /On fail goto//Label 458/ GIMT_Encode4(`9778`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2166 //
3955	/* 9676 / // (bitconvert:{ :[v2i64] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
3956	/ 9676 / GIR_MakeTempReg, /TempRegID/`3`, /TypeID/GILLT_v16s8,
3957	/ 9679 / GIR_BuildMI, /InsnID/`4`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3958	/ 9683 / GIR_AddTempRegister, /InsnID/`4`, /TempRegID/`3`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3959	/ 9688 / GIR_Copy, /NewInsnID/`4`, /OldInsnID/`0`, /OpIdx/`1`, // src
3960	/ 9692 / GIR_ConstrainOperandRC, /InsnID/`4`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3961	/ 9697 / GIR_MakeTempReg, /TempRegID/`2`, /TypeID/GILLT_v16s8,
3962	/ 9700 / GIR_BuildMI, /InsnID/`3`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3963	/ 9704 / GIR_AddTempRegister, /InsnID/`3`, /TempRegID/`2`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3964	/ 9709 / GIR_AddSimpleTempRegister, /InsnID/`3`, /TempRegID/`3`,
3965	/ 9712 / GIR_AddImm8, /InsnID/`3`, /Imm/`27`,
3966	/ 9715 / GIR_ConstrainSelectedInstOperands, /InsnID/`3`,
3967	/ 9717 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3968	/ 9720 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3969	/ 9724 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3970	/ 9729 / GIR_AddSimpleTempRegister, /InsnID/`2`, /TempRegID/`2`,
3971	/ 9732 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
3972	/ 9737 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
3973	/ 9740 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
3974	/ 9744 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3975	/ 9749 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
3976	/ 9752 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
3977	/ 9762 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
3978	/ 9764 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3979	/ 9767 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
3980	/ 9769 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
3981	/ 9772 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
3982	/ 9777 / // GIR_Coverage, 2166,
3983	/ 9777 / GIR_EraseRootFromParent_Done,
3984	/ 9778 / // Label 458: @9778
3985	/ 9778 / GIM_Try_CheckFeatures, /On fail goto//Label 459/ GIMT_Encode4(`9887`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2167 //
3986	/* 9785 / // (bitconvert:{ :[v2f64] } v16i8:{ :[v16i8] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_B:{ :[v16i8] } (COPY_TO_REGCLASS:{ :[v16i8] } v16i8:{ :[v16i8] }:$src, MSA128B:{ :[i32] }), 27:{ :[i32] }), MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
3987	/ 9785 / GIR_MakeTempReg, /TempRegID/`3`, /TypeID/GILLT_v16s8,
3988	/ 9788 / GIR_BuildMI, /InsnID/`4`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
3989	/ 9792 / GIR_AddTempRegister, /InsnID/`4`, /TempRegID/`3`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3990	/ 9797 / GIR_Copy, /NewInsnID/`4`, /OldInsnID/`0`, /OpIdx/`1`, // src
3991	/ 9801 / GIR_ConstrainOperandRC, /InsnID/`4`, /Op/`0`, GIMT_Encode2(Mips::MSA128BRegClassID),
3992	/ 9806 / GIR_MakeTempReg, /TempRegID/`2`, /TypeID/GILLT_v16s8,
3993	/ 9809 / GIR_BuildMI, /InsnID/`3`, /Opcode/GIMT_Encode2(Mips::SHF_B),
3994	/ 9813 / GIR_AddTempRegister, /InsnID/`3`, /TempRegID/`2`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3995	/ 9818 / GIR_AddSimpleTempRegister, /InsnID/`3`, /TempRegID/`3`,
3996	/ 9821 / GIR_AddImm8, /InsnID/`3`, /Imm/`27`,
3997	/ 9824 / GIR_ConstrainSelectedInstOperands, /InsnID/`3`,
3998	/ 9826 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
3999	/ 9829 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4000	/ 9833 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4001	/ 9838 / GIR_AddSimpleTempRegister, /InsnID/`2`, /TempRegID/`2`,
4002	/ 9841 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
4003	/ 9846 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
4004	/ 9849 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
4005	/ 9853 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4006	/ 9858 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4007	/ 9861 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
4008	/ 9871 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4009	/ 9873 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4010	/ 9876 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4011	/ 9878 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4012	/ 9881 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4013	/ 9886 / // GIR_Coverage, 2167,
4014	/ 9886 / GIR_EraseRootFromParent_Done,
4015	/ 9887 / // Label 459: @9887
4016	/ 9887 / GIM_Reject,
4017	/ 9888 / // Label 455: @9888
4018	/ 9888 / GIM_Reject,
4019	/ 9889 / // Label 451: @9889
4020	/ 9889 / GIM_Try, /On fail goto//Label 460/ GIMT_Encode4(`10219`),
4021	/ 9894 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
4022	/ 9898 / GIM_Try_CheckFeatures, /On fail goto//Label 461/ GIMT_Encode4(`9916`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2148 //
4023	/ 9905 / // (bitconvert:{ :[v2i64] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v8i16:{ :[v8i16] }:$src, MSA128D:{ :[i32] })*
4024	/ 9905 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4025	/ 9910 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4026	/ 9915 / // GIR_Coverage, 2148,
4027	/ 9915 / GIR_Done,
4028	/ 9916 / // Label 461: @9916
4029	/ 9916 / GIM_Try_CheckFeatures, /On fail goto//Label 462/ GIMT_Encode4(`9934`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2150 //
4030	/ 9923 / // (bitconvert:{ :[v2i64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v8f16:{ :[v8f16] }:$src, MSA128D:{ :[i32] })*
4031	/ 9923 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4032	/ 9928 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4033	/ 9933 / // GIR_Coverage, 2150,
4034	/ 9933 / GIR_Done,
4035	/ 9934 / // Label 462: @9934
4036	/ 9934 / GIM_Try_CheckFeatures, /On fail goto//Label 463/ GIMT_Encode4(`9952`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2158 //
4037	/ 9941 / // (bitconvert:{ :[v2f64] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v8i16:{ :[v8i16] }:$src, MSA128D:{ :[i32] })*
4038	/ 9941 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4039	/ 9946 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4040	/ 9951 / // GIR_Coverage, 2158,
4041	/ 9951 / GIR_Done,
4042	/ 9952 / // Label 463: @9952
4043	/ 9952 / GIM_Try_CheckFeatures, /On fail goto//Label 464/ GIMT_Encode4(`9970`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2160 //
4044	/ 9959 / // (bitconvert:{ :[v2f64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v8f16:{ :[v8f16] }:$src, MSA128D:{ :[i32] })*
4045	/ 9959 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4046	/ 9964 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4047	/ 9969 / // GIR_Coverage, 2160,
4048	/ 9969 / GIR_Done,
4049	/ 9970 / // Label 464: @9970
4050	/ 9970 / GIM_Try_CheckFeatures, /On fail goto//Label 465/ GIMT_Encode4(`10032`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2171 //
4051	/* 9977 / // (bitconvert:{ :[v2i64] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8i16:{ :[v8i16] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128D:{ :[i32] })
4052	/ 9977 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
4053	/ 9980 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4054	/ 9984 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4055	/ 9989 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4056	/ 9993 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
4057	/ 9998 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
4058	/ 10001 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
4059	/ 10005 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4060	/ 10010 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4061	/ 10013 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
4062	/ 10016 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4063	/ 10018 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4064	/ 10021 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4065	/ 10023 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4066	/ 10026 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4067	/ 10031 / // GIR_Coverage, 2171,
4068	/ 10031 / GIR_EraseRootFromParent_Done,
4069	/ 10032 / // Label 465: @10032
4070	/ 10032 / GIM_Try_CheckFeatures, /On fail goto//Label 466/ GIMT_Encode4(`10094`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2172 //
4071	/* 10039 / // (bitconvert:{ :[v2f64] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8i16:{ :[v8i16] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128D:{ :[i32] })
4072	/ 10039 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
4073	/ 10042 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4074	/ 10046 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4075	/ 10051 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4076	/ 10055 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
4077	/ 10060 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
4078	/ 10063 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
4079	/ 10067 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4080	/ 10072 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4081	/ 10075 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
4082	/ 10078 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4083	/ 10080 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4084	/ 10083 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4085	/ 10085 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4086	/ 10088 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4087	/ 10093 / // GIR_Coverage, 2172,
4088	/ 10093 / GIR_EraseRootFromParent_Done,
4089	/ 10094 / // Label 466: @10094
4090	/ 10094 / GIM_Try_CheckFeatures, /On fail goto//Label 467/ GIMT_Encode4(`10156`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2176 //
4091	/* 10101 / // (bitconvert:{ :[v2i64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:{ :[v8f16] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128D:{ :[i32] })
4092	/ 10101 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
4093	/ 10104 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4094	/ 10108 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4095	/ 10113 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4096	/ 10117 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
4097	/ 10122 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
4098	/ 10125 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
4099	/ 10129 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4100	/ 10134 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4101	/ 10137 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
4102	/ 10140 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4103	/ 10142 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4104	/ 10145 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4105	/ 10147 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4106	/ 10150 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4107	/ 10155 / // GIR_Coverage, 2176,
4108	/ 10155 / GIR_EraseRootFromParent_Done,
4109	/ 10156 / // Label 467: @10156
4110	/ 10156 / GIM_Try_CheckFeatures, /On fail goto//Label 468/ GIMT_Encode4(`10218`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2177 //
4111	/* 10163 / // (bitconvert:{ :[v2f64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_H:{ :[v8i16] } (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:{ :[v8f16] }:$src, MSA128H:{ :[i32] }), 27:{ :[i32] }), MSA128D:{ :[i32] })
4112	/ 10163 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v8s16,
4113	/ 10166 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4114	/ 10170 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4115	/ 10175 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4116	/ 10179 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128HRegClassID),
4117	/ 10184 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v8s16,
4118	/ 10187 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_H),
4119	/ 10191 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4120	/ 10196 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4121	/ 10199 / GIR_AddImm8, /InsnID/`1`, /Imm/`27`,
4122	/ 10202 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4123	/ 10204 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4124	/ 10207 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4125	/ 10209 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4126	/ 10212 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4127	/ 10217 / // GIR_Coverage, 2177,
4128	/ 10217 / GIR_EraseRootFromParent_Done,
4129	/ 10218 / // Label 468: @10218
4130	/ 10218 / GIM_Reject,
4131	/ 10219 / // Label 460: @10219
4132	/ 10219 / GIM_Reject,
4133	/ 10220 / // Label 452: @10220
4134	/ 10220 / GIM_Try, /On fail goto//Label 469/ GIMT_Encode4(`10578`),
4135	/ 10225 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
4136	/ 10229 / GIM_Try_CheckFeatures, /On fail goto//Label 470/ GIMT_Encode4(`10247`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2149 //
4137	/ 10236 / // (bitconvert:{ :[v2i64] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v4i32:{ :[v4i32] }:$src, MSA128D:{ :[i32] })*
4138	/ 10236 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4139	/ 10241 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4140	/ 10246 / // GIR_Coverage, 2149,
4141	/ 10246 / GIR_Done,
4142	/ 10247 / // Label 470: @10247
4143	/ 10247 / GIM_Try_CheckFeatures, /On fail goto//Label 471/ GIMT_Encode4(`10265`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2151 //
4144	/ 10254 / // (bitconvert:{ :[v2i64] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v4f32:{ :[v4f32] }:$src, MSA128D:{ :[i32] })*
4145	/ 10254 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4146	/ 10259 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4147	/ 10264 / // GIR_Coverage, 2151,
4148	/ 10264 / GIR_Done,
4149	/ 10265 / // Label 471: @10265
4150	/ 10265 / GIM_Try_CheckFeatures, /On fail goto//Label 472/ GIMT_Encode4(`10283`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2159 //
4151	/ 10272 / // (bitconvert:{ :[v2f64] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v4i32:{ :[v4i32] }:$src, MSA128D:{ :[i32] })*
4152	/ 10272 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4153	/ 10277 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4154	/ 10282 / // GIR_Coverage, 2159,
4155	/ 10282 / GIR_Done,
4156	/ 10283 / // Label 472: @10283
4157	/ 10283 / GIM_Try_CheckFeatures, /On fail goto//Label 473/ GIMT_Encode4(`10301`), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2161 //
4158	/ 10290 / // (bitconvert:{ :[v2f64] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v4f32:{ :[v4f32] }:$src, MSA128D:{ :[i32] })*
4159	/ 10290 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4160	/ 10295 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4161	/ 10300 / // GIR_Coverage, 2161,
4162	/ 10300 / GIR_Done,
4163	/ 10301 / // Label 473: @10301
4164	/ 10301 / GIM_Try_CheckFeatures, /On fail goto//Label 474/ GIMT_Encode4(`10370`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2181 //
4165	/* 10308 / // (bitconvert:{ :[v2i64] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v4i32:{ :[v4i32] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
4166	/ 10308 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
4167	/ 10311 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4168	/ 10315 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4169	/ 10320 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4170	/ 10324 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
4171	/ 10329 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
4172	/ 10332 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
4173	/ 10336 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4174	/ 10341 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4175	/ 10344 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
4176	/ 10354 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4177	/ 10356 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4178	/ 10359 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4179	/ 10361 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4180	/ 10364 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4181	/ 10369 / // GIR_Coverage, 2181,
4182	/ 10369 / GIR_EraseRootFromParent_Done,
4183	/ 10370 / // Label 474: @10370
4184	/ 10370 / GIM_Try_CheckFeatures, /On fail goto//Label 475/ GIMT_Encode4(`10439`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2182 //
4185	/* 10377 / // (bitconvert:{ :[v2f64] } v4i32:{ :[v4i32] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v4i32:{ :[v4i32] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
4186	/ 10377 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
4187	/ 10380 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4188	/ 10384 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4189	/ 10389 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4190	/ 10393 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
4191	/ 10398 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
4192	/ 10401 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
4193	/ 10405 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4194	/ 10410 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4195	/ 10413 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
4196	/ 10423 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4197	/ 10425 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4198	/ 10428 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4199	/ 10430 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4200	/ 10433 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4201	/ 10438 / // GIR_Coverage, 2182,
4202	/ 10438 / GIR_EraseRootFromParent_Done,
4203	/ 10439 / // Label 475: @10439
4204	/ 10439 / GIM_Try_CheckFeatures, /On fail goto//Label 476/ GIMT_Encode4(`10508`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2186 //
4205	/* 10446 / // (bitconvert:{ :[v2i64] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v4f32:{ :[v4f32] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
4206	/ 10446 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
4207	/ 10449 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4208	/ 10453 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4209	/ 10458 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4210	/ 10462 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
4211	/ 10467 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
4212	/ 10470 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
4213	/ 10474 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4214	/ 10479 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4215	/ 10482 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
4216	/ 10492 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4217	/ 10494 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4218	/ 10497 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4219	/ 10499 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4220	/ 10502 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4221	/ 10507 / // GIR_Coverage, 2186,
4222	/ 10507 / GIR_EraseRootFromParent_Done,
4223	/ 10508 / // Label 476: @10508
4224	/ 10508 / GIM_Try_CheckFeatures, /On fail goto//Label 477/ GIMT_Encode4(`10577`), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2187 //
4225	/* 10515 / // (bitconvert:{ :[v2f64] } v4f32:{ :[v4f32] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_W:{ :[v4i32] } (COPY_TO_REGCLASS:{ :[v4i32] } v4f32:{ :[v4f32] }:$src, MSA128W:{ :[i32] }), 177:{ :[i32] }), MSA128D:{ :[i32] })
4226	/ 10515 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_v4s32,
4227	/ 10518 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4228	/ 10522 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4229	/ 10527 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // src
4230	/ 10531 / GIR_ConstrainOperandRC, /InsnID/`2`, /Op/`0`, GIMT_Encode2(Mips::MSA128WRegClassID),
4231	/ 10536 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_v4s32,
4232	/ 10539 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SHF_W),
4233	/ 10543 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4234	/ 10548 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
4235	/ 10551 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`177`),
4236	/ 10561 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
4237	/ 10563 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4238	/ 10566 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
4239	/ 10568 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
4240	/ 10571 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4241	/ 10576 / // GIR_Coverage, 2187,
4242	/ 10576 / GIR_EraseRootFromParent_Done,
4243	/ 10577 / // Label 477: @10577
4244	/ 10577 / GIM_Reject,
4245	/ 10578 / // Label 469: @10578
4246	/ 10578 / GIM_Reject,
4247	/ 10579 / // Label 453: @10579
4248	/ 10579 / GIM_Try, /On fail goto//Label 478/ GIMT_Encode4(`10625`),
4249	/ 10584 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
4250	/ 10588 / GIM_Try_CheckFeatures, /On fail goto//Label 479/ GIMT_Encode4(`10606`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2127 //
4251	/ 10595 / // (bitconvert:{ :[v2i64] } v2f64:{ :[v2f64] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v2f64:{ :[v2f64] }:$src, MSA128D:{ :[i32] })*
4252	/ 10595 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4253	/ 10600 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4254	/ 10605 / // GIR_Coverage, 2127,
4255	/ 10605 / GIR_Done,
4256	/ 10606 / // Label 479: @10606
4257	/ 10606 / GIM_Try_CheckFeatures, /On fail goto//Label 480/ GIMT_Encode4(`10624`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2130 //
4258	/ 10613 / // (bitconvert:{ :[v2f64] } v2i64:{ :[v2i64] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v2i64:{ :[v2i64] }:$src, MSA128D:{ :[i32] })*
4259	/ 10613 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
4260	/ 10618 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::MSA128DRegClassID),
4261	/ 10623 / // GIR_Coverage, 2130,
4262	/ 10623 / GIR_Done,
4263	/ 10624 / // Label 480: @10624
4264	/ 10624 / GIM_Reject,
4265	/ 10625 / // Label 478: @10625
4266	/ 10625 / GIM_Reject,
4267	/ 10626 / // Label 454: @10626
4268	/ 10626 / GIM_Reject,
4269	/ 10627 / // Label 349: @10627
4270	/ 10627 / GIM_Reject,
4271	/ 10628 / // Label 13: @10628
4272	/ 10628 / GIM_Try_CheckFeatures, /On fail goto//Label 481/ GIMT_Encode4(`10691`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2116 //
4273	/ 10635 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
4274	/ 10638 / GIM_CheckAtomicOrdering, /MI/`0`, /Order/(uint8_t)AtomicOrdering::NotAtomic,
4275	/ 10641 / GIM_CheckMemorySizeEqualToLLT, /MI/`0`, /MMO/`0`, /OpIdx/`0`,
4276	/ 10645 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4277	/ 10649 / // MIs[0] Operand 1
4278	/ 10649 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`32`,
4279	/ 10653 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
4280	/ 10657 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ADD),
4281	/ 10661 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
4282	/ 10665 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
4283	/ 10669 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
4284	/* 10671 / // (ld:{ :[i32] } (add:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index)
4285	/ 10671 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LWX),
4286	/ 10674 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
4287	/ 10676 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // base
4288	/ 10680 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // index
4289	/ 10684 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
4290	/ 10689 / GIR_RootConstrainSelectedInstOperands,
4291	/ 10690 / // GIR_Coverage, 2116,
4292	/ 10690 / GIR_EraseRootFromParent_Done,
4293	/ 10691 / // Label 481: @10691
4294	/ 10691 / GIM_Reject,
4295	/ 10692 / // Label 14: @10692
4296	/ 10692 / GIM_Try_CheckFeatures, /On fail goto//Label 482/ GIMT_Encode4(`10758`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2115 //
4297	/ 10699 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
4298	/ 10702 / GIM_CheckAtomicOrdering, /MI/`0`, /Order/(uint8_t)AtomicOrdering::NotAtomic,
4299	/ 10705 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4300	/ 10712 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4301	/ 10716 / // MIs[0] Operand 1
4302	/ 10716 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`32`,
4303	/ 10720 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
4304	/ 10724 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ADD),
4305	/ 10728 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
4306	/ 10732 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
4307	/ 10736 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
4308	/* 10738 / // (ld:{ :[i32] } (add:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index)
4309	/ 10738 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LHX),
4310	/ 10741 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
4311	/ 10743 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // base
4312	/ 10747 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // index
4313	/ 10751 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
4314	/ 10756 / GIR_RootConstrainSelectedInstOperands,
4315	/ 10757 / // GIR_Coverage, 2115,
4316	/ 10757 / GIR_EraseRootFromParent_Done,
4317	/ 10758 / // Label 482: @10758
4318	/ 10758 / GIM_Reject,
4319	/ 10759 / // Label 15: @10759
4320	/ 10759 / GIM_Try_CheckFeatures, /On fail goto//Label 483/ GIMT_Encode4(`10825`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2114 //
4321	/ 10766 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
4322	/ 10769 / GIM_CheckAtomicOrdering, /MI/`0`, /Order/(uint8_t)AtomicOrdering::NotAtomic,
4323	/ 10772 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4324	/ 10779 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4325	/ 10783 / // MIs[0] Operand 1
4326	/ 10783 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`32`,
4327	/ 10787 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
4328	/ 10791 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ADD),
4329	/ 10795 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
4330	/ 10799 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
4331	/ 10803 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
4332	/* 10805 / // (ld:{ :[i32] } (add:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ :[i32] } i32:{ :[i32] }:$base, i32:{ :[i32] }:$index)
4333	/ 10805 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LBUX),
4334	/ 10808 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
4335	/ 10810 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // base
4336	/ 10814 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // index
4337	/ 10818 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
4338	/ 10823 / GIR_RootConstrainSelectedInstOperands,
4339	/ 10824 / // GIR_Coverage, 2114,
4340	/ 10824 / GIR_EraseRootFromParent_Done,
4341	/ 10825 / // Label 483: @10825
4342	/ 10825 / GIM_Reject,
4343	/ 10826 / // Label 16: @10826
4344	/ 10826 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 486/ GIMT_Encode4(`11013`),
4345	/ 10837 / /GILLT_s32//Label 484/ GIMT_Encode4(`10845`),
4346	/ 10841 / /GILLT_s64//Label 485/ GIMT_Encode4(`10969`),
4347	/ 10845 / // Label 484: @10845
4348	/ 10845 / GIM_Try, /On fail goto//Label 487/ GIMT_Encode4(`10968`),
4349	/ 10850 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4350	/ 10853 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
4351	/ 10856 / GIM_Try_CheckFeatures, /On fail goto//Label 488/ GIMT_Encode4(`10893`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 25 //
4352	/ 10863 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4353	/ 10870 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4354	/ 10874 / // MIs[0] ptr
4355	/ 10874 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4356	/ 10878 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4357	/ 10882 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4358	/* 10886 / // (atomic_cmp_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ :[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4359	/ 10886 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4360	/ 10891 / GIR_RootConstrainSelectedInstOperands,
4361	/ 10892 / // GIR_Coverage, 25,
4362	/ 10892 / GIR_Done,
4363	/ 10893 / // Label 488: @10893
4364	/ 10893 / GIM_Try_CheckFeatures, /On fail goto//Label 489/ GIMT_Encode4(`10930`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 26 //
4365	/ 10900 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4366	/ 10907 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4367	/ 10911 / // MIs[0] ptr
4368	/ 10911 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4369	/ 10915 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4370	/ 10919 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4371	/* 10923 / // (atomic_cmp_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ :[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4372	/ 10923 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4373	/ 10928 / GIR_RootConstrainSelectedInstOperands,
4374	/ 10929 / // GIR_Coverage, 26,
4375	/ 10929 / GIR_Done,
4376	/ 10930 / // Label 489: @10930
4377	/ 10930 / GIM_Try_CheckFeatures, /On fail goto//Label 490/ GIMT_Encode4(`10967`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 27 //
4378	/ 10937 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4379	/ 10944 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4380	/ 10948 / // MIs[0] ptr
4381	/ 10948 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4382	/ 10952 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4383	/ 10956 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4384	/* 10960 / // (atomic_cmp_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ :[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4385	/ 10960 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4386	/ 10965 / GIR_RootConstrainSelectedInstOperands,
4387	/ 10966 / // GIR_Coverage, 27,
4388	/ 10966 / GIR_Done,
4389	/ 10967 / // Label 490: @10967
4390	/ 10967 / GIM_Reject,
4391	/ 10968 / // Label 487: @10968
4392	/ 10968 / GIM_Reject,
4393	/ 10969 / // Label 485: @10969
4394	/ 10969 / GIM_Try_CheckFeatures, /On fail goto//Label 491/ GIMT_Encode4(`11012`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 218 //
4395	/ 10976 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4396	/ 10979 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s64,
4397	/ 10982 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4398	/ 10989 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4399	/ 10993 / // MIs[0] ptr
4400	/ 10993 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4401	/ 10997 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4402	/ 11001 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4403	/* 11005 / // (atomic_cmp_swap:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$cmp, GPR64:{ :[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4404	/ 11005 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4405	/ 11010 / GIR_RootConstrainSelectedInstOperands,
4406	/ 11011 / // GIR_Coverage, 218,
4407	/ 11011 / GIR_Done,
4408	/ 11012 / // Label 491: @11012
4409	/ 11012 / GIM_Reject,
4410	/ 11013 / // Label 486: @11013
4411	/ 11013 / GIM_Reject,
4412	/ 11014 / // Label 17: @11014
4413	/ 11014 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 494/ GIMT_Encode4(`11179`),
4414	/ 11025 / /GILLT_s32//Label 492/ GIMT_Encode4(`11033`),
4415	/ 11029 / /GILLT_s64//Label 493/ GIMT_Encode4(`11142`),
4416	/ 11033 / // Label 492: @11033
4417	/ 11033 / GIM_Try, /On fail goto//Label 495/ GIMT_Encode4(`11141`),
4418	/ 11038 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4419	/ 11041 / GIM_Try_CheckFeatures, /On fail goto//Label 496/ GIMT_Encode4(`11074`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 22 //
4420	/ 11048 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4421	/ 11055 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4422	/ 11059 / // MIs[0] ptr
4423	/ 11059 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4424	/ 11063 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4425	/* 11067 / // (atomic_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4426	/ 11067 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4427	/ 11072 / GIR_RootConstrainSelectedInstOperands,
4428	/ 11073 / // GIR_Coverage, 22,
4429	/ 11073 / GIR_Done,
4430	/ 11074 / // Label 496: @11074
4431	/ 11074 / GIM_Try_CheckFeatures, /On fail goto//Label 497/ GIMT_Encode4(`11107`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 23 //
4432	/ 11081 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4433	/ 11088 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4434	/ 11092 / // MIs[0] ptr
4435	/ 11092 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4436	/ 11096 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4437	/* 11100 / // (atomic_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4438	/ 11100 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4439	/ 11105 / GIR_RootConstrainSelectedInstOperands,
4440	/ 11106 / // GIR_Coverage, 23,
4441	/ 11106 / GIR_Done,
4442	/ 11107 / // Label 497: @11107
4443	/ 11107 / GIM_Try_CheckFeatures, /On fail goto//Label 498/ GIMT_Encode4(`11140`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 24 //
4444	/ 11114 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4445	/ 11121 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4446	/ 11125 / // MIs[0] ptr
4447	/ 11125 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4448	/ 11129 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4449	/* 11133 / // (atomic_swap:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4450	/ 11133 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4451	/ 11138 / GIR_RootConstrainSelectedInstOperands,
4452	/ 11139 / // GIR_Coverage, 24,
4453	/ 11139 / GIR_Done,
4454	/ 11140 / // Label 498: @11140
4455	/ 11140 / GIM_Reject,
4456	/ 11141 / // Label 495: @11141
4457	/ 11141 / GIM_Reject,
4458	/ 11142 / // Label 493: @11142
4459	/ 11142 / GIM_Try_CheckFeatures, /On fail goto//Label 499/ GIMT_Encode4(`11178`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 217 //
4460	/ 11149 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4461	/ 11152 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4462	/ 11159 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4463	/ 11163 / // MIs[0] ptr
4464	/ 11163 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4465	/ 11167 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4466	/* 11171 / // (atomic_swap:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4467	/ 11171 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4468	/ 11176 / GIR_RootConstrainSelectedInstOperands,
4469	/ 11177 / // GIR_Coverage, 217,
4470	/ 11177 / GIR_Done,
4471	/ 11178 / // Label 499: @11178
4472	/ 11178 / GIM_Reject,
4473	/ 11179 / // Label 494: @11179
4474	/ 11179 / GIM_Reject,
4475	/ 11180 / // Label 18: @11180
4476	/ 11180 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 502/ GIMT_Encode4(`11345`),
4477	/ 11191 / /GILLT_s32//Label 500/ GIMT_Encode4(`11199`),
4478	/ 11195 / /GILLT_s64//Label 501/ GIMT_Encode4(`11308`),
4479	/ 11199 / // Label 500: @11199
4480	/ 11199 / GIM_Try, /On fail goto//Label 503/ GIMT_Encode4(`11307`),
4481	/ 11204 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4482	/ 11207 / GIM_Try_CheckFeatures, /On fail goto//Label 504/ GIMT_Encode4(`11240`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 4 //
4483	/ 11214 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4484	/ 11221 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4485	/ 11225 / // MIs[0] ptr
4486	/ 11225 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4487	/ 11229 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4488	/* 11233 / // (atomic_load_add:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4489	/ 11233 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4490	/ 11238 / GIR_RootConstrainSelectedInstOperands,
4491	/ 11239 / // GIR_Coverage, 4,
4492	/ 11239 / GIR_Done,
4493	/ 11240 / // Label 504: @11240
4494	/ 11240 / GIM_Try_CheckFeatures, /On fail goto//Label 505/ GIMT_Encode4(`11273`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 5 //
4495	/ 11247 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4496	/ 11254 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4497	/ 11258 / // MIs[0] ptr
4498	/ 11258 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4499	/ 11262 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4500	/* 11266 / // (atomic_load_add:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4501	/ 11266 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4502	/ 11271 / GIR_RootConstrainSelectedInstOperands,
4503	/ 11272 / // GIR_Coverage, 5,
4504	/ 11272 / GIR_Done,
4505	/ 11273 / // Label 505: @11273
4506	/ 11273 / GIM_Try_CheckFeatures, /On fail goto//Label 506/ GIMT_Encode4(`11306`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 6 //
4507	/ 11280 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4508	/ 11287 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4509	/ 11291 / // MIs[0] ptr
4510	/ 11291 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4511	/ 11295 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4512	/* 11299 / // (atomic_load_add:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4513	/ 11299 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4514	/ 11304 / GIR_RootConstrainSelectedInstOperands,
4515	/ 11305 / // GIR_Coverage, 6,
4516	/ 11305 / GIR_Done,
4517	/ 11306 / // Label 506: @11306
4518	/ 11306 / GIM_Reject,
4519	/ 11307 / // Label 503: @11307
4520	/ 11307 / GIM_Reject,
4521	/ 11308 / // Label 501: @11308
4522	/ 11308 / GIM_Try_CheckFeatures, /On fail goto//Label 507/ GIMT_Encode4(`11344`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 211 //
4523	/ 11315 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4524	/ 11318 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4525	/ 11325 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4526	/ 11329 / // MIs[0] ptr
4527	/ 11329 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4528	/ 11333 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4529	/* 11337 / // (atomic_load_add:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4530	/ 11337 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4531	/ 11342 / GIR_RootConstrainSelectedInstOperands,
4532	/ 11343 / // GIR_Coverage, 211,
4533	/ 11343 / GIR_Done,
4534	/ 11344 / // Label 507: @11344
4535	/ 11344 / GIM_Reject,
4536	/ 11345 / // Label 502: @11345
4537	/ 11345 / GIM_Reject,
4538	/ 11346 / // Label 19: @11346
4539	/ 11346 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 510/ GIMT_Encode4(`11511`),
4540	/ 11357 / /GILLT_s32//Label 508/ GIMT_Encode4(`11365`),
4541	/ 11361 / /GILLT_s64//Label 509/ GIMT_Encode4(`11474`),
4542	/ 11365 / // Label 508: @11365
4543	/ 11365 / GIM_Try, /On fail goto//Label 511/ GIMT_Encode4(`11473`),
4544	/ 11370 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4545	/ 11373 / GIM_Try_CheckFeatures, /On fail goto//Label 512/ GIMT_Encode4(`11406`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 7 //
4546	/ 11380 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4547	/ 11387 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4548	/ 11391 / // MIs[0] ptr
4549	/ 11391 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4550	/ 11395 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4551	/* 11399 / // (atomic_load_sub:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4552	/ 11399 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4553	/ 11404 / GIR_RootConstrainSelectedInstOperands,
4554	/ 11405 / // GIR_Coverage, 7,
4555	/ 11405 / GIR_Done,
4556	/ 11406 / // Label 512: @11406
4557	/ 11406 / GIM_Try_CheckFeatures, /On fail goto//Label 513/ GIMT_Encode4(`11439`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 8 //
4558	/ 11413 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4559	/ 11420 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4560	/ 11424 / // MIs[0] ptr
4561	/ 11424 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4562	/ 11428 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4563	/* 11432 / // (atomic_load_sub:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4564	/ 11432 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4565	/ 11437 / GIR_RootConstrainSelectedInstOperands,
4566	/ 11438 / // GIR_Coverage, 8,
4567	/ 11438 / GIR_Done,
4568	/ 11439 / // Label 513: @11439
4569	/ 11439 / GIM_Try_CheckFeatures, /On fail goto//Label 514/ GIMT_Encode4(`11472`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 9 //
4570	/ 11446 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4571	/ 11453 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4572	/ 11457 / // MIs[0] ptr
4573	/ 11457 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4574	/ 11461 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4575	/* 11465 / // (atomic_load_sub:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4576	/ 11465 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4577	/ 11470 / GIR_RootConstrainSelectedInstOperands,
4578	/ 11471 / // GIR_Coverage, 9,
4579	/ 11471 / GIR_Done,
4580	/ 11472 / // Label 514: @11472
4581	/ 11472 / GIM_Reject,
4582	/ 11473 / // Label 511: @11473
4583	/ 11473 / GIM_Reject,
4584	/ 11474 / // Label 509: @11474
4585	/ 11474 / GIM_Try_CheckFeatures, /On fail goto//Label 515/ GIMT_Encode4(`11510`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 212 //
4586	/ 11481 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4587	/ 11484 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4588	/ 11491 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4589	/ 11495 / // MIs[0] ptr
4590	/ 11495 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4591	/ 11499 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4592	/* 11503 / // (atomic_load_sub:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4593	/ 11503 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4594	/ 11508 / GIR_RootConstrainSelectedInstOperands,
4595	/ 11509 / // GIR_Coverage, 212,
4596	/ 11509 / GIR_Done,
4597	/ 11510 / // Label 515: @11510
4598	/ 11510 / GIM_Reject,
4599	/ 11511 / // Label 510: @11511
4600	/ 11511 / GIM_Reject,
4601	/ 11512 / // Label 20: @11512
4602	/ 11512 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 518/ GIMT_Encode4(`11677`),
4603	/ 11523 / /GILLT_s32//Label 516/ GIMT_Encode4(`11531`),
4604	/ 11527 / /GILLT_s64//Label 517/ GIMT_Encode4(`11640`),
4605	/ 11531 / // Label 516: @11531
4606	/ 11531 / GIM_Try, /On fail goto//Label 519/ GIMT_Encode4(`11639`),
4607	/ 11536 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4608	/ 11539 / GIM_Try_CheckFeatures, /On fail goto//Label 520/ GIMT_Encode4(`11572`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 10 //
4609	/ 11546 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4610	/ 11553 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4611	/ 11557 / // MIs[0] ptr
4612	/ 11557 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4613	/ 11561 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4614	/* 11565 / // (atomic_load_and:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4615	/ 11565 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4616	/ 11570 / GIR_RootConstrainSelectedInstOperands,
4617	/ 11571 / // GIR_Coverage, 10,
4618	/ 11571 / GIR_Done,
4619	/ 11572 / // Label 520: @11572
4620	/ 11572 / GIM_Try_CheckFeatures, /On fail goto//Label 521/ GIMT_Encode4(`11605`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 11 //
4621	/ 11579 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4622	/ 11586 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4623	/ 11590 / // MIs[0] ptr
4624	/ 11590 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4625	/ 11594 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4626	/* 11598 / // (atomic_load_and:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4627	/ 11598 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4628	/ 11603 / GIR_RootConstrainSelectedInstOperands,
4629	/ 11604 / // GIR_Coverage, 11,
4630	/ 11604 / GIR_Done,
4631	/ 11605 / // Label 521: @11605
4632	/ 11605 / GIM_Try_CheckFeatures, /On fail goto//Label 522/ GIMT_Encode4(`11638`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 12 //
4633	/ 11612 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4634	/ 11619 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4635	/ 11623 / // MIs[0] ptr
4636	/ 11623 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4637	/ 11627 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4638	/* 11631 / // (atomic_load_and:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4639	/ 11631 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4640	/ 11636 / GIR_RootConstrainSelectedInstOperands,
4641	/ 11637 / // GIR_Coverage, 12,
4642	/ 11637 / GIR_Done,
4643	/ 11638 / // Label 522: @11638
4644	/ 11638 / GIM_Reject,
4645	/ 11639 / // Label 519: @11639
4646	/ 11639 / GIM_Reject,
4647	/ 11640 / // Label 517: @11640
4648	/ 11640 / GIM_Try_CheckFeatures, /On fail goto//Label 523/ GIMT_Encode4(`11676`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 213 //
4649	/ 11647 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4650	/ 11650 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4651	/ 11657 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4652	/ 11661 / // MIs[0] ptr
4653	/ 11661 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4654	/ 11665 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4655	/* 11669 / // (atomic_load_and:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4656	/ 11669 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4657	/ 11674 / GIR_RootConstrainSelectedInstOperands,
4658	/ 11675 / // GIR_Coverage, 213,
4659	/ 11675 / GIR_Done,
4660	/ 11676 / // Label 523: @11676
4661	/ 11676 / GIM_Reject,
4662	/ 11677 / // Label 518: @11677
4663	/ 11677 / GIM_Reject,
4664	/ 11678 / // Label 21: @11678
4665	/ 11678 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 526/ GIMT_Encode4(`11843`),
4666	/ 11689 / /GILLT_s32//Label 524/ GIMT_Encode4(`11697`),
4667	/ 11693 / /GILLT_s64//Label 525/ GIMT_Encode4(`11806`),
4668	/ 11697 / // Label 524: @11697
4669	/ 11697 / GIM_Try, /On fail goto//Label 527/ GIMT_Encode4(`11805`),
4670	/ 11702 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4671	/ 11705 / GIM_Try_CheckFeatures, /On fail goto//Label 528/ GIMT_Encode4(`11738`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 19 //
4672	/ 11712 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4673	/ 11719 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4674	/ 11723 / // MIs[0] ptr
4675	/ 11723 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4676	/ 11727 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4677	/* 11731 / // (atomic_load_nand:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4678	/ 11731 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4679	/ 11736 / GIR_RootConstrainSelectedInstOperands,
4680	/ 11737 / // GIR_Coverage, 19,
4681	/ 11737 / GIR_Done,
4682	/ 11738 / // Label 528: @11738
4683	/ 11738 / GIM_Try_CheckFeatures, /On fail goto//Label 529/ GIMT_Encode4(`11771`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 20 //
4684	/ 11745 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4685	/ 11752 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4686	/ 11756 / // MIs[0] ptr
4687	/ 11756 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4688	/ 11760 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4689	/* 11764 / // (atomic_load_nand:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4690	/ 11764 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4691	/ 11769 / GIR_RootConstrainSelectedInstOperands,
4692	/ 11770 / // GIR_Coverage, 20,
4693	/ 11770 / GIR_Done,
4694	/ 11771 / // Label 529: @11771
4695	/ 11771 / GIM_Try_CheckFeatures, /On fail goto//Label 530/ GIMT_Encode4(`11804`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 21 //
4696	/ 11778 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4697	/ 11785 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4698	/ 11789 / // MIs[0] ptr
4699	/ 11789 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4700	/ 11793 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4701	/* 11797 / // (atomic_load_nand:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4702	/ 11797 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4703	/ 11802 / GIR_RootConstrainSelectedInstOperands,
4704	/ 11803 / // GIR_Coverage, 21,
4705	/ 11803 / GIR_Done,
4706	/ 11804 / // Label 530: @11804
4707	/ 11804 / GIM_Reject,
4708	/ 11805 / // Label 527: @11805
4709	/ 11805 / GIM_Reject,
4710	/ 11806 / // Label 525: @11806
4711	/ 11806 / GIM_Try_CheckFeatures, /On fail goto//Label 531/ GIMT_Encode4(`11842`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 216 //
4712	/ 11813 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4713	/ 11816 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4714	/ 11823 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4715	/ 11827 / // MIs[0] ptr
4716	/ 11827 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4717	/ 11831 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4718	/* 11835 / // (atomic_load_nand:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4719	/ 11835 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4720	/ 11840 / GIR_RootConstrainSelectedInstOperands,
4721	/ 11841 / // GIR_Coverage, 216,
4722	/ 11841 / GIR_Done,
4723	/ 11842 / // Label 531: @11842
4724	/ 11842 / GIM_Reject,
4725	/ 11843 / // Label 526: @11843
4726	/ 11843 / GIM_Reject,
4727	/ 11844 / // Label 22: @11844
4728	/ 11844 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 534/ GIMT_Encode4(`12009`),
4729	/ 11855 / /GILLT_s32//Label 532/ GIMT_Encode4(`11863`),
4730	/ 11859 / /GILLT_s64//Label 533/ GIMT_Encode4(`11972`),
4731	/ 11863 / // Label 532: @11863
4732	/ 11863 / GIM_Try, /On fail goto//Label 535/ GIMT_Encode4(`11971`),
4733	/ 11868 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4734	/ 11871 / GIM_Try_CheckFeatures, /On fail goto//Label 536/ GIMT_Encode4(`11904`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 13 //
4735	/ 11878 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4736	/ 11885 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4737	/ 11889 / // MIs[0] ptr
4738	/ 11889 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4739	/ 11893 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4740	/* 11897 / // (atomic_load_or:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4741	/ 11897 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
4742	/ 11902 / GIR_RootConstrainSelectedInstOperands,
4743	/ 11903 / // GIR_Coverage, 13,
4744	/ 11903 / GIR_Done,
4745	/ 11904 / // Label 536: @11904
4746	/ 11904 / GIM_Try_CheckFeatures, /On fail goto//Label 537/ GIMT_Encode4(`11937`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 14 //
4747	/ 11911 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4748	/ 11918 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4749	/ 11922 / // MIs[0] ptr
4750	/ 11922 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4751	/ 11926 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4752	/* 11930 / // (atomic_load_or:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4753	/ 11930 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
4754	/ 11935 / GIR_RootConstrainSelectedInstOperands,
4755	/ 11936 / // GIR_Coverage, 14,
4756	/ 11936 / GIR_Done,
4757	/ 11937 / // Label 537: @11937
4758	/ 11937 / GIM_Try_CheckFeatures, /On fail goto//Label 538/ GIMT_Encode4(`11970`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 15 //
4759	/ 11944 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4760	/ 11951 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4761	/ 11955 / // MIs[0] ptr
4762	/ 11955 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4763	/ 11959 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4764	/* 11963 / // (atomic_load_or:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4765	/ 11963 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
4766	/ 11968 / GIR_RootConstrainSelectedInstOperands,
4767	/ 11969 / // GIR_Coverage, 15,
4768	/ 11969 / GIR_Done,
4769	/ 11970 / // Label 538: @11970
4770	/ 11970 / GIM_Reject,
4771	/ 11971 / // Label 535: @11971
4772	/ 11971 / GIM_Reject,
4773	/ 11972 / // Label 533: @11972
4774	/ 11972 / GIM_Try_CheckFeatures, /On fail goto//Label 539/ GIMT_Encode4(`12008`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 214 //
4775	/ 11979 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4776	/ 11982 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4777	/ 11989 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4778	/ 11993 / // MIs[0] ptr
4779	/ 11993 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4780	/ 11997 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4781	/* 12001 / // (atomic_load_or:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4782	/ 12001 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
4783	/ 12006 / GIR_RootConstrainSelectedInstOperands,
4784	/ 12007 / // GIR_Coverage, 214,
4785	/ 12007 / GIR_Done,
4786	/ 12008 / // Label 539: @12008
4787	/ 12008 / GIM_Reject,
4788	/ 12009 / // Label 534: @12009
4789	/ 12009 / GIM_Reject,
4790	/ 12010 / // Label 23: @12010
4791	/ 12010 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 542/ GIMT_Encode4(`12175`),
4792	/ 12021 / /GILLT_s32//Label 540/ GIMT_Encode4(`12029`),
4793	/ 12025 / /GILLT_s64//Label 541/ GIMT_Encode4(`12138`),
4794	/ 12029 / // Label 540: @12029
4795	/ 12029 / GIM_Try, /On fail goto//Label 543/ GIMT_Encode4(`12137`),
4796	/ 12034 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4797	/ 12037 / GIM_Try_CheckFeatures, /On fail goto//Label 544/ GIMT_Encode4(`12070`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 16 //
4798	/ 12044 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4799	/ 12051 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4800	/ 12055 / // MIs[0] ptr
4801	/ 12055 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4802	/ 12059 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4803	/* 12063 / // (atomic_load_xor:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4804	/ 12063 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
4805	/ 12068 / GIR_RootConstrainSelectedInstOperands,
4806	/ 12069 / // GIR_Coverage, 16,
4807	/ 12069 / GIR_Done,
4808	/ 12070 / // Label 544: @12070
4809	/ 12070 / GIM_Try_CheckFeatures, /On fail goto//Label 545/ GIMT_Encode4(`12103`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 17 //
4810	/ 12077 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4811	/ 12084 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4812	/ 12088 / // MIs[0] ptr
4813	/ 12088 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4814	/ 12092 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4815	/* 12096 / // (atomic_load_xor:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4816	/ 12096 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
4817	/ 12101 / GIR_RootConstrainSelectedInstOperands,
4818	/ 12102 / // GIR_Coverage, 17,
4819	/ 12102 / GIR_Done,
4820	/ 12103 / // Label 545: @12103
4821	/ 12103 / GIM_Try_CheckFeatures, /On fail goto//Label 546/ GIMT_Encode4(`12136`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 18 //
4822	/ 12110 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4823	/ 12117 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4824	/ 12121 / // MIs[0] ptr
4825	/ 12121 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4826	/ 12125 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4827	/* 12129 / // (atomic_load_xor:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4828	/ 12129 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
4829	/ 12134 / GIR_RootConstrainSelectedInstOperands,
4830	/ 12135 / // GIR_Coverage, 18,
4831	/ 12135 / GIR_Done,
4832	/ 12136 / // Label 546: @12136
4833	/ 12136 / GIM_Reject,
4834	/ 12137 / // Label 543: @12137
4835	/ 12137 / GIM_Reject,
4836	/ 12138 / // Label 541: @12138
4837	/ 12138 / GIM_Try_CheckFeatures, /On fail goto//Label 547/ GIMT_Encode4(`12174`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 215 //
4838	/ 12145 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4839	/ 12148 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4840	/ 12155 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4841	/ 12159 / // MIs[0] ptr
4842	/ 12159 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4843	/ 12163 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4844	/* 12167 / // (atomic_load_xor:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4845	/ 12167 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
4846	/ 12172 / GIR_RootConstrainSelectedInstOperands,
4847	/ 12173 / // GIR_Coverage, 215,
4848	/ 12173 / GIR_Done,
4849	/ 12174 / // Label 547: @12174
4850	/ 12174 / GIM_Reject,
4851	/ 12175 / // Label 542: @12175
4852	/ 12175 / GIM_Reject,
4853	/ 12176 / // Label 24: @12176
4854	/ 12176 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 550/ GIMT_Encode4(`12341`),
4855	/ 12187 / /GILLT_s32//Label 548/ GIMT_Encode4(`12195`),
4856	/ 12191 / /GILLT_s64//Label 549/ GIMT_Encode4(`12304`),
4857	/ 12195 / // Label 548: @12195
4858	/ 12195 / GIM_Try, /On fail goto//Label 551/ GIMT_Encode4(`12303`),
4859	/ 12200 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4860	/ 12203 / GIM_Try_CheckFeatures, /On fail goto//Label 552/ GIMT_Encode4(`12236`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 31 //
4861	/ 12210 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4862	/ 12217 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4863	/ 12221 / // MIs[0] ptr
4864	/ 12221 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4865	/ 12225 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4866	/* 12229 / // (atomic_load_max:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4867	/ 12229 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
4868	/ 12234 / GIR_RootConstrainSelectedInstOperands,
4869	/ 12235 / // GIR_Coverage, 31,
4870	/ 12235 / GIR_Done,
4871	/ 12236 / // Label 552: @12236
4872	/ 12236 / GIM_Try_CheckFeatures, /On fail goto//Label 553/ GIMT_Encode4(`12269`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 32 //
4873	/ 12243 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4874	/ 12250 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4875	/ 12254 / // MIs[0] ptr
4876	/ 12254 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4877	/ 12258 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4878	/* 12262 / // (atomic_load_max:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4879	/ 12262 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
4880	/ 12267 / GIR_RootConstrainSelectedInstOperands,
4881	/ 12268 / // GIR_Coverage, 32,
4882	/ 12268 / GIR_Done,
4883	/ 12269 / // Label 553: @12269
4884	/ 12269 / GIM_Try_CheckFeatures, /On fail goto//Label 554/ GIMT_Encode4(`12302`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 33 //
4885	/ 12276 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4886	/ 12283 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4887	/ 12287 / // MIs[0] ptr
4888	/ 12287 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4889	/ 12291 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4890	/* 12295 / // (atomic_load_max:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4891	/ 12295 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
4892	/ 12300 / GIR_RootConstrainSelectedInstOperands,
4893	/ 12301 / // GIR_Coverage, 33,
4894	/ 12301 / GIR_Done,
4895	/ 12302 / // Label 554: @12302
4896	/ 12302 / GIM_Reject,
4897	/ 12303 / // Label 551: @12303
4898	/ 12303 / GIM_Reject,
4899	/ 12304 / // Label 549: @12304
4900	/ 12304 / GIM_Try_CheckFeatures, /On fail goto//Label 555/ GIMT_Encode4(`12340`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 220 //
4901	/ 12311 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4902	/ 12314 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4903	/ 12321 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4904	/ 12325 / // MIs[0] ptr
4905	/ 12325 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4906	/ 12329 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4907	/* 12333 / // (atomic_load_max:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4908	/ 12333 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
4909	/ 12338 / GIR_RootConstrainSelectedInstOperands,
4910	/ 12339 / // GIR_Coverage, 220,
4911	/ 12339 / GIR_Done,
4912	/ 12340 / // Label 555: @12340
4913	/ 12340 / GIM_Reject,
4914	/ 12341 / // Label 550: @12341
4915	/ 12341 / GIM_Reject,
4916	/ 12342 / // Label 25: @12342
4917	/ 12342 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 558/ GIMT_Encode4(`12507`),
4918	/ 12353 / /GILLT_s32//Label 556/ GIMT_Encode4(`12361`),
4919	/ 12357 / /GILLT_s64//Label 557/ GIMT_Encode4(`12470`),
4920	/ 12361 / // Label 556: @12361
4921	/ 12361 / GIM_Try, /On fail goto//Label 559/ GIMT_Encode4(`12469`),
4922	/ 12366 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4923	/ 12369 / GIM_Try_CheckFeatures, /On fail goto//Label 560/ GIMT_Encode4(`12402`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 28 //
4924	/ 12376 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4925	/ 12383 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4926	/ 12387 / // MIs[0] ptr
4927	/ 12387 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4928	/ 12391 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4929	/* 12395 / // (atomic_load_min:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4930	/ 12395 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
4931	/ 12400 / GIR_RootConstrainSelectedInstOperands,
4932	/ 12401 / // GIR_Coverage, 28,
4933	/ 12401 / GIR_Done,
4934	/ 12402 / // Label 560: @12402
4935	/ 12402 / GIM_Try_CheckFeatures, /On fail goto//Label 561/ GIMT_Encode4(`12435`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 29 //
4936	/ 12409 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
4937	/ 12416 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4938	/ 12420 / // MIs[0] ptr
4939	/ 12420 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4940	/ 12424 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4941	/* 12428 / // (atomic_load_min:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4942	/ 12428 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
4943	/ 12433 / GIR_RootConstrainSelectedInstOperands,
4944	/ 12434 / // GIR_Coverage, 29,
4945	/ 12434 / GIR_Done,
4946	/ 12435 / // Label 561: @12435
4947	/ 12435 / GIM_Try_CheckFeatures, /On fail goto//Label 562/ GIMT_Encode4(`12468`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 30 //
4948	/ 12442 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
4949	/ 12449 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4950	/ 12453 / // MIs[0] ptr
4951	/ 12453 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4952	/ 12457 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4953	/* 12461 / // (atomic_load_min:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4954	/ 12461 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
4955	/ 12466 / GIR_RootConstrainSelectedInstOperands,
4956	/ 12467 / // GIR_Coverage, 30,
4957	/ 12467 / GIR_Done,
4958	/ 12468 / // Label 562: @12468
4959	/ 12468 / GIM_Reject,
4960	/ 12469 / // Label 559: @12469
4961	/ 12469 / GIM_Reject,
4962	/ 12470 / // Label 557: @12470
4963	/ 12470 / GIM_Try_CheckFeatures, /On fail goto//Label 563/ GIMT_Encode4(`12506`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 219 //
4964	/ 12477 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
4965	/ 12480 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
4966	/ 12487 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4967	/ 12491 / // MIs[0] ptr
4968	/ 12491 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4969	/ 12495 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
4970	/* 12499 / // (atomic_load_min:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4971	/ 12499 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
4972	/ 12504 / GIR_RootConstrainSelectedInstOperands,
4973	/ 12505 / // GIR_Coverage, 219,
4974	/ 12505 / GIR_Done,
4975	/ 12506 / // Label 563: @12506
4976	/ 12506 / GIM_Reject,
4977	/ 12507 / // Label 558: @12507
4978	/ 12507 / GIM_Reject,
4979	/ 12508 / // Label 26: @12508
4980	/ 12508 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 566/ GIMT_Encode4(`12673`),
4981	/ 12519 / /GILLT_s32//Label 564/ GIMT_Encode4(`12527`),
4982	/ 12523 / /GILLT_s64//Label 565/ GIMT_Encode4(`12636`),
4983	/ 12527 / // Label 564: @12527
4984	/ 12527 / GIM_Try, /On fail goto//Label 567/ GIMT_Encode4(`12635`),
4985	/ 12532 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
4986	/ 12535 / GIM_Try_CheckFeatures, /On fail goto//Label 568/ GIMT_Encode4(`12568`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 37 //
4987	/ 12542 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
4988	/ 12549 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4989	/ 12553 / // MIs[0] ptr
4990	/ 12553 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
4991	/ 12557 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
4992	/* 12561 / // (atomic_load_umax:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4993	/ 12561 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
4994	/ 12566 / GIR_RootConstrainSelectedInstOperands,
4995	/ 12567 / // GIR_Coverage, 37,
4996	/ 12567 / GIR_Done,
4997	/ 12568 / // Label 568: @12568
4998	/ 12568 / GIM_Try_CheckFeatures, /On fail goto//Label 569/ GIMT_Encode4(`12601`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 38 //
4999	/ 12575 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
5000	/ 12582 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5001	/ 12586 / // MIs[0] ptr
5002	/ 12586 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5003	/ 12590 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5004	/* 12594 / // (atomic_load_umax:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5005	/ 12594 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5006	/ 12599 / GIR_RootConstrainSelectedInstOperands,
5007	/ 12600 / // GIR_Coverage, 38,
5008	/ 12600 / GIR_Done,
5009	/ 12601 / // Label 569: @12601
5010	/ 12601 / GIM_Try_CheckFeatures, /On fail goto//Label 570/ GIMT_Encode4(`12634`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 39 //
5011	/ 12608 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
5012	/ 12615 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5013	/ 12619 / // MIs[0] ptr
5014	/ 12619 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5015	/ 12623 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5016	/* 12627 / // (atomic_load_umax:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5017	/ 12627 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5018	/ 12632 / GIR_RootConstrainSelectedInstOperands,
5019	/ 12633 / // GIR_Coverage, 39,
5020	/ 12633 / GIR_Done,
5021	/ 12634 / // Label 570: @12634
5022	/ 12634 / GIM_Reject,
5023	/ 12635 / // Label 567: @12635
5024	/ 12635 / GIM_Reject,
5025	/ 12636 / // Label 565: @12636
5026	/ 12636 / GIM_Try_CheckFeatures, /On fail goto//Label 571/ GIMT_Encode4(`12672`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 222 //
5027	/ 12643 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
5028	/ 12646 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
5029	/ 12653 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5030	/ 12657 / // MIs[0] ptr
5031	/ 12657 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5032	/ 12661 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5033	/* 12665 / // (atomic_load_umax:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5034	/ 12665 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5035	/ 12670 / GIR_RootConstrainSelectedInstOperands,
5036	/ 12671 / // GIR_Coverage, 222,
5037	/ 12671 / GIR_Done,
5038	/ 12672 / // Label 571: @12672
5039	/ 12672 / GIM_Reject,
5040	/ 12673 / // Label 566: @12673
5041	/ 12673 / GIM_Reject,
5042	/ 12674 / // Label 27: @12674
5043	/ 12674 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 574/ GIMT_Encode4(`12839`),
5044	/ 12685 / /GILLT_s32//Label 572/ GIMT_Encode4(`12693`),
5045	/ 12689 / /GILLT_s64//Label 573/ GIMT_Encode4(`12802`),
5046	/ 12693 / // Label 572: @12693
5047	/ 12693 / GIM_Try, /On fail goto//Label 575/ GIMT_Encode4(`12801`),
5048	/ 12698 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
5049	/ 12701 / GIM_Try_CheckFeatures, /On fail goto//Label 576/ GIMT_Encode4(`12734`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 34 //
5050	/ 12708 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`1`),
5051	/ 12715 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5052	/ 12719 / // MIs[0] ptr
5053	/ 12719 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5054	/ 12723 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5055	/* 12727 / // (atomic_load_umin:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5056	/ 12727 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5057	/ 12732 / GIR_RootConstrainSelectedInstOperands,
5058	/ 12733 / // GIR_Coverage, 34,
5059	/ 12733 / GIR_Done,
5060	/ 12734 / // Label 576: @12734
5061	/ 12734 / GIM_Try_CheckFeatures, /On fail goto//Label 577/ GIMT_Encode4(`12767`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 35 //
5062	/ 12741 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`2`),
5063	/ 12748 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5064	/ 12752 / // MIs[0] ptr
5065	/ 12752 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5066	/ 12756 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5067	/* 12760 / // (atomic_load_umin:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5068	/ 12760 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5069	/ 12765 / GIR_RootConstrainSelectedInstOperands,
5070	/ 12766 / // GIR_Coverage, 35,
5071	/ 12766 / GIR_Done,
5072	/ 12767 / // Label 577: @12767
5073	/ 12767 / GIM_Try_CheckFeatures, /On fail goto//Label 578/ GIMT_Encode4(`12800`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 36 //
5074	/ 12774 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`4`),
5075	/ 12781 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5076	/ 12785 / // MIs[0] ptr
5077	/ 12785 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5078	/ 12789 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5079	/* 12793 / // (atomic_load_umin:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ :[i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5080	/ 12793 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5081	/ 12798 / GIR_RootConstrainSelectedInstOperands,
5082	/ 12799 / // GIR_Coverage, 36,
5083	/ 12799 / GIR_Done,
5084	/ 12800 / // Label 578: @12800
5085	/ 12800 / GIM_Reject,
5086	/ 12801 / // Label 575: @12801
5087	/ 12801 / GIM_Reject,
5088	/ 12802 / // Label 573: @12802
5089	/ 12802 / GIM_Try_CheckFeatures, /On fail goto//Label 579/ GIMT_Encode4(`12838`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 221 //
5090	/ 12809 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
5091	/ 12812 / GIM_CheckMemorySizeEqualTo, /MI/`0`, /MMO/`0`, /Size/GIMT_Encode4(`8`),
5092	/ 12819 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5093	/ 12823 / // MIs[0] ptr
5094	/ 12823 / GIM_CheckPointerToAny, /MI/`0`, /Op/`1`, /SizeInBits/`0`,
5095	/ 12827 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5096	/* 12831 / // (atomic_load_umin:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ :[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ :[i64] } iPTR:{ :[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5097	/ 12831 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5098	/ 12836 / GIR_RootConstrainSelectedInstOperands,
5099	/ 12837 / // GIR_Coverage, 221,
5100	/ 12837 / GIR_Done,
5101	/ 12838 / // Label 579: @12838
5102	/ 12838 / GIM_Reject,
5103	/ 12839 / // Label 574: @12839
5104	/ 12839 / GIM_Reject,
5105	/ 12840 / // Label 28: @12840
5106	/ 12840 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 582/ GIMT_Encode4(`19003`),
5107	/ 12851 / /GILLT_s32//Label 580/ GIMT_Encode4(`12859`),
5108	/ 12855 / /GILLT_s64//Label 581/ GIMT_Encode4(`18970`),
5109	/ 12859 / // Label 580: @12859
5110	/ 12859 / GIM_Try, /On fail goto//Label 583/ GIMT_Encode4(`18858`),
5111	/ 12864 / GIM_CheckIsMBB, /MI/`0`, /Op/`1`,
5112	/ 12867 / GIM_Try_CheckFeatures, /On fail goto//Label 584/ GIMT_Encode4(`12971`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2501 //
5113	/ 12874 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5114	/ 12878 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5115	/ 12882 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5116	/ 12886 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5117	/ 12890 / // MIs[1] Operand 1
5118	/ 12890 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5119	/ 12895 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5120	/ 12899 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5121	/ 12903 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5122	/ 12907 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5123	/ 12911 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
5124	/ 12915 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5125	/ 12919 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5126	/ 12923 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5127	/ 12927 / GIM_CheckConstantInt8, /MI/`3`, /Op/`1`, `1`,
5128	/ 12931 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5129	/ 12935 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5130	/ 12939 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5131	/ 12943 / // MIs[4] Operand 1
5132	/ 12943 / // No operand predicates
5133	/ 12943 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5134	/ 12948 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5135	/ 12952 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5136	/* 12954 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ :[i64] }:$rs), 0:{ :[i64] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT0 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5137	/ 12954 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT0),
5138	/ 12957 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`2`, // rs
5139	/ 12961 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5140	/ 12964 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5141	/ 12966 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5142	/ 12969 / GIR_RootConstrainSelectedInstOperands,
5143	/ 12970 / // GIR_Coverage, 2501,
5144	/ 12970 / GIR_EraseRootFromParent_Done,
5145	/ 12971 / // Label 584: @12971
5146	/ 12971 / GIM_Try_CheckFeatures, /On fail goto//Label 585/ GIMT_Encode4(`13082`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2502 //
5147	/ 12978 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5148	/ 12982 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5149	/ 12986 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5150	/ 12990 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5151	/ 12994 / // MIs[1] Operand 1
5152	/ 12994 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5153	/ 12999 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5154	/ 13003 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5155	/ 13007 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5156	/ 13011 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5157	/ 13015 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
5158	/ 13019 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5159	/ 13023 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5160	/ 13027 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5161	/ 13031 / GIM_CheckConstantInt, /MI/`3`, /Op/`1`, GIMT_Encode8(`4294967296`),
5162	/ 13042 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5163	/ 13046 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5164	/ 13050 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5165	/ 13054 / // MIs[4] Operand 1
5166	/ 13054 / // No operand predicates
5167	/ 13054 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5168	/ 13059 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5169	/ 13063 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5170	/* 13065 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ :[i64] }:$rs), 0:{ :[i64] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT032 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5171	/ 13065 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT032),
5172	/ 13068 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`2`, // rs
5173	/ 13072 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5174	/ 13075 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5175	/ 13077 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5176	/ 13080 / GIR_RootConstrainSelectedInstOperands,
5177	/ 13081 / // GIR_Coverage, 2502,
5178	/ 13081 / GIR_EraseRootFromParent_Done,
5179	/ 13082 / // Label 585: @13082
5180	/ 13082 / GIM_Try_CheckFeatures, /On fail goto//Label 586/ GIMT_Encode4(`13186`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2503 //
5181	/ 13089 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5182	/ 13093 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5183	/ 13097 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5184	/ 13101 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5185	/ 13105 / // MIs[1] Operand 1
5186	/ 13105 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5187	/ 13110 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5188	/ 13114 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5189	/ 13118 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5190	/ 13122 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5191	/ 13126 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
5192	/ 13130 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5193	/ 13134 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5194	/ 13138 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5195	/ 13142 / GIM_CheckConstantInt8, /MI/`3`, /Op/`1`, `1`,
5196	/ 13146 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5197	/ 13150 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5198	/ 13154 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5199	/ 13158 / // MIs[4] Operand 1
5200	/ 13158 / // No operand predicates
5201	/ 13158 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5202	/ 13163 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5203	/ 13167 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5204	/* 13169 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ :[i64] }:$rs), 0:{ :[i64] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT1 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5205	/ 13169 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT1),
5206	/ 13172 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`2`, // rs
5207	/ 13176 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5208	/ 13179 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5209	/ 13181 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5210	/ 13184 / GIR_RootConstrainSelectedInstOperands,
5211	/ 13185 / // GIR_Coverage, 2503,
5212	/ 13185 / GIR_EraseRootFromParent_Done,
5213	/ 13186 / // Label 586: @13186
5214	/ 13186 / GIM_Try_CheckFeatures, /On fail goto//Label 587/ GIMT_Encode4(`13297`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2504 //
5215	/ 13193 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5216	/ 13197 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5217	/ 13201 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5218	/ 13205 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5219	/ 13209 / // MIs[1] Operand 1
5220	/ 13209 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5221	/ 13214 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5222	/ 13218 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5223	/ 13222 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5224	/ 13226 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5225	/ 13230 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
5226	/ 13234 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5227	/ 13238 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5228	/ 13242 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5229	/ 13246 / GIM_CheckConstantInt, /MI/`3`, /Op/`1`, GIMT_Encode8(`4294967296`),
5230	/ 13257 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5231	/ 13261 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5232	/ 13265 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5233	/ 13269 / // MIs[4] Operand 1
5234	/ 13269 / // No operand predicates
5235	/ 13269 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5236	/ 13274 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5237	/ 13278 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5238	/* 13280 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ :[i64] }:$rs), 0:{ :[i64] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT132 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5239	/ 13280 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT132),
5240	/ 13283 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`2`, // rs
5241	/ 13287 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5242	/ 13290 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5243	/ 13292 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5244	/ 13295 / GIR_RootConstrainSelectedInstOperands,
5245	/ 13296 / // GIR_Coverage, 2504,
5246	/ 13296 / GIR_EraseRootFromParent_Done,
5247	/ 13297 / // Label 587: @13297
5248	/ 13297 / GIM_Try_CheckFeatures, /On fail goto//Label 588/ GIMT_Encode4(`13401`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 297 //
5249	/ 13304 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5250	/ 13308 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5251	/ 13312 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5252	/ 13316 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5253	/ 13320 / // MIs[1] Operand 1
5254	/ 13320 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5255	/ 13325 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5256	/ 13329 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5257	/ 13333 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5258	/ 13337 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5259	/ 13341 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5260	/ 13346 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`2`, // MIs[3]
5261	/ 13350 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5262	/ 13354 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5263	/ 13358 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5264	/ 13362 / GIM_CheckConstantInt8, /MI/`3`, /Op/`1`, `1`,
5265	/ 13366 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5266	/ 13370 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5267	/ 13374 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5268	/ 13378 / // MIs[4] Operand 1
5269	/ 13378 / // No operand predicates
5270	/ 13378 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5271	/ 13382 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5272	/* 13384 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ :[i64] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT0 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5273	/ 13384 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT0),
5274	/ 13387 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`1`, // rs
5275	/ 13391 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5276	/ 13394 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5277	/ 13396 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5278	/ 13399 / GIR_RootConstrainSelectedInstOperands,
5279	/ 13400 / // GIR_Coverage, 297,
5280	/ 13400 / GIR_EraseRootFromParent_Done,
5281	/ 13401 / // Label 588: @13401
5282	/ 13401 / GIM_Try_CheckFeatures, /On fail goto//Label 589/ GIMT_Encode4(`13512`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 298 //
5283	/ 13408 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5284	/ 13412 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5285	/ 13416 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5286	/ 13420 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5287	/ 13424 / // MIs[1] Operand 1
5288	/ 13424 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5289	/ 13429 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5290	/ 13433 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5291	/ 13437 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5292	/ 13441 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5293	/ 13445 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5294	/ 13450 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`2`, // MIs[3]
5295	/ 13454 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5296	/ 13458 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5297	/ 13462 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5298	/ 13466 / GIM_CheckConstantInt, /MI/`3`, /Op/`1`, GIMT_Encode8(`4294967296`),
5299	/ 13477 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5300	/ 13481 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5301	/ 13485 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5302	/ 13489 / // MIs[4] Operand 1
5303	/ 13489 / // No operand predicates
5304	/ 13489 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5305	/ 13493 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5306	/* 13495 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ :[i64] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT032 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5307	/ 13495 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT032),
5308	/ 13498 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`1`, // rs
5309	/ 13502 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5310	/ 13505 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5311	/ 13507 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5312	/ 13510 / GIR_RootConstrainSelectedInstOperands,
5313	/ 13511 / // GIR_Coverage, 298,
5314	/ 13511 / GIR_EraseRootFromParent_Done,
5315	/ 13512 / // Label 589: @13512
5316	/ 13512 / GIM_Try_CheckFeatures, /On fail goto//Label 590/ GIMT_Encode4(`13616`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 299 //
5317	/ 13519 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5318	/ 13523 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5319	/ 13527 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5320	/ 13531 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5321	/ 13535 / // MIs[1] Operand 1
5322	/ 13535 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5323	/ 13540 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5324	/ 13544 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5325	/ 13548 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5326	/ 13552 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5327	/ 13556 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5328	/ 13561 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`2`, // MIs[3]
5329	/ 13565 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5330	/ 13569 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5331	/ 13573 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5332	/ 13577 / GIM_CheckConstantInt8, /MI/`3`, /Op/`1`, `1`,
5333	/ 13581 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5334	/ 13585 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5335	/ 13589 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5336	/ 13593 / // MIs[4] Operand 1
5337	/ 13593 / // No operand predicates
5338	/ 13593 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5339	/ 13597 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5340	/* 13599 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 1:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ :[i64] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT1 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5341	/ 13599 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT1),
5342	/ 13602 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`1`, // rs
5343	/ 13606 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5344	/ 13609 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5345	/ 13611 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5346	/ 13614 / GIR_RootConstrainSelectedInstOperands,
5347	/ 13615 / // GIR_Coverage, 299,
5348	/ 13615 / GIR_EraseRootFromParent_Done,
5349	/ 13616 / // Label 590: @13616
5350	/ 13616 / GIM_Try_CheckFeatures, /On fail goto//Label 591/ GIMT_Encode4(`13727`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 300 //
5351	/ 13623 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5352	/ 13627 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5353	/ 13631 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5354	/ 13635 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5355	/ 13639 / // MIs[1] Operand 1
5356	/ 13639 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5357	/ 13644 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
5358	/ 13648 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_AND),
5359	/ 13652 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
5360	/ 13656 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s64,
5361	/ 13660 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5362	/ 13665 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`2`, // MIs[3]
5363	/ 13669 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_SHL),
5364	/ 13673 / GIM_CheckType, /MI/`3`, /Op/`1`, /Type/GILLT_s64,
5365	/ 13677 / GIM_CheckType, /MI/`3`, /Op/`2`, /Type/GILLT_s64,
5366	/ 13681 / GIM_CheckConstantInt, /MI/`3`, /Op/`1`, GIMT_Encode8(`4294967296`),
5367	/ 13692 / GIM_RecordInsn, /DefineMI/`4`, /MI/`3`, /OpIdx/`2`, // MIs[4]
5368	/ 13696 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5369	/ 13700 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5370	/ 13704 / // MIs[4] Operand 1
5371	/ 13704 / // No operand predicates
5372	/ 13704 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5373	/ 13708 / GIM_CheckIsSafeToFold, /NumInsns/`4`,
5374	/* 13710 / // (brcond (setcc:{ :[i32] } (and:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, (shl:{ :[i64] } 4294967296:{ :[i64] }, (imm:{ :[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ :[i64] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BBIT132 GPR64Opnd:{ :[i64] }:$rs, (imm:{ :[i64] }):$p, (bb:{ *:[Other] }):$offset)
5375	/ 13710 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BBIT132),
5376	/ 13713 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`2`, /OpIdx/`1`, // rs
5377	/ 13717 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`4`, // p
5378	/ 13720 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5379	/ 13722 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5380	/ 13725 / GIR_RootConstrainSelectedInstOperands,
5381	/ 13726 / // GIR_Coverage, 300,
5382	/ 13726 / GIR_EraseRootFromParent_Done,
5383	/ 13727 / // Label 591: @13727
5384	/ 13727 / GIM_Try_CheckFeatures, /On fail goto//Label 592/ GIMT_Encode4(`13780`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 94 //
5385	/ 13734 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5386	/ 13738 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5387	/ 13742 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5388	/ 13746 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5389	/ 13750 / // MIs[1] Operand 1
5390	/ 13750 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
5391	/ 13755 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5392	/ 13760 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5393	/ 13764 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5394	/* 13766 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZ GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5395	/ 13766 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ),
5396	/ 13769 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5397	/ 13773 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5398	/ 13775 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5399	/ 13778 / GIR_RootConstrainSelectedInstOperands,
5400	/ 13779 / // GIR_Coverage, 94,
5401	/ 13779 / GIR_EraseRootFromParent_Done,
5402	/ 13780 / // Label 592: @13780
5403	/ 13780 / GIM_Try_CheckFeatures, /On fail goto//Label 593/ GIMT_Encode4(`13833`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 95 //
5404	/ 13787 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5405	/ 13791 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5406	/ 13795 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5407	/ 13799 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5408	/ 13803 / // MIs[1] Operand 1
5409	/ 13803 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5410	/ 13808 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5411	/ 13813 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5412	/ 13817 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5413	/* 13819 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZ GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5414	/ 13819 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZ),
5415	/ 13822 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5416	/ 13826 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5417	/ 13828 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5418	/ 13831 / GIR_RootConstrainSelectedInstOperands,
5419	/ 13832 / // GIR_Coverage, 95,
5420	/ 13832 / GIR_EraseRootFromParent_Done,
5421	/ 13833 / // Label 593: @13833
5422	/ 13833 / GIM_Try_CheckFeatures, /On fail goto//Label 594/ GIMT_Encode4(`13886`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 96 //
5423	/ 13840 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5424	/ 13844 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5425	/ 13848 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5426	/ 13852 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5427	/ 13856 / // MIs[1] Operand 1
5428	/ 13856 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
5429	/ 13861 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5430	/ 13866 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5431	/ 13870 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5432	/* 13872 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZ GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5433	/ 13872 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ),
5434	/ 13875 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5435	/ 13879 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5436	/ 13881 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5437	/ 13884 / GIR_RootConstrainSelectedInstOperands,
5438	/ 13885 / // GIR_Coverage, 96,
5439	/ 13885 / GIR_EraseRootFromParent_Done,
5440	/ 13886 / // Label 594: @13886
5441	/ 13886 / GIM_Try_CheckFeatures, /On fail goto//Label 595/ GIMT_Encode4(`13939`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 97 //
5442	/ 13893 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5443	/ 13897 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5444	/ 13901 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5445	/ 13905 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5446	/ 13909 / // MIs[1] Operand 1
5447	/ 13909 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5448	/ 13914 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5449	/ 13919 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5450	/ 13923 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5451	/* 13925 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZ GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5452	/ 13925 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZ),
5453	/ 13928 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5454	/ 13932 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5455	/ 13934 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5456	/ 13937 / GIR_RootConstrainSelectedInstOperands,
5457	/ 13938 / // GIR_Coverage, 97,
5458	/ 13938 / GIR_EraseRootFromParent_Done,
5459	/ 13939 / // Label 595: @13939
5460	/ 13939 / GIM_Try_CheckFeatures, /On fail goto//Label 596/ GIMT_Encode4(`13992`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 272 //
5461	/ 13946 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5462	/ 13950 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5463	/ 13954 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5464	/ 13958 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5465	/ 13962 / // MIs[1] Operand 1
5466	/ 13962 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
5467	/ 13967 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5468	/ 13972 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5469	/ 13976 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5470	/* 13978 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, 0:{ :[i64] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
5471	/ 13978 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ64),
5472	/ 13981 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5473	/ 13985 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5474	/ 13987 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5475	/ 13990 / GIR_RootConstrainSelectedInstOperands,
5476	/ 13991 / // GIR_Coverage, 272,
5477	/ 13991 / GIR_EraseRootFromParent_Done,
5478	/ 13992 / // Label 596: @13992
5479	/ 13992 / GIM_Try_CheckFeatures, /On fail goto//Label 597/ GIMT_Encode4(`14045`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 273 //
5480	/ 13999 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5481	/ 14003 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5482	/ 14007 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5483	/ 14011 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5484	/ 14015 / // MIs[1] Operand 1
5485	/ 14015 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5486	/ 14020 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5487	/ 14025 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5488	/ 14029 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5489	/* 14031 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, 0:{ :[i64] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
5490	/ 14031 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZ64),
5491	/ 14034 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5492	/ 14038 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5493	/ 14040 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5494	/ 14043 / GIR_RootConstrainSelectedInstOperands,
5495	/ 14044 / // GIR_Coverage, 273,
5496	/ 14044 / GIR_EraseRootFromParent_Done,
5497	/ 14045 / // Label 597: @14045
5498	/ 14045 / GIM_Try_CheckFeatures, /On fail goto//Label 598/ GIMT_Encode4(`14098`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 274 //
5499	/ 14052 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5500	/ 14056 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5501	/ 14060 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5502	/ 14064 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5503	/ 14068 / // MIs[1] Operand 1
5504	/ 14068 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
5505	/ 14073 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5506	/ 14078 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5507	/ 14082 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5508	/* 14084 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, 0:{ :[i64] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
5509	/ 14084 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ64),
5510	/ 14087 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5511	/ 14091 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5512	/ 14093 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5513	/ 14096 / GIR_RootConstrainSelectedInstOperands,
5514	/ 14097 / // GIR_Coverage, 274,
5515	/ 14097 / GIR_EraseRootFromParent_Done,
5516	/ 14098 / // Label 598: @14098
5517	/ 14098 / GIM_Try_CheckFeatures, /On fail goto//Label 599/ GIMT_Encode4(`14151`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 275 //
5518	/ 14105 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5519	/ 14109 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5520	/ 14113 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5521	/ 14117 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5522	/ 14121 / // MIs[1] Operand 1
5523	/ 14121 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5524	/ 14126 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5525	/ 14131 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5526	/ 14135 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5527	/* 14137 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, 0:{ :[i64] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
5528	/ 14137 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZ64),
5529	/ 14140 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5530	/ 14144 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5531	/ 14146 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5532	/ 14149 / GIR_RootConstrainSelectedInstOperands,
5533	/ 14150 / // GIR_Coverage, 275,
5534	/ 14150 / GIR_EraseRootFromParent_Done,
5535	/ 14151 / // Label 599: @14151
5536	/ 14151 / GIM_Try_CheckFeatures, /On fail goto//Label 600/ GIMT_Encode4(`14204`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1130 //
5537	/ 14158 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5538	/ 14162 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5539	/ 14166 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5540	/ 14170 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5541	/ 14174 / // MIs[1] Operand 1
5542	/ 14174 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
5543	/ 14179 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5544	/ 14184 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5545	/ 14188 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5546	/* 14190 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5547	/ 14190 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ_MM),
5548	/ 14193 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5549	/ 14197 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5550	/ 14199 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5551	/ 14202 / GIR_RootConstrainSelectedInstOperands,
5552	/ 14203 / // GIR_Coverage, 1130,
5553	/ 14203 / GIR_EraseRootFromParent_Done,
5554	/ 14204 / // Label 600: @14204
5555	/ 14204 / GIM_Try_CheckFeatures, /On fail goto//Label 601/ GIMT_Encode4(`14257`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1131 //
5556	/ 14211 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5557	/ 14215 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5558	/ 14219 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5559	/ 14223 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5560	/ 14227 / // MIs[1] Operand 1
5561	/ 14227 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5562	/ 14232 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5563	/ 14237 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5564	/ 14241 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5565	/* 14243 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5566	/ 14243 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZ_MM),
5567	/ 14246 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5568	/ 14250 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5569	/ 14252 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5570	/ 14255 / GIR_RootConstrainSelectedInstOperands,
5571	/ 14256 / // GIR_Coverage, 1131,
5572	/ 14256 / GIR_EraseRootFromParent_Done,
5573	/ 14257 / // Label 601: @14257
5574	/ 14257 / GIM_Try_CheckFeatures, /On fail goto//Label 602/ GIMT_Encode4(`14310`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1132 //
5575	/ 14264 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5576	/ 14268 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5577	/ 14272 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5578	/ 14276 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5579	/ 14280 / // MIs[1] Operand 1
5580	/ 14280 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
5581	/ 14285 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5582	/ 14290 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5583	/ 14294 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5584	/* 14296 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5585	/ 14296 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ_MM),
5586	/ 14299 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5587	/ 14303 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5588	/ 14305 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5589	/ 14308 / GIR_RootConstrainSelectedInstOperands,
5590	/ 14309 / // GIR_Coverage, 1132,
5591	/ 14309 / GIR_EraseRootFromParent_Done,
5592	/ 14310 / // Label 602: @14310
5593	/ 14310 / GIM_Try_CheckFeatures, /On fail goto//Label 603/ GIMT_Encode4(`14363`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1133 //
5594	/ 14317 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5595	/ 14321 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5596	/ 14325 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5597	/ 14329 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5598	/ 14333 / // MIs[1] Operand 1
5599	/ 14333 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5600	/ 14338 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5601	/ 14343 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5602	/ 14347 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5603	/* 14349 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, 0:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)
5604	/ 14349 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZ_MM),
5605	/ 14352 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5606	/ 14356 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5607	/ 14358 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5608	/ 14361 / GIR_RootConstrainSelectedInstOperands,
5609	/ 14362 / // GIR_Coverage, 1133,
5610	/ 14362 / GIR_EraseRootFromParent_Done,
5611	/ 14363 / // Label 603: @14363
5612	/ 14363 / GIM_Try_CheckFeatures, /On fail goto//Label 604/ GIMT_Encode4(`14422`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1423 //
5613	/ 14370 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5614	/ 14374 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5615	/ 14378 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5616	/ 14382 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5617	/ 14386 / // MIs[1] Operand 1
5618	/ 14386 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5619	/ 14391 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5620	/ 14396 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5621	/ 14400 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5622	/* 14402 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BNE GPR32:{ :[i32] }:$lhs, ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
5623	/ 14402 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE),
5624	/ 14405 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5625	/ 14409 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5626	/ 14415 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5627	/ 14417 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5628	/ 14420 / GIR_RootConstrainSelectedInstOperands,
5629	/ 14421 / // GIR_Coverage, 1423,
5630	/ 14421 / GIR_EraseRootFromParent_Done,
5631	/ 14422 / // Label 604: @14422
5632	/ 14422 / GIM_Try_CheckFeatures, /On fail goto//Label 605/ GIMT_Encode4(`14481`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1424 //
5633	/ 14429 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5634	/ 14433 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5635	/ 14437 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5636	/ 14441 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5637	/ 14445 / // MIs[1] Operand 1
5638	/ 14445 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5639	/ 14450 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5640	/ 14455 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5641	/ 14459 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5642	/* 14461 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ GPR32:{ :[i32] }:$lhs, ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
5643	/ 14461 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
5644	/ 14464 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5645	/ 14468 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5646	/ 14474 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5647	/ 14476 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5648	/ 14479 / GIR_RootConstrainSelectedInstOperands,
5649	/ 14480 / // GIR_Coverage, 1424,
5650	/ 14480 / GIR_EraseRootFromParent_Done,
5651	/ 14481 / // Label 605: @14481
5652	/ 14481 / GIM_Try_CheckFeatures, /On fail goto//Label 606/ GIMT_Encode4(`14540`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1651 //
5653	/ 14488 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5654	/ 14492 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5655	/ 14496 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5656	/ 14500 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5657	/ 14504 / // MIs[1] Operand 1
5658	/ 14504 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5659	/ 14509 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5660	/ 14514 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5661	/ 14518 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5662	/* 14520 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BNE64 GPR64:{ :[i64] }:$lhs, ZERO_64:{ :[i64] }, (bb:{ *:[Other] }):$dst)
5663	/ 14520 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE64),
5664	/ 14523 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5665	/ 14527 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO_64), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5666	/ 14533 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5667	/ 14535 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5668	/ 14538 / GIR_RootConstrainSelectedInstOperands,
5669	/ 14539 / // GIR_Coverage, 1651,
5670	/ 14539 / GIR_EraseRootFromParent_Done,
5671	/ 14540 / // Label 606: @14540
5672	/ 14540 / GIM_Try_CheckFeatures, /On fail goto//Label 607/ GIMT_Encode4(`14599`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1652 //
5673	/ 14547 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5674	/ 14551 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5675	/ 14555 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5676	/ 14559 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5677	/ 14563 / // MIs[1] Operand 1
5678	/ 14563 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5679	/ 14568 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
5680	/ 14573 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5681	/ 14577 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5682	/* 14579 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ64 GPR64:{ :[i64] }:$lhs, ZERO_64:{ :[i64] }, (bb:{ *:[Other] }):$dst)
5683	/ 14579 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ64),
5684	/ 14582 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5685	/ 14586 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO_64), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5686	/ 14592 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5687	/ 14594 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5688	/ 14597 / GIR_RootConstrainSelectedInstOperands,
5689	/ 14598 / // GIR_Coverage, 1652,
5690	/ 14598 / GIR_EraseRootFromParent_Done,
5691	/ 14599 / // Label 607: @14599
5692	/ 14599 / GIM_Try_CheckFeatures, /On fail goto//Label 608/ GIMT_Encode4(`14649`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1983 //
5693	/ 14606 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5694	/ 14610 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5695	/ 14614 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5696	/ 14618 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5697	/ 14622 / // MIs[1] Operand 1
5698	/ 14622 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5699	/ 14627 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5700	/ 14632 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5701	/ 14636 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5702	/* 14638 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, 0:{ :[i32] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ :[i32] }:$rx, (bb:{ :[Other] }):$targ16)
5703	/ 14638 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BeqzRxImm16),
5704	/ 14641 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
5705	/ 14645 / GIR_RootToRootCopy, /OpIdx/`1`, // targ16
5706	/ 14647 / GIR_RootConstrainSelectedInstOperands,
5707	/ 14648 / // GIR_Coverage, 1983,
5708	/ 14648 / GIR_EraseRootFromParent_Done,
5709	/ 14649 / // Label 608: @14649
5710	/ 14649 / GIM_Try_CheckFeatures, /On fail goto//Label 609/ GIMT_Encode4(`14699`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1992 //
5711	/ 14656 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5712	/ 14660 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5713	/ 14664 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5714	/ 14668 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5715	/ 14672 / // MIs[1] Operand 1
5716	/ 14672 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5717	/ 14677 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5718	/ 14682 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5719	/ 14686 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5720	/* 14688 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, 0:{ :[i32] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ :[i32] }:$rx, (bb:{ :[Other] }):$targ16)
5721	/ 14688 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BnezRxImm16),
5722	/ 14691 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
5723	/ 14695 / GIR_RootToRootCopy, /OpIdx/`1`, // targ16
5724	/ 14697 / GIR_RootConstrainSelectedInstOperands,
5725	/ 14698 / // GIR_Coverage, 1992,
5726	/ 14698 / GIR_EraseRootFromParent_Done,
5727	/ 14699 / // Label 609: @14699
5728	/ 14699 / GIM_Try_CheckFeatures, /On fail goto//Label 610/ GIMT_Encode4(`14758`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2320 //
5729	/ 14706 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5730	/ 14710 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5731	/ 14714 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5732	/ 14718 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5733	/ 14722 / // MIs[1] Operand 1
5734	/ 14722 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5735	/ 14727 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5736	/ 14732 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5737	/ 14736 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5738	/* 14738 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BNE_MM GPR32:{ :[i32] }:$lhs, ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
5739	/ 14738 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE_MM),
5740	/ 14741 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5741	/ 14745 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5742	/ 14751 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5743	/ 14753 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5744	/ 14756 / GIR_RootConstrainSelectedInstOperands,
5745	/ 14757 / // GIR_Coverage, 2320,
5746	/ 14757 / GIR_EraseRootFromParent_Done,
5747	/ 14758 / // Label 610: @14758
5748	/ 14758 / GIM_Try_CheckFeatures, /On fail goto//Label 611/ GIMT_Encode4(`14817`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2321 //
5749	/ 14765 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5750	/ 14769 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5751	/ 14773 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5752	/ 14777 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5753	/ 14781 / // MIs[1] Operand 1
5754	/ 14781 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5755	/ 14786 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5756	/ 14791 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5757	/ 14795 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5758	/* 14797 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ_MM GPR32:{ :[i32] }:$lhs, ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
5759	/ 14797 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
5760	/ 14800 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5761	/ 14804 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
5762	/ 14810 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5763	/ 14812 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5764	/ 14815 / GIR_RootConstrainSelectedInstOperands,
5765	/ 14816 / // GIR_Coverage, 2321,
5766	/ 14816 / GIR_EraseRootFromParent_Done,
5767	/ 14817 / // Label 611: @14817
5768	/ 14817 / GIM_Try_CheckFeatures, /On fail goto//Label 612/ GIMT_Encode4(`14870`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2472 //
5769	/ 14824 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5770	/ 14828 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5771	/ 14832 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5772	/ 14836 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5773	/ 14840 / // MIs[1] Operand 1
5774	/ 14840 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
5775	/ 14845 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5776	/ 14850 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5777	/ 14854 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5778	/ 14856 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
5779	/ 14856 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNEZC_MMR6),
5780	/ 14859 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5781	/ 14863 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5782	/ 14865 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5783	/ 14868 / GIR_RootConstrainSelectedInstOperands,
5784	/ 14869 / // GIR_Coverage, 2472,
5785	/ 14869 / GIR_EraseRootFromParent_Done,
5786	/ 14870 / // Label 612: @14870
5787	/ 14870 / GIM_Try_CheckFeatures, /On fail goto//Label 613/ GIMT_Encode4(`14923`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2473 //
5788	/ 14877 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5789	/ 14881 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5790	/ 14885 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5791	/ 14889 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5792	/ 14893 / // MIs[1] Operand 1
5793	/ 14893 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
5794	/ 14898 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
5795	/ 14903 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5796	/ 14907 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5797	/ 14909 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
5798	/ 14909 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQZC_MMR6),
5799	/ 14912 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5800	/ 14916 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5801	/ 14918 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5802	/ 14921 / GIR_RootConstrainSelectedInstOperands,
5803	/ 14922 / // GIR_Coverage, 2473,
5804	/ 14922 / GIR_EraseRootFromParent_Done,
5805	/ 14923 / // Label 613: @14923
5806	/ 14923 / GIM_Try_CheckFeatures, /On fail goto//Label 614/ GIMT_Encode4(`14971`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1434 //
5807	/ 14930 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5808	/ 14934 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5809	/ 14938 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5810	/ 14942 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5811	/ 14946 / // MIs[1] Operand 1
5812	/ 14946 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5813	/ 14951 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
5814	/ 14955 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5815	/ 14957 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$lhs, 1:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BLEZ i32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
5816	/ 14957 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ),
5817	/ 14960 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5818	/ 14964 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5819	/ 14966 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5820	/ 14969 / GIR_RootConstrainSelectedInstOperands,
5821	/ 14970 / // GIR_Coverage, 1434,
5822	/ 14970 / GIR_EraseRootFromParent_Done,
5823	/ 14971 / // Label 614: @14971
5824	/ 14971 / GIM_Try_CheckFeatures, /On fail goto//Label 615/ GIMT_Encode4(`15019`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1435 //
5825	/ 14978 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5826	/ 14982 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5827	/ 14986 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5828	/ 14990 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5829	/ 14994 / // MIs[1] Operand 1
5830	/ 14994 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5831	/ 14999 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
5832	/ 15003 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5833	/ 15005 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$lhs, -1:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BGEZ i32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
5834	/ 15005 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ),
5835	/ 15008 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5836	/ 15012 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5837	/ 15014 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5838	/ 15017 / GIR_RootConstrainSelectedInstOperands,
5839	/ 15018 / // GIR_Coverage, 1435,
5840	/ 15018 / GIR_EraseRootFromParent_Done,
5841	/ 15019 / // Label 615: @15019
5842	/ 15019 / GIM_Try_CheckFeatures, /On fail goto//Label 616/ GIMT_Encode4(`15067`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1662 //
5843	/ 15026 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5844	/ 15030 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5845	/ 15034 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5846	/ 15038 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5847	/ 15042 / // MIs[1] Operand 1
5848	/ 15042 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5849	/ 15047 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
5850	/ 15051 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5851	/ 15053 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$lhs, 1:{ :[i64] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BLEZ64 i64:{ :[i64] }:$lhs, (bb:{ :[Other] }):$dst)*
5852	/ 15053 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ64),
5853	/ 15056 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5854	/ 15060 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5855	/ 15062 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5856	/ 15065 / GIR_RootConstrainSelectedInstOperands,
5857	/ 15066 / // GIR_Coverage, 1662,
5858	/ 15066 / GIR_EraseRootFromParent_Done,
5859	/ 15067 / // Label 616: @15067
5860	/ 15067 / GIM_Try_CheckFeatures, /On fail goto//Label 617/ GIMT_Encode4(`15115`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1663 //
5861	/ 15074 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5862	/ 15078 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5863	/ 15082 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
5864	/ 15086 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
5865	/ 15090 / // MIs[1] Operand 1
5866	/ 15090 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5867	/ 15095 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
5868	/ 15099 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5869	/ 15101 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$lhs, -1:{ :[i64] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BGEZ64 i64:{ :[i64] }:$lhs, (bb:{ :[Other] }):$dst)*
5870	/ 15101 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ64),
5871	/ 15104 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
5872	/ 15108 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
5873	/ 15110 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5874	/ 15113 / GIR_RootConstrainSelectedInstOperands,
5875	/ 15114 / // GIR_Coverage, 1663,
5876	/ 15114 / GIR_EraseRootFromParent_Done,
5877	/ 15115 / // Label 617: @15115
5878	/ 15115 / GIM_Try_CheckFeatures, /On fail goto//Label 618/ GIMT_Encode4(`15163`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1893 //
5879	/ 15122 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5880	/ 15126 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5881	/ 15130 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5882	/ 15134 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5883	/ 15138 / // MIs[1] Operand 1
5884	/ 15138 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5885	/ 15143 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5886	/ 15147 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5887	/ 15149 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 0:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5888	/ 15149 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZC),
5889	/ 15152 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5890	/ 15156 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5891	/ 15158 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5892	/ 15161 / GIR_RootConstrainSelectedInstOperands,
5893	/ 15162 / // GIR_Coverage, 1893,
5894	/ 15162 / GIR_EraseRootFromParent_Done,
5895	/ 15163 / // Label 618: @15163
5896	/ 15163 / GIM_Try_CheckFeatures, /On fail goto//Label 619/ GIMT_Encode4(`15211`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1894 //
5897	/ 15170 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5898	/ 15174 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5899	/ 15178 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5900	/ 15182 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5901	/ 15186 / // MIs[1] Operand 1
5902	/ 15186 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
5903	/ 15191 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
5904	/ 15195 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5905	/ 15197 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 1:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5906	/ 15197 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZC),
5907	/ 15200 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5908	/ 15204 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5909	/ 15206 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5910	/ 15209 / GIR_RootConstrainSelectedInstOperands,
5911	/ 15210 / // GIR_Coverage, 1894,
5912	/ 15210 / GIR_EraseRootFromParent_Done,
5913	/ 15211 / // Label 619: @15211
5914	/ 15211 / GIM_Try_CheckFeatures, /On fail goto//Label 620/ GIMT_Encode4(`15259`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1895 //
5915	/ 15218 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5916	/ 15222 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5917	/ 15226 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5918	/ 15230 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5919	/ 15234 / // MIs[1] Operand 1
5920	/ 15234 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
5921	/ 15239 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5922	/ 15243 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5923	/ 15245 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 0:{ :[i32] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5924	/ 15245 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZC),
5925	/ 15248 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5926	/ 15252 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5927	/ 15254 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5928	/ 15257 / GIR_RootConstrainSelectedInstOperands,
5929	/ 15258 / // GIR_Coverage, 1895,
5930	/ 15258 / GIR_EraseRootFromParent_Done,
5931	/ 15259 / // Label 620: @15259
5932	/ 15259 / GIM_Try_CheckFeatures, /On fail goto//Label 621/ GIMT_Encode4(`15307`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1896 //
5933	/ 15266 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5934	/ 15270 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5935	/ 15274 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5936	/ 15278 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5937	/ 15282 / // MIs[1] Operand 1
5938	/ 15282 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
5939	/ 15287 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
5940	/ 15291 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5941	/ 15293 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 1:{ :[i32] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5942	/ 15293 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZC),
5943	/ 15296 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5944	/ 15300 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5945	/ 15302 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5946	/ 15305 / GIR_RootConstrainSelectedInstOperands,
5947	/ 15306 / // GIR_Coverage, 1896,
5948	/ 15306 / GIR_EraseRootFromParent_Done,
5949	/ 15307 / // Label 621: @15307
5950	/ 15307 / GIM_Try_CheckFeatures, /On fail goto//Label 622/ GIMT_Encode4(`15355`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1897 //
5951	/ 15314 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5952	/ 15318 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5953	/ 15322 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5954	/ 15326 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5955	/ 15330 / // MIs[1] Operand 1
5956	/ 15330 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5957	/ 15335 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5958	/ 15339 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5959	/ 15341 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 0:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5960	/ 15341 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZC),
5961	/ 15344 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5962	/ 15348 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5963	/ 15350 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5964	/ 15353 / GIR_RootConstrainSelectedInstOperands,
5965	/ 15354 / // GIR_Coverage, 1897,
5966	/ 15354 / GIR_EraseRootFromParent_Done,
5967	/ 15355 / // Label 622: @15355
5968	/ 15355 / GIM_Try_CheckFeatures, /On fail goto//Label 623/ GIMT_Encode4(`15403`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1898 //
5969	/ 15362 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5970	/ 15366 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5971	/ 15370 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5972	/ 15374 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5973	/ 15378 / // MIs[1] Operand 1
5974	/ 15378 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
5975	/ 15383 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
5976	/ 15387 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5977	/ 15389 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, -1:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5978	/ 15389 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZC),
5979	/ 15392 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5980	/ 15396 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5981	/ 15398 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
5982	/ 15401 / GIR_RootConstrainSelectedInstOperands,
5983	/ 15402 / // GIR_Coverage, 1898,
5984	/ 15402 / GIR_EraseRootFromParent_Done,
5985	/ 15403 / // Label 623: @15403
5986	/ 15403 / GIM_Try_CheckFeatures, /On fail goto//Label 624/ GIMT_Encode4(`15451`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1899 //
5987	/ 15410 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
5988	/ 15414 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
5989	/ 15418 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
5990	/ 15422 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
5991	/ 15426 / // MIs[1] Operand 1
5992	/ 15426 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
5993	/ 15431 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
5994	/ 15435 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
5995	/ 15437 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, 0:{ :[i32] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
5996	/ 15437 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZC),
5997	/ 15440 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
5998	/ 15444 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
5999	/ 15446 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6000	/ 15449 / GIR_RootConstrainSelectedInstOperands,
6001	/ 15450 / // GIR_Coverage, 1899,
6002	/ 15450 / GIR_EraseRootFromParent_Done,
6003	/ 15451 / // Label 624: @15451
6004	/ 15451 / GIM_Try_CheckFeatures, /On fail goto//Label 625/ GIMT_Encode4(`15499`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1900 //
6005	/ 15458 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6006	/ 15462 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6007	/ 15466 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6008	/ 15470 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6009	/ 15474 / // MIs[1] Operand 1
6010	/ 15474 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6011	/ 15479 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
6012	/ 15483 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6013	/ 15485 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$rs, -1:{ :[i32] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZC GPR32Opnd:{ :[i32] }:$rs, (bb:{ :[Other] }):$offset)*
6014	/ 15485 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZC),
6015	/ 15488 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6016	/ 15492 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6017	/ 15494 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6018	/ 15497 / GIR_RootConstrainSelectedInstOperands,
6019	/ 15498 / // GIR_Coverage, 1900,
6020	/ 15498 / GIR_EraseRootFromParent_Done,
6021	/ 15499 / // Label 625: @15499
6022	/ 15499 / GIM_Try_CheckFeatures, /On fail goto//Label 626/ GIMT_Encode4(`15547`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1936 //
6023	/ 15506 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6024	/ 15510 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6025	/ 15514 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6026	/ 15518 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6027	/ 15522 / // MIs[1] Operand 1
6028	/ 15522 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6029	/ 15527 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
6030	/ 15531 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6031	/ 15533 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 0:{ :[i64] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6032	/ 15533 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZC64),
6033	/ 15536 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6034	/ 15540 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6035	/ 15542 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6036	/ 15545 / GIR_RootConstrainSelectedInstOperands,
6037	/ 15546 / // GIR_Coverage, 1936,
6038	/ 15546 / GIR_EraseRootFromParent_Done,
6039	/ 15547 / // Label 626: @15547
6040	/ 15547 / GIM_Try_CheckFeatures, /On fail goto//Label 627/ GIMT_Encode4(`15595`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1937 //
6041	/ 15554 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6042	/ 15558 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6043	/ 15562 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6044	/ 15566 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6045	/ 15570 / // MIs[1] Operand 1
6046	/ 15570 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6047	/ 15575 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
6048	/ 15579 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6049	/ 15581 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 1:{ :[i64] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6050	/ 15581 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZC64),
6051	/ 15584 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6052	/ 15588 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6053	/ 15590 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6054	/ 15593 / GIR_RootConstrainSelectedInstOperands,
6055	/ 15594 / // GIR_Coverage, 1937,
6056	/ 15594 / GIR_EraseRootFromParent_Done,
6057	/ 15595 / // Label 627: @15595
6058	/ 15595 / GIM_Try_CheckFeatures, /On fail goto//Label 628/ GIMT_Encode4(`15643`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1938 //
6059	/ 15602 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6060	/ 15606 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6061	/ 15610 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6062	/ 15614 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6063	/ 15618 / // MIs[1] Operand 1
6064	/ 15618 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6065	/ 15623 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
6066	/ 15627 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6067	/ 15629 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 0:{ :[i64] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6068	/ 15629 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZC64),
6069	/ 15632 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6070	/ 15636 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6071	/ 15638 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6072	/ 15641 / GIR_RootConstrainSelectedInstOperands,
6073	/ 15642 / // GIR_Coverage, 1938,
6074	/ 15642 / GIR_EraseRootFromParent_Done,
6075	/ 15643 / // Label 628: @15643
6076	/ 15643 / GIM_Try_CheckFeatures, /On fail goto//Label 629/ GIMT_Encode4(`15691`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1939 //
6077	/ 15650 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6078	/ 15654 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6079	/ 15658 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6080	/ 15662 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6081	/ 15666 / // MIs[1] Operand 1
6082	/ 15666 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6083	/ 15671 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
6084	/ 15675 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6085	/ 15677 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 1:{ :[i64] }, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6086	/ 15677 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZC64),
6087	/ 15680 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6088	/ 15684 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6089	/ 15686 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6090	/ 15689 / GIR_RootConstrainSelectedInstOperands,
6091	/ 15690 / // GIR_Coverage, 1939,
6092	/ 15690 / GIR_EraseRootFromParent_Done,
6093	/ 15691 / // Label 629: @15691
6094	/ 15691 / GIM_Try_CheckFeatures, /On fail goto//Label 630/ GIMT_Encode4(`15739`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1940 //
6095	/ 15698 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6096	/ 15702 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6097	/ 15706 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6098	/ 15710 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6099	/ 15714 / // MIs[1] Operand 1
6100	/ 15714 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6101	/ 15719 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
6102	/ 15723 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6103	/ 15725 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 0:{ :[i64] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6104	/ 15725 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGTZC64),
6105	/ 15728 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6106	/ 15732 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6107	/ 15734 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6108	/ 15737 / GIR_RootConstrainSelectedInstOperands,
6109	/ 15738 / // GIR_Coverage, 1940,
6110	/ 15738 / GIR_EraseRootFromParent_Done,
6111	/ 15739 / // Label 630: @15739
6112	/ 15739 / GIM_Try_CheckFeatures, /On fail goto//Label 631/ GIMT_Encode4(`15787`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1941 //
6113	/ 15746 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6114	/ 15750 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6115	/ 15754 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6116	/ 15758 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6117	/ 15762 / // MIs[1] Operand 1
6118	/ 15762 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6119	/ 15767 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
6120	/ 15771 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6121	/* 15773 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, -1:{ :[i64] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
6122	/ 15773 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZC64),
6123	/ 15776 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6124	/ 15780 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6125	/ 15782 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6126	/ 15785 / GIR_RootConstrainSelectedInstOperands,
6127	/ 15786 / // GIR_Coverage, 1941,
6128	/ 15786 / GIR_EraseRootFromParent_Done,
6129	/ 15787 / // Label 631: @15787
6130	/ 15787 / GIM_Try_CheckFeatures, /On fail goto//Label 632/ GIMT_Encode4(`15835`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1942 //
6131	/ 15794 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6132	/ 15798 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6133	/ 15802 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6134	/ 15806 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6135	/ 15810 / // MIs[1] Operand 1
6136	/ 15810 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6137	/ 15815 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
6138	/ 15819 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6139	/ 15821 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, 0:{ :[i64] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)*
6140	/ 15821 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZC64),
6141	/ 15824 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6142	/ 15828 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6143	/ 15830 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6144	/ 15833 / GIR_RootConstrainSelectedInstOperands,
6145	/ 15834 / // GIR_Coverage, 1942,
6146	/ 15834 / GIR_EraseRootFromParent_Done,
6147	/ 15835 / // Label 632: @15835
6148	/ 15835 / GIM_Try_CheckFeatures, /On fail goto//Label 633/ GIMT_Encode4(`15883`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1943 //
6149	/ 15842 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6150	/ 15846 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6151	/ 15850 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6152	/ 15854 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6153	/ 15858 / // MIs[1] Operand 1
6154	/ 15858 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6155	/ 15863 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
6156	/ 15867 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6157	/* 15869 / // (brcond (setcc:{ :[i32] } i64:{ :[i64] }:$rs, -1:{ :[i64] }, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ :[i64] }:$rs, (bb:{ :[Other] }):$offset)
6158	/ 15869 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTZC64),
6159	/ 15872 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6160	/ 15876 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6161	/ 15878 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6162	/ 15881 / GIR_RootConstrainSelectedInstOperands,
6163	/ 15882 / // GIR_Coverage, 1943,
6164	/ 15882 / GIR_EraseRootFromParent_Done,
6165	/ 15883 / // Label 633: @15883
6166	/ 15883 / GIM_Try_CheckFeatures, /On fail goto//Label 634/ GIMT_Encode4(`15931`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2331 //
6167	/ 15890 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6168	/ 15894 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6169	/ 15898 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6170	/ 15902 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6171	/ 15906 / // MIs[1] Operand 1
6172	/ 15906 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6173	/ 15911 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `1`,
6174	/ 15915 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6175	/ 15917 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$lhs, 1:{ :[i32] }, SETLT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BLEZ_MM i32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
6176	/ 15917 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLEZ_MM),
6177	/ 15920 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6178	/ 15924 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6179	/ 15926 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6180	/ 15929 / GIR_RootConstrainSelectedInstOperands,
6181	/ 15930 / // GIR_Coverage, 2331,
6182	/ 15930 / GIR_EraseRootFromParent_Done,
6183	/ 15931 / // Label 634: @15931
6184	/ 15931 / GIM_Try_CheckFeatures, /On fail goto//Label 635/ GIMT_Encode4(`15979`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2332 //
6185	/ 15938 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6186	/ 15942 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6187	/ 15946 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6188	/ 15950 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6189	/ 15954 / // MIs[1] Operand 1
6190	/ 15954 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6191	/ 15959 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `255`,
6192	/ 15963 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6193	/ 15965 / // (brcond (setcc:{ :[i32] } i32:{ :[i32] }:$lhs, -1:{ :[i32] }, SETGT:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BGEZ_MM i32:{ :[i32] }:$lhs, (bb:{ :[Other] }):$dst)*
6194	/ 15965 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEZ_MM),
6195	/ 15968 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6196	/ 15972 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6197	/ 15974 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6198	/ 15977 / GIR_RootConstrainSelectedInstOperands,
6199	/ 15978 / // GIR_Coverage, 2332,
6200	/ 15978 / GIR_EraseRootFromParent_Done,
6201	/ 15979 / // Label 635: @15979
6202	/ 15979 / GIM_Try_CheckFeatures, /On fail goto//Label 636/ GIMT_Encode4(`16037`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 92 //
6203	/ 15986 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6204	/ 15990 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6205	/ 15994 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6206	/ 15998 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6207	/ 16002 / // MIs[1] Operand 1
6208	/ 16002 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
6209	/ 16007 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6210	/ 16012 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6211	/ 16017 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6212	/* 16019 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BEQ GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6213	/ 16019 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6214	/ 16022 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6215	/ 16026 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6216	/ 16030 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6217	/ 16032 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6218	/ 16035 / GIR_RootConstrainSelectedInstOperands,
6219	/ 16036 / // GIR_Coverage, 92,
6220	/ 16036 / GIR_EraseRootFromParent_Done,
6221	/ 16037 / // Label 636: @16037
6222	/ 16037 / GIM_Try_CheckFeatures, /On fail goto//Label 637/ GIMT_Encode4(`16095`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 93 //
6223	/ 16044 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6224	/ 16048 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6225	/ 16052 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6226	/ 16056 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6227	/ 16060 / // MIs[1] Operand 1
6228	/ 16060 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
6229	/ 16065 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6230	/ 16070 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6231	/ 16075 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6232	/* 16077 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BNE GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6233	/ 16077 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE),
6234	/ 16080 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6235	/ 16084 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6236	/ 16088 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6237	/ 16090 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6238	/ 16093 / GIR_RootConstrainSelectedInstOperands,
6239	/ 16094 / // GIR_Coverage, 93,
6240	/ 16094 / GIR_EraseRootFromParent_Done,
6241	/ 16095 / // Label 637: @16095
6242	/ 16095 / GIM_Try_CheckFeatures, /On fail goto//Label 638/ GIMT_Encode4(`16153`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 270 //
6243	/ 16102 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6244	/ 16106 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6245	/ 16110 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6246	/ 16114 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6247	/ 16118 / // MIs[1] Operand 1
6248	/ 16118 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
6249	/ 16123 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6250	/ 16128 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6251	/ 16133 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6252	/* 16135 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BEQ64 GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6253	/ 16135 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ64),
6254	/ 16138 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6255	/ 16142 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6256	/ 16146 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6257	/ 16148 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6258	/ 16151 / GIR_RootConstrainSelectedInstOperands,
6259	/ 16152 / // GIR_Coverage, 270,
6260	/ 16152 / GIR_EraseRootFromParent_Done,
6261	/ 16153 / // Label 638: @16153
6262	/ 16153 / GIM_Try_CheckFeatures, /On fail goto//Label 639/ GIMT_Encode4(`16211`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 271 //
6263	/ 16160 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6264	/ 16164 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6265	/ 16168 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6266	/ 16172 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6267	/ 16176 / // MIs[1] Operand 1
6268	/ 16176 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
6269	/ 16181 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6270	/ 16186 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6271	/ 16191 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6272	/* 16193 / // (brcond (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BNE64 GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6273	/ 16193 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE64),
6274	/ 16196 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6275	/ 16200 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6276	/ 16204 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6277	/ 16206 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6278	/ 16209 / GIR_RootConstrainSelectedInstOperands,
6279	/ 16210 / // GIR_Coverage, 271,
6280	/ 16210 / GIR_EraseRootFromParent_Done,
6281	/ 16211 / // Label 639: @16211
6282	/ 16211 / GIM_Try_CheckFeatures, /On fail goto//Label 640/ GIMT_Encode4(`16269`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1128 //
6283	/ 16218 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6284	/ 16222 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6285	/ 16226 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6286	/ 16230 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6287	/ 16234 / // MIs[1] Operand 1
6288	/ 16234 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
6289	/ 16239 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6290	/ 16244 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6291	/ 16249 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6292	/* 16251 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6293	/ 16251 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
6294	/ 16254 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6295	/ 16258 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6296	/ 16262 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6297	/ 16264 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6298	/ 16267 / GIR_RootConstrainSelectedInstOperands,
6299	/ 16268 / // GIR_Coverage, 1128,
6300	/ 16268 / GIR_EraseRootFromParent_Done,
6301	/ 16269 / // Label 640: @16269
6302	/ 16269 / GIM_Try_CheckFeatures, /On fail goto//Label 641/ GIMT_Encode4(`16327`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1129 //
6303	/ 16276 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6304	/ 16280 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6305	/ 16284 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6306	/ 16288 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6307	/ 16292 / // MIs[1] Operand 1
6308	/ 16292 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
6309	/ 16297 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6310	/ 16302 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6311	/ 16307 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6312	/* 16309 / // (brcond (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETNE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BNE_MM GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6313	/ 16309 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE_MM),
6314	/ 16312 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6315	/ 16316 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6316	/ 16320 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6317	/ 16322 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6318	/ 16325 / GIR_RootConstrainSelectedInstOperands,
6319	/ 16326 / // GIR_Coverage, 1129,
6320	/ 16326 / GIR_EraseRootFromParent_Done,
6321	/ 16327 / // Label 641: @16327
6322	/ 16327 / GIM_Try_CheckFeatures, /On fail goto//Label 642/ GIMT_Encode4(`16408`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1425 //
6323	/ 16334 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6324	/ 16338 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6325	/ 16342 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6326	/ 16346 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6327	/ 16350 / // MIs[1] Operand 1
6328	/ 16350 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6329	/ 16355 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6330	/ 16360 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6331	/ 16365 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6332	/* 16367 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6333	/ 16367 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6334	/ 16370 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
6335	/ 16374 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6336	/ 16379 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6337	/ 16383 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6338	/ 16387 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6339	/ 16389 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6340	/ 16392 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6341	/ 16395 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6342	/ 16401 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6343	/ 16403 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6344	/ 16406 / GIR_RootConstrainSelectedInstOperands,
6345	/ 16407 / // GIR_Coverage, 1425,
6346	/ 16407 / GIR_EraseRootFromParent_Done,
6347	/ 16408 / // Label 642: @16408
6348	/ 16408 / GIM_Try_CheckFeatures, /On fail goto//Label 643/ GIMT_Encode4(`16489`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1426 //
6349	/ 16415 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6350	/ 16419 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6351	/ 16423 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6352	/ 16427 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6353	/ 16431 / // MIs[1] Operand 1
6354	/ 16431 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
6355	/ 16436 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6356	/ 16441 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6357	/ 16446 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6358	/* 16448 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6359	/ 16448 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6360	/ 16451 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
6361	/ 16455 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6362	/ 16460 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6363	/ 16464 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6364	/ 16468 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6365	/ 16470 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6366	/ 16473 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6367	/ 16476 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6368	/ 16482 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6369	/ 16484 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6370	/ 16487 / GIR_RootConstrainSelectedInstOperands,
6371	/ 16488 / // GIR_Coverage, 1426,
6372	/ 16488 / GIR_EraseRootFromParent_Done,
6373	/ 16489 / // Label 643: @16489
6374	/ 16489 / GIM_Try_CheckFeatures, /On fail goto//Label 644/ GIMT_Encode4(`16570`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1431 //
6375	/ 16496 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6376	/ 16500 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6377	/ 16504 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6378	/ 16508 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6379	/ 16512 / // MIs[1] Operand 1
6380	/ 16512 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6381	/ 16517 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6382	/ 16522 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6383	/ 16527 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6384	/* 16529 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6385	/ 16529 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6386	/ 16532 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
6387	/ 16536 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6388	/ 16541 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6389	/ 16545 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6390	/ 16549 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6391	/ 16551 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6392	/ 16554 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6393	/ 16557 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6394	/ 16563 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6395	/ 16565 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6396	/ 16568 / GIR_RootConstrainSelectedInstOperands,
6397	/ 16569 / // GIR_Coverage, 1431,
6398	/ 16569 / GIR_EraseRootFromParent_Done,
6399	/ 16570 / // Label 644: @16570
6400	/ 16570 / GIM_Try_CheckFeatures, /On fail goto//Label 645/ GIMT_Encode4(`16651`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1432 //
6401	/ 16577 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6402	/ 16581 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6403	/ 16585 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6404	/ 16589 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6405	/ 16593 / // MIs[1] Operand 1
6406	/ 16593 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
6407	/ 16598 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6408	/ 16603 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6409	/ 16608 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6410	/* 16610 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6411	/ 16610 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6412	/ 16613 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
6413	/ 16617 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6414	/ 16622 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6415	/ 16626 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6416	/ 16630 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6417	/ 16632 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6418	/ 16635 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6419	/ 16638 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6420	/ 16644 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6421	/ 16646 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6422	/ 16649 / GIR_RootConstrainSelectedInstOperands,
6423	/ 16650 / // GIR_Coverage, 1432,
6424	/ 16650 / GIR_EraseRootFromParent_Done,
6425	/ 16651 / // Label 645: @16651
6426	/ 16651 / GIM_Try_CheckFeatures, /On fail goto//Label 646/ GIMT_Encode4(`16732`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1653 //
6427	/ 16658 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6428	/ 16662 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6429	/ 16666 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6430	/ 16670 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6431	/ 16674 / // MIs[1] Operand 1
6432	/ 16674 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6433	/ 16679 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6434	/ 16684 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6435	/ 16689 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6436	/* 16691 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6437	/ 16691 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6438	/ 16694 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
6439	/ 16698 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6440	/ 16703 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6441	/ 16707 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6442	/ 16711 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6443	/ 16713 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6444	/ 16716 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6445	/ 16719 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6446	/ 16725 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6447	/ 16727 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6448	/ 16730 / GIR_RootConstrainSelectedInstOperands,
6449	/ 16731 / // GIR_Coverage, 1653,
6450	/ 16731 / GIR_EraseRootFromParent_Done,
6451	/ 16732 / // Label 646: @16732
6452	/ 16732 / GIM_Try_CheckFeatures, /On fail goto//Label 647/ GIMT_Encode4(`16813`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1654 //
6453	/ 16739 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6454	/ 16743 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6455	/ 16747 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6456	/ 16751 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6457	/ 16755 / // MIs[1] Operand 1
6458	/ 16755 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
6459	/ 16760 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6460	/ 16765 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6461	/ 16770 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6462	/* 16772 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6463	/ 16772 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6464	/ 16775 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
6465	/ 16779 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6466	/ 16784 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6467	/ 16788 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6468	/ 16792 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6469	/ 16794 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6470	/ 16797 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6471	/ 16800 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6472	/ 16806 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6473	/ 16808 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6474	/ 16811 / GIR_RootConstrainSelectedInstOperands,
6475	/ 16812 / // GIR_Coverage, 1654,
6476	/ 16812 / GIR_EraseRootFromParent_Done,
6477	/ 16813 / // Label 647: @16813
6478	/ 16813 / GIM_Try_CheckFeatures, /On fail goto//Label 648/ GIMT_Encode4(`16894`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1659 //
6479	/ 16820 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6480	/ 16824 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6481	/ 16828 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6482	/ 16832 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6483	/ 16836 / // MIs[1] Operand 1
6484	/ 16836 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6485	/ 16841 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6486	/ 16846 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6487	/ 16851 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6488	/* 16853 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6489	/ 16853 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6490	/ 16856 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
6491	/ 16860 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6492	/ 16865 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6493	/ 16869 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6494	/ 16873 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6495	/ 16875 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6496	/ 16878 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6497	/ 16881 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6498	/ 16887 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6499	/ 16889 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6500	/ 16892 / GIR_RootConstrainSelectedInstOperands,
6501	/ 16893 / // GIR_Coverage, 1659,
6502	/ 16893 / GIR_EraseRootFromParent_Done,
6503	/ 16894 / // Label 648: @16894
6504	/ 16894 / GIM_Try_CheckFeatures, /On fail goto//Label 649/ GIMT_Encode4(`16975`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1660 //
6505	/ 16901 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6506	/ 16905 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6507	/ 16909 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6508	/ 16913 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6509	/ 16917 / // MIs[1] Operand 1
6510	/ 16917 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
6511	/ 16922 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6512	/ 16927 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6513	/ 16932 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6514	/* 16934 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6515	/ 16934 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6516	/ 16937 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
6517	/ 16941 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6518	/ 16946 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6519	/ 16950 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6520	/ 16954 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6521	/ 16956 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ),
6522	/ 16959 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6523	/ 16962 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6524	/ 16968 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6525	/ 16970 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6526	/ 16973 / GIR_RootConstrainSelectedInstOperands,
6527	/ 16974 / // GIR_Coverage, 1660,
6528	/ 16974 / GIR_EraseRootFromParent_Done,
6529	/ 16975 / // Label 649: @16975
6530	/ 16975 / GIM_Try_CheckFeatures, /On fail goto//Label 650/ GIMT_Encode4(`17033`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1901 //
6531	/ 16982 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6532	/ 16986 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6533	/ 16990 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6534	/ 16994 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6535	/ 16998 / // MIs[1] Operand 1
6536	/ 16998 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6537	/ 17003 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6538	/ 17008 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6539	/ 17013 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6540	/* 17015 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTC GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6541	/ 17015 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTC),
6542	/ 17018 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6543	/ 17022 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6544	/ 17026 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6545	/ 17028 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6546	/ 17031 / GIR_RootConstrainSelectedInstOperands,
6547	/ 17032 / // GIR_Coverage, 1901,
6548	/ 17032 / GIR_EraseRootFromParent_Done,
6549	/ 17033 / // Label 650: @17033
6550	/ 17033 / GIM_Try_CheckFeatures, /On fail goto//Label 651/ GIMT_Encode4(`17091`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1902 //
6551	/ 17040 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6552	/ 17044 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6553	/ 17048 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6554	/ 17052 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6555	/ 17056 / // MIs[1] Operand 1
6556	/ 17056 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6557	/ 17061 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6558	/ 17066 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6559	/ 17071 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6560	/* 17073 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEC GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6561	/ 17073 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEC),
6562	/ 17076 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6563	/ 17080 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6564	/ 17084 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6565	/ 17086 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6566	/ 17089 / GIR_RootConstrainSelectedInstOperands,
6567	/ 17090 / // GIR_Coverage, 1902,
6568	/ 17090 / GIR_EraseRootFromParent_Done,
6569	/ 17091 / // Label 651: @17091
6570	/ 17091 / GIM_Try_CheckFeatures, /On fail goto//Label 652/ GIMT_Encode4(`17149`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1903 //
6571	/ 17098 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6572	/ 17102 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6573	/ 17106 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6574	/ 17110 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6575	/ 17114 / // MIs[1] Operand 1
6576	/ 17114 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6577	/ 17119 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6578	/ 17124 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6579	/ 17129 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6580	/* 17131 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTC GPR32:{ :[i32] }:$rt, GPR32:{ :[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6581	/ 17131 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTC),
6582	/ 17134 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6583	/ 17138 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6584	/ 17142 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6585	/ 17144 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6586	/ 17147 / GIR_RootConstrainSelectedInstOperands,
6587	/ 17148 / // GIR_Coverage, 1903,
6588	/ 17148 / GIR_EraseRootFromParent_Done,
6589	/ 17149 / // Label 652: @17149
6590	/ 17149 / GIM_Try_CheckFeatures, /On fail goto//Label 653/ GIMT_Encode4(`17207`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1904 //
6591	/ 17156 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6592	/ 17160 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6593	/ 17164 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6594	/ 17168 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6595	/ 17172 / // MIs[1] Operand 1
6596	/ 17172 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6597	/ 17177 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6598	/ 17182 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6599	/ 17187 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6600	/* 17189 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEC GPR32:{ :[i32] }:$rt, GPR32:{ :[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6601	/ 17189 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEC),
6602	/ 17192 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6603	/ 17196 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6604	/ 17200 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6605	/ 17202 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6606	/ 17205 / GIR_RootConstrainSelectedInstOperands,
6607	/ 17206 / // GIR_Coverage, 1904,
6608	/ 17206 / GIR_EraseRootFromParent_Done,
6609	/ 17207 / // Label 653: @17207
6610	/ 17207 / GIM_Try_CheckFeatures, /On fail goto//Label 654/ GIMT_Encode4(`17265`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1905 //
6611	/ 17214 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6612	/ 17218 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6613	/ 17222 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6614	/ 17226 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6615	/ 17230 / // MIs[1] Operand 1
6616	/ 17230 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
6617	/ 17235 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6618	/ 17240 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6619	/ 17245 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6620	/* 17247 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETULT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTUC GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6621	/ 17247 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTUC),
6622	/ 17250 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6623	/ 17254 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6624	/ 17258 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6625	/ 17260 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6626	/ 17263 / GIR_RootConstrainSelectedInstOperands,
6627	/ 17264 / // GIR_Coverage, 1905,
6628	/ 17264 / GIR_EraseRootFromParent_Done,
6629	/ 17265 / // Label 654: @17265
6630	/ 17265 / GIM_Try_CheckFeatures, /On fail goto//Label 655/ GIMT_Encode4(`17323`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1906 //
6631	/ 17272 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6632	/ 17276 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6633	/ 17280 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6634	/ 17284 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6635	/ 17288 / // MIs[1] Operand 1
6636	/ 17288 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
6637	/ 17293 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6638	/ 17298 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6639	/ 17303 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6640	/* 17305 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEUC GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6641	/ 17305 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEUC),
6642	/ 17308 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6643	/ 17312 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6644	/ 17316 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6645	/ 17318 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6646	/ 17321 / GIR_RootConstrainSelectedInstOperands,
6647	/ 17322 / // GIR_Coverage, 1906,
6648	/ 17322 / GIR_EraseRootFromParent_Done,
6649	/ 17323 / // Label 655: @17323
6650	/ 17323 / GIM_Try_CheckFeatures, /On fail goto//Label 656/ GIMT_Encode4(`17381`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1907 //
6651	/ 17330 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6652	/ 17334 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6653	/ 17338 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6654	/ 17342 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6655	/ 17346 / // MIs[1] Operand 1
6656	/ 17346 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
6657	/ 17351 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6658	/ 17356 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6659	/ 17361 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6660	/* 17363 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETUGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTUC GPR32:{ :[i32] }:$rt, GPR32:{ :[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6661	/ 17363 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTUC),
6662	/ 17366 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6663	/ 17370 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6664	/ 17374 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6665	/ 17376 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6666	/ 17379 / GIR_RootConstrainSelectedInstOperands,
6667	/ 17380 / // GIR_Coverage, 1907,
6668	/ 17380 / GIR_EraseRootFromParent_Done,
6669	/ 17381 / // Label 656: @17381
6670	/ 17381 / GIM_Try_CheckFeatures, /On fail goto//Label 657/ GIMT_Encode4(`17439`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1908 //
6671	/ 17388 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6672	/ 17392 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6673	/ 17396 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6674	/ 17400 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6675	/ 17404 / // MIs[1] Operand 1
6676	/ 17404 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
6677	/ 17409 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6678	/ 17414 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6679	/ 17419 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6680	/* 17421 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$rs, GPR32:{ :[i32] }:$rt, SETULE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEUC GPR32:{ :[i32] }:$rt, GPR32:{ :[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6681	/ 17421 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEUC),
6682	/ 17424 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6683	/ 17428 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6684	/ 17432 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6685	/ 17434 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6686	/ 17437 / GIR_RootConstrainSelectedInstOperands,
6687	/ 17438 / // GIR_Coverage, 1908,
6688	/ 17438 / GIR_EraseRootFromParent_Done,
6689	/ 17439 / // Label 657: @17439
6690	/ 17439 / GIM_Try_CheckFeatures, /On fail goto//Label 658/ GIMT_Encode4(`17497`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1944 //
6691	/ 17446 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6692	/ 17450 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6693	/ 17454 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6694	/ 17458 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6695	/ 17462 / // MIs[1] Operand 1
6696	/ 17462 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6697	/ 17467 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6698	/ 17472 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6699	/ 17477 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6700	/* 17479 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETLT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTC64 GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6701	/ 17479 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTC64),
6702	/ 17482 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6703	/ 17486 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6704	/ 17490 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6705	/ 17492 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6706	/ 17495 / GIR_RootConstrainSelectedInstOperands,
6707	/ 17496 / // GIR_Coverage, 1944,
6708	/ 17496 / GIR_EraseRootFromParent_Done,
6709	/ 17497 / // Label 658: @17497
6710	/ 17497 / GIM_Try_CheckFeatures, /On fail goto//Label 659/ GIMT_Encode4(`17555`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1945 //
6711	/ 17504 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6712	/ 17508 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6713	/ 17512 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6714	/ 17516 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6715	/ 17520 / // MIs[1] Operand 1
6716	/ 17520 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6717	/ 17525 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6718	/ 17530 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6719	/ 17535 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6720	/* 17537 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEC64 GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6721	/ 17537 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEC64),
6722	/ 17540 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6723	/ 17544 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6724	/ 17548 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6725	/ 17550 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6726	/ 17553 / GIR_RootConstrainSelectedInstOperands,
6727	/ 17554 / // GIR_Coverage, 1945,
6728	/ 17554 / GIR_EraseRootFromParent_Done,
6729	/ 17555 / // Label 659: @17555
6730	/ 17555 / GIM_Try_CheckFeatures, /On fail goto//Label 660/ GIMT_Encode4(`17613`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1946 //
6731	/ 17562 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6732	/ 17566 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6733	/ 17570 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6734	/ 17574 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6735	/ 17578 / // MIs[1] Operand 1
6736	/ 17578 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6737	/ 17583 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6738	/ 17588 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6739	/ 17593 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6740	/* 17595 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTC64 GPR64:{ :[i64] }:$rt, GPR64:{ :[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6741	/ 17595 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTC64),
6742	/ 17598 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6743	/ 17602 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6744	/ 17606 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6745	/ 17608 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6746	/ 17611 / GIR_RootConstrainSelectedInstOperands,
6747	/ 17612 / // GIR_Coverage, 1946,
6748	/ 17612 / GIR_EraseRootFromParent_Done,
6749	/ 17613 / // Label 660: @17613
6750	/ 17613 / GIM_Try_CheckFeatures, /On fail goto//Label 661/ GIMT_Encode4(`17671`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1947 //
6751	/ 17620 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6752	/ 17624 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6753	/ 17628 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6754	/ 17632 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6755	/ 17636 / // MIs[1] Operand 1
6756	/ 17636 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6757	/ 17641 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6758	/ 17646 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6759	/ 17651 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6760	/* 17653 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETLE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEC64 GPR64:{ :[i64] }:$rt, GPR64:{ :[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6761	/ 17653 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEC64),
6762	/ 17656 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6763	/ 17660 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6764	/ 17664 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6765	/ 17666 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6766	/ 17669 / GIR_RootConstrainSelectedInstOperands,
6767	/ 17670 / // GIR_Coverage, 1947,
6768	/ 17670 / GIR_EraseRootFromParent_Done,
6769	/ 17671 / // Label 661: @17671
6770	/ 17671 / GIM_Try_CheckFeatures, /On fail goto//Label 662/ GIMT_Encode4(`17729`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1948 //
6771	/ 17678 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6772	/ 17682 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6773	/ 17686 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6774	/ 17690 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6775	/ 17694 / // MIs[1] Operand 1
6776	/ 17694 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
6777	/ 17699 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6778	/ 17704 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6779	/ 17709 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6780	/* 17711 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETULT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTUC64 GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6781	/ 17711 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTUC64),
6782	/ 17714 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6783	/ 17718 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6784	/ 17722 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6785	/ 17724 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6786	/ 17727 / GIR_RootConstrainSelectedInstOperands,
6787	/ 17728 / // GIR_Coverage, 1948,
6788	/ 17728 / GIR_EraseRootFromParent_Done,
6789	/ 17729 / // Label 662: @17729
6790	/ 17729 / GIM_Try_CheckFeatures, /On fail goto//Label 663/ GIMT_Encode4(`17787`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1949 //
6791	/ 17736 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6792	/ 17740 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6793	/ 17744 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6794	/ 17748 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6795	/ 17752 / // MIs[1] Operand 1
6796	/ 17752 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
6797	/ 17757 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6798	/ 17762 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6799	/ 17767 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6800	/* 17769 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEUC64 GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6801	/ 17769 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEUC64),
6802	/ 17772 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6803	/ 17776 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6804	/ 17780 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6805	/ 17782 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6806	/ 17785 / GIR_RootConstrainSelectedInstOperands,
6807	/ 17786 / // GIR_Coverage, 1949,
6808	/ 17786 / GIR_EraseRootFromParent_Done,
6809	/ 17787 / // Label 663: @17787
6810	/ 17787 / GIM_Try_CheckFeatures, /On fail goto//Label 664/ GIMT_Encode4(`17845`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1950 //
6811	/ 17794 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6812	/ 17798 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6813	/ 17802 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6814	/ 17806 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6815	/ 17810 / // MIs[1] Operand 1
6816	/ 17810 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
6817	/ 17815 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6818	/ 17820 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6819	/ 17825 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6820	/* 17827 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETUGT:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BLTUC64 GPR64:{ :[i64] }:$rt, GPR64:{ :[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6821	/ 17827 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BLTUC64),
6822	/ 17830 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6823	/ 17834 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6824	/ 17838 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6825	/ 17840 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6826	/ 17843 / GIR_RootConstrainSelectedInstOperands,
6827	/ 17844 / // GIR_Coverage, 1950,
6828	/ 17844 / GIR_EraseRootFromParent_Done,
6829	/ 17845 / // Label 664: @17845
6830	/ 17845 / GIM_Try_CheckFeatures, /On fail goto//Label 665/ GIMT_Encode4(`17903`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1951 //
6831	/ 17852 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6832	/ 17856 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6833	/ 17860 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
6834	/ 17864 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
6835	/ 17868 / // MIs[1] Operand 1
6836	/ 17868 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
6837	/ 17873 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6838	/ 17878 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
6839	/ 17883 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6840	/* 17885 / // (brcond (setcc:{ :[i32] } GPR64:{ :[i64] }:$rs, GPR64:{ :[i64] }:$rt, SETULE:{ :[Other] }), (bb:{ :[Other] }):$offset) => (BGEUC64 GPR64:{ :[i64] }:$rt, GPR64:{ :[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6841	/ 17885 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BGEUC64),
6842	/ 17888 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
6843	/ 17892 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
6844	/ 17896 / GIR_RootToRootCopy, /OpIdx/`1`, // offset
6845	/ 17898 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6846	/ 17901 / GIR_RootConstrainSelectedInstOperands,
6847	/ 17902 / // GIR_Coverage, 1951,
6848	/ 17902 / GIR_EraseRootFromParent_Done,
6849	/ 17903 / // Label 665: @17903
6850	/ 17903 / GIM_Try_CheckFeatures, /On fail goto//Label 666/ GIMT_Encode4(`17958`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1981 //
6851	/ 17910 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6852	/ 17914 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6853	/ 17918 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6854	/ 17922 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6855	/ 17926 / // MIs[1] Operand 1
6856	/ 17926 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
6857	/ 17931 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6858	/ 17936 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6859	/ 17941 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6860	/* 17943 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETEQ:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6861	/ 17943 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BteqzT8CmpX16),
6862	/ 17946 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6863	/ 17950 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6864	/ 17954 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6865	/ 17956 / GIR_RootConstrainSelectedInstOperands,
6866	/ 17957 / // GIR_Coverage, 1981,
6867	/ 17957 / GIR_EraseRootFromParent_Done,
6868	/ 17958 / // Label 666: @17958
6869	/ 17958 / GIM_Try_CheckFeatures, /On fail goto//Label 667/ GIMT_Encode4(`18013`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1984 //
6870	/ 17965 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6871	/ 17969 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6872	/ 17973 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6873	/ 17977 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6874	/ 17981 / // MIs[1] Operand 1
6875	/ 17981 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
6876	/ 17986 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6877	/ 17991 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6878	/ 17996 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6879	/* 17998 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETGT:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ :[i32] }:$ry, CPU16Regs:{ :[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6880	/ 17998 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BtnezT8SltX16),
6881	/ 18001 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6882	/ 18005 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6883	/ 18009 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6884	/ 18011 / GIR_RootConstrainSelectedInstOperands,
6885	/ 18012 / // GIR_Coverage, 1984,
6886	/ 18012 / GIR_EraseRootFromParent_Done,
6887	/ 18013 / // Label 667: @18013
6888	/ 18013 / GIM_Try_CheckFeatures, /On fail goto//Label 668/ GIMT_Encode4(`18068`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1985 //
6889	/ 18020 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6890	/ 18024 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6891	/ 18028 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6892	/ 18032 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6893	/ 18036 / // MIs[1] Operand 1
6894	/ 18036 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6895	/ 18041 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6896	/ 18046 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6897	/ 18051 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6898	/* 18053 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETGE:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6899	/ 18053 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BteqzT8SltX16),
6900	/ 18056 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6901	/ 18060 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6902	/ 18064 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6903	/ 18066 / GIR_RootConstrainSelectedInstOperands,
6904	/ 18067 / // GIR_Coverage, 1985,
6905	/ 18067 / GIR_EraseRootFromParent_Done,
6906	/ 18068 / // Label 668: @18068
6907	/ 18068 / GIM_Try_CheckFeatures, /On fail goto//Label 669/ GIMT_Encode4(`18123`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1987 //
6908	/ 18075 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6909	/ 18079 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6910	/ 18083 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6911	/ 18087 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6912	/ 18091 / // MIs[1] Operand 1
6913	/ 18091 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
6914	/ 18096 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6915	/ 18101 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6916	/ 18106 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6917	/* 18108 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETLT:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6918	/ 18108 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BtnezT8SltX16),
6919	/ 18111 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6920	/ 18115 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6921	/ 18119 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6922	/ 18121 / GIR_RootConstrainSelectedInstOperands,
6923	/ 18122 / // GIR_Coverage, 1987,
6924	/ 18122 / GIR_EraseRootFromParent_Done,
6925	/ 18123 / // Label 669: @18123
6926	/ 18123 / GIM_Try_CheckFeatures, /On fail goto//Label 670/ GIMT_Encode4(`18178`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1989 //
6927	/ 18130 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6928	/ 18134 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6929	/ 18138 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6930	/ 18142 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6931	/ 18146 / // MIs[1] Operand 1
6932	/ 18146 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
6933	/ 18151 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6934	/ 18156 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6935	/ 18161 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6936	/* 18163 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETLE:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ :[i32] }:$ry, CPU16Regs:{ :[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6937	/ 18163 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BteqzT8SltX16),
6938	/ 18166 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6939	/ 18170 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6940	/ 18174 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6941	/ 18176 / GIR_RootConstrainSelectedInstOperands,
6942	/ 18177 / // GIR_Coverage, 1989,
6943	/ 18177 / GIR_EraseRootFromParent_Done,
6944	/ 18178 / // Label 670: @18178
6945	/ 18178 / GIM_Try_CheckFeatures, /On fail goto//Label 671/ GIMT_Encode4(`18233`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1990 //
6946	/ 18185 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6947	/ 18189 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6948	/ 18193 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6949	/ 18197 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6950	/ 18201 / // MIs[1] Operand 1
6951	/ 18201 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
6952	/ 18206 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6953	/ 18211 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6954	/ 18216 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6955	/* 18218 / // (brcond (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETNE:{ :[Other] }), (bb:{ :[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6956	/ 18218 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BtnezT8CmpX16),
6957	/ 18221 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rx
6958	/ 18225 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // ry
6959	/ 18229 / GIR_RootToRootCopy, /OpIdx/`1`, // imm16
6960	/ 18231 / GIR_RootConstrainSelectedInstOperands,
6961	/ 18232 / // GIR_Coverage, 1990,
6962	/ 18232 / GIR_EraseRootFromParent_Done,
6963	/ 18233 / // Label 671: @18233
6964	/ 18233 / GIM_Try_CheckFeatures, /On fail goto//Label 672/ GIMT_Encode4(`18314`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2322 //
6965	/ 18240 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6966	/ 18244 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6967	/ 18248 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6968	/ 18252 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6969	/ 18256 / // MIs[1] Operand 1
6970	/ 18256 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
6971	/ 18261 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6972	/ 18266 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6973	/ 18271 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
6974	/* 18273 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ_MM (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
6975	/ 18273 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
6976	/ 18276 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
6977	/ 18280 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6978	/ 18285 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
6979	/ 18289 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
6980	/ 18293 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
6981	/ 18295 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
6982	/ 18298 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
6983	/ 18301 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
6984	/ 18307 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
6985	/ 18309 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
6986	/ 18312 / GIR_RootConstrainSelectedInstOperands,
6987	/ 18313 / // GIR_Coverage, 2322,
6988	/ 18313 / GIR_EraseRootFromParent_Done,
6989	/ 18314 / // Label 672: @18314
6990	/ 18314 / GIM_Try_CheckFeatures, /On fail goto//Label 673/ GIMT_Encode4(`18395`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2323 //
6991	/ 18321 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
6992	/ 18325 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
6993	/ 18329 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
6994	/ 18333 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
6995	/ 18337 / // MIs[1] Operand 1
6996	/ 18337 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
6997	/ 18342 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6998	/ 18347 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
6999	/ 18352 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7000	/* 18354 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
7001	/ 18354 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7002	/ 18357 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
7003	/ 18361 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7004	/ 18366 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7005	/ 18370 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7006	/ 18374 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7007	/ 18376 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
7008	/ 18379 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7009	/ 18382 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7010	/ 18388 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7011	/ 18390 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7012	/ 18393 / GIR_RootConstrainSelectedInstOperands,
7013	/ 18394 / // GIR_Coverage, 2323,
7014	/ 18394 / GIR_EraseRootFromParent_Done,
7015	/ 18395 / // Label 673: @18395
7016	/ 18395 / GIM_Try_CheckFeatures, /On fail goto//Label 674/ GIMT_Encode4(`18476`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2328 //
7017	/ 18402 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7018	/ 18406 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7019	/ 18410 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7020	/ 18414 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7021	/ 18418 / // MIs[1] Operand 1
7022	/ 18418 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
7023	/ 18423 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7024	/ 18428 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7025	/ 18433 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7026	/* 18435 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ_MM (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
7027	/ 18435 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7028	/ 18438 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
7029	/ 18442 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7030	/ 18447 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7031	/ 18451 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7032	/ 18455 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7033	/ 18457 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
7034	/ 18460 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7035	/ 18463 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7036	/ 18469 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7037	/ 18471 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7038	/ 18474 / GIR_RootConstrainSelectedInstOperands,
7039	/ 18475 / // GIR_Coverage, 2328,
7040	/ 18475 / GIR_EraseRootFromParent_Done,
7041	/ 18476 / // Label 674: @18476
7042	/ 18476 / GIM_Try_CheckFeatures, /On fail goto//Label 675/ GIMT_Encode4(`18557`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2329 //
7043	/ 18483 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7044	/ 18487 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7045	/ 18491 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7046	/ 18495 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7047	/ 18499 / // MIs[1] Operand 1
7048	/ 18499 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
7049	/ 18504 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7050	/ 18509 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7051	/ 18514 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7052	/* 18516 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), ZERO:{ :[i32] }, (bb:{ *:[Other] }):$dst)
7053	/ 18516 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7054	/ 18519 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
7055	/ 18523 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7056	/ 18528 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7057	/ 18532 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7058	/ 18536 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7059	/ 18538 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQ_MM),
7060	/ 18541 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7061	/ 18544 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7062	/ 18550 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7063	/ 18552 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7064	/ 18555 / GIR_RootConstrainSelectedInstOperands,
7065	/ 18556 / // GIR_Coverage, 2329,
7066	/ 18556 / GIR_EraseRootFromParent_Done,
7067	/ 18557 / // Label 675: @18557
7068	/ 18557 / GIM_Try_CheckFeatures, /On fail goto//Label 676/ GIMT_Encode4(`18632`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2474 //
7069	/ 18564 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7070	/ 18568 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7071	/ 18572 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7072	/ 18576 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7073	/ 18580 / // MIs[1] Operand 1
7074	/ 18580 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
7075	/ 18585 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7076	/ 18590 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7077	/ 18595 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7078	/* 18597 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), (bb:{ :[Other] }):$dst)
7079	/ 18597 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7080	/ 18600 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
7081	/ 18604 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7082	/ 18609 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7083	/ 18613 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7084	/ 18617 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7085	/ 18619 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQZC_MMR6),
7086	/ 18622 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7087	/ 18625 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7088	/ 18627 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7089	/ 18630 / GIR_RootConstrainSelectedInstOperands,
7090	/ 18631 / // GIR_Coverage, 2474,
7091	/ 18631 / GIR_EraseRootFromParent_Done,
7092	/ 18632 / // Label 676: @18632
7093	/ 18632 / GIM_Try_CheckFeatures, /On fail goto//Label 677/ GIMT_Encode4(`18707`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2475 //
7094	/ 18639 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7095	/ 18643 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7096	/ 18647 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7097	/ 18651 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7098	/ 18655 / // MIs[1] Operand 1
7099	/ 18655 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
7100	/ 18660 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7101	/ 18665 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7102	/ 18670 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7103	/* 18672 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), (bb:{ :[Other] }):$dst)
7104	/ 18672 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7105	/ 18675 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
7106	/ 18679 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7107	/ 18684 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7108	/ 18688 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7109	/ 18692 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7110	/ 18694 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQZC_MMR6),
7111	/ 18697 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7112	/ 18700 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7113	/ 18702 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7114	/ 18705 / GIR_RootConstrainSelectedInstOperands,
7115	/ 18706 / // GIR_Coverage, 2475,
7116	/ 18706 / GIR_EraseRootFromParent_Done,
7117	/ 18707 / // Label 677: @18707
7118	/ 18707 / GIM_Try_CheckFeatures, /On fail goto//Label 678/ GIMT_Encode4(`18782`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2480 //
7119	/ 18714 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7120	/ 18718 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7121	/ 18722 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7122	/ 18726 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7123	/ 18730 / // MIs[1] Operand 1
7124	/ 18730 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
7125	/ 18735 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7126	/ 18740 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7127	/ 18745 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7128	/* 18747 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), (bb:{ :[Other] }):$dst)
7129	/ 18747 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7130	/ 18750 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
7131	/ 18754 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7132	/ 18759 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7133	/ 18763 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7134	/ 18767 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7135	/ 18769 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQZC_MMR6),
7136	/ 18772 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7137	/ 18775 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7138	/ 18777 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7139	/ 18780 / GIR_RootConstrainSelectedInstOperands,
7140	/ 18781 / // GIR_Coverage, 2480,
7141	/ 18781 / GIR_EraseRootFromParent_Done,
7142	/ 18782 / // Label 678: @18782
7143	/ 18782 / GIM_Try_CheckFeatures, /On fail goto//Label 679/ GIMT_Encode4(`18857`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2481 //
7144	/ 18789 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`0`, // MIs[1]
7145	/ 18793 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
7146	/ 18797 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
7147	/ 18801 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
7148	/ 18805 / // MIs[1] Operand 1
7149	/ 18805 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
7150	/ 18810 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7151	/ 18815 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7152	/ 18820 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7153	/* 18822 / // (brcond (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), (bb:{ :[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), (bb:{ :[Other] }):$dst)
7154	/ 18822 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
7155	/ 18825 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
7156	/ 18829 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7157	/ 18834 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
7158	/ 18838 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
7159	/ 18842 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
7160	/ 18844 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BEQZC_MMR6),
7161	/ 18847 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
7162	/ 18850 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7163	/ 18852 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7164	/ 18855 / GIR_RootConstrainSelectedInstOperands,
7165	/ 18856 / // GIR_Coverage, 2481,
7166	/ 18856 / GIR_EraseRootFromParent_Done,
7167	/ 18857 / // Label 679: @18857
7168	/ 18857 / GIM_Reject,
7169	/ 18858 / // Label 583: @18858
7170	/ 18858 / GIM_Try_CheckFeatures, /On fail goto//Label 680/ GIMT_Encode4(`18890`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1433 //
7171	/ 18865 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7172	/ 18869 / // MIs[0] dst
7173	/ 18869 / GIM_CheckIsMBB, /MI/`0`, /Op/`1`,
7174	/ 18872 / // (brcond GPR32:{ :[i32] }:$cond, (bb:{ :[Other] }):$dst) => (BNE GPR32:{ :[i32] }:$cond, ZERO:{ :[i32] }, (bb:{ :[Other] }):$dst)*
7175	/ 18872 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE),
7176	/ 18875 / GIR_RootToRootCopy, /OpIdx/`0`, // cond
7177	/ 18877 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7178	/ 18883 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7179	/ 18885 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7180	/ 18888 / GIR_RootConstrainSelectedInstOperands,
7181	/ 18889 / // GIR_Coverage, 1433,
7182	/ 18889 / GIR_EraseRootFromParent_Done,
7183	/ 18890 / // Label 680: @18890
7184	/ 18890 / GIM_Try_CheckFeatures, /On fail goto//Label 681/ GIMT_Encode4(`18911`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1993 //
7185	/ 18897 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7186	/ 18901 / // MIs[0] targ16
7187	/ 18901 / GIM_CheckIsMBB, /MI/`0`, /Op/`1`,
7188	/ 18904 / // (brcond CPU16Regs:{ :[i32] }:$rx, (bb:{ :[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ :[i32] }:$rx, (bb:{ :[Other] }):$targ16)
7189	/ 18904 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::BnezRxImm16),
7190	/ 18909 / GIR_RootConstrainSelectedInstOperands,
7191	/ 18910 / // GIR_Coverage, 1993,
7192	/ 18910 / GIR_Done,
7193	/ 18911 / // Label 681: @18911
7194	/ 18911 / GIM_Try, /On fail goto//Label 682/ GIMT_Encode4(`18969`),
7195	/ 18916 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7196	/ 18920 / GIM_CheckIsMBB, /MI/`0`, /Op/`1`,
7197	/ 18923 / GIM_Try_CheckFeatures, /On fail goto//Label 683/ GIMT_Encode4(`18948`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2330 //
7198	/ 18930 / // (brcond GPR32:{ :[i32] }:$cond, (bb:{ :[Other] }):$dst) => (BNE_MM GPR32:{ :[i32] }:$cond, ZERO:{ :[i32] }, (bb:{ :[Other] }):$dst)*
7199	/ 18930 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE_MM),
7200	/ 18933 / GIR_RootToRootCopy, /OpIdx/`0`, // cond
7201	/ 18935 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7202	/ 18941 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7203	/ 18943 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7204	/ 18946 / GIR_RootConstrainSelectedInstOperands,
7205	/ 18947 / // GIR_Coverage, 2330,
7206	/ 18947 / GIR_EraseRootFromParent_Done,
7207	/ 18948 / // Label 683: @18948
7208	/ 18948 / GIM_Try_CheckFeatures, /On fail goto//Label 684/ GIMT_Encode4(`18968`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2482 //
7209	/ 18955 / // (brcond GPR32:{ :[i32] }:$cond, (bb:{ :[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ :[i32] }:$cond, (bb:{ :[Other] }):$dst)
7210	/ 18955 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::BNEZC_MMR6),
7211	/ 18960 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
7212	/ 18966 / GIR_RootConstrainSelectedInstOperands,
7213	/ 18967 / // GIR_Coverage, 2482,
7214	/ 18967 / GIR_Done,
7215	/ 18968 / // Label 684: @18968
7216	/ 18968 / GIM_Reject,
7217	/ 18969 / // Label 682: @18969
7218	/ 18969 / GIM_Reject,
7219	/ 18970 / // Label 581: @18970
7220	/ 18970 / GIM_Try_CheckFeatures, /On fail goto//Label 685/ GIMT_Encode4(`19002`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1661 //
7221	/ 18977 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
7222	/ 18981 / // MIs[0] dst
7223	/ 18981 / GIM_CheckIsMBB, /MI/`0`, /Op/`1`,
7224	/ 18984 / // (brcond GPR64:{ :[i64] }:$cond, (bb:{ :[Other] }):$dst) => (BNE64 GPR64:{ :[i64] }:$cond, ZERO_64:{ :[i64] }, (bb:{ :[Other] }):$dst)*
7225	/ 18984 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BNE64),
7226	/ 18987 / GIR_RootToRootCopy, /OpIdx/`0`, // cond
7227	/ 18989 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO_64), /AddRegisterRegFlags/GIMT_Encode2(`0`),
7228	/ 18995 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
7229	/ 18997 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::AT/`0`,
7230	/ 19000 / GIR_RootConstrainSelectedInstOperands,
7231	/ 19001 / // GIR_Coverage, 1661,
7232	/ 19001 / GIR_EraseRootFromParent_Done,
7233	/ 19002 / // Label 685: @19002
7234	/ 19002 / GIM_Reject,
7235	/ 19003 / // Label 582: @19003
7236	/ 19003 / GIM_Reject,
7237	/ 19004 / // Label 29: @19004
7238	/ 19004 / GIM_Try, /On fail goto//Label 686/ GIMT_Encode4(`20938`),
7239	/ 19009 / GIM_CheckNumOperands, /MI/`0`, /Expected/`3`,
7240	/ 19012 / GIM_Try_CheckFeatures, /On fail goto//Label 687/ GIMT_Encode4(`19058`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 455 //
7241	/ 19019 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_qb),
7242	/ 19024 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
7243	/ 19027 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7244	/ 19030 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7245	/ 19034 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
7246	/ 19038 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7247	/ 19042 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7248	/ 19046 / // MIs[1] Operand 1
7249	/ 19046 / // No operand predicates
7250	/ 19046 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7251	/ 19048 / // (intrinsic_wo_chain:{ :[v4i8] } 8556:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ :[v4i8] } (imm:{ :[i32] }):$imm)*
7252	/ 19048 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPL_QB),
7253	/ 19051 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7254	/ 19053 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
7255	/ 19056 / GIR_RootConstrainSelectedInstOperands,
7256	/ 19057 / // GIR_Coverage, 455,
7257	/ 19057 / GIR_EraseRootFromParent_Done,
7258	/ 19058 / // Label 687: @19058
7259	/ 19058 / GIM_Try, /On fail goto//Label 688/ GIMT_Encode4(`19141`),
7260	/ 19063 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_ph),
7261	/ 19068 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7262	/ 19071 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7263	/ 19074 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7264	/ 19078 / GIM_Try_CheckFeatures, /On fail goto//Label 689/ GIMT_Encode4(`19109`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 456 //
7265	/ 19085 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
7266	/ 19089 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7267	/ 19093 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7268	/ 19097 / // MIs[1] Operand 1
7269	/ 19097 / // No operand predicates
7270	/ 19097 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7271	/ 19099 / // (intrinsic_wo_chain:{ :[v2i16] } 8555:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ :[v2i16] } (imm:{ :[i32] }):$imm)*
7272	/ 19099 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPL_PH),
7273	/ 19102 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7274	/ 19104 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
7275	/ 19107 / GIR_RootConstrainSelectedInstOperands,
7276	/ 19108 / // GIR_Coverage, 456,
7277	/ 19108 / GIR_EraseRootFromParent_Done,
7278	/ 19109 / // Label 689: @19109
7279	/ 19109 / GIM_Try_CheckFeatures, /On fail goto//Label 690/ GIMT_Encode4(`19140`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1309 //
7280	/ 19116 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
7281	/ 19120 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7282	/ 19124 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7283	/ 19128 / // MIs[1] Operand 1
7284	/ 19128 / // No operand predicates
7285	/ 19128 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7286	/ 19130 / // (intrinsic_wo_chain:{ :[v2i16] } 8555:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ :[v2i16] } (imm:{ :[i32] }):$imm)*
7287	/ 19130 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPL_PH_MM),
7288	/ 19133 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7289	/ 19135 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
7290	/ 19138 / GIR_RootConstrainSelectedInstOperands,
7291	/ 19139 / // GIR_Coverage, 1309,
7292	/ 19139 / GIR_EraseRootFromParent_Done,
7293	/ 19140 / // Label 690: @19140
7294	/ 19140 / GIM_Reject,
7295	/ 19141 / // Label 688: @19141
7296	/ 19141 / GIM_Try_CheckFeatures, /On fail goto//Label 691/ GIMT_Encode4(`19187`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1310 //
7297	/ 19148 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_qb),
7298	/ 19153 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
7299	/ 19156 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7300	/ 19159 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7301	/ 19163 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
7302	/ 19167 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7303	/ 19171 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7304	/ 19175 / // MIs[1] Operand 1
7305	/ 19175 / // No operand predicates
7306	/ 19175 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
7307	/ 19177 / // (intrinsic_wo_chain:{ :[v4i8] } 8556:{ :[iPTR] }, (imm:{ :[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ :[v4i8] } (imm:{ :[i32] }):$imm)*
7308	/ 19177 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPL_QB_MM),
7309	/ 19180 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7310	/ 19182 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
7311	/ 19185 / GIR_RootConstrainSelectedInstOperands,
7312	/ 19186 / // GIR_Coverage, 1310,
7313	/ 19186 / GIR_EraseRootFromParent_Done,
7314	/ 19187 / // Label 691: @19187
7315	/ 19187 / GIM_Try_CheckFeatures, /On fail goto//Label 692/ GIMT_Encode4(`19222`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 389 //
7316	/ 19194 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7317	/ 19199 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7318	/ 19202 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7319	/ 19205 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7320	/ 19209 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7321	/ 19213 / // (intrinsic_wo_chain:{ :[i32] } 8553:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (RADDU_W_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs)*
7322	/ 19213 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::RADDU_W_QB),
7323	/ 19216 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7324	/ 19218 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7325	/ 19220 / GIR_RootConstrainSelectedInstOperands,
7326	/ 19221 / // GIR_Coverage, 389,
7327	/ 19221 / GIR_EraseRootFromParent_Done,
7328	/ 19222 / // Label 692: @19222
7329	/ 19222 / GIM_Try_CheckFeatures, /On fail goto//Label 693/ GIMT_Encode4(`19257`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 396 //
7330	/ 19229 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7331	/ 19234 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7332	/ 19237 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
7333	/ 19240 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7334	/ 19244 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7335	/ 19248 / // (intrinsic_wo_chain:{ :[i32] } 8535:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt) => (PRECEQ_W_PHL:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rt)*
7336	/ 19248 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7337	/ 19251 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7338	/ 19253 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7339	/ 19255 / GIR_RootConstrainSelectedInstOperands,
7340	/ 19256 / // GIR_Coverage, 396,
7341	/ 19256 / GIR_EraseRootFromParent_Done,
7342	/ 19257 / // Label 693: @19257
7343	/ 19257 / GIM_Try_CheckFeatures, /On fail goto//Label 694/ GIMT_Encode4(`19292`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 397 //
7344	/ 19264 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7345	/ 19269 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7346	/ 19272 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
7347	/ 19275 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7348	/ 19279 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7349	/ 19283 / // (intrinsic_wo_chain:{ :[i32] } 8536:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt) => (PRECEQ_W_PHR:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rt)*
7350	/ 19283 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7351	/ 19286 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7352	/ 19288 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7353	/ 19290 / GIR_RootConstrainSelectedInstOperands,
7354	/ 19291 / // GIR_Coverage, 397,
7355	/ 19291 / GIR_EraseRootFromParent_Done,
7356	/ 19292 / // Label 694: @19292
7357	/ 19292 / GIM_Try_CheckFeatures, /On fail goto//Label 695/ GIMT_Encode4(`19327`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 398 //
7358	/ 19299 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7359	/ 19304 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7360	/ 19307 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7361	/ 19310 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7362	/ 19314 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7363	/ 19318 / // (intrinsic_wo_chain:{ :[v2i16] } 8537:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7364	/ 19318 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7365	/ 19321 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7366	/ 19323 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7367	/ 19325 / GIR_RootConstrainSelectedInstOperands,
7368	/ 19326 / // GIR_Coverage, 398,
7369	/ 19326 / GIR_EraseRootFromParent_Done,
7370	/ 19327 / // Label 695: @19327
7371	/ 19327 / GIM_Try_CheckFeatures, /On fail goto//Label 696/ GIMT_Encode4(`19362`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 399 //
7372	/ 19334 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7373	/ 19339 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7374	/ 19342 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7375	/ 19345 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7376	/ 19349 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7377	/ 19353 / // (intrinsic_wo_chain:{ :[v2i16] } 8539:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7378	/ 19353 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7379	/ 19356 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7380	/ 19358 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7381	/ 19360 / GIR_RootConstrainSelectedInstOperands,
7382	/ 19361 / // GIR_Coverage, 399,
7383	/ 19361 / GIR_EraseRootFromParent_Done,
7384	/ 19362 / // Label 696: @19362
7385	/ 19362 / GIM_Try_CheckFeatures, /On fail goto//Label 697/ GIMT_Encode4(`19397`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 400 //
7386	/ 19369 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7387	/ 19374 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7388	/ 19377 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7389	/ 19380 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7390	/ 19384 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7391	/ 19388 / // (intrinsic_wo_chain:{ :[v2i16] } 8538:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7392	/ 19388 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7393	/ 19391 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7394	/ 19393 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7395	/ 19395 / GIR_RootConstrainSelectedInstOperands,
7396	/ 19396 / // GIR_Coverage, 400,
7397	/ 19396 / GIR_EraseRootFromParent_Done,
7398	/ 19397 / // Label 697: @19397
7399	/ 19397 / GIM_Try_CheckFeatures, /On fail goto//Label 698/ GIMT_Encode4(`19432`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 401 //
7400	/ 19404 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7401	/ 19409 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7402	/ 19412 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7403	/ 19415 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7404	/ 19419 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7405	/ 19423 / // (intrinsic_wo_chain:{ :[v2i16] } 8540:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7406	/ 19423 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
7407	/ 19426 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7408	/ 19428 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7409	/ 19430 / GIR_RootConstrainSelectedInstOperands,
7410	/ 19431 / // GIR_Coverage, 401,
7411	/ 19431 / GIR_EraseRootFromParent_Done,
7412	/ 19432 / // Label 698: @19432
7413	/ 19432 / GIM_Try_CheckFeatures, /On fail goto//Label 699/ GIMT_Encode4(`19467`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 402 //
7414	/ 19439 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7415	/ 19444 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7416	/ 19447 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7417	/ 19450 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7418	/ 19454 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7419	/ 19458 / // (intrinsic_wo_chain:{ :[v2i16] } 8541:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEU_PH_QBL:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7420	/ 19458 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBL),
7421	/ 19461 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7422	/ 19463 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7423	/ 19465 / GIR_RootConstrainSelectedInstOperands,
7424	/ 19466 / // GIR_Coverage, 402,
7425	/ 19466 / GIR_EraseRootFromParent_Done,
7426	/ 19467 / // Label 699: @19467
7427	/ 19467 / GIM_Try_CheckFeatures, /On fail goto//Label 700/ GIMT_Encode4(`19502`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 403 //
7428	/ 19474 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7429	/ 19479 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7430	/ 19482 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7431	/ 19485 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7432	/ 19489 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7433	/ 19493 / // (intrinsic_wo_chain:{ :[v2i16] } 8543:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEU_PH_QBR:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7434	/ 19493 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBR),
7435	/ 19496 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7436	/ 19498 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7437	/ 19500 / GIR_RootConstrainSelectedInstOperands,
7438	/ 19501 / // GIR_Coverage, 403,
7439	/ 19501 / GIR_EraseRootFromParent_Done,
7440	/ 19502 / // Label 700: @19502
7441	/ 19502 / GIM_Try_CheckFeatures, /On fail goto//Label 701/ GIMT_Encode4(`19537`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 404 //
7442	/ 19509 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7443	/ 19514 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7444	/ 19517 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7445	/ 19520 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7446	/ 19524 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7447	/ 19528 / // (intrinsic_wo_chain:{ :[v2i16] } 8542:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7448	/ 19528 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
7449	/ 19531 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7450	/ 19533 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7451	/ 19535 / GIR_RootConstrainSelectedInstOperands,
7452	/ 19536 / // GIR_Coverage, 404,
7453	/ 19536 / GIR_EraseRootFromParent_Done,
7454	/ 19537 / // Label 701: @19537
7455	/ 19537 / GIM_Try_CheckFeatures, /On fail goto//Label 702/ GIMT_Encode4(`19572`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 405 //
7456	/ 19544 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7457	/ 19549 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7458	/ 19552 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7459	/ 19555 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7460	/ 19559 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7461	/ 19563 / // (intrinsic_wo_chain:{ :[v2i16] } 8544:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rt)*
7462	/ 19563 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
7463	/ 19566 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7464	/ 19568 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7465	/ 19570 / GIR_RootConstrainSelectedInstOperands,
7466	/ 19571 / // GIR_Coverage, 405,
7467	/ 19571 / GIR_EraseRootFromParent_Done,
7468	/ 19572 / // Label 702: @19572
7469	/ 19572 / GIM_Try_CheckFeatures, /On fail goto//Label 703/ GIMT_Encode4(`19607`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 453 //
7470	/ 19579 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_bitrev),
7471	/ 19584 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7472	/ 19587 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7473	/ 19590 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7474	/ 19594 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7475	/ 19598 / // (intrinsic_wo_chain:{ :[i32] } 8109:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt) => (BITREV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
7476	/ 19598 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BITREV),
7477	/ 19601 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7478	/ 19603 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7479	/ 19605 / GIR_RootConstrainSelectedInstOperands,
7480	/ 19606 / // GIR_Coverage, 453,
7481	/ 19606 / GIR_EraseRootFromParent_Done,
7482	/ 19607 / // Label 703: @19607
7483	/ 19607 / GIM_Try_CheckFeatures, /On fail goto//Label 704/ GIMT_Encode4(`19642`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 457 //
7484	/ 19614 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_qb),
7485	/ 19619 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
7486	/ 19622 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7487	/ 19625 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7488	/ 19629 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7489	/ 19633 / // (intrinsic_wo_chain:{ :[v4i8] } 8556:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt) => (REPLV_QB:{ :[v4i8] } GPR32Opnd:{ :[i32] }:$rt)*
7490	/ 19633 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPLV_QB),
7491	/ 19636 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7492	/ 19638 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7493	/ 19640 / GIR_RootConstrainSelectedInstOperands,
7494	/ 19641 / // GIR_Coverage, 457,
7495	/ 19641 / GIR_EraseRootFromParent_Done,
7496	/ 19642 / // Label 704: @19642
7497	/ 19642 / GIM_Try_CheckFeatures, /On fail goto//Label 705/ GIMT_Encode4(`19677`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 458 //
7498	/ 19649 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_ph),
7499	/ 19654 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7500	/ 19657 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7501	/ 19660 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7502	/ 19664 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7503	/ 19668 / // (intrinsic_wo_chain:{ :[v2i16] } 8555:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt) => (REPLV_PH:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rt)*
7504	/ 19668 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPLV_PH),
7505	/ 19671 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
7506	/ 19673 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
7507	/ 19675 / GIR_RootConstrainSelectedInstOperands,
7508	/ 19676 / // GIR_Coverage, 458,
7509	/ 19676 / GIR_EraseRootFromParent_Done,
7510	/ 19677 / // Label 705: @19677
7511	/ 19677 / GIM_Try_CheckFeatures, /On fail goto//Label 706/ GIMT_Encode4(`19712`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 707 //
7512	/ 19684 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fclass_w),
7513	/ 19689 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7514	/ 19692 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7515	/ 19695 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7516	/ 19699 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7517	/ 19703 / // (intrinsic_wo_chain:{ :[v4i32] } 8261:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FCLASS_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7518	/ 19703 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FCLASS_W),
7519	/ 19706 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7520	/ 19708 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7521	/ 19710 / GIR_RootConstrainSelectedInstOperands,
7522	/ 19711 / // GIR_Coverage, 707,
7523	/ 19711 / GIR_EraseRootFromParent_Done,
7524	/ 19712 / // Label 706: @19712
7525	/ 19712 / GIM_Try_CheckFeatures, /On fail goto//Label 707/ GIMT_Encode4(`19747`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 708 //
7526	/ 19719 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fclass_d),
7527	/ 19724 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7528	/ 19727 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7529	/ 19730 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7530	/ 19734 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7531	/ 19738 / // (intrinsic_wo_chain:{ :[v2i64] } 8260:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws) => (FCLASS_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws)*
7532	/ 19738 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FCLASS_D),
7533	/ 19741 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7534	/ 19743 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7535	/ 19745 / GIR_RootConstrainSelectedInstOperands,
7536	/ 19746 / // GIR_Coverage, 708,
7537	/ 19746 / GIR_EraseRootFromParent_Done,
7538	/ 19747 / // Label 707: @19747
7539	/ 19747 / GIM_Try_CheckFeatures, /On fail goto//Label 708/ GIMT_Encode4(`19782`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 731 //
7540	/ 19754 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexupl_w),
7541	/ 19759 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7542	/ 19762 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
7543	/ 19765 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7544	/ 19769 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7545	/ 19773 / // (intrinsic_wo_chain:{ :[v4f32] } 8287:{ :[iPTR] }, MSA128HOpnd:{ :[v8f16] }:$ws) => (FEXUPL_W:{ :[v4f32] } MSA128HOpnd:{ :[v8f16] }:$ws)*
7546	/ 19773 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXUPL_W),
7547	/ 19776 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7548	/ 19778 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7549	/ 19780 / GIR_RootConstrainSelectedInstOperands,
7550	/ 19781 / // GIR_Coverage, 731,
7551	/ 19781 / GIR_EraseRootFromParent_Done,
7552	/ 19782 / // Label 708: @19782
7553	/ 19782 / GIM_Try_CheckFeatures, /On fail goto//Label 709/ GIMT_Encode4(`19817`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 732 //
7554	/ 19789 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexupl_d),
7555	/ 19794 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7556	/ 19797 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7557	/ 19800 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7558	/ 19804 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7559	/ 19808 / // (intrinsic_wo_chain:{ :[v2f64] } 8286:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FEXUPL_D:{ :[v2f64] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7560	/ 19808 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXUPL_D),
7561	/ 19811 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7562	/ 19813 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7563	/ 19815 / GIR_RootConstrainSelectedInstOperands,
7564	/ 19816 / // GIR_Coverage, 732,
7565	/ 19816 / GIR_EraseRootFromParent_Done,
7566	/ 19817 / // Label 709: @19817
7567	/ 19817 / GIM_Try_CheckFeatures, /On fail goto//Label 710/ GIMT_Encode4(`19852`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 733 //
7568	/ 19824 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexupr_w),
7569	/ 19829 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7570	/ 19832 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
7571	/ 19835 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7572	/ 19839 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7573	/ 19843 / // (intrinsic_wo_chain:{ :[v4f32] } 8289:{ :[iPTR] }, MSA128HOpnd:{ :[v8f16] }:$ws) => (FEXUPR_W:{ :[v4f32] } MSA128HOpnd:{ :[v8f16] }:$ws)*
7574	/ 19843 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXUPR_W),
7575	/ 19846 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7576	/ 19848 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7577	/ 19850 / GIR_RootConstrainSelectedInstOperands,
7578	/ 19851 / // GIR_Coverage, 733,
7579	/ 19851 / GIR_EraseRootFromParent_Done,
7580	/ 19852 / // Label 710: @19852
7581	/ 19852 / GIM_Try_CheckFeatures, /On fail goto//Label 711/ GIMT_Encode4(`19887`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 734 //
7582	/ 19859 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexupr_d),
7583	/ 19864 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7584	/ 19867 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7585	/ 19870 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7586	/ 19874 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7587	/ 19878 / // (intrinsic_wo_chain:{ :[v2f64] } 8288:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FEXUPR_D:{ :[v2f64] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7588	/ 19878 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXUPR_D),
7589	/ 19881 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7590	/ 19883 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7591	/ 19885 / GIR_RootConstrainSelectedInstOperands,
7592	/ 19886 / // GIR_Coverage, 734,
7593	/ 19886 / GIR_EraseRootFromParent_Done,
7594	/ 19887 / // Label 711: @19887
7595	/ 19887 / GIM_Try_CheckFeatures, /On fail goto//Label 712/ GIMT_Encode4(`19922`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 739 //
7596	/ 19894 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ffql_w),
7597	/ 19899 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7598	/ 19902 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
7599	/ 19905 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7600	/ 19909 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7601	/ 19913 / // (intrinsic_wo_chain:{ :[v4f32] } 8295:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws) => (FFQL_W:{ :[v4f32] } MSA128HOpnd:{ :[v8i16] }:$ws)*
7602	/ 19913 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FFQL_W),
7603	/ 19916 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7604	/ 19918 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7605	/ 19920 / GIR_RootConstrainSelectedInstOperands,
7606	/ 19921 / // GIR_Coverage, 739,
7607	/ 19921 / GIR_EraseRootFromParent_Done,
7608	/ 19922 / // Label 712: @19922
7609	/ 19922 / GIM_Try_CheckFeatures, /On fail goto//Label 713/ GIMT_Encode4(`19957`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 740 //
7610	/ 19929 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ffql_d),
7611	/ 19934 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7612	/ 19937 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7613	/ 19940 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7614	/ 19944 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7615	/ 19948 / // (intrinsic_wo_chain:{ :[v2f64] } 8294:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws) => (FFQL_D:{ :[v2f64] } MSA128WOpnd:{ :[v4i32] }:$ws)*
7616	/ 19948 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FFQL_D),
7617	/ 19951 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7618	/ 19953 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7619	/ 19955 / GIR_RootConstrainSelectedInstOperands,
7620	/ 19956 / // GIR_Coverage, 740,
7621	/ 19956 / GIR_EraseRootFromParent_Done,
7622	/ 19957 / // Label 713: @19957
7623	/ 19957 / GIM_Try_CheckFeatures, /On fail goto//Label 714/ GIMT_Encode4(`19992`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 741 //
7624	/ 19964 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ffqr_w),
7625	/ 19969 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7626	/ 19972 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
7627	/ 19975 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7628	/ 19979 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7629	/ 19983 / // (intrinsic_wo_chain:{ :[v4f32] } 8297:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws) => (FFQR_W:{ :[v4f32] } MSA128HOpnd:{ :[v8i16] }:$ws)*
7630	/ 19983 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FFQR_W),
7631	/ 19986 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7632	/ 19988 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7633	/ 19990 / GIR_RootConstrainSelectedInstOperands,
7634	/ 19991 / // GIR_Coverage, 741,
7635	/ 19991 / GIR_EraseRootFromParent_Done,
7636	/ 19992 / // Label 714: @19992
7637	/ 19992 / GIM_Try_CheckFeatures, /On fail goto//Label 715/ GIMT_Encode4(`20027`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 742 //
7638	/ 19999 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ffqr_d),
7639	/ 20004 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7640	/ 20007 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7641	/ 20010 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7642	/ 20014 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7643	/ 20018 / // (intrinsic_wo_chain:{ :[v2f64] } 8296:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws) => (FFQR_D:{ :[v2f64] } MSA128WOpnd:{ :[v4i32] }:$ws)*
7644	/ 20018 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FFQR_D),
7645	/ 20021 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7646	/ 20023 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7647	/ 20025 / GIR_RootConstrainSelectedInstOperands,
7648	/ 20026 / // GIR_Coverage, 742,
7649	/ 20026 / GIR_EraseRootFromParent_Done,
7650	/ 20027 / // Label 715: @20027
7651	/ 20027 / GIM_Try_CheckFeatures, /On fail goto//Label 716/ GIMT_Encode4(`20062`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 767 //
7652	/ 20034 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_frcp_w),
7653	/ 20039 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7654	/ 20042 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7655	/ 20045 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7656	/ 20049 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7657	/ 20053 / // (intrinsic_wo_chain:{ :[v4f32] } 8319:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FRCP_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7658	/ 20053 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FRCP_W),
7659	/ 20056 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7660	/ 20058 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7661	/ 20060 / GIR_RootConstrainSelectedInstOperands,
7662	/ 20061 / // GIR_Coverage, 767,
7663	/ 20061 / GIR_EraseRootFromParent_Done,
7664	/ 20062 / // Label 716: @20062
7665	/ 20062 / GIM_Try_CheckFeatures, /On fail goto//Label 717/ GIMT_Encode4(`20097`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 768 //
7666	/ 20069 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_frcp_d),
7667	/ 20074 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7668	/ 20077 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7669	/ 20080 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7670	/ 20084 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7671	/ 20088 / // (intrinsic_wo_chain:{ :[v2f64] } 8318:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws) => (FRCP_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)*
7672	/ 20088 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FRCP_D),
7673	/ 20091 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7674	/ 20093 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7675	/ 20095 / GIR_RootConstrainSelectedInstOperands,
7676	/ 20096 / // GIR_Coverage, 768,
7677	/ 20096 / GIR_EraseRootFromParent_Done,
7678	/ 20097 / // Label 717: @20097
7679	/ 20097 / GIM_Try_CheckFeatures, /On fail goto//Label 718/ GIMT_Encode4(`20132`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 769 //
7680	/ 20104 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
7681	/ 20109 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7682	/ 20112 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7683	/ 20115 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7684	/ 20119 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7685	/ 20123 / // (intrinsic_wo_chain:{ :[v4f32] } 8323:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FRSQRT_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7686	/ 20123 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FRSQRT_W),
7687	/ 20126 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7688	/ 20128 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7689	/ 20130 / GIR_RootConstrainSelectedInstOperands,
7690	/ 20131 / // GIR_Coverage, 769,
7691	/ 20131 / GIR_EraseRootFromParent_Done,
7692	/ 20132 / // Label 718: @20132
7693	/ 20132 / GIM_Try_CheckFeatures, /On fail goto//Label 719/ GIMT_Encode4(`20167`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 770 //
7694	/ 20139 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
7695	/ 20144 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7696	/ 20147 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7697	/ 20150 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7698	/ 20154 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7699	/ 20158 / // (intrinsic_wo_chain:{ :[v2f64] } 8322:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws) => (FRSQRT_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)*
7700	/ 20158 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FRSQRT_D),
7701	/ 20161 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7702	/ 20163 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7703	/ 20165 / GIR_RootConstrainSelectedInstOperands,
7704	/ 20166 / // GIR_Coverage, 770,
7705	/ 20166 / GIR_EraseRootFromParent_Done,
7706	/ 20167 / // Label 719: @20167
7707	/ 20167 / GIM_Try_CheckFeatures, /On fail goto//Label 720/ GIMT_Encode4(`20202`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 797 //
7708	/ 20174 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
7709	/ 20179 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7710	/ 20182 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7711	/ 20185 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7712	/ 20189 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7713	/ 20193 / // (intrinsic_wo_chain:{ :[v4i32] } 8351:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FTINT_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7714	/ 20193 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTINT_S_W),
7715	/ 20196 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7716	/ 20198 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7717	/ 20200 / GIR_RootConstrainSelectedInstOperands,
7718	/ 20201 / // GIR_Coverage, 797,
7719	/ 20201 / GIR_EraseRootFromParent_Done,
7720	/ 20202 / // Label 720: @20202
7721	/ 20202 / GIM_Try_CheckFeatures, /On fail goto//Label 721/ GIMT_Encode4(`20237`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 798 //
7722	/ 20209 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
7723	/ 20214 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7724	/ 20217 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7725	/ 20220 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7726	/ 20224 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7727	/ 20228 / // (intrinsic_wo_chain:{ :[v2i64] } 8350:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws) => (FTINT_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws)*
7728	/ 20228 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTINT_S_D),
7729	/ 20231 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7730	/ 20233 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7731	/ 20235 / GIR_RootConstrainSelectedInstOperands,
7732	/ 20236 / // GIR_Coverage, 798,
7733	/ 20236 / GIR_EraseRootFromParent_Done,
7734	/ 20237 / // Label 721: @20237
7735	/ 20237 / GIM_Try_CheckFeatures, /On fail goto//Label 722/ GIMT_Encode4(`20272`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 799 //
7736	/ 20244 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
7737	/ 20249 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7738	/ 20252 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7739	/ 20255 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7740	/ 20259 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7741	/ 20263 / // (intrinsic_wo_chain:{ :[v4i32] } 8353:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws) => (FTINT_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws)*
7742	/ 20263 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTINT_U_W),
7743	/ 20266 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7744	/ 20268 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7745	/ 20270 / GIR_RootConstrainSelectedInstOperands,
7746	/ 20271 / // GIR_Coverage, 799,
7747	/ 20271 / GIR_EraseRootFromParent_Done,
7748	/ 20272 / // Label 722: @20272
7749	/ 20272 / GIM_Try_CheckFeatures, /On fail goto//Label 723/ GIMT_Encode4(`20307`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 800 //
7750	/ 20279 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
7751	/ 20284 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7752	/ 20287 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7753	/ 20290 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7754	/ 20294 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7755	/ 20298 / // (intrinsic_wo_chain:{ :[v2i64] } 8352:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws) => (FTINT_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws)*
7756	/ 20298 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTINT_U_D),
7757	/ 20301 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7758	/ 20303 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7759	/ 20305 / GIR_RootConstrainSelectedInstOperands,
7760	/ 20306 / // GIR_Coverage, 800,
7761	/ 20306 / GIR_EraseRootFromParent_Done,
7762	/ 20307 / // Label 723: @20307
7763	/ 20307 / GIM_Try_CheckFeatures, /On fail goto//Label 724/ GIMT_Encode4(`20342`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 935 //
7764	/ 20314 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_nloc_b),
7765	/ 20319 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
7766	/ 20322 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
7767	/ 20325 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
7768	/ 20329 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
7769	/ 20333 / // (intrinsic_wo_chain:{ :[v16i8] } 8508:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws) => (NLOC_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws)*
7770	/ 20333 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NLOC_B),
7771	/ 20336 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7772	/ 20338 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7773	/ 20340 / GIR_RootConstrainSelectedInstOperands,
7774	/ 20341 / // GIR_Coverage, 935,
7775	/ 20341 / GIR_EraseRootFromParent_Done,
7776	/ 20342 / // Label 724: @20342
7777	/ 20342 / GIM_Try_CheckFeatures, /On fail goto//Label 725/ GIMT_Encode4(`20377`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 936 //
7778	/ 20349 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_nloc_h),
7779	/ 20354 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
7780	/ 20357 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
7781	/ 20360 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7782	/ 20364 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
7783	/ 20368 / // (intrinsic_wo_chain:{ :[v8i16] } 8510:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws) => (NLOC_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws)*
7784	/ 20368 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NLOC_H),
7785	/ 20371 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7786	/ 20373 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7787	/ 20375 / GIR_RootConstrainSelectedInstOperands,
7788	/ 20376 / // GIR_Coverage, 936,
7789	/ 20376 / GIR_EraseRootFromParent_Done,
7790	/ 20377 / // Label 725: @20377
7791	/ 20377 / GIM_Try_CheckFeatures, /On fail goto//Label 726/ GIMT_Encode4(`20412`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 937 //
7792	/ 20384 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_nloc_w),
7793	/ 20389 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
7794	/ 20392 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
7795	/ 20395 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7796	/ 20399 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
7797	/ 20403 / // (intrinsic_wo_chain:{ :[v4i32] } 8511:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws) => (NLOC_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws)*
7798	/ 20403 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NLOC_W),
7799	/ 20406 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7800	/ 20408 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7801	/ 20410 / GIR_RootConstrainSelectedInstOperands,
7802	/ 20411 / // GIR_Coverage, 937,
7803	/ 20411 / GIR_EraseRootFromParent_Done,
7804	/ 20412 / // Label 726: @20412
7805	/ 20412 / GIM_Try_CheckFeatures, /On fail goto//Label 727/ GIMT_Encode4(`20447`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 938 //
7806	/ 20419 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_nloc_d),
7807	/ 20424 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
7808	/ 20427 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
7809	/ 20430 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7810	/ 20434 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
7811	/ 20438 / // (intrinsic_wo_chain:{ :[v2i64] } 8509:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws) => (NLOC_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws)*
7812	/ 20438 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::NLOC_D),
7813	/ 20441 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
7814	/ 20443 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
7815	/ 20445 / GIR_RootConstrainSelectedInstOperands,
7816	/ 20446 / // GIR_Coverage, 938,
7817	/ 20446 / GIR_EraseRootFromParent_Done,
7818	/ 20447 / // Label 727: @20447
7819	/ 20447 / GIM_Try_CheckFeatures, /On fail goto//Label 728/ GIMT_Encode4(`20482`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1272 //
7820	/ 20454 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7821	/ 20459 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7822	/ 20462 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
7823	/ 20465 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7824	/ 20469 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7825	/ 20473 / // (intrinsic_wo_chain:{ :[i32] } 8535:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs)*
7826	/ 20473 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
7827	/ 20476 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7828	/ 20478 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7829	/ 20480 / GIR_RootConstrainSelectedInstOperands,
7830	/ 20481 / // GIR_Coverage, 1272,
7831	/ 20481 / GIR_EraseRootFromParent_Done,
7832	/ 20482 / // Label 728: @20482
7833	/ 20482 / GIM_Try_CheckFeatures, /On fail goto//Label 729/ GIMT_Encode4(`20517`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1273 //
7834	/ 20489 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7835	/ 20494 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7836	/ 20497 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
7837	/ 20500 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7838	/ 20504 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7839	/ 20508 / // (intrinsic_wo_chain:{ :[i32] } 8536:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs)*
7840	/ 20508 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
7841	/ 20511 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7842	/ 20513 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7843	/ 20515 / GIR_RootConstrainSelectedInstOperands,
7844	/ 20516 / // GIR_Coverage, 1273,
7845	/ 20516 / GIR_EraseRootFromParent_Done,
7846	/ 20517 / // Label 729: @20517
7847	/ 20517 / GIM_Try_CheckFeatures, /On fail goto//Label 730/ GIMT_Encode4(`20552`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1274 //
7848	/ 20524 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7849	/ 20529 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7850	/ 20532 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7851	/ 20535 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7852	/ 20539 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7853	/ 20543 / // (intrinsic_wo_chain:{ :[v2i16] } 8537:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7854	/ 20543 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
7855	/ 20546 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7856	/ 20548 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7857	/ 20550 / GIR_RootConstrainSelectedInstOperands,
7858	/ 20551 / // GIR_Coverage, 1274,
7859	/ 20551 / GIR_EraseRootFromParent_Done,
7860	/ 20552 / // Label 730: @20552
7861	/ 20552 / GIM_Try_CheckFeatures, /On fail goto//Label 731/ GIMT_Encode4(`20587`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1275 //
7862	/ 20559 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7863	/ 20564 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7864	/ 20567 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7865	/ 20570 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7866	/ 20574 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7867	/ 20578 / // (intrinsic_wo_chain:{ :[v2i16] } 8538:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7868	/ 20578 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
7869	/ 20581 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7870	/ 20583 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7871	/ 20585 / GIR_RootConstrainSelectedInstOperands,
7872	/ 20586 / // GIR_Coverage, 1275,
7873	/ 20586 / GIR_EraseRootFromParent_Done,
7874	/ 20587 / // Label 731: @20587
7875	/ 20587 / GIM_Try_CheckFeatures, /On fail goto//Label 732/ GIMT_Encode4(`20622`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1276 //
7876	/ 20594 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7877	/ 20599 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7878	/ 20602 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7879	/ 20605 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7880	/ 20609 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7881	/ 20613 / // (intrinsic_wo_chain:{ :[v2i16] } 8539:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7882	/ 20613 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
7883	/ 20616 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7884	/ 20618 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7885	/ 20620 / GIR_RootConstrainSelectedInstOperands,
7886	/ 20621 / // GIR_Coverage, 1276,
7887	/ 20621 / GIR_EraseRootFromParent_Done,
7888	/ 20622 / // Label 732: @20622
7889	/ 20622 / GIM_Try_CheckFeatures, /On fail goto//Label 733/ GIMT_Encode4(`20657`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1277 //
7890	/ 20629 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7891	/ 20634 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7892	/ 20637 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7893	/ 20640 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7894	/ 20644 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7895	/ 20648 / // (intrinsic_wo_chain:{ :[v2i16] } 8540:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7896	/ 20648 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
7897	/ 20651 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7898	/ 20653 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7899	/ 20655 / GIR_RootConstrainSelectedInstOperands,
7900	/ 20656 / // GIR_Coverage, 1277,
7901	/ 20656 / GIR_EraseRootFromParent_Done,
7902	/ 20657 / // Label 733: @20657
7903	/ 20657 / GIM_Try_CheckFeatures, /On fail goto//Label 734/ GIMT_Encode4(`20692`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1278 //
7904	/ 20664 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7905	/ 20669 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7906	/ 20672 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7907	/ 20675 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7908	/ 20679 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7909	/ 20683 / // (intrinsic_wo_chain:{ :[v2i16] } 8541:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7910	/ 20683 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
7911	/ 20686 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7912	/ 20688 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7913	/ 20690 / GIR_RootConstrainSelectedInstOperands,
7914	/ 20691 / // GIR_Coverage, 1278,
7915	/ 20691 / GIR_EraseRootFromParent_Done,
7916	/ 20692 / // Label 734: @20692
7917	/ 20692 / GIM_Try_CheckFeatures, /On fail goto//Label 735/ GIMT_Encode4(`20727`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1279 //
7918	/ 20699 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7919	/ 20704 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7920	/ 20707 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7921	/ 20710 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7922	/ 20714 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7923	/ 20718 / // (intrinsic_wo_chain:{ :[v2i16] } 8542:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7924	/ 20718 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
7925	/ 20721 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7926	/ 20723 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7927	/ 20725 / GIR_RootConstrainSelectedInstOperands,
7928	/ 20726 / // GIR_Coverage, 1279,
7929	/ 20726 / GIR_EraseRootFromParent_Done,
7930	/ 20727 / // Label 735: @20727
7931	/ 20727 / GIM_Try_CheckFeatures, /On fail goto//Label 736/ GIMT_Encode4(`20762`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1280 //
7932	/ 20734 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7933	/ 20739 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7934	/ 20742 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7935	/ 20745 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7936	/ 20749 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7937	/ 20753 / // (intrinsic_wo_chain:{ :[v2i16] } 8543:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7938	/ 20753 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
7939	/ 20756 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7940	/ 20758 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7941	/ 20760 / GIR_RootConstrainSelectedInstOperands,
7942	/ 20761 / // GIR_Coverage, 1280,
7943	/ 20761 / GIR_EraseRootFromParent_Done,
7944	/ 20762 / // Label 736: @20762
7945	/ 20762 / GIM_Try_CheckFeatures, /On fail goto//Label 737/ GIMT_Encode4(`20797`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1281 //
7946	/ 20769 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7947	/ 20774 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7948	/ 20777 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7949	/ 20780 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7950	/ 20784 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7951	/ 20788 / // (intrinsic_wo_chain:{ :[v2i16] } 8544:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs)*
7952	/ 20788 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
7953	/ 20791 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7954	/ 20793 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7955	/ 20795 / GIR_RootConstrainSelectedInstOperands,
7956	/ 20796 / // GIR_Coverage, 1281,
7957	/ 20796 / GIR_EraseRootFromParent_Done,
7958	/ 20797 / // Label 737: @20797
7959	/ 20797 / GIM_Try_CheckFeatures, /On fail goto//Label 738/ GIMT_Encode4(`20832`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1307 //
7960	/ 20804 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7961	/ 20809 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
7962	/ 20812 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
7963	/ 20815 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7964	/ 20819 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7965	/ 20823 / // (intrinsic_wo_chain:{ :[i32] } 8553:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (RADDU_W_QB_MM:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs)*
7966	/ 20823 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::RADDU_W_QB_MM),
7967	/ 20826 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7968	/ 20828 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7969	/ 20830 / GIR_RootConstrainSelectedInstOperands,
7970	/ 20831 / // GIR_Coverage, 1307,
7971	/ 20831 / GIR_EraseRootFromParent_Done,
7972	/ 20832 / // Label 738: @20832
7973	/ 20832 / GIM_Try_CheckFeatures, /On fail goto//Label 739/ GIMT_Encode4(`20867`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1311 //
7974	/ 20839 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_ph),
7975	/ 20844 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
7976	/ 20847 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7977	/ 20850 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7978	/ 20854 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7979	/ 20858 / // (intrinsic_wo_chain:{ :[v2i16] } 8555:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs) => (REPLV_PH_MM:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs)*
7980	/ 20858 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPLV_PH_MM),
7981	/ 20861 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7982	/ 20863 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7983	/ 20865 / GIR_RootConstrainSelectedInstOperands,
7984	/ 20866 / // GIR_Coverage, 1311,
7985	/ 20866 / GIR_EraseRootFromParent_Done,
7986	/ 20867 / // Label 739: @20867
7987	/ 20867 / GIM_Try_CheckFeatures, /On fail goto//Label 740/ GIMT_Encode4(`20902`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1312 //
7988	/ 20874 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_repl_qb),
7989	/ 20879 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
7990	/ 20882 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
7991	/ 20885 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
7992	/ 20889 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
7993	/ 20893 / // (intrinsic_wo_chain:{ :[v4i8] } 8556:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs) => (REPLV_QB_MM:{ :[v4i8] } GPR32Opnd:{ :[i32] }:$rs)*
7994	/ 20893 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::REPLV_QB_MM),
7995	/ 20896 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
7996	/ 20898 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
7997	/ 20900 / GIR_RootConstrainSelectedInstOperands,
7998	/ 20901 / // GIR_Coverage, 1312,
7999	/ 20901 / GIR_EraseRootFromParent_Done,
8000	/ 20902 / // Label 740: @20902
8001	/ 20902 / GIM_Try_CheckFeatures, /On fail goto//Label 741/ GIMT_Encode4(`20937`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1322 //
8002	/ 20909 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_bitrev),
8003	/ 20914 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8004	/ 20917 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8005	/ 20920 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8006	/ 20924 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8007	/ 20928 / // (intrinsic_wo_chain:{ :[i32] } 8109:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs) => (BITREV_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)*
8008	/ 20928 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BITREV_MM),
8009	/ 20931 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
8010	/ 20933 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8011	/ 20935 / GIR_RootConstrainSelectedInstOperands,
8012	/ 20936 / // GIR_Coverage, 1322,
8013	/ 20936 / GIR_EraseRootFromParent_Done,
8014	/ 20937 / // Label 741: @20937
8015	/ 20937 / GIM_Reject,
8016	/ 20938 / // Label 686: @20938
8017	/ 20938 / GIM_Try, /On fail goto//Label 742/ GIMT_Encode4(`30477`),
8018	/ 20943 / GIM_CheckNumOperands, /MI/`0`, /Expected/`4`,
8019	/ 20946 / GIM_Try_CheckFeatures, /On fail goto//Label 743/ GIMT_Encode4(`20991`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 965 //
8020	/ 20953 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_s_b),
8021	/ 20958 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
8022	/ 20961 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
8023	/ 20964 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8024	/ 20968 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8025	/ 20972 / // MIs[0] m
8026	/ 20972 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8027	/ 20975 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8028	/* 20980 / // (intrinsic_wo_chain:{ :[v16i8] } 8557:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] }):$m)
8029	/ 20980 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_S_B),
8030	/ 20983 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8031	/ 20985 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8032	/ 20987 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8033	/ 20989 / GIR_RootConstrainSelectedInstOperands,
8034	/ 20990 / // GIR_Coverage, 965,
8035	/ 20990 / GIR_EraseRootFromParent_Done,
8036	/ 20991 / // Label 743: @20991
8037	/ 20991 / GIM_Try_CheckFeatures, /On fail goto//Label 744/ GIMT_Encode4(`21036`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 966 //
8038	/ 20998 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_s_h),
8039	/ 21003 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
8040	/ 21006 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
8041	/ 21009 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8042	/ 21013 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8043	/ 21017 / // MIs[0] m
8044	/ 21017 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8045	/ 21020 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8046	/* 21025 / // (intrinsic_wo_chain:{ :[v8i16] } 8559:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] }):$m)
8047	/ 21025 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_S_H),
8048	/ 21028 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8049	/ 21030 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8050	/ 21032 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8051	/ 21034 / GIR_RootConstrainSelectedInstOperands,
8052	/ 21035 / // GIR_Coverage, 966,
8053	/ 21035 / GIR_EraseRootFromParent_Done,
8054	/ 21036 / // Label 744: @21036
8055	/ 21036 / GIM_Try_CheckFeatures, /On fail goto//Label 745/ GIMT_Encode4(`21081`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 967 //
8056	/ 21043 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_s_w),
8057	/ 21048 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
8058	/ 21051 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
8059	/ 21054 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8060	/ 21058 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8061	/ 21062 / // MIs[0] m
8062	/ 21062 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8063	/ 21065 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8064	/* 21070 / // (intrinsic_wo_chain:{ :[v4i32] } 8560:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] }):$m)
8065	/ 21070 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_S_W),
8066	/ 21073 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8067	/ 21075 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8068	/ 21077 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8069	/ 21079 / GIR_RootConstrainSelectedInstOperands,
8070	/ 21080 / // GIR_Coverage, 967,
8071	/ 21080 / GIR_EraseRootFromParent_Done,
8072	/ 21081 / // Label 745: @21081
8073	/ 21081 / GIM_Try_CheckFeatures, /On fail goto//Label 746/ GIMT_Encode4(`21126`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 968 //
8074	/ 21088 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8075	/ 21093 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
8076	/ 21096 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
8077	/ 21099 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8078	/ 21103 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8079	/ 21107 / // MIs[0] m
8080	/ 21107 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8081	/ 21110 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8082	/* 21115 / // (intrinsic_wo_chain:{ :[v2i64] } 8558:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] }):$m)
8083	/ 21115 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_S_D),
8084	/ 21118 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8085	/ 21120 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8086	/ 21122 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8087	/ 21124 / GIR_RootConstrainSelectedInstOperands,
8088	/ 21125 / // GIR_Coverage, 968,
8089	/ 21125 / GIR_EraseRootFromParent_Done,
8090	/ 21126 / // Label 746: @21126
8091	/ 21126 / GIM_Try_CheckFeatures, /On fail goto//Label 747/ GIMT_Encode4(`21171`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 969 //
8092	/ 21133 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8093	/ 21138 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
8094	/ 21141 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
8095	/ 21144 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8096	/ 21148 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8097	/ 21152 / // MIs[0] m
8098	/ 21152 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8099	/ 21155 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8100	/* 21160 / // (intrinsic_wo_chain:{ :[v16i8] } 8561:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] }):$m)
8101	/ 21160 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_U_B),
8102	/ 21163 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8103	/ 21165 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8104	/ 21167 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8105	/ 21169 / GIR_RootConstrainSelectedInstOperands,
8106	/ 21170 / // GIR_Coverage, 969,
8107	/ 21170 / GIR_EraseRootFromParent_Done,
8108	/ 21171 / // Label 747: @21171
8109	/ 21171 / GIM_Try_CheckFeatures, /On fail goto//Label 748/ GIMT_Encode4(`21216`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 970 //
8110	/ 21178 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8111	/ 21183 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
8112	/ 21186 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
8113	/ 21189 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8114	/ 21193 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8115	/ 21197 / // MIs[0] m
8116	/ 21197 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8117	/ 21200 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8118	/* 21205 / // (intrinsic_wo_chain:{ :[v8i16] } 8563:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] }):$m)
8119	/ 21205 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_U_H),
8120	/ 21208 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8121	/ 21210 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8122	/ 21212 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8123	/ 21214 / GIR_RootConstrainSelectedInstOperands,
8124	/ 21215 / // GIR_Coverage, 970,
8125	/ 21215 / GIR_EraseRootFromParent_Done,
8126	/ 21216 / // Label 748: @21216
8127	/ 21216 / GIM_Try_CheckFeatures, /On fail goto//Label 749/ GIMT_Encode4(`21261`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 971 //
8128	/ 21223 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8129	/ 21228 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
8130	/ 21231 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
8131	/ 21234 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8132	/ 21238 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8133	/ 21242 / // MIs[0] m
8134	/ 21242 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8135	/ 21245 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8136	/* 21250 / // (intrinsic_wo_chain:{ :[v4i32] } 8564:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] }):$m)
8137	/ 21250 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_U_W),
8138	/ 21253 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8139	/ 21255 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8140	/ 21257 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8141	/ 21259 / GIR_RootConstrainSelectedInstOperands,
8142	/ 21260 / // GIR_Coverage, 971,
8143	/ 21260 / GIR_EraseRootFromParent_Done,
8144	/ 21261 / // Label 749: @21261
8145	/ 21261 / GIM_Try_CheckFeatures, /On fail goto//Label 750/ GIMT_Encode4(`21306`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 972 //
8146	/ 21268 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8147	/ 21273 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
8148	/ 21276 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
8149	/ 21279 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8150	/ 21283 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8151	/ 21287 / // MIs[0] m
8152	/ 21287 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8153	/ 21290 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8154	/* 21295 / // (intrinsic_wo_chain:{ :[v2i64] } 8562:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] }):$m)
8155	/ 21295 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SAT_U_D),
8156	/ 21298 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8157	/ 21300 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8158	/ 21302 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8159	/ 21304 / GIR_RootConstrainSelectedInstOperands,
8160	/ 21305 / // GIR_Coverage, 972,
8161	/ 21305 / GIR_EraseRootFromParent_Done,
8162	/ 21306 / // Label 750: @21306
8163	/ 21306 / GIM_Try_CheckFeatures, /On fail goto//Label 751/ GIMT_Encode4(`21351`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1012 //
8164	/ 21313 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srari_b),
8165	/ 21318 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
8166	/ 21321 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
8167	/ 21324 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8168	/ 21328 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8169	/ 21332 / // MIs[0] m
8170	/ 21332 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8171	/ 21335 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8172	/* 21340 / // (intrinsic_wo_chain:{ :[v16i8] } 8616:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] }):$m)
8173	/ 21340 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRARI_B),
8174	/ 21343 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8175	/ 21345 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8176	/ 21347 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8177	/ 21349 / GIR_RootConstrainSelectedInstOperands,
8178	/ 21350 / // GIR_Coverage, 1012,
8179	/ 21350 / GIR_EraseRootFromParent_Done,
8180	/ 21351 / // Label 751: @21351
8181	/ 21351 / GIM_Try_CheckFeatures, /On fail goto//Label 752/ GIMT_Encode4(`21396`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1013 //
8182	/ 21358 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srari_h),
8183	/ 21363 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
8184	/ 21366 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
8185	/ 21369 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8186	/ 21373 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8187	/ 21377 / // MIs[0] m
8188	/ 21377 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8189	/ 21380 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8190	/* 21385 / // (intrinsic_wo_chain:{ :[v8i16] } 8618:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] }):$m)
8191	/ 21385 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRARI_H),
8192	/ 21388 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8193	/ 21390 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8194	/ 21392 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8195	/ 21394 / GIR_RootConstrainSelectedInstOperands,
8196	/ 21395 / // GIR_Coverage, 1013,
8197	/ 21395 / GIR_EraseRootFromParent_Done,
8198	/ 21396 / // Label 752: @21396
8199	/ 21396 / GIM_Try_CheckFeatures, /On fail goto//Label 753/ GIMT_Encode4(`21441`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1014 //
8200	/ 21403 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srari_w),
8201	/ 21408 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
8202	/ 21411 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
8203	/ 21414 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8204	/ 21418 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8205	/ 21422 / // MIs[0] m
8206	/ 21422 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8207	/ 21425 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8208	/* 21430 / // (intrinsic_wo_chain:{ :[v4i32] } 8619:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] }):$m)
8209	/ 21430 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRARI_W),
8210	/ 21433 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8211	/ 21435 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8212	/ 21437 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8213	/ 21439 / GIR_RootConstrainSelectedInstOperands,
8214	/ 21440 / // GIR_Coverage, 1014,
8215	/ 21440 / GIR_EraseRootFromParent_Done,
8216	/ 21441 / // Label 753: @21441
8217	/ 21441 / GIM_Try_CheckFeatures, /On fail goto//Label 754/ GIMT_Encode4(`21486`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1015 //
8218	/ 21448 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srari_d),
8219	/ 21453 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
8220	/ 21456 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
8221	/ 21459 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8222	/ 21463 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8223	/ 21467 / // MIs[0] m
8224	/ 21467 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8225	/ 21470 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8226	/* 21475 / // (intrinsic_wo_chain:{ :[v2i64] } 8617:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] }):$m)
8227	/ 21475 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRARI_D),
8228	/ 21478 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8229	/ 21480 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8230	/ 21482 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8231	/ 21484 / GIR_RootConstrainSelectedInstOperands,
8232	/ 21485 / // GIR_Coverage, 1015,
8233	/ 21485 / GIR_EraseRootFromParent_Done,
8234	/ 21486 / // Label 754: @21486
8235	/ 21486 / GIM_Try_CheckFeatures, /On fail goto//Label 755/ GIMT_Encode4(`21531`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1028 //
8236	/ 21493 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlri_b),
8237	/ 21498 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
8238	/ 21501 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
8239	/ 21504 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8240	/ 21508 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8241	/ 21512 / // MIs[0] m
8242	/ 21512 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8243	/ 21515 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8244	/* 21520 / // (intrinsic_wo_chain:{ :[v16i8] } 8632:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] }):$m)
8245	/ 21520 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLRI_B),
8246	/ 21523 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8247	/ 21525 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8248	/ 21527 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8249	/ 21529 / GIR_RootConstrainSelectedInstOperands,
8250	/ 21530 / // GIR_Coverage, 1028,
8251	/ 21530 / GIR_EraseRootFromParent_Done,
8252	/ 21531 / // Label 755: @21531
8253	/ 21531 / GIM_Try_CheckFeatures, /On fail goto//Label 756/ GIMT_Encode4(`21576`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1029 //
8254	/ 21538 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlri_h),
8255	/ 21543 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
8256	/ 21546 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
8257	/ 21549 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8258	/ 21553 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
8259	/ 21557 / // MIs[0] m
8260	/ 21557 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8261	/ 21560 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8262	/* 21565 / // (intrinsic_wo_chain:{ :[v8i16] } 8634:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] }):$m)
8263	/ 21565 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLRI_H),
8264	/ 21568 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8265	/ 21570 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8266	/ 21572 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8267	/ 21574 / GIR_RootConstrainSelectedInstOperands,
8268	/ 21575 / // GIR_Coverage, 1029,
8269	/ 21575 / GIR_EraseRootFromParent_Done,
8270	/ 21576 / // Label 756: @21576
8271	/ 21576 / GIM_Try_CheckFeatures, /On fail goto//Label 757/ GIMT_Encode4(`21621`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1030 //
8272	/ 21583 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlri_w),
8273	/ 21588 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
8274	/ 21591 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
8275	/ 21594 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8276	/ 21598 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
8277	/ 21602 / // MIs[0] m
8278	/ 21602 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8279	/ 21605 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8280	/* 21610 / // (intrinsic_wo_chain:{ :[v4i32] } 8635:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] }):$m)
8281	/ 21610 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLRI_W),
8282	/ 21613 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8283	/ 21615 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8284	/ 21617 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8285	/ 21619 / GIR_RootConstrainSelectedInstOperands,
8286	/ 21620 / // GIR_Coverage, 1030,
8287	/ 21620 / GIR_EraseRootFromParent_Done,
8288	/ 21621 / // Label 757: @21621
8289	/ 21621 / GIM_Try_CheckFeatures, /On fail goto//Label 758/ GIMT_Encode4(`21666`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1031 //
8290	/ 21628 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlri_d),
8291	/ 21633 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
8292	/ 21636 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
8293	/ 21639 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8294	/ 21643 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
8295	/ 21647 / // MIs[0] m
8296	/ 21647 / GIM_CheckIsImm, /MI/`0`, /Op/`3`,
8297	/ 21650 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8298	/* 21655 / // (intrinsic_wo_chain:{ :[v2i64] } 8633:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] }):$m)
8299	/ 21655 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLRI_D),
8300	/ 21658 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8301	/ 21660 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8302	/ 21662 / GIR_RootToRootCopy, /OpIdx/`3`, // m
8303	/ 21664 / GIR_RootConstrainSelectedInstOperands,
8304	/ 21665 / // GIR_Coverage, 1031,
8305	/ 21665 / GIR_EraseRootFromParent_Done,
8306	/ 21666 / // Label 758: @21666
8307	/ 21666 / GIM_Try_CheckFeatures, /On fail goto//Label 759/ GIMT_Encode4(`21721`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 412 //
8308	/ 21673 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8309	/ 21678 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8310	/ 21681 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8311	/ 21684 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8312	/ 21687 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8313	/ 21691 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8314	/ 21695 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8315	/ 21699 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8316	/ 21703 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8317	/ 21707 / // MIs[1] Operand 1
8318	/ 21707 / // No operand predicates
8319	/ 21707 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8320	/* 21709 / // (intrinsic_wo_chain:{ :[v2i16] } 8575:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, (imm:{ :[i32] }):$rs_sa)
8321	/ 21709 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_PH),
8322	/ 21712 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8323	/ 21714 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8324	/ 21716 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // rs_sa
8325	/ 21719 / GIR_RootConstrainSelectedInstOperands,
8326	/ 21720 / // GIR_Coverage, 412,
8327	/ 21720 / GIR_EraseRootFromParent_Done,
8328	/ 21721 / // Label 759: @21721
8329	/ 21721 / GIM_Try_CheckFeatures, /On fail goto//Label 760/ GIMT_Encode4(`21776`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 416 //
8330	/ 21728 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8331	/ 21733 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8332	/ 21736 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8333	/ 21739 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8334	/ 21742 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8335	/ 21746 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8336	/ 21750 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8337	/ 21754 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8338	/ 21758 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8339	/ 21762 / // MIs[1] Operand 1
8340	/ 21762 / // No operand predicates
8341	/ 21762 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8342	/* 21764 / // (intrinsic_wo_chain:{ :[i32] } 8577:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$rs_sa)
8343	/ 21764 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_W),
8344	/ 21767 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8345	/ 21769 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8346	/ 21771 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // rs_sa
8347	/ 21774 / GIR_RootConstrainSelectedInstOperands,
8348	/ 21775 / // GIR_Coverage, 416,
8349	/ 21775 / GIR_EraseRootFromParent_Done,
8350	/ 21776 / // Label 760: @21776
8351	/ 21776 / GIM_Try_CheckFeatures, /On fail goto//Label 761/ GIMT_Encode4(`21831`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 507 //
8352	/ 21783 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8353	/ 21788 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8354	/ 21791 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8355	/ 21794 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8356	/ 21797 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8357	/ 21801 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8358	/ 21805 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8359	/ 21809 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8360	/ 21813 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8361	/ 21817 / // MIs[1] Operand 1
8362	/ 21817 / // No operand predicates
8363	/ 21817 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8364	/* 21819 / // (intrinsic_wo_chain:{ :[v4i8] } 8576:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, (imm:{ :[i32] }):$rs_sa)
8365	/ 21819 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_QB),
8366	/ 21822 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8367	/ 21824 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8368	/ 21826 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // rs_sa
8369	/ 21829 / GIR_RootConstrainSelectedInstOperands,
8370	/ 21830 / // GIR_Coverage, 507,
8371	/ 21830 / GIR_EraseRootFromParent_Done,
8372	/ 21831 / // Label 761: @21831
8373	/ 21831 / GIM_Try_CheckFeatures, /On fail goto//Label 762/ GIMT_Encode4(`21886`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1266 //
8374	/ 21838 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8375	/ 21843 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8376	/ 21846 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8377	/ 21849 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8378	/ 21852 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8379	/ 21856 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8380	/ 21860 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8381	/ 21864 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8382	/ 21868 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8383	/ 21872 / // MIs[1] Operand 1
8384	/ 21872 / // No operand predicates
8385	/ 21872 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8386	/* 21874 / // (intrinsic_wo_chain:{ :[v2i16] } 8575:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, (imm:{ :[i32] }):$sa)
8387	/ 21874 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_PH_MM),
8388	/ 21877 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
8389	/ 21879 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8390	/ 21881 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // sa
8391	/ 21884 / GIR_RootConstrainSelectedInstOperands,
8392	/ 21885 / // GIR_Coverage, 1266,
8393	/ 21885 / GIR_EraseRootFromParent_Done,
8394	/ 21886 / // Label 762: @21886
8395	/ 21886 / GIM_Try_CheckFeatures, /On fail goto//Label 763/ GIMT_Encode4(`21941`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1270 //
8396	/ 21893 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8397	/ 21898 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8398	/ 21901 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8399	/ 21904 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8400	/ 21907 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8401	/ 21911 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8402	/ 21915 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8403	/ 21919 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8404	/ 21923 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8405	/ 21927 / // MIs[1] Operand 1
8406	/ 21927 / // No operand predicates
8407	/ 21927 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8408	/* 21929 / // (intrinsic_wo_chain:{ :[i32] } 8577:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$sa)
8409	/ 21929 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_W_MM),
8410	/ 21932 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
8411	/ 21934 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8412	/ 21936 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // sa
8413	/ 21939 / GIR_RootConstrainSelectedInstOperands,
8414	/ 21940 / // GIR_Coverage, 1270,
8415	/ 21940 / GIR_EraseRootFromParent_Done,
8416	/ 21941 / // Label 763: @21941
8417	/ 21941 / GIM_Try_CheckFeatures, /On fail goto//Label 764/ GIMT_Encode4(`21996`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1345 //
8418	/ 21948 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8419	/ 21953 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8420	/ 21956 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8421	/ 21959 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8422	/ 21962 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8423	/ 21966 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8424	/ 21970 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8425	/ 21974 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8426	/ 21978 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8427	/ 21982 / // MIs[1] Operand 1
8428	/ 21982 / // No operand predicates
8429	/ 21982 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8430	/* 21984 / // (intrinsic_wo_chain:{ :[v4i8] } 8576:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, (imm:{ :[i32] }):$sa)
8431	/ 21984 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
8432	/ 21987 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
8433	/ 21989 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8434	/ 21991 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // sa
8435	/ 21994 / GIR_RootConstrainSelectedInstOperands,
8436	/ 21995 / // GIR_Coverage, 1345,
8437	/ 21995 / GIR_EraseRootFromParent_Done,
8438	/ 21996 / // Label 764: @21996
8439	/ 21996 / GIM_Try_CheckFeatures, /On fail goto//Label 765/ GIMT_Encode4(`22047`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2070 //
8440	/ 22003 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_ph),
8441	/ 22008 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8442	/ 22011 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8443	/ 22014 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8444	/ 22017 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8445	/ 22021 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8446	/ 22025 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8447	/ 22029 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8448	/ 22033 / // MIs[1] Operand 1
8449	/ 22033 / // No operand predicates
8450	/ 22033 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8451	/* 22035 / // (intrinsic_wo_chain:{ :[v2i16] } 8573:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt)
8452	/ 22035 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_PH),
8453	/ 22038 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8454	/ 22040 / GIR_RootToRootCopy, /OpIdx/`2`, // a
8455	/ 22042 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
8456	/ 22045 / GIR_RootConstrainSelectedInstOperands,
8457	/ 22046 / // GIR_Coverage, 2070,
8458	/ 22046 / GIR_EraseRootFromParent_Done,
8459	/ 22047 / // Label 765: @22047
8460	/ 22047 / GIM_Try_CheckFeatures, /On fail goto//Label 766/ GIMT_Encode4(`22098`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2071 //
8461	/ 22054 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8462	/ 22059 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8463	/ 22062 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8464	/ 22065 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8465	/ 22068 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8466	/ 22072 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8467	/ 22076 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8468	/ 22080 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8469	/ 22084 / // MIs[1] Operand 1
8470	/ 22084 / // No operand predicates
8471	/ 22084 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8472	/* 22086 / // (intrinsic_wo_chain:{ :[v2i16] } 8578:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt)
8473	/ 22086 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRL_PH),
8474	/ 22089 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8475	/ 22091 / GIR_RootToRootCopy, /OpIdx/`2`, // a
8476	/ 22093 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
8477	/ 22096 / GIR_RootConstrainSelectedInstOperands,
8478	/ 22097 / // GIR_Coverage, 2071,
8479	/ 22097 / GIR_EraseRootFromParent_Done,
8480	/ 22098 / // Label 766: @22098
8481	/ 22098 / GIM_Try_CheckFeatures, /On fail goto//Label 767/ GIMT_Encode4(`22149`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2076 //
8482	/ 22105 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_qb),
8483	/ 22110 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8484	/ 22113 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8485	/ 22116 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8486	/ 22119 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8487	/ 22123 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8488	/ 22127 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8489	/ 22131 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8490	/ 22135 / // MIs[1] Operand 1
8491	/ 22135 / // No operand predicates
8492	/ 22135 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8493	/* 22137 / // (intrinsic_wo_chain:{ :[v4i8] } 8574:{ :[iPTR] }, v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt)
8494	/ 22137 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRA_QB),
8495	/ 22140 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8496	/ 22142 / GIR_RootToRootCopy, /OpIdx/`2`, // a
8497	/ 22144 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
8498	/ 22147 / GIR_RootConstrainSelectedInstOperands,
8499	/ 22148 / // GIR_Coverage, 2076,
8500	/ 22148 / GIR_EraseRootFromParent_Done,
8501	/ 22149 / // Label 767: @22149
8502	/ 22149 / GIM_Try_CheckFeatures, /On fail goto//Label 768/ GIMT_Encode4(`22200`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2077 //
8503	/ 22156 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8504	/ 22161 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8505	/ 22164 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8506	/ 22167 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8507	/ 22170 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8508	/ 22174 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
8509	/ 22178 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8510	/ 22182 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8511	/ 22186 / // MIs[1] Operand 1
8512	/ 22186 / // No operand predicates
8513	/ 22186 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
8514	/* 22188 / // (intrinsic_wo_chain:{ :[v4i8] } 8579:{ :[iPTR] }, v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt)
8515	/ 22188 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRL_QB),
8516	/ 22191 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8517	/ 22193 / GIR_RootToRootCopy, /OpIdx/`2`, // a
8518	/ 22195 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
8519	/ 22198 / GIR_RootConstrainSelectedInstOperands,
8520	/ 22199 / // GIR_Coverage, 2077,
8521	/ 22199 / GIR_EraseRootFromParent_Done,
8522	/ 22200 / // Label 768: @22200
8523	/ 22200 / GIM_Try_CheckFeatures, /On fail goto//Label 769/ GIMT_Encode4(`22247`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 382 //
8524	/ 22207 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
8525	/ 22212 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8526	/ 22215 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8527	/ 22218 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8528	/ 22221 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8529	/ 22225 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8530	/ 22229 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8531	/* 22233 / // (intrinsic_wo_chain:{ :[v4i8] } 8045:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDU_S_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8532	/ 22233 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_S_QB),
8533	/ 22236 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8534	/ 22238 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8535	/ 22240 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8536	/ 22242 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
8537	/ 22245 / GIR_RootConstrainSelectedInstOperands,
8538	/ 22246 / // GIR_Coverage, 382,
8539	/ 22246 / GIR_EraseRootFromParent_Done,
8540	/ 22247 / // Label 769: @22247
8541	/ 22247 / GIM_Try_CheckFeatures, /On fail goto//Label 770/ GIMT_Encode4(`22294`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 383 //
8542	/ 22254 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
8543	/ 22259 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8544	/ 22262 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8545	/ 22265 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8546	/ 22268 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8547	/ 22272 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8548	/ 22276 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8549	/* 22280 / // (intrinsic_wo_chain:{ :[v4i8] } 8668:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBU_S_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8550	/ 22280 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_S_QB),
8551	/ 22283 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8552	/ 22285 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8553	/ 22287 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8554	/ 22289 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
8555	/ 22292 / GIR_RootConstrainSelectedInstOperands,
8556	/ 22293 / // GIR_Coverage, 383,
8557	/ 22293 / GIR_EraseRootFromParent_Done,
8558	/ 22294 / // Label 770: @22294
8559	/ 22294 / GIM_Try_CheckFeatures, /On fail goto//Label 771/ GIMT_Encode4(`22341`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 384 //
8560	/ 22301 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
8561	/ 22306 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8562	/ 22309 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8563	/ 22312 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8564	/ 22315 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8565	/ 22319 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8566	/ 22323 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8567	/* 22327 / // (intrinsic_wo_chain:{ :[v2i16] } 8023:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQ_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8568	/ 22327 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQ_S_PH),
8569	/ 22330 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8570	/ 22332 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8571	/ 22334 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8572	/ 22336 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
8573	/ 22339 / GIR_RootConstrainSelectedInstOperands,
8574	/ 22340 / // GIR_Coverage, 384,
8575	/ 22340 / GIR_EraseRootFromParent_Done,
8576	/ 22341 / // Label 771: @22341
8577	/ 22341 / GIM_Try_CheckFeatures, /On fail goto//Label 772/ GIMT_Encode4(`22388`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 385 //
8578	/ 22348 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
8579	/ 22353 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8580	/ 22356 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8581	/ 22359 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8582	/ 22362 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8583	/ 22366 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8584	/ 22370 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8585	/* 22374 / // (intrinsic_wo_chain:{ :[v2i16] } 8643:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQ_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8586	/ 22374 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQ_S_PH),
8587	/ 22377 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8588	/ 22379 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8589	/ 22381 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8590	/ 22383 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
8591	/ 22386 / GIR_RootConstrainSelectedInstOperands,
8592	/ 22387 / // GIR_Coverage, 385,
8593	/ 22387 / GIR_EraseRootFromParent_Done,
8594	/ 22388 / // Label 772: @22388
8595	/ 22388 / GIM_Try_CheckFeatures, /On fail goto//Label 773/ GIMT_Encode4(`22432`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 388 //
8596	/ 22395 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_modsub),
8597	/ 22400 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8598	/ 22403 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8599	/ 22406 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8600	/ 22409 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8601	/ 22413 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8602	/ 22417 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8603	/* 22421 / // (intrinsic_wo_chain:{ :[i32] } 8473:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MODSUB:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8604	/ 22421 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MODSUB),
8605	/ 22424 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8606	/ 22426 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8607	/ 22428 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8608	/ 22430 / GIR_RootConstrainSelectedInstOperands,
8609	/ 22431 / // GIR_Coverage, 388,
8610	/ 22431 / GIR_EraseRootFromParent_Done,
8611	/ 22432 / // Label 773: @22432
8612	/ 22432 / GIM_Try_CheckFeatures, /On fail goto//Label 774/ GIMT_Encode4(`22476`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 392 //
8613	/ 22439 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
8614	/ 22444 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8615	/ 22447 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8616	/ 22450 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8617	/ 22453 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8618	/ 22457 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8619	/ 22461 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8620	/* 22465 / // (intrinsic_wo_chain:{ :[v4i8] } 8549:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECRQ_QB_PH:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8621	/ 22465 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_QB_PH),
8622	/ 22468 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8623	/ 22470 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8624	/ 22472 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8625	/ 22474 / GIR_RootConstrainSelectedInstOperands,
8626	/ 22475 / // GIR_Coverage, 392,
8627	/ 22475 / GIR_EraseRootFromParent_Done,
8628	/ 22476 / // Label 774: @22476
8629	/ 22476 / GIM_Try_CheckFeatures, /On fail goto//Label 775/ GIMT_Encode4(`22520`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 393 //
8630	/ 22483 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
8631	/ 22488 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8632	/ 22491 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8633	/ 22494 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8634	/ 22497 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8635	/ 22501 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8636	/ 22505 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8637	/* 22509 / // (intrinsic_wo_chain:{ :[v2i16] } 8548:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (PRECRQ_PH_W:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8638	/ 22509 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_PH_W),
8639	/ 22512 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8640	/ 22514 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8641	/ 22516 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8642	/ 22518 / GIR_RootConstrainSelectedInstOperands,
8643	/ 22519 / // GIR_Coverage, 393,
8644	/ 22519 / GIR_EraseRootFromParent_Done,
8645	/ 22520 / // Label 775: @22520
8646	/ 22520 / GIM_Try_CheckFeatures, /On fail goto//Label 776/ GIMT_Encode4(`22564`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 407 //
8647	/ 22527 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8648	/ 22532 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8649	/ 22535 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8650	/ 22538 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8651	/ 22541 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8652	/ 22545 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8653	/ 22549 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8654	/* 22553 / // (intrinsic_wo_chain:{ :[v4i8] } 8579:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRLV_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8655	/ 22553 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRLV_QB),
8656	/ 22556 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8657	/ 22558 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8658	/ 22560 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8659	/ 22562 / GIR_RootConstrainSelectedInstOperands,
8660	/ 22563 / // GIR_Coverage, 407,
8661	/ 22563 / GIR_EraseRootFromParent_Done,
8662	/ 22564 / // Label 776: @22564
8663	/ 22564 / GIM_Try_CheckFeatures, /On fail goto//Label 777/ GIMT_Encode4(`22608`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 411 //
8664	/ 22571 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_ph),
8665	/ 22576 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8666	/ 22579 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8667	/ 22582 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8668	/ 22585 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8669	/ 22589 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8670	/ 22593 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8671	/* 22597 / // (intrinsic_wo_chain:{ :[v2i16] } 8573:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRAV_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8672	/ 22597 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_PH),
8673	/ 22600 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8674	/ 22602 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8675	/ 22604 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8676	/ 22606 / GIR_RootConstrainSelectedInstOperands,
8677	/ 22607 / // GIR_Coverage, 411,
8678	/ 22607 / GIR_EraseRootFromParent_Done,
8679	/ 22608 / // Label 777: @22608
8680	/ 22608 / GIM_Try_CheckFeatures, /On fail goto//Label 778/ GIMT_Encode4(`22652`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 413 //
8681	/ 22615 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8682	/ 22620 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8683	/ 22623 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8684	/ 22626 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8685	/ 22629 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8686	/ 22633 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8687	/ 22637 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8688	/* 22641 / // (intrinsic_wo_chain:{ :[v2i16] } 8575:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRAV_R_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8689	/ 22641 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_PH),
8690	/ 22644 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8691	/ 22646 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8692	/ 22648 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8693	/ 22650 / GIR_RootConstrainSelectedInstOperands,
8694	/ 22651 / // GIR_Coverage, 413,
8695	/ 22651 / GIR_EraseRootFromParent_Done,
8696	/ 22652 / // Label 778: @22652
8697	/ 22652 / GIM_Try_CheckFeatures, /On fail goto//Label 779/ GIMT_Encode4(`22696`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 417 //
8698	/ 22659 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8699	/ 22664 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8700	/ 22667 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8701	/ 22670 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8702	/ 22673 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8703	/ 22677 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8704	/ 22681 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8705	/* 22685 / // (intrinsic_wo_chain:{ :[i32] } 8577:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRAV_R_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8706	/ 22685 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_W),
8707	/ 22688 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8708	/ 22690 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8709	/ 22692 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8710	/ 22694 / GIR_RootConstrainSelectedInstOperands,
8711	/ 22695 / // GIR_Coverage, 417,
8712	/ 22695 / GIR_EraseRootFromParent_Done,
8713	/ 22696 / // Label 779: @22696
8714	/ 22696 / GIM_Try_CheckFeatures, /On fail goto//Label 780/ GIMT_Encode4(`22740`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 454 //
8715	/ 22703 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_packrl_ph),
8716	/ 22708 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8717	/ 22711 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8718	/ 22714 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8719	/ 22717 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8720	/ 22721 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8721	/ 22725 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8722	/* 22729 / // (intrinsic_wo_chain:{ :[v2i16] } 8520:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PACKRL_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8723	/ 22729 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PACKRL_PH),
8724	/ 22732 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8725	/ 22734 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8726	/ 22736 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8727	/ 22738 / GIR_RootConstrainSelectedInstOperands,
8728	/ 22739 / // GIR_Coverage, 454,
8729	/ 22739 / GIR_EraseRootFromParent_Done,
8730	/ 22740 / // Label 780: @22740
8731	/ 22740 / GIM_Try_CheckFeatures, /On fail goto//Label 781/ GIMT_Encode4(`22784`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 478 //
8732	/ 22747 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adduh_qb),
8733	/ 22752 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8734	/ 22755 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8735	/ 22758 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8736	/ 22761 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8737	/ 22765 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8738	/ 22769 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8739	/* 22773 / // (intrinsic_wo_chain:{ :[v4i8] } 8046:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDUH_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8740	/ 22773 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDUH_QB),
8741	/ 22776 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8742	/ 22778 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8743	/ 22780 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8744	/ 22782 / GIR_RootConstrainSelectedInstOperands,
8745	/ 22783 / // GIR_Coverage, 478,
8746	/ 22783 / GIR_EraseRootFromParent_Done,
8747	/ 22784 / // Label 781: @22784
8748	/ 22784 / GIM_Try_CheckFeatures, /On fail goto//Label 782/ GIMT_Encode4(`22828`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 479 //
8749	/ 22791 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
8750	/ 22796 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8751	/ 22799 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8752	/ 22802 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8753	/ 22805 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8754	/ 22809 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8755	/ 22813 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8756	/* 22817 / // (intrinsic_wo_chain:{ :[v4i8] } 8047:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDUH_R_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8757	/ 22817 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDUH_R_QB),
8758	/ 22820 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8759	/ 22822 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8760	/ 22824 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8761	/ 22826 / GIR_RootConstrainSelectedInstOperands,
8762	/ 22827 / // GIR_Coverage, 479,
8763	/ 22827 / GIR_EraseRootFromParent_Done,
8764	/ 22828 / // Label 782: @22828
8765	/ 22828 / GIM_Try_CheckFeatures, /On fail goto//Label 783/ GIMT_Encode4(`22872`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 480 //
8766	/ 22835 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subuh_qb),
8767	/ 22840 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8768	/ 22843 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8769	/ 22846 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8770	/ 22849 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8771	/ 22853 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8772	/ 22857 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8773	/* 22861 / // (intrinsic_wo_chain:{ :[v4i8] } 8669:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBUH_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8774	/ 22861 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBUH_QB),
8775	/ 22864 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8776	/ 22866 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8777	/ 22868 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8778	/ 22870 / GIR_RootConstrainSelectedInstOperands,
8779	/ 22871 / // GIR_Coverage, 480,
8780	/ 22871 / GIR_EraseRootFromParent_Done,
8781	/ 22872 / // Label 783: @22872
8782	/ 22872 / GIM_Try_CheckFeatures, /On fail goto//Label 784/ GIMT_Encode4(`22916`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 481 //
8783	/ 22879 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
8784	/ 22884 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8785	/ 22887 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8786	/ 22890 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
8787	/ 22893 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8788	/ 22897 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8789	/ 22901 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8790	/* 22905 / // (intrinsic_wo_chain:{ :[v4i8] } 8670:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBUH_R_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
8791	/ 22905 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBUH_R_QB),
8792	/ 22908 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8793	/ 22910 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8794	/ 22912 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8795	/ 22914 / GIR_RootConstrainSelectedInstOperands,
8796	/ 22915 / // GIR_Coverage, 481,
8797	/ 22915 / GIR_EraseRootFromParent_Done,
8798	/ 22916 / // Label 784: @22916
8799	/ 22916 / GIM_Try_CheckFeatures, /On fail goto//Label 785/ GIMT_Encode4(`22960`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 482 //
8800	/ 22923 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_ph),
8801	/ 22928 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8802	/ 22931 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8803	/ 22934 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8804	/ 22937 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8805	/ 22941 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8806	/ 22945 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8807	/* 22949 / // (intrinsic_wo_chain:{ :[v2i16] } 8025:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQH_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8808	/ 22949 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_PH),
8809	/ 22952 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8810	/ 22954 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8811	/ 22956 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8812	/ 22958 / GIR_RootConstrainSelectedInstOperands,
8813	/ 22959 / // GIR_Coverage, 482,
8814	/ 22959 / GIR_EraseRootFromParent_Done,
8815	/ 22960 / // Label 785: @22960
8816	/ 22960 / GIM_Try_CheckFeatures, /On fail goto//Label 786/ GIMT_Encode4(`23004`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 483 //
8817	/ 22967 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
8818	/ 22972 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8819	/ 22975 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8820	/ 22978 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8821	/ 22981 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8822	/ 22985 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8823	/ 22989 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8824	/* 22993 / // (intrinsic_wo_chain:{ :[v2i16] } 8026:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQH_R_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8825	/ 22993 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_R_PH),
8826	/ 22996 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8827	/ 22998 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8828	/ 23000 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8829	/ 23002 / GIR_RootConstrainSelectedInstOperands,
8830	/ 23003 / // GIR_Coverage, 483,
8831	/ 23003 / GIR_EraseRootFromParent_Done,
8832	/ 23004 / // Label 786: @23004
8833	/ 23004 / GIM_Try_CheckFeatures, /On fail goto//Label 787/ GIMT_Encode4(`23048`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 484 //
8834	/ 23011 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_ph),
8835	/ 23016 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8836	/ 23019 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8837	/ 23022 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8838	/ 23025 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8839	/ 23029 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8840	/ 23033 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8841	/* 23037 / // (intrinsic_wo_chain:{ :[v2i16] } 8645:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQH_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8842	/ 23037 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_PH),
8843	/ 23040 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8844	/ 23042 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8845	/ 23044 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8846	/ 23046 / GIR_RootConstrainSelectedInstOperands,
8847	/ 23047 / // GIR_Coverage, 484,
8848	/ 23047 / GIR_EraseRootFromParent_Done,
8849	/ 23048 / // Label 787: @23048
8850	/ 23048 / GIM_Try_CheckFeatures, /On fail goto//Label 788/ GIMT_Encode4(`23092`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 485 //
8851	/ 23055 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
8852	/ 23060 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8853	/ 23063 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8854	/ 23066 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
8855	/ 23069 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8856	/ 23073 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8857	/ 23077 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8858	/* 23081 / // (intrinsic_wo_chain:{ :[v2i16] } 8646:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQH_R_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
8859	/ 23081 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_R_PH),
8860	/ 23084 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8861	/ 23086 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8862	/ 23088 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8863	/ 23090 / GIR_RootConstrainSelectedInstOperands,
8864	/ 23091 / // GIR_Coverage, 485,
8865	/ 23091 / GIR_EraseRootFromParent_Done,
8866	/ 23092 / // Label 788: @23092
8867	/ 23092 / GIM_Try_CheckFeatures, /On fail goto//Label 789/ GIMT_Encode4(`23136`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 486 //
8868	/ 23099 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_w),
8869	/ 23104 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8870	/ 23107 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8871	/ 23110 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8872	/ 23113 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8873	/ 23117 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8874	/ 23121 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8875	/* 23125 / // (intrinsic_wo_chain:{ :[i32] } 8028:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQH_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8876	/ 23125 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_W),
8877	/ 23128 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8878	/ 23130 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8879	/ 23132 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8880	/ 23134 / GIR_RootConstrainSelectedInstOperands,
8881	/ 23135 / // GIR_Coverage, 486,
8882	/ 23135 / GIR_EraseRootFromParent_Done,
8883	/ 23136 / // Label 789: @23136
8884	/ 23136 / GIM_Try_CheckFeatures, /On fail goto//Label 790/ GIMT_Encode4(`23180`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 487 //
8885	/ 23143 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
8886	/ 23148 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8887	/ 23151 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8888	/ 23154 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8889	/ 23157 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8890	/ 23161 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8891	/ 23165 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8892	/* 23169 / // (intrinsic_wo_chain:{ :[i32] } 8027:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQH_R_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8893	/ 23169 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_R_W),
8894	/ 23172 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8895	/ 23174 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8896	/ 23176 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8897	/ 23178 / GIR_RootConstrainSelectedInstOperands,
8898	/ 23179 / // GIR_Coverage, 487,
8899	/ 23179 / GIR_EraseRootFromParent_Done,
8900	/ 23180 / // Label 790: @23180
8901	/ 23180 / GIM_Try_CheckFeatures, /On fail goto//Label 791/ GIMT_Encode4(`23224`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 488 //
8902	/ 23187 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_w),
8903	/ 23192 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8904	/ 23195 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8905	/ 23198 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8906	/ 23201 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8907	/ 23205 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8908	/ 23209 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8909	/* 23213 / // (intrinsic_wo_chain:{ :[i32] } 8648:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQH_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8910	/ 23213 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_W),
8911	/ 23216 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8912	/ 23218 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8913	/ 23220 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8914	/ 23222 / GIR_RootConstrainSelectedInstOperands,
8915	/ 23223 / // GIR_Coverage, 488,
8916	/ 23223 / GIR_EraseRootFromParent_Done,
8917	/ 23224 / // Label 791: @23224
8918	/ 23224 / GIM_Try_CheckFeatures, /On fail goto//Label 792/ GIMT_Encode4(`23268`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 489 //
8919	/ 23231 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
8920	/ 23236 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
8921	/ 23239 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
8922	/ 23242 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8923	/ 23245 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8924	/ 23249 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8925	/ 23253 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8926	/* 23257 / // (intrinsic_wo_chain:{ :[i32] } 8647:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQH_R_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
8927	/ 23257 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_R_W),
8928	/ 23260 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8929	/ 23262 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
8930	/ 23264 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
8931	/ 23266 / GIR_RootConstrainSelectedInstOperands,
8932	/ 23267 / // GIR_Coverage, 489,
8933	/ 23267 / GIR_EraseRootFromParent_Done,
8934	/ 23268 / // Label 792: @23268
8935	/ 23268 / GIM_Try_CheckFeatures, /On fail goto//Label 793/ GIMT_Encode4(`23312`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 506 //
8936	/ 23275 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_qb),
8937	/ 23280 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8938	/ 23283 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8939	/ 23286 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8940	/ 23289 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8941	/ 23293 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8942	/ 23297 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8943	/* 23301 / // (intrinsic_wo_chain:{ :[v4i8] } 8574:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRAV_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8944	/ 23301 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_QB),
8945	/ 23304 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8946	/ 23306 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8947	/ 23308 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8948	/ 23310 / GIR_RootConstrainSelectedInstOperands,
8949	/ 23311 / // GIR_Coverage, 506,
8950	/ 23311 / GIR_EraseRootFromParent_Done,
8951	/ 23312 / // Label 793: @23312
8952	/ 23312 / GIM_Try_CheckFeatures, /On fail goto//Label 794/ GIMT_Encode4(`23356`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 508 //
8953	/ 23319 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8954	/ 23324 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
8955	/ 23327 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
8956	/ 23330 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8957	/ 23333 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8958	/ 23337 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8959	/ 23341 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8960	/* 23345 / // (intrinsic_wo_chain:{ :[v4i8] } 8576:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRAV_R_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8961	/ 23345 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_QB),
8962	/ 23348 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8963	/ 23350 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8964	/ 23352 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8965	/ 23354 / GIR_RootConstrainSelectedInstOperands,
8966	/ 23355 / // GIR_Coverage, 508,
8967	/ 23355 / GIR_EraseRootFromParent_Done,
8968	/ 23356 / // Label 794: @23356
8969	/ 23356 / GIM_Try_CheckFeatures, /On fail goto//Label 795/ GIMT_Encode4(`23400`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 509 //
8970	/ 23363 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8971	/ 23368 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
8972	/ 23371 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
8973	/ 23374 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
8974	/ 23377 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8975	/ 23381 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
8976	/ 23385 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
8977	/* 23389 / // (intrinsic_wo_chain:{ :[v2i16] } 8578:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHRLV_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
8978	/ 23389 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRLV_PH),
8979	/ 23392 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
8980	/ 23394 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
8981	/ 23396 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
8982	/ 23398 / GIR_RootConstrainSelectedInstOperands,
8983	/ 23399 / // GIR_Coverage, 509,
8984	/ 23399 / GIR_EraseRootFromParent_Done,
8985	/ 23400 / // Label 795: @23400
8986	/ 23400 / GIM_Try_CheckFeatures, /On fail goto//Label 796/ GIMT_Encode4(`23444`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 518 //
8987	/ 23407 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_add_a_b),
8988	/ 23412 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
8989	/ 23415 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
8990	/ 23418 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
8991	/ 23421 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8992	/ 23425 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8993	/ 23429 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
8994	/* 23433 / // (intrinsic_wo_chain:{ :[v16i8] } 8018:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ADD_A_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
8995	/ 23433 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADD_A_B),
8996	/ 23436 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
8997	/ 23438 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
8998	/ 23440 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
8999	/ 23442 / GIR_RootConstrainSelectedInstOperands,
9000	/ 23443 / // GIR_Coverage, 518,
9001	/ 23443 / GIR_EraseRootFromParent_Done,
9002	/ 23444 / // Label 796: @23444
9003	/ 23444 / GIM_Try_CheckFeatures, /On fail goto//Label 797/ GIMT_Encode4(`23488`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 519 //
9004	/ 23451 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_add_a_h),
9005	/ 23456 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9006	/ 23459 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9007	/ 23462 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9008	/ 23465 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9009	/ 23469 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9010	/ 23473 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9011	/* 23477 / // (intrinsic_wo_chain:{ :[v8i16] } 8020:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ADD_A_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9012	/ 23477 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADD_A_H),
9013	/ 23480 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9014	/ 23482 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9015	/ 23484 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9016	/ 23486 / GIR_RootConstrainSelectedInstOperands,
9017	/ 23487 / // GIR_Coverage, 519,
9018	/ 23487 / GIR_EraseRootFromParent_Done,
9019	/ 23488 / // Label 797: @23488
9020	/ 23488 / GIM_Try_CheckFeatures, /On fail goto//Label 798/ GIMT_Encode4(`23532`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 520 //
9021	/ 23495 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_add_a_w),
9022	/ 23500 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9023	/ 23503 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9024	/ 23506 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9025	/ 23509 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9026	/ 23513 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9027	/ 23517 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9028	/* 23521 / // (intrinsic_wo_chain:{ :[v4i32] } 8021:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ADD_A_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9029	/ 23521 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADD_A_W),
9030	/ 23524 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9031	/ 23526 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9032	/ 23528 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9033	/ 23530 / GIR_RootConstrainSelectedInstOperands,
9034	/ 23531 / // GIR_Coverage, 520,
9035	/ 23531 / GIR_EraseRootFromParent_Done,
9036	/ 23532 / // Label 798: @23532
9037	/ 23532 / GIM_Try_CheckFeatures, /On fail goto//Label 799/ GIMT_Encode4(`23576`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 521 //
9038	/ 23539 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_add_a_d),
9039	/ 23544 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9040	/ 23547 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9041	/ 23550 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9042	/ 23553 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9043	/ 23557 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9044	/ 23561 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9045	/* 23565 / // (intrinsic_wo_chain:{ :[v2i64] } 8019:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ADD_A_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9046	/ 23565 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADD_A_D),
9047	/ 23568 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9048	/ 23570 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9049	/ 23572 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9050	/ 23574 / GIR_RootConstrainSelectedInstOperands,
9051	/ 23575 / // GIR_Coverage, 521,
9052	/ 23575 / GIR_EraseRootFromParent_Done,
9053	/ 23576 / // Label 799: @23576
9054	/ 23576 / GIM_Try_CheckFeatures, /On fail goto//Label 800/ GIMT_Encode4(`23620`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 522 //
9055	/ 23583 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9056	/ 23588 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9057	/ 23591 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9058	/ 23594 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9059	/ 23597 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9060	/ 23601 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9061	/ 23605 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9062	/* 23609 / // (intrinsic_wo_chain:{ :[v16i8] } 8029:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ADDS_A_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9063	/ 23609 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_A_B),
9064	/ 23612 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9065	/ 23614 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9066	/ 23616 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9067	/ 23618 / GIR_RootConstrainSelectedInstOperands,
9068	/ 23619 / // GIR_Coverage, 522,
9069	/ 23619 / GIR_EraseRootFromParent_Done,
9070	/ 23620 / // Label 800: @23620
9071	/ 23620 / GIM_Try_CheckFeatures, /On fail goto//Label 801/ GIMT_Encode4(`23664`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 523 //
9072	/ 23627 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9073	/ 23632 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9074	/ 23635 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9075	/ 23638 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9076	/ 23641 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9077	/ 23645 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9078	/ 23649 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9079	/* 23653 / // (intrinsic_wo_chain:{ :[v8i16] } 8031:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ADDS_A_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9080	/ 23653 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_A_H),
9081	/ 23656 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9082	/ 23658 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9083	/ 23660 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9084	/ 23662 / GIR_RootConstrainSelectedInstOperands,
9085	/ 23663 / // GIR_Coverage, 523,
9086	/ 23663 / GIR_EraseRootFromParent_Done,
9087	/ 23664 / // Label 801: @23664
9088	/ 23664 / GIM_Try_CheckFeatures, /On fail goto//Label 802/ GIMT_Encode4(`23708`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 524 //
9089	/ 23671 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9090	/ 23676 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9091	/ 23679 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9092	/ 23682 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9093	/ 23685 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9094	/ 23689 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9095	/ 23693 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9096	/* 23697 / // (intrinsic_wo_chain:{ :[v4i32] } 8032:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ADDS_A_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9097	/ 23697 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_A_W),
9098	/ 23700 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9099	/ 23702 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9100	/ 23704 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9101	/ 23706 / GIR_RootConstrainSelectedInstOperands,
9102	/ 23707 / // GIR_Coverage, 524,
9103	/ 23707 / GIR_EraseRootFromParent_Done,
9104	/ 23708 / // Label 802: @23708
9105	/ 23708 / GIM_Try_CheckFeatures, /On fail goto//Label 803/ GIMT_Encode4(`23752`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 525 //
9106	/ 23715 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9107	/ 23720 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9108	/ 23723 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9109	/ 23726 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9110	/ 23729 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9111	/ 23733 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9112	/ 23737 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9113	/* 23741 / // (intrinsic_wo_chain:{ :[v2i64] } 8030:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ADDS_A_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9114	/ 23741 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_A_D),
9115	/ 23744 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9116	/ 23746 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9117	/ 23748 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9118	/ 23750 / GIR_RootConstrainSelectedInstOperands,
9119	/ 23751 / // GIR_Coverage, 525,
9120	/ 23751 / GIR_EraseRootFromParent_Done,
9121	/ 23752 / // Label 803: @23752
9122	/ 23752 / GIM_Try_CheckFeatures, /On fail goto//Label 804/ GIMT_Encode4(`23796`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 526 //
9123	/ 23759 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9124	/ 23764 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9125	/ 23767 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9126	/ 23770 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9127	/ 23773 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9128	/ 23777 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9129	/ 23781 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9130	/* 23785 / // (intrinsic_wo_chain:{ :[v16i8] } 8033:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ADDS_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9131	/ 23785 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_S_B),
9132	/ 23788 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9133	/ 23790 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9134	/ 23792 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9135	/ 23794 / GIR_RootConstrainSelectedInstOperands,
9136	/ 23795 / // GIR_Coverage, 526,
9137	/ 23795 / GIR_EraseRootFromParent_Done,
9138	/ 23796 / // Label 804: @23796
9139	/ 23796 / GIM_Try_CheckFeatures, /On fail goto//Label 805/ GIMT_Encode4(`23840`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 527 //
9140	/ 23803 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9141	/ 23808 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9142	/ 23811 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9143	/ 23814 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9144	/ 23817 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9145	/ 23821 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9146	/ 23825 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9147	/* 23829 / // (intrinsic_wo_chain:{ :[v8i16] } 8035:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ADDS_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9148	/ 23829 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_S_H),
9149	/ 23832 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9150	/ 23834 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9151	/ 23836 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9152	/ 23838 / GIR_RootConstrainSelectedInstOperands,
9153	/ 23839 / // GIR_Coverage, 527,
9154	/ 23839 / GIR_EraseRootFromParent_Done,
9155	/ 23840 / // Label 805: @23840
9156	/ 23840 / GIM_Try_CheckFeatures, /On fail goto//Label 806/ GIMT_Encode4(`23884`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 528 //
9157	/ 23847 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9158	/ 23852 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9159	/ 23855 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9160	/ 23858 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9161	/ 23861 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9162	/ 23865 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9163	/ 23869 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9164	/* 23873 / // (intrinsic_wo_chain:{ :[v4i32] } 8036:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ADDS_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9165	/ 23873 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_S_W),
9166	/ 23876 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9167	/ 23878 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9168	/ 23880 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9169	/ 23882 / GIR_RootConstrainSelectedInstOperands,
9170	/ 23883 / // GIR_Coverage, 528,
9171	/ 23883 / GIR_EraseRootFromParent_Done,
9172	/ 23884 / // Label 806: @23884
9173	/ 23884 / GIM_Try_CheckFeatures, /On fail goto//Label 807/ GIMT_Encode4(`23928`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 529 //
9174	/ 23891 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9175	/ 23896 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9176	/ 23899 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9177	/ 23902 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9178	/ 23905 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9179	/ 23909 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9180	/ 23913 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9181	/* 23917 / // (intrinsic_wo_chain:{ :[v2i64] } 8034:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ADDS_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9182	/ 23917 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_S_D),
9183	/ 23920 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9184	/ 23922 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9185	/ 23924 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9186	/ 23926 / GIR_RootConstrainSelectedInstOperands,
9187	/ 23927 / // GIR_Coverage, 529,
9188	/ 23927 / GIR_EraseRootFromParent_Done,
9189	/ 23928 / // Label 807: @23928
9190	/ 23928 / GIM_Try_CheckFeatures, /On fail goto//Label 808/ GIMT_Encode4(`23972`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 530 //
9191	/ 23935 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9192	/ 23940 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9193	/ 23943 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9194	/ 23946 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9195	/ 23949 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9196	/ 23953 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9197	/ 23957 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9198	/* 23961 / // (intrinsic_wo_chain:{ :[v16i8] } 8037:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ADDS_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9199	/ 23961 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_U_B),
9200	/ 23964 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9201	/ 23966 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9202	/ 23968 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9203	/ 23970 / GIR_RootConstrainSelectedInstOperands,
9204	/ 23971 / // GIR_Coverage, 530,
9205	/ 23971 / GIR_EraseRootFromParent_Done,
9206	/ 23972 / // Label 808: @23972
9207	/ 23972 / GIM_Try_CheckFeatures, /On fail goto//Label 809/ GIMT_Encode4(`24016`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 531 //
9208	/ 23979 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9209	/ 23984 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9210	/ 23987 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9211	/ 23990 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9212	/ 23993 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9213	/ 23997 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9214	/ 24001 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9215	/* 24005 / // (intrinsic_wo_chain:{ :[v8i16] } 8039:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ADDS_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9216	/ 24005 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_U_H),
9217	/ 24008 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9218	/ 24010 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9219	/ 24012 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9220	/ 24014 / GIR_RootConstrainSelectedInstOperands,
9221	/ 24015 / // GIR_Coverage, 531,
9222	/ 24015 / GIR_EraseRootFromParent_Done,
9223	/ 24016 / // Label 809: @24016
9224	/ 24016 / GIM_Try_CheckFeatures, /On fail goto//Label 810/ GIMT_Encode4(`24060`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 532 //
9225	/ 24023 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9226	/ 24028 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9227	/ 24031 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9228	/ 24034 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9229	/ 24037 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9230	/ 24041 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9231	/ 24045 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9232	/* 24049 / // (intrinsic_wo_chain:{ :[v4i32] } 8040:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ADDS_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9233	/ 24049 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_U_W),
9234	/ 24052 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9235	/ 24054 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9236	/ 24056 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9237	/ 24058 / GIR_RootConstrainSelectedInstOperands,
9238	/ 24059 / // GIR_Coverage, 532,
9239	/ 24059 / GIR_EraseRootFromParent_Done,
9240	/ 24060 / // Label 810: @24060
9241	/ 24060 / GIM_Try_CheckFeatures, /On fail goto//Label 811/ GIMT_Encode4(`24104`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 533 //
9242	/ 24067 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9243	/ 24072 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9244	/ 24075 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9245	/ 24078 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9246	/ 24081 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9247	/ 24085 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9248	/ 24089 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9249	/* 24093 / // (intrinsic_wo_chain:{ :[v2i64] } 8038:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ADDS_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9250	/ 24093 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDS_U_D),
9251	/ 24096 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9252	/ 24098 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9253	/ 24100 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9254	/ 24102 / GIR_RootConstrainSelectedInstOperands,
9255	/ 24103 / // GIR_Coverage, 533,
9256	/ 24103 / GIR_EraseRootFromParent_Done,
9257	/ 24104 / // Label 811: @24104
9258	/ 24104 / GIM_Try_CheckFeatures, /On fail goto//Label 812/ GIMT_Encode4(`24148`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 547 //
9259	/ 24111 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9260	/ 24116 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9261	/ 24119 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9262	/ 24122 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9263	/ 24125 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9264	/ 24129 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9265	/ 24133 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9266	/* 24137 / // (intrinsic_wo_chain:{ :[v16i8] } 8060:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ASUB_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9267	/ 24137 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_S_B),
9268	/ 24140 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9269	/ 24142 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9270	/ 24144 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9271	/ 24146 / GIR_RootConstrainSelectedInstOperands,
9272	/ 24147 / // GIR_Coverage, 547,
9273	/ 24147 / GIR_EraseRootFromParent_Done,
9274	/ 24148 / // Label 812: @24148
9275	/ 24148 / GIM_Try_CheckFeatures, /On fail goto//Label 813/ GIMT_Encode4(`24192`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 548 //
9276	/ 24155 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9277	/ 24160 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9278	/ 24163 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9279	/ 24166 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9280	/ 24169 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9281	/ 24173 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9282	/ 24177 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9283	/* 24181 / // (intrinsic_wo_chain:{ :[v8i16] } 8062:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ASUB_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9284	/ 24181 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_S_H),
9285	/ 24184 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9286	/ 24186 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9287	/ 24188 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9288	/ 24190 / GIR_RootConstrainSelectedInstOperands,
9289	/ 24191 / // GIR_Coverage, 548,
9290	/ 24191 / GIR_EraseRootFromParent_Done,
9291	/ 24192 / // Label 813: @24192
9292	/ 24192 / GIM_Try_CheckFeatures, /On fail goto//Label 814/ GIMT_Encode4(`24236`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 549 //
9293	/ 24199 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_s_w),
9294	/ 24204 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9295	/ 24207 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9296	/ 24210 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9297	/ 24213 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9298	/ 24217 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9299	/ 24221 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9300	/* 24225 / // (intrinsic_wo_chain:{ :[v4i32] } 8063:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ASUB_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9301	/ 24225 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_S_W),
9302	/ 24228 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9303	/ 24230 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9304	/ 24232 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9305	/ 24234 / GIR_RootConstrainSelectedInstOperands,
9306	/ 24235 / // GIR_Coverage, 549,
9307	/ 24235 / GIR_EraseRootFromParent_Done,
9308	/ 24236 / // Label 814: @24236
9309	/ 24236 / GIM_Try_CheckFeatures, /On fail goto//Label 815/ GIMT_Encode4(`24280`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 550 //
9310	/ 24243 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_s_d),
9311	/ 24248 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9312	/ 24251 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9313	/ 24254 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9314	/ 24257 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9315	/ 24261 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9316	/ 24265 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9317	/* 24269 / // (intrinsic_wo_chain:{ :[v2i64] } 8061:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ASUB_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9318	/ 24269 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_S_D),
9319	/ 24272 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9320	/ 24274 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9321	/ 24276 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9322	/ 24278 / GIR_RootConstrainSelectedInstOperands,
9323	/ 24279 / // GIR_Coverage, 550,
9324	/ 24279 / GIR_EraseRootFromParent_Done,
9325	/ 24280 / // Label 815: @24280
9326	/ 24280 / GIM_Try_CheckFeatures, /On fail goto//Label 816/ GIMT_Encode4(`24324`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 551 //
9327	/ 24287 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_u_b),
9328	/ 24292 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9329	/ 24295 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9330	/ 24298 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9331	/ 24301 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9332	/ 24305 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9333	/ 24309 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9334	/* 24313 / // (intrinsic_wo_chain:{ :[v16i8] } 8064:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (ASUB_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9335	/ 24313 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_U_B),
9336	/ 24316 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9337	/ 24318 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9338	/ 24320 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9339	/ 24322 / GIR_RootConstrainSelectedInstOperands,
9340	/ 24323 / // GIR_Coverage, 551,
9341	/ 24323 / GIR_EraseRootFromParent_Done,
9342	/ 24324 / // Label 816: @24324
9343	/ 24324 / GIM_Try_CheckFeatures, /On fail goto//Label 817/ GIMT_Encode4(`24368`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 552 //
9344	/ 24331 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_u_h),
9345	/ 24336 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9346	/ 24339 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9347	/ 24342 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9348	/ 24345 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9349	/ 24349 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9350	/ 24353 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9351	/* 24357 / // (intrinsic_wo_chain:{ :[v8i16] } 8066:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (ASUB_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9352	/ 24357 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_U_H),
9353	/ 24360 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9354	/ 24362 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9355	/ 24364 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9356	/ 24366 / GIR_RootConstrainSelectedInstOperands,
9357	/ 24367 / // GIR_Coverage, 552,
9358	/ 24367 / GIR_EraseRootFromParent_Done,
9359	/ 24368 / // Label 817: @24368
9360	/ 24368 / GIM_Try_CheckFeatures, /On fail goto//Label 818/ GIMT_Encode4(`24412`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 553 //
9361	/ 24375 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_u_w),
9362	/ 24380 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9363	/ 24383 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9364	/ 24386 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9365	/ 24389 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9366	/ 24393 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9367	/ 24397 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9368	/* 24401 / // (intrinsic_wo_chain:{ :[v4i32] } 8067:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (ASUB_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9369	/ 24401 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_U_W),
9370	/ 24404 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9371	/ 24406 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9372	/ 24408 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9373	/ 24410 / GIR_RootConstrainSelectedInstOperands,
9374	/ 24411 / // GIR_Coverage, 553,
9375	/ 24411 / GIR_EraseRootFromParent_Done,
9376	/ 24412 / // Label 818: @24412
9377	/ 24412 / GIM_Try_CheckFeatures, /On fail goto//Label 819/ GIMT_Encode4(`24456`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 554 //
9378	/ 24419 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_asub_u_d),
9379	/ 24424 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9380	/ 24427 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9381	/ 24430 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9382	/ 24433 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9383	/ 24437 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9384	/ 24441 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9385	/* 24445 / // (intrinsic_wo_chain:{ :[v2i64] } 8065:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (ASUB_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9386	/ 24445 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ASUB_U_D),
9387	/ 24448 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9388	/ 24450 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9389	/ 24452 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9390	/ 24454 / GIR_RootConstrainSelectedInstOperands,
9391	/ 24455 / // GIR_Coverage, 554,
9392	/ 24455 / GIR_EraseRootFromParent_Done,
9393	/ 24456 / // Label 819: @24456
9394	/ 24456 / GIM_Try_CheckFeatures, /On fail goto//Label 820/ GIMT_Encode4(`24500`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 555 //
9395	/ 24463 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_s_b),
9396	/ 24468 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9397	/ 24471 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9398	/ 24474 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9399	/ 24477 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9400	/ 24481 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9401	/ 24485 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9402	/* 24489 / // (intrinsic_wo_chain:{ :[v16i8] } 8068:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (AVE_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9403	/ 24489 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_S_B),
9404	/ 24492 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9405	/ 24494 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9406	/ 24496 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9407	/ 24498 / GIR_RootConstrainSelectedInstOperands,
9408	/ 24499 / // GIR_Coverage, 555,
9409	/ 24499 / GIR_EraseRootFromParent_Done,
9410	/ 24500 / // Label 820: @24500
9411	/ 24500 / GIM_Try_CheckFeatures, /On fail goto//Label 821/ GIMT_Encode4(`24544`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 556 //
9412	/ 24507 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_s_h),
9413	/ 24512 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9414	/ 24515 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9415	/ 24518 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9416	/ 24521 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9417	/ 24525 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9418	/ 24529 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9419	/* 24533 / // (intrinsic_wo_chain:{ :[v8i16] } 8070:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (AVE_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9420	/ 24533 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_S_H),
9421	/ 24536 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9422	/ 24538 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9423	/ 24540 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9424	/ 24542 / GIR_RootConstrainSelectedInstOperands,
9425	/ 24543 / // GIR_Coverage, 556,
9426	/ 24543 / GIR_EraseRootFromParent_Done,
9427	/ 24544 / // Label 821: @24544
9428	/ 24544 / GIM_Try_CheckFeatures, /On fail goto//Label 822/ GIMT_Encode4(`24588`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 557 //
9429	/ 24551 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_s_w),
9430	/ 24556 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9431	/ 24559 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9432	/ 24562 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9433	/ 24565 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9434	/ 24569 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9435	/ 24573 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9436	/* 24577 / // (intrinsic_wo_chain:{ :[v4i32] } 8071:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (AVE_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9437	/ 24577 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_S_W),
9438	/ 24580 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9439	/ 24582 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9440	/ 24584 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9441	/ 24586 / GIR_RootConstrainSelectedInstOperands,
9442	/ 24587 / // GIR_Coverage, 557,
9443	/ 24587 / GIR_EraseRootFromParent_Done,
9444	/ 24588 / // Label 822: @24588
9445	/ 24588 / GIM_Try_CheckFeatures, /On fail goto//Label 823/ GIMT_Encode4(`24632`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 558 //
9446	/ 24595 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_s_d),
9447	/ 24600 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9448	/ 24603 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9449	/ 24606 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9450	/ 24609 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9451	/ 24613 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9452	/ 24617 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9453	/* 24621 / // (intrinsic_wo_chain:{ :[v2i64] } 8069:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (AVE_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9454	/ 24621 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_S_D),
9455	/ 24624 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9456	/ 24626 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9457	/ 24628 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9458	/ 24630 / GIR_RootConstrainSelectedInstOperands,
9459	/ 24631 / // GIR_Coverage, 558,
9460	/ 24631 / GIR_EraseRootFromParent_Done,
9461	/ 24632 / // Label 823: @24632
9462	/ 24632 / GIM_Try_CheckFeatures, /On fail goto//Label 824/ GIMT_Encode4(`24676`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 559 //
9463	/ 24639 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_u_b),
9464	/ 24644 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9465	/ 24647 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9466	/ 24650 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9467	/ 24653 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9468	/ 24657 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9469	/ 24661 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9470	/* 24665 / // (intrinsic_wo_chain:{ :[v16i8] } 8072:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (AVE_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9471	/ 24665 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_U_B),
9472	/ 24668 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9473	/ 24670 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9474	/ 24672 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9475	/ 24674 / GIR_RootConstrainSelectedInstOperands,
9476	/ 24675 / // GIR_Coverage, 559,
9477	/ 24675 / GIR_EraseRootFromParent_Done,
9478	/ 24676 / // Label 824: @24676
9479	/ 24676 / GIM_Try_CheckFeatures, /On fail goto//Label 825/ GIMT_Encode4(`24720`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 560 //
9480	/ 24683 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_u_h),
9481	/ 24688 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9482	/ 24691 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9483	/ 24694 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9484	/ 24697 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9485	/ 24701 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9486	/ 24705 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9487	/* 24709 / // (intrinsic_wo_chain:{ :[v8i16] } 8074:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (AVE_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9488	/ 24709 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_U_H),
9489	/ 24712 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9490	/ 24714 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9491	/ 24716 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9492	/ 24718 / GIR_RootConstrainSelectedInstOperands,
9493	/ 24719 / // GIR_Coverage, 560,
9494	/ 24719 / GIR_EraseRootFromParent_Done,
9495	/ 24720 / // Label 825: @24720
9496	/ 24720 / GIM_Try_CheckFeatures, /On fail goto//Label 826/ GIMT_Encode4(`24764`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 561 //
9497	/ 24727 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_u_w),
9498	/ 24732 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9499	/ 24735 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9500	/ 24738 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9501	/ 24741 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9502	/ 24745 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9503	/ 24749 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9504	/* 24753 / // (intrinsic_wo_chain:{ :[v4i32] } 8075:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (AVE_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9505	/ 24753 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_U_W),
9506	/ 24756 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9507	/ 24758 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9508	/ 24760 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9509	/ 24762 / GIR_RootConstrainSelectedInstOperands,
9510	/ 24763 / // GIR_Coverage, 561,
9511	/ 24763 / GIR_EraseRootFromParent_Done,
9512	/ 24764 / // Label 826: @24764
9513	/ 24764 / GIM_Try_CheckFeatures, /On fail goto//Label 827/ GIMT_Encode4(`24808`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 562 //
9514	/ 24771 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ave_u_d),
9515	/ 24776 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9516	/ 24779 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9517	/ 24782 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9518	/ 24785 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9519	/ 24789 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9520	/ 24793 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9521	/* 24797 / // (intrinsic_wo_chain:{ :[v2i64] } 8073:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (AVE_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9522	/ 24797 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVE_U_D),
9523	/ 24800 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9524	/ 24802 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9525	/ 24804 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9526	/ 24806 / GIR_RootConstrainSelectedInstOperands,
9527	/ 24807 / // GIR_Coverage, 562,
9528	/ 24807 / GIR_EraseRootFromParent_Done,
9529	/ 24808 / // Label 827: @24808
9530	/ 24808 / GIM_Try_CheckFeatures, /On fail goto//Label 828/ GIMT_Encode4(`24852`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 563 //
9531	/ 24815 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_s_b),
9532	/ 24820 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9533	/ 24823 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9534	/ 24826 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9535	/ 24829 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9536	/ 24833 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9537	/ 24837 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9538	/* 24841 / // (intrinsic_wo_chain:{ :[v16i8] } 8076:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (AVER_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9539	/ 24841 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_S_B),
9540	/ 24844 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9541	/ 24846 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9542	/ 24848 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9543	/ 24850 / GIR_RootConstrainSelectedInstOperands,
9544	/ 24851 / // GIR_Coverage, 563,
9545	/ 24851 / GIR_EraseRootFromParent_Done,
9546	/ 24852 / // Label 828: @24852
9547	/ 24852 / GIM_Try_CheckFeatures, /On fail goto//Label 829/ GIMT_Encode4(`24896`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 564 //
9548	/ 24859 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_s_h),
9549	/ 24864 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9550	/ 24867 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9551	/ 24870 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9552	/ 24873 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9553	/ 24877 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9554	/ 24881 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9555	/* 24885 / // (intrinsic_wo_chain:{ :[v8i16] } 8078:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (AVER_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9556	/ 24885 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_S_H),
9557	/ 24888 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9558	/ 24890 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9559	/ 24892 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9560	/ 24894 / GIR_RootConstrainSelectedInstOperands,
9561	/ 24895 / // GIR_Coverage, 564,
9562	/ 24895 / GIR_EraseRootFromParent_Done,
9563	/ 24896 / // Label 829: @24896
9564	/ 24896 / GIM_Try_CheckFeatures, /On fail goto//Label 830/ GIMT_Encode4(`24940`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 565 //
9565	/ 24903 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_s_w),
9566	/ 24908 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9567	/ 24911 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9568	/ 24914 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9569	/ 24917 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9570	/ 24921 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9571	/ 24925 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9572	/* 24929 / // (intrinsic_wo_chain:{ :[v4i32] } 8079:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (AVER_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9573	/ 24929 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_S_W),
9574	/ 24932 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9575	/ 24934 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9576	/ 24936 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9577	/ 24938 / GIR_RootConstrainSelectedInstOperands,
9578	/ 24939 / // GIR_Coverage, 565,
9579	/ 24939 / GIR_EraseRootFromParent_Done,
9580	/ 24940 / // Label 830: @24940
9581	/ 24940 / GIM_Try_CheckFeatures, /On fail goto//Label 831/ GIMT_Encode4(`24984`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 566 //
9582	/ 24947 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_s_d),
9583	/ 24952 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9584	/ 24955 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9585	/ 24958 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9586	/ 24961 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9587	/ 24965 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9588	/ 24969 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9589	/* 24973 / // (intrinsic_wo_chain:{ :[v2i64] } 8077:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (AVER_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9590	/ 24973 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_S_D),
9591	/ 24976 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9592	/ 24978 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9593	/ 24980 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9594	/ 24982 / GIR_RootConstrainSelectedInstOperands,
9595	/ 24983 / // GIR_Coverage, 566,
9596	/ 24983 / GIR_EraseRootFromParent_Done,
9597	/ 24984 / // Label 831: @24984
9598	/ 24984 / GIM_Try_CheckFeatures, /On fail goto//Label 832/ GIMT_Encode4(`25028`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 567 //
9599	/ 24991 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_u_b),
9600	/ 24996 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
9601	/ 24999 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9602	/ 25002 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9603	/ 25005 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9604	/ 25009 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9605	/ 25013 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9606	/* 25017 / // (intrinsic_wo_chain:{ :[v16i8] } 8080:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (AVER_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9607	/ 25017 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_U_B),
9608	/ 25020 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9609	/ 25022 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9610	/ 25024 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9611	/ 25026 / GIR_RootConstrainSelectedInstOperands,
9612	/ 25027 / // GIR_Coverage, 567,
9613	/ 25027 / GIR_EraseRootFromParent_Done,
9614	/ 25028 / // Label 832: @25028
9615	/ 25028 / GIM_Try_CheckFeatures, /On fail goto//Label 833/ GIMT_Encode4(`25072`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 568 //
9616	/ 25035 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_u_h),
9617	/ 25040 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9618	/ 25043 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9619	/ 25046 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9620	/ 25049 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9621	/ 25053 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9622	/ 25057 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9623	/* 25061 / // (intrinsic_wo_chain:{ :[v8i16] } 8082:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (AVER_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9624	/ 25061 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_U_H),
9625	/ 25064 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9626	/ 25066 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9627	/ 25068 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9628	/ 25070 / GIR_RootConstrainSelectedInstOperands,
9629	/ 25071 / // GIR_Coverage, 568,
9630	/ 25071 / GIR_EraseRootFromParent_Done,
9631	/ 25072 / // Label 833: @25072
9632	/ 25072 / GIM_Try_CheckFeatures, /On fail goto//Label 834/ GIMT_Encode4(`25116`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 569 //
9633	/ 25079 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_u_w),
9634	/ 25084 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9635	/ 25087 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9636	/ 25090 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9637	/ 25093 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9638	/ 25097 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9639	/ 25101 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9640	/* 25105 / // (intrinsic_wo_chain:{ :[v4i32] } 8083:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (AVER_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9641	/ 25105 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_U_W),
9642	/ 25108 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9643	/ 25110 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9644	/ 25112 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9645	/ 25114 / GIR_RootConstrainSelectedInstOperands,
9646	/ 25115 / // GIR_Coverage, 569,
9647	/ 25115 / GIR_EraseRootFromParent_Done,
9648	/ 25116 / // Label 834: @25116
9649	/ 25116 / GIM_Try_CheckFeatures, /On fail goto//Label 835/ GIMT_Encode4(`25160`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 570 //
9650	/ 25123 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_aver_u_d),
9651	/ 25128 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9652	/ 25131 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9653	/ 25134 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9654	/ 25137 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9655	/ 25141 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9656	/ 25145 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9657	/* 25149 / // (intrinsic_wo_chain:{ :[v2i64] } 8081:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (AVER_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
9658	/ 25149 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::AVER_U_D),
9659	/ 25152 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9660	/ 25154 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9661	/ 25156 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9662	/ 25158 / GIR_RootConstrainSelectedInstOperands,
9663	/ 25159 / // GIR_Coverage, 570,
9664	/ 25159 / GIR_EraseRootFromParent_Done,
9665	/ 25160 / // Label 835: @25160
9666	/ 25160 / GIM_Try_CheckFeatures, /On fail goto//Label 836/ GIMT_Encode4(`25204`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 679 //
9667	/ 25167 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
9668	/ 25172 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9669	/ 25175 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9670	/ 25178 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9671	/ 25181 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9672	/ 25185 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9673	/ 25189 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9674	/* 25193 / // (intrinsic_wo_chain:{ :[v8i16] } 8215:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DOTP_S_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9675	/ 25193 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_S_H),
9676	/ 25196 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9677	/ 25198 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9678	/ 25200 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9679	/ 25202 / GIR_RootConstrainSelectedInstOperands,
9680	/ 25203 / // GIR_Coverage, 679,
9681	/ 25203 / GIR_EraseRootFromParent_Done,
9682	/ 25204 / // Label 836: @25204
9683	/ 25204 / GIM_Try_CheckFeatures, /On fail goto//Label 837/ GIMT_Encode4(`25248`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 680 //
9684	/ 25211 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
9685	/ 25216 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9686	/ 25219 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9687	/ 25222 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9688	/ 25225 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9689	/ 25229 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9690	/ 25233 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9691	/* 25237 / // (intrinsic_wo_chain:{ :[v4i32] } 8216:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DOTP_S_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9692	/ 25237 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_S_W),
9693	/ 25240 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9694	/ 25242 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9695	/ 25244 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9696	/ 25246 / GIR_RootConstrainSelectedInstOperands,
9697	/ 25247 / // GIR_Coverage, 680,
9698	/ 25247 / GIR_EraseRootFromParent_Done,
9699	/ 25248 / // Label 837: @25248
9700	/ 25248 / GIM_Try_CheckFeatures, /On fail goto//Label 838/ GIMT_Encode4(`25292`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 681 //
9701	/ 25255 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
9702	/ 25260 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9703	/ 25263 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9704	/ 25266 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9705	/ 25269 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9706	/ 25273 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9707	/ 25277 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9708	/* 25281 / // (intrinsic_wo_chain:{ :[v2i64] } 8214:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DOTP_S_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9709	/ 25281 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_S_D),
9710	/ 25284 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9711	/ 25286 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9712	/ 25288 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9713	/ 25290 / GIR_RootConstrainSelectedInstOperands,
9714	/ 25291 / // GIR_Coverage, 681,
9715	/ 25291 / GIR_EraseRootFromParent_Done,
9716	/ 25292 / // Label 838: @25292
9717	/ 25292 / GIM_Try_CheckFeatures, /On fail goto//Label 839/ GIMT_Encode4(`25336`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 682 //
9718	/ 25299 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
9719	/ 25304 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9720	/ 25307 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
9721	/ 25310 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
9722	/ 25313 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9723	/ 25317 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9724	/ 25321 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
9725	/* 25325 / // (intrinsic_wo_chain:{ :[v8i16] } 8218:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DOTP_U_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
9726	/ 25325 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_U_H),
9727	/ 25328 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9728	/ 25330 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9729	/ 25332 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9730	/ 25334 / GIR_RootConstrainSelectedInstOperands,
9731	/ 25335 / // GIR_Coverage, 682,
9732	/ 25335 / GIR_EraseRootFromParent_Done,
9733	/ 25336 / // Label 839: @25336
9734	/ 25336 / GIM_Try_CheckFeatures, /On fail goto//Label 840/ GIMT_Encode4(`25380`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 683 //
9735	/ 25343 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
9736	/ 25348 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9737	/ 25351 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
9738	/ 25354 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
9739	/ 25357 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9740	/ 25361 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9741	/ 25365 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9742	/* 25369 / // (intrinsic_wo_chain:{ :[v4i32] } 8219:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DOTP_U_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
9743	/ 25369 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_U_W),
9744	/ 25372 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9745	/ 25374 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9746	/ 25376 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9747	/ 25378 / GIR_RootConstrainSelectedInstOperands,
9748	/ 25379 / // GIR_Coverage, 683,
9749	/ 25379 / GIR_EraseRootFromParent_Done,
9750	/ 25380 / // Label 840: @25380
9751	/ 25380 / GIM_Try_CheckFeatures, /On fail goto//Label 841/ GIMT_Encode4(`25424`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 684 //
9752	/ 25387 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
9753	/ 25392 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9754	/ 25395 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9755	/ 25398 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9756	/ 25401 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9757	/ 25405 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9758	/ 25409 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9759	/* 25413 / // (intrinsic_wo_chain:{ :[v2i64] } 8217:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DOTP_U_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
9760	/ 25413 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DOTP_U_D),
9761	/ 25416 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9762	/ 25418 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9763	/ 25420 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9764	/ 25422 / GIR_RootConstrainSelectedInstOperands,
9765	/ 25423 / // GIR_Coverage, 684,
9766	/ 25423 / GIR_EraseRootFromParent_Done,
9767	/ 25424 / // Label 841: @25424
9768	/ 25424 / GIM_Try_CheckFeatures, /On fail goto//Label 842/ GIMT_Encode4(`25468`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 699 //
9769	/ 25431 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fcaf_w),
9770	/ 25436 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9771	/ 25439 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9772	/ 25442 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9773	/ 25445 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9774	/ 25449 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9775	/ 25453 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9776	/* 25457 / // (intrinsic_wo_chain:{ :[v4i32] } 8257:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FCAF_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9777	/ 25457 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FCAF_W),
9778	/ 25460 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9779	/ 25462 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9780	/ 25464 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9781	/ 25466 / GIR_RootConstrainSelectedInstOperands,
9782	/ 25467 / // GIR_Coverage, 699,
9783	/ 25467 / GIR_EraseRootFromParent_Done,
9784	/ 25468 / // Label 842: @25468
9785	/ 25468 / GIM_Try_CheckFeatures, /On fail goto//Label 843/ GIMT_Encode4(`25512`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 700 //
9786	/ 25475 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fcaf_d),
9787	/ 25480 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9788	/ 25483 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9789	/ 25486 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9790	/ 25489 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9791	/ 25493 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9792	/ 25497 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9793	/* 25501 / // (intrinsic_wo_chain:{ :[v2i64] } 8256:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FCAF_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9794	/ 25501 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FCAF_D),
9795	/ 25504 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9796	/ 25506 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9797	/ 25508 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9798	/ 25510 / GIR_RootConstrainSelectedInstOperands,
9799	/ 25511 / // GIR_Coverage, 700,
9800	/ 25511 / GIR_EraseRootFromParent_Done,
9801	/ 25512 / // Label 843: @25512
9802	/ 25512 / GIM_Try_CheckFeatures, /On fail goto//Label 844/ GIMT_Encode4(`25556`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 725 //
9803	/ 25519 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexdo_h),
9804	/ 25524 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
9805	/ 25527 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9806	/ 25530 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9807	/ 25533 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
9808	/ 25537 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9809	/ 25541 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9810	/* 25545 / // (intrinsic_wo_chain:{ :[v8f16] } 8282:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FEXDO_H:{ :[v8f16] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9811	/ 25545 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXDO_H),
9812	/ 25548 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9813	/ 25550 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9814	/ 25552 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9815	/ 25554 / GIR_RootConstrainSelectedInstOperands,
9816	/ 25555 / // GIR_Coverage, 725,
9817	/ 25555 / GIR_EraseRootFromParent_Done,
9818	/ 25556 / // Label 844: @25556
9819	/ 25556 / GIM_Try_CheckFeatures, /On fail goto//Label 845/ GIMT_Encode4(`25600`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 726 //
9820	/ 25563 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fexdo_w),
9821	/ 25568 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9822	/ 25571 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9823	/ 25574 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9824	/ 25577 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9825	/ 25581 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9826	/ 25585 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9827	/* 25589 / // (intrinsic_wo_chain:{ :[v4f32] } 8283:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FEXDO_W:{ :[v4f32] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9828	/ 25589 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXDO_W),
9829	/ 25592 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9830	/ 25594 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9831	/ 25596 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9832	/ 25598 / GIR_RootConstrainSelectedInstOperands,
9833	/ 25599 / // GIR_Coverage, 726,
9834	/ 25599 / GIR_EraseRootFromParent_Done,
9835	/ 25600 / // Label 845: @25600
9836	/ 25600 / GIM_Try_CheckFeatures, /On fail goto//Label 846/ GIMT_Encode4(`25644`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 753 //
9837	/ 25607 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmax_w),
9838	/ 25612 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9839	/ 25615 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9840	/ 25618 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9841	/ 25621 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9842	/ 25625 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9843	/ 25629 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9844	/* 25633 / // (intrinsic_wo_chain:{ :[v4f32] } 8309:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMAX_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9845	/ 25633 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMAX_W),
9846	/ 25636 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9847	/ 25638 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9848	/ 25640 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9849	/ 25642 / GIR_RootConstrainSelectedInstOperands,
9850	/ 25643 / // GIR_Coverage, 753,
9851	/ 25643 / GIR_EraseRootFromParent_Done,
9852	/ 25644 / // Label 846: @25644
9853	/ 25644 / GIM_Try_CheckFeatures, /On fail goto//Label 847/ GIMT_Encode4(`25688`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 754 //
9854	/ 25651 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmax_d),
9855	/ 25656 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9856	/ 25659 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9857	/ 25662 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9858	/ 25665 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9859	/ 25669 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9860	/ 25673 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9861	/* 25677 / // (intrinsic_wo_chain:{ :[v2f64] } 8308:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMAX_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9862	/ 25677 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMAX_D),
9863	/ 25680 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9864	/ 25682 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9865	/ 25684 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9866	/ 25686 / GIR_RootConstrainSelectedInstOperands,
9867	/ 25687 / // GIR_Coverage, 754,
9868	/ 25687 / GIR_EraseRootFromParent_Done,
9869	/ 25688 / // Label 847: @25688
9870	/ 25688 / GIM_Try_CheckFeatures, /On fail goto//Label 848/ GIMT_Encode4(`25732`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 755 //
9871	/ 25695 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
9872	/ 25700 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9873	/ 25703 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9874	/ 25706 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9875	/ 25709 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9876	/ 25713 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9877	/ 25717 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9878	/* 25721 / // (intrinsic_wo_chain:{ :[v4f32] } 8307:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMAX_A_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9879	/ 25721 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMAX_A_W),
9880	/ 25724 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9881	/ 25726 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9882	/ 25728 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9883	/ 25730 / GIR_RootConstrainSelectedInstOperands,
9884	/ 25731 / // GIR_Coverage, 755,
9885	/ 25731 / GIR_EraseRootFromParent_Done,
9886	/ 25732 / // Label 848: @25732
9887	/ 25732 / GIM_Try_CheckFeatures, /On fail goto//Label 849/ GIMT_Encode4(`25776`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 756 //
9888	/ 25739 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
9889	/ 25744 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9890	/ 25747 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9891	/ 25750 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9892	/ 25753 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9893	/ 25757 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9894	/ 25761 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9895	/* 25765 / // (intrinsic_wo_chain:{ :[v2f64] } 8306:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMAX_A_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9896	/ 25765 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMAX_A_D),
9897	/ 25768 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9898	/ 25770 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9899	/ 25772 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9900	/ 25774 / GIR_RootConstrainSelectedInstOperands,
9901	/ 25775 / // GIR_Coverage, 756,
9902	/ 25775 / GIR_EraseRootFromParent_Done,
9903	/ 25776 / // Label 849: @25776
9904	/ 25776 / GIM_Try_CheckFeatures, /On fail goto//Label 850/ GIMT_Encode4(`25820`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 757 //
9905	/ 25783 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmin_w),
9906	/ 25788 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9907	/ 25791 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9908	/ 25794 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9909	/ 25797 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9910	/ 25801 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9911	/ 25805 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9912	/* 25809 / // (intrinsic_wo_chain:{ :[v4f32] } 8313:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMIN_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9913	/ 25809 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMIN_W),
9914	/ 25812 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9915	/ 25814 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9916	/ 25816 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9917	/ 25818 / GIR_RootConstrainSelectedInstOperands,
9918	/ 25819 / // GIR_Coverage, 757,
9919	/ 25819 / GIR_EraseRootFromParent_Done,
9920	/ 25820 / // Label 850: @25820
9921	/ 25820 / GIM_Try_CheckFeatures, /On fail goto//Label 851/ GIMT_Encode4(`25864`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 758 //
9922	/ 25827 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmin_d),
9923	/ 25832 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9924	/ 25835 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9925	/ 25838 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9926	/ 25841 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9927	/ 25845 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9928	/ 25849 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9929	/* 25853 / // (intrinsic_wo_chain:{ :[v2f64] } 8312:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMIN_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9930	/ 25853 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMIN_D),
9931	/ 25856 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9932	/ 25858 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9933	/ 25860 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9934	/ 25862 / GIR_RootConstrainSelectedInstOperands,
9935	/ 25863 / // GIR_Coverage, 758,
9936	/ 25863 / GIR_EraseRootFromParent_Done,
9937	/ 25864 / // Label 851: @25864
9938	/ 25864 / GIM_Try_CheckFeatures, /On fail goto//Label 852/ GIMT_Encode4(`25908`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 759 //
9939	/ 25871 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
9940	/ 25876 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9941	/ 25879 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9942	/ 25882 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9943	/ 25885 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9944	/ 25889 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9945	/ 25893 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9946	/* 25897 / // (intrinsic_wo_chain:{ :[v4f32] } 8311:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMIN_A_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9947	/ 25897 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMIN_A_W),
9948	/ 25900 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9949	/ 25902 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9950	/ 25904 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9951	/ 25906 / GIR_RootConstrainSelectedInstOperands,
9952	/ 25907 / // GIR_Coverage, 759,
9953	/ 25907 / GIR_EraseRootFromParent_Done,
9954	/ 25908 / // Label 852: @25908
9955	/ 25908 / GIM_Try_CheckFeatures, /On fail goto//Label 853/ GIMT_Encode4(`25952`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 760 //
9956	/ 25915 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
9957	/ 25920 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9958	/ 25923 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9959	/ 25926 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9960	/ 25929 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9961	/ 25933 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9962	/ 25937 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9963	/* 25941 / // (intrinsic_wo_chain:{ :[v2f64] } 8310:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMIN_A_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9964	/ 25941 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMIN_A_D),
9965	/ 25944 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9966	/ 25946 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9967	/ 25948 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9968	/ 25950 / GIR_RootConstrainSelectedInstOperands,
9969	/ 25951 / // GIR_Coverage, 760,
9970	/ 25951 / GIR_EraseRootFromParent_Done,
9971	/ 25952 / // Label 853: @25952
9972	/ 25952 / GIM_Try_CheckFeatures, /On fail goto//Label 854/ GIMT_Encode4(`25996`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 771 //
9973	/ 25959 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsaf_w),
9974	/ 25964 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
9975	/ 25967 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
9976	/ 25970 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
9977	/ 25973 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9978	/ 25977 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9979	/ 25981 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
9980	/* 25985 / // (intrinsic_wo_chain:{ :[v4i32] } 8325:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSAF_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
9981	/ 25985 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSAF_W),
9982	/ 25988 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
9983	/ 25990 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
9984	/ 25992 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
9985	/ 25994 / GIR_RootConstrainSelectedInstOperands,
9986	/ 25995 / // GIR_Coverage, 771,
9987	/ 25995 / GIR_EraseRootFromParent_Done,
9988	/ 25996 / // Label 854: @25996
9989	/ 25996 / GIM_Try_CheckFeatures, /On fail goto//Label 855/ GIMT_Encode4(`26040`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 772 //
9990	/ 26003 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsaf_d),
9991	/ 26008 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
9992	/ 26011 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
9993	/ 26014 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
9994	/ 26017 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9995	/ 26021 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9996	/ 26025 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
9997	/* 26029 / // (intrinsic_wo_chain:{ :[v2i64] } 8324:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSAF_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
9998	/ 26029 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSAF_D),
9999	/ 26032 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10000	/ 26034 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10001	/ 26036 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10002	/ 26038 / GIR_RootConstrainSelectedInstOperands,
10003	/ 26039 / // GIR_Coverage, 772,
10004	/ 26039 / GIR_EraseRootFromParent_Done,
10005	/ 26040 / // Label 855: @26040
10006	/ 26040 / GIM_Try_CheckFeatures, /On fail goto//Label 856/ GIMT_Encode4(`26084`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 773 //
10007	/ 26047 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fseq_w),
10008	/ 26052 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10009	/ 26055 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10010	/ 26058 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10011	/ 26061 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10012	/ 26065 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10013	/ 26069 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10014	/* 26073 / // (intrinsic_wo_chain:{ :[v4i32] } 8327:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSEQ_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10015	/ 26073 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSEQ_W),
10016	/ 26076 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10017	/ 26078 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10018	/ 26080 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10019	/ 26082 / GIR_RootConstrainSelectedInstOperands,
10020	/ 26083 / // GIR_Coverage, 773,
10021	/ 26083 / GIR_EraseRootFromParent_Done,
10022	/ 26084 / // Label 856: @26084
10023	/ 26084 / GIM_Try_CheckFeatures, /On fail goto//Label 857/ GIMT_Encode4(`26128`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 774 //
10024	/ 26091 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fseq_d),
10025	/ 26096 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10026	/ 26099 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10027	/ 26102 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10028	/ 26105 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10029	/ 26109 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10030	/ 26113 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10031	/* 26117 / // (intrinsic_wo_chain:{ :[v2i64] } 8326:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSEQ_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10032	/ 26117 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSEQ_D),
10033	/ 26120 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10034	/ 26122 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10035	/ 26124 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10036	/ 26126 / GIR_RootConstrainSelectedInstOperands,
10037	/ 26127 / // GIR_Coverage, 774,
10038	/ 26127 / GIR_EraseRootFromParent_Done,
10039	/ 26128 / // Label 857: @26128
10040	/ 26128 / GIM_Try_CheckFeatures, /On fail goto//Label 858/ GIMT_Encode4(`26172`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 775 //
10041	/ 26135 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsle_w),
10042	/ 26140 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10043	/ 26143 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10044	/ 26146 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10045	/ 26149 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10046	/ 26153 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10047	/ 26157 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10048	/* 26161 / // (intrinsic_wo_chain:{ :[v4i32] } 8329:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSLE_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10049	/ 26161 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSLE_W),
10050	/ 26164 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10051	/ 26166 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10052	/ 26168 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10053	/ 26170 / GIR_RootConstrainSelectedInstOperands,
10054	/ 26171 / // GIR_Coverage, 775,
10055	/ 26171 / GIR_EraseRootFromParent_Done,
10056	/ 26172 / // Label 858: @26172
10057	/ 26172 / GIM_Try_CheckFeatures, /On fail goto//Label 859/ GIMT_Encode4(`26216`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 776 //
10058	/ 26179 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsle_d),
10059	/ 26184 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10060	/ 26187 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10061	/ 26190 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10062	/ 26193 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10063	/ 26197 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10064	/ 26201 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10065	/* 26205 / // (intrinsic_wo_chain:{ :[v2i64] } 8328:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSLE_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10066	/ 26205 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSLE_D),
10067	/ 26208 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10068	/ 26210 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10069	/ 26212 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10070	/ 26214 / GIR_RootConstrainSelectedInstOperands,
10071	/ 26215 / // GIR_Coverage, 776,
10072	/ 26215 / GIR_EraseRootFromParent_Done,
10073	/ 26216 / // Label 859: @26216
10074	/ 26216 / GIM_Try_CheckFeatures, /On fail goto//Label 860/ GIMT_Encode4(`26260`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 777 //
10075	/ 26223 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fslt_w),
10076	/ 26228 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10077	/ 26231 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10078	/ 26234 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10079	/ 26237 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10080	/ 26241 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10081	/ 26245 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10082	/* 26249 / // (intrinsic_wo_chain:{ :[v4i32] } 8331:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSLT_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10083	/ 26249 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSLT_W),
10084	/ 26252 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10085	/ 26254 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10086	/ 26256 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10087	/ 26258 / GIR_RootConstrainSelectedInstOperands,
10088	/ 26259 / // GIR_Coverage, 777,
10089	/ 26259 / GIR_EraseRootFromParent_Done,
10090	/ 26260 / // Label 860: @26260
10091	/ 26260 / GIM_Try_CheckFeatures, /On fail goto//Label 861/ GIMT_Encode4(`26304`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 778 //
10092	/ 26267 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fslt_d),
10093	/ 26272 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10094	/ 26275 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10095	/ 26278 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10096	/ 26281 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10097	/ 26285 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10098	/ 26289 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10099	/* 26293 / // (intrinsic_wo_chain:{ :[v2i64] } 8330:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSLT_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10100	/ 26293 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSLT_D),
10101	/ 26296 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10102	/ 26298 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10103	/ 26300 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10104	/ 26302 / GIR_RootConstrainSelectedInstOperands,
10105	/ 26303 / // GIR_Coverage, 778,
10106	/ 26303 / GIR_EraseRootFromParent_Done,
10107	/ 26304 / // Label 861: @26304
10108	/ 26304 / GIM_Try_CheckFeatures, /On fail goto//Label 862/ GIMT_Encode4(`26348`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 779 //
10109	/ 26311 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsne_w),
10110	/ 26316 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10111	/ 26319 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10112	/ 26322 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10113	/ 26325 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10114	/ 26329 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10115	/ 26333 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10116	/* 26337 / // (intrinsic_wo_chain:{ :[v4i32] } 8333:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSNE_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10117	/ 26337 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSNE_W),
10118	/ 26340 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10119	/ 26342 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10120	/ 26344 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10121	/ 26346 / GIR_RootConstrainSelectedInstOperands,
10122	/ 26347 / // GIR_Coverage, 779,
10123	/ 26347 / GIR_EraseRootFromParent_Done,
10124	/ 26348 / // Label 862: @26348
10125	/ 26348 / GIM_Try_CheckFeatures, /On fail goto//Label 863/ GIMT_Encode4(`26392`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 780 //
10126	/ 26355 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsne_d),
10127	/ 26360 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10128	/ 26363 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10129	/ 26366 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10130	/ 26369 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10131	/ 26373 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10132	/ 26377 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10133	/* 26381 / // (intrinsic_wo_chain:{ :[v2i64] } 8332:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSNE_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10134	/ 26381 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSNE_D),
10135	/ 26384 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10136	/ 26386 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10137	/ 26388 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10138	/ 26390 / GIR_RootConstrainSelectedInstOperands,
10139	/ 26391 / // GIR_Coverage, 780,
10140	/ 26391 / GIR_EraseRootFromParent_Done,
10141	/ 26392 / // Label 863: @26392
10142	/ 26392 / GIM_Try_CheckFeatures, /On fail goto//Label 864/ GIMT_Encode4(`26436`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 781 //
10143	/ 26399 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsor_w),
10144	/ 26404 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10145	/ 26407 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10146	/ 26410 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10147	/ 26413 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10148	/ 26417 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10149	/ 26421 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10150	/* 26425 / // (intrinsic_wo_chain:{ :[v4i32] } 8335:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSOR_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10151	/ 26425 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSOR_W),
10152	/ 26428 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10153	/ 26430 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10154	/ 26432 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10155	/ 26434 / GIR_RootConstrainSelectedInstOperands,
10156	/ 26435 / // GIR_Coverage, 781,
10157	/ 26435 / GIR_EraseRootFromParent_Done,
10158	/ 26436 / // Label 864: @26436
10159	/ 26436 / GIM_Try_CheckFeatures, /On fail goto//Label 865/ GIMT_Encode4(`26480`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 782 //
10160	/ 26443 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsor_d),
10161	/ 26448 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10162	/ 26451 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10163	/ 26454 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10164	/ 26457 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10165	/ 26461 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10166	/ 26465 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10167	/* 26469 / // (intrinsic_wo_chain:{ :[v2i64] } 8334:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSOR_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10168	/ 26469 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSOR_D),
10169	/ 26472 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10170	/ 26474 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10171	/ 26476 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10172	/ 26478 / GIR_RootConstrainSelectedInstOperands,
10173	/ 26479 / // GIR_Coverage, 782,
10174	/ 26479 / GIR_EraseRootFromParent_Done,
10175	/ 26480 / // Label 865: @26480
10176	/ 26480 / GIM_Try_CheckFeatures, /On fail goto//Label 866/ GIMT_Encode4(`26524`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 787 //
10177	/ 26487 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10178	/ 26492 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10179	/ 26495 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10180	/ 26498 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10181	/ 26501 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10182	/ 26505 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10183	/ 26509 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10184	/* 26513 / // (intrinsic_wo_chain:{ :[v4i32] } 8341:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSUEQ_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10185	/ 26513 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUEQ_W),
10186	/ 26516 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10187	/ 26518 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10188	/ 26520 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10189	/ 26522 / GIR_RootConstrainSelectedInstOperands,
10190	/ 26523 / // GIR_Coverage, 787,
10191	/ 26523 / GIR_EraseRootFromParent_Done,
10192	/ 26524 / // Label 866: @26524
10193	/ 26524 / GIM_Try_CheckFeatures, /On fail goto//Label 867/ GIMT_Encode4(`26568`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 788 //
10194	/ 26531 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10195	/ 26536 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10196	/ 26539 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10197	/ 26542 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10198	/ 26545 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10199	/ 26549 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10200	/ 26553 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10201	/* 26557 / // (intrinsic_wo_chain:{ :[v2i64] } 8340:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSUEQ_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10202	/ 26557 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUEQ_D),
10203	/ 26560 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10204	/ 26562 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10205	/ 26564 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10206	/ 26566 / GIR_RootConstrainSelectedInstOperands,
10207	/ 26567 / // GIR_Coverage, 788,
10208	/ 26567 / GIR_EraseRootFromParent_Done,
10209	/ 26568 / // Label 867: @26568
10210	/ 26568 / GIM_Try_CheckFeatures, /On fail goto//Label 868/ GIMT_Encode4(`26612`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 789 //
10211	/ 26575 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsule_w),
10212	/ 26580 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10213	/ 26583 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10214	/ 26586 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10215	/ 26589 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10216	/ 26593 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10217	/ 26597 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10218	/* 26601 / // (intrinsic_wo_chain:{ :[v4i32] } 8343:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSULE_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10219	/ 26601 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSULE_W),
10220	/ 26604 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10221	/ 26606 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10222	/ 26608 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10223	/ 26610 / GIR_RootConstrainSelectedInstOperands,
10224	/ 26611 / // GIR_Coverage, 789,
10225	/ 26611 / GIR_EraseRootFromParent_Done,
10226	/ 26612 / // Label 868: @26612
10227	/ 26612 / GIM_Try_CheckFeatures, /On fail goto//Label 869/ GIMT_Encode4(`26656`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 790 //
10228	/ 26619 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsule_d),
10229	/ 26624 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10230	/ 26627 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10231	/ 26630 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10232	/ 26633 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10233	/ 26637 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10234	/ 26641 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10235	/* 26645 / // (intrinsic_wo_chain:{ :[v2i64] } 8342:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSULE_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10236	/ 26645 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSULE_D),
10237	/ 26648 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10238	/ 26650 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10239	/ 26652 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10240	/ 26654 / GIR_RootConstrainSelectedInstOperands,
10241	/ 26655 / // GIR_Coverage, 790,
10242	/ 26655 / GIR_EraseRootFromParent_Done,
10243	/ 26656 / // Label 869: @26656
10244	/ 26656 / GIM_Try_CheckFeatures, /On fail goto//Label 870/ GIMT_Encode4(`26700`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 791 //
10245	/ 26663 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsult_w),
10246	/ 26668 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10247	/ 26671 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10248	/ 26674 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10249	/ 26677 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10250	/ 26681 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10251	/ 26685 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10252	/* 26689 / // (intrinsic_wo_chain:{ :[v4i32] } 8345:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSULT_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10253	/ 26689 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSULT_W),
10254	/ 26692 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10255	/ 26694 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10256	/ 26696 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10257	/ 26698 / GIR_RootConstrainSelectedInstOperands,
10258	/ 26699 / // GIR_Coverage, 791,
10259	/ 26699 / GIR_EraseRootFromParent_Done,
10260	/ 26700 / // Label 870: @26700
10261	/ 26700 / GIM_Try_CheckFeatures, /On fail goto//Label 871/ GIMT_Encode4(`26744`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 792 //
10262	/ 26707 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsult_d),
10263	/ 26712 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10264	/ 26715 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10265	/ 26718 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10266	/ 26721 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10267	/ 26725 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10268	/ 26729 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10269	/* 26733 / // (intrinsic_wo_chain:{ :[v2i64] } 8344:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSULT_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10270	/ 26733 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSULT_D),
10271	/ 26736 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10272	/ 26738 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10273	/ 26740 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10274	/ 26742 / GIR_RootConstrainSelectedInstOperands,
10275	/ 26743 / // GIR_Coverage, 792,
10276	/ 26743 / GIR_EraseRootFromParent_Done,
10277	/ 26744 / // Label 871: @26744
10278	/ 26744 / GIM_Try_CheckFeatures, /On fail goto//Label 872/ GIMT_Encode4(`26788`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 793 //
10279	/ 26751 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsun_w),
10280	/ 26756 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10281	/ 26759 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10282	/ 26762 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10283	/ 26765 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10284	/ 26769 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10285	/ 26773 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10286	/* 26777 / // (intrinsic_wo_chain:{ :[v4i32] } 8347:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSUN_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10287	/ 26777 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUN_W),
10288	/ 26780 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10289	/ 26782 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10290	/ 26784 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10291	/ 26786 / GIR_RootConstrainSelectedInstOperands,
10292	/ 26787 / // GIR_Coverage, 793,
10293	/ 26787 / GIR_EraseRootFromParent_Done,
10294	/ 26788 / // Label 872: @26788
10295	/ 26788 / GIM_Try_CheckFeatures, /On fail goto//Label 873/ GIMT_Encode4(`26832`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 794 //
10296	/ 26795 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsun_d),
10297	/ 26800 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10298	/ 26803 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10299	/ 26806 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10300	/ 26809 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10301	/ 26813 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10302	/ 26817 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10303	/* 26821 / // (intrinsic_wo_chain:{ :[v2i64] } 8346:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSUN_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10304	/ 26821 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUN_D),
10305	/ 26824 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10306	/ 26826 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10307	/ 26828 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10308	/ 26830 / GIR_RootConstrainSelectedInstOperands,
10309	/ 26831 / // GIR_Coverage, 794,
10310	/ 26831 / GIR_EraseRootFromParent_Done,
10311	/ 26832 / // Label 873: @26832
10312	/ 26832 / GIM_Try_CheckFeatures, /On fail goto//Label 874/ GIMT_Encode4(`26876`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 795 //
10313	/ 26839 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsune_w),
10314	/ 26844 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10315	/ 26847 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10316	/ 26850 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10317	/ 26853 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10318	/ 26857 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10319	/ 26861 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10320	/* 26865 / // (intrinsic_wo_chain:{ :[v4i32] } 8349:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSUNE_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10321	/ 26865 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUNE_W),
10322	/ 26868 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10323	/ 26870 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10324	/ 26872 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10325	/ 26874 / GIR_RootConstrainSelectedInstOperands,
10326	/ 26875 / // GIR_Coverage, 795,
10327	/ 26875 / GIR_EraseRootFromParent_Done,
10328	/ 26876 / // Label 874: @26876
10329	/ 26876 / GIM_Try_CheckFeatures, /On fail goto//Label 875/ GIMT_Encode4(`26920`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 796 //
10330	/ 26883 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_fsune_d),
10331	/ 26888 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10332	/ 26891 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10333	/ 26894 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10334	/ 26897 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10335	/ 26901 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10336	/ 26905 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10337	/* 26909 / // (intrinsic_wo_chain:{ :[v2i64] } 8348:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSUNE_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10338	/ 26909 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUNE_D),
10339	/ 26912 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10340	/ 26914 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10341	/ 26916 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10342	/ 26918 / GIR_RootConstrainSelectedInstOperands,
10343	/ 26919 / // GIR_Coverage, 796,
10344	/ 26919 / GIR_EraseRootFromParent_Done,
10345	/ 26920 / // Label 875: @26920
10346	/ 26920 / GIM_Try_CheckFeatures, /On fail goto//Label 876/ GIMT_Encode4(`26964`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 801 //
10347	/ 26927 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftq_h),
10348	/ 26932 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10349	/ 26935 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10350	/ 26938 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10351	/ 26941 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10352	/ 26945 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10353	/ 26949 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10354	/* 26953 / // (intrinsic_wo_chain:{ :[v8i16] } 8354:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FTQ_H:{ :[v8i16] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
10355	/ 26953 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTQ_H),
10356	/ 26956 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10357	/ 26958 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10358	/ 26960 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10359	/ 26962 / GIR_RootConstrainSelectedInstOperands,
10360	/ 26963 / // GIR_Coverage, 801,
10361	/ 26963 / GIR_EraseRootFromParent_Done,
10362	/ 26964 / // Label 876: @26964
10363	/ 26964 / GIM_Try_CheckFeatures, /On fail goto//Label 877/ GIMT_Encode4(`27008`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 802 //
10364	/ 26971 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ftq_w),
10365	/ 26976 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10366	/ 26979 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10367	/ 26982 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10368	/ 26985 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10369	/ 26989 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10370	/ 26993 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10371	/* 26997 / // (intrinsic_wo_chain:{ :[v4i32] } 8355:{ :[iPTR] }, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FTQ_W:{ :[v4i32] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
10372	/ 26997 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FTQ_W),
10373	/ 27000 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10374	/ 27002 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10375	/ 27004 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10376	/ 27006 / GIR_RootConstrainSelectedInstOperands,
10377	/ 27007 / // GIR_Coverage, 802,
10378	/ 27007 / GIR_EraseRootFromParent_Done,
10379	/ 27008 / // Label 877: @27008
10380	/ 27008 / GIM_Try_CheckFeatures, /On fail goto//Label 878/ GIMT_Encode4(`27052`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 807 //
10381	/ 27015 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
10382	/ 27020 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10383	/ 27023 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10384	/ 27026 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10385	/ 27029 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10386	/ 27033 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10387	/ 27037 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10388	/* 27041 / // (intrinsic_wo_chain:{ :[v8i16] } 8361:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (HADD_S_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10389	/ 27041 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_S_H),
10390	/ 27044 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10391	/ 27046 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10392	/ 27048 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10393	/ 27050 / GIR_RootConstrainSelectedInstOperands,
10394	/ 27051 / // GIR_Coverage, 807,
10395	/ 27051 / GIR_EraseRootFromParent_Done,
10396	/ 27052 / // Label 878: @27052
10397	/ 27052 / GIM_Try_CheckFeatures, /On fail goto//Label 879/ GIMT_Encode4(`27096`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 808 //
10398	/ 27059 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
10399	/ 27064 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10400	/ 27067 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10401	/ 27070 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10402	/ 27073 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10403	/ 27077 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10404	/ 27081 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10405	/* 27085 / // (intrinsic_wo_chain:{ :[v4i32] } 8362:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (HADD_S_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10406	/ 27085 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_S_W),
10407	/ 27088 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10408	/ 27090 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10409	/ 27092 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10410	/ 27094 / GIR_RootConstrainSelectedInstOperands,
10411	/ 27095 / // GIR_Coverage, 808,
10412	/ 27095 / GIR_EraseRootFromParent_Done,
10413	/ 27096 / // Label 879: @27096
10414	/ 27096 / GIM_Try_CheckFeatures, /On fail goto//Label 880/ GIMT_Encode4(`27140`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 809 //
10415	/ 27103 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
10416	/ 27108 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10417	/ 27111 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10418	/ 27114 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10419	/ 27117 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10420	/ 27121 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10421	/ 27125 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10422	/* 27129 / // (intrinsic_wo_chain:{ :[v2i64] } 8360:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (HADD_S_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10423	/ 27129 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_S_D),
10424	/ 27132 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10425	/ 27134 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10426	/ 27136 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10427	/ 27138 / GIR_RootConstrainSelectedInstOperands,
10428	/ 27139 / // GIR_Coverage, 809,
10429	/ 27139 / GIR_EraseRootFromParent_Done,
10430	/ 27140 / // Label 880: @27140
10431	/ 27140 / GIM_Try_CheckFeatures, /On fail goto//Label 881/ GIMT_Encode4(`27184`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 810 //
10432	/ 27147 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
10433	/ 27152 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10434	/ 27155 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10435	/ 27158 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10436	/ 27161 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10437	/ 27165 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10438	/ 27169 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10439	/* 27173 / // (intrinsic_wo_chain:{ :[v8i16] } 8364:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (HADD_U_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10440	/ 27173 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_U_H),
10441	/ 27176 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10442	/ 27178 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10443	/ 27180 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10444	/ 27182 / GIR_RootConstrainSelectedInstOperands,
10445	/ 27183 / // GIR_Coverage, 810,
10446	/ 27183 / GIR_EraseRootFromParent_Done,
10447	/ 27184 / // Label 881: @27184
10448	/ 27184 / GIM_Try_CheckFeatures, /On fail goto//Label 882/ GIMT_Encode4(`27228`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 811 //
10449	/ 27191 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
10450	/ 27196 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10451	/ 27199 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10452	/ 27202 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10453	/ 27205 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10454	/ 27209 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10455	/ 27213 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10456	/* 27217 / // (intrinsic_wo_chain:{ :[v4i32] } 8365:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (HADD_U_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10457	/ 27217 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_U_W),
10458	/ 27220 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10459	/ 27222 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10460	/ 27224 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10461	/ 27226 / GIR_RootConstrainSelectedInstOperands,
10462	/ 27227 / // GIR_Coverage, 811,
10463	/ 27227 / GIR_EraseRootFromParent_Done,
10464	/ 27228 / // Label 882: @27228
10465	/ 27228 / GIM_Try_CheckFeatures, /On fail goto//Label 883/ GIMT_Encode4(`27272`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 812 //
10466	/ 27235 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
10467	/ 27240 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10468	/ 27243 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10469	/ 27246 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10470	/ 27249 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10471	/ 27253 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10472	/ 27257 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10473	/* 27261 / // (intrinsic_wo_chain:{ :[v2i64] } 8363:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (HADD_U_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10474	/ 27261 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HADD_U_D),
10475	/ 27264 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10476	/ 27266 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10477	/ 27268 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10478	/ 27270 / GIR_RootConstrainSelectedInstOperands,
10479	/ 27271 / // GIR_Coverage, 812,
10480	/ 27271 / GIR_EraseRootFromParent_Done,
10481	/ 27272 / // Label 883: @27272
10482	/ 27272 / GIM_Try_CheckFeatures, /On fail goto//Label 884/ GIMT_Encode4(`27316`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 813 //
10483	/ 27279 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
10484	/ 27284 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10485	/ 27287 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10486	/ 27290 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10487	/ 27293 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10488	/ 27297 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10489	/ 27301 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10490	/* 27305 / // (intrinsic_wo_chain:{ :[v8i16] } 8367:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (HSUB_S_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10491	/ 27305 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_S_H),
10492	/ 27308 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10493	/ 27310 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10494	/ 27312 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10495	/ 27314 / GIR_RootConstrainSelectedInstOperands,
10496	/ 27315 / // GIR_Coverage, 813,
10497	/ 27315 / GIR_EraseRootFromParent_Done,
10498	/ 27316 / // Label 884: @27316
10499	/ 27316 / GIM_Try_CheckFeatures, /On fail goto//Label 885/ GIMT_Encode4(`27360`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 814 //
10500	/ 27323 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
10501	/ 27328 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10502	/ 27331 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10503	/ 27334 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10504	/ 27337 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10505	/ 27341 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10506	/ 27345 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10507	/* 27349 / // (intrinsic_wo_chain:{ :[v4i32] } 8368:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (HSUB_S_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10508	/ 27349 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_S_W),
10509	/ 27352 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10510	/ 27354 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10511	/ 27356 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10512	/ 27358 / GIR_RootConstrainSelectedInstOperands,
10513	/ 27359 / // GIR_Coverage, 814,
10514	/ 27359 / GIR_EraseRootFromParent_Done,
10515	/ 27360 / // Label 885: @27360
10516	/ 27360 / GIM_Try_CheckFeatures, /On fail goto//Label 886/ GIMT_Encode4(`27404`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 815 //
10517	/ 27367 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
10518	/ 27372 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10519	/ 27375 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10520	/ 27378 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10521	/ 27381 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10522	/ 27385 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10523	/ 27389 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10524	/* 27393 / // (intrinsic_wo_chain:{ :[v2i64] } 8366:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (HSUB_S_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10525	/ 27393 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_S_D),
10526	/ 27396 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10527	/ 27398 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10528	/ 27400 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10529	/ 27402 / GIR_RootConstrainSelectedInstOperands,
10530	/ 27403 / // GIR_Coverage, 815,
10531	/ 27403 / GIR_EraseRootFromParent_Done,
10532	/ 27404 / // Label 886: @27404
10533	/ 27404 / GIM_Try_CheckFeatures, /On fail goto//Label 887/ GIMT_Encode4(`27448`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 816 //
10534	/ 27411 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
10535	/ 27416 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10536	/ 27419 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10537	/ 27422 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10538	/ 27425 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10539	/ 27429 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10540	/ 27433 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10541	/* 27437 / // (intrinsic_wo_chain:{ :[v8i16] } 8370:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (HSUB_U_H:{ :[v8i16] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10542	/ 27437 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_U_H),
10543	/ 27440 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10544	/ 27442 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10545	/ 27444 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10546	/ 27446 / GIR_RootConstrainSelectedInstOperands,
10547	/ 27447 / // GIR_Coverage, 816,
10548	/ 27447 / GIR_EraseRootFromParent_Done,
10549	/ 27448 / // Label 887: @27448
10550	/ 27448 / GIM_Try_CheckFeatures, /On fail goto//Label 888/ GIMT_Encode4(`27492`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 817 //
10551	/ 27455 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
10552	/ 27460 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10553	/ 27463 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10554	/ 27466 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10555	/ 27469 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10556	/ 27473 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10557	/ 27477 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10558	/* 27481 / // (intrinsic_wo_chain:{ :[v4i32] } 8371:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (HSUB_U_W:{ :[v4i32] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10559	/ 27481 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_U_W),
10560	/ 27484 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10561	/ 27486 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10562	/ 27488 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10563	/ 27490 / GIR_RootConstrainSelectedInstOperands,
10564	/ 27491 / // GIR_Coverage, 817,
10565	/ 27491 / GIR_EraseRootFromParent_Done,
10566	/ 27492 / // Label 888: @27492
10567	/ 27492 / GIM_Try_CheckFeatures, /On fail goto//Label 889/ GIMT_Encode4(`27536`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 818 //
10568	/ 27499 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
10569	/ 27504 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10570	/ 27507 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10571	/ 27510 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10572	/ 27513 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10573	/ 27517 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10574	/ 27521 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10575	/* 27525 / // (intrinsic_wo_chain:{ :[v2i64] } 8369:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (HSUB_U_D:{ :[v2i64] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10576	/ 27525 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::HSUB_U_D),
10577	/ 27528 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10578	/ 27530 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10579	/ 27532 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10580	/ 27534 / GIR_RootConstrainSelectedInstOperands,
10581	/ 27535 / // GIR_Coverage, 818,
10582	/ 27535 / GIR_EraseRootFromParent_Done,
10583	/ 27536 / // Label 889: @27536
10584	/ 27536 / GIM_Try_CheckFeatures, /On fail goto//Label 890/ GIMT_Encode4(`27580`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 871 //
10585	/ 27543 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_max_a_b),
10586	/ 27548 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10587	/ 27551 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10588	/ 27554 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10589	/ 27557 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10590	/ 27561 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10591	/ 27565 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10592	/* 27569 / // (intrinsic_wo_chain:{ :[v16i8] } 8425:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MAX_A_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10593	/ 27569 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MAX_A_B),
10594	/ 27572 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10595	/ 27574 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10596	/ 27576 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10597	/ 27578 / GIR_RootConstrainSelectedInstOperands,
10598	/ 27579 / // GIR_Coverage, 871,
10599	/ 27579 / GIR_EraseRootFromParent_Done,
10600	/ 27580 / // Label 890: @27580
10601	/ 27580 / GIM_Try_CheckFeatures, /On fail goto//Label 891/ GIMT_Encode4(`27624`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 872 //
10602	/ 27587 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_max_a_h),
10603	/ 27592 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10604	/ 27595 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10605	/ 27598 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10606	/ 27601 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10607	/ 27605 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10608	/ 27609 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10609	/* 27613 / // (intrinsic_wo_chain:{ :[v8i16] } 8427:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MAX_A_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10610	/ 27613 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MAX_A_H),
10611	/ 27616 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10612	/ 27618 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10613	/ 27620 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10614	/ 27622 / GIR_RootConstrainSelectedInstOperands,
10615	/ 27623 / // GIR_Coverage, 872,
10616	/ 27623 / GIR_EraseRootFromParent_Done,
10617	/ 27624 / // Label 891: @27624
10618	/ 27624 / GIM_Try_CheckFeatures, /On fail goto//Label 892/ GIMT_Encode4(`27668`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 873 //
10619	/ 27631 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_max_a_w),
10620	/ 27636 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10621	/ 27639 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10622	/ 27642 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10623	/ 27645 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10624	/ 27649 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10625	/ 27653 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10626	/* 27657 / // (intrinsic_wo_chain:{ :[v4i32] } 8428:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MAX_A_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10627	/ 27657 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MAX_A_W),
10628	/ 27660 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10629	/ 27662 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10630	/ 27664 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10631	/ 27666 / GIR_RootConstrainSelectedInstOperands,
10632	/ 27667 / // GIR_Coverage, 873,
10633	/ 27667 / GIR_EraseRootFromParent_Done,
10634	/ 27668 / // Label 892: @27668
10635	/ 27668 / GIM_Try_CheckFeatures, /On fail goto//Label 893/ GIMT_Encode4(`27712`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 874 //
10636	/ 27675 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_max_a_d),
10637	/ 27680 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10638	/ 27683 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10639	/ 27686 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10640	/ 27689 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10641	/ 27693 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10642	/ 27697 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10643	/* 27701 / // (intrinsic_wo_chain:{ :[v2i64] } 8426:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MAX_A_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
10644	/ 27701 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MAX_A_D),
10645	/ 27704 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10646	/ 27706 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10647	/ 27708 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10648	/ 27710 / GIR_RootConstrainSelectedInstOperands,
10649	/ 27711 / // GIR_Coverage, 874,
10650	/ 27711 / GIR_EraseRootFromParent_Done,
10651	/ 27712 / // Label 893: @27712
10652	/ 27712 / GIM_Try_CheckFeatures, /On fail goto//Label 894/ GIMT_Encode4(`27756`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 891 //
10653	/ 27719 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_min_a_b),
10654	/ 27724 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10655	/ 27727 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10656	/ 27730 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10657	/ 27733 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10658	/ 27737 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10659	/ 27741 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10660	/* 27745 / // (intrinsic_wo_chain:{ :[v16i8] } 8445:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MIN_A_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10661	/ 27745 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_A_B),
10662	/ 27748 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10663	/ 27750 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10664	/ 27752 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10665	/ 27754 / GIR_RootConstrainSelectedInstOperands,
10666	/ 27755 / // GIR_Coverage, 891,
10667	/ 27755 / GIR_EraseRootFromParent_Done,
10668	/ 27756 / // Label 894: @27756
10669	/ 27756 / GIM_Try_CheckFeatures, /On fail goto//Label 895/ GIMT_Encode4(`27800`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 892 //
10670	/ 27763 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_min_a_h),
10671	/ 27768 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10672	/ 27771 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10673	/ 27774 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10674	/ 27777 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10675	/ 27781 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10676	/ 27785 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10677	/* 27789 / // (intrinsic_wo_chain:{ :[v8i16] } 8447:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MIN_A_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10678	/ 27789 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_A_H),
10679	/ 27792 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10680	/ 27794 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10681	/ 27796 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10682	/ 27798 / GIR_RootConstrainSelectedInstOperands,
10683	/ 27799 / // GIR_Coverage, 892,
10684	/ 27799 / GIR_EraseRootFromParent_Done,
10685	/ 27800 / // Label 895: @27800
10686	/ 27800 / GIM_Try_CheckFeatures, /On fail goto//Label 896/ GIMT_Encode4(`27844`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 893 //
10687	/ 27807 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_min_a_w),
10688	/ 27812 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10689	/ 27815 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10690	/ 27818 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10691	/ 27821 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10692	/ 27825 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10693	/ 27829 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10694	/* 27833 / // (intrinsic_wo_chain:{ :[v4i32] } 8448:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MIN_A_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10695	/ 27833 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_A_W),
10696	/ 27836 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10697	/ 27838 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10698	/ 27840 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10699	/ 27842 / GIR_RootConstrainSelectedInstOperands,
10700	/ 27843 / // GIR_Coverage, 893,
10701	/ 27843 / GIR_EraseRootFromParent_Done,
10702	/ 27844 / // Label 896: @27844
10703	/ 27844 / GIM_Try_CheckFeatures, /On fail goto//Label 897/ GIMT_Encode4(`27888`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 894 //
10704	/ 27851 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_min_a_d),
10705	/ 27856 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10706	/ 27859 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10707	/ 27862 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10708	/ 27865 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10709	/ 27869 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10710	/ 27873 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10711	/* 27877 / // (intrinsic_wo_chain:{ :[v2i64] } 8446:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MIN_A_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
10712	/ 27877 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_A_D),
10713	/ 27880 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10714	/ 27882 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10715	/ 27884 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10716	/ 27886 / GIR_RootConstrainSelectedInstOperands,
10717	/ 27887 / // GIR_Coverage, 894,
10718	/ 27887 / GIR_EraseRootFromParent_Done,
10719	/ 27888 / // Label 897: @27888
10720	/ 27888 / GIM_Try_CheckFeatures, /On fail goto//Label 898/ GIMT_Encode4(`27932`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 927 //
10721	/ 27895 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mul_q_h),
10722	/ 27900 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10723	/ 27903 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10724	/ 27906 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10725	/ 27909 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10726	/ 27913 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10727	/ 27917 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10728	/* 27921 / // (intrinsic_wo_chain:{ :[v8i16] } 8487:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MUL_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10729	/ 27921 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MUL_Q_H),
10730	/ 27924 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10731	/ 27926 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10732	/ 27928 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10733	/ 27930 / GIR_RootConstrainSelectedInstOperands,
10734	/ 27931 / // GIR_Coverage, 927,
10735	/ 27931 / GIR_EraseRootFromParent_Done,
10736	/ 27932 / // Label 898: @27932
10737	/ 27932 / GIM_Try_CheckFeatures, /On fail goto//Label 899/ GIMT_Encode4(`27976`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 928 //
10738	/ 27939 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mul_q_w),
10739	/ 27944 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10740	/ 27947 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10741	/ 27950 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10742	/ 27953 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10743	/ 27957 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10744	/ 27961 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10745	/* 27965 / // (intrinsic_wo_chain:{ :[v4i32] } 8488:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MUL_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10746	/ 27965 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MUL_Q_W),
10747	/ 27968 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10748	/ 27970 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10749	/ 27972 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10750	/ 27974 / GIR_RootConstrainSelectedInstOperands,
10751	/ 27975 / // GIR_Coverage, 928,
10752	/ 27975 / GIR_EraseRootFromParent_Done,
10753	/ 27976 / // Label 899: @27976
10754	/ 27976 / GIM_Try_CheckFeatures, /On fail goto//Label 900/ GIMT_Encode4(`28020`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 929 //
10755	/ 27983 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
10756	/ 27988 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10757	/ 27991 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10758	/ 27994 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10759	/ 27997 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10760	/ 28001 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10761	/ 28005 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10762	/* 28009 / // (intrinsic_wo_chain:{ :[v8i16] } 8498:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MULR_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10763	/ 28009 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULR_Q_H),
10764	/ 28012 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10765	/ 28014 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10766	/ 28016 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10767	/ 28018 / GIR_RootConstrainSelectedInstOperands,
10768	/ 28019 / // GIR_Coverage, 929,
10769	/ 28019 / GIR_EraseRootFromParent_Done,
10770	/ 28020 / // Label 900: @28020
10771	/ 28020 / GIM_Try_CheckFeatures, /On fail goto//Label 901/ GIMT_Encode4(`28064`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 930 //
10772	/ 28027 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
10773	/ 28032 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10774	/ 28035 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10775	/ 28038 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10776	/ 28041 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10777	/ 28045 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10778	/ 28049 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10779	/* 28053 / // (intrinsic_wo_chain:{ :[v4i32] } 8499:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MULR_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10780	/ 28053 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULR_Q_W),
10781	/ 28056 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10782	/ 28058 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10783	/ 28060 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10784	/ 28062 / GIR_RootConstrainSelectedInstOperands,
10785	/ 28063 / // GIR_Coverage, 930,
10786	/ 28063 / GIR_EraseRootFromParent_Done,
10787	/ 28064 / // Label 901: @28064
10788	/ 28064 / GIM_Try_CheckFeatures, /On fail goto//Label 902/ GIMT_Encode4(`28108`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1008 //
10789	/ 28071 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srar_b),
10790	/ 28076 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10791	/ 28079 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10792	/ 28082 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10793	/ 28085 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10794	/ 28089 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10795	/ 28093 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10796	/* 28097 / // (intrinsic_wo_chain:{ :[v16i8] } 8612:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SRAR_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10797	/ 28097 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRAR_B),
10798	/ 28100 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10799	/ 28102 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10800	/ 28104 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10801	/ 28106 / GIR_RootConstrainSelectedInstOperands,
10802	/ 28107 / // GIR_Coverage, 1008,
10803	/ 28107 / GIR_EraseRootFromParent_Done,
10804	/ 28108 / // Label 902: @28108
10805	/ 28108 / GIM_Try_CheckFeatures, /On fail goto//Label 903/ GIMT_Encode4(`28152`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1009 //
10806	/ 28115 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srar_h),
10807	/ 28120 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10808	/ 28123 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10809	/ 28126 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10810	/ 28129 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10811	/ 28133 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10812	/ 28137 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10813	/* 28141 / // (intrinsic_wo_chain:{ :[v8i16] } 8614:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SRAR_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10814	/ 28141 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRAR_H),
10815	/ 28144 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10816	/ 28146 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10817	/ 28148 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10818	/ 28150 / GIR_RootConstrainSelectedInstOperands,
10819	/ 28151 / // GIR_Coverage, 1009,
10820	/ 28151 / GIR_EraseRootFromParent_Done,
10821	/ 28152 / // Label 903: @28152
10822	/ 28152 / GIM_Try_CheckFeatures, /On fail goto//Label 904/ GIMT_Encode4(`28196`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1010 //
10823	/ 28159 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srar_w),
10824	/ 28164 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10825	/ 28167 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10826	/ 28170 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10827	/ 28173 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10828	/ 28177 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10829	/ 28181 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10830	/* 28185 / // (intrinsic_wo_chain:{ :[v4i32] } 8615:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SRAR_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10831	/ 28185 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRAR_W),
10832	/ 28188 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10833	/ 28190 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10834	/ 28192 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10835	/ 28194 / GIR_RootConstrainSelectedInstOperands,
10836	/ 28195 / // GIR_Coverage, 1010,
10837	/ 28195 / GIR_EraseRootFromParent_Done,
10838	/ 28196 / // Label 904: @28196
10839	/ 28196 / GIM_Try_CheckFeatures, /On fail goto//Label 905/ GIMT_Encode4(`28240`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1011 //
10840	/ 28203 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srar_d),
10841	/ 28208 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10842	/ 28211 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10843	/ 28214 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10844	/ 28217 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10845	/ 28221 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10846	/ 28225 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10847	/* 28229 / // (intrinsic_wo_chain:{ :[v2i64] } 8613:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SRAR_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
10848	/ 28229 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRAR_D),
10849	/ 28232 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10850	/ 28234 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10851	/ 28236 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10852	/ 28238 / GIR_RootConstrainSelectedInstOperands,
10853	/ 28239 / // GIR_Coverage, 1011,
10854	/ 28239 / GIR_EraseRootFromParent_Done,
10855	/ 28240 / // Label 905: @28240
10856	/ 28240 / GIM_Try_CheckFeatures, /On fail goto//Label 906/ GIMT_Encode4(`28284`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1024 //
10857	/ 28247 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlr_b),
10858	/ 28252 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10859	/ 28255 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10860	/ 28258 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10861	/ 28261 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10862	/ 28265 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10863	/ 28269 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10864	/* 28273 / // (intrinsic_wo_chain:{ :[v16i8] } 8628:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SRLR_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10865	/ 28273 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLR_B),
10866	/ 28276 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10867	/ 28278 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10868	/ 28280 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10869	/ 28282 / GIR_RootConstrainSelectedInstOperands,
10870	/ 28283 / // GIR_Coverage, 1024,
10871	/ 28283 / GIR_EraseRootFromParent_Done,
10872	/ 28284 / // Label 906: @28284
10873	/ 28284 / GIM_Try_CheckFeatures, /On fail goto//Label 907/ GIMT_Encode4(`28328`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1025 //
10874	/ 28291 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlr_h),
10875	/ 28296 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10876	/ 28299 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10877	/ 28302 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10878	/ 28305 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10879	/ 28309 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10880	/ 28313 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10881	/* 28317 / // (intrinsic_wo_chain:{ :[v8i16] } 8630:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SRLR_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10882	/ 28317 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLR_H),
10883	/ 28320 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10884	/ 28322 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10885	/ 28324 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10886	/ 28326 / GIR_RootConstrainSelectedInstOperands,
10887	/ 28327 / // GIR_Coverage, 1025,
10888	/ 28327 / GIR_EraseRootFromParent_Done,
10889	/ 28328 / // Label 907: @28328
10890	/ 28328 / GIM_Try_CheckFeatures, /On fail goto//Label 908/ GIMT_Encode4(`28372`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1026 //
10891	/ 28335 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlr_w),
10892	/ 28340 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10893	/ 28343 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10894	/ 28346 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10895	/ 28349 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10896	/ 28353 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10897	/ 28357 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10898	/* 28361 / // (intrinsic_wo_chain:{ :[v4i32] } 8631:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SRLR_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10899	/ 28361 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLR_W),
10900	/ 28364 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10901	/ 28366 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10902	/ 28368 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10903	/ 28370 / GIR_RootConstrainSelectedInstOperands,
10904	/ 28371 / // GIR_Coverage, 1026,
10905	/ 28371 / GIR_EraseRootFromParent_Done,
10906	/ 28372 / // Label 908: @28372
10907	/ 28372 / GIM_Try_CheckFeatures, /On fail goto//Label 909/ GIMT_Encode4(`28416`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1027 //
10908	/ 28379 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_srlr_d),
10909	/ 28384 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10910	/ 28387 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10911	/ 28390 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10912	/ 28393 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10913	/ 28397 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10914	/ 28401 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10915	/* 28405 / // (intrinsic_wo_chain:{ :[v2i64] } 8629:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SRLR_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
10916	/ 28405 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRLR_D),
10917	/ 28408 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10918	/ 28410 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10919	/ 28412 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10920	/ 28414 / GIR_RootConstrainSelectedInstOperands,
10921	/ 28415 / // GIR_Coverage, 1027,
10922	/ 28415 / GIR_EraseRootFromParent_Done,
10923	/ 28416 / // Label 909: @28416
10924	/ 28416 / GIM_Try_CheckFeatures, /On fail goto//Label 910/ GIMT_Encode4(`28460`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1036 //
10925	/ 28423 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_s_b),
10926	/ 28428 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10927	/ 28431 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10928	/ 28434 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10929	/ 28437 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10930	/ 28441 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10931	/ 28445 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10932	/* 28449 / // (intrinsic_wo_chain:{ :[v16i8] } 8649:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SUBS_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
10933	/ 28449 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_S_B),
10934	/ 28452 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10935	/ 28454 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10936	/ 28456 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10937	/ 28458 / GIR_RootConstrainSelectedInstOperands,
10938	/ 28459 / // GIR_Coverage, 1036,
10939	/ 28459 / GIR_EraseRootFromParent_Done,
10940	/ 28460 / // Label 910: @28460
10941	/ 28460 / GIM_Try_CheckFeatures, /On fail goto//Label 911/ GIMT_Encode4(`28504`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1037 //
10942	/ 28467 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_s_h),
10943	/ 28472 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
10944	/ 28475 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
10945	/ 28478 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
10946	/ 28481 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10947	/ 28485 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10948	/ 28489 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
10949	/* 28493 / // (intrinsic_wo_chain:{ :[v8i16] } 8651:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SUBS_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
10950	/ 28493 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_S_H),
10951	/ 28496 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10952	/ 28498 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10953	/ 28500 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10954	/ 28502 / GIR_RootConstrainSelectedInstOperands,
10955	/ 28503 / // GIR_Coverage, 1037,
10956	/ 28503 / GIR_EraseRootFromParent_Done,
10957	/ 28504 / // Label 911: @28504
10958	/ 28504 / GIM_Try_CheckFeatures, /On fail goto//Label 912/ GIMT_Encode4(`28548`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1038 //
10959	/ 28511 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_s_w),
10960	/ 28516 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
10961	/ 28519 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
10962	/ 28522 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
10963	/ 28525 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10964	/ 28529 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10965	/ 28533 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
10966	/* 28537 / // (intrinsic_wo_chain:{ :[v4i32] } 8652:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SUBS_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
10967	/ 28537 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_S_W),
10968	/ 28540 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10969	/ 28542 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10970	/ 28544 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10971	/ 28546 / GIR_RootConstrainSelectedInstOperands,
10972	/ 28547 / // GIR_Coverage, 1038,
10973	/ 28547 / GIR_EraseRootFromParent_Done,
10974	/ 28548 / // Label 912: @28548
10975	/ 28548 / GIM_Try_CheckFeatures, /On fail goto//Label 913/ GIMT_Encode4(`28592`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1039 //
10976	/ 28555 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_s_d),
10977	/ 28560 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
10978	/ 28563 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
10979	/ 28566 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
10980	/ 28569 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10981	/ 28573 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10982	/ 28577 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
10983	/* 28581 / // (intrinsic_wo_chain:{ :[v2i64] } 8650:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SUBS_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
10984	/ 28581 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_S_D),
10985	/ 28584 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
10986	/ 28586 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
10987	/ 28588 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
10988	/ 28590 / GIR_RootConstrainSelectedInstOperands,
10989	/ 28591 / // GIR_Coverage, 1039,
10990	/ 28591 / GIR_EraseRootFromParent_Done,
10991	/ 28592 / // Label 913: @28592
10992	/ 28592 / GIM_Try_CheckFeatures, /On fail goto//Label 914/ GIMT_Encode4(`28636`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1040 //
10993	/ 28599 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_u_b),
10994	/ 28604 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
10995	/ 28607 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
10996	/ 28610 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
10997	/ 28613 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10998	/ 28617 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
10999	/ 28621 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11000	/* 28625 / // (intrinsic_wo_chain:{ :[v16i8] } 8653:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SUBS_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
11001	/ 28625 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_U_B),
11002	/ 28628 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11003	/ 28630 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11004	/ 28632 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11005	/ 28634 / GIR_RootConstrainSelectedInstOperands,
11006	/ 28635 / // GIR_Coverage, 1040,
11007	/ 28635 / GIR_EraseRootFromParent_Done,
11008	/ 28636 / // Label 914: @28636
11009	/ 28636 / GIM_Try_CheckFeatures, /On fail goto//Label 915/ GIMT_Encode4(`28680`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1041 //
11010	/ 28643 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11011	/ 28648 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
11012	/ 28651 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
11013	/ 28654 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
11014	/ 28657 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11015	/ 28661 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11016	/ 28665 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11017	/* 28669 / // (intrinsic_wo_chain:{ :[v8i16] } 8655:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SUBS_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
11018	/ 28669 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_U_H),
11019	/ 28672 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11020	/ 28674 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11021	/ 28676 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11022	/ 28678 / GIR_RootConstrainSelectedInstOperands,
11023	/ 28679 / // GIR_Coverage, 1041,
11024	/ 28679 / GIR_EraseRootFromParent_Done,
11025	/ 28680 / // Label 915: @28680
11026	/ 28680 / GIM_Try_CheckFeatures, /On fail goto//Label 916/ GIMT_Encode4(`28724`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1042 //
11027	/ 28687 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11028	/ 28692 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
11029	/ 28695 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
11030	/ 28698 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
11031	/ 28701 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11032	/ 28705 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11033	/ 28709 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11034	/* 28713 / // (intrinsic_wo_chain:{ :[v4i32] } 8656:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SUBS_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
11035	/ 28713 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_U_W),
11036	/ 28716 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11037	/ 28718 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11038	/ 28720 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11039	/ 28722 / GIR_RootConstrainSelectedInstOperands,
11040	/ 28723 / // GIR_Coverage, 1042,
11041	/ 28723 / GIR_EraseRootFromParent_Done,
11042	/ 28724 / // Label 916: @28724
11043	/ 28724 / GIM_Try_CheckFeatures, /On fail goto//Label 917/ GIMT_Encode4(`28768`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1043 //
11044	/ 28731 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11045	/ 28736 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
11046	/ 28739 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
11047	/ 28742 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
11048	/ 28745 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11049	/ 28749 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11050	/ 28753 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11051	/* 28757 / // (intrinsic_wo_chain:{ :[v2i64] } 8654:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SUBS_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
11052	/ 28757 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBS_U_D),
11053	/ 28760 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11054	/ 28762 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11055	/ 28764 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11056	/ 28766 / GIR_RootConstrainSelectedInstOperands,
11057	/ 28767 / // GIR_Coverage, 1043,
11058	/ 28767 / GIR_EraseRootFromParent_Done,
11059	/ 28768 / // Label 917: @28768
11060	/ 28768 / GIM_Try_CheckFeatures, /On fail goto//Label 918/ GIMT_Encode4(`28812`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1044 //
11061	/ 28775 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11062	/ 28780 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
11063	/ 28783 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
11064	/ 28786 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
11065	/ 28789 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11066	/ 28793 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11067	/ 28797 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11068	/* 28801 / // (intrinsic_wo_chain:{ :[v16i8] } 8657:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SUBSUS_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
11069	/ 28801 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUS_U_B),
11070	/ 28804 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11071	/ 28806 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11072	/ 28808 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11073	/ 28810 / GIR_RootConstrainSelectedInstOperands,
11074	/ 28811 / // GIR_Coverage, 1044,
11075	/ 28811 / GIR_EraseRootFromParent_Done,
11076	/ 28812 / // Label 918: @28812
11077	/ 28812 / GIM_Try_CheckFeatures, /On fail goto//Label 919/ GIMT_Encode4(`28856`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1045 //
11078	/ 28819 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11079	/ 28824 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
11080	/ 28827 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
11081	/ 28830 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
11082	/ 28833 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11083	/ 28837 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11084	/ 28841 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11085	/* 28845 / // (intrinsic_wo_chain:{ :[v8i16] } 8659:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SUBSUS_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
11086	/ 28845 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUS_U_H),
11087	/ 28848 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11088	/ 28850 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11089	/ 28852 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11090	/ 28854 / GIR_RootConstrainSelectedInstOperands,
11091	/ 28855 / // GIR_Coverage, 1045,
11092	/ 28855 / GIR_EraseRootFromParent_Done,
11093	/ 28856 / // Label 919: @28856
11094	/ 28856 / GIM_Try_CheckFeatures, /On fail goto//Label 920/ GIMT_Encode4(`28900`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1046 //
11095	/ 28863 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11096	/ 28868 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
11097	/ 28871 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
11098	/ 28874 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
11099	/ 28877 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11100	/ 28881 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11101	/ 28885 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11102	/* 28889 / // (intrinsic_wo_chain:{ :[v4i32] } 8660:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SUBSUS_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
11103	/ 28889 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUS_U_W),
11104	/ 28892 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11105	/ 28894 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11106	/ 28896 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11107	/ 28898 / GIR_RootConstrainSelectedInstOperands,
11108	/ 28899 / // GIR_Coverage, 1046,
11109	/ 28899 / GIR_EraseRootFromParent_Done,
11110	/ 28900 / // Label 920: @28900
11111	/ 28900 / GIM_Try_CheckFeatures, /On fail goto//Label 921/ GIMT_Encode4(`28944`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1047 //
11112	/ 28907 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11113	/ 28912 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
11114	/ 28915 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
11115	/ 28918 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
11116	/ 28921 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11117	/ 28925 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11118	/ 28929 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11119	/* 28933 / // (intrinsic_wo_chain:{ :[v2i64] } 8658:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SUBSUS_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
11120	/ 28933 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUS_U_D),
11121	/ 28936 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11122	/ 28938 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11123	/ 28940 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11124	/ 28942 / GIR_RootConstrainSelectedInstOperands,
11125	/ 28943 / // GIR_Coverage, 1047,
11126	/ 28943 / GIR_EraseRootFromParent_Done,
11127	/ 28944 / // Label 921: @28944
11128	/ 28944 / GIM_Try_CheckFeatures, /On fail goto//Label 922/ GIMT_Encode4(`28988`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1048 //
11129	/ 28951 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11130	/ 28956 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
11131	/ 28959 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
11132	/ 28962 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
11133	/ 28965 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11134	/ 28969 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11135	/ 28973 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11136	/* 28977 / // (intrinsic_wo_chain:{ :[v16i8] } 8661:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SUBSUU_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
11137	/ 28977 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUU_S_B),
11138	/ 28980 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11139	/ 28982 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11140	/ 28984 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11141	/ 28986 / GIR_RootConstrainSelectedInstOperands,
11142	/ 28987 / // GIR_Coverage, 1048,
11143	/ 28987 / GIR_EraseRootFromParent_Done,
11144	/ 28988 / // Label 922: @28988
11145	/ 28988 / GIM_Try_CheckFeatures, /On fail goto//Label 923/ GIMT_Encode4(`29032`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1049 //
11146	/ 28995 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11147	/ 29000 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
11148	/ 29003 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
11149	/ 29006 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
11150	/ 29009 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11151	/ 29013 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11152	/ 29017 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11153	/* 29021 / // (intrinsic_wo_chain:{ :[v8i16] } 8663:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SUBSUU_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
11154	/ 29021 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUU_S_H),
11155	/ 29024 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11156	/ 29026 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11157	/ 29028 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11158	/ 29030 / GIR_RootConstrainSelectedInstOperands,
11159	/ 29031 / // GIR_Coverage, 1049,
11160	/ 29031 / GIR_EraseRootFromParent_Done,
11161	/ 29032 / // Label 923: @29032
11162	/ 29032 / GIM_Try_CheckFeatures, /On fail goto//Label 924/ GIMT_Encode4(`29076`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1050 //
11163	/ 29039 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11164	/ 29044 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
11165	/ 29047 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
11166	/ 29050 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
11167	/ 29053 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11168	/ 29057 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11169	/ 29061 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11170	/* 29065 / // (intrinsic_wo_chain:{ :[v4i32] } 8664:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SUBSUU_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
11171	/ 29065 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUU_S_W),
11172	/ 29068 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11173	/ 29070 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11174	/ 29072 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11175	/ 29074 / GIR_RootConstrainSelectedInstOperands,
11176	/ 29075 / // GIR_Coverage, 1050,
11177	/ 29075 / GIR_EraseRootFromParent_Done,
11178	/ 29076 / // Label 924: @29076
11179	/ 29076 / GIM_Try_CheckFeatures, /On fail goto//Label 925/ GIMT_Encode4(`29120`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1051 //
11180	/ 29083 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
11181	/ 29088 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
11182	/ 29091 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
11183	/ 29094 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
11184	/ 29097 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11185	/ 29101 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11186	/ 29105 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11187	/* 29109 / // (intrinsic_wo_chain:{ :[v2i64] } 8662:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SUBSUU_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
11188	/ 29109 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBSUU_S_D),
11189	/ 29112 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11190	/ 29114 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
11191	/ 29116 / GIR_RootToRootCopy, /OpIdx/`3`, // wt
11192	/ 29118 / GIR_RootConstrainSelectedInstOperands,
11193	/ 29119 / // GIR_Coverage, 1051,
11194	/ 29119 / GIR_EraseRootFromParent_Done,
11195	/ 29120 / // Label 925: @29120
11196	/ 29120 / GIM_Try_CheckFeatures, /On fail goto//Label 926/ GIMT_Encode4(`29167`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1244 //
11197	/ 29127 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
11198	/ 29132 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11199	/ 29135 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11200	/ 29138 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11201	/ 29141 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11202	/ 29145 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11203	/ 29149 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11204	/* 29153 / // (intrinsic_wo_chain:{ :[v2i16] } 8023:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11205	/ 29153 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
11206	/ 29156 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11207	/ 29158 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11208	/ 29160 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11209	/ 29162 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11210	/ 29165 / GIR_RootConstrainSelectedInstOperands,
11211	/ 29166 / // GIR_Coverage, 1244,
11212	/ 29166 / GIR_EraseRootFromParent_Done,
11213	/ 29167 / // Label 926: @29167
11214	/ 29167 / GIM_Try_CheckFeatures, /On fail goto//Label 927/ GIMT_Encode4(`29214`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1246 //
11215	/ 29174 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
11216	/ 29179 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11217	/ 29182 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11218	/ 29185 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11219	/ 29188 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11220	/ 29192 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11221	/ 29196 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11222	/* 29200 / // (intrinsic_wo_chain:{ :[v4i8] } 8045:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDU_S_QB_MM:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11223	/ 29200 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_S_QB_MM),
11224	/ 29203 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11225	/ 29205 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11226	/ 29207 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11227	/ 29209 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11228	/ 29212 / GIR_RootConstrainSelectedInstOperands,
11229	/ 29213 / // GIR_Coverage, 1246,
11230	/ 29213 / GIR_EraseRootFromParent_Done,
11231	/ 29214 / // Label 927: @29214
11232	/ 29214 / GIM_Try_CheckFeatures, /On fail goto//Label 928/ GIMT_Encode4(`29258`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1267 //
11233	/ 29221 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_ph),
11234	/ 29226 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11235	/ 29229 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11236	/ 29232 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11237	/ 29235 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11238	/ 29239 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11239	/ 29243 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11240	/* 29247 / // (intrinsic_wo_chain:{ :[v2i16] } 8573:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRAV_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11241	/ 29247 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_PH_MM),
11242	/ 29250 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11243	/ 29252 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11244	/ 29254 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11245	/ 29256 / GIR_RootConstrainSelectedInstOperands,
11246	/ 29257 / // GIR_Coverage, 1267,
11247	/ 29257 / GIR_EraseRootFromParent_Done,
11248	/ 29258 / // Label 928: @29258
11249	/ 29258 / GIM_Try_CheckFeatures, /On fail goto//Label 929/ GIMT_Encode4(`29302`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1268 //
11250	/ 29265 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
11251	/ 29270 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11252	/ 29273 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11253	/ 29276 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11254	/ 29279 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11255	/ 29283 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11256	/ 29287 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11257	/* 29291 / // (intrinsic_wo_chain:{ :[v2i16] } 8575:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRAV_R_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11258	/ 29291 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
11259	/ 29294 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11260	/ 29296 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11261	/ 29298 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11262	/ 29300 / GIR_RootConstrainSelectedInstOperands,
11263	/ 29301 / // GIR_Coverage, 1268,
11264	/ 29301 / GIR_EraseRootFromParent_Done,
11265	/ 29302 / // Label 929: @29302
11266	/ 29302 / GIM_Try_CheckFeatures, /On fail goto//Label 930/ GIMT_Encode4(`29346`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1269 //
11267	/ 29309 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_w),
11268	/ 29314 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11269	/ 29317 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11270	/ 29320 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11271	/ 29323 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11272	/ 29327 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11273	/ 29331 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11274	/* 29335 / // (intrinsic_wo_chain:{ :[i32] } 8577:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRAV_R_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11275	/ 29335 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_W_MM),
11276	/ 29338 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11277	/ 29340 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11278	/ 29342 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11279	/ 29344 / GIR_RootConstrainSelectedInstOperands,
11280	/ 29345 / // GIR_Coverage, 1269,
11281	/ 29345 / GIR_EraseRootFromParent_Done,
11282	/ 29346 / // Label 930: @29346
11283	/ 29346 / GIM_Try_CheckFeatures, /On fail goto//Label 931/ GIMT_Encode4(`29390`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1271 //
11284	/ 29353 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_qb),
11285	/ 29358 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11286	/ 29361 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11287	/ 29364 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11288	/ 29367 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11289	/ 29371 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11290	/ 29375 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11291	/* 29379 / // (intrinsic_wo_chain:{ :[v4i8] } 8579:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRLV_QB_MM:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11292	/ 29379 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRLV_QB_MM),
11293	/ 29382 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11294	/ 29384 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11295	/ 29386 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11296	/ 29388 / GIR_RootConstrainSelectedInstOperands,
11297	/ 29389 / // GIR_Coverage, 1271,
11298	/ 29389 / GIR_EraseRootFromParent_Done,
11299	/ 29390 / // Label 931: @29390
11300	/ 29390 / GIM_Try_CheckFeatures, /On fail goto//Label 932/ GIMT_Encode4(`29437`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1282 //
11301	/ 29397 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
11302	/ 29402 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11303	/ 29405 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11304	/ 29408 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11305	/ 29411 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11306	/ 29415 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11307	/ 29419 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11308	/* 29423 / // (intrinsic_wo_chain:{ :[v2i16] } 8643:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11309	/ 29423 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
11310	/ 29426 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11311	/ 29428 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11312	/ 29430 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11313	/ 29432 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11314	/ 29435 / GIR_RootConstrainSelectedInstOperands,
11315	/ 29436 / // GIR_Coverage, 1282,
11316	/ 29436 / GIR_EraseRootFromParent_Done,
11317	/ 29437 / // Label 932: @29437
11318	/ 29437 / GIM_Try_CheckFeatures, /On fail goto//Label 933/ GIMT_Encode4(`29484`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1284 //
11319	/ 29444 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
11320	/ 29449 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11321	/ 29452 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11322	/ 29455 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11323	/ 29458 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11324	/ 29462 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11325	/ 29466 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11326	/* 29470 / // (intrinsic_wo_chain:{ :[v4i8] } 8668:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBU_S_QB_MM:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11327	/ 29470 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_S_QB_MM),
11328	/ 29473 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11329	/ 29475 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11330	/ 29477 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11331	/ 29479 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11332	/ 29482 / GIR_RootConstrainSelectedInstOperands,
11333	/ 29483 / // GIR_Coverage, 1284,
11334	/ 29483 / GIR_EraseRootFromParent_Done,
11335	/ 29484 / // Label 933: @29484
11336	/ 29484 / GIM_Try_CheckFeatures, /On fail goto//Label 934/ GIMT_Encode4(`29528`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1294 //
11337	/ 29491 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
11338	/ 29496 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11339	/ 29499 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11340	/ 29502 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11341	/ 29505 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11342	/ 29509 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11343	/ 29513 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11344	/* 29517 / // (intrinsic_wo_chain:{ :[v2i16] } 8548:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (PRECRQ_PH_W_MM:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11345	/ 29517 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
11346	/ 29520 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11347	/ 29522 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11348	/ 29524 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11349	/ 29526 / GIR_RootConstrainSelectedInstOperands,
11350	/ 29527 / // GIR_Coverage, 1294,
11351	/ 29527 / GIR_EraseRootFromParent_Done,
11352	/ 29528 / // Label 934: @29528
11353	/ 29528 / GIM_Try_CheckFeatures, /On fail goto//Label 935/ GIMT_Encode4(`29572`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1295 //
11354	/ 29535 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
11355	/ 29540 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11356	/ 29543 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11357	/ 29546 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11358	/ 29549 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11359	/ 29553 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11360	/ 29557 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11361	/* 29561 / // (intrinsic_wo_chain:{ :[v4i8] } 8549:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11362	/ 29561 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
11363	/ 29564 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11364	/ 29566 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11365	/ 29568 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11366	/ 29570 / GIR_RootConstrainSelectedInstOperands,
11367	/ 29571 / // GIR_Coverage, 1295,
11368	/ 29571 / GIR_EraseRootFromParent_Done,
11369	/ 29572 / // Label 935: @29572
11370	/ 29572 / GIM_Try_CheckFeatures, /On fail goto//Label 936/ GIMT_Encode4(`29616`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1314 //
11371	/ 29579 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_packrl_ph),
11372	/ 29584 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11373	/ 29587 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11374	/ 29590 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11375	/ 29593 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11376	/ 29597 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11377	/ 29601 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11378	/* 29605 / // (intrinsic_wo_chain:{ :[v2i16] } 8520:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PACKRL_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11379	/ 29605 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PACKRL_PH_MM),
11380	/ 29608 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11381	/ 29610 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11382	/ 29612 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11383	/ 29614 / GIR_RootConstrainSelectedInstOperands,
11384	/ 29615 / // GIR_Coverage, 1314,
11385	/ 29615 / GIR_EraseRootFromParent_Done,
11386	/ 29616 / // Label 936: @29616
11387	/ 29616 / GIM_Try_CheckFeatures, /On fail goto//Label 937/ GIMT_Encode4(`29660`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1320 //
11388	/ 29623 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_modsub),
11389	/ 29628 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11390	/ 29631 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11391	/ 29634 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11392	/ 29637 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11393	/ 29641 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11394	/ 29645 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11395	/* 29649 / // (intrinsic_wo_chain:{ :[i32] } 8473:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MODSUB_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11396	/ 29649 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MODSUB_MM),
11397	/ 29652 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11398	/ 29654 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11399	/ 29656 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11400	/ 29658 / GIR_RootConstrainSelectedInstOperands,
11401	/ 29659 / // GIR_Coverage, 1320,
11402	/ 29659 / GIR_EraseRootFromParent_Done,
11403	/ 29660 / // Label 937: @29660
11404	/ 29660 / GIM_Try_CheckFeatures, /On fail goto//Label 938/ GIMT_Encode4(`29704`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1333 //
11405	/ 29667 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_ph),
11406	/ 29672 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11407	/ 29675 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11408	/ 29678 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11409	/ 29681 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11410	/ 29685 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11411	/ 29689 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11412	/* 29693 / // (intrinsic_wo_chain:{ :[v2i16] } 8025:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11413	/ 29693 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
11414	/ 29696 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11415	/ 29698 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11416	/ 29700 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11417	/ 29702 / GIR_RootConstrainSelectedInstOperands,
11418	/ 29703 / // GIR_Coverage, 1333,
11419	/ 29703 / GIR_EraseRootFromParent_Done,
11420	/ 29704 / // Label 938: @29704
11421	/ 29704 / GIM_Try_CheckFeatures, /On fail goto//Label 939/ GIMT_Encode4(`29748`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1334 //
11422	/ 29711 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
11423	/ 29716 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11424	/ 29719 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11425	/ 29722 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11426	/ 29725 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11427	/ 29729 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11428	/ 29733 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11429	/* 29737 / // (intrinsic_wo_chain:{ :[v2i16] } 8026:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11430	/ 29737 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
11431	/ 29740 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11432	/ 29742 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11433	/ 29744 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11434	/ 29746 / GIR_RootConstrainSelectedInstOperands,
11435	/ 29747 / // GIR_Coverage, 1334,
11436	/ 29747 / GIR_EraseRootFromParent_Done,
11437	/ 29748 / // Label 939: @29748
11438	/ 29748 / GIM_Try_CheckFeatures, /On fail goto//Label 940/ GIMT_Encode4(`29792`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1335 //
11439	/ 29755 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_w),
11440	/ 29760 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11441	/ 29763 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11442	/ 29766 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11443	/ 29769 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11444	/ 29773 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11445	/ 29777 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11446	/* 29781 / // (intrinsic_wo_chain:{ :[i32] } 8028:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQH_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11447	/ 29781 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_W_MMR2),
11448	/ 29784 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11449	/ 29786 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11450	/ 29788 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11451	/ 29790 / GIR_RootConstrainSelectedInstOperands,
11452	/ 29791 / // GIR_Coverage, 1335,
11453	/ 29791 / GIR_EraseRootFromParent_Done,
11454	/ 29792 / // Label 940: @29792
11455	/ 29792 / GIM_Try_CheckFeatures, /On fail goto//Label 941/ GIMT_Encode4(`29836`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1336 //
11456	/ 29799 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
11457	/ 29804 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11458	/ 29807 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11459	/ 29810 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11460	/ 29813 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11461	/ 29817 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11462	/ 29821 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11463	/* 29825 / // (intrinsic_wo_chain:{ :[i32] } 8027:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQH_R_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11464	/ 29825 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
11465	/ 29828 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11466	/ 29830 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11467	/ 29832 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11468	/ 29834 / GIR_RootConstrainSelectedInstOperands,
11469	/ 29835 / // GIR_Coverage, 1336,
11470	/ 29835 / GIR_EraseRootFromParent_Done,
11471	/ 29836 / // Label 941: @29836
11472	/ 29836 / GIM_Try_CheckFeatures, /On fail goto//Label 942/ GIMT_Encode4(`29880`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1339 //
11473	/ 29843 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adduh_qb),
11474	/ 29848 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11475	/ 29851 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11476	/ 29854 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11477	/ 29857 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11478	/ 29861 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11479	/ 29865 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11480	/* 29869 / // (intrinsic_wo_chain:{ :[v4i8] } 8046:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11481	/ 29869 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
11482	/ 29872 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11483	/ 29874 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11484	/ 29876 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11485	/ 29878 / GIR_RootConstrainSelectedInstOperands,
11486	/ 29879 / // GIR_Coverage, 1339,
11487	/ 29879 / GIR_EraseRootFromParent_Done,
11488	/ 29880 / // Label 942: @29880
11489	/ 29880 / GIM_Try_CheckFeatures, /On fail goto//Label 943/ GIMT_Encode4(`29924`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1340 //
11490	/ 29887 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
11491	/ 29892 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11492	/ 29895 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11493	/ 29898 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11494	/ 29901 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11495	/ 29905 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11496	/ 29909 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11497	/* 29913 / // (intrinsic_wo_chain:{ :[v4i8] } 8047:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11498	/ 29913 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
11499	/ 29916 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11500	/ 29918 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11501	/ 29920 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11502	/ 29922 / GIR_RootConstrainSelectedInstOperands,
11503	/ 29923 / // GIR_Coverage, 1340,
11504	/ 29923 / GIR_EraseRootFromParent_Done,
11505	/ 29924 / // Label 943: @29924
11506	/ 29924 / GIM_Try_CheckFeatures, /On fail goto//Label 944/ GIMT_Encode4(`29968`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1346 //
11507	/ 29931 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_qb),
11508	/ 29936 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11509	/ 29939 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11510	/ 29942 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11511	/ 29945 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11512	/ 29949 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11513	/ 29953 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11514	/* 29957 / // (intrinsic_wo_chain:{ :[v4i8] } 8574:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRAV_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11515	/ 29957 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
11516	/ 29960 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11517	/ 29962 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11518	/ 29964 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11519	/ 29966 / GIR_RootConstrainSelectedInstOperands,
11520	/ 29967 / // GIR_Coverage, 1346,
11521	/ 29967 / GIR_EraseRootFromParent_Done,
11522	/ 29968 / // Label 944: @29968
11523	/ 29968 / GIM_Try_CheckFeatures, /On fail goto//Label 945/ GIMT_Encode4(`30012`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1347 //
11524	/ 29975 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
11525	/ 29980 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11526	/ 29983 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11527	/ 29986 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11528	/ 29989 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11529	/ 29993 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11530	/ 29997 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11531	/* 30001 / // (intrinsic_wo_chain:{ :[v4i8] } 8576:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11532	/ 30001 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
11533	/ 30004 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11534	/ 30006 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11535	/ 30008 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11536	/ 30010 / GIR_RootConstrainSelectedInstOperands,
11537	/ 30011 / // GIR_Coverage, 1347,
11538	/ 30011 / GIR_EraseRootFromParent_Done,
11539	/ 30012 / // Label 945: @30012
11540	/ 30012 / GIM_Try_CheckFeatures, /On fail goto//Label 946/ GIMT_Encode4(`30056`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1352 //
11541	/ 30019 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shrl_ph),
11542	/ 30024 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11543	/ 30027 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11544	/ 30030 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11545	/ 30033 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11546	/ 30037 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11547	/ 30041 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11548	/* 30045 / // (intrinsic_wo_chain:{ :[v2i16] } 8578:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHRLV_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
11549	/ 30045 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
11550	/ 30048 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11551	/ 30050 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
11552	/ 30052 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11553	/ 30054 / GIR_RootConstrainSelectedInstOperands,
11554	/ 30055 / // GIR_Coverage, 1352,
11555	/ 30055 / GIR_EraseRootFromParent_Done,
11556	/ 30056 / // Label 946: @30056
11557	/ 30056 / GIM_Try_CheckFeatures, /On fail goto//Label 947/ GIMT_Encode4(`30100`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1353 //
11558	/ 30063 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_ph),
11559	/ 30068 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11560	/ 30071 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11561	/ 30074 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11562	/ 30077 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11563	/ 30081 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11564	/ 30085 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11565	/* 30089 / // (intrinsic_wo_chain:{ :[v2i16] } 8645:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11566	/ 30089 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
11567	/ 30092 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11568	/ 30094 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11569	/ 30096 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11570	/ 30098 / GIR_RootConstrainSelectedInstOperands,
11571	/ 30099 / // GIR_Coverage, 1353,
11572	/ 30099 / GIR_EraseRootFromParent_Done,
11573	/ 30100 / // Label 947: @30100
11574	/ 30100 / GIM_Try_CheckFeatures, /On fail goto//Label 948/ GIMT_Encode4(`30144`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1354 //
11575	/ 30107 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
11576	/ 30112 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11577	/ 30115 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11578	/ 30118 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11579	/ 30121 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11580	/ 30125 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11581	/ 30129 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11582	/* 30133 / // (intrinsic_wo_chain:{ :[v2i16] } 8646:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
11583	/ 30133 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
11584	/ 30136 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11585	/ 30138 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11586	/ 30140 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11587	/ 30142 / GIR_RootConstrainSelectedInstOperands,
11588	/ 30143 / // GIR_Coverage, 1354,
11589	/ 30143 / GIR_EraseRootFromParent_Done,
11590	/ 30144 / // Label 948: @30144
11591	/ 30144 / GIM_Try_CheckFeatures, /On fail goto//Label 949/ GIMT_Encode4(`30188`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1355 //
11592	/ 30151 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_w),
11593	/ 30156 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11594	/ 30159 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11595	/ 30162 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11596	/ 30165 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11597	/ 30169 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11598	/ 30173 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11599	/* 30177 / // (intrinsic_wo_chain:{ :[i32] } 8648:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQH_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11600	/ 30177 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_W_MMR2),
11601	/ 30180 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11602	/ 30182 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11603	/ 30184 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11604	/ 30186 / GIR_RootConstrainSelectedInstOperands,
11605	/ 30187 / // GIR_Coverage, 1355,
11606	/ 30187 / GIR_EraseRootFromParent_Done,
11607	/ 30188 / // Label 949: @30188
11608	/ 30188 / GIM_Try_CheckFeatures, /On fail goto//Label 950/ GIMT_Encode4(`30232`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1356 //
11609	/ 30195 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
11610	/ 30200 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11611	/ 30203 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11612	/ 30206 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11613	/ 30209 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11614	/ 30213 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11615	/ 30217 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11616	/* 30221 / // (intrinsic_wo_chain:{ :[i32] } 8647:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQH_R_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
11617	/ 30221 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
11618	/ 30224 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11619	/ 30226 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11620	/ 30228 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11621	/ 30230 / GIR_RootConstrainSelectedInstOperands,
11622	/ 30231 / // GIR_Coverage, 1356,
11623	/ 30231 / GIR_EraseRootFromParent_Done,
11624	/ 30232 / // Label 950: @30232
11625	/ 30232 / GIM_Try_CheckFeatures, /On fail goto//Label 951/ GIMT_Encode4(`30276`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1359 //
11626	/ 30239 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subuh_qb),
11627	/ 30244 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11628	/ 30247 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11629	/ 30250 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11630	/ 30253 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11631	/ 30257 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11632	/ 30261 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11633	/* 30265 / // (intrinsic_wo_chain:{ :[v4i8] } 8669:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11634	/ 30265 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
11635	/ 30268 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11636	/ 30270 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11637	/ 30272 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11638	/ 30274 / GIR_RootConstrainSelectedInstOperands,
11639	/ 30275 / // GIR_Coverage, 1359,
11640	/ 30275 / GIR_EraseRootFromParent_Done,
11641	/ 30276 / // Label 951: @30276
11642	/ 30276 / GIM_Try_CheckFeatures, /On fail goto//Label 952/ GIMT_Encode4(`30320`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1360 //
11643	/ 30283 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
11644	/ 30288 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11645	/ 30291 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11646	/ 30294 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11647	/ 30297 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11648	/ 30301 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11649	/ 30305 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11650	/* 30309 / // (intrinsic_wo_chain:{ :[v4i8] } 8670:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
11651	/ 30309 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
11652	/ 30312 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11653	/ 30314 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
11654	/ 30316 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
11655	/ 30318 / GIR_RootConstrainSelectedInstOperands,
11656	/ 30319 / // GIR_Coverage, 1360,
11657	/ 30319 / GIR_EraseRootFromParent_Done,
11658	/ 30320 / // Label 952: @30320
11659	/ 30320 / GIM_Try_CheckFeatures, /On fail goto//Label 953/ GIMT_Encode4(`30359`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2052 //
11660	/ 30327 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addq_ph),
11661	/ 30332 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11662	/ 30335 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11663	/ 30338 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11664	/ 30341 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11665	/ 30345 / // (intrinsic_wo_chain:{ :[v2i16] } 8022:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (ADDQ_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)*
11666	/ 30345 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQ_PH),
11667	/ 30348 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11668	/ 30350 / GIR_RootToRootCopy, /OpIdx/`2`, // a
11669	/ 30352 / GIR_RootToRootCopy, /OpIdx/`3`, // b
11670	/ 30354 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11671	/ 30357 / GIR_RootConstrainSelectedInstOperands,
11672	/ 30358 / // GIR_Coverage, 2052,
11673	/ 30358 / GIR_EraseRootFromParent_Done,
11674	/ 30359 / // Label 953: @30359
11675	/ 30359 / GIM_Try_CheckFeatures, /On fail goto//Label 954/ GIMT_Encode4(`30398`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2054 //
11676	/ 30366 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subq_ph),
11677	/ 30371 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11678	/ 30374 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
11679	/ 30377 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
11680	/ 30380 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11681	/ 30384 / // (intrinsic_wo_chain:{ :[v2i16] } 8642:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (SUBQ_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)*
11682	/ 30384 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQ_PH),
11683	/ 30387 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11684	/ 30389 / GIR_RootToRootCopy, /OpIdx/`2`, // a
11685	/ 30391 / GIR_RootToRootCopy, /OpIdx/`3`, // b
11686	/ 30393 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11687	/ 30396 / GIR_RootConstrainSelectedInstOperands,
11688	/ 30397 / // GIR_Coverage, 2054,
11689	/ 30397 / GIR_EraseRootFromParent_Done,
11690	/ 30398 / // Label 954: @30398
11691	/ 30398 / GIM_Try_CheckFeatures, /On fail goto//Label 955/ GIMT_Encode4(`30437`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2058 //
11692	/ 30405 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_qb),
11693	/ 30410 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11694	/ 30413 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11695	/ 30416 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11696	/ 30419 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11697	/ 30423 / // (intrinsic_wo_chain:{ :[v4i8] } 8043:{ :[iPTR] }, v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b) => (ADDU_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b)*
11698	/ 30423 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_QB),
11699	/ 30426 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11700	/ 30428 / GIR_RootToRootCopy, /OpIdx/`2`, // a
11701	/ 30430 / GIR_RootToRootCopy, /OpIdx/`3`, // b
11702	/ 30432 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11703	/ 30435 / GIR_RootConstrainSelectedInstOperands,
11704	/ 30436 / // GIR_Coverage, 2058,
11705	/ 30436 / GIR_EraseRootFromParent_Done,
11706	/ 30437 / // Label 955: @30437
11707	/ 30437 / GIM_Try_CheckFeatures, /On fail goto//Label 956/ GIMT_Encode4(`30476`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2060 //
11708	/ 30444 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_qb),
11709	/ 30449 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
11710	/ 30452 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
11711	/ 30455 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
11712	/ 30458 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11713	/ 30462 / // (intrinsic_wo_chain:{ :[v4i8] } 8666:{ :[iPTR] }, v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b) => (SUBU_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, v4i8:{ :[v4i8] }:$b)*
11714	/ 30462 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_QB),
11715	/ 30465 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
11716	/ 30467 / GIR_RootToRootCopy, /OpIdx/`2`, // a
11717	/ 30469 / GIR_RootToRootCopy, /OpIdx/`3`, // b
11718	/ 30471 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
11719	/ 30474 / GIR_RootConstrainSelectedInstOperands,
11720	/ 30475 / // GIR_Coverage, 2060,
11721	/ 30475 / GIR_EraseRootFromParent_Done,
11722	/ 30476 / // Label 956: @30476
11723	/ 30476 / GIM_Reject,
11724	/ 30477 / // Label 742: @30477
11725	/ 30477 / GIM_Try, /On fail goto//Label 957/ GIMT_Encode4(`32945`),
11726	/ 30482 / GIM_CheckNumOperands, /MI/`0`, /Expected/`5`,
11727	/ 30485 / GIM_Try_CheckFeatures, /On fail goto//Label 958/ GIMT_Encode4(`30539`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 504 //
11728	/ 30492 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11729	/ 30497 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11730	/ 30500 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11731	/ 30503 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11732	/ 30506 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11733	/ 30510 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11734	/ 30514 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11735	/ 30518 / // MIs[0] sa
11736	/ 30518 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11737	/ 30521 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11738	/* 30526 / // (intrinsic_wo_chain:{ :[v2i16] } 8546:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11739	/ 30526 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
11740	/ 30529 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11741	/ 30531 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11742	/ 30533 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11743	/ 30535 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11744	/ 30537 / GIR_RootConstrainSelectedInstOperands,
11745	/ 30538 / // GIR_Coverage, 504,
11746	/ 30538 / GIR_EraseRootFromParent_Done,
11747	/ 30539 / // Label 958: @30539
11748	/ 30539 / GIM_Try_CheckFeatures, /On fail goto//Label 959/ GIMT_Encode4(`30593`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 505 //
11749	/ 30546 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11750	/ 30551 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11751	/ 30554 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11752	/ 30557 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11753	/ 30560 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11754	/ 30564 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11755	/ 30568 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11756	/ 30572 / // MIs[0] sa
11757	/ 30572 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11758	/ 30575 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11759	/* 30580 / // (intrinsic_wo_chain:{ :[v2i16] } 8547:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11760	/ 30580 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
11761	/ 30583 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11762	/ 30585 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11763	/ 30587 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11764	/ 30589 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11765	/ 30591 / GIR_RootConstrainSelectedInstOperands,
11766	/ 30592 / // GIR_Coverage, 505,
11767	/ 30592 / GIR_EraseRootFromParent_Done,
11768	/ 30593 / // Label 959: @30593
11769	/ 30593 / GIM_Try_CheckFeatures, /On fail goto//Label 960/ GIMT_Encode4(`30647`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 510 //
11770	/ 30600 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_append),
11771	/ 30605 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11772	/ 30608 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11773	/ 30611 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11774	/ 30614 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11775	/ 30618 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11776	/ 30622 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11777	/ 30626 / // MIs[0] sa
11778	/ 30626 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11779	/ 30629 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11780	/* 30634 / // (intrinsic_wo_chain:{ :[i32] } 8059:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11781	/ 30634 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::APPEND),
11782	/ 30637 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11783	/ 30639 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11784	/ 30641 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11785	/ 30643 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11786	/ 30645 / GIR_RootConstrainSelectedInstOperands,
11787	/ 30646 / // GIR_Coverage, 510,
11788	/ 30646 / GIR_EraseRootFromParent_Done,
11789	/ 30647 / // Label 960: @30647
11790	/ 30647 / GIM_Try_CheckFeatures, /On fail goto//Label 961/ GIMT_Encode4(`30701`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 511 //
11791	/ 30654 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_balign),
11792	/ 30659 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11793	/ 30662 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11794	/ 30665 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11795	/ 30668 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11796	/ 30672 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11797	/ 30676 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11798	/ 30680 / // MIs[0] sa
11799	/ 30680 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11800	/ 30683 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11801	/* 30688 / // (intrinsic_wo_chain:{ :[i32] } 8084:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11802	/ 30688 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BALIGN),
11803	/ 30691 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11804	/ 30693 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11805	/ 30695 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11806	/ 30697 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11807	/ 30699 / GIR_RootConstrainSelectedInstOperands,
11808	/ 30700 / // GIR_Coverage, 511,
11809	/ 30700 / GIR_EraseRootFromParent_Done,
11810	/ 30701 / // Label 961: @30701
11811	/ 30701 / GIM_Try_CheckFeatures, /On fail goto//Label 962/ GIMT_Encode4(`30755`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 512 //
11812	/ 30708 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_prepend),
11813	/ 30713 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11814	/ 30716 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11815	/ 30719 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11816	/ 30722 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11817	/ 30726 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11818	/ 30730 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11819	/ 30734 / // MIs[0] sa
11820	/ 30734 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11821	/ 30737 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11822	/* 30742 / // (intrinsic_wo_chain:{ :[i32] } 8552:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11823	/ 30742 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PREPEND),
11824	/ 30745 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11825	/ 30747 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11826	/ 30749 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11827	/ 30751 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11828	/ 30753 / GIR_RootConstrainSelectedInstOperands,
11829	/ 30754 / // GIR_Coverage, 512,
11830	/ 30754 / GIR_EraseRootFromParent_Done,
11831	/ 30755 / // Label 962: @30755
11832	/ 30755 / GIM_Try_CheckFeatures, /On fail goto//Label 963/ GIMT_Encode4(`30809`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 980 //
11833	/ 30762 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sldi_b),
11834	/ 30767 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
11835	/ 30770 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
11836	/ 30773 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
11837	/ 30776 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11838	/ 30780 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11839	/ 30784 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
11840	/ 30788 / // MIs[0] n
11841	/ 30788 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11842	/ 30791 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
11843	/* 30796 / // (intrinsic_wo_chain:{ :[v16i8] } 8584:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, (timm:{ :[i32] }):$n)
11844	/ 30796 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLDI_B),
11845	/ 30799 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11846	/ 30801 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
11847	/ 30803 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
11848	/ 30805 / GIR_RootToRootCopy, /OpIdx/`4`, // n
11849	/ 30807 / GIR_RootConstrainSelectedInstOperands,
11850	/ 30808 / // GIR_Coverage, 980,
11851	/ 30808 / GIR_EraseRootFromParent_Done,
11852	/ 30809 / // Label 963: @30809
11853	/ 30809 / GIM_Try_CheckFeatures, /On fail goto//Label 964/ GIMT_Encode4(`30863`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 981 //
11854	/ 30816 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sldi_h),
11855	/ 30821 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
11856	/ 30824 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
11857	/ 30827 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
11858	/ 30830 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11859	/ 30834 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11860	/ 30838 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
11861	/ 30842 / // MIs[0] n
11862	/ 30842 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11863	/ 30845 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
11864	/* 30850 / // (intrinsic_wo_chain:{ :[v8i16] } 8586:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, (timm:{ :[i32] }):$n)
11865	/ 30850 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLDI_H),
11866	/ 30853 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11867	/ 30855 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
11868	/ 30857 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
11869	/ 30859 / GIR_RootToRootCopy, /OpIdx/`4`, // n
11870	/ 30861 / GIR_RootConstrainSelectedInstOperands,
11871	/ 30862 / // GIR_Coverage, 981,
11872	/ 30862 / GIR_EraseRootFromParent_Done,
11873	/ 30863 / // Label 964: @30863
11874	/ 30863 / GIM_Try_CheckFeatures, /On fail goto//Label 965/ GIMT_Encode4(`30917`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 982 //
11875	/ 30870 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sldi_w),
11876	/ 30875 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
11877	/ 30878 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
11878	/ 30881 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
11879	/ 30884 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11880	/ 30888 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11881	/ 30892 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
11882	/ 30896 / // MIs[0] n
11883	/ 30896 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11884	/ 30899 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11885	/* 30904 / // (intrinsic_wo_chain:{ :[v4i32] } 8587:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, (timm:{ :[i32] }):$n)
11886	/ 30904 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLDI_W),
11887	/ 30907 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11888	/ 30909 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
11889	/ 30911 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
11890	/ 30913 / GIR_RootToRootCopy, /OpIdx/`4`, // n
11891	/ 30915 / GIR_RootConstrainSelectedInstOperands,
11892	/ 30916 / // GIR_Coverage, 982,
11893	/ 30916 / GIR_EraseRootFromParent_Done,
11894	/ 30917 / // Label 965: @30917
11895	/ 30917 / GIM_Try_CheckFeatures, /On fail goto//Label 966/ GIMT_Encode4(`30971`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 983 //
11896	/ 30924 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sldi_d),
11897	/ 30929 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
11898	/ 30932 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
11899	/ 30935 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
11900	/ 30938 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11901	/ 30942 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11902	/ 30946 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
11903	/ 30950 / // MIs[0] n
11904	/ 30950 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11905	/ 30953 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
11906	/* 30958 / // (intrinsic_wo_chain:{ :[v2i64] } 8585:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, (timm:{ :[i32] }):$n)
11907	/ 30958 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLDI_D),
11908	/ 30961 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
11909	/ 30963 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
11910	/ 30965 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
11911	/ 30967 / GIR_RootToRootCopy, /OpIdx/`4`, // n
11912	/ 30969 / GIR_RootConstrainSelectedInstOperands,
11913	/ 30970 / // GIR_Coverage, 983,
11914	/ 30970 / GIR_EraseRootFromParent_Done,
11915	/ 30971 / // Label 966: @30971
11916	/ 30971 / GIM_Try_CheckFeatures, /On fail goto//Label 967/ GIMT_Encode4(`31025`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1370 //
11917	/ 30978 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11918	/ 30983 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11919	/ 30986 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11920	/ 30989 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11921	/ 30992 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11922	/ 30996 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11923	/ 31000 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11924	/ 31004 / // MIs[0] sa
11925	/ 31004 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11926	/ 31007 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11927	/* 31012 / // (intrinsic_wo_chain:{ :[v2i16] } 8546:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11928	/ 31012 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
11929	/ 31015 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11930	/ 31017 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11931	/ 31019 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11932	/ 31021 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11933	/ 31023 / GIR_RootConstrainSelectedInstOperands,
11934	/ 31024 / // GIR_Coverage, 1370,
11935	/ 31024 / GIR_EraseRootFromParent_Done,
11936	/ 31025 / // Label 967: @31025
11937	/ 31025 / GIM_Try_CheckFeatures, /On fail goto//Label 968/ GIMT_Encode4(`31079`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1371 //
11938	/ 31032 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11939	/ 31037 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
11940	/ 31040 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11941	/ 31043 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11942	/ 31046 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
11943	/ 31050 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11944	/ 31054 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11945	/ 31058 / // MIs[0] sa
11946	/ 31058 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11947	/ 31061 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11948	/* 31066 / // (intrinsic_wo_chain:{ :[v2i16] } 8547:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11949	/ 31066 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
11950	/ 31069 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11951	/ 31071 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11952	/ 31073 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11953	/ 31075 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11954	/ 31077 / GIR_RootConstrainSelectedInstOperands,
11955	/ 31078 / // GIR_Coverage, 1371,
11956	/ 31078 / GIR_EraseRootFromParent_Done,
11957	/ 31079 / // Label 968: @31079
11958	/ 31079 / GIM_Try_CheckFeatures, /On fail goto//Label 969/ GIMT_Encode4(`31133`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1372 //
11959	/ 31086 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_prepend),
11960	/ 31091 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11961	/ 31094 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11962	/ 31097 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11963	/ 31100 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11964	/ 31104 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11965	/ 31108 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11966	/ 31112 / // MIs[0] sa
11967	/ 31112 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11968	/ 31115 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11969	/* 31120 / // (intrinsic_wo_chain:{ :[i32] } 8552:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11970	/ 31120 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PREPEND_MMR2),
11971	/ 31123 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11972	/ 31125 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11973	/ 31127 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11974	/ 31129 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11975	/ 31131 / GIR_RootConstrainSelectedInstOperands,
11976	/ 31132 / // GIR_Coverage, 1372,
11977	/ 31132 / GIR_EraseRootFromParent_Done,
11978	/ 31133 / // Label 969: @31133
11979	/ 31133 / GIM_Try_CheckFeatures, /On fail goto//Label 970/ GIMT_Encode4(`31187`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1373 //
11980	/ 31140 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_append),
11981	/ 31145 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
11982	/ 31148 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
11983	/ 31151 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
11984	/ 31154 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11985	/ 31158 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11986	/ 31162 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
11987	/ 31166 / // MIs[0] sa
11988	/ 31166 / GIM_CheckIsImm, /MI/`0`, /Op/`4`,
11989	/ 31169 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11990	/* 31174 / // (intrinsic_wo_chain:{ :[i32] } 8059:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$sa, GPR32Opnd:{ :[i32] }:$src)
11991	/ 31174 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::APPEND_MMR2),
11992	/ 31177 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
11993	/ 31179 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
11994	/ 31181 / GIR_RootToRootCopy, /OpIdx/`4`, // sa
11995	/ 31183 / GIR_RootToRootCopy, /OpIdx/`2`, // src
11996	/ 31185 / GIR_RootConstrainSelectedInstOperands,
11997	/ 31186 / // GIR_Coverage, 1373,
11998	/ 31186 / GIR_EraseRootFromParent_Done,
11999	/ 31187 / // Label 970: @31187
12000	/ 31187 / GIM_Try_CheckFeatures, /On fail goto//Label 971/ GIMT_Encode4(`31248`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1348 //
12001	/ 31194 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_balign),
12002	/ 31199 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
12003	/ 31202 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
12004	/ 31205 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
12005	/ 31208 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12006	/ 31212 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12007	/ 31216 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12008	/ 31220 / // MIs[0] bp
12009	/ 31220 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`4`, // MIs[1]
12010	/ 31224 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12011	/ 31228 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12012	/ 31232 / // MIs[1] Operand 1
12013	/ 31232 / // No operand predicates
12014	/ 31232 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
12015	/* 31234 / // (intrinsic_wo_chain:{ :[i32] } 8084:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$bp, GPR32Opnd:{ :[i32] }:$src)
12016	/ 31234 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BALIGN_MMR2),
12017	/ 31237 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
12018	/ 31239 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
12019	/ 31241 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // bp
12020	/ 31244 / GIR_RootToRootCopy, /OpIdx/`2`, // src
12021	/ 31246 / GIR_RootConstrainSelectedInstOperands,
12022	/ 31247 / // GIR_Coverage, 1348,
12023	/ 31247 / GIR_EraseRootFromParent_Done,
12024	/ 31248 / // Label 971: @31248
12025	/ 31248 / GIM_Try_CheckFeatures, /On fail goto//Label 972/ GIMT_Encode4(`31301`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 579 //
12026	/ 31255 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsl_b),
12027	/ 31260 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
12028	/ 31263 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
12029	/ 31266 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12030	/ 31269 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12031	/ 31272 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12032	/ 31276 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12033	/ 31280 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12034	/ 31284 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12035	/* 31288 / // (intrinsic_wo_chain:{ :[v16i8] } 8093:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (BINSL_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12036	/ 31288 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSL_B),
12037	/ 31291 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12038	/ 31293 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12039	/ 31295 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12040	/ 31297 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12041	/ 31299 / GIR_RootConstrainSelectedInstOperands,
12042	/ 31300 / // GIR_Coverage, 579,
12043	/ 31300 / GIR_EraseRootFromParent_Done,
12044	/ 31301 / // Label 972: @31301
12045	/ 31301 / GIM_Try_CheckFeatures, /On fail goto//Label 973/ GIMT_Encode4(`31354`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 580 //
12046	/ 31308 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsl_h),
12047	/ 31313 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12048	/ 31316 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12049	/ 31319 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12050	/ 31322 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12051	/ 31325 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12052	/ 31329 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12053	/ 31333 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12054	/ 31337 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12055	/* 31341 / // (intrinsic_wo_chain:{ :[v8i16] } 8095:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (BINSL_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12056	/ 31341 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSL_H),
12057	/ 31344 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12058	/ 31346 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12059	/ 31348 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12060	/ 31350 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12061	/ 31352 / GIR_RootConstrainSelectedInstOperands,
12062	/ 31353 / // GIR_Coverage, 580,
12063	/ 31353 / GIR_EraseRootFromParent_Done,
12064	/ 31354 / // Label 973: @31354
12065	/ 31354 / GIM_Try_CheckFeatures, /On fail goto//Label 974/ GIMT_Encode4(`31407`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 581 //
12066	/ 31361 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsl_w),
12067	/ 31366 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12068	/ 31369 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12069	/ 31372 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12070	/ 31375 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12071	/ 31378 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12072	/ 31382 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12073	/ 31386 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12074	/ 31390 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12075	/* 31394 / // (intrinsic_wo_chain:{ :[v4i32] } 8096:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (BINSL_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12076	/ 31394 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSL_W),
12077	/ 31397 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12078	/ 31399 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12079	/ 31401 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12080	/ 31403 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12081	/ 31405 / GIR_RootConstrainSelectedInstOperands,
12082	/ 31406 / // GIR_Coverage, 581,
12083	/ 31406 / GIR_EraseRootFromParent_Done,
12084	/ 31407 / // Label 974: @31407
12085	/ 31407 / GIM_Try_CheckFeatures, /On fail goto//Label 975/ GIMT_Encode4(`31460`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 582 //
12086	/ 31414 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsl_d),
12087	/ 31419 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12088	/ 31422 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12089	/ 31425 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
12090	/ 31428 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v2s64,
12091	/ 31431 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12092	/ 31435 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12093	/ 31439 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12094	/ 31443 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12095	/* 31447 / // (intrinsic_wo_chain:{ :[v2i64] } 8094:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (BINSL_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
12096	/ 31447 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSL_D),
12097	/ 31450 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12098	/ 31452 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12099	/ 31454 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12100	/ 31456 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12101	/ 31458 / GIR_RootConstrainSelectedInstOperands,
12102	/ 31459 / // GIR_Coverage, 582,
12103	/ 31459 / GIR_EraseRootFromParent_Done,
12104	/ 31460 / // Label 975: @31460
12105	/ 31460 / GIM_Try_CheckFeatures, /On fail goto//Label 976/ GIMT_Encode4(`31513`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 587 //
12106	/ 31467 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsr_b),
12107	/ 31472 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
12108	/ 31475 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
12109	/ 31478 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12110	/ 31481 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12111	/ 31484 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12112	/ 31488 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12113	/ 31492 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12114	/ 31496 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12115	/* 31500 / // (intrinsic_wo_chain:{ :[v16i8] } 8101:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (BINSR_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12116	/ 31500 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSR_B),
12117	/ 31503 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12118	/ 31505 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12119	/ 31507 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12120	/ 31509 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12121	/ 31511 / GIR_RootConstrainSelectedInstOperands,
12122	/ 31512 / // GIR_Coverage, 587,
12123	/ 31512 / GIR_EraseRootFromParent_Done,
12124	/ 31513 / // Label 976: @31513
12125	/ 31513 / GIM_Try_CheckFeatures, /On fail goto//Label 977/ GIMT_Encode4(`31566`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 588 //
12126	/ 31520 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsr_h),
12127	/ 31525 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12128	/ 31528 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12129	/ 31531 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12130	/ 31534 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12131	/ 31537 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12132	/ 31541 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12133	/ 31545 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12134	/ 31549 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12135	/* 31553 / // (intrinsic_wo_chain:{ :[v8i16] } 8103:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (BINSR_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12136	/ 31553 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSR_H),
12137	/ 31556 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12138	/ 31558 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12139	/ 31560 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12140	/ 31562 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12141	/ 31564 / GIR_RootConstrainSelectedInstOperands,
12142	/ 31565 / // GIR_Coverage, 588,
12143	/ 31565 / GIR_EraseRootFromParent_Done,
12144	/ 31566 / // Label 977: @31566
12145	/ 31566 / GIM_Try_CheckFeatures, /On fail goto//Label 978/ GIMT_Encode4(`31619`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 589 //
12146	/ 31573 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsr_w),
12147	/ 31578 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12148	/ 31581 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12149	/ 31584 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12150	/ 31587 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12151	/ 31590 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12152	/ 31594 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12153	/ 31598 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12154	/ 31602 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12155	/* 31606 / // (intrinsic_wo_chain:{ :[v4i32] } 8104:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (BINSR_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12156	/ 31606 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSR_W),
12157	/ 31609 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12158	/ 31611 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12159	/ 31613 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12160	/ 31615 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12161	/ 31617 / GIR_RootConstrainSelectedInstOperands,
12162	/ 31618 / // GIR_Coverage, 589,
12163	/ 31618 / GIR_EraseRootFromParent_Done,
12164	/ 31619 / // Label 978: @31619
12165	/ 31619 / GIM_Try_CheckFeatures, /On fail goto//Label 979/ GIMT_Encode4(`31672`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 590 //
12166	/ 31626 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_binsr_d),
12167	/ 31631 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12168	/ 31634 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12169	/ 31637 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
12170	/ 31640 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v2s64,
12171	/ 31643 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12172	/ 31647 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12173	/ 31651 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12174	/ 31655 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12175	/* 31659 / // (intrinsic_wo_chain:{ :[v2i64] } 8102:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (BINSR_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
12176	/ 31659 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BINSR_D),
12177	/ 31662 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12178	/ 31664 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12179	/ 31666 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12180	/ 31668 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12181	/ 31670 / GIR_RootConstrainSelectedInstOperands,
12182	/ 31671 / // GIR_Coverage, 590,
12183	/ 31671 / GIR_EraseRootFromParent_Done,
12184	/ 31672 / // Label 979: @31672
12185	/ 31672 / GIM_Try_CheckFeatures, /On fail goto//Label 980/ GIMT_Encode4(`31725`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 685 //
12186	/ 31679 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
12187	/ 31684 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12188	/ 31687 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12189	/ 31690 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12190	/ 31693 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12191	/ 31696 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12192	/ 31700 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12193	/ 31704 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12194	/ 31708 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12195	/* 31712 / // (intrinsic_wo_chain:{ :[v8i16] } 8222:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DPADD_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12196	/ 31712 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_S_H),
12197	/ 31715 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12198	/ 31717 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12199	/ 31719 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12200	/ 31721 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12201	/ 31723 / GIR_RootConstrainSelectedInstOperands,
12202	/ 31724 / // GIR_Coverage, 685,
12203	/ 31724 / GIR_EraseRootFromParent_Done,
12204	/ 31725 / // Label 980: @31725
12205	/ 31725 / GIM_Try_CheckFeatures, /On fail goto//Label 981/ GIMT_Encode4(`31778`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 686 //
12206	/ 31732 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
12207	/ 31737 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12208	/ 31740 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12209	/ 31743 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12210	/ 31746 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12211	/ 31749 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12212	/ 31753 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12213	/ 31757 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12214	/ 31761 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12215	/* 31765 / // (intrinsic_wo_chain:{ :[v4i32] } 8223:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DPADD_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12216	/ 31765 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_S_W),
12217	/ 31768 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12218	/ 31770 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12219	/ 31772 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12220	/ 31774 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12221	/ 31776 / GIR_RootConstrainSelectedInstOperands,
12222	/ 31777 / // GIR_Coverage, 686,
12223	/ 31777 / GIR_EraseRootFromParent_Done,
12224	/ 31778 / // Label 981: @31778
12225	/ 31778 / GIM_Try_CheckFeatures, /On fail goto//Label 982/ GIMT_Encode4(`31831`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 687 //
12226	/ 31785 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
12227	/ 31790 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12228	/ 31793 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12229	/ 31796 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12230	/ 31799 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12231	/ 31802 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12232	/ 31806 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12233	/ 31810 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12234	/ 31814 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12235	/* 31818 / // (intrinsic_wo_chain:{ :[v2i64] } 8221:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DPADD_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12236	/ 31818 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_S_D),
12237	/ 31821 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12238	/ 31823 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12239	/ 31825 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12240	/ 31827 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12241	/ 31829 / GIR_RootConstrainSelectedInstOperands,
12242	/ 31830 / // GIR_Coverage, 687,
12243	/ 31830 / GIR_EraseRootFromParent_Done,
12244	/ 31831 / // Label 982: @31831
12245	/ 31831 / GIM_Try_CheckFeatures, /On fail goto//Label 983/ GIMT_Encode4(`31884`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 688 //
12246	/ 31838 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
12247	/ 31843 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12248	/ 31846 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12249	/ 31849 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12250	/ 31852 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12251	/ 31855 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12252	/ 31859 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12253	/ 31863 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12254	/ 31867 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12255	/* 31871 / // (intrinsic_wo_chain:{ :[v8i16] } 8225:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DPADD_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12256	/ 31871 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_U_H),
12257	/ 31874 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12258	/ 31876 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12259	/ 31878 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12260	/ 31880 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12261	/ 31882 / GIR_RootConstrainSelectedInstOperands,
12262	/ 31883 / // GIR_Coverage, 688,
12263	/ 31883 / GIR_EraseRootFromParent_Done,
12264	/ 31884 / // Label 983: @31884
12265	/ 31884 / GIM_Try_CheckFeatures, /On fail goto//Label 984/ GIMT_Encode4(`31937`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 689 //
12266	/ 31891 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
12267	/ 31896 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12268	/ 31899 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12269	/ 31902 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12270	/ 31905 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12271	/ 31908 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12272	/ 31912 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12273	/ 31916 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12274	/ 31920 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12275	/* 31924 / // (intrinsic_wo_chain:{ :[v4i32] } 8226:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DPADD_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12276	/ 31924 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_U_W),
12277	/ 31927 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12278	/ 31929 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12279	/ 31931 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12280	/ 31933 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12281	/ 31935 / GIR_RootConstrainSelectedInstOperands,
12282	/ 31936 / // GIR_Coverage, 689,
12283	/ 31936 / GIR_EraseRootFromParent_Done,
12284	/ 31937 / // Label 984: @31937
12285	/ 31937 / GIM_Try_CheckFeatures, /On fail goto//Label 985/ GIMT_Encode4(`31990`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 690 //
12286	/ 31944 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
12287	/ 31949 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12288	/ 31952 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12289	/ 31955 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12290	/ 31958 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12291	/ 31961 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12292	/ 31965 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12293	/ 31969 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12294	/ 31973 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12295	/* 31977 / // (intrinsic_wo_chain:{ :[v2i64] } 8224:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DPADD_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12296	/ 31977 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPADD_U_D),
12297	/ 31980 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12298	/ 31982 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12299	/ 31984 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12300	/ 31986 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12301	/ 31988 / GIR_RootConstrainSelectedInstOperands,
12302	/ 31989 / // GIR_Coverage, 690,
12303	/ 31989 / GIR_EraseRootFromParent_Done,
12304	/ 31990 / // Label 985: @31990
12305	/ 31990 / GIM_Try_CheckFeatures, /On fail goto//Label 986/ GIMT_Encode4(`32043`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 691 //
12306	/ 31997 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
12307	/ 32002 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12308	/ 32005 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12309	/ 32008 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12310	/ 32011 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12311	/ 32014 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12312	/ 32018 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12313	/ 32022 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12314	/ 32026 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12315	/* 32030 / // (intrinsic_wo_chain:{ :[v8i16] } 8242:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DPSUB_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12316	/ 32030 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_S_H),
12317	/ 32033 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12318	/ 32035 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12319	/ 32037 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12320	/ 32039 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12321	/ 32041 / GIR_RootConstrainSelectedInstOperands,
12322	/ 32042 / // GIR_Coverage, 691,
12323	/ 32042 / GIR_EraseRootFromParent_Done,
12324	/ 32043 / // Label 986: @32043
12325	/ 32043 / GIM_Try_CheckFeatures, /On fail goto//Label 987/ GIMT_Encode4(`32096`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 692 //
12326	/ 32050 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
12327	/ 32055 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12328	/ 32058 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12329	/ 32061 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12330	/ 32064 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12331	/ 32067 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12332	/ 32071 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12333	/ 32075 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12334	/ 32079 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12335	/* 32083 / // (intrinsic_wo_chain:{ :[v4i32] } 8243:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DPSUB_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12336	/ 32083 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_S_W),
12337	/ 32086 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12338	/ 32088 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12339	/ 32090 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12340	/ 32092 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12341	/ 32094 / GIR_RootConstrainSelectedInstOperands,
12342	/ 32095 / // GIR_Coverage, 692,
12343	/ 32095 / GIR_EraseRootFromParent_Done,
12344	/ 32096 / // Label 987: @32096
12345	/ 32096 / GIM_Try_CheckFeatures, /On fail goto//Label 988/ GIMT_Encode4(`32149`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 693 //
12346	/ 32103 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
12347	/ 32108 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12348	/ 32111 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12349	/ 32114 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12350	/ 32117 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12351	/ 32120 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12352	/ 32124 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12353	/ 32128 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12354	/ 32132 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12355	/* 32136 / // (intrinsic_wo_chain:{ :[v2i64] } 8241:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DPSUB_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12356	/ 32136 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_S_D),
12357	/ 32139 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12358	/ 32141 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12359	/ 32143 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12360	/ 32145 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12361	/ 32147 / GIR_RootConstrainSelectedInstOperands,
12362	/ 32148 / // GIR_Coverage, 693,
12363	/ 32148 / GIR_EraseRootFromParent_Done,
12364	/ 32149 / // Label 988: @32149
12365	/ 32149 / GIM_Try_CheckFeatures, /On fail goto//Label 989/ GIMT_Encode4(`32202`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 694 //
12366	/ 32156 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
12367	/ 32161 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12368	/ 32164 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12369	/ 32167 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12370	/ 32170 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v16s8,
12371	/ 32173 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12372	/ 32177 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12373	/ 32181 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12374	/ 32185 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12375	/* 32189 / // (intrinsic_wo_chain:{ :[v8i16] } 8245:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (DPSUB_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
12376	/ 32189 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_U_H),
12377	/ 32192 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12378	/ 32194 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12379	/ 32196 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12380	/ 32198 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12381	/ 32200 / GIR_RootConstrainSelectedInstOperands,
12382	/ 32201 / // GIR_Coverage, 694,
12383	/ 32201 / GIR_EraseRootFromParent_Done,
12384	/ 32202 / // Label 989: @32202
12385	/ 32202 / GIM_Try_CheckFeatures, /On fail goto//Label 990/ GIMT_Encode4(`32255`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 695 //
12386	/ 32209 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
12387	/ 32214 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12388	/ 32217 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12389	/ 32220 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12390	/ 32223 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12391	/ 32226 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12392	/ 32230 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12393	/ 32234 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12394	/ 32238 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12395	/* 32242 / // (intrinsic_wo_chain:{ :[v4i32] } 8246:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (DPSUB_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12396	/ 32242 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_U_W),
12397	/ 32245 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12398	/ 32247 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12399	/ 32249 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12400	/ 32251 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12401	/ 32253 / GIR_RootConstrainSelectedInstOperands,
12402	/ 32254 / // GIR_Coverage, 695,
12403	/ 32254 / GIR_EraseRootFromParent_Done,
12404	/ 32255 / // Label 990: @32255
12405	/ 32255 / GIM_Try_CheckFeatures, /On fail goto//Label 991/ GIMT_Encode4(`32308`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 696 //
12406	/ 32262 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
12407	/ 32267 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12408	/ 32270 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12409	/ 32273 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12410	/ 32276 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12411	/ 32279 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12412	/ 32283 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12413	/ 32287 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12414	/ 32291 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12415	/* 32295 / // (intrinsic_wo_chain:{ :[v2i64] } 8244:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (DPSUB_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12416	/ 32295 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DPSUB_U_D),
12417	/ 32298 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12418	/ 32300 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12419	/ 32302 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12420	/ 32304 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12421	/ 32306 / GIR_RootConstrainSelectedInstOperands,
12422	/ 32307 / // GIR_Coverage, 696,
12423	/ 32307 / GIR_EraseRootFromParent_Done,
12424	/ 32308 / // Label 991: @32308
12425	/ 32308 / GIM_Try_CheckFeatures, /On fail goto//Label 992/ GIMT_Encode4(`32361`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 863 //
12426	/ 32315 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_madd_q_h),
12427	/ 32320 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12428	/ 32323 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12429	/ 32326 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12430	/ 32329 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12431	/ 32332 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12432	/ 32336 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12433	/ 32340 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12434	/ 32344 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12435	/* 32348 / // (intrinsic_wo_chain:{ :[v8i16] } 8412:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MADD_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12436	/ 32348 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_Q_H),
12437	/ 32351 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12438	/ 32353 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12439	/ 32355 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12440	/ 32357 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12441	/ 32359 / GIR_RootConstrainSelectedInstOperands,
12442	/ 32360 / // GIR_Coverage, 863,
12443	/ 32360 / GIR_EraseRootFromParent_Done,
12444	/ 32361 / // Label 992: @32361
12445	/ 32361 / GIM_Try_CheckFeatures, /On fail goto//Label 993/ GIMT_Encode4(`32414`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 864 //
12446	/ 32368 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_madd_q_w),
12447	/ 32373 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12448	/ 32376 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12449	/ 32379 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12450	/ 32382 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12451	/ 32385 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12452	/ 32389 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12453	/ 32393 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12454	/ 32397 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12455	/* 32401 / // (intrinsic_wo_chain:{ :[v4i32] } 8413:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MADD_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12456	/ 32401 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_Q_W),
12457	/ 32404 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12458	/ 32406 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12459	/ 32408 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12460	/ 32410 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12461	/ 32412 / GIR_RootConstrainSelectedInstOperands,
12462	/ 32413 / // GIR_Coverage, 864,
12463	/ 32413 / GIR_EraseRootFromParent_Done,
12464	/ 32414 / // Label 993: @32414
12465	/ 32414 / GIM_Try_CheckFeatures, /On fail goto//Label 994/ GIMT_Encode4(`32467`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 865 //
12466	/ 32421 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
12467	/ 32426 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12468	/ 32429 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12469	/ 32432 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12470	/ 32435 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12471	/ 32438 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12472	/ 32442 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12473	/ 32446 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12474	/ 32450 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12475	/* 32454 / // (intrinsic_wo_chain:{ :[v8i16] } 8414:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MADDR_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12476	/ 32454 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDR_Q_H),
12477	/ 32457 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12478	/ 32459 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12479	/ 32461 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12480	/ 32463 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12481	/ 32465 / GIR_RootConstrainSelectedInstOperands,
12482	/ 32466 / // GIR_Coverage, 865,
12483	/ 32466 / GIR_EraseRootFromParent_Done,
12484	/ 32467 / // Label 994: @32467
12485	/ 32467 / GIM_Try_CheckFeatures, /On fail goto//Label 995/ GIMT_Encode4(`32520`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 866 //
12486	/ 32474 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
12487	/ 32479 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12488	/ 32482 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12489	/ 32485 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12490	/ 32488 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12491	/ 32491 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12492	/ 32495 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12493	/ 32499 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12494	/ 32503 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12495	/* 32507 / // (intrinsic_wo_chain:{ :[v4i32] } 8415:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MADDR_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12496	/ 32507 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADDR_Q_W),
12497	/ 32510 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12498	/ 32512 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12499	/ 32514 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12500	/ 32516 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12501	/ 32518 / GIR_RootConstrainSelectedInstOperands,
12502	/ 32519 / // GIR_Coverage, 866,
12503	/ 32519 / GIR_EraseRootFromParent_Done,
12504	/ 32520 / // Label 995: @32520
12505	/ 32520 / GIM_Try_CheckFeatures, /On fail goto//Label 996/ GIMT_Encode4(`32573`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 919 //
12506	/ 32527 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_msub_q_h),
12507	/ 32532 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12508	/ 32535 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12509	/ 32538 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12510	/ 32541 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12511	/ 32544 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12512	/ 32548 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12513	/ 32552 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12514	/ 32556 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12515	/* 32560 / // (intrinsic_wo_chain:{ :[v8i16] } 8476:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MSUB_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12516	/ 32560 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_Q_H),
12517	/ 32563 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12518	/ 32565 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12519	/ 32567 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12520	/ 32569 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12521	/ 32571 / GIR_RootConstrainSelectedInstOperands,
12522	/ 32572 / // GIR_Coverage, 919,
12523	/ 32572 / GIR_EraseRootFromParent_Done,
12524	/ 32573 / // Label 996: @32573
12525	/ 32573 / GIM_Try_CheckFeatures, /On fail goto//Label 997/ GIMT_Encode4(`32626`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 920 //
12526	/ 32580 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_msub_q_w),
12527	/ 32585 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12528	/ 32588 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12529	/ 32591 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12530	/ 32594 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12531	/ 32597 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12532	/ 32601 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12533	/ 32605 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12534	/ 32609 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12535	/* 32613 / // (intrinsic_wo_chain:{ :[v4i32] } 8477:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MSUB_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12536	/ 32613 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_Q_W),
12537	/ 32616 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12538	/ 32618 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12539	/ 32620 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12540	/ 32622 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12541	/ 32624 / GIR_RootConstrainSelectedInstOperands,
12542	/ 32625 / // GIR_Coverage, 920,
12543	/ 32625 / GIR_EraseRootFromParent_Done,
12544	/ 32626 / // Label 997: @32626
12545	/ 32626 / GIM_Try_CheckFeatures, /On fail goto//Label 998/ GIMT_Encode4(`32679`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 921 //
12546	/ 32633 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
12547	/ 32638 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12548	/ 32641 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12549	/ 32644 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12550	/ 32647 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v8s16,
12551	/ 32650 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12552	/ 32654 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12553	/ 32658 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12554	/ 32662 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12555	/* 32666 / // (intrinsic_wo_chain:{ :[v8i16] } 8478:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MSUBR_Q_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
12556	/ 32666 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBR_Q_H),
12557	/ 32669 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12558	/ 32671 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12559	/ 32673 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12560	/ 32675 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12561	/ 32677 / GIR_RootConstrainSelectedInstOperands,
12562	/ 32678 / // GIR_Coverage, 921,
12563	/ 32678 / GIR_EraseRootFromParent_Done,
12564	/ 32679 / // Label 998: @32679
12565	/ 32679 / GIM_Try_CheckFeatures, /On fail goto//Label 999/ GIMT_Encode4(`32732`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 922 //
12566	/ 32686 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
12567	/ 32691 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12568	/ 32694 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12569	/ 32697 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12570	/ 32700 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_v4s32,
12571	/ 32703 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12572	/ 32707 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12573	/ 32711 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12574	/ 32715 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12575	/* 32719 / // (intrinsic_wo_chain:{ :[v4i32] } 8479:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MSUBR_Q_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
12576	/ 32719 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUBR_Q_W),
12577	/ 32722 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12578	/ 32724 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12579	/ 32726 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12580	/ 32728 / GIR_RootToRootCopy, /OpIdx/`4`, // wt
12581	/ 32730 / GIR_RootConstrainSelectedInstOperands,
12582	/ 32731 / // GIR_Coverage, 922,
12583	/ 32731 / GIR_EraseRootFromParent_Done,
12584	/ 32732 / // Label 999: @32732
12585	/ 32732 / GIM_Try_CheckFeatures, /On fail goto//Label 1000/ GIMT_Encode4(`32785`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 976 //
12586	/ 32739 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sld_b),
12587	/ 32744 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v16s8,
12588	/ 32747 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
12589	/ 32750 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
12590	/ 32753 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_s32,
12591	/ 32756 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12592	/ 32760 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12593	/ 32764 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
12594	/ 32768 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12595	/* 32772 / // (intrinsic_wo_chain:{ :[v16i8] } 8580:{ :[iPTR] }, MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, GPR32Opnd:{ :[i32] }:$rt) => (SLD_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, GPR32Opnd:{ :[i32] }:$rt)
12596	/ 32772 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLD_B),
12597	/ 32775 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12598	/ 32777 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12599	/ 32779 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12600	/ 32781 / GIR_RootToRootCopy, /OpIdx/`4`, // rt
12601	/ 32783 / GIR_RootConstrainSelectedInstOperands,
12602	/ 32784 / // GIR_Coverage, 976,
12603	/ 32784 / GIR_EraseRootFromParent_Done,
12604	/ 32785 / // Label 1000: @32785
12605	/ 32785 / GIM_Try_CheckFeatures, /On fail goto//Label 1001/ GIMT_Encode4(`32838`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 977 //
12606	/ 32792 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sld_h),
12607	/ 32797 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v8s16,
12608	/ 32800 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
12609	/ 32803 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
12610	/ 32806 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_s32,
12611	/ 32809 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12612	/ 32813 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12613	/ 32817 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
12614	/ 32821 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12615	/* 32825 / // (intrinsic_wo_chain:{ :[v8i16] } 8582:{ :[iPTR] }, MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, GPR32Opnd:{ :[i32] }:$rt) => (SLD_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, GPR32Opnd:{ :[i32] }:$rt)
12616	/ 32825 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLD_H),
12617	/ 32828 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12618	/ 32830 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12619	/ 32832 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12620	/ 32834 / GIR_RootToRootCopy, /OpIdx/`4`, // rt
12621	/ 32836 / GIR_RootConstrainSelectedInstOperands,
12622	/ 32837 / // GIR_Coverage, 977,
12623	/ 32837 / GIR_EraseRootFromParent_Done,
12624	/ 32838 / // Label 1001: @32838
12625	/ 32838 / GIM_Try_CheckFeatures, /On fail goto//Label 1002/ GIMT_Encode4(`32891`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 978 //
12626	/ 32845 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sld_w),
12627	/ 32850 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
12628	/ 32853 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
12629	/ 32856 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
12630	/ 32859 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_s32,
12631	/ 32862 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12632	/ 32866 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12633	/ 32870 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
12634	/ 32874 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12635	/* 32878 / // (intrinsic_wo_chain:{ :[v4i32] } 8583:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, GPR32Opnd:{ :[i32] }:$rt) => (SLD_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, GPR32Opnd:{ :[i32] }:$rt)
12636	/ 32878 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLD_W),
12637	/ 32881 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12638	/ 32883 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12639	/ 32885 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12640	/ 32887 / GIR_RootToRootCopy, /OpIdx/`4`, // rt
12641	/ 32889 / GIR_RootConstrainSelectedInstOperands,
12642	/ 32890 / // GIR_Coverage, 978,
12643	/ 32890 / GIR_EraseRootFromParent_Done,
12644	/ 32891 / // Label 1002: @32891
12645	/ 32891 / GIM_Try_CheckFeatures, /On fail goto//Label 1003/ GIMT_Encode4(`32944`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 979 //
12646	/ 32898 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_sld_d),
12647	/ 32903 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
12648	/ 32906 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
12649	/ 32909 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
12650	/ 32912 / GIM_RootCheckType, /Op/`4`, /Type/GILLT_s32,
12651	/ 32915 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12652	/ 32919 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12653	/ 32923 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
12654	/ 32927 / GIM_RootCheckRegBankForClass, /Op/`4`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12655	/* 32931 / // (intrinsic_wo_chain:{ :[v2i64] } 8581:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, GPR32Opnd:{ :[i32] }:$rt) => (SLD_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, GPR32Opnd:{ :[i32] }:$rt)
12656	/ 32931 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLD_D),
12657	/ 32934 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
12658	/ 32936 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
12659	/ 32938 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
12660	/ 32940 / GIR_RootToRootCopy, /OpIdx/`4`, // rt
12661	/ 32942 / GIR_RootConstrainSelectedInstOperands,
12662	/ 32943 / // GIR_Coverage, 979,
12663	/ 32943 / GIR_EraseRootFromParent_Done,
12664	/ 32944 / // Label 1003: @32944
12665	/ 32944 / GIM_Reject,
12666	/ 32945 / // Label 957: @32945
12667	/ 32945 / GIM_Reject,
12668	/ 32946 / // Label 30: @32946
12669	/ 32946 / GIM_Try, /On fail goto//Label 1004/ GIMT_Encode4(`32977`), // Rule ID 381 //
12670	/ 32951 / GIM_CheckNumOperands, /MI/`0`, /Expected/`2`,
12671	/ 32954 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_bposge32),
12672	/ 32959 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
12673	/ 32962 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12674	/ 32966 / // (intrinsic_w_chain:{ :[i32] } 8127:{ :[iPTR] }) => (BPOSGE32_PSEUDO:{ :[i32] })*
12675	/ 32966 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
12676	/ 32969 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
12677	/ 32971 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12678	/ 32975 / GIR_RootConstrainSelectedInstOperands,
12679	/ 32976 / // GIR_Coverage, 381,
12680	/ 32976 / GIR_EraseRootFromParent_Done,
12681	/ 32977 / // Label 1004: @32977
12682	/ 32977 / GIM_Try, /On fail goto//Label 1005/ GIMT_Encode4(`33874`),
12683	/ 32982 / GIM_CheckNumOperands, /MI/`0`, /Expected/`3`,
12684	/ 32985 / GIM_Try, /On fail goto//Label 1006/ GIMT_Encode4(`33051`),
12685	/ 32990 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_rddsp),
12686	/ 32995 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
12687	/ 32998 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12688	/ 33002 / GIM_CheckIsImm, /MI/`0`, /Op/`2`,
12689	/ 33005 / GIM_Try_CheckFeatures, /On fail goto//Label 1007/ GIMT_Encode4(`33030`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 468 //
12690	/ 33012 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12691	/ 33017 / // (intrinsic_w_chain:{ :[i32] } 8554:{ :[iPTR] }, (timm:{ :[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ :[i32] } (timm:{ :[i32] }):$mask)*
12692	/ 33017 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::RDDSP),
12693	/ 33020 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
12694	/ 33022 / GIR_RootToRootCopy, /OpIdx/`2`, // mask
12695	/ 33024 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12696	/ 33028 / GIR_RootConstrainSelectedInstOperands,
12697	/ 33029 / // GIR_Coverage, 468,
12698	/ 33029 / GIR_EraseRootFromParent_Done,
12699	/ 33030 / // Label 1007: @33030
12700	/ 33030 / GIM_Try_CheckFeatures, /On fail goto//Label 1008/ GIMT_Encode4(`33050`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1308 //
12701	/ 33037 / // (intrinsic_w_chain:{ :[i32] } 8554:{ :[iPTR] }, (timm:{ :[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ :[i32] } (timm:{ :[i32] }):$mask)*
12702	/ 33037 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::RDDSP_MM),
12703	/ 33040 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
12704	/ 33042 / GIR_RootToRootCopy, /OpIdx/`2`, // mask
12705	/ 33044 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12706	/ 33048 / GIR_RootConstrainSelectedInstOperands,
12707	/ 33049 / // GIR_Coverage, 1308,
12708	/ 33049 / GIR_EraseRootFromParent_Done,
12709	/ 33050 / // Label 1008: @33050
12710	/ 33050 / GIM_Reject,
12711	/ 33051 / // Label 1006: @33051
12712	/ 33051 / GIM_Try, /On fail goto//Label 1009/ GIMT_Encode4(`33117`),
12713	/ 33056 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_wrdsp),
12714	/ 33061 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
12715	/ 33064 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12716	/ 33068 / GIM_CheckIsImm, /MI/`0`, /Op/`2`,
12717	/ 33071 / GIM_Try_CheckFeatures, /On fail goto//Label 1010/ GIMT_Encode4(`33096`), GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips), // Rule ID 469 //
12718	/ 33078 / GIM_CheckImmOperandPredicate, /MI/`0`, /MO/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12719	/ 33083 / // (intrinsic_void 8683:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ :[i32] }:$rs, (timm:{ :[i32] }):$mask)*
12720	/ 33083 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::WRDSP),
12721	/ 33086 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12722	/ 33088 / GIR_RootToRootCopy, /OpIdx/`2`, // mask
12723	/ 33090 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12724	/ 33094 / GIR_RootConstrainSelectedInstOperands,
12725	/ 33095 / // GIR_Coverage, 469,
12726	/ 33095 / GIR_EraseRootFromParent_Done,
12727	/ 33096 / // Label 1010: @33096
12728	/ 33096 / GIM_Try_CheckFeatures, /On fail goto//Label 1011/ GIMT_Encode4(`33116`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1319 //
12729	/* 33103 / // (intrinsic_void 8683:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, (timm:{ :[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ :[i32] }:$rt, (timm:{ :[i32] }):$mask)
12730	/ 33103 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::WRDSP_MM),
12731	/ 33106 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
12732	/ 33108 / GIR_RootToRootCopy, /OpIdx/`2`, // mask
12733	/ 33110 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12734	/ 33114 / GIR_RootConstrainSelectedInstOperands,
12735	/ 33115 / // GIR_Coverage, 1319,
12736	/ 33115 / GIR_EraseRootFromParent_Done,
12737	/ 33116 / // Label 1011: @33116
12738	/ 33116 / GIM_Reject,
12739	/ 33117 / // Label 1009: @33117
12740	/ 33117 / GIM_Try_CheckFeatures, /On fail goto//Label 1012/ GIMT_Encode4(`33159`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 390 //
12741	/ 33124 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12742	/ 33129 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
12743	/ 33132 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12744	/ 33135 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12745	/ 33139 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12746	/ 33143 / // (intrinsic_w_chain:{ :[v2i16] } 8015:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt) => (ABSQ_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt)*
12747	/ 33143 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_PH),
12748	/ 33146 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
12749	/ 33148 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12750	/ 33150 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12751	/ 33153 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12752	/ 33157 / GIR_RootConstrainSelectedInstOperands,
12753	/ 33158 / // GIR_Coverage, 390,
12754	/ 33158 / GIR_EraseRootFromParent_Done,
12755	/ 33159 / // Label 1012: @33159
12756	/ 33159 / GIM_Try_CheckFeatures, /On fail goto//Label 1013/ GIMT_Encode4(`33201`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 391 //
12757	/ 33166 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12758	/ 33171 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
12759	/ 33174 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
12760	/ 33177 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12761	/ 33181 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12762	/ 33185 / // (intrinsic_w_chain:{ :[i32] } 8017:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt) => (ABSQ_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
12763	/ 33185 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_W),
12764	/ 33188 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
12765	/ 33190 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12766	/ 33192 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12767	/ 33195 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12768	/ 33199 / GIR_RootConstrainSelectedInstOperands,
12769	/ 33200 / // GIR_Coverage, 391,
12770	/ 33200 / GIR_EraseRootFromParent_Done,
12771	/ 33201 / // Label 1013: @33201
12772	/ 33201 / GIM_Try_CheckFeatures, /On fail goto//Label 1014/ GIMT_Encode4(`33243`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 477 //
12773	/ 33208 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12774	/ 33213 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
12775	/ 33216 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12776	/ 33219 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12777	/ 33223 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12778	/ 33227 / // (intrinsic_w_chain:{ :[v4i8] } 8016:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt) => (ABSQ_S_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt)*
12779	/ 33227 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_QB),
12780	/ 33230 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
12781	/ 33232 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12782	/ 33234 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12783	/ 33237 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12784	/ 33241 / GIR_RootConstrainSelectedInstOperands,
12785	/ 33242 / // GIR_Coverage, 477,
12786	/ 33242 / GIR_EraseRootFromParent_Done,
12787	/ 33243 / // Label 1014: @33243
12788	/ 33243 / GIM_Try_CheckFeatures, /On fail goto//Label 1015/ GIMT_Encode4(`33285`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1251 //
12789	/ 33250 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12790	/ 33255 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
12791	/ 33258 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12792	/ 33261 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12793	/ 33265 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12794	/ 33269 / // (intrinsic_w_chain:{ :[v2i16] } 8015:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs)*
12795	/ 33269 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
12796	/ 33272 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
12797	/ 33274 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
12798	/ 33276 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12799	/ 33279 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12800	/ 33283 / GIR_RootConstrainSelectedInstOperands,
12801	/ 33284 / // GIR_Coverage, 1251,
12802	/ 33284 / GIR_EraseRootFromParent_Done,
12803	/ 33285 / // Label 1015: @33285
12804	/ 33285 / GIM_Try_CheckFeatures, /On fail goto//Label 1016/ GIMT_Encode4(`33327`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1252 //
12805	/ 33292 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12806	/ 33297 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
12807	/ 33300 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
12808	/ 33303 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12809	/ 33307 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
12810	/ 33311 / // (intrinsic_w_chain:{ :[i32] } 8017:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs) => (ABSQ_S_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)*
12811	/ 33311 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_W_MM),
12812	/ 33314 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
12813	/ 33316 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
12814	/ 33318 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12815	/ 33321 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12816	/ 33325 / GIR_RootConstrainSelectedInstOperands,
12817	/ 33326 / // GIR_Coverage, 1252,
12818	/ 33326 / GIR_EraseRootFromParent_Done,
12819	/ 33327 / // Label 1016: @33327
12820	/ 33327 / GIM_Try_CheckFeatures, /On fail goto//Label 1017/ GIMT_Encode4(`33369`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1332 //
12821	/ 33334 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12822	/ 33339 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
12823	/ 33342 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12824	/ 33345 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12825	/ 33349 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12826	/ 33353 / // (intrinsic_w_chain:{ :[v4i8] } 8016:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs)*
12827	/ 33353 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
12828	/ 33356 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
12829	/ 33358 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
12830	/ 33360 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
12831	/ 33363 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12832	/ 33367 / GIR_RootConstrainSelectedInstOperands,
12833	/ 33368 / // GIR_Coverage, 1332,
12834	/ 33368 / GIR_EraseRootFromParent_Done,
12835	/ 33369 / // Label 1017: @33369
12836	/ 33369 / GIM_Try_CheckFeatures, /On fail goto//Label 1018/ GIMT_Encode4(`33411`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 444 //
12837	/ 33376 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
12838	/ 33381 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
12839	/ 33384 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12840	/ 33387 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12841	/ 33391 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12842	/ 33395 / // (intrinsic_void 8193:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
12843	/ 33395 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_EQ_QB),
12844	/ 33398 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12845	/ 33400 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12846	/ 33402 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12847	/ 33405 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12848	/ 33409 / GIR_RootConstrainSelectedInstOperands,
12849	/ 33410 / // GIR_Coverage, 444,
12850	/ 33410 / GIR_EraseRootFromParent_Done,
12851	/ 33411 / // Label 1018: @33411
12852	/ 33411 / GIM_Try_CheckFeatures, /On fail goto//Label 1019/ GIMT_Encode4(`33453`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 445 //
12853	/ 33418 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
12854	/ 33423 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
12855	/ 33426 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12856	/ 33429 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12857	/ 33433 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12858	/ 33437 / // (intrinsic_void 8195:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
12859	/ 33437 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_LT_QB),
12860	/ 33440 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12861	/ 33442 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12862	/ 33444 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12863	/ 33447 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12864	/ 33451 / GIR_RootConstrainSelectedInstOperands,
12865	/ 33452 / // GIR_Coverage, 445,
12866	/ 33452 / GIR_EraseRootFromParent_Done,
12867	/ 33453 / // Label 1019: @33453
12868	/ 33453 / GIM_Try_CheckFeatures, /On fail goto//Label 1020/ GIMT_Encode4(`33495`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 446 //
12869	/ 33460 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
12870	/ 33465 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
12871	/ 33468 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12872	/ 33471 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12873	/ 33475 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12874	/ 33479 / // (intrinsic_void 8194:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
12875	/ 33479 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_LE_QB),
12876	/ 33482 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12877	/ 33484 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12878	/ 33486 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12879	/ 33489 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12880	/ 33493 / GIR_RootConstrainSelectedInstOperands,
12881	/ 33494 / // GIR_Coverage, 446,
12882	/ 33494 / GIR_EraseRootFromParent_Done,
12883	/ 33495 / // Label 1020: @33495
12884	/ 33495 / GIM_Try_CheckFeatures, /On fail goto//Label 1021/ GIMT_Encode4(`33537`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 450 //
12885	/ 33502 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12886	/ 33507 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12887	/ 33510 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12888	/ 33513 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12889	/ 33517 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12890	/ 33521 / // (intrinsic_void 8184:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12891	/ 33521 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_PH),
12892	/ 33524 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12893	/ 33526 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12894	/ 33528 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12895	/ 33531 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12896	/ 33535 / GIR_RootConstrainSelectedInstOperands,
12897	/ 33536 / // GIR_Coverage, 450,
12898	/ 33536 / GIR_EraseRootFromParent_Done,
12899	/ 33537 / // Label 1021: @33537
12900	/ 33537 / GIM_Try_CheckFeatures, /On fail goto//Label 1022/ GIMT_Encode4(`33579`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 451 //
12901	/ 33544 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12902	/ 33549 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12903	/ 33552 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12904	/ 33555 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12905	/ 33559 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12906	/ 33563 / // (intrinsic_void 8186:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12907	/ 33563 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_PH),
12908	/ 33566 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12909	/ 33568 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12910	/ 33570 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12911	/ 33573 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12912	/ 33577 / GIR_RootConstrainSelectedInstOperands,
12913	/ 33578 / // GIR_Coverage, 451,
12914	/ 33578 / GIR_EraseRootFromParent_Done,
12915	/ 33579 / // Label 1022: @33579
12916	/ 33579 / GIM_Try_CheckFeatures, /On fail goto//Label 1023/ GIMT_Encode4(`33621`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 452 //
12917	/ 33586 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
12918	/ 33591 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12919	/ 33594 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12920	/ 33597 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12921	/ 33601 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12922	/ 33605 / // (intrinsic_void 8185:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12923	/ 33605 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_PH),
12924	/ 33608 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12925	/ 33610 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12926	/ 33612 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12927	/ 33615 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12928	/ 33619 / GIR_RootConstrainSelectedInstOperands,
12929	/ 33620 / // GIR_Coverage, 452,
12930	/ 33620 / GIR_EraseRootFromParent_Done,
12931	/ 33621 / // Label 1023: @33621
12932	/ 33621 / GIM_Try_CheckFeatures, /On fail goto//Label 1024/ GIMT_Encode4(`33663`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1323 //
12933	/ 33628 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12934	/ 33633 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12935	/ 33636 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12936	/ 33639 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12937	/ 33643 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12938	/ 33647 / // (intrinsic_void 8184:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12939	/ 33647 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
12940	/ 33650 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12941	/ 33652 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12942	/ 33654 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12943	/ 33657 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12944	/ 33661 / GIR_RootConstrainSelectedInstOperands,
12945	/ 33662 / // GIR_Coverage, 1323,
12946	/ 33662 / GIR_EraseRootFromParent_Done,
12947	/ 33663 / // Label 1024: @33663
12948	/ 33663 / GIM_Try_CheckFeatures, /On fail goto//Label 1025/ GIMT_Encode4(`33705`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1324 //
12949	/ 33670 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12950	/ 33675 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12951	/ 33678 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12952	/ 33681 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12953	/ 33685 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12954	/ 33689 / // (intrinsic_void 8186:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12955	/ 33689 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_PH_MM),
12956	/ 33692 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12957	/ 33694 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12958	/ 33696 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12959	/ 33699 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12960	/ 33703 / GIR_RootConstrainSelectedInstOperands,
12961	/ 33704 / // GIR_Coverage, 1324,
12962	/ 33704 / GIR_EraseRootFromParent_Done,
12963	/ 33705 / // Label 1025: @33705
12964	/ 33705 / GIM_Try_CheckFeatures, /On fail goto//Label 1026/ GIMT_Encode4(`33747`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1325 //
12965	/ 33712 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
12966	/ 33717 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s16,
12967	/ 33720 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
12968	/ 33723 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12969	/ 33727 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12970	/ 33731 / // (intrinsic_void 8185:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)*
12971	/ 33731 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_PH_MM),
12972	/ 33734 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12973	/ 33736 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12974	/ 33738 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12975	/ 33741 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12976	/ 33745 / GIR_RootConstrainSelectedInstOperands,
12977	/ 33746 / // GIR_Coverage, 1325,
12978	/ 33746 / GIR_EraseRootFromParent_Done,
12979	/ 33747 / // Label 1026: @33747
12980	/ 33747 / GIM_Try_CheckFeatures, /On fail goto//Label 1027/ GIMT_Encode4(`33789`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1329 //
12981	/ 33754 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
12982	/ 33759 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
12983	/ 33762 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
12984	/ 33765 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12985	/ 33769 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
12986	/ 33773 / // (intrinsic_void 8193:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
12987	/ 33773 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
12988	/ 33776 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
12989	/ 33778 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
12990	/ 33780 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
12991	/ 33783 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
12992	/ 33787 / GIR_RootConstrainSelectedInstOperands,
12993	/ 33788 / // GIR_Coverage, 1329,
12994	/ 33788 / GIR_EraseRootFromParent_Done,
12995	/ 33789 / // Label 1027: @33789
12996	/ 33789 / GIM_Try_CheckFeatures, /On fail goto//Label 1028/ GIMT_Encode4(`33831`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1330 //
12997	/ 33796 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
12998	/ 33801 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
12999	/ 33804 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13000	/ 33807 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13001	/ 33811 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13002	/ 33815 / // (intrinsic_void 8195:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
13003	/ 33815 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13004	/ 33818 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
13005	/ 33820 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13006	/ 33822 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
13007	/ 33825 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13008	/ 33829 / GIR_RootConstrainSelectedInstOperands,
13009	/ 33830 / // GIR_Coverage, 1330,
13010	/ 33830 / GIR_EraseRootFromParent_Done,
13011	/ 33831 / // Label 1028: @33831
13012	/ 33831 / GIM_Try_CheckFeatures, /On fail goto//Label 1029/ GIMT_Encode4(`33873`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1331 //
13013	/ 33838 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13014	/ 33843 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s8,
13015	/ 33846 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13016	/ 33849 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13017	/ 33853 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13018	/ 33857 / // (intrinsic_void 8194:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)*
13019	/ 33857 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13020	/ 33860 / GIR_RootToRootCopy, /OpIdx/`1`, // rs
13021	/ 33862 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13022	/ 33864 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
13023	/ 33867 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13024	/ 33871 / GIR_RootConstrainSelectedInstOperands,
13025	/ 33872 / // GIR_Coverage, 1331,
13026	/ 33872 / GIR_EraseRootFromParent_Done,
13027	/ 33873 / // Label 1029: @33873
13028	/ 33873 / GIM_Reject,
13029	/ 33874 / // Label 1005: @33874
13030	/ 33874 / GIM_Try, /On fail goto//Label 1030/ GIMT_Encode4(`37905`),
13031	/ 33879 / GIM_CheckNumOperands, /MI/`0`, /Expected/`4`,
13032	/ 33882 / GIM_Try_CheckFeatures, /On fail goto//Label 1031/ GIMT_Encode4(`33945`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 409 //
13033	/ 33889 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13034	/ 33894 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13035	/ 33897 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13036	/ 33900 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13037	/ 33903 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13038	/ 33907 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13039	/ 33911 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13040	/ 33915 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13041	/ 33919 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13042	/ 33923 / // MIs[1] Operand 1
13043	/ 33923 / // No operand predicates
13044	/ 33923 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13045	/* 33925 / // (intrinsic_w_chain:{ :[v2i16] } 8571:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, (imm:{ :[i32] }):$rs_sa)
13046	/ 33925 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_S_PH),
13047	/ 33928 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13048	/ 33930 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13049	/ 33932 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // rs_sa
13050	/ 33935 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13051	/ 33938 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
13052	/ 33943 / GIR_RootConstrainSelectedInstOperands,
13053	/ 33944 / // GIR_Coverage, 409,
13054	/ 33944 / GIR_EraseRootFromParent_Done,
13055	/ 33945 / // Label 1031: @33945
13056	/ 33945 / GIM_Try_CheckFeatures, /On fail goto//Label 1032/ GIMT_Encode4(`34008`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 414 //
13057	/ 33952 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13058	/ 33957 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13059	/ 33960 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13060	/ 33963 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13061	/ 33966 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13062	/ 33970 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13063	/ 33974 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13064	/ 33978 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13065	/ 33982 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13066	/ 33986 / // MIs[1] Operand 1
13067	/ 33986 / // No operand predicates
13068	/ 33986 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13069	/* 33988 / // (intrinsic_w_chain:{ :[i32] } 8572:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$rs_sa)
13070	/ 33988 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_S_W),
13071	/ 33991 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13072	/ 33993 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13073	/ 33995 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // rs_sa
13074	/ 33998 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13075	/ 34001 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
13076	/ 34006 / GIR_RootConstrainSelectedInstOperands,
13077	/ 34007 / // GIR_Coverage, 414,
13078	/ 34007 / GIR_EraseRootFromParent_Done,
13079	/ 34008 / // Label 1032: @34008
13080	/ 34008 / GIM_Try_CheckFeatures, /On fail goto//Label 1033/ GIMT_Encode4(`34071`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1260 //
13081	/ 34015 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13082	/ 34020 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13083	/ 34023 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13084	/ 34026 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13085	/ 34029 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13086	/ 34033 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13087	/ 34037 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13088	/ 34041 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13089	/ 34045 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13090	/ 34049 / // MIs[1] Operand 1
13091	/ 34049 / // No operand predicates
13092	/ 34049 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13093	/* 34051 / // (intrinsic_w_chain:{ :[v2i16] } 8571:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, (imm:{ :[i32] }):$sa)
13094	/ 34051 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_S_PH_MM),
13095	/ 34054 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
13096	/ 34056 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13097	/ 34058 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // sa
13098	/ 34061 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13099	/ 34064 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
13100	/ 34069 / GIR_RootConstrainSelectedInstOperands,
13101	/ 34070 / // GIR_Coverage, 1260,
13102	/ 34070 / GIR_EraseRootFromParent_Done,
13103	/ 34071 / // Label 1033: @34071
13104	/ 34071 / GIM_Try_CheckFeatures, /On fail goto//Label 1034/ GIMT_Encode4(`34134`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1265 //
13105	/ 34078 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13106	/ 34083 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13107	/ 34086 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13108	/ 34089 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13109	/ 34092 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13110	/ 34096 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13111	/ 34100 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13112	/ 34104 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13113	/ 34108 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13114	/ 34112 / // MIs[1] Operand 1
13115	/ 34112 / // No operand predicates
13116	/ 34112 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13117	/* 34114 / // (intrinsic_w_chain:{ :[i32] } 8572:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, (imm:{ :[i32] }):$sa)
13118	/ 34114 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_S_W_MM),
13119	/ 34117 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
13120	/ 34119 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13121	/ 34121 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // sa
13122	/ 34124 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13123	/ 34127 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`2`, /MergeInsnID's/`0`, `1`,
13124	/ 34132 / GIR_RootConstrainSelectedInstOperands,
13125	/ 34133 / // GIR_Coverage, 1265,
13126	/ 34133 / GIR_EraseRootFromParent_Done,
13127	/ 34134 / // Label 1034: @34134
13128	/ 34134 / GIM_Try_CheckFeatures, /On fail goto//Label 1035/ GIMT_Encode4(`34188`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2069 //
13129	/ 34141 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_ph),
13130	/ 34146 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13131	/ 34149 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13132	/ 34152 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13133	/ 34155 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13134	/ 34159 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13135	/ 34163 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13136	/ 34167 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13137	/ 34171 / // MIs[1] Operand 1
13138	/ 34171 / // No operand predicates
13139	/ 34171 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13140	/* 34173 / // (intrinsic_w_chain:{ :[v2i16] } 8569:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$shamt)
13141	/ 34173 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_PH),
13142	/ 34176 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13143	/ 34178 / GIR_RootToRootCopy, /OpIdx/`2`, // a
13144	/ 34180 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
13145	/ 34183 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13146	/ 34186 / GIR_RootConstrainSelectedInstOperands,
13147	/ 34187 / // GIR_Coverage, 2069,
13148	/ 34187 / GIR_EraseRootFromParent_Done,
13149	/ 34188 / // Label 1035: @34188
13150	/ 34188 / GIM_Try_CheckFeatures, /On fail goto//Label 1036/ GIMT_Encode4(`34242`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2075 //
13151	/ 34195 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_qb),
13152	/ 34200 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13153	/ 34203 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13154	/ 34206 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13155	/ 34209 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13156	/ 34213 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`3`, // MIs[1]
13157	/ 34217 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13158	/ 34221 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
13159	/ 34225 / // MIs[1] Operand 1
13160	/ 34225 / // No operand predicates
13161	/ 34225 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
13162	/* 34227 / // (intrinsic_w_chain:{ :[v4i8] } 8570:{ :[iPTR] }, v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ :[v4i8] } v4i8:{ :[v4i8] }:$a, (imm:{ :[i32] })<<P:Predicate_immZExt3>>:$shamt)
13163	/ 34227 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLL_QB),
13164	/ 34230 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13165	/ 34232 / GIR_RootToRootCopy, /OpIdx/`2`, // a
13166	/ 34234 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
13167	/ 34237 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13168	/ 34240 / GIR_RootConstrainSelectedInstOperands,
13169	/ 34241 / // GIR_Coverage, 2075,
13170	/ 34241 / GIR_EraseRootFromParent_Done,
13171	/ 34242 / // Label 1036: @34242
13172	/ 34242 / GIM_Try_CheckFeatures, /On fail goto//Label 1037/ GIMT_Encode4(`34293`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 386 //
13173	/ 34249 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13174	/ 34254 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13175	/ 34257 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13176	/ 34260 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13177	/ 34263 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13178	/ 34267 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13179	/ 34271 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13180	/* 34275 / // (intrinsic_w_chain:{ :[i32] } 8024:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQ_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13181	/ 34275 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQ_S_W),
13182	/ 34278 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13183	/ 34280 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13184	/ 34282 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13185	/ 34284 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13186	/ 34287 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13187	/ 34291 / GIR_RootConstrainSelectedInstOperands,
13188	/ 34292 / // GIR_Coverage, 386,
13189	/ 34292 / GIR_EraseRootFromParent_Done,
13190	/ 34293 / // Label 1037: @34293
13191	/ 34293 / GIM_Try_CheckFeatures, /On fail goto//Label 1038/ GIMT_Encode4(`34344`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 387 //
13192	/ 34300 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13193	/ 34305 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13194	/ 34308 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13195	/ 34311 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13196	/ 34314 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13197	/ 34318 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13198	/ 34322 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13199	/* 34326 / // (intrinsic_w_chain:{ :[i32] } 8644:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQ_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13200	/ 34326 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQ_S_W),
13201	/ 34329 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13202	/ 34331 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13203	/ 34333 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13204	/ 34335 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13205	/ 34338 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13206	/ 34342 / GIR_RootConstrainSelectedInstOperands,
13207	/ 34343 / // GIR_Coverage, 387,
13208	/ 34343 / GIR_EraseRootFromParent_Done,
13209	/ 34344 / // Label 1038: @34344
13210	/ 34344 / GIM_Try_CheckFeatures, /On fail goto//Label 1039/ GIMT_Encode4(`34395`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 394 //
13211	/ 34351 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
13212	/ 34356 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13213	/ 34359 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13214	/ 34362 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13215	/ 34365 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13216	/ 34369 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13217	/ 34373 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13218	/* 34377 / // (intrinsic_w_chain:{ :[v2i16] } 8550:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (PRECRQ_RS_PH_W:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13219	/ 34377 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
13220	/ 34380 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13221	/ 34382 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13222	/ 34384 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13223	/ 34386 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13224	/ 34389 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13225	/ 34393 / GIR_RootConstrainSelectedInstOperands,
13226	/ 34394 / // GIR_Coverage, 394,
13227	/ 34394 / GIR_EraseRootFromParent_Done,
13228	/ 34395 / // Label 1039: @34395
13229	/ 34395 / GIM_Try_CheckFeatures, /On fail goto//Label 1040/ GIMT_Encode4(`34446`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 395 //
13230	/ 34402 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13231	/ 34407 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13232	/ 34410 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13233	/ 34413 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13234	/ 34416 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13235	/ 34420 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13236	/ 34424 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13237	/* 34428 / // (intrinsic_w_chain:{ :[v4i8] } 8551:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13238	/ 34428 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
13239	/ 34431 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13240	/ 34433 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13241	/ 34435 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13242	/ 34437 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13243	/ 34440 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13244	/ 34444 / GIR_RootConstrainSelectedInstOperands,
13245	/ 34445 / // GIR_Coverage, 395,
13246	/ 34445 / GIR_EraseRootFromParent_Done,
13247	/ 34446 / // Label 1040: @34446
13248	/ 34446 / GIM_Try_CheckFeatures, /On fail goto//Label 1041/ GIMT_Encode4(`34497`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 406 //
13249	/ 34453 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_qb),
13250	/ 34458 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13251	/ 34461 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13252	/ 34464 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13253	/ 34467 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13254	/ 34471 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13255	/ 34475 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13256	/* 34479 / // (intrinsic_w_chain:{ :[v4i8] } 8570:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHLLV_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
13257	/ 34479 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_QB),
13258	/ 34482 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13259	/ 34484 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13260	/ 34486 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
13261	/ 34488 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13262	/ 34491 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13263	/ 34495 / GIR_RootConstrainSelectedInstOperands,
13264	/ 34496 / // GIR_Coverage, 406,
13265	/ 34496 / GIR_EraseRootFromParent_Done,
13266	/ 34497 / // Label 1041: @34497
13267	/ 34497 / GIM_Try_CheckFeatures, /On fail goto//Label 1042/ GIMT_Encode4(`34548`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 408 //
13268	/ 34504 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_ph),
13269	/ 34509 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13270	/ 34512 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13271	/ 34515 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13272	/ 34518 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13273	/ 34522 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13274	/ 34526 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13275	/* 34530 / // (intrinsic_w_chain:{ :[v2i16] } 8569:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHLLV_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
13276	/ 34530 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_PH),
13277	/ 34533 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13278	/ 34535 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13279	/ 34537 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
13280	/ 34539 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13281	/ 34542 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13282	/ 34546 / GIR_RootConstrainSelectedInstOperands,
13283	/ 34547 / // GIR_Coverage, 408,
13284	/ 34547 / GIR_EraseRootFromParent_Done,
13285	/ 34548 / // Label 1042: @34548
13286	/ 34548 / GIM_Try_CheckFeatures, /On fail goto//Label 1043/ GIMT_Encode4(`34599`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 410 //
13287	/ 34555 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13288	/ 34560 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13289	/ 34563 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13290	/ 34566 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13291	/ 34569 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13292	/ 34573 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13293	/ 34577 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13294	/* 34581 / // (intrinsic_w_chain:{ :[v2i16] } 8571:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHLLV_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
13295	/ 34581 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_S_PH),
13296	/ 34584 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13297	/ 34586 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13298	/ 34588 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
13299	/ 34590 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13300	/ 34593 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13301	/ 34597 / GIR_RootConstrainSelectedInstOperands,
13302	/ 34598 / // GIR_Coverage, 410,
13303	/ 34598 / GIR_EraseRootFromParent_Done,
13304	/ 34599 / // Label 1043: @34599
13305	/ 34599 / GIM_Try_CheckFeatures, /On fail goto//Label 1044/ GIMT_Encode4(`34650`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 415 //
13306	/ 34606 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13307	/ 34611 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13308	/ 34614 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13309	/ 34617 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13310	/ 34620 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13311	/ 34624 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13312	/ 34628 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13313	/* 34632 / // (intrinsic_w_chain:{ :[i32] } 8572:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa) => (SHLLV_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs_sa)
13314	/ 34632 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_S_W),
13315	/ 34635 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13316	/ 34637 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13317	/ 34639 / GIR_RootToRootCopy, /OpIdx/`3`, // rs_sa
13318	/ 34641 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13319	/ 34644 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13320	/ 34648 / GIR_RootConstrainSelectedInstOperands,
13321	/ 34649 / // GIR_Coverage, 415,
13322	/ 34649 / GIR_EraseRootFromParent_Done,
13323	/ 34650 / // Label 1044: @34650
13324	/ 34650 / GIM_Try_CheckFeatures, /On fail goto//Label 1045/ GIMT_Encode4(`34701`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 418 //
13325	/ 34657 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13326	/ 34662 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13327	/ 34665 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13328	/ 34668 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13329	/ 34671 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13330	/ 34675 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13331	/ 34679 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13332	/* 34683 / // (intrinsic_w_chain:{ :[v2i16] } 8492:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13333	/ 34683 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
13334	/ 34686 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13335	/ 34688 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13336	/ 34690 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13337	/ 34692 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13338	/ 34695 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13339	/ 34699 / GIR_RootConstrainSelectedInstOperands,
13340	/ 34700 / // GIR_Coverage, 418,
13341	/ 34700 / GIR_EraseRootFromParent_Done,
13342	/ 34701 / // Label 1045: @34701
13343	/ 34701 / GIM_Try_CheckFeatures, /On fail goto//Label 1046/ GIMT_Encode4(`34752`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 419 //
13344	/ 34708 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13345	/ 34713 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13346	/ 34716 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13347	/ 34719 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13348	/ 34722 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13349	/ 34726 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13350	/ 34730 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13351	/* 34734 / // (intrinsic_w_chain:{ :[v2i16] } 8493:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13352	/ 34734 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
13353	/ 34737 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13354	/ 34739 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13355	/ 34741 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13356	/ 34743 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13357	/ 34746 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13358	/ 34750 / GIR_RootConstrainSelectedInstOperands,
13359	/ 34751 / // GIR_Coverage, 419,
13360	/ 34751 / GIR_EraseRootFromParent_Done,
13361	/ 34752 / // Label 1046: @34752
13362	/ 34752 / GIM_Try_CheckFeatures, /On fail goto//Label 1047/ GIMT_Encode4(`34803`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 420 //
13363	/ 34759 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13364	/ 34764 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13365	/ 34767 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13366	/ 34770 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13367	/ 34773 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13368	/ 34777 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13369	/ 34781 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13370	/* 34785 / // (intrinsic_w_chain:{ :[i32] } 8490:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13371	/ 34785 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
13372	/ 34788 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13373	/ 34790 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13374	/ 34792 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13375	/ 34794 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13376	/ 34797 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13377	/ 34801 / GIR_RootConstrainSelectedInstOperands,
13378	/ 34802 / // GIR_Coverage, 420,
13379	/ 34802 / GIR_EraseRootFromParent_Done,
13380	/ 34803 / // Label 1047: @34803
13381	/ 34803 / GIM_Try_CheckFeatures, /On fail goto//Label 1048/ GIMT_Encode4(`34854`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 421 //
13382	/ 34810 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13383	/ 34815 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13384	/ 34818 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13385	/ 34821 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13386	/ 34824 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13387	/ 34828 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13388	/ 34832 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13389	/* 34836 / // (intrinsic_w_chain:{ :[i32] } 8491:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13390	/ 34836 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
13391	/ 34839 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13392	/ 34841 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13393	/ 34843 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13394	/ 34845 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13395	/ 34848 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13396	/ 34852 / GIR_RootConstrainSelectedInstOperands,
13397	/ 34853 / // GIR_Coverage, 421,
13398	/ 34853 / GIR_EraseRootFromParent_Done,
13399	/ 34854 / // Label 1048: @34854
13400	/ 34854 / GIM_Try_CheckFeatures, /On fail goto//Label 1049/ GIMT_Encode4(`34905`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 422 //
13401	/ 34861 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13402	/ 34866 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13403	/ 34869 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13404	/ 34872 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13405	/ 34875 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13406	/ 34879 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13407	/ 34883 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13408	/* 34887 / // (intrinsic_w_chain:{ :[v2i16] } 8494:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULQ_RS_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13409	/ 34887 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_RS_PH),
13410	/ 34890 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13411	/ 34892 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13412	/ 34894 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13413	/ 34896 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13414	/ 34899 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13415	/ 34903 / GIR_RootConstrainSelectedInstOperands,
13416	/ 34904 / // GIR_Coverage, 422,
13417	/ 34904 / GIR_EraseRootFromParent_Done,
13418	/ 34905 / // Label 1049: @34905
13419	/ 34905 / GIM_Try_CheckFeatures, /On fail goto//Label 1050/ GIMT_Encode4(`34953`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 447 //
13420	/ 34912 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
13421	/ 34917 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13422	/ 34920 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13423	/ 34923 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13424	/ 34926 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13425	/ 34930 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13426	/ 34934 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13427	/* 34938 / // (intrinsic_w_chain:{ :[i32] } 8190:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_EQ_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13428	/ 34938 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_EQ_QB),
13429	/ 34941 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13430	/ 34943 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13431	/ 34945 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13432	/ 34947 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13433	/ 34951 / GIR_RootConstrainSelectedInstOperands,
13434	/ 34952 / // GIR_Coverage, 447,
13435	/ 34952 / GIR_EraseRootFromParent_Done,
13436	/ 34953 / // Label 1050: @34953
13437	/ 34953 / GIM_Try_CheckFeatures, /On fail goto//Label 1051/ GIMT_Encode4(`35001`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 448 //
13438	/ 34960 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
13439	/ 34965 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13440	/ 34968 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13441	/ 34971 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13442	/ 34974 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13443	/ 34978 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13444	/ 34982 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13445	/* 34986 / // (intrinsic_w_chain:{ :[i32] } 8192:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_LT_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13446	/ 34986 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_LT_QB),
13447	/ 34989 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13448	/ 34991 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13449	/ 34993 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13450	/ 34995 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13451	/ 34999 / GIR_RootConstrainSelectedInstOperands,
13452	/ 35000 / // GIR_Coverage, 448,
13453	/ 35000 / GIR_EraseRootFromParent_Done,
13454	/ 35001 / // Label 1051: @35001
13455	/ 35001 / GIM_Try_CheckFeatures, /On fail goto//Label 1052/ GIMT_Encode4(`35049`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 449 //
13456	/ 35008 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
13457	/ 35013 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13458	/ 35016 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13459	/ 35019 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13460	/ 35022 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13461	/ 35026 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13462	/ 35030 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13463	/* 35034 / // (intrinsic_w_chain:{ :[i32] } 8191:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_LE_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13464	/ 35034 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_LE_QB),
13465	/ 35037 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13466	/ 35039 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13467	/ 35041 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13468	/ 35043 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13469	/ 35047 / GIR_RootConstrainSelectedInstOperands,
13470	/ 35048 / // GIR_Coverage, 449,
13471	/ 35048 / GIR_EraseRootFromParent_Done,
13472	/ 35049 / // Label 1052: @35049
13473	/ 35049 / GIM_Try_CheckFeatures, /On fail goto//Label 1053/ GIMT_Encode4(`35097`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 459 //
13474	/ 35056 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_pick_qb),
13475	/ 35061 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13476	/ 35064 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13477	/ 35067 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13478	/ 35070 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13479	/ 35074 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13480	/ 35078 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13481	/* 35082 / // (intrinsic_w_chain:{ :[v4i8] } 8534:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (PICK_QB:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13482	/ 35082 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PICK_QB),
13483	/ 35085 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13484	/ 35087 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13485	/ 35089 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13486	/ 35091 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13487	/ 35095 / GIR_RootConstrainSelectedInstOperands,
13488	/ 35096 / // GIR_Coverage, 459,
13489	/ 35096 / GIR_EraseRootFromParent_Done,
13490	/ 35097 / // Label 1053: @35097
13491	/ 35097 / GIM_Try_CheckFeatures, /On fail goto//Label 1054/ GIMT_Encode4(`35145`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 460 //
13492	/ 35104 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_pick_ph),
13493	/ 35109 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13494	/ 35112 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13495	/ 35115 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13496	/ 35118 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13497	/ 35122 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13498	/ 35126 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13499	/* 35130 / // (intrinsic_w_chain:{ :[v2i16] } 8533:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PICK_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13500	/ 35130 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PICK_PH),
13501	/ 35133 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13502	/ 35135 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13503	/ 35137 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13504	/ 35139 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13505	/ 35143 / GIR_RootConstrainSelectedInstOperands,
13506	/ 35144 / // GIR_Coverage, 460,
13507	/ 35144 / GIR_EraseRootFromParent_Done,
13508	/ 35145 / // Label 1054: @35145
13509	/ 35145 / GIM_Try_CheckFeatures, /On fail goto//Label 1055/ GIMT_Encode4(`35193`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 464 //
13510	/ 35152 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_insv),
13511	/ 35157 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13512	/ 35160 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13513	/ 35163 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13514	/ 35166 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13515	/ 35170 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13516	/ 35174 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13517	/* 35178 / // (intrinsic_w_chain:{ :[i32] } 8392:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs) => (INSV:{ :[i32] } GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs)
13518	/ 35178 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSV),
13519	/ 35181 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
13520	/ 35183 / GIR_RootToRootCopy, /OpIdx/`2`, // src
13521	/ 35185 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13522	/ 35187 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13523	/ 35191 / GIR_RootConstrainSelectedInstOperands,
13524	/ 35192 / // GIR_Coverage, 464,
13525	/ 35192 / GIR_EraseRootFromParent_Done,
13526	/ 35193 / // Label 1055: @35193
13527	/ 35193 / GIM_Try_CheckFeatures, /On fail goto//Label 1056/ GIMT_Encode4(`35244`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 470 //
13528	/ 35200 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_ph),
13529	/ 35205 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13530	/ 35208 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13531	/ 35211 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13532	/ 35214 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13533	/ 35218 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13534	/ 35222 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13535	/* 35226 / // (intrinsic_w_chain:{ :[v2i16] } 8042:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDU_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13536	/ 35226 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_PH),
13537	/ 35229 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13538	/ 35231 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13539	/ 35233 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13540	/ 35235 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13541	/ 35238 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13542	/ 35242 / GIR_RootConstrainSelectedInstOperands,
13543	/ 35243 / // GIR_Coverage, 470,
13544	/ 35243 / GIR_EraseRootFromParent_Done,
13545	/ 35244 / // Label 1056: @35244
13546	/ 35244 / GIM_Try_CheckFeatures, /On fail goto//Label 1057/ GIMT_Encode4(`35295`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 471 //
13547	/ 35251 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
13548	/ 35256 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13549	/ 35259 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13550	/ 35262 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13551	/ 35265 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13552	/ 35269 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13553	/ 35273 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13554	/* 35277 / // (intrinsic_w_chain:{ :[v2i16] } 8044:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDU_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13555	/ 35277 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_S_PH),
13556	/ 35280 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13557	/ 35282 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13558	/ 35284 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13559	/ 35286 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13560	/ 35289 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13561	/ 35293 / GIR_RootConstrainSelectedInstOperands,
13562	/ 35294 / // GIR_Coverage, 471,
13563	/ 35294 / GIR_EraseRootFromParent_Done,
13564	/ 35295 / // Label 1057: @35295
13565	/ 35295 / GIM_Try_CheckFeatures, /On fail goto//Label 1058/ GIMT_Encode4(`35346`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 472 //
13566	/ 35302 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_ph),
13567	/ 35307 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13568	/ 35310 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13569	/ 35313 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13570	/ 35316 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13571	/ 35320 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13572	/ 35324 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13573	/* 35328 / // (intrinsic_w_chain:{ :[v2i16] } 8665:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBU_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13574	/ 35328 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_PH),
13575	/ 35331 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13576	/ 35333 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13577	/ 35335 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13578	/ 35337 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13579	/ 35340 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13580	/ 35344 / GIR_RootConstrainSelectedInstOperands,
13581	/ 35345 / // GIR_Coverage, 472,
13582	/ 35345 / GIR_EraseRootFromParent_Done,
13583	/ 35346 / // Label 1058: @35346
13584	/ 35346 / GIM_Try_CheckFeatures, /On fail goto//Label 1059/ GIMT_Encode4(`35397`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 473 //
13585	/ 35353 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
13586	/ 35358 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13587	/ 35361 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13588	/ 35364 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13589	/ 35367 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13590	/ 35371 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13591	/ 35375 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13592	/* 35379 / // (intrinsic_w_chain:{ :[v2i16] } 8667:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBU_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13593	/ 35379 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_S_PH),
13594	/ 35382 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13595	/ 35384 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13596	/ 35386 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13597	/ 35388 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13598	/ 35391 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13599	/ 35395 / GIR_RootConstrainSelectedInstOperands,
13600	/ 35396 / // GIR_Coverage, 473,
13601	/ 35396 / GIR_EraseRootFromParent_Done,
13602	/ 35397 / // Label 1059: @35397
13603	/ 35397 / GIM_Try_CheckFeatures, /On fail goto//Label 1060/ GIMT_Encode4(`35448`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 474 //
13604	/ 35404 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13605	/ 35409 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13606	/ 35412 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13607	/ 35415 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13608	/ 35418 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13609	/ 35422 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13610	/ 35426 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13611	/* 35430 / // (intrinsic_w_chain:{ :[i32] } 8187:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13612	/ 35430 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
13613	/ 35433 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13614	/ 35435 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13615	/ 35437 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13616	/ 35439 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
13617	/ 35442 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13618	/ 35446 / GIR_RootConstrainSelectedInstOperands,
13619	/ 35447 / // GIR_Coverage, 474,
13620	/ 35447 / GIR_EraseRootFromParent_Done,
13621	/ 35448 / // Label 1060: @35448
13622	/ 35448 / GIM_Try_CheckFeatures, /On fail goto//Label 1061/ GIMT_Encode4(`35499`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 475 //
13623	/ 35455 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13624	/ 35460 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13625	/ 35463 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13626	/ 35466 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13627	/ 35469 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13628	/ 35473 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13629	/ 35477 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13630	/* 35481 / // (intrinsic_w_chain:{ :[i32] } 8189:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_LT_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13631	/ 35481 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_LT_QB),
13632	/ 35484 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13633	/ 35486 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13634	/ 35488 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13635	/ 35490 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
13636	/ 35493 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13637	/ 35497 / GIR_RootConstrainSelectedInstOperands,
13638	/ 35498 / // GIR_Coverage, 475,
13639	/ 35498 / GIR_EraseRootFromParent_Done,
13640	/ 35499 / // Label 1061: @35499
13641	/ 35499 / GIM_Try_CheckFeatures, /On fail goto//Label 1062/ GIMT_Encode4(`35550`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 476 //
13642	/ 35506 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13643	/ 35511 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13644	/ 35514 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13645	/ 35517 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
13646	/ 35520 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13647	/ 35524 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13648	/ 35528 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13649	/* 35532 / // (intrinsic_w_chain:{ :[i32] } 8188:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_LE_QB:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
13650	/ 35532 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_LE_QB),
13651	/ 35535 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13652	/ 35537 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13653	/ 35539 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13654	/ 35541 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
13655	/ 35544 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13656	/ 35548 / GIR_RootConstrainSelectedInstOperands,
13657	/ 35549 / // GIR_Coverage, 476,
13658	/ 35549 / GIR_EraseRootFromParent_Done,
13659	/ 35550 / // Label 1062: @35550
13660	/ 35550 / GIM_Try_CheckFeatures, /On fail goto//Label 1063/ GIMT_Encode4(`35601`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 490 //
13661	/ 35557 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13662	/ 35562 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13663	/ 35565 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13664	/ 35568 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13665	/ 35571 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13666	/ 35575 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13667	/ 35579 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13668	/* 35583 / // (intrinsic_w_chain:{ :[v2i16] } 8489:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MUL_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13669	/ 35583 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MUL_S_PH),
13670	/ 35586 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13671	/ 35588 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13672	/ 35590 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13673	/ 35592 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13674	/ 35595 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13675	/ 35599 / GIR_RootConstrainSelectedInstOperands,
13676	/ 35600 / // GIR_Coverage, 490,
13677	/ 35600 / GIR_EraseRootFromParent_Done,
13678	/ 35601 / // Label 1063: @35601
13679	/ 35601 / GIM_Try_CheckFeatures, /On fail goto//Label 1064/ GIMT_Encode4(`35652`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 491 //
13680	/ 35608 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13681	/ 35613 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13682	/ 35616 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13683	/ 35619 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13684	/ 35622 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13685	/ 35626 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13686	/ 35630 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13687	/* 35634 / // (intrinsic_w_chain:{ :[i32] } 8497:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MULQ_S_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13688	/ 35634 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_S_W),
13689	/ 35637 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13690	/ 35639 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13691	/ 35641 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13692	/ 35643 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13693	/ 35646 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13694	/ 35650 / GIR_RootConstrainSelectedInstOperands,
13695	/ 35651 / // GIR_Coverage, 491,
13696	/ 35651 / GIR_EraseRootFromParent_Done,
13697	/ 35652 / // Label 1064: @35652
13698	/ 35652 / GIM_Try_CheckFeatures, /On fail goto//Label 1065/ GIMT_Encode4(`35703`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 492 //
13699	/ 35659 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13700	/ 35664 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13701	/ 35667 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13702	/ 35670 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13703	/ 35673 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13704	/ 35677 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13705	/ 35681 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13706	/* 35685 / // (intrinsic_w_chain:{ :[i32] } 8495:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MULQ_RS_W:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13707	/ 35685 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_RS_W),
13708	/ 35688 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13709	/ 35690 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13710	/ 35692 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13711	/ 35694 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13712	/ 35697 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13713	/ 35701 / GIR_RootConstrainSelectedInstOperands,
13714	/ 35702 / // GIR_Coverage, 492,
13715	/ 35702 / GIR_EraseRootFromParent_Done,
13716	/ 35703 / // Label 1065: @35703
13717	/ 35703 / GIM_Try_CheckFeatures, /On fail goto//Label 1066/ GIMT_Encode4(`35754`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 493 //
13718	/ 35710 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13719	/ 35715 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13720	/ 35718 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13721	/ 35721 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13722	/ 35724 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13723	/ 35728 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13724	/ 35732 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13725	/* 35736 / // (intrinsic_w_chain:{ :[v2i16] } 8496:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULQ_S_PH:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13726	/ 35736 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_S_PH),
13727	/ 35739 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13728	/ 35741 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13729	/ 35743 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13730	/ 35745 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13731	/ 35748 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13732	/ 35752 / GIR_RootConstrainSelectedInstOperands,
13733	/ 35753 / // GIR_Coverage, 493,
13734	/ 35753 / GIR_EraseRootFromParent_Done,
13735	/ 35754 / // Label 1066: @35754
13736	/ 35754 / GIM_Try_CheckFeatures, /On fail goto//Label 1067/ GIMT_Encode4(`35802`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 503 //
13737	/ 35761 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13738	/ 35766 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13739	/ 35769 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13740	/ 35772 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13741	/ 35775 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13742	/ 35779 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13743	/ 35783 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13744	/* 35787 / // (intrinsic_w_chain:{ :[v4i8] } 8545:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECR_QB_PH:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13745	/ 35787 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_QB_PH),
13746	/ 35790 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13747	/ 35792 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13748	/ 35794 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13749	/ 35796 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13750	/ 35800 / GIR_RootConstrainSelectedInstOperands,
13751	/ 35801 / // GIR_Coverage, 503,
13752	/ 35801 / GIR_EraseRootFromParent_Done,
13753	/ 35802 / // Label 1067: @35802
13754	/ 35802 / GIM_Try_CheckFeatures, /On fail goto//Label 1068/ GIMT_Encode4(`35853`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1245 //
13755	/ 35809 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13756	/ 35814 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13757	/ 35817 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13758	/ 35820 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13759	/ 35823 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13760	/ 35827 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13761	/ 35831 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13762	/* 35835 / // (intrinsic_w_chain:{ :[i32] } 8024:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (ADDQ_S_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13763	/ 35835 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDQ_S_W_MM),
13764	/ 35838 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13765	/ 35840 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13766	/ 35842 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13767	/ 35844 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13768	/ 35847 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13769	/ 35851 / GIR_RootConstrainSelectedInstOperands,
13770	/ 35852 / // GIR_Coverage, 1245,
13771	/ 35852 / GIR_EraseRootFromParent_Done,
13772	/ 35853 / // Label 1068: @35853
13773	/ 35853 / GIM_Try_CheckFeatures, /On fail goto//Label 1069/ GIMT_Encode4(`35901`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1253 //
13774	/ 35860 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_insv),
13775	/ 35865 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13776	/ 35868 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13777	/ 35871 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13778	/ 35874 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13779	/ 35878 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13780	/ 35882 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13781	/* 35886 / // (intrinsic_w_chain:{ :[i32] } 8392:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs) => (INSV_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$src, GPR32Opnd:{ :[i32] }:$rs)
13782	/ 35886 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSV_MM),
13783	/ 35889 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
13784	/ 35891 / GIR_RootToRootCopy, /OpIdx/`2`, // src
13785	/ 35893 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13786	/ 35895 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13787	/ 35899 / GIR_RootConstrainSelectedInstOperands,
13788	/ 35900 / // GIR_Coverage, 1253,
13789	/ 35900 / GIR_EraseRootFromParent_Done,
13790	/ 35901 / // Label 1069: @35901
13791	/ 35901 / GIM_Try_CheckFeatures, /On fail goto//Label 1070/ GIMT_Encode4(`35952`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1261 //
13792	/ 35908 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_ph),
13793	/ 35913 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13794	/ 35916 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13795	/ 35919 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13796	/ 35922 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13797	/ 35926 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13798	/ 35930 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13799	/* 35934 / // (intrinsic_w_chain:{ :[v2i16] } 8569:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHLLV_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
13800	/ 35934 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_PH_MM),
13801	/ 35937 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13802	/ 35939 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13803	/ 35941 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13804	/ 35943 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13805	/ 35946 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13806	/ 35950 / GIR_RootConstrainSelectedInstOperands,
13807	/ 35951 / // GIR_Coverage, 1261,
13808	/ 35951 / GIR_EraseRootFromParent_Done,
13809	/ 35952 / // Label 1070: @35952
13810	/ 35952 / GIM_Try_CheckFeatures, /On fail goto//Label 1071/ GIMT_Encode4(`36003`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1262 //
13811	/ 35959 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13812	/ 35964 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13813	/ 35967 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13814	/ 35970 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13815	/ 35973 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13816	/ 35977 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13817	/ 35981 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13818	/* 35985 / // (intrinsic_w_chain:{ :[v2i16] } 8571:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHLLV_S_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
13819	/ 35985 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
13820	/ 35988 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13821	/ 35990 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13822	/ 35992 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13823	/ 35994 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13824	/ 35997 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13825	/ 36001 / GIR_RootConstrainSelectedInstOperands,
13826	/ 36002 / // GIR_Coverage, 1262,
13827	/ 36002 / GIR_EraseRootFromParent_Done,
13828	/ 36003 / // Label 1071: @36003
13829	/ 36003 / GIM_Try_CheckFeatures, /On fail goto//Label 1072/ GIMT_Encode4(`36054`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1263 //
13830	/ 36010 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_qb),
13831	/ 36015 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13832	/ 36018 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13833	/ 36021 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13834	/ 36024 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13835	/ 36028 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13836	/ 36032 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13837	/* 36036 / // (intrinsic_w_chain:{ :[v4i8] } 8570:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHLLV_QB_MM:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
13838	/ 36036 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_QB_MM),
13839	/ 36039 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13840	/ 36041 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13841	/ 36043 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13842	/ 36045 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13843	/ 36048 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13844	/ 36052 / GIR_RootConstrainSelectedInstOperands,
13845	/ 36053 / // GIR_Coverage, 1263,
13846	/ 36053 / GIR_EraseRootFromParent_Done,
13847	/ 36054 / // Label 1072: @36054
13848	/ 36054 / GIM_Try_CheckFeatures, /On fail goto//Label 1073/ GIMT_Encode4(`36105`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1264 //
13849	/ 36061 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13850	/ 36066 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13851	/ 36069 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13852	/ 36072 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13853	/ 36075 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13854	/ 36079 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13855	/ 36083 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13856	/* 36087 / // (intrinsic_w_chain:{ :[i32] } 8572:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SHLLV_S_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
13857	/ 36087 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SHLLV_S_W_MM),
13858	/ 36090 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13859	/ 36092 / GIR_RootToRootCopy, /OpIdx/`2`, // rt
13860	/ 36094 / GIR_RootToRootCopy, /OpIdx/`3`, // rs
13861	/ 36096 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13862	/ 36099 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13863	/ 36103 / GIR_RootConstrainSelectedInstOperands,
13864	/ 36104 / // GIR_Coverage, 1264,
13865	/ 36104 / GIR_EraseRootFromParent_Done,
13866	/ 36105 / // Label 1073: @36105
13867	/ 36105 / GIM_Try_CheckFeatures, /On fail goto//Label 1074/ GIMT_Encode4(`36156`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1283 //
13868	/ 36112 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13869	/ 36117 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13870	/ 36120 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
13871	/ 36123 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
13872	/ 36126 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13873	/ 36130 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13874	/ 36134 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13875	/* 36138 / // (intrinsic_w_chain:{ :[i32] } 8644:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (SUBQ_S_W_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
13876	/ 36138 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBQ_S_W_MM),
13877	/ 36141 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13878	/ 36143 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13879	/ 36145 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13880	/ 36147 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
13881	/ 36150 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13882	/ 36154 / GIR_RootConstrainSelectedInstOperands,
13883	/ 36155 / // GIR_Coverage, 1283,
13884	/ 36155 / GIR_EraseRootFromParent_Done,
13885	/ 36156 / // Label 1074: @36156
13886	/ 36156 / GIM_Try_CheckFeatures, /On fail goto//Label 1075/ GIMT_Encode4(`36207`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1289 //
13887	/ 36163 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13888	/ 36168 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13889	/ 36171 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13890	/ 36174 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13891	/ 36177 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13892	/ 36181 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13893	/ 36185 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13894	/* 36189 / // (intrinsic_w_chain:{ :[i32] } 8490:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13895	/ 36189 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
13896	/ 36192 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13897	/ 36194 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13898	/ 36196 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13899	/ 36198 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13900	/ 36201 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13901	/ 36205 / GIR_RootConstrainSelectedInstOperands,
13902	/ 36206 / // GIR_Coverage, 1289,
13903	/ 36206 / GIR_EraseRootFromParent_Done,
13904	/ 36207 / // Label 1075: @36207
13905	/ 36207 / GIM_Try_CheckFeatures, /On fail goto//Label 1076/ GIMT_Encode4(`36258`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1290 //
13906	/ 36214 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13907	/ 36219 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
13908	/ 36222 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13909	/ 36225 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13910	/ 36228 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
13911	/ 36232 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13912	/ 36236 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13913	/* 36240 / // (intrinsic_w_chain:{ :[i32] } 8491:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ :[i32] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13914	/ 36240 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
13915	/ 36243 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13916	/ 36245 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13917	/ 36247 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13918	/ 36249 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13919	/ 36252 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13920	/ 36256 / GIR_RootConstrainSelectedInstOperands,
13921	/ 36257 / // GIR_Coverage, 1290,
13922	/ 36257 / GIR_EraseRootFromParent_Done,
13923	/ 36258 / // Label 1076: @36258
13924	/ 36258 / GIM_Try_CheckFeatures, /On fail goto//Label 1077/ GIMT_Encode4(`36309`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1291 //
13925	/ 36265 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13926	/ 36270 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13927	/ 36273 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13928	/ 36276 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13929	/ 36279 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13930	/ 36283 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13931	/ 36287 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13932	/* 36291 / // (intrinsic_w_chain:{ :[v2i16] } 8492:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13933	/ 36291 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
13934	/ 36294 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13935	/ 36296 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13936	/ 36298 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13937	/ 36300 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13938	/ 36303 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13939	/ 36307 / GIR_RootConstrainSelectedInstOperands,
13940	/ 36308 / // GIR_Coverage, 1291,
13941	/ 36308 / GIR_EraseRootFromParent_Done,
13942	/ 36309 / // Label 1077: @36309
13943	/ 36309 / GIM_Try_CheckFeatures, /On fail goto//Label 1078/ GIMT_Encode4(`36360`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1292 //
13944	/ 36316 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13945	/ 36321 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13946	/ 36324 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
13947	/ 36327 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13948	/ 36330 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13949	/ 36334 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13950	/ 36338 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13951	/* 36342 / // (intrinsic_w_chain:{ :[v2i16] } 8493:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ :[v2i16] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13952	/ 36342 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
13953	/ 36345 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13954	/ 36347 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13955	/ 36349 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13956	/ 36351 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13957	/ 36354 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13958	/ 36358 / GIR_RootConstrainSelectedInstOperands,
13959	/ 36359 / // GIR_Coverage, 1292,
13960	/ 36359 / GIR_EraseRootFromParent_Done,
13961	/ 36360 / // Label 1078: @36360
13962	/ 36360 / GIM_Try_CheckFeatures, /On fail goto//Label 1079/ GIMT_Encode4(`36411`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1293 //
13963	/ 36367 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13964	/ 36372 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
13965	/ 36375 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13966	/ 36378 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13967	/ 36381 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13968	/ 36385 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13969	/ 36389 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13970	/* 36393 / // (intrinsic_w_chain:{ :[v2i16] } 8494:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13971	/ 36393 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
13972	/ 36396 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13973	/ 36398 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13974	/ 36400 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13975	/ 36402 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
13976	/ 36405 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13977	/ 36409 / GIR_RootConstrainSelectedInstOperands,
13978	/ 36410 / // GIR_Coverage, 1293,
13979	/ 36410 / GIR_EraseRootFromParent_Done,
13980	/ 36411 / // Label 1079: @36411
13981	/ 36411 / GIM_Try_CheckFeatures, /On fail goto//Label 1080/ GIMT_Encode4(`36462`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1296 //
13982	/ 36418 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13983	/ 36423 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
13984	/ 36426 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
13985	/ 36429 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
13986	/ 36432 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13987	/ 36436 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13988	/ 36440 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
13989	/* 36444 / // (intrinsic_w_chain:{ :[v4i8] } 8551:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
13990	/ 36444 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
13991	/ 36447 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
13992	/ 36449 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
13993	/ 36451 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
13994	/ 36453 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
13995	/ 36456 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
13996	/ 36460 / GIR_RootConstrainSelectedInstOperands,
13997	/ 36461 / // GIR_Coverage, 1296,
13998	/ 36461 / GIR_EraseRootFromParent_Done,
13999	/ 36462 / // Label 1080: @36462
14000	/ 36462 / GIM_Try_CheckFeatures, /On fail goto//Label 1081/ GIMT_Encode4(`36513`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1297 //
14001	/ 36469 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14002	/ 36474 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14003	/ 36477 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
14004	/ 36480 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14005	/ 36483 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14006	/ 36487 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14007	/ 36491 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14008	/* 36495 / // (intrinsic_w_chain:{ :[v2i16] } 8550:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ :[v2i16] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
14009	/ 36495 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14010	/ 36498 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14011	/ 36500 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14012	/ 36502 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14013	/ 36504 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag22/`0`,
14014	/ 36507 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14015	/ 36511 / GIR_RootConstrainSelectedInstOperands,
14016	/ 36512 / // GIR_Coverage, 1297,
14017	/ 36512 / GIR_EraseRootFromParent_Done,
14018	/ 36513 / // Label 1081: @36513
14019	/ 36513 / GIM_Try_CheckFeatures, /On fail goto//Label 1082/ GIMT_Encode4(`36561`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1315 //
14020	/ 36520 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_pick_ph),
14021	/ 36525 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14022	/ 36528 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14023	/ 36531 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14024	/ 36534 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14025	/ 36538 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14026	/ 36542 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14027	/* 36546 / // (intrinsic_w_chain:{ :[v2i16] } 8533:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PICK_PH_MM:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14028	/ 36546 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PICK_PH_MM),
14029	/ 36549 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14030	/ 36551 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14031	/ 36553 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14032	/ 36555 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14033	/ 36559 / GIR_RootConstrainSelectedInstOperands,
14034	/ 36560 / // GIR_Coverage, 1315,
14035	/ 36560 / GIR_EraseRootFromParent_Done,
14036	/ 36561 / // Label 1082: @36561
14037	/ 36561 / GIM_Try_CheckFeatures, /On fail goto//Label 1083/ GIMT_Encode4(`36609`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1316 //
14038	/ 36568 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_pick_qb),
14039	/ 36573 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
14040	/ 36576 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14041	/ 36579 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14042	/ 36582 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14043	/ 36586 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14044	/ 36590 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14045	/* 36594 / // (intrinsic_w_chain:{ :[v4i8] } 8534:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (PICK_QB_MM:{ :[v4i8] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14046	/ 36594 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PICK_QB_MM),
14047	/ 36597 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14048	/ 36599 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14049	/ 36601 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14050	/ 36603 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14051	/ 36607 / GIR_RootConstrainSelectedInstOperands,
14052	/ 36608 / // GIR_Coverage, 1316,
14053	/ 36608 / GIR_EraseRootFromParent_Done,
14054	/ 36609 / // Label 1083: @36609
14055	/ 36609 / GIM_Try_CheckFeatures, /On fail goto//Label 1084/ GIMT_Encode4(`36657`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1326 //
14056	/ 36616 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14057	/ 36621 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14058	/ 36624 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14059	/ 36627 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14060	/ 36630 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14061	/ 36634 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14062	/ 36638 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14063	/* 36642 / // (intrinsic_w_chain:{ :[i32] } 8190:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14064	/ 36642 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
14065	/ 36645 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14066	/ 36647 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14067	/ 36649 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14068	/ 36651 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14069	/ 36655 / GIR_RootConstrainSelectedInstOperands,
14070	/ 36656 / // GIR_Coverage, 1326,
14071	/ 36656 / GIR_EraseRootFromParent_Done,
14072	/ 36657 / // Label 1084: @36657
14073	/ 36657 / GIM_Try_CheckFeatures, /On fail goto//Label 1085/ GIMT_Encode4(`36705`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1327 //
14074	/ 36664 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14075	/ 36669 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14076	/ 36672 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14077	/ 36675 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14078	/ 36678 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14079	/ 36682 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14080	/ 36686 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14081	/* 36690 / // (intrinsic_w_chain:{ :[i32] } 8192:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14082	/ 36690 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
14083	/ 36693 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14084	/ 36695 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14085	/ 36697 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14086	/ 36699 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14087	/ 36703 / GIR_RootConstrainSelectedInstOperands,
14088	/ 36704 / // GIR_Coverage, 1327,
14089	/ 36704 / GIR_EraseRootFromParent_Done,
14090	/ 36705 / // Label 1085: @36705
14091	/ 36705 / GIM_Try_CheckFeatures, /On fail goto//Label 1086/ GIMT_Encode4(`36753`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1328 //
14092	/ 36712 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14093	/ 36717 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14094	/ 36720 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14095	/ 36723 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14096	/ 36726 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14097	/ 36730 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14098	/ 36734 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14099	/* 36738 / // (intrinsic_w_chain:{ :[i32] } 8191:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14100	/ 36738 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
14101	/ 36741 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14102	/ 36743 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14103	/ 36745 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14104	/ 36747 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14105	/ 36751 / GIR_RootConstrainSelectedInstOperands,
14106	/ 36752 / // GIR_Coverage, 1328,
14107	/ 36752 / GIR_EraseRootFromParent_Done,
14108	/ 36753 / // Label 1086: @36753
14109	/ 36753 / GIM_Try_CheckFeatures, /On fail goto//Label 1087/ GIMT_Encode4(`36804`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1337 //
14110	/ 36760 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_ph),
14111	/ 36765 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14112	/ 36768 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14113	/ 36771 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14114	/ 36774 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14115	/ 36778 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14116	/ 36782 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14117	/* 36786 / // (intrinsic_w_chain:{ :[v2i16] } 8042:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDU_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14118	/ 36786 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_PH_MMR2),
14119	/ 36789 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14120	/ 36791 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14121	/ 36793 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14122	/ 36795 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
14123	/ 36798 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14124	/ 36802 / GIR_RootConstrainSelectedInstOperands,
14125	/ 36803 / // GIR_Coverage, 1337,
14126	/ 36803 / GIR_EraseRootFromParent_Done,
14127	/ 36804 / // Label 1087: @36804
14128	/ 36804 / GIM_Try_CheckFeatures, /On fail goto//Label 1088/ GIMT_Encode4(`36855`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1338 //
14129	/ 36811 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14130	/ 36816 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14131	/ 36819 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14132	/ 36822 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14133	/ 36825 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14134	/ 36829 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14135	/ 36833 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14136	/* 36837 / // (intrinsic_w_chain:{ :[v2i16] } 8044:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14137	/ 36837 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
14138	/ 36840 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14139	/ 36842 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14140	/ 36844 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14141	/ 36846 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
14142	/ 36849 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14143	/ 36853 / GIR_RootConstrainSelectedInstOperands,
14144	/ 36854 / // GIR_Coverage, 1338,
14145	/ 36854 / GIR_EraseRootFromParent_Done,
14146	/ 36855 / // Label 1088: @36855
14147	/ 36855 / GIM_Try_CheckFeatures, /On fail goto//Label 1089/ GIMT_Encode4(`36906`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1349 //
14148	/ 36862 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14149	/ 36867 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14150	/ 36870 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14151	/ 36873 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14152	/ 36876 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14153	/ 36880 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14154	/ 36884 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14155	/* 36888 / // (intrinsic_w_chain:{ :[i32] } 8187:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14156	/ 36888 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
14157	/ 36891 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14158	/ 36893 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14159	/ 36895 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14160	/ 36897 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
14161	/ 36900 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14162	/ 36904 / GIR_RootConstrainSelectedInstOperands,
14163	/ 36905 / // GIR_Coverage, 1349,
14164	/ 36905 / GIR_EraseRootFromParent_Done,
14165	/ 36906 / // Label 1089: @36906
14166	/ 36906 / GIM_Try_CheckFeatures, /On fail goto//Label 1090/ GIMT_Encode4(`36957`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1350 //
14167	/ 36913 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14168	/ 36918 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14169	/ 36921 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14170	/ 36924 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14171	/ 36927 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14172	/ 36931 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14173	/ 36935 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14174	/* 36939 / // (intrinsic_w_chain:{ :[i32] } 8189:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14175	/ 36939 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
14176	/ 36942 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14177	/ 36944 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14178	/ 36946 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14179	/ 36948 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
14180	/ 36951 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14181	/ 36955 / GIR_RootConstrainSelectedInstOperands,
14182	/ 36956 / // GIR_Coverage, 1350,
14183	/ 36956 / GIR_EraseRootFromParent_Done,
14184	/ 36957 / // Label 1090: @36957
14185	/ 36957 / GIM_Try_CheckFeatures, /On fail goto//Label 1091/ GIMT_Encode4(`37008`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1351 //
14186	/ 36964 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14187	/ 36969 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14188	/ 36972 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s8,
14189	/ 36975 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s8,
14190	/ 36978 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14191	/ 36982 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14192	/ 36986 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14193	/* 36990 / // (intrinsic_w_chain:{ :[i32] } 8188:{ :[iPTR] }, DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ :[i32] } DSPROpnd:{ :[v4i8] }:$rs, DSPROpnd:{ :[v4i8] }:$rt)
14194	/ 36990 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
14195	/ 36993 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14196	/ 36995 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14197	/ 36997 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14198	/ 36999 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCCond/`0`,
14199	/ 37002 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14200	/ 37006 / GIR_RootConstrainSelectedInstOperands,
14201	/ 37007 / // GIR_Coverage, 1351,
14202	/ 37007 / GIR_EraseRootFromParent_Done,
14203	/ 37008 / // Label 1091: @37008
14204	/ 37008 / GIM_Try_CheckFeatures, /On fail goto//Label 1092/ GIMT_Encode4(`37059`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1357 //
14205	/ 37015 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_ph),
14206	/ 37020 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14207	/ 37023 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14208	/ 37026 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14209	/ 37029 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14210	/ 37033 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14211	/ 37037 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14212	/* 37041 / // (intrinsic_w_chain:{ :[v2i16] } 8665:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBU_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14213	/ 37041 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_PH_MMR2),
14214	/ 37044 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14215	/ 37046 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14216	/ 37048 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14217	/ 37050 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
14218	/ 37053 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14219	/ 37057 / GIR_RootConstrainSelectedInstOperands,
14220	/ 37058 / // GIR_Coverage, 1357,
14221	/ 37058 / GIR_EraseRootFromParent_Done,
14222	/ 37059 / // Label 1092: @37059
14223	/ 37059 / GIM_Try_CheckFeatures, /On fail goto//Label 1093/ GIMT_Encode4(`37110`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1358 //
14224	/ 37066 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14225	/ 37071 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14226	/ 37074 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14227	/ 37077 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14228	/ 37080 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14229	/ 37084 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14230	/ 37088 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14231	/* 37092 / // (intrinsic_w_chain:{ :[v2i16] } 8667:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14232	/ 37092 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
14233	/ 37095 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14234	/ 37097 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14235	/ 37099 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14236	/ 37101 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
14237	/ 37104 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14238	/ 37108 / GIR_RootConstrainSelectedInstOperands,
14239	/ 37109 / // GIR_Coverage, 1358,
14240	/ 37109 / GIR_EraseRootFromParent_Done,
14241	/ 37110 / // Label 1093: @37110
14242	/ 37110 / GIM_Try_CheckFeatures, /On fail goto//Label 1094/ GIMT_Encode4(`37161`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1365 //
14243	/ 37117 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14244	/ 37122 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14245	/ 37125 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14246	/ 37128 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14247	/ 37131 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14248	/ 37135 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14249	/ 37139 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14250	/* 37143 / // (intrinsic_w_chain:{ :[v2i16] } 8489:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14251	/ 37143 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
14252	/ 37146 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14253	/ 37148 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14254	/ 37150 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14255	/ 37152 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
14256	/ 37155 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14257	/ 37159 / GIR_RootConstrainSelectedInstOperands,
14258	/ 37160 / // GIR_Coverage, 1365,
14259	/ 37160 / GIR_EraseRootFromParent_Done,
14260	/ 37161 / // Label 1094: @37161
14261	/ 37161 / GIM_Try_CheckFeatures, /On fail goto//Label 1095/ GIMT_Encode4(`37212`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1366 //
14262	/ 37168 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14263	/ 37173 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14264	/ 37176 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
14265	/ 37179 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14266	/ 37182 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14267	/ 37186 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14268	/ 37190 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14269	/* 37194 / // (intrinsic_w_chain:{ :[i32] } 8495:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MULQ_RS_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
14270	/ 37194 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
14271	/ 37197 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14272	/ 37199 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14273	/ 37201 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14274	/ 37203 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
14275	/ 37206 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14276	/ 37210 / GIR_RootConstrainSelectedInstOperands,
14277	/ 37211 / // GIR_Coverage, 1366,
14278	/ 37211 / GIR_EraseRootFromParent_Done,
14279	/ 37212 / // Label 1095: @37212
14280	/ 37212 / GIM_Try_CheckFeatures, /On fail goto//Label 1096/ GIMT_Encode4(`37263`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1367 //
14281	/ 37219 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14282	/ 37224 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14283	/ 37227 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14284	/ 37230 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14285	/ 37233 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14286	/ 37237 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14287	/ 37241 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14288	/* 37245 / // (intrinsic_w_chain:{ :[v2i16] } 8496:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ :[v2i16] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14289	/ 37245 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
14290	/ 37248 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14291	/ 37250 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14292	/ 37252 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14293	/ 37254 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
14294	/ 37257 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14295	/ 37261 / GIR_RootConstrainSelectedInstOperands,
14296	/ 37262 / // GIR_Coverage, 1367,
14297	/ 37262 / GIR_EraseRootFromParent_Done,
14298	/ 37263 / // Label 1096: @37263
14299	/ 37263 / GIM_Try_CheckFeatures, /On fail goto//Label 1097/ GIMT_Encode4(`37314`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1368 //
14300	/ 37270 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14301	/ 37275 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14302	/ 37278 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
14303	/ 37281 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14304	/ 37284 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14305	/ 37288 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14306	/ 37292 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14307	/* 37296 / // (intrinsic_w_chain:{ :[i32] } 8497:{ :[iPTR] }, GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MULQ_S_W_MMR2:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
14308	/ 37296 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
14309	/ 37299 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14310	/ 37301 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14311	/ 37303 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14312	/ 37305 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
14313	/ 37308 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14314	/ 37312 / GIR_RootConstrainSelectedInstOperands,
14315	/ 37313 / // GIR_Coverage, 1368,
14316	/ 37313 / GIR_EraseRootFromParent_Done,
14317	/ 37314 / // Label 1097: @37314
14318	/ 37314 / GIM_Try_CheckFeatures, /On fail goto//Label 1098/ GIMT_Encode4(`37362`), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1369 //
14319	/ 37321 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14320	/ 37326 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s8,
14321	/ 37329 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14322	/ 37332 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14323	/ 37335 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14324	/ 37339 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14325	/ 37343 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14326	/* 37347 / // (intrinsic_w_chain:{ :[v4i8] } 8545:{ :[iPTR] }, DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ :[v4i8] } DSPROpnd:{ :[v2i16] }:$rs, DSPROpnd:{ :[v2i16] }:$rt)
14327	/ 37347 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
14328	/ 37350 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14329	/ 37352 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
14330	/ 37354 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
14331	/ 37356 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14332	/ 37360 / GIR_RootConstrainSelectedInstOperands,
14333	/ 37361 / // GIR_Coverage, 1369,
14334	/ 37361 / GIR_EraseRootFromParent_Done,
14335	/ 37362 / // Label 1098: @37362
14336	/ 37362 / GIM_Try_CheckFeatures, /On fail goto//Label 1099/ GIMT_Encode4(`37405`), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2056 //
14337	/ 37369 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_mul_ph),
14338	/ 37374 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s16,
14339	/ 37377 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s16,
14340	/ 37380 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s16,
14341	/ 37383 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::DSPRRegClassID),
14342	/ 37387 / // (intrinsic_w_chain:{ :[v2i16] } 8486:{ :[iPTR] }, v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b) => (MUL_PH:{ :[v2i16] } v2i16:{ :[v2i16] }:$a, v2i16:{ :[v2i16] }:$b)*
14343	/ 37387 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MUL_PH),
14344	/ 37390 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14345	/ 37392 / GIR_RootToRootCopy, /OpIdx/`2`, // a
14346	/ 37394 / GIR_RootToRootCopy, /OpIdx/`3`, // b
14347	/ 37396 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag21/`0`,
14348	/ 37399 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14349	/ 37403 / GIR_RootConstrainSelectedInstOperands,
14350	/ 37404 / // GIR_Coverage, 2056,
14351	/ 37404 / GIR_EraseRootFromParent_Done,
14352	/ 37405 / // Label 1099: @37405
14353	/ 37405 / GIM_Try_CheckFeatures, /On fail goto//Label 1100/ GIMT_Encode4(`37448`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2062 //
14354	/ 37412 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addsc),
14355	/ 37417 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14356	/ 37420 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
14357	/ 37423 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14358	/ 37426 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14359	/ 37430 / // (intrinsic_w_chain:{ :[i32] } 8041:{ :[iPTR] }, i32:{ :[i32] }:$a, i32:{ :[i32] }:$b) => (ADDSC:{ :[i32] } i32:{ :[i32] }:$a, i32:{ :[i32] }:$b)*
14360	/ 37430 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDSC),
14361	/ 37433 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14362	/ 37435 / GIR_RootToRootCopy, /OpIdx/`2`, // a
14363	/ 37437 / GIR_RootToRootCopy, /OpIdx/`3`, // b
14364	/ 37439 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPCarry/`0`,
14365	/ 37442 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14366	/ 37446 / GIR_RootConstrainSelectedInstOperands,
14367	/ 37447 / // GIR_Coverage, 2062,
14368	/ 37447 / GIR_EraseRootFromParent_Done,
14369	/ 37448 / // Label 1100: @37448
14370	/ 37448 / GIM_Try_CheckFeatures, /On fail goto//Label 1101/ GIMT_Encode4(`37491`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2064 //
14371	/ 37455 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_addwc),
14372	/ 37460 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14373	/ 37463 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
14374	/ 37466 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14375	/ 37469 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14376	/ 37473 / // (intrinsic_w_chain:{ :[i32] } 8056:{ :[iPTR] }, i32:{ :[i32] }:$a, i32:{ :[i32] }:$b) => (ADDWC:{ :[i32] } i32:{ :[i32] }:$a, i32:{ :[i32] }:$b)*
14377	/ 37473 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ADDWC),
14378	/ 37476 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14379	/ 37478 / GIR_RootToRootCopy, /OpIdx/`2`, // a
14380	/ 37480 / GIR_RootToRootCopy, /OpIdx/`3`, // b
14381	/ 37482 / GIR_SetImplicitDefDead, /InsnID/`0`, /OpIdx for Mips::DSPOutFlag20/`0`,
14382	/ 37485 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14383	/ 37489 / GIR_RootConstrainSelectedInstOperands,
14384	/ 37490 / // GIR_Coverage, 2064,
14385	/ 37490 / GIR_EraseRootFromParent_Done,
14386	/ 37491 / // Label 1101: @37491
14387	/ 37491 / GIM_Try_CheckFeatures, /On fail goto//Label 1102/ GIMT_Encode4(`37536`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 514 //
14388	/ 37498 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ldr_d),
14389	/ 37503 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v2s64,
14390	/ 37506 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14391	/ 37509 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
14392	/ 37513 / // MIs[0] ptr
14393	/ 37513 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14394	/ 37517 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14395	/ 37521 / // (intrinsic_w_chain:{ :[v2i64] } 8406:{ :[iPTR] }, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm) => (LDR_D:{ :[v2i64] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm)*
14396	/ 37521 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LDR_D),
14397	/ 37524 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14398	/ 37526 / GIR_RootToRootCopy, /OpIdx/`2`, // ptr
14399	/ 37528 / GIR_RootToRootCopy, /OpIdx/`3`, // imm
14400	/ 37530 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14401	/ 37534 / GIR_RootConstrainSelectedInstOperands,
14402	/ 37535 / // GIR_Coverage, 514,
14403	/ 37535 / GIR_EraseRootFromParent_Done,
14404	/ 37536 / // Label 1102: @37536
14405	/ 37536 / GIM_Try_CheckFeatures, /On fail goto//Label 1103/ GIMT_Encode4(`37581`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 515 //
14406	/ 37543 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_ldr_w),
14407	/ 37548 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_v4s32,
14408	/ 37551 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14409	/ 37554 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
14410	/ 37558 / // MIs[0] ptr
14411	/ 37558 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14412	/ 37562 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14413	/ 37566 / // (intrinsic_w_chain:{ :[v4i32] } 8407:{ :[iPTR] }, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm) => (LDR_W:{ :[v4i32] } iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm)*
14414	/ 37566 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LDR_W),
14415	/ 37569 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14416	/ 37571 / GIR_RootToRootCopy, /OpIdx/`2`, // ptr
14417	/ 37573 / GIR_RootToRootCopy, /OpIdx/`3`, // imm
14418	/ 37575 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14419	/ 37579 / GIR_RootConstrainSelectedInstOperands,
14420	/ 37580 / // GIR_Coverage, 515,
14421	/ 37580 / GIR_EraseRootFromParent_Done,
14422	/ 37581 / // Label 1103: @37581
14423	/ 37581 / GIM_Try_CheckFeatures, /On fail goto//Label 1104/ GIMT_Encode4(`37622`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 461 //
14424	/ 37588 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_lwx),
14425	/ 37593 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14426	/ 37596 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14427	/ 37599 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14428	/ 37603 / // MIs[0] base
14429	/ 37603 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14430	/ 37607 / // (intrinsic_w_chain:{ :[i32] } 8410:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LWX:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14431	/ 37607 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LWX),
14432	/ 37610 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14433	/ 37612 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14434	/ 37614 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14435	/ 37616 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14436	/ 37620 / GIR_RootConstrainSelectedInstOperands,
14437	/ 37621 / // GIR_Coverage, 461,
14438	/ 37621 / GIR_EraseRootFromParent_Done,
14439	/ 37622 / // Label 1104: @37622
14440	/ 37622 / GIM_Try_CheckFeatures, /On fail goto//Label 1105/ GIMT_Encode4(`37663`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 462 //
14441	/ 37629 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_lhx),
14442	/ 37634 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14443	/ 37637 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14444	/ 37640 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14445	/ 37644 / // MIs[0] base
14446	/ 37644 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14447	/ 37648 / // (intrinsic_w_chain:{ :[i32] } 8408:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LHX:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14448	/ 37648 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LHX),
14449	/ 37651 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14450	/ 37653 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14451	/ 37655 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14452	/ 37657 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14453	/ 37661 / GIR_RootConstrainSelectedInstOperands,
14454	/ 37662 / // GIR_Coverage, 462,
14455	/ 37662 / GIR_EraseRootFromParent_Done,
14456	/ 37663 / // Label 1105: @37663
14457	/ 37663 / GIM_Try, /On fail goto//Label 1106/ GIMT_Encode4(`37732`),
14458	/ 37668 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_lbux),
14459	/ 37673 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14460	/ 37676 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14461	/ 37679 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14462	/ 37683 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14463	/ 37687 / GIM_Try_CheckFeatures, /On fail goto//Label 1107/ GIMT_Encode4(`37709`), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 463 //
14464	/ 37694 / // (intrinsic_w_chain:{ :[i32] } 8397:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LBUX:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14465	/ 37694 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LBUX),
14466	/ 37697 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14467	/ 37699 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14468	/ 37701 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14469	/ 37703 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14470	/ 37707 / GIR_RootConstrainSelectedInstOperands,
14471	/ 37708 / // GIR_Coverage, 463,
14472	/ 37708 / GIR_EraseRootFromParent_Done,
14473	/ 37709 / // Label 1107: @37709
14474	/ 37709 / GIM_Try_CheckFeatures, /On fail goto//Label 1108/ GIMT_Encode4(`37731`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1298 //
14475	/ 37716 / // (intrinsic_w_chain:{ :[i32] } 8397:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LBUX_MM:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14476	/ 37716 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LBUX_MM),
14477	/ 37719 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14478	/ 37721 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14479	/ 37723 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14480	/ 37725 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14481	/ 37729 / GIR_RootConstrainSelectedInstOperands,
14482	/ 37730 / // GIR_Coverage, 1298,
14483	/ 37730 / GIR_EraseRootFromParent_Done,
14484	/ 37731 / // Label 1108: @37731
14485	/ 37731 / GIM_Reject,
14486	/ 37732 / // Label 1106: @37732
14487	/ 37732 / GIM_Try_CheckFeatures, /On fail goto//Label 1109/ GIMT_Encode4(`37773`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1299 //
14488	/ 37739 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_lhx),
14489	/ 37744 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14490	/ 37747 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14491	/ 37750 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14492	/ 37754 / // MIs[0] base
14493	/ 37754 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14494	/ 37758 / // (intrinsic_w_chain:{ :[i32] } 8408:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LHX_MM:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14495	/ 37758 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LHX_MM),
14496	/ 37761 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14497	/ 37763 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14498	/ 37765 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14499	/ 37767 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14500	/ 37771 / GIR_RootConstrainSelectedInstOperands,
14501	/ 37772 / // GIR_Coverage, 1299,
14502	/ 37772 / GIR_EraseRootFromParent_Done,
14503	/ 37773 / // Label 1109: @37773
14504	/ 37773 / GIM_Try_CheckFeatures, /On fail goto//Label 1110/ GIMT_Encode4(`37814`), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1300 //
14505	/ 37780 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`1`, GIMT_Encode2(Intrinsic::mips_lwx),
14506	/ 37785 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14507	/ 37788 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14508	/ 37791 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14509	/ 37795 / // MIs[0] base
14510	/ 37795 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14511	/ 37799 / // (intrinsic_w_chain:{ :[i32] } 8410:{ :[iPTR] }, iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index) => (LWX_MM:{ :[i32] } iPTR:{ :[iPTR] }:$base, iPTR:{ :[i32] }:$index)*
14512	/ 37799 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LWX_MM),
14513	/ 37802 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14514	/ 37804 / GIR_RootToRootCopy, /OpIdx/`2`, // base
14515	/ 37806 / GIR_RootToRootCopy, /OpIdx/`3`, // index
14516	/ 37808 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14517	/ 37812 / GIR_RootConstrainSelectedInstOperands,
14518	/ 37813 / // GIR_Coverage, 1300,
14519	/ 37813 / GIR_EraseRootFromParent_Done,
14520	/ 37814 / // Label 1110: @37814
14521	/ 37814 / GIM_Try_CheckFeatures, /On fail goto//Label 1111/ GIMT_Encode4(`37859`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 516 //
14522	/ 37821 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_str_d),
14523	/ 37826 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
14524	/ 37829 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14525	/ 37832 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
14526	/ 37836 / // MIs[0] ptr
14527	/ 37836 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14528	/ 37840 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14529	/* 37844 / // (intrinsic_void 8640:{ :[iPTR] }, MSA128DOpnd:{ :[v2i64] }:$dst, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm) => (STR_D MSA128DOpnd:{ :[v2i64] }:$dst, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm)
14530	/ 37844 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::STR_D),
14531	/ 37847 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
14532	/ 37849 / GIR_RootToRootCopy, /OpIdx/`2`, // ptr
14533	/ 37851 / GIR_RootToRootCopy, /OpIdx/`3`, // imm
14534	/ 37853 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14535	/ 37857 / GIR_RootConstrainSelectedInstOperands,
14536	/ 37858 / // GIR_Coverage, 516,
14537	/ 37858 / GIR_EraseRootFromParent_Done,
14538	/ 37859 / // Label 1111: @37859
14539	/ 37859 / GIM_Try_CheckFeatures, /On fail goto//Label 1112/ GIMT_Encode4(`37904`), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 517 //
14540	/ 37866 / GIM_CheckIntrinsicID, /MI/`0`, /Op/`0`, GIMT_Encode2(Intrinsic::mips_str_w),
14541	/ 37871 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
14542	/ 37874 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
14543	/ 37877 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
14544	/ 37881 / // MIs[0] ptr
14545	/ 37881 / GIM_CheckPointerToAny, /MI/`0`, /Op/`2`, /SizeInBits/`0`,
14546	/ 37885 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14547	/* 37889 / // (intrinsic_void 8641:{ :[iPTR] }, MSA128WOpnd:{ :[v4i32] }:$dst, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm) => (STR_W MSA128WOpnd:{ :[v4i32] }:$dst, iPTR:{ :[iPTR] }:$ptr, GPR32:{ :[i32] }:$imm)
14548	/ 37889 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::STR_W),
14549	/ 37892 / GIR_RootToRootCopy, /OpIdx/`1`, // dst
14550	/ 37894 / GIR_RootToRootCopy, /OpIdx/`2`, // ptr
14551	/ 37896 / GIR_RootToRootCopy, /OpIdx/`3`, // imm
14552	/ 37898 / GIR_MergeMemOperands, /InsnID/`0`, /NumInsns/`1`, /MergeInsnID's/`0`,
14553	/ 37902 / GIR_RootConstrainSelectedInstOperands,
14554	/ 37903 / // GIR_Coverage, 517,
14555	/ 37903 / GIR_EraseRootFromParent_Done,
14556	/ 37904 / // Label 1112: @37904
14557	/ 37904 / GIM_Reject,
14558	/ 37905 / // Label 1030: @37905
14559	/ 37905 / GIM_Reject,
14560	/ 37906 / // Label 31: @37906
14561	/ 37906 / GIM_Try_CheckFeatures, /On fail goto//Label 1113/ GIMT_Encode4(`37970`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1685 //
14562	/ 37913 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s64,
14563	/ 37916 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
14564	/ 37919 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
14565	/ 37923 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14566	/ 37927 / // (anyext:{ :[i64] } GPR32:{ :[i32] }:$src) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), GPR32:{ :[i32] }:$src, sub_32:{ :[i32] })
14567	/ 37927 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14568	/ 37930 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14569	/ 37934 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14570	/ 37939 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14571	/ 37941 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14572	/ 37944 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14573	/ 37946 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14574	/ 37949 / GIR_RootToRootCopy, /OpIdx/`1`, // src
14575	/ 37951 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14576	/ 37954 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14577	/ 37959 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14578	/ 37964 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14579	/ 37969 / // GIR_Coverage, 1685,
14580	/ 37969 / GIR_EraseRootFromParent_Done,
14581	/ 37970 / // Label 1113: @37970
14582	/ 37970 / GIM_Reject,
14583	/ 37971 / // Label 32: @37971
14584	/ 37971 / GIM_Try_CheckFeatures, /On fail goto//Label 1114/ GIMT_Encode4(`38033`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1678 //
14585	/ 37978 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14586	/ 37981 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
14587	/ 37984 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14588	/ 37988 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
14589	/ 37992 / // (trunc:{ :[i32] } GPR64:{ :[i64] }:$src) => (SLL:{ :[i32] } (EXTRACT_SUBREG:{ :[i32] } GPR64:{ :[i64] }:$src, sub_32:{ :[i32] }), 0:{ :[i32] })*
14590	/ 37992 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
14591	/ 37995 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
14592	/ 37999 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14593	/ 38004 / GIR_CopySubReg, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, /SubRegIdx/GIMT_Encode2(`1`), // src
14594	/ 38010 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
14595	/ 38015 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14596	/ 38020 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL),
14597	/ 38023 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14598	/ 38025 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14599	/ 38028 / GIR_AddImm8, /InsnID/`0`, /Imm/`0`,
14600	/ 38031 / GIR_RootConstrainSelectedInstOperands,
14601	/ 38032 / // GIR_Coverage, 1678,
14602	/ 38032 / GIR_EraseRootFromParent_Done,
14603	/ 38033 / // Label 1114: @38033
14604	/ 38033 / GIM_Reject,
14605	/ 38034 / // Label 33: @38034
14606	/ 38034 / GIM_Try, /On fail goto//Label 1115/ GIMT_Encode4(`38092`),
14607	/ 38039 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
14608	/ 38042 / GIM_Try_CheckFeatures, /On fail goto//Label 1116/ GIMT_Encode4(`38067`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2287 //
14609	/ 38049 / GIM_CheckI64ImmPredicate, /MI/`0`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
14610	/ 38053 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
14611	/ 38057 / // MIs[0] Operand 1
14612	/ 38057 / // No operand predicates
14613	/ 38057 / // (imm:{ :[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ :[i32] } (imm:{ :[i32] })<<P:Predicate_immLi16>>:$imm)*
14614	/ 38057 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LI16_MM),
14615	/ 38060 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
14616	/ 38062 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`0`, // imm
14617	/ 38065 / GIR_RootConstrainSelectedInstOperands,
14618	/ 38066 / // GIR_Coverage, 2287,
14619	/ 38066 / GIR_EraseRootFromParent_Done,
14620	/ 38067 / // Label 1116: @38067
14621	/ 38067 / GIM_Try_CheckFeatures, /On fail goto//Label 1117/ GIMT_Encode4(`38091`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1980 //
14622	/ 38074 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14623	/ 38078 / // MIs[0] Operand 1
14624	/ 38078 / // No operand predicates
14625	/ 38078 / // (imm:{ :[i32] }):$imm => (LwConstant32:{ :[i32] } (imm:{ :[i32] }):$imm, -1:{ :[i32] })
14626	/ 38078 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::LwConstant32),
14627	/ 38081 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
14628	/ 38083 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`0`, // imm
14629	/ 38086 / GIR_AddImm8, /InsnID/`0`, /Imm/`255`,
14630	/ 38089 / GIR_RootConstrainSelectedInstOperands,
14631	/ 38090 / // GIR_Coverage, 1980,
14632	/ 38090 / GIR_EraseRootFromParent_Done,
14633	/ 38091 / // Label 1117: @38091
14634	/ 38091 / GIM_Reject,
14635	/ 38092 / // Label 1115: @38092
14636	/ 38092 / GIM_Reject,
14637	/ 38093 / // Label 34: @38093
14638	/ 38093 / GIM_Try, /On fail goto//Label 1118/ GIMT_Encode4(`39549`),
14639	/ 38098 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s64,
14640	/ 38101 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
14641	/ 38104 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
14642	/ 38108 / GIM_Try, /On fail goto//Label 1119/ GIMT_Encode4(`38213`), // Rule ID 1734 //
14643	/ 38113 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14644	/ 38117 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ASHR),
14645	/ 38121 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14646	/ 38125 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14647	/ 38129 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14648	/ 38134 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
14649	/ 38138 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14650	/ 38142 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14651	/ 38146 / // MIs[2] Operand 1
14652	/ 38146 / // No operand predicates
14653	/ 38146 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
14654	/* 38148 / // (sext:{ :[i64] } (sra:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SRA:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14655	/ 38148 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14656	/ 38151 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SRA),
14657	/ 38155 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14658	/ 38160 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14659	/ 38164 / GIR_CopyConstantAsSImm, /NewInsnID/`2`, /OldInsnID/`2`, // imm5
14660	/ 38167 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14661	/ 38169 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14662	/ 38172 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14663	/ 38176 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14664	/ 38181 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14665	/ 38183 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14666	/ 38186 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14667	/ 38188 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14668	/ 38191 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14669	/ 38194 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14670	/ 38197 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14671	/ 38202 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14672	/ 38207 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14673	/ 38212 / // GIR_Coverage, 1734,
14674	/ 38212 / GIR_EraseRootFromParent_Done,
14675	/ 38213 / // Label 1119: @38213
14676	/ 38213 / GIM_Try, /On fail goto//Label 1120/ GIMT_Encode4(`38318`), // Rule ID 1730 //
14677	/ 38218 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14678	/ 38222 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_LSHR),
14679	/ 38226 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14680	/ 38230 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14681	/ 38234 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14682	/ 38239 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
14683	/ 38243 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14684	/ 38247 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14685	/ 38251 / // MIs[2] Operand 1
14686	/ 38251 / // No operand predicates
14687	/ 38251 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
14688	/* 38253 / // (sext:{ :[i64] } (srl:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SRL:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14689	/ 38253 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14690	/ 38256 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SRL),
14691	/ 38260 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14692	/ 38265 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14693	/ 38269 / GIR_CopyConstantAsSImm, /NewInsnID/`2`, /OldInsnID/`2`, // imm5
14694	/ 38272 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14695	/ 38274 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14696	/ 38277 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14697	/ 38281 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14698	/ 38286 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14699	/ 38288 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14700	/ 38291 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14701	/ 38293 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14702	/ 38296 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14703	/ 38299 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14704	/ 38302 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14705	/ 38307 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14706	/ 38312 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14707	/ 38317 / // GIR_Coverage, 1730,
14708	/ 38317 / GIR_EraseRootFromParent_Done,
14709	/ 38318 / // Label 1120: @38318
14710	/ 38318 / GIM_Try, /On fail goto//Label 1121/ GIMT_Encode4(`38423`), // Rule ID 1726 //
14711	/ 38323 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14712	/ 38327 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
14713	/ 38331 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14714	/ 38335 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14715	/ 38339 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14716	/ 38344 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
14717	/ 38348 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14718	/ 38352 / GIM_CheckI64ImmPredicate, /MI/`2`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14719	/ 38356 / // MIs[2] Operand 1
14720	/ 38356 / // No operand predicates
14721	/ 38356 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
14722	/* 38358 / // (sext:{ :[i64] } (shl:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SLL:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14723	/ 38358 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14724	/ 38361 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SLL),
14725	/ 38365 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14726	/ 38370 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14727	/ 38374 / GIR_CopyConstantAsSImm, /NewInsnID/`2`, /OldInsnID/`2`, // imm5
14728	/ 38377 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14729	/ 38379 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14730	/ 38382 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14731	/ 38386 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14732	/ 38391 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14733	/ 38393 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14734	/ 38396 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14735	/ 38398 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14736	/ 38401 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14737	/ 38404 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14738	/ 38407 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14739	/ 38412 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14740	/ 38417 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14741	/ 38422 / // GIR_Coverage, 1726,
14742	/ 38422 / GIR_EraseRootFromParent_Done,
14743	/ 38423 / // Label 1121: @38423
14744	/ 38423 / GIM_Try, /On fail goto//Label 1122/ GIMT_Encode4(`38522`), // Rule ID 1716 //
14745	/ 38428 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14746	/ 38432 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ADD),
14747	/ 38436 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14748	/ 38440 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14749	/ 38444 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14750	/ 38449 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14751	/ 38454 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14752	/* 38456 / // (sext:{ :[i64] } (add:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (ADDu:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14753	/ 38456 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14754	/ 38459 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::ADDu),
14755	/ 38463 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14756	/ 38468 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14757	/ 38472 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14758	/ 38476 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14759	/ 38478 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14760	/ 38481 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14761	/ 38485 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14762	/ 38490 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14763	/ 38492 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14764	/ 38495 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14765	/ 38497 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14766	/ 38500 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14767	/ 38503 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14768	/ 38506 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14769	/ 38511 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14770	/ 38516 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14771	/ 38521 / // GIR_Coverage, 1716,
14772	/ 38521 / GIR_EraseRootFromParent_Done,
14773	/ 38522 / // Label 1122: @38522
14774	/ 38522 / GIM_Try, /On fail goto//Label 1123/ GIMT_Encode4(`38621`), // Rule ID 1736 //
14775	/ 38527 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14776	/ 38531 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ASHR),
14777	/ 38535 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14778	/ 38539 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14779	/ 38543 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14780	/ 38548 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14781	/ 38553 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14782	/* 38555 / // (sext:{ :[i64] } (sra:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SRAV:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14783	/ 38555 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14784	/ 38558 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SRAV),
14785	/ 38562 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14786	/ 38567 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14787	/ 38571 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14788	/ 38575 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14789	/ 38577 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14790	/ 38580 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14791	/ 38584 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14792	/ 38589 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14793	/ 38591 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14794	/ 38594 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14795	/ 38596 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14796	/ 38599 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14797	/ 38602 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14798	/ 38605 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14799	/ 38610 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14800	/ 38615 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14801	/ 38620 / // GIR_Coverage, 1736,
14802	/ 38620 / GIR_EraseRootFromParent_Done,
14803	/ 38621 / // Label 1123: @38621
14804	/ 38621 / GIM_Try, /On fail goto//Label 1124/ GIMT_Encode4(`38720`), // Rule ID 1732 //
14805	/ 38626 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14806	/ 38630 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_LSHR),
14807	/ 38634 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14808	/ 38638 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14809	/ 38642 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14810	/ 38647 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14811	/ 38652 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14812	/* 38654 / // (sext:{ :[i64] } (srl:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SRLV:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14813	/ 38654 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14814	/ 38657 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SRLV),
14815	/ 38661 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14816	/ 38666 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14817	/ 38670 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14818	/ 38674 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14819	/ 38676 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14820	/ 38679 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14821	/ 38683 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14822	/ 38688 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14823	/ 38690 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14824	/ 38693 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14825	/ 38695 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14826	/ 38698 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14827	/ 38701 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14828	/ 38704 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14829	/ 38709 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14830	/ 38714 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14831	/ 38719 / // GIR_Coverage, 1732,
14832	/ 38719 / GIR_EraseRootFromParent_Done,
14833	/ 38720 / // Label 1124: @38720
14834	/ 38720 / GIM_Try_CheckFeatures, /On fail goto//Label 1125/ GIMT_Encode4(`38827`), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 1720 //
14835	/ 38727 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14836	/ 38731 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
14837	/ 38735 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14838	/ 38739 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14839	/ 38743 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14840	/ 38748 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14841	/ 38753 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14842	/* 38755 / // (sext:{ :[i64] } (mul:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (MUL:{ :[i32] }:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ :[i32] })
14843	/ 38755 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14844	/ 38758 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::MUL),
14845	/ 38762 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14846	/ 38767 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14847	/ 38771 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14848	/ 38775 / GIR_SetImplicitDefDead, /InsnID/`2`, /OpIdx for Mips::HI0/`0`,
14849	/ 38778 / GIR_SetImplicitDefDead, /InsnID/`2`, /OpIdx for Mips::LO0/`1`,
14850	/ 38781 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14851	/ 38783 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14852	/ 38786 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14853	/ 38790 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14854	/ 38795 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14855	/ 38797 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14856	/ 38800 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14857	/ 38802 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14858	/ 38805 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14859	/ 38808 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14860	/ 38811 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14861	/ 38816 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14862	/ 38821 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14863	/ 38826 / // GIR_Coverage, 1720,
14864	/ 38826 / GIR_EraseRootFromParent_Done,
14865	/ 38827 / // Label 1125: @38827
14866	/ 38827 / GIM_Try_CheckFeatures, /On fail goto//Label 1126/ GIMT_Encode4(`38928`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1931 //
14867	/ 38834 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14868	/ 38838 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_MUL),
14869	/ 38842 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14870	/ 38846 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14871	/ 38850 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14872	/ 38855 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14873	/ 38860 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14874	/* 38862 / // (sext:{ :[i64] } (mul:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (MUL_R6:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14875	/ 38862 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14876	/ 38865 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::MUL_R6),
14877	/ 38869 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14878	/ 38874 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14879	/ 38878 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14880	/ 38882 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14881	/ 38884 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14882	/ 38887 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14883	/ 38891 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14884	/ 38896 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14885	/ 38898 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14886	/ 38901 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14887	/ 38903 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14888	/ 38906 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14889	/ 38909 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14890	/ 38912 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14891	/ 38917 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14892	/ 38922 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14893	/ 38927 / // GIR_Coverage, 1931,
14894	/ 38927 / GIR_EraseRootFromParent_Done,
14895	/ 38928 / // Label 1126: @38928
14896	/ 38928 / GIM_Try_CheckFeatures, /On fail goto//Label 1127/ GIMT_Encode4(`39029`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1932 //
14897	/ 38935 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14898	/ 38939 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SDIV),
14899	/ 38943 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14900	/ 38947 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14901	/ 38951 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14902	/ 38956 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14903	/ 38961 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14904	/* 38963 / // (sext:{ :[i64] } (sdiv:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (DIV:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14905	/ 38963 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14906	/ 38966 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::DIV),
14907	/ 38970 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14908	/ 38975 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14909	/ 38979 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14910	/ 38983 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14911	/ 38985 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14912	/ 38988 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14913	/ 38992 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14914	/ 38997 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14915	/ 38999 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14916	/ 39002 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14917	/ 39004 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14918	/ 39007 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14919	/ 39010 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14920	/ 39013 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14921	/ 39018 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14922	/ 39023 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14923	/ 39028 / // GIR_Coverage, 1932,
14924	/ 39028 / GIR_EraseRootFromParent_Done,
14925	/ 39029 / // Label 1127: @39029
14926	/ 39029 / GIM_Try, /On fail goto//Label 1128/ GIMT_Encode4(`39128`), // Rule ID 1728 //
14927	/ 39034 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14928	/ 39038 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SHL),
14929	/ 39042 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14930	/ 39046 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14931	/ 39050 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14932	/ 39055 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14933	/ 39060 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14934	/* 39062 / // (sext:{ :[i64] } (shl:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SLLV:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14935	/ 39062 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14936	/ 39065 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SLLV),
14937	/ 39069 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14938	/ 39074 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14939	/ 39078 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14940	/ 39082 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14941	/ 39084 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14942	/ 39087 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14943	/ 39091 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14944	/ 39096 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14945	/ 39098 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14946	/ 39101 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14947	/ 39103 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14948	/ 39106 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14949	/ 39109 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14950	/ 39112 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14951	/ 39117 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14952	/ 39122 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14953	/ 39127 / // GIR_Coverage, 1728,
14954	/ 39127 / GIR_EraseRootFromParent_Done,
14955	/ 39128 / // Label 1128: @39128
14956	/ 39128 / GIM_Try_CheckFeatures, /On fail goto//Label 1129/ GIMT_Encode4(`39229`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1934 //
14957	/ 39135 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14958	/ 39139 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SREM),
14959	/ 39143 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14960	/ 39147 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14961	/ 39151 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14962	/ 39156 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14963	/ 39161 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14964	/* 39163 / // (sext:{ :[i64] } (srem:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (MOD:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14965	/ 39163 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14966	/ 39166 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::MOD),
14967	/ 39170 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14968	/ 39175 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14969	/ 39179 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
14970	/ 39183 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
14971	/ 39185 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
14972	/ 39188 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14973	/ 39192 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14974	/ 39197 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
14975	/ 39199 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14976	/ 39202 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
14977	/ 39204 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
14978	/ 39207 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
14979	/ 39210 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
14980	/ 39213 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
14981	/ 39218 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
14982	/ 39223 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
14983	/ 39228 / // GIR_Coverage, 1934,
14984	/ 39228 / GIR_EraseRootFromParent_Done,
14985	/ 39229 / // Label 1129: @39229
14986	/ 39229 / GIM_Try, /On fail goto//Label 1130/ GIMT_Encode4(`39328`), // Rule ID 1718 //
14987	/ 39234 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
14988	/ 39238 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_SUB),
14989	/ 39242 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
14990	/ 39246 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
14991	/ 39250 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14992	/ 39255 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
14993	/ 39260 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
14994	/* 39262 / // (sext:{ :[i64] } (sub:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (SUBu:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
14995	/ 39262 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
14996	/ 39265 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SUBu),
14997	/ 39269 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14998	/ 39274 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
14999	/ 39278 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
15000	/ 39282 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
15001	/ 39284 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
15002	/ 39287 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15003	/ 39291 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15004	/ 39296 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
15005	/ 39298 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15006	/ 39301 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
15007	/ 39303 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
15008	/ 39306 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
15009	/ 39309 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
15010	/ 39312 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
15011	/ 39317 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
15012	/ 39322 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
15013	/ 39327 / // GIR_Coverage, 1718,
15014	/ 39327 / GIR_EraseRootFromParent_Done,
15015	/ 39328 / // Label 1130: @39328
15016	/ 39328 / GIM_Try_CheckFeatures, /On fail goto//Label 1131/ GIMT_Encode4(`39429`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1933 //
15017	/ 39335 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
15018	/ 39339 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_UDIV),
15019	/ 39343 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
15020	/ 39347 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
15021	/ 39351 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15022	/ 39356 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15023	/ 39361 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15024	/* 39363 / // (sext:{ :[i64] } (udiv:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (DIVU:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
15025	/ 39363 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
15026	/ 39366 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::DIVU),
15027	/ 39370 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15028	/ 39375 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
15029	/ 39379 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
15030	/ 39383 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
15031	/ 39385 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
15032	/ 39388 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15033	/ 39392 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15034	/ 39397 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
15035	/ 39399 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15036	/ 39402 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
15037	/ 39404 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
15038	/ 39407 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
15039	/ 39410 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
15040	/ 39413 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
15041	/ 39418 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
15042	/ 39423 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
15043	/ 39428 / // GIR_Coverage, 1933,
15044	/ 39428 / GIR_EraseRootFromParent_Done,
15045	/ 39429 / // Label 1131: @39429
15046	/ 39429 / GIM_Try_CheckFeatures, /On fail goto//Label 1132/ GIMT_Encode4(`39530`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1935 //
15047	/ 39436 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
15048	/ 39440 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_UREM),
15049	/ 39444 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
15050	/ 39448 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
15051	/ 39452 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15052	/ 39457 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15053	/ 39462 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15054	/* 39464 / // (sext:{ :[i64] } (urem:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2)) => (INSERT_SUBREG:{ :[i64] } (IMPLICIT_DEF:{ :[i64] }), (MODU:{ :[i32] } GPR32:{ :[i32] }:$src, GPR32:{ :[i32] }:$src2), sub_32:{ *:[i32] })
15055	/ 39464 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
15056	/ 39467 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::MODU),
15057	/ 39471 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15058	/ 39476 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`1`, // src
15059	/ 39480 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`1`, /OpIdx/`2`, // src2
15060	/ 39484 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
15061	/ 39486 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
15062	/ 39489 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15063	/ 39493 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15064	/ 39498 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
15065	/ 39500 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15066	/ 39503 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
15067	/ 39505 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
15068	/ 39508 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
15069	/ 39511 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
15070	/ 39514 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::GPR64RegClassID),
15071	/ 39519 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
15072	/ 39524 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`2`, GIMT_Encode2(Mips::GPR32RegClassID),
15073	/ 39529 / // GIR_Coverage, 1935,
15074	/ 39529 / GIR_EraseRootFromParent_Done,
15075	/ 39530 / // Label 1132: @39530
15076	/ 39530 / GIM_Try_CheckFeatures, /On fail goto//Label 1133/ GIMT_Encode4(`39548`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1688 //
15077	/ 39537 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15078	/ 39541 / // (sext:{ :[i64] } GPR32:{ :[i32] }:$src) => (SLL64_32:{ :[i64] } GPR32:{ :[i32] }:$src)
15079	/ 39541 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLL64_32),
15080	/ 39546 / GIR_RootConstrainSelectedInstOperands,
15081	/ 39547 / // GIR_Coverage, 1688,
15082	/ 39547 / GIR_Done,
15083	/ 39548 / // Label 1133: @39548
15084	/ 39548 / GIM_Reject,
15085	/ 39549 / // Label 1118: @39549
15086	/ 39549 / GIM_Reject,
15087	/ 39550 / // Label 35: @39550
15088	/ 39550 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1136/ GIMT_Encode4(`39868`),
15089	/ 39561 / /GILLT_s32//Label 1134/ GIMT_Encode4(`39569`),
15090	/ 39565 / /GILLT_s64//Label 1135/ GIMT_Encode4(`39769`),
15091	/ 39569 / // Label 1134: @39569
15092	/ 39569 / GIM_Try, /On fail goto//Label 1137/ GIMT_Encode4(`39768`),
15093	/ 39574 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
15094	/ 39577 / GIM_Try, /On fail goto//Label 1138/ GIMT_Encode4(`39699`),
15095	/ 39582 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15096	/ 39586 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15097	/ 39590 / GIM_Try_CheckFeatures, /On fail goto//Label 1139/ GIMT_Encode4(`39617`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 106 //
15098	/ 39597 / // MIs[0] Operand 2
15099	/ 39597 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`8`),
15100	/ 39608 / // (sext_inreg:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, i8:{ :[Other] }) => (SEB:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
15101	/ 39608 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEB),
15102	/ 39611 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15103	/ 39613 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15104	/ 39615 / GIR_RootConstrainSelectedInstOperands,
15105	/ 39616 / // GIR_Coverage, 106,
15106	/ 39616 / GIR_EraseRootFromParent_Done,
15107	/ 39617 / // Label 1139: @39617
15108	/ 39617 / GIM_Try_CheckFeatures, /On fail goto//Label 1140/ GIMT_Encode4(`39644`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 107 //
15109	/ 39624 / // MIs[0] Operand 2
15110	/ 39624 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`16`),
15111	/ 39635 / // (sext_inreg:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, i16:{ :[Other] }) => (SEH:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
15112	/ 39635 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEH),
15113	/ 39638 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15114	/ 39640 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15115	/ 39642 / GIR_RootConstrainSelectedInstOperands,
15116	/ 39643 / // GIR_Coverage, 107,
15117	/ 39643 / GIR_EraseRootFromParent_Done,
15118	/ 39644 / // Label 1140: @39644
15119	/ 39644 / GIM_Try_CheckFeatures, /On fail goto//Label 1141/ GIMT_Encode4(`39671`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1122 //
15120	/ 39651 / // MIs[0] Operand 2
15121	/ 39651 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`8`),
15122	/ 39662 / // (sext_inreg:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, i8:{ :[Other] }) => (SEB_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
15123	/ 39662 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEB_MM),
15124	/ 39665 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15125	/ 39667 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15126	/ 39669 / GIR_RootConstrainSelectedInstOperands,
15127	/ 39670 / // GIR_Coverage, 1122,
15128	/ 39670 / GIR_EraseRootFromParent_Done,
15129	/ 39671 / // Label 1141: @39671
15130	/ 39671 / GIM_Try_CheckFeatures, /On fail goto//Label 1142/ GIMT_Encode4(`39698`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1123 //
15131	/ 39678 / // MIs[0] Operand 2
15132	/ 39678 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`16`),
15133	/ 39689 / // (sext_inreg:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, i16:{ :[Other] }) => (SEH_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt)*
15134	/ 39689 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEH_MM),
15135	/ 39692 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15136	/ 39694 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15137	/ 39696 / GIR_RootConstrainSelectedInstOperands,
15138	/ 39697 / // GIR_Coverage, 1123,
15139	/ 39697 / GIR_EraseRootFromParent_Done,
15140	/ 39698 / // Label 1142: @39698
15141	/ 39698 / GIM_Reject,
15142	/ 39699 / // Label 1138: @39699
15143	/ 39699 / GIM_Try, /On fail goto//Label 1143/ GIMT_Encode4(`39767`),
15144	/ 39704 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15145	/ 39708 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15146	/ 39712 / GIM_Try_CheckFeatures, /On fail goto//Label 1144/ GIMT_Encode4(`39739`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2038 //
15147	/ 39719 / // MIs[0] Operand 2
15148	/ 39719 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`8`),
15149	/ 39730 / // (sext_inreg:{ :[i32] } CPU16Regs:{ :[i32] }:$val, i8:{ :[Other] }) => (SebRx16:{ :[i32] } CPU16Regs:{ :[i32] }:$val)*
15150	/ 39730 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SebRx16),
15151	/ 39733 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
15152	/ 39735 / GIR_RootToRootCopy, /OpIdx/`1`, // val
15153	/ 39737 / GIR_RootConstrainSelectedInstOperands,
15154	/ 39738 / // GIR_Coverage, 2038,
15155	/ 39738 / GIR_EraseRootFromParent_Done,
15156	/ 39739 / // Label 1144: @39739
15157	/ 39739 / GIM_Try_CheckFeatures, /On fail goto//Label 1145/ GIMT_Encode4(`39766`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2039 //
15158	/ 39746 / // MIs[0] Operand 2
15159	/ 39746 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`16`),
15160	/ 39757 / // (sext_inreg:{ :[i32] } CPU16Regs:{ :[i32] }:$val, i16:{ :[Other] }) => (SehRx16:{ :[i32] } CPU16Regs:{ :[i32] }:$val)*
15161	/ 39757 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SehRx16),
15162	/ 39760 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
15163	/ 39762 / GIR_RootToRootCopy, /OpIdx/`1`, // val
15164	/ 39764 / GIR_RootConstrainSelectedInstOperands,
15165	/ 39765 / // GIR_Coverage, 2039,
15166	/ 39765 / GIR_EraseRootFromParent_Done,
15167	/ 39766 / // Label 1145: @39766
15168	/ 39766 / GIM_Reject,
15169	/ 39767 / // Label 1143: @39767
15170	/ 39767 / GIM_Reject,
15171	/ 39768 / // Label 1137: @39768
15172	/ 39768 / GIM_Reject,
15173	/ 39769 / // Label 1135: @39769
15174	/ 39769 / GIM_Try, /On fail goto//Label 1146/ GIMT_Encode4(`39867`),
15175	/ 39774 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
15176	/ 39777 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15177	/ 39781 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15178	/ 39785 / GIM_Try_CheckFeatures, /On fail goto//Label 1147/ GIMT_Encode4(`39812`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 288 //
15179	/ 39792 / // MIs[0] Operand 2
15180	/ 39792 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`8`),
15181	/ 39803 / // (sext_inreg:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, i8:{ :[Other] }) => (SEB64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt)*
15182	/ 39803 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEB64),
15183	/ 39806 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15184	/ 39808 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15185	/ 39810 / GIR_RootConstrainSelectedInstOperands,
15186	/ 39811 / // GIR_Coverage, 288,
15187	/ 39811 / GIR_EraseRootFromParent_Done,
15188	/ 39812 / // Label 1147: @39812
15189	/ 39812 / GIM_Try_CheckFeatures, /On fail goto//Label 1148/ GIMT_Encode4(`39839`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 289 //
15190	/ 39819 / // MIs[0] Operand 2
15191	/ 39819 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`16`),
15192	/ 39830 / // (sext_inreg:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, i16:{ :[Other] }) => (SEH64:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt)*
15193	/ 39830 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEH64),
15194	/ 39833 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15195	/ 39835 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15196	/ 39837 / GIR_RootConstrainSelectedInstOperands,
15197	/ 39838 / // GIR_Coverage, 289,
15198	/ 39838 / GIR_EraseRootFromParent_Done,
15199	/ 39839 / // Label 1148: @39839
15200	/ 39839 / GIM_Try_CheckFeatures, /On fail goto//Label 1149/ GIMT_Encode4(`39866`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1691 //
15201	/ 39846 / // MIs[0] Operand 2
15202	/ 39846 / GIM_CheckLiteralInt, /MI/`0`, /Op/`2`, GIMT_Encode8(`32`),
15203	/ 39857 / // (sext_inreg:{ :[i64] } GPR64:{ :[i64] }:$src, i32:{ :[Other] }) => (SLL64_64:{ :[i64] } GPR64:{ :[i64] }:$src)*
15204	/ 39857 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL64_64),
15205	/ 39860 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15206	/ 39862 / GIR_RootToRootCopy, /OpIdx/`1`, // src
15207	/ 39864 / GIR_RootConstrainSelectedInstOperands,
15208	/ 39865 / // GIR_Coverage, 1691,
15209	/ 39865 / GIR_EraseRootFromParent_Done,
15210	/ 39866 / // Label 1149: @39866
15211	/ 39866 / GIM_Reject,
15212	/ 39867 / // Label 1146: @39867
15213	/ 39867 / GIM_Reject,
15214	/ 39868 / // Label 1136: @39868
15215	/ 39868 / GIM_Reject,
15216	/ 39869 / // Label 36: @39869
15217	/ 39869 / GIM_Try, /On fail goto//Label 1150/ GIMT_Encode4(`40065`),
15218	/ 39874 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s64,
15219	/ 39877 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
15220	/ 39880 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15221	/ 39884 / GIM_Try_CheckFeatures, /On fail goto//Label 1151/ GIMT_Encode4(`39939`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 307 //
15222	/ 39891 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
15223	/ 39895 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
15224	/ 39899 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
15225	/ 39903 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
15226	/ 39907 / // MIs[1] Operand 1
15227	/ 39907 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
15228	/ 39912 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15229	/ 39917 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15230	/ 39922 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15231	/* 39924 / // (zext:{ :[i64] } (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETEQ:{ :[Other] })) => (SEQ:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15232	/ 39924 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEQ),
15233	/ 39927 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15234	/ 39929 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
15235	/ 39933 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
15236	/ 39937 / GIR_RootConstrainSelectedInstOperands,
15237	/ 39938 / // GIR_Coverage, 307,
15238	/ 39938 / GIR_EraseRootFromParent_Done,
15239	/ 39939 / // Label 1151: @39939
15240	/ 39939 / GIM_Try_CheckFeatures, /On fail goto//Label 1152/ GIMT_Encode4(`39994`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 309 //
15241	/ 39946 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
15242	/ 39950 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
15243	/ 39954 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
15244	/ 39958 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
15245	/ 39962 / // MIs[1] Operand 1
15246	/ 39962 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
15247	/ 39967 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15248	/ 39972 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15249	/ 39977 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15250	/* 39979 / // (zext:{ :[i64] } (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETNE:{ :[Other] })) => (SNE:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15251	/ 39979 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SNE),
15252	/ 39982 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15253	/ 39984 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // rs
15254	/ 39988 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // rt
15255	/ 39992 / GIR_RootConstrainSelectedInstOperands,
15256	/ 39993 / // GIR_Coverage, 309,
15257	/ 39993 / GIR_EraseRootFromParent_Done,
15258	/ 39994 / // Label 1152: @39994
15259	/ 39994 / GIM_Try, /On fail goto//Label 1153/ GIMT_Encode4(`40064`),
15260	/ 39999 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15261	/ 40003 / GIM_Try_CheckFeatures, /On fail goto//Label 1154/ GIMT_Encode4(`40041`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1686 //
15262	/ 40010 / // (zext:{ :[i64] } GPR32:{ :[i32] }:$src) => (DSRL:{ :[i64] } (DSLL64_32:{ :[i64] } GPR32:{ :[i32] }:$src), 32:{ :[i32] })
15263	/ 40010 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
15264	/ 40013 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::DSLL64_32),
15265	/ 40017 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15266	/ 40022 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // src
15267	/ 40026 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
15268	/ 40028 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSRL),
15269	/ 40031 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15270	/ 40033 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
15271	/ 40036 / GIR_AddImm8, /InsnID/`0`, /Imm/`32`,
15272	/ 40039 / GIR_RootConstrainSelectedInstOperands,
15273	/ 40040 / // GIR_Coverage, 1686,
15274	/ 40040 / GIR_EraseRootFromParent_Done,
15275	/ 40041 / // Label 1154: @40041
15276	/ 40041 / GIM_Try_CheckFeatures, /On fail goto//Label 1155/ GIMT_Encode4(`40063`), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1689 //
15277	/ 40048 / // (zext:{ :[i64] } GPR32:{ :[i32] }:$src) => (DEXT64_32:{ :[i64] } GPR32:{ :[i32] }:$src, 0:{ :[i32] }, 32:{ :[i32] })
15278	/ 40048 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DEXT64_32),
15279	/ 40051 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
15280	/ 40053 / GIR_RootToRootCopy, /OpIdx/`1`, // src
15281	/ 40055 / GIR_AddImm8, /InsnID/`0`, /Imm/`0`,
15282	/ 40058 / GIR_AddImm8, /InsnID/`0`, /Imm/`32`,
15283	/ 40061 / GIR_RootConstrainSelectedInstOperands,
15284	/ 40062 / // GIR_Coverage, 1689,
15285	/ 40062 / GIR_EraseRootFromParent_Done,
15286	/ 40063 / // Label 1155: @40063
15287	/ 40063 / GIM_Reject,
15288	/ 40064 / // Label 1153: @40064
15289	/ 40064 / GIM_Reject,
15290	/ 40065 / // Label 1150: @40065
15291	/ 40065 / GIM_Reject,
15292	/ 40066 / // Label 37: @40066
15293	/ 40066 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1162/ GIMT_Encode4(`41840`),
15294	/ 40077 / /GILLT_s32//Label 1156/ GIMT_Encode4(`40109`),
15295	/ 40081 / /GILLT_s64//Label 1157/ GIMT_Encode4(`40362`), GIMT_Encode4(`0`),
15296	/ 40089 / /GILLT_v16s8//Label 1158/ GIMT_Encode4(`40500`), GIMT_Encode4(`0`),
15297	/ 40097 / /GILLT_v8s16//Label 1159/ GIMT_Encode4(`41149`),
15298	/ 40101 / /GILLT_v4s32//Label 1160/ GIMT_Encode4(`41542`),
15299	/ 40105 / /GILLT_v2s64//Label 1161/ GIMT_Encode4(`41807`),
15300	/ 40109 / // Label 1156: @40109
15301	/ 40109 / GIM_Try, /On fail goto//Label 1163/ GIMT_Encode4(`40361`),
15302	/ 40114 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
15303	/ 40117 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
15304	/ 40120 / GIM_Try_CheckFeatures, /On fail goto//Label 1164/ GIMT_Encode4(`40161`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 55 //
15305	/ 40127 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15306	/ 40131 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15307	/ 40135 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15308	/ 40139 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15309	/ 40143 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15310	/ 40147 / // MIs[1] Operand 1
15311	/ 40147 / // No operand predicates
15312	/ 40147 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15313	/ 40149 / // (shl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$shamt)
15314	/ 40149 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL),
15315	/ 40152 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15316	/ 40154 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15317	/ 40156 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
15318	/ 40159 / GIR_RootConstrainSelectedInstOperands,
15319	/ 40160 / // GIR_Coverage, 55,
15320	/ 40160 / GIR_EraseRootFromParent_Done,
15321	/ 40161 / // Label 1164: @40161
15322	/ 40161 / GIM_Try_CheckFeatures, /On fail goto//Label 1165/ GIMT_Encode4(`40202`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1962 //
15323	/ 40168 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15324	/ 40172 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15325	/ 40176 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15326	/ 40180 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15327	/ 40184 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15328	/ 40188 / // MIs[1] Operand 1
15329	/ 40188 / // No operand predicates
15330	/ 40188 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15331	/* 40190 / // (shl:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15332	/ 40190 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SllX16),
15333	/ 40193 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
15334	/ 40195 / GIR_RootToRootCopy, /OpIdx/`1`, // in
15335	/ 40197 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
15336	/ 40200 / GIR_RootConstrainSelectedInstOperands,
15337	/ 40201 / // GIR_Coverage, 1962,
15338	/ 40201 / GIR_EraseRootFromParent_Done,
15339	/ 40202 / // Label 1165: @40202
15340	/ 40202 / GIM_Try_CheckFeatures, /On fail goto//Label 1166/ GIMT_Encode4(`40243`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2299 //
15341	/ 40209 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
15342	/ 40213 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
15343	/ 40217 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15344	/ 40221 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15345	/ 40225 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
15346	/ 40229 / // MIs[1] Operand 1
15347	/ 40229 / // No operand predicates
15348	/ 40229 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15349	/* 40231 / // (shl:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
15350	/ 40231 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL16_MM),
15351	/ 40234 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15352	/ 40236 / GIR_RootToRootCopy, /OpIdx/`1`, // src
15353	/ 40238 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
15354	/ 40241 / GIR_RootConstrainSelectedInstOperands,
15355	/ 40242 / // GIR_Coverage, 2299,
15356	/ 40242 / GIR_EraseRootFromParent_Done,
15357	/ 40243 / // Label 1166: @40243
15358	/ 40243 / GIM_Try, /On fail goto//Label 1167/ GIMT_Encode4(`40308`),
15359	/ 40248 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15360	/ 40252 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15361	/ 40256 / GIM_Try_CheckFeatures, /On fail goto//Label 1168/ GIMT_Encode4(`40289`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2300 //
15362	/ 40263 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15363	/ 40267 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15364	/ 40271 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15365	/ 40275 / // MIs[1] Operand 1
15366	/ 40275 / // No operand predicates
15367	/ 40275 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15368	/* 40277 / // (shl:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15369	/ 40277 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_MM),
15370	/ 40280 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15371	/ 40282 / GIR_RootToRootCopy, /OpIdx/`1`, // src
15372	/ 40284 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
15373	/ 40287 / GIR_RootConstrainSelectedInstOperands,
15374	/ 40288 / // GIR_Coverage, 2300,
15375	/ 40288 / GIR_EraseRootFromParent_Done,
15376	/ 40289 / // Label 1168: @40289
15377	/ 40289 / GIM_Try_CheckFeatures, /On fail goto//Label 1169/ GIMT_Encode4(`40307`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 61 //
15378	/ 40296 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15379	/ 40300 / // (shl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SLLV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
15380	/ 40300 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLLV),
15381	/ 40305 / GIR_RootConstrainSelectedInstOperands,
15382	/ 40306 / // GIR_Coverage, 61,
15383	/ 40306 / GIR_Done,
15384	/ 40307 / // Label 1169: @40307
15385	/ 40307 / GIM_Reject,
15386	/ 40308 / // Label 1167: @40308
15387	/ 40308 / GIM_Try_CheckFeatures, /On fail goto//Label 1170/ GIMT_Encode4(`40334`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1965 //
15388	/ 40315 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15389	/ 40319 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15390	/ 40323 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15391	/ 40327 / // (shl:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra) => (SllvRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra)
15392	/ 40327 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SllvRxRy16),
15393	/ 40332 / GIR_RootConstrainSelectedInstOperands,
15394	/ 40333 / // GIR_Coverage, 1965,
15395	/ 40333 / GIR_Done,
15396	/ 40334 / // Label 1170: @40334
15397	/ 40334 / GIM_Try_CheckFeatures, /On fail goto//Label 1171/ GIMT_Encode4(`40360`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2301 //
15398	/ 40341 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15399	/ 40345 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15400	/ 40349 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15401	/ 40353 / // (shl:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs) => (SLLV_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs)
15402	/ 40353 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLLV_MM),
15403	/ 40358 / GIR_RootConstrainSelectedInstOperands,
15404	/ 40359 / // GIR_Coverage, 2301,
15405	/ 40359 / GIR_Done,
15406	/ 40360 / // Label 1171: @40360
15407	/ 40360 / GIM_Reject,
15408	/ 40361 / // Label 1163: @40361
15409	/ 40361 / GIM_Reject,
15410	/ 40362 / // Label 1157: @40362
15411	/ 40362 / GIM_Try, /On fail goto//Label 1172/ GIMT_Encode4(`40499`),
15412	/ 40367 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
15413	/ 40370 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
15414	/ 40373 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15415	/ 40377 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15416	/ 40381 / GIM_Try_CheckFeatures, /On fail goto//Label 1173/ GIMT_Encode4(`40414`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 237 //
15417	/ 40388 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15418	/ 40392 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15419	/ 40396 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15420	/ 40400 / // MIs[1] Operand 1
15421	/ 40400 / // No operand predicates
15422	/ 40400 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15423	/ 40402 / // (shl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$shamt)
15424	/ 40402 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSLL),
15425	/ 40405 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15426	/ 40407 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15427	/ 40409 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
15428	/ 40412 / GIR_RootConstrainSelectedInstOperands,
15429	/ 40413 / // GIR_Coverage, 237,
15430	/ 40413 / GIR_EraseRootFromParent_Done,
15431	/ 40414 / // Label 1173: @40414
15432	/ 40414 / GIM_Try_CheckFeatures, /On fail goto//Label 1174/ GIMT_Encode4(`40480`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1679 //
15433	/ 40421 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15434	/ 40425 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_TRUNC),
15435	/ 40429 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
15436	/ 40433 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
15437	/ 40438 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15438	/* 40440 / // (shl:{ :[i64] } GPR64:{ :[i64] }:$rt, (trunc:{ :[i32] } GPR64:{ :[i64] }:$rs)) => (DSLLV:{ :[i64] } GPR64:{ :[i64] }:$rt, (EXTRACT_SUBREG:{ :[i32] } GPR64:{ :[i64] }:$rs, sub_32:{ :[i32] }))
15439	/ 40440 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
15440	/ 40443 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
15441	/ 40447 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15442	/ 40452 / GIR_CopySubReg, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`1`, /SubRegIdx/GIMT_Encode2(`1`), // rs
15443	/ 40458 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
15444	/ 40463 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
15445	/ 40468 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSLLV),
15446	/ 40471 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15447	/ 40473 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
15448	/ 40475 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
15449	/ 40478 / GIR_RootConstrainSelectedInstOperands,
15450	/ 40479 / // GIR_Coverage, 1679,
15451	/ 40479 / GIR_EraseRootFromParent_Done,
15452	/ 40480 / // Label 1174: @40480
15453	/ 40480 / GIM_Try_CheckFeatures, /On fail goto//Label 1175/ GIMT_Encode4(`40498`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 243 //
15454	/ 40487 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15455	/ 40491 / // (shl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (DSLLV:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
15456	/ 40491 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DSLLV),
15457	/ 40496 / GIR_RootConstrainSelectedInstOperands,
15458	/ 40497 / // GIR_Coverage, 243,
15459	/ 40497 / GIR_Done,
15460	/ 40498 / // Label 1175: @40498
15461	/ 40498 / GIM_Reject,
15462	/ 40499 / // Label 1172: @40499
15463	/ 40499 / GIM_Reject,
15464	/ 40500 / // Label 1158: @40500
15465	/ 40500 / GIM_Try, /On fail goto//Label 1176/ GIMT_Encode4(`41148`),
15466	/ 40505 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
15467	/ 40508 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
15468	/ 40511 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
15469	/ 40515 / GIM_Try_CheckFeatures, /On fail goto//Label 1177/ GIMT_Encode4(`40820`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2633 //
15470	/ 40522 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15471	/ 40526 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15472	/ 40530 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
15473	/ 40534 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
15474	/ 40538 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
15475	/ 40542 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15476	/ 40546 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
15477	/ 40549 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15478	/ 40553 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15479	/ 40557 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15480	/ 40561 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15481	/ 40565 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
15482	/ 40569 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
15483	/ 40573 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
15484	/ 40577 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
15485	/ 40581 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
15486	/ 40585 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
15487	/ 40589 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
15488	/ 40593 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
15489	/ 40597 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
15490	/ 40601 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
15491	/ 40605 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
15492	/ 40609 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
15493	/ 40613 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15494	/ 40617 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15495	/ 40621 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15496	/ 40625 / // MIs[3] Operand 1
15497	/ 40625 / // No operand predicates
15498	/ 40625 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15499	/ 40629 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15500	/ 40633 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15501	/ 40637 / // MIs[4] Operand 1
15502	/ 40637 / // No operand predicates
15503	/ 40637 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15504	/ 40641 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15505	/ 40645 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15506	/ 40649 / // MIs[5] Operand 1
15507	/ 40649 / // No operand predicates
15508	/ 40649 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15509	/ 40653 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15510	/ 40657 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15511	/ 40661 / // MIs[6] Operand 1
15512	/ 40661 / // No operand predicates
15513	/ 40661 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
15514	/ 40665 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15515	/ 40669 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15516	/ 40673 / // MIs[7] Operand 1
15517	/ 40673 / // No operand predicates
15518	/ 40673 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
15519	/ 40677 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15520	/ 40681 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15521	/ 40685 / // MIs[8] Operand 1
15522	/ 40685 / // No operand predicates
15523	/ 40685 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
15524	/ 40689 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15525	/ 40693 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15526	/ 40697 / // MIs[9] Operand 1
15527	/ 40697 / // No operand predicates
15528	/ 40697 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
15529	/ 40701 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15530	/ 40705 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15531	/ 40709 / // MIs[10] Operand 1
15532	/ 40709 / // No operand predicates
15533	/ 40709 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
15534	/ 40713 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15535	/ 40717 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15536	/ 40721 / // MIs[11] Operand 1
15537	/ 40721 / // No operand predicates
15538	/ 40721 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
15539	/ 40725 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15540	/ 40729 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15541	/ 40733 / // MIs[12] Operand 1
15542	/ 40733 / // No operand predicates
15543	/ 40733 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
15544	/ 40737 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15545	/ 40741 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15546	/ 40745 / // MIs[13] Operand 1
15547	/ 40745 / // No operand predicates
15548	/ 40745 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
15549	/ 40749 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15550	/ 40753 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15551	/ 40757 / // MIs[14] Operand 1
15552	/ 40757 / // No operand predicates
15553	/ 40757 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
15554	/ 40761 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15555	/ 40765 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15556	/ 40769 / // MIs[15] Operand 1
15557	/ 40769 / // No operand predicates
15558	/ 40769 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
15559	/ 40773 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15560	/ 40777 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15561	/ 40781 / // MIs[16] Operand 1
15562	/ 40781 / // No operand predicates
15563	/ 40781 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
15564	/ 40785 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15565	/ 40789 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15566	/ 40793 / // MIs[17] Operand 1
15567	/ 40793 / // No operand predicates
15568	/ 40793 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
15569	/ 40797 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15570	/ 40801 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15571	/ 40805 / // MIs[18] Operand 1
15572	/ 40805 / // No operand predicates
15573	/ 40805 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
15574	/* 40807 / // (shl:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ :[v16i8] }:$wt)) => (SLL_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15575	/ 40807 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_B),
15576	/ 40810 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15577	/ 40812 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15578	/ 40814 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
15579	/ 40818 / GIR_RootConstrainSelectedInstOperands,
15580	/ 40819 / // GIR_Coverage, 2633,
15581	/ 40819 / GIR_EraseRootFromParent_Done,
15582	/ 40820 / // Label 1177: @40820
15583	/ 40820 / GIM_Try_CheckFeatures, /On fail goto//Label 1178/ GIMT_Encode4(`41125`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2198 //
15584	/ 40827 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15585	/ 40831 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15586	/ 40835 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
15587	/ 40839 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
15588	/ 40843 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
15589	/ 40847 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15590	/ 40851 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
15591	/ 40854 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15592	/ 40858 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15593	/ 40862 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15594	/ 40866 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15595	/ 40870 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
15596	/ 40874 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
15597	/ 40878 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
15598	/ 40882 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
15599	/ 40886 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
15600	/ 40890 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
15601	/ 40894 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
15602	/ 40898 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
15603	/ 40902 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
15604	/ 40906 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
15605	/ 40910 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
15606	/ 40914 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
15607	/ 40918 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15608	/ 40922 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15609	/ 40926 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15610	/ 40930 / // MIs[3] Operand 1
15611	/ 40930 / // No operand predicates
15612	/ 40930 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15613	/ 40934 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15614	/ 40938 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15615	/ 40942 / // MIs[4] Operand 1
15616	/ 40942 / // No operand predicates
15617	/ 40942 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15618	/ 40946 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15619	/ 40950 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15620	/ 40954 / // MIs[5] Operand 1
15621	/ 40954 / // No operand predicates
15622	/ 40954 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15623	/ 40958 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15624	/ 40962 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15625	/ 40966 / // MIs[6] Operand 1
15626	/ 40966 / // No operand predicates
15627	/ 40966 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
15628	/ 40970 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15629	/ 40974 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15630	/ 40978 / // MIs[7] Operand 1
15631	/ 40978 / // No operand predicates
15632	/ 40978 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
15633	/ 40982 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15634	/ 40986 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15635	/ 40990 / // MIs[8] Operand 1
15636	/ 40990 / // No operand predicates
15637	/ 40990 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
15638	/ 40994 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15639	/ 40998 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15640	/ 41002 / // MIs[9] Operand 1
15641	/ 41002 / // No operand predicates
15642	/ 41002 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
15643	/ 41006 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15644	/ 41010 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15645	/ 41014 / // MIs[10] Operand 1
15646	/ 41014 / // No operand predicates
15647	/ 41014 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
15648	/ 41018 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15649	/ 41022 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15650	/ 41026 / // MIs[11] Operand 1
15651	/ 41026 / // No operand predicates
15652	/ 41026 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
15653	/ 41030 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15654	/ 41034 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15655	/ 41038 / // MIs[12] Operand 1
15656	/ 41038 / // No operand predicates
15657	/ 41038 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
15658	/ 41042 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15659	/ 41046 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15660	/ 41050 / // MIs[13] Operand 1
15661	/ 41050 / // No operand predicates
15662	/ 41050 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
15663	/ 41054 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15664	/ 41058 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15665	/ 41062 / // MIs[14] Operand 1
15666	/ 41062 / // No operand predicates
15667	/ 41062 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
15668	/ 41066 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15669	/ 41070 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15670	/ 41074 / // MIs[15] Operand 1
15671	/ 41074 / // No operand predicates
15672	/ 41074 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
15673	/ 41078 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15674	/ 41082 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15675	/ 41086 / // MIs[16] Operand 1
15676	/ 41086 / // No operand predicates
15677	/ 41086 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
15678	/ 41090 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15679	/ 41094 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15680	/ 41098 / // MIs[17] Operand 1
15681	/ 41098 / // No operand predicates
15682	/ 41098 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
15683	/ 41102 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15684	/ 41106 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15685	/ 41110 / // MIs[18] Operand 1
15686	/ 41110 / // No operand predicates
15687	/ 41110 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
15688	/* 41112 / // (shl:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } v16i8:{ :[v16i8] }:$wt, (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15689	/ 41112 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_B),
15690	/ 41115 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15691	/ 41117 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15692	/ 41119 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
15693	/ 41123 / GIR_RootConstrainSelectedInstOperands,
15694	/ 41124 / // GIR_Coverage, 2198,
15695	/ 41124 / GIR_EraseRootFromParent_Done,
15696	/ 41125 / // Label 1178: @41125
15697	/ 41125 / GIM_Try_CheckFeatures, /On fail goto//Label 1179/ GIMT_Encode4(`41147`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 984 //
15698	/ 41132 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
15699	/ 41136 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
15700	/ 41140 / // (shl:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SLL_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
15701	/ 41140 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLL_B),
15702	/ 41145 / GIR_RootConstrainSelectedInstOperands,
15703	/ 41146 / // GIR_Coverage, 984,
15704	/ 41146 / GIR_Done,
15705	/ 41147 / // Label 1179: @41147
15706	/ 41147 / GIM_Reject,
15707	/ 41148 / // Label 1176: @41148
15708	/ 41148 / GIM_Reject,
15709	/ 41149 / // Label 1159: @41149
15710	/ 41149 / GIM_Try, /On fail goto//Label 1180/ GIMT_Encode4(`41541`),
15711	/ 41154 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
15712	/ 41157 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
15713	/ 41160 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
15714	/ 41164 / GIM_Try_CheckFeatures, /On fail goto//Label 1181/ GIMT_Encode4(`41341`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2634 //
15715	/ 41171 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15716	/ 41175 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15717	/ 41179 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
15718	/ 41183 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
15719	/ 41187 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
15720	/ 41191 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15721	/ 41195 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
15722	/ 41198 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15723	/ 41202 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15724	/ 41206 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15725	/ 41210 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15726	/ 41214 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
15727	/ 41218 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
15728	/ 41222 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
15729	/ 41226 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
15730	/ 41230 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15731	/ 41234 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15732	/ 41238 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15733	/ 41242 / // MIs[3] Operand 1
15734	/ 41242 / // No operand predicates
15735	/ 41242 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15736	/ 41246 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15737	/ 41250 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15738	/ 41254 / // MIs[4] Operand 1
15739	/ 41254 / // No operand predicates
15740	/ 41254 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15741	/ 41258 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15742	/ 41262 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15743	/ 41266 / // MIs[5] Operand 1
15744	/ 41266 / // No operand predicates
15745	/ 41266 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15746	/ 41270 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15747	/ 41274 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15748	/ 41278 / // MIs[6] Operand 1
15749	/ 41278 / // No operand predicates
15750	/ 41278 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
15751	/ 41282 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15752	/ 41286 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15753	/ 41290 / // MIs[7] Operand 1
15754	/ 41290 / // No operand predicates
15755	/ 41290 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
15756	/ 41294 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15757	/ 41298 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15758	/ 41302 / // MIs[8] Operand 1
15759	/ 41302 / // No operand predicates
15760	/ 41302 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
15761	/ 41306 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15762	/ 41310 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15763	/ 41314 / // MIs[9] Operand 1
15764	/ 41314 / // No operand predicates
15765	/ 41314 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
15766	/ 41318 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15767	/ 41322 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15768	/ 41326 / // MIs[10] Operand 1
15769	/ 41326 / // No operand predicates
15770	/ 41326 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
15771	/* 41328 / // (shl:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ :[v8i16] }:$wt)) => (SLL_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15772	/ 41328 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_H),
15773	/ 41331 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15774	/ 41333 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15775	/ 41335 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
15776	/ 41339 / GIR_RootConstrainSelectedInstOperands,
15777	/ 41340 / // GIR_Coverage, 2634,
15778	/ 41340 / GIR_EraseRootFromParent_Done,
15779	/ 41341 / // Label 1181: @41341
15780	/ 41341 / GIM_Try_CheckFeatures, /On fail goto//Label 1182/ GIMT_Encode4(`41518`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2199 //
15781	/ 41348 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15782	/ 41352 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15783	/ 41356 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
15784	/ 41360 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
15785	/ 41364 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
15786	/ 41368 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15787	/ 41372 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
15788	/ 41375 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15789	/ 41379 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15790	/ 41383 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15791	/ 41387 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15792	/ 41391 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
15793	/ 41395 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
15794	/ 41399 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
15795	/ 41403 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
15796	/ 41407 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15797	/ 41411 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15798	/ 41415 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15799	/ 41419 / // MIs[3] Operand 1
15800	/ 41419 / // No operand predicates
15801	/ 41419 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15802	/ 41423 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15803	/ 41427 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15804	/ 41431 / // MIs[4] Operand 1
15805	/ 41431 / // No operand predicates
15806	/ 41431 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15807	/ 41435 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15808	/ 41439 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15809	/ 41443 / // MIs[5] Operand 1
15810	/ 41443 / // No operand predicates
15811	/ 41443 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15812	/ 41447 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15813	/ 41451 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15814	/ 41455 / // MIs[6] Operand 1
15815	/ 41455 / // No operand predicates
15816	/ 41455 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
15817	/ 41459 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15818	/ 41463 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15819	/ 41467 / // MIs[7] Operand 1
15820	/ 41467 / // No operand predicates
15821	/ 41467 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
15822	/ 41471 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15823	/ 41475 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15824	/ 41479 / // MIs[8] Operand 1
15825	/ 41479 / // No operand predicates
15826	/ 41479 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
15827	/ 41483 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15828	/ 41487 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15829	/ 41491 / // MIs[9] Operand 1
15830	/ 41491 / // No operand predicates
15831	/ 41491 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
15832	/ 41495 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15833	/ 41499 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15834	/ 41503 / // MIs[10] Operand 1
15835	/ 41503 / // No operand predicates
15836	/ 41503 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
15837	/* 41505 / // (shl:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } v8i16:{ :[v8i16] }:$wt, (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15838	/ 41505 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_H),
15839	/ 41508 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15840	/ 41510 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15841	/ 41512 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
15842	/ 41516 / GIR_RootConstrainSelectedInstOperands,
15843	/ 41517 / // GIR_Coverage, 2199,
15844	/ 41517 / GIR_EraseRootFromParent_Done,
15845	/ 41518 / // Label 1182: @41518
15846	/ 41518 / GIM_Try_CheckFeatures, /On fail goto//Label 1183/ GIMT_Encode4(`41540`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 985 //
15847	/ 41525 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
15848	/ 41529 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
15849	/ 41533 / // (shl:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SLL_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
15850	/ 41533 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLL_H),
15851	/ 41538 / GIR_RootConstrainSelectedInstOperands,
15852	/ 41539 / // GIR_Coverage, 985,
15853	/ 41539 / GIR_Done,
15854	/ 41540 / // Label 1183: @41540
15855	/ 41540 / GIM_Reject,
15856	/ 41541 / // Label 1180: @41541
15857	/ 41541 / GIM_Reject,
15858	/ 41542 / // Label 1160: @41542
15859	/ 41542 / GIM_Try, /On fail goto//Label 1184/ GIMT_Encode4(`41806`),
15860	/ 41547 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
15861	/ 41550 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
15862	/ 41553 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
15863	/ 41557 / GIM_Try_CheckFeatures, /On fail goto//Label 1185/ GIMT_Encode4(`41670`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2635 //
15864	/ 41564 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15865	/ 41568 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15866	/ 41572 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
15867	/ 41576 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
15868	/ 41580 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
15869	/ 41584 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15870	/ 41588 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
15871	/ 41591 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15872	/ 41595 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15873	/ 41599 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15874	/ 41603 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15875	/ 41607 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15876	/ 41611 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15877	/ 41615 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15878	/ 41619 / // MIs[3] Operand 1
15879	/ 41619 / // No operand predicates
15880	/ 41619 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15881	/ 41623 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15882	/ 41627 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15883	/ 41631 / // MIs[4] Operand 1
15884	/ 41631 / // No operand predicates
15885	/ 41631 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15886	/ 41635 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15887	/ 41639 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15888	/ 41643 / // MIs[5] Operand 1
15889	/ 41643 / // No operand predicates
15890	/ 41643 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15891	/ 41647 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15892	/ 41651 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15893	/ 41655 / // MIs[6] Operand 1
15894	/ 41655 / // No operand predicates
15895	/ 41655 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
15896	/* 41657 / // (shl:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ :[v4i32] }:$wt)) => (SLL_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15897	/ 41657 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_W),
15898	/ 41660 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15899	/ 41662 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15900	/ 41664 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
15901	/ 41668 / GIR_RootConstrainSelectedInstOperands,
15902	/ 41669 / // GIR_Coverage, 2635,
15903	/ 41669 / GIR_EraseRootFromParent_Done,
15904	/ 41670 / // Label 1185: @41670
15905	/ 41670 / GIM_Try_CheckFeatures, /On fail goto//Label 1186/ GIMT_Encode4(`41783`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2200 //
15906	/ 41677 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15907	/ 41681 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
15908	/ 41685 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
15909	/ 41689 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
15910	/ 41693 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
15911	/ 41697 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15912	/ 41701 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
15913	/ 41704 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
15914	/ 41708 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
15915	/ 41712 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
15916	/ 41716 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
15917	/ 41720 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
15918	/ 41724 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15919	/ 41728 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15920	/ 41732 / // MIs[3] Operand 1
15921	/ 41732 / // No operand predicates
15922	/ 41732 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
15923	/ 41736 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15924	/ 41740 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15925	/ 41744 / // MIs[4] Operand 1
15926	/ 41744 / // No operand predicates
15927	/ 41744 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
15928	/ 41748 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15929	/ 41752 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15930	/ 41756 / // MIs[5] Operand 1
15931	/ 41756 / // No operand predicates
15932	/ 41756 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
15933	/ 41760 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15934	/ 41764 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15935	/ 41768 / // MIs[6] Operand 1
15936	/ 41768 / // No operand predicates
15937	/ 41768 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
15938	/* 41770 / // (shl:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } v4i32:{ :[v4i32] }:$wt, (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15939	/ 41770 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLL_W),
15940	/ 41773 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
15941	/ 41775 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
15942	/ 41777 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
15943	/ 41781 / GIR_RootConstrainSelectedInstOperands,
15944	/ 41782 / // GIR_Coverage, 2200,
15945	/ 41782 / GIR_EraseRootFromParent_Done,
15946	/ 41783 / // Label 1186: @41783
15947	/ 41783 / GIM_Try_CheckFeatures, /On fail goto//Label 1187/ GIMT_Encode4(`41805`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 986 //
15948	/ 41790 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
15949	/ 41794 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
15950	/ 41798 / // (shl:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SLL_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
15951	/ 41798 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLL_W),
15952	/ 41803 / GIR_RootConstrainSelectedInstOperands,
15953	/ 41804 / // GIR_Coverage, 986,
15954	/ 41804 / GIR_Done,
15955	/ 41805 / // Label 1187: @41805
15956	/ 41805 / GIM_Reject,
15957	/ 41806 / // Label 1184: @41806
15958	/ 41806 / GIM_Reject,
15959	/ 41807 / // Label 1161: @41807
15960	/ 41807 / GIM_Try_CheckFeatures, /On fail goto//Label 1188/ GIMT_Encode4(`41839`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 987 //
15961	/ 41814 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
15962	/ 41817 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
15963	/ 41820 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
15964	/ 41824 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
15965	/ 41828 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
15966	/ 41832 / // (shl:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SLL_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
15967	/ 41832 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SLL_D),
15968	/ 41837 / GIR_RootConstrainSelectedInstOperands,
15969	/ 41838 / // GIR_Coverage, 987,
15970	/ 41838 / GIR_Done,
15971	/ 41839 / // Label 1188: @41839
15972	/ 41839 / GIM_Reject,
15973	/ 41840 / // Label 1162: @41840
15974	/ 41840 / GIM_Reject,
15975	/ 41841 / // Label 38: @41841
15976	/ 41841 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1195/ GIMT_Encode4(`43615`),
15977	/ 41852 / /GILLT_s32//Label 1189/ GIMT_Encode4(`41884`),
15978	/ 41856 / /GILLT_s64//Label 1190/ GIMT_Encode4(`42137`), GIMT_Encode4(`0`),
15979	/ 41864 / /GILLT_v16s8//Label 1191/ GIMT_Encode4(`42275`), GIMT_Encode4(`0`),
15980	/ 41872 / /GILLT_v8s16//Label 1192/ GIMT_Encode4(`42924`),
15981	/ 41876 / /GILLT_v4s32//Label 1193/ GIMT_Encode4(`43317`),
15982	/ 41880 / /GILLT_v2s64//Label 1194/ GIMT_Encode4(`43582`),
15983	/ 41884 / // Label 1189: @41884
15984	/ 41884 / GIM_Try, /On fail goto//Label 1196/ GIMT_Encode4(`42136`),
15985	/ 41889 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
15986	/ 41892 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
15987	/ 41895 / GIM_Try_CheckFeatures, /On fail goto//Label 1197/ GIMT_Encode4(`41936`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 57 //
15988	/ 41902 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15989	/ 41906 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
15990	/ 41910 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
15991	/ 41914 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15992	/ 41918 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15993	/ 41922 / // MIs[1] Operand 1
15994	/ 41922 / // No operand predicates
15995	/ 41922 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
15996	/ 41924 / // (srl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$shamt)
15997	/ 41924 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL),
15998	/ 41927 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
15999	/ 41929 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16000	/ 41931 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
16001	/ 41934 / GIR_RootConstrainSelectedInstOperands,
16002	/ 41935 / // GIR_Coverage, 57,
16003	/ 41935 / GIR_EraseRootFromParent_Done,
16004	/ 41936 / // Label 1197: @41936
16005	/ 41936 / GIM_Try_CheckFeatures, /On fail goto//Label 1198/ GIMT_Encode4(`41977`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1963 //
16006	/ 41943 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16007	/ 41947 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16008	/ 41951 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16009	/ 41955 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16010	/ 41959 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16011	/ 41963 / // MIs[1] Operand 1
16012	/ 41963 / // No operand predicates
16013	/ 41963 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16014	/* 41965 / // (srl:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16015	/ 41965 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SrlX16),
16016	/ 41968 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
16017	/ 41970 / GIR_RootToRootCopy, /OpIdx/`1`, // in
16018	/ 41972 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
16019	/ 41975 / GIR_RootConstrainSelectedInstOperands,
16020	/ 41976 / // GIR_Coverage, 1963,
16021	/ 41976 / GIR_EraseRootFromParent_Done,
16022	/ 41977 / // Label 1198: @41977
16023	/ 41977 / GIM_Try_CheckFeatures, /On fail goto//Label 1199/ GIMT_Encode4(`42018`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2302 //
16024	/ 41984 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
16025	/ 41988 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPRMM16RegClassID),
16026	/ 41992 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16027	/ 41996 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16028	/ 42000 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16029	/ 42004 / // MIs[1] Operand 1
16030	/ 42004 / // No operand predicates
16031	/ 42004 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16032	/* 42006 / // (srl:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ :[i32] } GPRMM16:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16033	/ 42006 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL16_MM),
16034	/ 42009 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16035	/ 42011 / GIR_RootToRootCopy, /OpIdx/`1`, // src
16036	/ 42013 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
16037	/ 42016 / GIR_RootConstrainSelectedInstOperands,
16038	/ 42017 / // GIR_Coverage, 2302,
16039	/ 42017 / GIR_EraseRootFromParent_Done,
16040	/ 42018 / // Label 1199: @42018
16041	/ 42018 / GIM_Try, /On fail goto//Label 1200/ GIMT_Encode4(`42083`),
16042	/ 42023 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16043	/ 42027 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16044	/ 42031 / GIM_Try_CheckFeatures, /On fail goto//Label 1201/ GIMT_Encode4(`42064`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2303 //
16045	/ 42038 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16046	/ 42042 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16047	/ 42046 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16048	/ 42050 / // MIs[1] Operand 1
16049	/ 42050 / // No operand predicates
16050	/ 42050 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16051	/* 42052 / // (srl:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16052	/ 42052 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_MM),
16053	/ 42055 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16054	/ 42057 / GIR_RootToRootCopy, /OpIdx/`1`, // src
16055	/ 42059 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
16056	/ 42062 / GIR_RootConstrainSelectedInstOperands,
16057	/ 42063 / // GIR_Coverage, 2303,
16058	/ 42063 / GIR_EraseRootFromParent_Done,
16059	/ 42064 / // Label 1201: @42064
16060	/ 42064 / GIM_Try_CheckFeatures, /On fail goto//Label 1202/ GIMT_Encode4(`42082`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 63 //
16061	/ 42071 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16062	/ 42075 / // (srl:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SRLV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
16063	/ 42075 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRLV),
16064	/ 42080 / GIR_RootConstrainSelectedInstOperands,
16065	/ 42081 / // GIR_Coverage, 63,
16066	/ 42081 / GIR_Done,
16067	/ 42082 / // Label 1202: @42082
16068	/ 42082 / GIM_Reject,
16069	/ 42083 / // Label 1200: @42083
16070	/ 42083 / GIM_Try_CheckFeatures, /On fail goto//Label 1203/ GIMT_Encode4(`42109`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1967 //
16071	/ 42090 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16072	/ 42094 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16073	/ 42098 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16074	/ 42102 / // (srl:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra) => (SrlvRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra)
16075	/ 42102 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SrlvRxRy16),
16076	/ 42107 / GIR_RootConstrainSelectedInstOperands,
16077	/ 42108 / // GIR_Coverage, 1967,
16078	/ 42108 / GIR_Done,
16079	/ 42109 / // Label 1203: @42109
16080	/ 42109 / GIM_Try_CheckFeatures, /On fail goto//Label 1204/ GIMT_Encode4(`42135`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2304 //
16081	/ 42116 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16082	/ 42120 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16083	/ 42124 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16084	/ 42128 / // (srl:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs) => (SRLV_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs)
16085	/ 42128 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRLV_MM),
16086	/ 42133 / GIR_RootConstrainSelectedInstOperands,
16087	/ 42134 / // GIR_Coverage, 2304,
16088	/ 42134 / GIR_Done,
16089	/ 42135 / // Label 1204: @42135
16090	/ 42135 / GIM_Reject,
16091	/ 42136 / // Label 1196: @42136
16092	/ 42136 / GIM_Reject,
16093	/ 42137 / // Label 1190: @42137
16094	/ 42137 / GIM_Try, /On fail goto//Label 1205/ GIMT_Encode4(`42274`),
16095	/ 42142 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
16096	/ 42145 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
16097	/ 42148 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16098	/ 42152 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16099	/ 42156 / GIM_Try_CheckFeatures, /On fail goto//Label 1206/ GIMT_Encode4(`42189`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 239 //
16100	/ 42163 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16101	/ 42167 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16102	/ 42171 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16103	/ 42175 / // MIs[1] Operand 1
16104	/ 42175 / // No operand predicates
16105	/ 42175 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16106	/ 42177 / // (srl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$shamt)
16107	/ 42177 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSRL),
16108	/ 42180 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16109	/ 42182 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16110	/ 42184 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
16111	/ 42187 / GIR_RootConstrainSelectedInstOperands,
16112	/ 42188 / // GIR_Coverage, 239,
16113	/ 42188 / GIR_EraseRootFromParent_Done,
16114	/ 42189 / // Label 1206: @42189
16115	/ 42189 / GIM_Try_CheckFeatures, /On fail goto//Label 1207/ GIMT_Encode4(`42255`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1680 //
16116	/ 42196 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16117	/ 42200 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_TRUNC),
16118	/ 42204 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
16119	/ 42208 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16120	/ 42213 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16121	/* 42215 / // (srl:{ :[i64] } GPR64:{ :[i64] }:$rt, (trunc:{ :[i32] } GPR64:{ :[i64] }:$rs)) => (DSRLV:{ :[i64] } GPR64:{ :[i64] }:$rt, (EXTRACT_SUBREG:{ :[i32] } GPR64:{ :[i64] }:$rs, sub_32:{ :[i32] }))
16122	/ 42215 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
16123	/ 42218 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
16124	/ 42222 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16125	/ 42227 / GIR_CopySubReg, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`1`, /SubRegIdx/GIMT_Encode2(`1`), // rs
16126	/ 42233 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
16127	/ 42238 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
16128	/ 42243 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSRLV),
16129	/ 42246 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16130	/ 42248 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16131	/ 42250 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
16132	/ 42253 / GIR_RootConstrainSelectedInstOperands,
16133	/ 42254 / // GIR_Coverage, 1680,
16134	/ 42254 / GIR_EraseRootFromParent_Done,
16135	/ 42255 / // Label 1207: @42255
16136	/ 42255 / GIM_Try_CheckFeatures, /On fail goto//Label 1208/ GIMT_Encode4(`42273`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 247 //
16137	/ 42262 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16138	/ 42266 / // (srl:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (DSRLV:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
16139	/ 42266 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DSRLV),
16140	/ 42271 / GIR_RootConstrainSelectedInstOperands,
16141	/ 42272 / // GIR_Coverage, 247,
16142	/ 42272 / GIR_Done,
16143	/ 42273 / // Label 1208: @42273
16144	/ 42273 / GIM_Reject,
16145	/ 42274 / // Label 1205: @42274
16146	/ 42274 / GIM_Reject,
16147	/ 42275 / // Label 1191: @42275
16148	/ 42275 / GIM_Try, /On fail goto//Label 1209/ GIMT_Encode4(`42923`),
16149	/ 42280 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
16150	/ 42283 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
16151	/ 42286 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
16152	/ 42290 / GIM_Try_CheckFeatures, /On fail goto//Label 1210/ GIMT_Encode4(`42595`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2649 //
16153	/ 42297 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16154	/ 42301 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16155	/ 42305 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
16156	/ 42309 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
16157	/ 42313 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
16158	/ 42317 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16159	/ 42321 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
16160	/ 42324 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16161	/ 42328 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16162	/ 42332 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16163	/ 42336 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16164	/ 42340 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16165	/ 42344 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16166	/ 42348 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16167	/ 42352 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16168	/ 42356 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
16169	/ 42360 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
16170	/ 42364 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
16171	/ 42368 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
16172	/ 42372 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
16173	/ 42376 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
16174	/ 42380 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
16175	/ 42384 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
16176	/ 42388 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16177	/ 42392 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16178	/ 42396 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16179	/ 42400 / // MIs[3] Operand 1
16180	/ 42400 / // No operand predicates
16181	/ 42400 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16182	/ 42404 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16183	/ 42408 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16184	/ 42412 / // MIs[4] Operand 1
16185	/ 42412 / // No operand predicates
16186	/ 42412 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16187	/ 42416 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16188	/ 42420 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16189	/ 42424 / // MIs[5] Operand 1
16190	/ 42424 / // No operand predicates
16191	/ 42424 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16192	/ 42428 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16193	/ 42432 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16194	/ 42436 / // MIs[6] Operand 1
16195	/ 42436 / // No operand predicates
16196	/ 42436 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16197	/ 42440 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16198	/ 42444 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16199	/ 42448 / // MIs[7] Operand 1
16200	/ 42448 / // No operand predicates
16201	/ 42448 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16202	/ 42452 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16203	/ 42456 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16204	/ 42460 / // MIs[8] Operand 1
16205	/ 42460 / // No operand predicates
16206	/ 42460 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16207	/ 42464 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16208	/ 42468 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16209	/ 42472 / // MIs[9] Operand 1
16210	/ 42472 / // No operand predicates
16211	/ 42472 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16212	/ 42476 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16213	/ 42480 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16214	/ 42484 / // MIs[10] Operand 1
16215	/ 42484 / // No operand predicates
16216	/ 42484 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
16217	/ 42488 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16218	/ 42492 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16219	/ 42496 / // MIs[11] Operand 1
16220	/ 42496 / // No operand predicates
16221	/ 42496 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
16222	/ 42500 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16223	/ 42504 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16224	/ 42508 / // MIs[12] Operand 1
16225	/ 42508 / // No operand predicates
16226	/ 42508 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
16227	/ 42512 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16228	/ 42516 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16229	/ 42520 / // MIs[13] Operand 1
16230	/ 42520 / // No operand predicates
16231	/ 42520 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
16232	/ 42524 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16233	/ 42528 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16234	/ 42532 / // MIs[14] Operand 1
16235	/ 42532 / // No operand predicates
16236	/ 42532 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
16237	/ 42536 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16238	/ 42540 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16239	/ 42544 / // MIs[15] Operand 1
16240	/ 42544 / // No operand predicates
16241	/ 42544 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
16242	/ 42548 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16243	/ 42552 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16244	/ 42556 / // MIs[16] Operand 1
16245	/ 42556 / // No operand predicates
16246	/ 42556 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
16247	/ 42560 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16248	/ 42564 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16249	/ 42568 / // MIs[17] Operand 1
16250	/ 42568 / // No operand predicates
16251	/ 42568 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
16252	/ 42572 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16253	/ 42576 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16254	/ 42580 / // MIs[18] Operand 1
16255	/ 42580 / // No operand predicates
16256	/ 42580 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
16257	/* 42582 / // (srl:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ :[v16i8] }:$wt)) => (SRL_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16258	/ 42582 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_B),
16259	/ 42585 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16260	/ 42587 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16261	/ 42589 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
16262	/ 42593 / GIR_RootConstrainSelectedInstOperands,
16263	/ 42594 / // GIR_Coverage, 2649,
16264	/ 42594 / GIR_EraseRootFromParent_Done,
16265	/ 42595 / // Label 1210: @42595
16266	/ 42595 / GIM_Try_CheckFeatures, /On fail goto//Label 1211/ GIMT_Encode4(`42900`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2206 //
16267	/ 42602 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16268	/ 42606 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16269	/ 42610 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
16270	/ 42614 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
16271	/ 42618 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
16272	/ 42622 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16273	/ 42626 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
16274	/ 42629 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16275	/ 42633 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16276	/ 42637 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16277	/ 42641 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16278	/ 42645 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16279	/ 42649 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16280	/ 42653 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16281	/ 42657 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16282	/ 42661 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
16283	/ 42665 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
16284	/ 42669 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
16285	/ 42673 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
16286	/ 42677 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
16287	/ 42681 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
16288	/ 42685 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
16289	/ 42689 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
16290	/ 42693 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16291	/ 42697 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16292	/ 42701 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16293	/ 42705 / // MIs[3] Operand 1
16294	/ 42705 / // No operand predicates
16295	/ 42705 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16296	/ 42709 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16297	/ 42713 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16298	/ 42717 / // MIs[4] Operand 1
16299	/ 42717 / // No operand predicates
16300	/ 42717 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16301	/ 42721 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16302	/ 42725 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16303	/ 42729 / // MIs[5] Operand 1
16304	/ 42729 / // No operand predicates
16305	/ 42729 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16306	/ 42733 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16307	/ 42737 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16308	/ 42741 / // MIs[6] Operand 1
16309	/ 42741 / // No operand predicates
16310	/ 42741 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16311	/ 42745 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16312	/ 42749 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16313	/ 42753 / // MIs[7] Operand 1
16314	/ 42753 / // No operand predicates
16315	/ 42753 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16316	/ 42757 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16317	/ 42761 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16318	/ 42765 / // MIs[8] Operand 1
16319	/ 42765 / // No operand predicates
16320	/ 42765 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16321	/ 42769 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16322	/ 42773 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16323	/ 42777 / // MIs[9] Operand 1
16324	/ 42777 / // No operand predicates
16325	/ 42777 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16326	/ 42781 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16327	/ 42785 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16328	/ 42789 / // MIs[10] Operand 1
16329	/ 42789 / // No operand predicates
16330	/ 42789 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
16331	/ 42793 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16332	/ 42797 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16333	/ 42801 / // MIs[11] Operand 1
16334	/ 42801 / // No operand predicates
16335	/ 42801 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
16336	/ 42805 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16337	/ 42809 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16338	/ 42813 / // MIs[12] Operand 1
16339	/ 42813 / // No operand predicates
16340	/ 42813 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
16341	/ 42817 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16342	/ 42821 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16343	/ 42825 / // MIs[13] Operand 1
16344	/ 42825 / // No operand predicates
16345	/ 42825 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
16346	/ 42829 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16347	/ 42833 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16348	/ 42837 / // MIs[14] Operand 1
16349	/ 42837 / // No operand predicates
16350	/ 42837 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
16351	/ 42841 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16352	/ 42845 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16353	/ 42849 / // MIs[15] Operand 1
16354	/ 42849 / // No operand predicates
16355	/ 42849 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
16356	/ 42853 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16357	/ 42857 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16358	/ 42861 / // MIs[16] Operand 1
16359	/ 42861 / // No operand predicates
16360	/ 42861 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
16361	/ 42865 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16362	/ 42869 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16363	/ 42873 / // MIs[17] Operand 1
16364	/ 42873 / // No operand predicates
16365	/ 42873 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
16366	/ 42877 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16367	/ 42881 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16368	/ 42885 / // MIs[18] Operand 1
16369	/ 42885 / // No operand predicates
16370	/ 42885 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
16371	/* 42887 / // (srl:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } v16i8:{ :[v16i8] }:$wt, (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16372	/ 42887 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_B),
16373	/ 42890 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16374	/ 42892 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16375	/ 42894 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
16376	/ 42898 / GIR_RootConstrainSelectedInstOperands,
16377	/ 42899 / // GIR_Coverage, 2206,
16378	/ 42899 / GIR_EraseRootFromParent_Done,
16379	/ 42900 / // Label 1211: @42900
16380	/ 42900 / GIM_Try_CheckFeatures, /On fail goto//Label 1212/ GIMT_Encode4(`42922`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1016 //
16381	/ 42907 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
16382	/ 42911 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
16383	/ 42915 / // (srl:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SRL_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
16384	/ 42915 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRL_B),
16385	/ 42920 / GIR_RootConstrainSelectedInstOperands,
16386	/ 42921 / // GIR_Coverage, 1016,
16387	/ 42921 / GIR_Done,
16388	/ 42922 / // Label 1212: @42922
16389	/ 42922 / GIM_Reject,
16390	/ 42923 / // Label 1209: @42923
16391	/ 42923 / GIM_Reject,
16392	/ 42924 / // Label 1192: @42924
16393	/ 42924 / GIM_Try, /On fail goto//Label 1213/ GIMT_Encode4(`43316`),
16394	/ 42929 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
16395	/ 42932 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
16396	/ 42935 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
16397	/ 42939 / GIM_Try_CheckFeatures, /On fail goto//Label 1214/ GIMT_Encode4(`43116`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2650 //
16398	/ 42946 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16399	/ 42950 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16400	/ 42954 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
16401	/ 42958 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
16402	/ 42962 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
16403	/ 42966 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16404	/ 42970 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
16405	/ 42973 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16406	/ 42977 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16407	/ 42981 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16408	/ 42985 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16409	/ 42989 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16410	/ 42993 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16411	/ 42997 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16412	/ 43001 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16413	/ 43005 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16414	/ 43009 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16415	/ 43013 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16416	/ 43017 / // MIs[3] Operand 1
16417	/ 43017 / // No operand predicates
16418	/ 43017 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16419	/ 43021 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16420	/ 43025 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16421	/ 43029 / // MIs[4] Operand 1
16422	/ 43029 / // No operand predicates
16423	/ 43029 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16424	/ 43033 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16425	/ 43037 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16426	/ 43041 / // MIs[5] Operand 1
16427	/ 43041 / // No operand predicates
16428	/ 43041 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16429	/ 43045 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16430	/ 43049 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16431	/ 43053 / // MIs[6] Operand 1
16432	/ 43053 / // No operand predicates
16433	/ 43053 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16434	/ 43057 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16435	/ 43061 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16436	/ 43065 / // MIs[7] Operand 1
16437	/ 43065 / // No operand predicates
16438	/ 43065 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16439	/ 43069 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16440	/ 43073 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16441	/ 43077 / // MIs[8] Operand 1
16442	/ 43077 / // No operand predicates
16443	/ 43077 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16444	/ 43081 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16445	/ 43085 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16446	/ 43089 / // MIs[9] Operand 1
16447	/ 43089 / // No operand predicates
16448	/ 43089 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16449	/ 43093 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16450	/ 43097 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16451	/ 43101 / // MIs[10] Operand 1
16452	/ 43101 / // No operand predicates
16453	/ 43101 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
16454	/* 43103 / // (srl:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ :[v8i16] }:$wt)) => (SRL_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16455	/ 43103 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_H),
16456	/ 43106 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16457	/ 43108 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16458	/ 43110 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
16459	/ 43114 / GIR_RootConstrainSelectedInstOperands,
16460	/ 43115 / // GIR_Coverage, 2650,
16461	/ 43115 / GIR_EraseRootFromParent_Done,
16462	/ 43116 / // Label 1214: @43116
16463	/ 43116 / GIM_Try_CheckFeatures, /On fail goto//Label 1215/ GIMT_Encode4(`43293`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2207 //
16464	/ 43123 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16465	/ 43127 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16466	/ 43131 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
16467	/ 43135 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
16468	/ 43139 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
16469	/ 43143 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16470	/ 43147 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
16471	/ 43150 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16472	/ 43154 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16473	/ 43158 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16474	/ 43162 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16475	/ 43166 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16476	/ 43170 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16477	/ 43174 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16478	/ 43178 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16479	/ 43182 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16480	/ 43186 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16481	/ 43190 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16482	/ 43194 / // MIs[3] Operand 1
16483	/ 43194 / // No operand predicates
16484	/ 43194 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16485	/ 43198 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16486	/ 43202 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16487	/ 43206 / // MIs[4] Operand 1
16488	/ 43206 / // No operand predicates
16489	/ 43206 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16490	/ 43210 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16491	/ 43214 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16492	/ 43218 / // MIs[5] Operand 1
16493	/ 43218 / // No operand predicates
16494	/ 43218 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16495	/ 43222 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16496	/ 43226 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16497	/ 43230 / // MIs[6] Operand 1
16498	/ 43230 / // No operand predicates
16499	/ 43230 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16500	/ 43234 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16501	/ 43238 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16502	/ 43242 / // MIs[7] Operand 1
16503	/ 43242 / // No operand predicates
16504	/ 43242 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16505	/ 43246 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16506	/ 43250 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16507	/ 43254 / // MIs[8] Operand 1
16508	/ 43254 / // No operand predicates
16509	/ 43254 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16510	/ 43258 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16511	/ 43262 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16512	/ 43266 / // MIs[9] Operand 1
16513	/ 43266 / // No operand predicates
16514	/ 43266 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16515	/ 43270 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16516	/ 43274 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16517	/ 43278 / // MIs[10] Operand 1
16518	/ 43278 / // No operand predicates
16519	/ 43278 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
16520	/* 43280 / // (srl:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } v8i16:{ :[v8i16] }:$wt, (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16521	/ 43280 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_H),
16522	/ 43283 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16523	/ 43285 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16524	/ 43287 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
16525	/ 43291 / GIR_RootConstrainSelectedInstOperands,
16526	/ 43292 / // GIR_Coverage, 2207,
16527	/ 43292 / GIR_EraseRootFromParent_Done,
16528	/ 43293 / // Label 1215: @43293
16529	/ 43293 / GIM_Try_CheckFeatures, /On fail goto//Label 1216/ GIMT_Encode4(`43315`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1017 //
16530	/ 43300 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
16531	/ 43304 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
16532	/ 43308 / // (srl:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SRL_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
16533	/ 43308 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRL_H),
16534	/ 43313 / GIR_RootConstrainSelectedInstOperands,
16535	/ 43314 / // GIR_Coverage, 1017,
16536	/ 43314 / GIR_Done,
16537	/ 43315 / // Label 1216: @43315
16538	/ 43315 / GIM_Reject,
16539	/ 43316 / // Label 1213: @43316
16540	/ 43316 / GIM_Reject,
16541	/ 43317 / // Label 1193: @43317
16542	/ 43317 / GIM_Try, /On fail goto//Label 1217/ GIMT_Encode4(`43581`),
16543	/ 43322 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
16544	/ 43325 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
16545	/ 43328 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
16546	/ 43332 / GIM_Try_CheckFeatures, /On fail goto//Label 1218/ GIMT_Encode4(`43445`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2651 //
16547	/ 43339 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16548	/ 43343 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16549	/ 43347 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
16550	/ 43351 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
16551	/ 43355 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
16552	/ 43359 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16553	/ 43363 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
16554	/ 43366 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16555	/ 43370 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16556	/ 43374 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16557	/ 43378 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16558	/ 43382 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16559	/ 43386 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16560	/ 43390 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16561	/ 43394 / // MIs[3] Operand 1
16562	/ 43394 / // No operand predicates
16563	/ 43394 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16564	/ 43398 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16565	/ 43402 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16566	/ 43406 / // MIs[4] Operand 1
16567	/ 43406 / // No operand predicates
16568	/ 43406 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16569	/ 43410 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16570	/ 43414 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16571	/ 43418 / // MIs[5] Operand 1
16572	/ 43418 / // No operand predicates
16573	/ 43418 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16574	/ 43422 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16575	/ 43426 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16576	/ 43430 / // MIs[6] Operand 1
16577	/ 43430 / // No operand predicates
16578	/ 43430 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
16579	/* 43432 / // (srl:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ :[v4i32] }:$wt)) => (SRL_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16580	/ 43432 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_W),
16581	/ 43435 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16582	/ 43437 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16583	/ 43439 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
16584	/ 43443 / GIR_RootConstrainSelectedInstOperands,
16585	/ 43444 / // GIR_Coverage, 2651,
16586	/ 43444 / GIR_EraseRootFromParent_Done,
16587	/ 43445 / // Label 1218: @43445
16588	/ 43445 / GIM_Try_CheckFeatures, /On fail goto//Label 1219/ GIMT_Encode4(`43558`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2208 //
16589	/ 43452 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16590	/ 43456 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16591	/ 43460 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
16592	/ 43464 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
16593	/ 43468 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
16594	/ 43472 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16595	/ 43476 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
16596	/ 43479 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16597	/ 43483 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16598	/ 43487 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16599	/ 43491 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16600	/ 43495 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16601	/ 43499 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16602	/ 43503 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16603	/ 43507 / // MIs[3] Operand 1
16604	/ 43507 / // No operand predicates
16605	/ 43507 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16606	/ 43511 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16607	/ 43515 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16608	/ 43519 / // MIs[4] Operand 1
16609	/ 43519 / // No operand predicates
16610	/ 43519 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16611	/ 43523 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16612	/ 43527 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16613	/ 43531 / // MIs[5] Operand 1
16614	/ 43531 / // No operand predicates
16615	/ 43531 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16616	/ 43535 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16617	/ 43539 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16618	/ 43543 / // MIs[6] Operand 1
16619	/ 43543 / // No operand predicates
16620	/ 43543 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
16621	/* 43545 / // (srl:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } v4i32:{ :[v4i32] }:$wt, (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16622	/ 43545 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRL_W),
16623	/ 43548 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16624	/ 43550 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16625	/ 43552 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
16626	/ 43556 / GIR_RootConstrainSelectedInstOperands,
16627	/ 43557 / // GIR_Coverage, 2208,
16628	/ 43557 / GIR_EraseRootFromParent_Done,
16629	/ 43558 / // Label 1219: @43558
16630	/ 43558 / GIM_Try_CheckFeatures, /On fail goto//Label 1220/ GIMT_Encode4(`43580`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1018 //
16631	/ 43565 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
16632	/ 43569 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
16633	/ 43573 / // (srl:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SRL_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
16634	/ 43573 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRL_W),
16635	/ 43578 / GIR_RootConstrainSelectedInstOperands,
16636	/ 43579 / // GIR_Coverage, 1018,
16637	/ 43579 / GIR_Done,
16638	/ 43580 / // Label 1220: @43580
16639	/ 43580 / GIM_Reject,
16640	/ 43581 / // Label 1217: @43581
16641	/ 43581 / GIM_Reject,
16642	/ 43582 / // Label 1194: @43582
16643	/ 43582 / GIM_Try_CheckFeatures, /On fail goto//Label 1221/ GIMT_Encode4(`43614`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1019 //
16644	/ 43589 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
16645	/ 43592 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
16646	/ 43595 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
16647	/ 43599 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
16648	/ 43603 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
16649	/ 43607 / // (srl:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SRL_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
16650	/ 43607 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRL_D),
16651	/ 43612 / GIR_RootConstrainSelectedInstOperands,
16652	/ 43613 / // GIR_Coverage, 1019,
16653	/ 43613 / GIR_Done,
16654	/ 43614 / // Label 1221: @43614
16655	/ 43614 / GIM_Reject,
16656	/ 43615 / // Label 1195: @43615
16657	/ 43615 / GIM_Reject,
16658	/ 43616 / // Label 39: @43616
16659	/ 43616 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1228/ GIMT_Encode4(`45349`),
16660	/ 43627 / /GILLT_s32//Label 1222/ GIMT_Encode4(`43659`),
16661	/ 43631 / /GILLT_s64//Label 1223/ GIMT_Encode4(`43871`), GIMT_Encode4(`0`),
16662	/ 43639 / /GILLT_v16s8//Label 1224/ GIMT_Encode4(`44009`), GIMT_Encode4(`0`),
16663	/ 43647 / /GILLT_v8s16//Label 1225/ GIMT_Encode4(`44658`),
16664	/ 43651 / /GILLT_v4s32//Label 1226/ GIMT_Encode4(`45051`),
16665	/ 43655 / /GILLT_v2s64//Label 1227/ GIMT_Encode4(`45316`),
16666	/ 43659 / // Label 1222: @43659
16667	/ 43659 / GIM_Try, /On fail goto//Label 1229/ GIMT_Encode4(`43870`),
16668	/ 43664 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
16669	/ 43667 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
16670	/ 43670 / GIM_Try_CheckFeatures, /On fail goto//Label 1230/ GIMT_Encode4(`43711`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 59 //
16671	/ 43677 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16672	/ 43681 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16673	/ 43685 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16674	/ 43689 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16675	/ 43693 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16676	/ 43697 / // MIs[1] Operand 1
16677	/ 43697 / // No operand predicates
16678	/ 43697 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16679	/ 43699 / // (sra:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$shamt)
16680	/ 43699 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA),
16681	/ 43702 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16682	/ 43704 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16683	/ 43706 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
16684	/ 43709 / GIR_RootConstrainSelectedInstOperands,
16685	/ 43710 / // GIR_Coverage, 59,
16686	/ 43710 / GIR_EraseRootFromParent_Done,
16687	/ 43711 / // Label 1230: @43711
16688	/ 43711 / GIM_Try_CheckFeatures, /On fail goto//Label 1231/ GIMT_Encode4(`43752`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1964 //
16689	/ 43718 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16690	/ 43722 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16691	/ 43726 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16692	/ 43730 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16693	/ 43734 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16694	/ 43738 / // MIs[1] Operand 1
16695	/ 43738 / // No operand predicates
16696	/ 43738 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16697	/* 43740 / // (sra:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ :[i32] } CPU16Regs:{ :[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16698	/ 43740 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SraX16),
16699	/ 43743 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rx]
16700	/ 43745 / GIR_RootToRootCopy, /OpIdx/`1`, // in
16701	/ 43747 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
16702	/ 43750 / GIR_RootConstrainSelectedInstOperands,
16703	/ 43751 / // GIR_Coverage, 1964,
16704	/ 43751 / GIR_EraseRootFromParent_Done,
16705	/ 43752 / // Label 1231: @43752
16706	/ 43752 / GIM_Try, /On fail goto//Label 1232/ GIMT_Encode4(`43817`),
16707	/ 43757 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16708	/ 43761 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16709	/ 43765 / GIM_Try_CheckFeatures, /On fail goto//Label 1233/ GIMT_Encode4(`43798`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2305 //
16710	/ 43772 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16711	/ 43776 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16712	/ 43780 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16713	/ 43784 / // MIs[1] Operand 1
16714	/ 43784 / // No operand predicates
16715	/ 43784 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16716	/* 43786 / // (sra:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ :[i32] } GPR32:{ :[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16717	/ 43786 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_MM),
16718	/ 43789 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16719	/ 43791 / GIR_RootToRootCopy, /OpIdx/`1`, // src
16720	/ 43793 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // imm
16721	/ 43796 / GIR_RootConstrainSelectedInstOperands,
16722	/ 43797 / // GIR_Coverage, 2305,
16723	/ 43797 / GIR_EraseRootFromParent_Done,
16724	/ 43798 / // Label 1233: @43798
16725	/ 43798 / GIM_Try_CheckFeatures, /On fail goto//Label 1234/ GIMT_Encode4(`43816`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 65 //
16726	/ 43805 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16727	/ 43809 / // (sra:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (SRAV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
16728	/ 43809 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRAV),
16729	/ 43814 / GIR_RootConstrainSelectedInstOperands,
16730	/ 43815 / // GIR_Coverage, 65,
16731	/ 43815 / GIR_Done,
16732	/ 43816 / // Label 1234: @43816
16733	/ 43816 / GIM_Reject,
16734	/ 43817 / // Label 1232: @43817
16735	/ 43817 / GIM_Try_CheckFeatures, /On fail goto//Label 1235/ GIMT_Encode4(`43843`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1966 //
16736	/ 43824 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16737	/ 43828 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16738	/ 43832 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16739	/ 43836 / // (sra:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra) => (SravRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$r, CPU16Regs:{ :[i32] }:$ra)
16740	/ 43836 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SravRxRy16),
16741	/ 43841 / GIR_RootConstrainSelectedInstOperands,
16742	/ 43842 / // GIR_Coverage, 1966,
16743	/ 43842 / GIR_Done,
16744	/ 43843 / // Label 1235: @43843
16745	/ 43843 / GIM_Try_CheckFeatures, /On fail goto//Label 1236/ GIMT_Encode4(`43869`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2306 //
16746	/ 43850 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16747	/ 43854 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16748	/ 43858 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16749	/ 43862 / // (sra:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs) => (SRAV_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs)
16750	/ 43862 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRAV_MM),
16751	/ 43867 / GIR_RootConstrainSelectedInstOperands,
16752	/ 43868 / // GIR_Coverage, 2306,
16753	/ 43868 / GIR_Done,
16754	/ 43869 / // Label 1236: @43869
16755	/ 43869 / GIM_Reject,
16756	/ 43870 / // Label 1229: @43870
16757	/ 43870 / GIM_Reject,
16758	/ 43871 / // Label 1223: @43871
16759	/ 43871 / GIM_Try, /On fail goto//Label 1237/ GIMT_Encode4(`44008`),
16760	/ 43876 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
16761	/ 43879 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
16762	/ 43882 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16763	/ 43886 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16764	/ 43890 / GIM_Try_CheckFeatures, /On fail goto//Label 1238/ GIMT_Encode4(`43923`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 241 //
16765	/ 43897 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16766	/ 43901 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16767	/ 43905 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16768	/ 43909 / // MIs[1] Operand 1
16769	/ 43909 / // No operand predicates
16770	/ 43909 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16771	/ 43911 / // (sra:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$shamt)
16772	/ 43911 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSRA),
16773	/ 43914 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16774	/ 43916 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16775	/ 43918 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
16776	/ 43921 / GIR_RootConstrainSelectedInstOperands,
16777	/ 43922 / // GIR_Coverage, 241,
16778	/ 43922 / GIR_EraseRootFromParent_Done,
16779	/ 43923 / // Label 1238: @43923
16780	/ 43923 / GIM_Try_CheckFeatures, /On fail goto//Label 1239/ GIMT_Encode4(`43989`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1681 //
16781	/ 43930 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16782	/ 43934 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_TRUNC),
16783	/ 43938 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
16784	/ 43942 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
16785	/ 43947 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
16786	/* 43949 / // (sra:{ :[i64] } GPR64:{ :[i64] }:$rt, (trunc:{ :[i32] } GPR64:{ :[i64] }:$rs)) => (DSRAV:{ :[i64] } GPR64:{ :[i64] }:$rt, (EXTRACT_SUBREG:{ :[i32] } GPR64:{ :[i64] }:$rs, sub_32:{ :[i32] }))
16787	/ 43949 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
16788	/ 43952 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
16789	/ 43956 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16790	/ 43961 / GIR_CopySubReg, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`1`, /SubRegIdx/GIMT_Encode2(`1`), // rs
16791	/ 43967 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
16792	/ 43972 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
16793	/ 43977 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSRAV),
16794	/ 43980 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
16795	/ 43982 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
16796	/ 43984 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
16797	/ 43987 / GIR_RootConstrainSelectedInstOperands,
16798	/ 43988 / // GIR_Coverage, 1681,
16799	/ 43988 / GIR_EraseRootFromParent_Done,
16800	/ 43989 / // Label 1239: @43989
16801	/ 43989 / GIM_Try_CheckFeatures, /On fail goto//Label 1240/ GIMT_Encode4(`44007`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 245 //
16802	/ 43996 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
16803	/ 44000 / // (sra:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (DSRAV:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
16804	/ 44000 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DSRAV),
16805	/ 44005 / GIR_RootConstrainSelectedInstOperands,
16806	/ 44006 / // GIR_Coverage, 245,
16807	/ 44006 / GIR_Done,
16808	/ 44007 / // Label 1240: @44007
16809	/ 44007 / GIM_Reject,
16810	/ 44008 / // Label 1237: @44008
16811	/ 44008 / GIM_Reject,
16812	/ 44009 / // Label 1224: @44009
16813	/ 44009 / GIM_Try, /On fail goto//Label 1241/ GIMT_Encode4(`44657`),
16814	/ 44014 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
16815	/ 44017 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
16816	/ 44020 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
16817	/ 44024 / GIM_Try_CheckFeatures, /On fail goto//Label 1242/ GIMT_Encode4(`44329`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2653 //
16818	/ 44031 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16819	/ 44035 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16820	/ 44039 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
16821	/ 44043 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
16822	/ 44047 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
16823	/ 44051 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16824	/ 44055 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
16825	/ 44058 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16826	/ 44062 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16827	/ 44066 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16828	/ 44070 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16829	/ 44074 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16830	/ 44078 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16831	/ 44082 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16832	/ 44086 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16833	/ 44090 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
16834	/ 44094 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
16835	/ 44098 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
16836	/ 44102 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
16837	/ 44106 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
16838	/ 44110 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
16839	/ 44114 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
16840	/ 44118 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
16841	/ 44122 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16842	/ 44126 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16843	/ 44130 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16844	/ 44134 / // MIs[3] Operand 1
16845	/ 44134 / // No operand predicates
16846	/ 44134 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16847	/ 44138 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16848	/ 44142 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16849	/ 44146 / // MIs[4] Operand 1
16850	/ 44146 / // No operand predicates
16851	/ 44146 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16852	/ 44150 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16853	/ 44154 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16854	/ 44158 / // MIs[5] Operand 1
16855	/ 44158 / // No operand predicates
16856	/ 44158 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16857	/ 44162 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16858	/ 44166 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16859	/ 44170 / // MIs[6] Operand 1
16860	/ 44170 / // No operand predicates
16861	/ 44170 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16862	/ 44174 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16863	/ 44178 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16864	/ 44182 / // MIs[7] Operand 1
16865	/ 44182 / // No operand predicates
16866	/ 44182 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16867	/ 44186 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16868	/ 44190 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16869	/ 44194 / // MIs[8] Operand 1
16870	/ 44194 / // No operand predicates
16871	/ 44194 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16872	/ 44198 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16873	/ 44202 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16874	/ 44206 / // MIs[9] Operand 1
16875	/ 44206 / // No operand predicates
16876	/ 44206 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16877	/ 44210 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16878	/ 44214 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16879	/ 44218 / // MIs[10] Operand 1
16880	/ 44218 / // No operand predicates
16881	/ 44218 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
16882	/ 44222 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16883	/ 44226 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16884	/ 44230 / // MIs[11] Operand 1
16885	/ 44230 / // No operand predicates
16886	/ 44230 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
16887	/ 44234 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16888	/ 44238 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16889	/ 44242 / // MIs[12] Operand 1
16890	/ 44242 / // No operand predicates
16891	/ 44242 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
16892	/ 44246 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16893	/ 44250 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16894	/ 44254 / // MIs[13] Operand 1
16895	/ 44254 / // No operand predicates
16896	/ 44254 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
16897	/ 44258 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16898	/ 44262 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16899	/ 44266 / // MIs[14] Operand 1
16900	/ 44266 / // No operand predicates
16901	/ 44266 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
16902	/ 44270 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16903	/ 44274 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16904	/ 44278 / // MIs[15] Operand 1
16905	/ 44278 / // No operand predicates
16906	/ 44278 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
16907	/ 44282 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16908	/ 44286 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16909	/ 44290 / // MIs[16] Operand 1
16910	/ 44290 / // No operand predicates
16911	/ 44290 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
16912	/ 44294 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16913	/ 44298 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16914	/ 44302 / // MIs[17] Operand 1
16915	/ 44302 / // No operand predicates
16916	/ 44302 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
16917	/ 44306 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16918	/ 44310 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16919	/ 44314 / // MIs[18] Operand 1
16920	/ 44314 / // No operand predicates
16921	/ 44314 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
16922	/* 44316 / // (sra:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ :[v16i8] }:$wt)) => (SRA_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16923	/ 44316 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_B),
16924	/ 44319 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
16925	/ 44321 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
16926	/ 44323 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
16927	/ 44327 / GIR_RootConstrainSelectedInstOperands,
16928	/ 44328 / // GIR_Coverage, 2653,
16929	/ 44328 / GIR_EraseRootFromParent_Done,
16930	/ 44329 / // Label 1242: @44329
16931	/ 44329 / GIM_Try_CheckFeatures, /On fail goto//Label 1243/ GIMT_Encode4(`44634`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2210 //
16932	/ 44336 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
16933	/ 44340 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
16934	/ 44344 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v16s8,
16935	/ 44348 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v16s8,
16936	/ 44352 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
16937	/ 44356 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16938	/ 44360 / GIM_CheckNumOperands, /MI/`2`, /Expected/`17`,
16939	/ 44363 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
16940	/ 44367 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
16941	/ 44371 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
16942	/ 44375 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
16943	/ 44379 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
16944	/ 44383 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
16945	/ 44387 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
16946	/ 44391 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
16947	/ 44395 / GIM_CheckType, /MI/`2`, /Op/`9`, /Type/GILLT_s32,
16948	/ 44399 / GIM_CheckType, /MI/`2`, /Op/`10`, /Type/GILLT_s32,
16949	/ 44403 / GIM_CheckType, /MI/`2`, /Op/`11`, /Type/GILLT_s32,
16950	/ 44407 / GIM_CheckType, /MI/`2`, /Op/`12`, /Type/GILLT_s32,
16951	/ 44411 / GIM_CheckType, /MI/`2`, /Op/`13`, /Type/GILLT_s32,
16952	/ 44415 / GIM_CheckType, /MI/`2`, /Op/`14`, /Type/GILLT_s32,
16953	/ 44419 / GIM_CheckType, /MI/`2`, /Op/`15`, /Type/GILLT_s32,
16954	/ 44423 / GIM_CheckType, /MI/`2`, /Op/`16`, /Type/GILLT_s32,
16955	/ 44427 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
16956	/ 44431 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16957	/ 44435 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16958	/ 44439 / // MIs[3] Operand 1
16959	/ 44439 / // No operand predicates
16960	/ 44439 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
16961	/ 44443 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16962	/ 44447 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16963	/ 44451 / // MIs[4] Operand 1
16964	/ 44451 / // No operand predicates
16965	/ 44451 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
16966	/ 44455 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16967	/ 44459 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16968	/ 44463 / // MIs[5] Operand 1
16969	/ 44463 / // No operand predicates
16970	/ 44463 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
16971	/ 44467 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16972	/ 44471 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16973	/ 44475 / // MIs[6] Operand 1
16974	/ 44475 / // No operand predicates
16975	/ 44475 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
16976	/ 44479 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16977	/ 44483 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16978	/ 44487 / // MIs[7] Operand 1
16979	/ 44487 / // No operand predicates
16980	/ 44487 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
16981	/ 44491 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16982	/ 44495 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16983	/ 44499 / // MIs[8] Operand 1
16984	/ 44499 / // No operand predicates
16985	/ 44499 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
16986	/ 44503 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16987	/ 44507 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16988	/ 44511 / // MIs[9] Operand 1
16989	/ 44511 / // No operand predicates
16990	/ 44511 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
16991	/ 44515 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16992	/ 44519 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16993	/ 44523 / // MIs[10] Operand 1
16994	/ 44523 / // No operand predicates
16995	/ 44523 / GIM_RecordInsn, /DefineMI/`11`, /MI/`2`, /OpIdx/`9`, // MIs[11]
16996	/ 44527 / GIM_CheckOpcode, /MI/`11`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16997	/ 44531 / GIM_CheckI64ImmPredicate, /MI/`11`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16998	/ 44535 / // MIs[11] Operand 1
16999	/ 44535 / // No operand predicates
17000	/ 44535 / GIM_RecordInsn, /DefineMI/`12`, /MI/`2`, /OpIdx/`10`, // MIs[12]
17001	/ 44539 / GIM_CheckOpcode, /MI/`12`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17002	/ 44543 / GIM_CheckI64ImmPredicate, /MI/`12`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17003	/ 44547 / // MIs[12] Operand 1
17004	/ 44547 / // No operand predicates
17005	/ 44547 / GIM_RecordInsn, /DefineMI/`13`, /MI/`2`, /OpIdx/`11`, // MIs[13]
17006	/ 44551 / GIM_CheckOpcode, /MI/`13`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17007	/ 44555 / GIM_CheckI64ImmPredicate, /MI/`13`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17008	/ 44559 / // MIs[13] Operand 1
17009	/ 44559 / // No operand predicates
17010	/ 44559 / GIM_RecordInsn, /DefineMI/`14`, /MI/`2`, /OpIdx/`12`, // MIs[14]
17011	/ 44563 / GIM_CheckOpcode, /MI/`14`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17012	/ 44567 / GIM_CheckI64ImmPredicate, /MI/`14`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17013	/ 44571 / // MIs[14] Operand 1
17014	/ 44571 / // No operand predicates
17015	/ 44571 / GIM_RecordInsn, /DefineMI/`15`, /MI/`2`, /OpIdx/`13`, // MIs[15]
17016	/ 44575 / GIM_CheckOpcode, /MI/`15`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17017	/ 44579 / GIM_CheckI64ImmPredicate, /MI/`15`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17018	/ 44583 / // MIs[15] Operand 1
17019	/ 44583 / // No operand predicates
17020	/ 44583 / GIM_RecordInsn, /DefineMI/`16`, /MI/`2`, /OpIdx/`14`, // MIs[16]
17021	/ 44587 / GIM_CheckOpcode, /MI/`16`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17022	/ 44591 / GIM_CheckI64ImmPredicate, /MI/`16`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17023	/ 44595 / // MIs[16] Operand 1
17024	/ 44595 / // No operand predicates
17025	/ 44595 / GIM_RecordInsn, /DefineMI/`17`, /MI/`2`, /OpIdx/`15`, // MIs[17]
17026	/ 44599 / GIM_CheckOpcode, /MI/`17`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17027	/ 44603 / GIM_CheckI64ImmPredicate, /MI/`17`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17028	/ 44607 / // MIs[17] Operand 1
17029	/ 44607 / // No operand predicates
17030	/ 44607 / GIM_RecordInsn, /DefineMI/`18`, /MI/`2`, /OpIdx/`16`, // MIs[18]
17031	/ 44611 / GIM_CheckOpcode, /MI/`18`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17032	/ 44615 / GIM_CheckI64ImmPredicate, /MI/`18`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17033	/ 44619 / // MIs[18] Operand 1
17034	/ 44619 / // No operand predicates
17035	/ 44619 / GIM_CheckIsSafeToFold, /NumInsns/`18`,
17036	/* 44621 / // (sra:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, (and:{ :[v16i8] } v16i8:{ :[v16i8] }:$wt, (build_vector:{ :[v16i8] } (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ :[v16i8] } v16i8:{ :[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17037	/ 44621 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_B),
17038	/ 44624 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
17039	/ 44626 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
17040	/ 44628 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
17041	/ 44632 / GIR_RootConstrainSelectedInstOperands,
17042	/ 44633 / // GIR_Coverage, 2210,
17043	/ 44633 / GIR_EraseRootFromParent_Done,
17044	/ 44634 / // Label 1243: @44634
17045	/ 44634 / GIM_Try_CheckFeatures, /On fail goto//Label 1244/ GIMT_Encode4(`44656`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1000 //
17046	/ 44641 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
17047	/ 44645 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
17048	/ 44649 / // (sra:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (SRA_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
17049	/ 44649 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRA_B),
17050	/ 44654 / GIR_RootConstrainSelectedInstOperands,
17051	/ 44655 / // GIR_Coverage, 1000,
17052	/ 44655 / GIR_Done,
17053	/ 44656 / // Label 1244: @44656
17054	/ 44656 / GIM_Reject,
17055	/ 44657 / // Label 1241: @44657
17056	/ 44657 / GIM_Reject,
17057	/ 44658 / // Label 1225: @44658
17058	/ 44658 / GIM_Try, /On fail goto//Label 1245/ GIMT_Encode4(`45050`),
17059	/ 44663 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
17060	/ 44666 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
17061	/ 44669 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
17062	/ 44673 / GIM_Try_CheckFeatures, /On fail goto//Label 1246/ GIMT_Encode4(`44850`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2654 //
17063	/ 44680 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17064	/ 44684 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
17065	/ 44688 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
17066	/ 44692 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
17067	/ 44696 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
17068	/ 44700 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17069	/ 44704 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
17070	/ 44707 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
17071	/ 44711 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
17072	/ 44715 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
17073	/ 44719 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
17074	/ 44723 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
17075	/ 44727 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
17076	/ 44731 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
17077	/ 44735 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
17078	/ 44739 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
17079	/ 44743 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17080	/ 44747 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17081	/ 44751 / // MIs[3] Operand 1
17082	/ 44751 / // No operand predicates
17083	/ 44751 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
17084	/ 44755 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17085	/ 44759 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17086	/ 44763 / // MIs[4] Operand 1
17087	/ 44763 / // No operand predicates
17088	/ 44763 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
17089	/ 44767 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17090	/ 44771 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17091	/ 44775 / // MIs[5] Operand 1
17092	/ 44775 / // No operand predicates
17093	/ 44775 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
17094	/ 44779 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17095	/ 44783 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17096	/ 44787 / // MIs[6] Operand 1
17097	/ 44787 / // No operand predicates
17098	/ 44787 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
17099	/ 44791 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17100	/ 44795 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17101	/ 44799 / // MIs[7] Operand 1
17102	/ 44799 / // No operand predicates
17103	/ 44799 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
17104	/ 44803 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17105	/ 44807 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17106	/ 44811 / // MIs[8] Operand 1
17107	/ 44811 / // No operand predicates
17108	/ 44811 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
17109	/ 44815 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17110	/ 44819 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17111	/ 44823 / // MIs[9] Operand 1
17112	/ 44823 / // No operand predicates
17113	/ 44823 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
17114	/ 44827 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17115	/ 44831 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17116	/ 44835 / // MIs[10] Operand 1
17117	/ 44835 / // No operand predicates
17118	/ 44835 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
17119	/* 44837 / // (sra:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ :[v8i16] }:$wt)) => (SRA_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17120	/ 44837 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_H),
17121	/ 44840 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
17122	/ 44842 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
17123	/ 44844 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
17124	/ 44848 / GIR_RootConstrainSelectedInstOperands,
17125	/ 44849 / // GIR_Coverage, 2654,
17126	/ 44849 / GIR_EraseRootFromParent_Done,
17127	/ 44850 / // Label 1246: @44850
17128	/ 44850 / GIM_Try_CheckFeatures, /On fail goto//Label 1247/ GIMT_Encode4(`45027`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2211 //
17129	/ 44857 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17130	/ 44861 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
17131	/ 44865 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v8s16,
17132	/ 44869 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v8s16,
17133	/ 44873 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
17134	/ 44877 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17135	/ 44881 / GIM_CheckNumOperands, /MI/`2`, /Expected/`9`,
17136	/ 44884 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
17137	/ 44888 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
17138	/ 44892 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
17139	/ 44896 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
17140	/ 44900 / GIM_CheckType, /MI/`2`, /Op/`5`, /Type/GILLT_s32,
17141	/ 44904 / GIM_CheckType, /MI/`2`, /Op/`6`, /Type/GILLT_s32,
17142	/ 44908 / GIM_CheckType, /MI/`2`, /Op/`7`, /Type/GILLT_s32,
17143	/ 44912 / GIM_CheckType, /MI/`2`, /Op/`8`, /Type/GILLT_s32,
17144	/ 44916 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
17145	/ 44920 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17146	/ 44924 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17147	/ 44928 / // MIs[3] Operand 1
17148	/ 44928 / // No operand predicates
17149	/ 44928 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
17150	/ 44932 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17151	/ 44936 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17152	/ 44940 / // MIs[4] Operand 1
17153	/ 44940 / // No operand predicates
17154	/ 44940 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
17155	/ 44944 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17156	/ 44948 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17157	/ 44952 / // MIs[5] Operand 1
17158	/ 44952 / // No operand predicates
17159	/ 44952 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
17160	/ 44956 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17161	/ 44960 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17162	/ 44964 / // MIs[6] Operand 1
17163	/ 44964 / // No operand predicates
17164	/ 44964 / GIM_RecordInsn, /DefineMI/`7`, /MI/`2`, /OpIdx/`5`, // MIs[7]
17165	/ 44968 / GIM_CheckOpcode, /MI/`7`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17166	/ 44972 / GIM_CheckI64ImmPredicate, /MI/`7`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17167	/ 44976 / // MIs[7] Operand 1
17168	/ 44976 / // No operand predicates
17169	/ 44976 / GIM_RecordInsn, /DefineMI/`8`, /MI/`2`, /OpIdx/`6`, // MIs[8]
17170	/ 44980 / GIM_CheckOpcode, /MI/`8`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17171	/ 44984 / GIM_CheckI64ImmPredicate, /MI/`8`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17172	/ 44988 / // MIs[8] Operand 1
17173	/ 44988 / // No operand predicates
17174	/ 44988 / GIM_RecordInsn, /DefineMI/`9`, /MI/`2`, /OpIdx/`7`, // MIs[9]
17175	/ 44992 / GIM_CheckOpcode, /MI/`9`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17176	/ 44996 / GIM_CheckI64ImmPredicate, /MI/`9`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17177	/ 45000 / // MIs[9] Operand 1
17178	/ 45000 / // No operand predicates
17179	/ 45000 / GIM_RecordInsn, /DefineMI/`10`, /MI/`2`, /OpIdx/`8`, // MIs[10]
17180	/ 45004 / GIM_CheckOpcode, /MI/`10`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17181	/ 45008 / GIM_CheckI64ImmPredicate, /MI/`10`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17182	/ 45012 / // MIs[10] Operand 1
17183	/ 45012 / // No operand predicates
17184	/ 45012 / GIM_CheckIsSafeToFold, /NumInsns/`10`,
17185	/* 45014 / // (sra:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, (and:{ :[v8i16] } v8i16:{ :[v8i16] }:$wt, (build_vector:{ :[v8i16] } (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ :[v8i16] } v8i16:{ :[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17186	/ 45014 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_H),
17187	/ 45017 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
17188	/ 45019 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
17189	/ 45021 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
17190	/ 45025 / GIR_RootConstrainSelectedInstOperands,
17191	/ 45026 / // GIR_Coverage, 2211,
17192	/ 45026 / GIR_EraseRootFromParent_Done,
17193	/ 45027 / // Label 1247: @45027
17194	/ 45027 / GIM_Try_CheckFeatures, /On fail goto//Label 1248/ GIMT_Encode4(`45049`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1001 //
17195	/ 45034 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
17196	/ 45038 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
17197	/ 45042 / // (sra:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (SRA_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
17198	/ 45042 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRA_H),
17199	/ 45047 / GIR_RootConstrainSelectedInstOperands,
17200	/ 45048 / // GIR_Coverage, 1001,
17201	/ 45048 / GIR_Done,
17202	/ 45049 / // Label 1248: @45049
17203	/ 45049 / GIM_Reject,
17204	/ 45050 / // Label 1245: @45050
17205	/ 45050 / GIM_Reject,
17206	/ 45051 / // Label 1226: @45051
17207	/ 45051 / GIM_Try, /On fail goto//Label 1249/ GIMT_Encode4(`45315`),
17208	/ 45056 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
17209	/ 45059 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
17210	/ 45062 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
17211	/ 45066 / GIM_Try_CheckFeatures, /On fail goto//Label 1250/ GIMT_Encode4(`45179`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2655 //
17212	/ 45073 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17213	/ 45077 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
17214	/ 45081 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
17215	/ 45085 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
17216	/ 45089 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
17217	/ 45093 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17218	/ 45097 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
17219	/ 45100 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
17220	/ 45104 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
17221	/ 45108 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
17222	/ 45112 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
17223	/ 45116 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
17224	/ 45120 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17225	/ 45124 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17226	/ 45128 / // MIs[3] Operand 1
17227	/ 45128 / // No operand predicates
17228	/ 45128 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
17229	/ 45132 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17230	/ 45136 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17231	/ 45140 / // MIs[4] Operand 1
17232	/ 45140 / // No operand predicates
17233	/ 45140 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
17234	/ 45144 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17235	/ 45148 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17236	/ 45152 / // MIs[5] Operand 1
17237	/ 45152 / // No operand predicates
17238	/ 45152 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
17239	/ 45156 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17240	/ 45160 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17241	/ 45164 / // MIs[6] Operand 1
17242	/ 45164 / // No operand predicates
17243	/ 45164 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
17244	/* 45166 / // (sra:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ :[v4i32] }:$wt)) => (SRA_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17245	/ 45166 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_W),
17246	/ 45169 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
17247	/ 45171 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
17248	/ 45173 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
17249	/ 45177 / GIR_RootConstrainSelectedInstOperands,
17250	/ 45178 / // GIR_Coverage, 2655,
17251	/ 45178 / GIR_EraseRootFromParent_Done,
17252	/ 45179 / // Label 1250: @45179
17253	/ 45179 / GIM_Try_CheckFeatures, /On fail goto//Label 1251/ GIMT_Encode4(`45292`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2212 //
17254	/ 45186 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17255	/ 45190 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_AND),
17256	/ 45194 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
17257	/ 45198 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
17258	/ 45202 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`2`, // MIs[2]
17259	/ 45206 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17260	/ 45210 / GIM_CheckNumOperands, /MI/`2`, /Expected/`5`,
17261	/ 45213 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s32,
17262	/ 45217 / GIM_CheckType, /MI/`2`, /Op/`2`, /Type/GILLT_s32,
17263	/ 45221 / GIM_CheckType, /MI/`2`, /Op/`3`, /Type/GILLT_s32,
17264	/ 45225 / GIM_CheckType, /MI/`2`, /Op/`4`, /Type/GILLT_s32,
17265	/ 45229 / GIM_RecordInsn, /DefineMI/`3`, /MI/`2`, /OpIdx/`1`, // MIs[3]
17266	/ 45233 / GIM_CheckOpcode, /MI/`3`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17267	/ 45237 / GIM_CheckI64ImmPredicate, /MI/`3`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17268	/ 45241 / // MIs[3] Operand 1
17269	/ 45241 / // No operand predicates
17270	/ 45241 / GIM_RecordInsn, /DefineMI/`4`, /MI/`2`, /OpIdx/`2`, // MIs[4]
17271	/ 45245 / GIM_CheckOpcode, /MI/`4`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17272	/ 45249 / GIM_CheckI64ImmPredicate, /MI/`4`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17273	/ 45253 / // MIs[4] Operand 1
17274	/ 45253 / // No operand predicates
17275	/ 45253 / GIM_RecordInsn, /DefineMI/`5`, /MI/`2`, /OpIdx/`3`, // MIs[5]
17276	/ 45257 / GIM_CheckOpcode, /MI/`5`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17277	/ 45261 / GIM_CheckI64ImmPredicate, /MI/`5`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17278	/ 45265 / // MIs[5] Operand 1
17279	/ 45265 / // No operand predicates
17280	/ 45265 / GIM_RecordInsn, /DefineMI/`6`, /MI/`2`, /OpIdx/`4`, // MIs[6]
17281	/ 45269 / GIM_CheckOpcode, /MI/`6`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17282	/ 45273 / GIM_CheckI64ImmPredicate, /MI/`6`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17283	/ 45277 / // MIs[6] Operand 1
17284	/ 45277 / // No operand predicates
17285	/ 45277 / GIM_CheckIsSafeToFold, /NumInsns/`6`,
17286	/* 45279 / // (sra:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, (and:{ :[v4i32] } v4i32:{ :[v4i32] }:$wt, (build_vector:{ :[v4i32] } (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ :[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ :[v4i32] } v4i32:{ :[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17287	/ 45279 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SRA_W),
17288	/ 45282 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
17289	/ 45284 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
17290	/ 45286 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
17291	/ 45290 / GIR_RootConstrainSelectedInstOperands,
17292	/ 45291 / // GIR_Coverage, 2212,
17293	/ 45291 / GIR_EraseRootFromParent_Done,
17294	/ 45292 / // Label 1251: @45292
17295	/ 45292 / GIM_Try_CheckFeatures, /On fail goto//Label 1252/ GIMT_Encode4(`45314`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1002 //
17296	/ 45299 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
17297	/ 45303 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
17298	/ 45307 / // (sra:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (SRA_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
17299	/ 45307 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRA_W),
17300	/ 45312 / GIR_RootConstrainSelectedInstOperands,
17301	/ 45313 / // GIR_Coverage, 1002,
17302	/ 45313 / GIR_Done,
17303	/ 45314 / // Label 1252: @45314
17304	/ 45314 / GIM_Reject,
17305	/ 45315 / // Label 1249: @45315
17306	/ 45315 / GIM_Reject,
17307	/ 45316 / // Label 1227: @45316
17308	/ 45316 / GIM_Try_CheckFeatures, /On fail goto//Label 1253/ GIMT_Encode4(`45348`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1003 //
17309	/ 45323 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
17310	/ 45326 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
17311	/ 45329 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
17312	/ 45333 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
17313	/ 45337 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
17314	/ 45341 / // (sra:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (SRA_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
17315	/ 45341 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::SRA_D),
17316	/ 45346 / GIR_RootConstrainSelectedInstOperands,
17317	/ 45347 / // GIR_Coverage, 1003,
17318	/ 45347 / GIR_Done,
17319	/ 45348 / // Label 1253: @45348
17320	/ 45348 / GIM_Reject,
17321	/ 45349 / // Label 1228: @45349
17322	/ 45349 / GIM_Reject,
17323	/ 45350 / // Label 40: @45350
17324	/ 45350 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1256/ GIMT_Encode4(`45632`),
17325	/ 45361 / /GILLT_s32//Label 1254/ GIMT_Encode4(`45369`),
17326	/ 45365 / /GILLT_s64//Label 1255/ GIMT_Encode4(`45494`),
17327	/ 45369 / // Label 1254: @45369
17328	/ 45369 / GIM_Try, /On fail goto//Label 1257/ GIMT_Encode4(`45493`),
17329	/ 45374 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
17330	/ 45377 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
17331	/ 45380 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17332	/ 45384 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17333	/ 45388 / GIM_Try_CheckFeatures, /On fail goto//Label 1258/ GIMT_Encode4(`45421`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 67 //
17334	/ 45395 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17335	/ 45399 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17336	/ 45403 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17337	/ 45407 / // MIs[1] Operand 1
17338	/ 45407 / // No operand predicates
17339	/ 45407 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
17340	/ 45409 / // (rotr:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$shamt)
17341	/ 45409 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ROTR),
17342	/ 45412 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17343	/ 45414 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
17344	/ 45416 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
17345	/ 45419 / GIR_RootConstrainSelectedInstOperands,
17346	/ 45420 / // GIR_Coverage, 67,
17347	/ 45420 / GIR_EraseRootFromParent_Done,
17348	/ 45421 / // Label 1258: @45421
17349	/ 45421 / GIM_Try_CheckFeatures, /On fail goto//Label 1259/ GIMT_Encode4(`45454`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1102 //
17350	/ 45428 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17351	/ 45432 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17352	/ 45436 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17353	/ 45440 / // MIs[1] Operand 1
17354	/ 45440 / // No operand predicates
17355	/ 45440 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
17356	/ 45442 / // (rotr:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, (imm:{ :[i32] }):$shamt)
17357	/ 45442 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ROTR_MM),
17358	/ 45445 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17359	/ 45447 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
17360	/ 45449 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
17361	/ 45452 / GIR_RootConstrainSelectedInstOperands,
17362	/ 45453 / // GIR_Coverage, 1102,
17363	/ 45453 / GIR_EraseRootFromParent_Done,
17364	/ 45454 / // Label 1259: @45454
17365	/ 45454 / GIM_Try, /On fail goto//Label 1260/ GIMT_Encode4(`45492`),
17366	/ 45459 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17367	/ 45463 / GIM_Try_CheckFeatures, /On fail goto//Label 1261/ GIMT_Encode4(`45477`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 68 //
17368	/ 45470 / // (rotr:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (ROTRV:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
17369	/ 45470 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ROTRV),
17370	/ 45475 / GIR_RootConstrainSelectedInstOperands,
17371	/ 45476 / // GIR_Coverage, 68,
17372	/ 45476 / GIR_Done,
17373	/ 45477 / // Label 1261: @45477
17374	/ 45477 / GIM_Try_CheckFeatures, /On fail goto//Label 1262/ GIMT_Encode4(`45491`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1103 //
17375	/ 45484 / // (rotr:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (ROTRV_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
17376	/ 45484 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::ROTRV_MM),
17377	/ 45489 / GIR_RootConstrainSelectedInstOperands,
17378	/ 45490 / // GIR_Coverage, 1103,
17379	/ 45490 / GIR_Done,
17380	/ 45491 / // Label 1262: @45491
17381	/ 45491 / GIM_Reject,
17382	/ 45492 / // Label 1260: @45492
17383	/ 45492 / GIM_Reject,
17384	/ 45493 / // Label 1257: @45493
17385	/ 45493 / GIM_Reject,
17386	/ 45494 / // Label 1255: @45494
17387	/ 45494 / GIM_Try, /On fail goto//Label 1263/ GIMT_Encode4(`45631`),
17388	/ 45499 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
17389	/ 45502 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
17390	/ 45505 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
17391	/ 45509 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
17392	/ 45513 / GIM_Try_CheckFeatures, /On fail goto//Label 1264/ GIMT_Encode4(`45546`), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 249 //
17393	/ 45520 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17394	/ 45524 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17395	/ 45528 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17396	/ 45532 / // MIs[1] Operand 1
17397	/ 45532 / // No operand predicates
17398	/ 45532 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
17399	/ 45534 / // (rotr:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, (imm:{ :[i32] }):$shamt)
17400	/ 45534 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DROTR),
17401	/ 45537 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17402	/ 45539 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
17403	/ 45541 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // shamt
17404	/ 45544 / GIR_RootConstrainSelectedInstOperands,
17405	/ 45545 / // GIR_Coverage, 249,
17406	/ 45545 / GIR_EraseRootFromParent_Done,
17407	/ 45546 / // Label 1264: @45546
17408	/ 45546 / GIM_Try_CheckFeatures, /On fail goto//Label 1265/ GIMT_Encode4(`45612`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1682 //
17409	/ 45553 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17410	/ 45557 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_TRUNC),
17411	/ 45561 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
17412	/ 45565 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
17413	/ 45570 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
17414	/* 45572 / // (rotr:{ :[i64] } GPR64:{ :[i64] }:$rt, (trunc:{ :[i32] } GPR64:{ :[i64] }:$rs)) => (DROTRV:{ :[i64] } GPR64:{ :[i64] }:$rt, (EXTRACT_SUBREG:{ :[i32] } GPR64:{ :[i64] }:$rs, sub_32:{ :[i32] }))
17415	/ 45572 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17416	/ 45575 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
17417	/ 45579 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17418	/ 45584 / GIR_CopySubReg, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`1`, /SubRegIdx/GIMT_Encode2(`1`), // rs
17419	/ 45590 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`0`, GIMT_Encode2(Mips::DSPRRegClassID),
17420	/ 45595 / GIR_ConstrainOperandRC, /InsnID/`1`, /Op/`1`, GIMT_Encode2(Mips::GPR64RegClassID),
17421	/ 45600 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DROTRV),
17422	/ 45603 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17423	/ 45605 / GIR_RootToRootCopy, /OpIdx/`1`, // rt
17424	/ 45607 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17425	/ 45610 / GIR_RootConstrainSelectedInstOperands,
17426	/ 45611 / // GIR_Coverage, 1682,
17427	/ 45611 / GIR_EraseRootFromParent_Done,
17428	/ 45612 / // Label 1265: @45612
17429	/ 45612 / GIM_Try_CheckFeatures, /On fail goto//Label 1266/ GIMT_Encode4(`45630`), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 250 //
17430	/ 45619 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17431	/ 45623 / // (rotr:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs) => (DROTRV:{ :[i64] } GPR64Opnd:{ :[i64] }:$rt, GPR32Opnd:{ :[i32] }:$rs)
17432	/ 45623 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DROTRV),
17433	/ 45628 / GIR_RootConstrainSelectedInstOperands,
17434	/ 45629 / // GIR_Coverage, 250,
17435	/ 45629 / GIR_Done,
17436	/ 45630 / // Label 1266: @45630
17437	/ 45630 / GIM_Reject,
17438	/ 45631 / // Label 1263: @45631
17439	/ 45631 / GIM_Reject,
17440	/ 45632 / // Label 1256: @45632
17441	/ 45632 / GIM_Reject,
17442	/ 45633 / // Label 41: @45633
17443	/ 45633 / GIM_Try, /On fail goto//Label 1267/ GIMT_Encode4(`48126`),
17444	/ 45638 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
17445	/ 45641 / GIM_SwitchType, /MI/`0`, /Op/`2`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1270/ GIMT_Encode4(`48125`),
17446	/ 45652 / /GILLT_s32//Label 1268/ GIMT_Encode4(`45660`),
17447	/ 45656 / /GILLT_s64//Label 1269/ GIMT_Encode4(`47587`),
17448	/ 45660 / // Label 1268: @45660
17449	/ 45660 / GIM_Try, /On fail goto//Label 1271/ GIMT_Encode4(`47586`),
17450	/ 45665 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
17451	/ 45668 / GIM_Try, /On fail goto//Label 1272/ GIMT_Encode4(`45898`),
17452	/ 45673 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17453	/ 45677 / GIM_Try, /On fail goto//Label 1273/ GIMT_Encode4(`45830`),
17454	/ 45682 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
17455	/ 45687 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17456	/ 45691 / GIM_Try_CheckFeatures, /On fail goto//Label 1274/ GIMT_Encode4(`45760`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit), // Rule ID 1520 //
17457	/ 45698 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17458	/ 45702 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_BITCAST),
17459	/ 45706 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
17460	/ 45710 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
17461	/ 45714 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17462	/ 45718 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
17463	/ 45722 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
17464	/ 45727 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
17465	/* 45729 / // (setcc:{ :[i32] } (bitconvert:{ :[i32] } (fpround:{ :[f32] } AFGR64Opnd:{ :[f64] }:$src)), 0:{ :[i32] }, SETLT:{ :[Other] }) => (SLTi:{ :[i32] } (MFHC1_D32:{ :[i32] } AFGR64Opnd:{ :[f64] }:$src), 0:{ *:[i32] })
17466	/ 45729 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17467	/ 45732 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::MFHC1_D32),
17468	/ 45736 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17469	/ 45741 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`2`, /OpIdx/`1`, // src
17470	/ 45745 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17471	/ 45747 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTi),
17472	/ 45750 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17473	/ 45752 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17474	/ 45755 / GIR_AddImm8, /InsnID/`0`, /Imm/`0`,
17475	/ 45758 / GIR_RootConstrainSelectedInstOperands,
17476	/ 45759 / // GIR_Coverage, 1520,
17477	/ 45759 / GIR_EraseRootFromParent_Done,
17478	/ 45760 / // Label 1274: @45760
17479	/ 45760 / GIM_Try_CheckFeatures, /On fail goto//Label 1275/ GIMT_Encode4(`45829`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat), // Rule ID 1521 //
17480	/ 45767 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
17481	/ 45771 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_BITCAST),
17482	/ 45775 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
17483	/ 45779 / GIM_RecordInsn, /DefineMI/`2`, /MI/`1`, /OpIdx/`1`, // MIs[2]
17484	/ 45783 / GIM_CheckOpcode, /MI/`2`, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17485	/ 45787 / GIM_CheckType, /MI/`2`, /Op/`1`, /Type/GILLT_s64,
17486	/ 45791 / GIM_CheckRegBankForClass, /MI/`2`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
17487	/ 45796 / GIM_CheckIsSafeToFold, /NumInsns/`2`,
17488	/* 45798 / // (setcc:{ :[i32] } (bitconvert:{ :[i32] } (fpround:{ :[f32] } FGR64Opnd:{ :[f64] }:$src)), 0:{ :[i32] }, SETLT:{ :[Other] }) => (SLTi:{ :[i32] } (MFHC1_D64:{ :[i32] } FGR64Opnd:{ :[f64] }:$src), 0:{ *:[i32] })
17489	/ 45798 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17490	/ 45801 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::MFHC1_D64),
17491	/ 45805 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17492	/ 45810 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`2`, /OpIdx/`1`, // src
17493	/ 45814 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17494	/ 45816 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTi),
17495	/ 45819 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17496	/ 45821 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17497	/ 45824 / GIR_AddImm8, /InsnID/`0`, /Imm/`0`,
17498	/ 45827 / GIR_RootConstrainSelectedInstOperands,
17499	/ 45828 / // GIR_Coverage, 1521,
17500	/ 45828 / GIR_EraseRootFromParent_Done,
17501	/ 45829 / // Label 1275: @45829
17502	/ 45829 / GIM_Reject,
17503	/ 45830 / // Label 1273: @45830
17504	/ 45830 / GIM_Try_CheckFeatures, /On fail goto//Label 1276/ GIMT_Encode4(`45862`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1436 //
17505	/ 45837 / // MIs[0] Operand 1
17506	/ 45837 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
17507	/ 45842 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17508	/ 45846 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17509	/ 45850 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }) => (SLTiu:{ :[i32] } GPR32:{ :[i32] }:$lhs, 1:{ :[i32] })*
17510	/ 45850 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu),
17511	/ 45853 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17512	/ 45855 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17513	/ 45857 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17514	/ 45860 / GIR_RootConstrainSelectedInstOperands,
17515	/ 45861 / // GIR_Coverage, 1436,
17516	/ 45861 / GIR_EraseRootFromParent_Done,
17517	/ 45862 / // Label 1276: @45862
17518	/ 45862 / GIM_Try_CheckFeatures, /On fail goto//Label 1277/ GIMT_Encode4(`45897`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1437 //
17519	/ 45869 / // MIs[0] Operand 1
17520	/ 45869 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
17521	/ 45874 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17522	/ 45878 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17523	/ 45882 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }) => (SLTu:{ :[i32] } ZERO:{ :[i32] }, GPR32:{ :[i32] }:$lhs)*
17524	/ 45882 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu),
17525	/ 45885 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17526	/ 45887 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
17527	/ 45893 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17528	/ 45895 / GIR_RootConstrainSelectedInstOperands,
17529	/ 45896 / // GIR_Coverage, 1437,
17530	/ 45896 / GIR_EraseRootFromParent_Done,
17531	/ 45897 / // Label 1277: @45897
17532	/ 45897 / GIM_Reject,
17533	/ 45898 / // Label 1272: @45898
17534	/ 45898 / GIM_Try, /On fail goto//Label 1278/ GIMT_Encode4(`46025`),
17535	/ 45903 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17536	/ 45907 / GIM_Try_CheckFeatures, /On fail goto//Label 1279/ GIMT_Encode4(`45939`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2014 //
17537	/ 45914 / // MIs[0] Operand 1
17538	/ 45914 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
17539	/ 45919 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17540	/ 45923 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17541	/ 45927 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }) => (SltiuCCRxImmX16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, 1:{ :[i32] })*
17542	/ 45927 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17543	/ 45930 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17544	/ 45932 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17545	/ 45934 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17546	/ 45937 / GIR_RootConstrainSelectedInstOperands,
17547	/ 45938 / // GIR_Coverage, 2014,
17548	/ 45938 / GIR_EraseRootFromParent_Done,
17549	/ 45939 / // Label 1279: @45939
17550	/ 45939 / GIM_Try_CheckFeatures, /On fail goto//Label 1280/ GIMT_Encode4(`46024`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2016 //
17551	/ 45946 / // MIs[0] Operand 1
17552	/ 45946 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
17553	/ 45951 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17554	/ 45955 / GIM_CheckConstantInt, /MI/`0`, /Op/`3`, GIMT_Encode8(`18446744073709518847u`),
17555	/* 45966 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, -32769:{ :[i32] }, SETGT:{ :[Other] }) => (XorRxRxRy16:{ :[i32] } (SltiCCRxImmX16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, -32768:{ :[i32] }), (LiRxImmX16:{ :[i32] } 1:{ *:[i32] }))
17556	/ 45966 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17557	/ 45969 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::LiRxImmX16),
17558	/ 45973 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17559	/ 45978 / GIR_AddImm8, /InsnID/`2`, /Imm/`1`,
17560	/ 45981 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17561	/ 45983 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17562	/ 45986 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SltiCCRxImmX16),
17563	/ 45990 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17564	/ 45995 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17565	/ 45999 / GIR_AddImm, /InsnID/`1`, /Imm/GIMT_Encode8(`18446744073709518848u`),
17566	/ 46009 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17567	/ 46011 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17568	/ 46014 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rz]
17569	/ 46016 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17570	/ 46019 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
17571	/ 46022 / GIR_RootConstrainSelectedInstOperands,
17572	/ 46023 / // GIR_Coverage, 2016,
17573	/ 46023 / GIR_EraseRootFromParent_Done,
17574	/ 46024 / // Label 1280: @46024
17575	/ 46024 / GIM_Reject,
17576	/ 46025 / // Label 1278: @46025
17577	/ 46025 / GIM_Try, /On fail goto//Label 1281/ GIMT_Encode4(`46164`),
17578	/ 46030 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17579	/ 46034 / GIM_Try_CheckFeatures, /On fail goto//Label 1282/ GIMT_Encode4(`46066`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2333 //
17580	/ 46041 / // MIs[0] Operand 1
17581	/ 46041 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
17582	/ 46046 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17583	/ 46050 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17584	/ 46054 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }) => (SLTiu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, 1:{ :[i32] })*
17585	/ 46054 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu_MM),
17586	/ 46057 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17587	/ 46059 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17588	/ 46061 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17589	/ 46064 / GIR_RootConstrainSelectedInstOperands,
17590	/ 46065 / // GIR_Coverage, 2333,
17591	/ 46065 / GIR_EraseRootFromParent_Done,
17592	/ 46066 / // Label 1282: @46066
17593	/ 46066 / GIM_Try_CheckFeatures, /On fail goto//Label 1283/ GIMT_Encode4(`46101`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2334 //
17594	/ 46073 / // MIs[0] Operand 1
17595	/ 46073 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
17596	/ 46078 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17597	/ 46082 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
17598	/ 46086 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }) => (SLTu_MM:{ :[i32] } ZERO:{ :[i32] }, GPR32:{ :[i32] }:$lhs)*
17599	/ 46086 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
17600	/ 46089 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17601	/ 46091 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
17602	/ 46097 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17603	/ 46099 / GIR_RootConstrainSelectedInstOperands,
17604	/ 46100 / // GIR_Coverage, 2334,
17605	/ 46100 / GIR_EraseRootFromParent_Done,
17606	/ 46101 / // Label 1283: @46101
17607	/ 46101 / GIM_Try_CheckFeatures, /On fail goto//Label 1284/ GIMT_Encode4(`46132`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 49 //
17608	/ 46108 / // MIs[0] Operand 1
17609	/ 46108 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
17610	/ 46113 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17611	/ 46117 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17612	/ 46121 / // (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETLT:{ :[Other] }) => (SLT:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
17613	/ 46121 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT),
17614	/ 46124 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17615	/ 46126 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
17616	/ 46128 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
17617	/ 46130 / GIR_RootConstrainSelectedInstOperands,
17618	/ 46131 / // GIR_Coverage, 49,
17619	/ 46131 / GIR_EraseRootFromParent_Done,
17620	/ 46132 / // Label 1284: @46132
17621	/ 46132 / GIM_Try_CheckFeatures, /On fail goto//Label 1285/ GIMT_Encode4(`46163`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 50 //
17622	/ 46139 / // MIs[0] Operand 1
17623	/ 46139 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
17624	/ 46144 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17625	/ 46148 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17626	/ 46152 / // (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETULT:{ :[Other] }) => (SLTu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
17627	/ 46152 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu),
17628	/ 46155 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17629	/ 46157 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
17630	/ 46159 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
17631	/ 46161 / GIR_RootConstrainSelectedInstOperands,
17632	/ 46162 / // GIR_Coverage, 50,
17633	/ 46162 / GIR_EraseRootFromParent_Done,
17634	/ 46163 / // Label 1285: @46163
17635	/ 46163 / GIM_Reject,
17636	/ 46164 / // Label 1281: @46164
17637	/ 46164 / GIM_Try, /On fail goto//Label 1286/ GIMT_Encode4(`46631`),
17638	/ 46169 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17639	/ 46173 / GIM_Try_CheckFeatures, /On fail goto//Label 1287/ GIMT_Encode4(`46204`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1096 //
17640	/ 46180 / // MIs[0] Operand 1
17641	/ 46180 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
17642	/ 46185 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17643	/ 46189 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17644	/ 46193 / // (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETLT:{ :[Other] }) => (SLT_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
17645	/ 46193 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT_MM),
17646	/ 46196 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17647	/ 46198 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
17648	/ 46200 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
17649	/ 46202 / GIR_RootConstrainSelectedInstOperands,
17650	/ 46203 / // GIR_Coverage, 1096,
17651	/ 46203 / GIR_EraseRootFromParent_Done,
17652	/ 46204 / // Label 1287: @46204
17653	/ 46204 / GIM_Try_CheckFeatures, /On fail goto//Label 1288/ GIMT_Encode4(`46235`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1097 //
17654	/ 46211 / // MIs[0] Operand 1
17655	/ 46211 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
17656	/ 46216 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17657	/ 46220 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17658	/ 46224 / // (setcc:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt, SETULT:{ :[Other] }) => (SLTu_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)*
17659	/ 46224 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
17660	/ 46227 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17661	/ 46229 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
17662	/ 46231 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
17663	/ 46233 / GIR_RootConstrainSelectedInstOperands,
17664	/ 46234 / // GIR_Coverage, 1097,
17665	/ 46234 / GIR_EraseRootFromParent_Done,
17666	/ 46235 / // Label 1288: @46235
17667	/ 46235 / GIM_Try_CheckFeatures, /On fail goto//Label 1289/ GIMT_Encode4(`46290`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1438 //
17668	/ 46242 / // MIs[0] Operand 1
17669	/ 46242 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
17670	/ 46247 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17671	/ 46251 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17672	/* 46255 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }) => (SLTiu:{ :[i32] } (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
17673	/ 46255 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17674	/ 46258 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
17675	/ 46262 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17676	/ 46267 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17677	/ 46271 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17678	/ 46275 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17679	/ 46277 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu),
17680	/ 46280 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17681	/ 46282 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17682	/ 46285 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17683	/ 46288 / GIR_RootConstrainSelectedInstOperands,
17684	/ 46289 / // GIR_Coverage, 1438,
17685	/ 46289 / GIR_EraseRootFromParent_Done,
17686	/ 46290 / // Label 1289: @46290
17687	/ 46290 / GIM_Try_CheckFeatures, /On fail goto//Label 1290/ GIMT_Encode4(`46348`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1439 //
17688	/ 46297 / // MIs[0] Operand 1
17689	/ 46297 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
17690	/ 46302 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17691	/ 46306 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17692	/* 46310 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }) => (SLTu:{ :[i32] } ZERO:{ :[i32] }, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs))
17693	/ 46310 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17694	/ 46313 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
17695	/ 46317 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17696	/ 46322 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17697	/ 46326 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17698	/ 46330 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17699	/ 46332 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu),
17700	/ 46335 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17701	/ 46337 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
17702	/ 46343 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17703	/ 46346 / GIR_RootConstrainSelectedInstOperands,
17704	/ 46347 / // GIR_Coverage, 1439,
17705	/ 46347 / GIR_EraseRootFromParent_Done,
17706	/ 46348 / // Label 1290: @46348
17707	/ 46348 / GIM_Try_CheckFeatures, /On fail goto//Label 1291/ GIMT_Encode4(`46403`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1440 //
17708	/ 46355 / // MIs[0] Operand 1
17709	/ 46355 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
17710	/ 46360 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17711	/ 46364 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17712	/* 46368 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }) => (XORi:{ :[i32] } (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), 1:{ :[i32] })
17713	/ 46368 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17714	/ 46371 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
17715	/ 46375 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17716	/ 46380 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17717	/ 46384 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17718	/ 46388 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17719	/ 46390 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
17720	/ 46393 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17721	/ 46395 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17722	/ 46398 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17723	/ 46401 / GIR_RootConstrainSelectedInstOperands,
17724	/ 46402 / // GIR_Coverage, 1440,
17725	/ 46402 / GIR_EraseRootFromParent_Done,
17726	/ 46403 / // Label 1291: @46403
17727	/ 46403 / GIM_Try_CheckFeatures, /On fail goto//Label 1292/ GIMT_Encode4(`46458`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1441 //
17728	/ 46410 / // MIs[0] Operand 1
17729	/ 46410 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
17730	/ 46415 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17731	/ 46419 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17732	/* 46423 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }) => (XORi:{ :[i32] } (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), 1:{ :[i32] })
17733	/ 46423 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17734	/ 46426 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
17735	/ 46430 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17736	/ 46435 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17737	/ 46439 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17738	/ 46443 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17739	/ 46445 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
17740	/ 46448 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17741	/ 46450 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17742	/ 46453 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17743	/ 46456 / GIR_RootConstrainSelectedInstOperands,
17744	/ 46457 / // GIR_Coverage, 1441,
17745	/ 46457 / GIR_EraseRootFromParent_Done,
17746	/ 46458 / // Label 1292: @46458
17747	/ 46458 / GIM_Try_CheckFeatures, /On fail goto//Label 1293/ GIMT_Encode4(`46489`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1442 //
17748	/ 46465 / // MIs[0] Operand 1
17749	/ 46465 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
17750	/ 46470 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17751	/ 46474 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17752	/ 46478 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGT:{ :[Other] }) => (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs)*
17753	/ 46478 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT),
17754	/ 46481 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17755	/ 46483 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
17756	/ 46485 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17757	/ 46487 / GIR_RootConstrainSelectedInstOperands,
17758	/ 46488 / // GIR_Coverage, 1442,
17759	/ 46488 / GIR_EraseRootFromParent_Done,
17760	/ 46489 / // Label 1293: @46489
17761	/ 46489 / GIM_Try_CheckFeatures, /On fail goto//Label 1294/ GIMT_Encode4(`46520`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1443 //
17762	/ 46496 / // MIs[0] Operand 1
17763	/ 46496 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
17764	/ 46501 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17765	/ 46505 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17766	/ 46509 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGT:{ :[Other] }) => (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs)*
17767	/ 46509 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu),
17768	/ 46512 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
17769	/ 46514 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
17770	/ 46516 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17771	/ 46518 / GIR_RootConstrainSelectedInstOperands,
17772	/ 46519 / // GIR_Coverage, 1443,
17773	/ 46519 / GIR_EraseRootFromParent_Done,
17774	/ 46520 / // Label 1294: @46520
17775	/ 46520 / GIM_Try_CheckFeatures, /On fail goto//Label 1295/ GIMT_Encode4(`46575`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1444 //
17776	/ 46527 / // MIs[0] Operand 1
17777	/ 46527 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
17778	/ 46532 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17779	/ 46536 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17780	/* 46540 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }) => (XORi:{ :[i32] } (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
17781	/ 46540 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17782	/ 46543 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
17783	/ 46547 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17784	/ 46552 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17785	/ 46556 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17786	/ 46560 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17787	/ 46562 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
17788	/ 46565 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17789	/ 46567 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17790	/ 46570 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17791	/ 46573 / GIR_RootConstrainSelectedInstOperands,
17792	/ 46574 / // GIR_Coverage, 1444,
17793	/ 46574 / GIR_EraseRootFromParent_Done,
17794	/ 46575 / // Label 1295: @46575
17795	/ 46575 / GIM_Try_CheckFeatures, /On fail goto//Label 1296/ GIMT_Encode4(`46630`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1445 //
17796	/ 46582 / // MIs[0] Operand 1
17797	/ 46582 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
17798	/ 46587 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17799	/ 46591 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
17800	/* 46595 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }) => (XORi:{ :[i32] } (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
17801	/ 46595 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17802	/ 46598 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
17803	/ 46602 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17804	/ 46607 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17805	/ 46611 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17806	/ 46615 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17807	/ 46617 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
17808	/ 46620 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
17809	/ 46622 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17810	/ 46625 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17811	/ 46628 / GIR_RootConstrainSelectedInstOperands,
17812	/ 46629 / // GIR_Coverage, 1445,
17813	/ 46629 / GIR_EraseRootFromParent_Done,
17814	/ 46630 / // Label 1296: @46630
17815	/ 46630 / GIM_Reject,
17816	/ 46631 / // Label 1286: @46631
17817	/ 46631 / GIM_Try, /On fail goto//Label 1297/ GIMT_Encode4(`47180`),
17818	/ 46636 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17819	/ 46640 / GIM_Try_CheckFeatures, /On fail goto//Label 1298/ GIMT_Encode4(`46695`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2013 //
17820	/ 46647 / // MIs[0] Operand 1
17821	/ 46647 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
17822	/ 46652 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17823	/ 46656 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17824	/* 46660 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETEQ:{ :[Other] }) => (SltiuCCRxImmX16:{ :[i32] } (XorRxRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs), 1:{ :[i32] })
17825	/ 46660 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17826	/ 46663 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17827	/ 46667 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17828	/ 46672 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17829	/ 46676 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17830	/ 46680 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17831	/ 46682 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17832	/ 46685 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17833	/ 46687 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17834	/ 46690 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
17835	/ 46693 / GIR_RootConstrainSelectedInstOperands,
17836	/ 46694 / // GIR_Coverage, 2013,
17837	/ 46694 / GIR_EraseRootFromParent_Done,
17838	/ 46695 / // Label 1298: @46695
17839	/ 46695 / GIM_Try_CheckFeatures, /On fail goto//Label 1299/ GIMT_Encode4(`46767`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2015 //
17840	/ 46702 / // MIs[0] Operand 1
17841	/ 46702 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
17842	/ 46707 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17843	/ 46711 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17844	/* 46715 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETGE:{ :[Other] }) => (XorRxRxRy16:{ :[i32] } (SltCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs), (LiRxImmX16:{ :[i32] } 1:{ *:[i32] }))
17845	/ 46715 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17846	/ 46718 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::LiRxImmX16),
17847	/ 46722 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17848	/ 46727 / GIR_AddImm8, /InsnID/`2`, /Imm/`1`,
17849	/ 46730 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17850	/ 46732 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17851	/ 46735 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SltCCRxRy16),
17852	/ 46739 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17853	/ 46744 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17854	/ 46748 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17855	/ 46752 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17856	/ 46754 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17857	/ 46757 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rz]
17858	/ 46759 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17859	/ 46762 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
17860	/ 46765 / GIR_RootConstrainSelectedInstOperands,
17861	/ 46766 / // GIR_Coverage, 2015,
17862	/ 46766 / GIR_EraseRootFromParent_Done,
17863	/ 46767 / // Label 1299: @46767
17864	/ 46767 / GIM_Try_CheckFeatures, /On fail goto//Label 1300/ GIMT_Encode4(`46798`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2017 //
17865	/ 46774 / // MIs[0] Operand 1
17866	/ 46774 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
17867	/ 46779 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17868	/ 46783 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17869	/* 46787 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETGT:{ :[Other] }) => (SltCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rhs, CPU16Regs:{ :[i32] }:$lhs)
17870	/ 46787 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltCCRxRy16),
17871	/ 46790 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17872	/ 46792 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
17873	/ 46794 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17874	/ 46796 / GIR_RootConstrainSelectedInstOperands,
17875	/ 46797 / // GIR_Coverage, 2017,
17876	/ 46797 / GIR_EraseRootFromParent_Done,
17877	/ 46798 / // Label 1300: @46798
17878	/ 46798 / GIM_Try_CheckFeatures, /On fail goto//Label 1301/ GIMT_Encode4(`46870`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2018 //
17879	/ 46805 / // MIs[0] Operand 1
17880	/ 46805 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
17881	/ 46810 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17882	/ 46814 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17883	/* 46818 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETLE:{ :[Other] }) => (XorRxRxRy16:{ :[i32] } (SltCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rhs, CPU16Regs:{ :[i32] }:$lhs), (LiRxImm16:{ :[i32] } 1:{ *:[i32] }))
17884	/ 46818 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17885	/ 46821 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::LiRxImm16),
17886	/ 46825 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17887	/ 46830 / GIR_AddImm8, /InsnID/`2`, /Imm/`1`,
17888	/ 46833 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17889	/ 46835 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17890	/ 46838 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SltCCRxRy16),
17891	/ 46842 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17892	/ 46847 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17893	/ 46851 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17894	/ 46855 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17895	/ 46857 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17896	/ 46860 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rz]
17897	/ 46862 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17898	/ 46865 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
17899	/ 46868 / GIR_RootConstrainSelectedInstOperands,
17900	/ 46869 / // GIR_Coverage, 2018,
17901	/ 46869 / GIR_EraseRootFromParent_Done,
17902	/ 46870 / // Label 1301: @46870
17903	/ 46870 / GIM_Try_CheckFeatures, /On fail goto//Label 1302/ GIMT_Encode4(`46901`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2019 //
17904	/ 46877 / // MIs[0] Operand 1
17905	/ 46877 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
17906	/ 46882 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17907	/ 46886 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17908	/ 46890 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETLT:{ :[Other] }) => (SltCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry)*
17909	/ 46890 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltCCRxRy16),
17910	/ 46893 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17911	/ 46895 / GIR_RootToRootCopy, /OpIdx/`2`, // rx
17912	/ 46897 / GIR_RootToRootCopy, /OpIdx/`3`, // ry
17913	/ 46899 / GIR_RootConstrainSelectedInstOperands,
17914	/ 46900 / // GIR_Coverage, 2019,
17915	/ 46900 / GIR_EraseRootFromParent_Done,
17916	/ 46901 / // Label 1302: @46901
17917	/ 46901 / GIM_Try_CheckFeatures, /On fail goto//Label 1303/ GIMT_Encode4(`46973`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2021 //
17918	/ 46908 / // MIs[0] Operand 1
17919	/ 46908 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
17920	/ 46913 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17921	/ 46917 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17922	/* 46921 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETNE:{ :[Other] }) => (SltuCCRxRy16:{ :[i32] } (LiRxImmX16:{ :[i32] } 0:{ :[i32] }), (XorRxRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
17923	/ 46921 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17924	/ 46924 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17925	/ 46928 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17926	/ 46933 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17927	/ 46937 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17928	/ 46941 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17929	/ 46943 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17930	/ 46946 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::LiRxImmX16),
17931	/ 46950 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17932	/ 46955 / GIR_AddImm8, /InsnID/`1`, /Imm/`0`,
17933	/ 46958 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17934	/ 46960 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltuCCRxRy16),
17935	/ 46963 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17936	/ 46965 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17937	/ 46968 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
17938	/ 46971 / GIR_RootConstrainSelectedInstOperands,
17939	/ 46972 / // GIR_Coverage, 2021,
17940	/ 46972 / GIR_EraseRootFromParent_Done,
17941	/ 46973 / // Label 1303: @46973
17942	/ 46973 / GIM_Try_CheckFeatures, /On fail goto//Label 1304/ GIMT_Encode4(`47045`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2022 //
17943	/ 46980 / // MIs[0] Operand 1
17944	/ 46980 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
17945	/ 46985 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17946	/ 46989 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17947	/* 46993 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETUGE:{ :[Other] }) => (XorRxRxRy16:{ :[i32] } (SltuCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs), (LiRxImmX16:{ :[i32] } 1:{ *:[i32] }))
17948	/ 46993 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17949	/ 46996 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::LiRxImmX16),
17950	/ 47000 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17951	/ 47005 / GIR_AddImm8, /InsnID/`2`, /Imm/`1`,
17952	/ 47008 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17953	/ 47010 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17954	/ 47013 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SltuCCRxRy16),
17955	/ 47017 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17956	/ 47022 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17957	/ 47026 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17958	/ 47030 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17959	/ 47032 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17960	/ 47035 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rz]
17961	/ 47037 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
17962	/ 47040 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
17963	/ 47043 / GIR_RootConstrainSelectedInstOperands,
17964	/ 47044 / // GIR_Coverage, 2022,
17965	/ 47044 / GIR_EraseRootFromParent_Done,
17966	/ 47045 / // Label 1304: @47045
17967	/ 47045 / GIM_Try_CheckFeatures, /On fail goto//Label 1305/ GIMT_Encode4(`47076`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2023 //
17968	/ 47052 / // MIs[0] Operand 1
17969	/ 47052 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
17970	/ 47057 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17971	/ 47061 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17972	/* 47065 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETUGT:{ :[Other] }) => (SltuCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rhs, CPU16Regs:{ :[i32] }:$lhs)
17973	/ 47065 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltuCCRxRy16),
17974	/ 47068 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
17975	/ 47070 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
17976	/ 47072 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
17977	/ 47074 / GIR_RootConstrainSelectedInstOperands,
17978	/ 47075 / // GIR_Coverage, 2023,
17979	/ 47075 / GIR_EraseRootFromParent_Done,
17980	/ 47076 / // Label 1305: @47076
17981	/ 47076 / GIM_Try_CheckFeatures, /On fail goto//Label 1306/ GIMT_Encode4(`47148`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2024 //
17982	/ 47083 / // MIs[0] Operand 1
17983	/ 47083 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
17984	/ 47088 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17985	/ 47092 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17986	/* 47096 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$lhs, CPU16Regs:{ :[i32] }:$rhs, SETULE:{ :[Other] }) => (XorRxRxRy16:{ :[i32] } (SltuCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rhs, CPU16Regs:{ :[i32] }:$lhs), (LiRxImmX16:{ :[i32] } 1:{ *:[i32] }))
17987	/ 47096 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
17988	/ 47099 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::LiRxImmX16),
17989	/ 47103 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17990	/ 47108 / GIR_AddImm8, /InsnID/`2`, /Imm/`1`,
17991	/ 47111 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
17992	/ 47113 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
17993	/ 47116 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SltuCCRxRy16),
17994	/ 47120 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17995	/ 47125 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
17996	/ 47129 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
17997	/ 47133 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
17998	/ 47135 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XorRxRxRy16),
17999	/ 47138 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rz]
18000	/ 47140 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18001	/ 47143 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
18002	/ 47146 / GIR_RootConstrainSelectedInstOperands,
18003	/ 47147 / // GIR_Coverage, 2024,
18004	/ 47147 / GIR_EraseRootFromParent_Done,
18005	/ 47148 / // Label 1306: @47148
18006	/ 47148 / GIM_Try_CheckFeatures, /On fail goto//Label 1307/ GIMT_Encode4(`47179`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2025 //
18007	/ 47155 / // MIs[0] Operand 1
18008	/ 47155 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
18009	/ 47160 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18010	/ 47164 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18011	/* 47168 / // (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry, SETULT:{ :[Other] }) => (SltuCCRxRy16:{ :[i32] } CPU16Regs:{ :[i32] }:$rx, CPU16Regs:{ :[i32] }:$ry)
18012	/ 47168 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SltuCCRxRy16),
18013	/ 47171 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[cc]
18014	/ 47173 / GIR_RootToRootCopy, /OpIdx/`2`, // rx
18015	/ 47175 / GIR_RootToRootCopy, /OpIdx/`3`, // ry
18016	/ 47177 / GIR_RootConstrainSelectedInstOperands,
18017	/ 47178 / // GIR_Coverage, 2025,
18018	/ 47178 / GIR_EraseRootFromParent_Done,
18019	/ 47179 / // Label 1307: @47179
18020	/ 47179 / GIM_Reject,
18021	/ 47180 / // Label 1297: @47180
18022	/ 47180 / GIM_Try, /On fail goto//Label 1308/ GIMT_Encode4(`47585`),
18023	/ 47185 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18024	/ 47189 / GIM_Try_CheckFeatures, /On fail goto//Label 1309/ GIMT_Encode4(`47244`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2335 //
18025	/ 47196 / // MIs[0] Operand 1
18026	/ 47196 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18027	/ 47201 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18028	/ 47205 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18029	/* 47209 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }) => (SLTiu_MM:{ :[i32] } (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
18030	/ 47209 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18031	/ 47212 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
18032	/ 47216 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18033	/ 47221 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18034	/ 47225 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18035	/ 47229 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18036	/ 47231 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu_MM),
18037	/ 47234 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18038	/ 47236 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18039	/ 47239 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18040	/ 47242 / GIR_RootConstrainSelectedInstOperands,
18041	/ 47243 / // GIR_Coverage, 2335,
18042	/ 47243 / GIR_EraseRootFromParent_Done,
18043	/ 47244 / // Label 1309: @47244
18044	/ 47244 / GIM_Try_CheckFeatures, /On fail goto//Label 1310/ GIMT_Encode4(`47302`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2336 //
18045	/ 47251 / // MIs[0] Operand 1
18046	/ 47251 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18047	/ 47256 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18048	/ 47260 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18049	/* 47264 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }) => (SLTu_MM:{ :[i32] } ZERO:{ :[i32] }, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs))
18050	/ 47264 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18051	/ 47267 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
18052	/ 47271 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18053	/ 47276 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18054	/ 47280 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18055	/ 47284 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18056	/ 47286 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
18057	/ 47289 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18058	/ 47291 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO), /AddRegisterRegFlags/GIMT_Encode2(`0`),
18059	/ 47297 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18060	/ 47300 / GIR_RootConstrainSelectedInstOperands,
18061	/ 47301 / // GIR_Coverage, 2336,
18062	/ 47301 / GIR_EraseRootFromParent_Done,
18063	/ 47302 / // Label 1310: @47302
18064	/ 47302 / GIM_Try_CheckFeatures, /On fail goto//Label 1311/ GIMT_Encode4(`47357`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2337 //
18065	/ 47309 / // MIs[0] Operand 1
18066	/ 47309 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
18067	/ 47314 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18068	/ 47318 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18069	/* 47322 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }) => (XORi_MM:{ :[i32] } (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), 1:{ :[i32] })
18070	/ 47322 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18071	/ 47325 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
18072	/ 47329 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18073	/ 47334 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18074	/ 47338 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18075	/ 47342 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18076	/ 47344 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi_MM),
18077	/ 47347 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18078	/ 47349 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18079	/ 47352 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18080	/ 47355 / GIR_RootConstrainSelectedInstOperands,
18081	/ 47356 / // GIR_Coverage, 2337,
18082	/ 47356 / GIR_EraseRootFromParent_Done,
18083	/ 47357 / // Label 1311: @47357
18084	/ 47357 / GIM_Try_CheckFeatures, /On fail goto//Label 1312/ GIMT_Encode4(`47412`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2338 //
18085	/ 47364 / // MIs[0] Operand 1
18086	/ 47364 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
18087	/ 47369 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18088	/ 47373 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18089	/* 47377 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }) => (XORi_MM:{ :[i32] } (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), 1:{ :[i32] })
18090	/ 47377 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18091	/ 47380 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
18092	/ 47384 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18093	/ 47389 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18094	/ 47393 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18095	/ 47397 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18096	/ 47399 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi_MM),
18097	/ 47402 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18098	/ 47404 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18099	/ 47407 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18100	/ 47410 / GIR_RootConstrainSelectedInstOperands,
18101	/ 47411 / // GIR_Coverage, 2338,
18102	/ 47411 / GIR_EraseRootFromParent_Done,
18103	/ 47412 / // Label 1312: @47412
18104	/ 47412 / GIM_Try_CheckFeatures, /On fail goto//Label 1313/ GIMT_Encode4(`47443`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2339 //
18105	/ 47419 / // MIs[0] Operand 1
18106	/ 47419 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
18107	/ 47424 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18108	/ 47428 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18109	/ 47432 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGT:{ :[Other] }) => (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs)*
18110	/ 47432 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT_MM),
18111	/ 47435 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18112	/ 47437 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
18113	/ 47439 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18114	/ 47441 / GIR_RootConstrainSelectedInstOperands,
18115	/ 47442 / // GIR_Coverage, 2339,
18116	/ 47442 / GIR_EraseRootFromParent_Done,
18117	/ 47443 / // Label 1313: @47443
18118	/ 47443 / GIM_Try_CheckFeatures, /On fail goto//Label 1314/ GIMT_Encode4(`47474`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2340 //
18119	/ 47450 / // MIs[0] Operand 1
18120	/ 47450 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
18121	/ 47455 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18122	/ 47459 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18123	/ 47463 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGT:{ :[Other] }) => (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs)*
18124	/ 47463 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
18125	/ 47466 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18126	/ 47468 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
18127	/ 47470 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18128	/ 47472 / GIR_RootConstrainSelectedInstOperands,
18129	/ 47473 / // GIR_Coverage, 2340,
18130	/ 47473 / GIR_EraseRootFromParent_Done,
18131	/ 47474 / // Label 1314: @47474
18132	/ 47474 / GIM_Try_CheckFeatures, /On fail goto//Label 1315/ GIMT_Encode4(`47529`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2341 //
18133	/ 47481 / // MIs[0] Operand 1
18134	/ 47481 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
18135	/ 47486 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18136	/ 47490 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18137	/* 47494 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }) => (XORi_MM:{ :[i32] } (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
18138	/ 47494 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18139	/ 47497 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
18140	/ 47501 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18141	/ 47506 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18142	/ 47510 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18143	/ 47514 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18144	/ 47516 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi_MM),
18145	/ 47519 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18146	/ 47521 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18147	/ 47524 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18148	/ 47527 / GIR_RootConstrainSelectedInstOperands,
18149	/ 47528 / // GIR_Coverage, 2341,
18150	/ 47528 / GIR_EraseRootFromParent_Done,
18151	/ 47529 / // Label 1315: @47529
18152	/ 47529 / GIM_Try_CheckFeatures, /On fail goto//Label 1316/ GIMT_Encode4(`47584`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2342 //
18153	/ 47536 / // MIs[0] Operand 1
18154	/ 47536 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
18155	/ 47541 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18156	/ 47545 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18157	/* 47549 / // (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }) => (XORi_MM:{ :[i32] } (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), 1:{ :[i32] })
18158	/ 47549 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18159	/ 47552 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
18160	/ 47556 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18161	/ 47561 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18162	/ 47565 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18163	/ 47569 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18164	/ 47571 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi_MM),
18165	/ 47574 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18166	/ 47576 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18167	/ 47579 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18168	/ 47582 / GIR_RootConstrainSelectedInstOperands,
18169	/ 47583 / // GIR_Coverage, 2342,
18170	/ 47583 / GIR_EraseRootFromParent_Done,
18171	/ 47584 / // Label 1316: @47584
18172	/ 47584 / GIM_Reject,
18173	/ 47585 / // Label 1308: @47585
18174	/ 47585 / GIM_Reject,
18175	/ 47586 / // Label 1271: @47586
18176	/ 47586 / GIM_Reject,
18177	/ 47587 / // Label 1269: @47587
18178	/ 47587 / GIM_Try, /On fail goto//Label 1317/ GIMT_Encode4(`48124`),
18179	/ 47592 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s64,
18180	/ 47595 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18181	/ 47599 / GIM_Try_CheckFeatures, /On fail goto//Label 1318/ GIMT_Encode4(`47631`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1664 //
18182	/ 47606 / // MIs[0] Operand 1
18183	/ 47606 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18184	/ 47611 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18185	/ 47615 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
18186	/ 47619 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }) => (SLTiu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, 1:{ :[i64] })*
18187	/ 47619 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu64),
18188	/ 47622 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18189	/ 47624 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18190	/ 47626 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18191	/ 47629 / GIR_RootConstrainSelectedInstOperands,
18192	/ 47630 / // GIR_Coverage, 1664,
18193	/ 47630 / GIR_EraseRootFromParent_Done,
18194	/ 47631 / // Label 1318: @47631
18195	/ 47631 / GIM_Try_CheckFeatures, /On fail goto//Label 1319/ GIMT_Encode4(`47666`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1665 //
18196	/ 47638 / // MIs[0] Operand 1
18197	/ 47638 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18198	/ 47643 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18199	/ 47647 / GIM_CheckConstantInt8, /MI/`0`, /Op/`3`, `0`,
18200	/ 47651 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }) => (SLTu64:{ :[i32] } ZERO_64:{ :[i64] }, GPR64:{ :[i64] }:$lhs)*
18201	/ 47651 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu64),
18202	/ 47654 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18203	/ 47656 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO_64), /AddRegisterRegFlags/GIMT_Encode2(`0`),
18204	/ 47662 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18205	/ 47664 / GIR_RootConstrainSelectedInstOperands,
18206	/ 47665 / // GIR_Coverage, 1665,
18207	/ 47665 / GIR_EraseRootFromParent_Done,
18208	/ 47666 / // Label 1319: @47666
18209	/ 47666 / GIM_Try_CheckFeatures, /On fail goto//Label 1320/ GIMT_Encode4(`47697`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 231 //
18210	/ 47673 / // MIs[0] Operand 1
18211	/ 47673 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLT),
18212	/ 47678 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18213	/ 47682 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18214	/ 47686 / // (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETLT:{ :[Other] }) => (SLT64:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)*
18215	/ 47686 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT64),
18216	/ 47689 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18217	/ 47691 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
18218	/ 47693 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
18219	/ 47695 / GIR_RootConstrainSelectedInstOperands,
18220	/ 47696 / // GIR_Coverage, 231,
18221	/ 47696 / GIR_EraseRootFromParent_Done,
18222	/ 47697 / // Label 1320: @47697
18223	/ 47697 / GIM_Try_CheckFeatures, /On fail goto//Label 1321/ GIMT_Encode4(`47728`), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 232 //
18224	/ 47704 / // MIs[0] Operand 1
18225	/ 47704 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULT),
18226	/ 47709 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18227	/ 47713 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18228	/ 47717 / // (setcc:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt, SETULT:{ :[Other] }) => (SLTu64:{ :[i32] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)*
18229	/ 47717 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu64),
18230	/ 47720 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18231	/ 47722 / GIR_RootToRootCopy, /OpIdx/`2`, // rs
18232	/ 47724 / GIR_RootToRootCopy, /OpIdx/`3`, // rt
18233	/ 47726 / GIR_RootConstrainSelectedInstOperands,
18234	/ 47727 / // GIR_Coverage, 232,
18235	/ 47727 / GIR_EraseRootFromParent_Done,
18236	/ 47728 / // Label 1321: @47728
18237	/ 47728 / GIM_Try_CheckFeatures, /On fail goto//Label 1322/ GIMT_Encode4(`47783`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1666 //
18238	/ 47735 / // MIs[0] Operand 1
18239	/ 47735 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18240	/ 47740 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18241	/ 47744 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18242	/* 47748 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETEQ:{ :[Other] }) => (SLTiu64:{ :[i32] } (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), 1:{ :[i64] })
18243	/ 47748 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
18244	/ 47751 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
18245	/ 47755 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18246	/ 47760 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18247	/ 47764 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18248	/ 47768 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18249	/ 47770 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTiu64),
18250	/ 47773 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18251	/ 47775 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18252	/ 47778 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18253	/ 47781 / GIR_RootConstrainSelectedInstOperands,
18254	/ 47782 / // GIR_Coverage, 1666,
18255	/ 47782 / GIR_EraseRootFromParent_Done,
18256	/ 47783 / // Label 1322: @47783
18257	/ 47783 / GIM_Try_CheckFeatures, /On fail goto//Label 1323/ GIMT_Encode4(`47841`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1667 //
18258	/ 47790 / // MIs[0] Operand 1
18259	/ 47790 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18260	/ 47795 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18261	/ 47799 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18262	/* 47803 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETNE:{ :[Other] }) => (SLTu64:{ :[i32] } ZERO_64:{ :[i64] }, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs))
18263	/ 47803 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
18264	/ 47806 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
18265	/ 47810 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18266	/ 47815 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18267	/ 47819 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18268	/ 47823 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18269	/ 47825 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu64),
18270	/ 47828 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18271	/ 47830 / GIR_AddRegister, /InsnID/`0`, GIMT_Encode2(Mips::ZERO_64), /AddRegisterRegFlags/GIMT_Encode2(`0`),
18272	/ 47836 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18273	/ 47839 / GIR_RootConstrainSelectedInstOperands,
18274	/ 47840 / // GIR_Coverage, 1667,
18275	/ 47840 / GIR_EraseRootFromParent_Done,
18276	/ 47841 / // Label 1323: @47841
18277	/ 47841 / GIM_Try_CheckFeatures, /On fail goto//Label 1324/ GIMT_Encode4(`47896`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1668 //
18278	/ 47848 / // MIs[0] Operand 1
18279	/ 47848 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
18280	/ 47853 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18281	/ 47857 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18282	/* 47861 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }) => (XORi:{ :[i32] } (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), 1:{ :[i32] })
18283	/ 47861 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18284	/ 47864 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
18285	/ 47868 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18286	/ 47873 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18287	/ 47877 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18288	/ 47881 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18289	/ 47883 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
18290	/ 47886 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18291	/ 47888 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18292	/ 47891 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18293	/ 47894 / GIR_RootConstrainSelectedInstOperands,
18294	/ 47895 / // GIR_Coverage, 1668,
18295	/ 47895 / GIR_EraseRootFromParent_Done,
18296	/ 47896 / // Label 1324: @47896
18297	/ 47896 / GIM_Try_CheckFeatures, /On fail goto//Label 1325/ GIMT_Encode4(`47951`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1669 //
18298	/ 47903 / // MIs[0] Operand 1
18299	/ 47903 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
18300	/ 47908 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18301	/ 47912 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18302	/* 47916 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }) => (XORi:{ :[i32] } (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), 1:{ :[i32] })
18303	/ 47916 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18304	/ 47919 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
18305	/ 47923 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18306	/ 47928 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18307	/ 47932 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18308	/ 47936 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18309	/ 47938 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
18310	/ 47941 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18311	/ 47943 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18312	/ 47946 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18313	/ 47949 / GIR_RootConstrainSelectedInstOperands,
18314	/ 47950 / // GIR_Coverage, 1669,
18315	/ 47950 / GIR_EraseRootFromParent_Done,
18316	/ 47951 / // Label 1325: @47951
18317	/ 47951 / GIM_Try_CheckFeatures, /On fail goto//Label 1326/ GIMT_Encode4(`47982`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1670 //
18318	/ 47958 / // MIs[0] Operand 1
18319	/ 47958 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
18320	/ 47963 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18321	/ 47967 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18322	/ 47971 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGT:{ :[Other] }) => (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs)*
18323	/ 47971 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLT64),
18324	/ 47974 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18325	/ 47976 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
18326	/ 47978 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18327	/ 47980 / GIR_RootConstrainSelectedInstOperands,
18328	/ 47981 / // GIR_Coverage, 1670,
18329	/ 47981 / GIR_EraseRootFromParent_Done,
18330	/ 47982 / // Label 1326: @47982
18331	/ 47982 / GIM_Try_CheckFeatures, /On fail goto//Label 1327/ GIMT_Encode4(`48013`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1671 //
18332	/ 47989 / // MIs[0] Operand 1
18333	/ 47989 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
18334	/ 47994 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18335	/ 47998 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18336	/ 48002 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGT:{ :[Other] }) => (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs)*
18337	/ 48002 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SLTu64),
18338	/ 48005 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18339	/ 48007 / GIR_RootToRootCopy, /OpIdx/`3`, // rhs
18340	/ 48009 / GIR_RootToRootCopy, /OpIdx/`2`, // lhs
18341	/ 48011 / GIR_RootConstrainSelectedInstOperands,
18342	/ 48012 / // GIR_Coverage, 1671,
18343	/ 48012 / GIR_EraseRootFromParent_Done,
18344	/ 48013 / // Label 1327: @48013
18345	/ 48013 / GIM_Try_CheckFeatures, /On fail goto//Label 1328/ GIMT_Encode4(`48068`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1672 //
18346	/ 48020 / // MIs[0] Operand 1
18347	/ 48020 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
18348	/ 48025 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18349	/ 48029 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18350	/* 48033 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }) => (XORi:{ :[i32] } (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), 1:{ :[i32] })
18351	/ 48033 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18352	/ 48036 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
18353	/ 48040 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18354	/ 48045 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18355	/ 48049 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18356	/ 48053 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18357	/ 48055 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
18358	/ 48058 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18359	/ 48060 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18360	/ 48063 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18361	/ 48066 / GIR_RootConstrainSelectedInstOperands,
18362	/ 48067 / // GIR_Coverage, 1672,
18363	/ 48067 / GIR_EraseRootFromParent_Done,
18364	/ 48068 / // Label 1328: @48068
18365	/ 48068 / GIM_Try_CheckFeatures, /On fail goto//Label 1329/ GIMT_Encode4(`48123`), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1673 //
18366	/ 48075 / // MIs[0] Operand 1
18367	/ 48075 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
18368	/ 48080 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18369	/ 48084 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18370	/* 48088 / // (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }) => (XORi:{ :[i32] } (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), 1:{ :[i32] })
18371	/ 48088 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
18372	/ 48091 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
18373	/ 48095 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18374	/ 48100 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // lhs
18375	/ 48104 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`3`, // rhs
18376	/ 48108 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
18377	/ 48110 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::XORi),
18378	/ 48113 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rt]
18379	/ 48115 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
18380	/ 48118 / GIR_AddImm8, /InsnID/`0`, /Imm/`1`,
18381	/ 48121 / GIR_RootConstrainSelectedInstOperands,
18382	/ 48122 / // GIR_Coverage, 1673,
18383	/ 48122 / GIR_EraseRootFromParent_Done,
18384	/ 48123 / // Label 1329: @48123
18385	/ 48123 / GIM_Reject,
18386	/ 48124 / // Label 1317: @48124
18387	/ 48124 / GIM_Reject,
18388	/ 48125 / // Label 1270: @48125
18389	/ 48125 / GIM_Reject,
18390	/ 48126 / // Label 1267: @48126
18391	/ 48126 / GIM_Reject,
18392	/ 48127 / // Label 42: @48127
18393	/ 48127 / GIM_Try, /On fail goto//Label 1330/ GIMT_Encode4(`49051`),
18394	/ 48132 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
18395	/ 48135 / GIM_SwitchType, /MI/`0`, /Op/`2`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1333/ GIMT_Encode4(`49050`),
18396	/ 48146 / /GILLT_s32//Label 1331/ GIMT_Encode4(`48154`),
18397	/ 48150 / /GILLT_s64//Label 1332/ GIMT_Encode4(`48602`),
18398	/ 48154 / // Label 1331: @48154
18399	/ 48154 / GIM_Try, /On fail goto//Label 1334/ GIMT_Encode4(`48601`),
18400	/ 48159 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
18401	/ 48162 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32CCRegClassID),
18402	/ 48166 / GIM_Try_CheckFeatures, /On fail goto//Label 1335/ GIMT_Encode4(`48197`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 339 //
18403	/ 48173 / // MIs[0] Operand 1
18404	/ 48173 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UNO),
18405	/ 48178 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18406	/ 48182 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18407	/ 48186 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETUO:{ :[Other] }) => (CMP_UN_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18408	/ 48186 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UN_S),
18409	/ 48189 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18410	/ 48191 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18411	/ 48193 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18412	/ 48195 / GIR_RootConstrainSelectedInstOperands,
18413	/ 48196 / // GIR_Coverage, 339,
18414	/ 48196 / GIR_EraseRootFromParent_Done,
18415	/ 48197 / // Label 1335: @48197
18416	/ 48197 / GIM_Try_CheckFeatures, /On fail goto//Label 1336/ GIMT_Encode4(`48228`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 340 //
18417	/ 48204 / // MIs[0] Operand 1
18418	/ 48204 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OEQ),
18419	/ 48209 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18420	/ 48213 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18421	/ 48217 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOEQ:{ :[Other] }) => (CMP_EQ_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18422	/ 48217 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_S),
18423	/ 48220 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18424	/ 48222 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18425	/ 48224 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18426	/ 48226 / GIR_RootConstrainSelectedInstOperands,
18427	/ 48227 / // GIR_Coverage, 340,
18428	/ 48227 / GIR_EraseRootFromParent_Done,
18429	/ 48228 / // Label 1336: @48228
18430	/ 48228 / GIM_Try_CheckFeatures, /On fail goto//Label 1337/ GIMT_Encode4(`48259`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 341 //
18431	/ 48235 / // MIs[0] Operand 1
18432	/ 48235 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UEQ),
18433	/ 48240 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18434	/ 48244 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18435	/ 48248 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETUEQ:{ :[Other] }) => (CMP_UEQ_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18436	/ 48248 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UEQ_S),
18437	/ 48251 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18438	/ 48253 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18439	/ 48255 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18440	/ 48257 / GIR_RootConstrainSelectedInstOperands,
18441	/ 48258 / // GIR_Coverage, 341,
18442	/ 48258 / GIR_EraseRootFromParent_Done,
18443	/ 48259 / // Label 1337: @48259
18444	/ 48259 / GIM_Try_CheckFeatures, /On fail goto//Label 1338/ GIMT_Encode4(`48290`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 342 //
18445	/ 48266 / // MIs[0] Operand 1
18446	/ 48266 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLT),
18447	/ 48271 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18448	/ 48275 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18449	/ 48279 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOLT:{ :[Other] }) => (CMP_LT_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18450	/ 48279 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_S),
18451	/ 48282 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18452	/ 48284 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18453	/ 48286 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18454	/ 48288 / GIR_RootConstrainSelectedInstOperands,
18455	/ 48289 / // GIR_Coverage, 342,
18456	/ 48289 / GIR_EraseRootFromParent_Done,
18457	/ 48290 / // Label 1338: @48290
18458	/ 48290 / GIM_Try_CheckFeatures, /On fail goto//Label 1339/ GIMT_Encode4(`48321`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 343 //
18459	/ 48297 / // MIs[0] Operand 1
18460	/ 48297 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULT),
18461	/ 48302 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18462	/ 48306 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18463	/ 48310 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETULT:{ :[Other] }) => (CMP_ULT_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18464	/ 48310 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULT_S),
18465	/ 48313 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18466	/ 48315 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18467	/ 48317 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18468	/ 48319 / GIR_RootConstrainSelectedInstOperands,
18469	/ 48320 / // GIR_Coverage, 343,
18470	/ 48320 / GIR_EraseRootFromParent_Done,
18471	/ 48321 / // Label 1339: @48321
18472	/ 48321 / GIM_Try_CheckFeatures, /On fail goto//Label 1340/ GIMT_Encode4(`48352`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 344 //
18473	/ 48328 / // MIs[0] Operand 1
18474	/ 48328 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLE),
18475	/ 48333 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18476	/ 48337 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18477	/ 48341 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOLE:{ :[Other] }) => (CMP_LE_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18478	/ 48341 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_S),
18479	/ 48344 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18480	/ 48346 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18481	/ 48348 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18482	/ 48350 / GIR_RootConstrainSelectedInstOperands,
18483	/ 48351 / // GIR_Coverage, 344,
18484	/ 48351 / GIR_EraseRootFromParent_Done,
18485	/ 48352 / // Label 1340: @48352
18486	/ 48352 / GIM_Try_CheckFeatures, /On fail goto//Label 1341/ GIMT_Encode4(`48383`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 345 //
18487	/ 48359 / // MIs[0] Operand 1
18488	/ 48359 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULE),
18489	/ 48364 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18490	/ 48368 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18491	/ 48372 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETULE:{ :[Other] }) => (CMP_ULE_S:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18492	/ 48372 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULE_S),
18493	/ 48375 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18494	/ 48377 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18495	/ 48379 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18496	/ 48381 / GIR_RootConstrainSelectedInstOperands,
18497	/ 48382 / // GIR_Coverage, 345,
18498	/ 48382 / GIR_EraseRootFromParent_Done,
18499	/ 48383 / // Label 1341: @48383
18500	/ 48383 / GIM_Try_CheckFeatures, /On fail goto//Label 1342/ GIMT_Encode4(`48414`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1214 //
18501	/ 48390 / // MIs[0] Operand 1
18502	/ 48390 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UNO),
18503	/ 48395 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18504	/ 48399 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18505	/ 48403 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETUO:{ :[Other] }) => (CMP_UN_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)*
18506	/ 48403 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
18507	/ 48406 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18508	/ 48408 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18509	/ 48410 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18510	/ 48412 / GIR_RootConstrainSelectedInstOperands,
18511	/ 48413 / // GIR_Coverage, 1214,
18512	/ 48413 / GIR_EraseRootFromParent_Done,
18513	/ 48414 / // Label 1342: @48414
18514	/ 48414 / GIM_Try_CheckFeatures, /On fail goto//Label 1343/ GIMT_Encode4(`48445`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1215 //
18515	/ 48421 / // MIs[0] Operand 1
18516	/ 48421 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OEQ),
18517	/ 48426 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18518	/ 48430 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18519	/* 48434 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOEQ:{ :[Other] }) => (CMP_EQ_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18520	/ 48434 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
18521	/ 48437 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18522	/ 48439 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18523	/ 48441 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18524	/ 48443 / GIR_RootConstrainSelectedInstOperands,
18525	/ 48444 / // GIR_Coverage, 1215,
18526	/ 48444 / GIR_EraseRootFromParent_Done,
18527	/ 48445 / // Label 1343: @48445
18528	/ 48445 / GIM_Try_CheckFeatures, /On fail goto//Label 1344/ GIMT_Encode4(`48476`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1216 //
18529	/ 48452 / // MIs[0] Operand 1
18530	/ 48452 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UEQ),
18531	/ 48457 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18532	/ 48461 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18533	/* 48465 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETUEQ:{ :[Other] }) => (CMP_UEQ_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18534	/ 48465 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
18535	/ 48468 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18536	/ 48470 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18537	/ 48472 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18538	/ 48474 / GIR_RootConstrainSelectedInstOperands,
18539	/ 48475 / // GIR_Coverage, 1216,
18540	/ 48475 / GIR_EraseRootFromParent_Done,
18541	/ 48476 / // Label 1344: @48476
18542	/ 48476 / GIM_Try_CheckFeatures, /On fail goto//Label 1345/ GIMT_Encode4(`48507`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1217 //
18543	/ 48483 / // MIs[0] Operand 1
18544	/ 48483 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLT),
18545	/ 48488 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18546	/ 48492 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18547	/* 48496 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOLT:{ :[Other] }) => (CMP_LT_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18548	/ 48496 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
18549	/ 48499 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18550	/ 48501 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18551	/ 48503 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18552	/ 48505 / GIR_RootConstrainSelectedInstOperands,
18553	/ 48506 / // GIR_Coverage, 1217,
18554	/ 48506 / GIR_EraseRootFromParent_Done,
18555	/ 48507 / // Label 1345: @48507
18556	/ 48507 / GIM_Try_CheckFeatures, /On fail goto//Label 1346/ GIMT_Encode4(`48538`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1218 //
18557	/ 48514 / // MIs[0] Operand 1
18558	/ 48514 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULT),
18559	/ 48519 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18560	/ 48523 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18561	/* 48527 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETULT:{ :[Other] }) => (CMP_ULT_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18562	/ 48527 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
18563	/ 48530 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18564	/ 48532 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18565	/ 48534 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18566	/ 48536 / GIR_RootConstrainSelectedInstOperands,
18567	/ 48537 / // GIR_Coverage, 1218,
18568	/ 48537 / GIR_EraseRootFromParent_Done,
18569	/ 48538 / // Label 1346: @48538
18570	/ 48538 / GIM_Try_CheckFeatures, /On fail goto//Label 1347/ GIMT_Encode4(`48569`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1219 //
18571	/ 48545 / // MIs[0] Operand 1
18572	/ 48545 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLE),
18573	/ 48550 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18574	/ 48554 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18575	/* 48558 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETOLE:{ :[Other] }) => (CMP_LE_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18576	/ 48558 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
18577	/ 48561 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18578	/ 48563 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18579	/ 48565 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18580	/ 48567 / GIR_RootConstrainSelectedInstOperands,
18581	/ 48568 / // GIR_Coverage, 1219,
18582	/ 48568 / GIR_EraseRootFromParent_Done,
18583	/ 48569 / // Label 1347: @48569
18584	/ 48569 / GIM_Try_CheckFeatures, /On fail goto//Label 1348/ GIMT_Encode4(`48600`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1220 //
18585	/ 48576 / // MIs[0] Operand 1
18586	/ 48576 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULE),
18587	/ 48581 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18588	/ 48585 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18589	/* 48589 / // (setcc:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft, SETULE:{ :[Other] }) => (CMP_ULE_S_MMR6:{ :[i32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
18590	/ 48589 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
18591	/ 48592 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18592	/ 48594 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18593	/ 48596 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18594	/ 48598 / GIR_RootConstrainSelectedInstOperands,
18595	/ 48599 / // GIR_Coverage, 1220,
18596	/ 48599 / GIR_EraseRootFromParent_Done,
18597	/ 48600 / // Label 1348: @48600
18598	/ 48600 / GIM_Reject,
18599	/ 48601 / // Label 1334: @48601
18600	/ 48601 / GIM_Reject,
18601	/ 48602 / // Label 1332: @48602
18602	/ 48602 / GIM_Try, /On fail goto//Label 1349/ GIMT_Encode4(`49049`),
18603	/ 48607 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s64,
18604	/ 48610 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64CCRegClassID),
18605	/ 48614 / GIM_Try_CheckFeatures, /On fail goto//Label 1350/ GIMT_Encode4(`48645`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 346 //
18606	/ 48621 / // MIs[0] Operand 1
18607	/ 48621 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UNO),
18608	/ 48626 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18609	/ 48630 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18610	/ 48634 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETUO:{ :[Other] }) => (CMP_UN_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18611	/ 48634 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UN_D),
18612	/ 48637 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18613	/ 48639 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18614	/ 48641 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18615	/ 48643 / GIR_RootConstrainSelectedInstOperands,
18616	/ 48644 / // GIR_Coverage, 346,
18617	/ 48644 / GIR_EraseRootFromParent_Done,
18618	/ 48645 / // Label 1350: @48645
18619	/ 48645 / GIM_Try_CheckFeatures, /On fail goto//Label 1351/ GIMT_Encode4(`48676`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 347 //
18620	/ 48652 / // MIs[0] Operand 1
18621	/ 48652 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OEQ),
18622	/ 48657 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18623	/ 48661 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18624	/ 48665 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOEQ:{ :[Other] }) => (CMP_EQ_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18625	/ 48665 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_D),
18626	/ 48668 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18627	/ 48670 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18628	/ 48672 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18629	/ 48674 / GIR_RootConstrainSelectedInstOperands,
18630	/ 48675 / // GIR_Coverage, 347,
18631	/ 48675 / GIR_EraseRootFromParent_Done,
18632	/ 48676 / // Label 1351: @48676
18633	/ 48676 / GIM_Try_CheckFeatures, /On fail goto//Label 1352/ GIMT_Encode4(`48707`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 348 //
18634	/ 48683 / // MIs[0] Operand 1
18635	/ 48683 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UEQ),
18636	/ 48688 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18637	/ 48692 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18638	/ 48696 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETUEQ:{ :[Other] }) => (CMP_UEQ_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18639	/ 48696 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UEQ_D),
18640	/ 48699 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18641	/ 48701 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18642	/ 48703 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18643	/ 48705 / GIR_RootConstrainSelectedInstOperands,
18644	/ 48706 / // GIR_Coverage, 348,
18645	/ 48706 / GIR_EraseRootFromParent_Done,
18646	/ 48707 / // Label 1352: @48707
18647	/ 48707 / GIM_Try_CheckFeatures, /On fail goto//Label 1353/ GIMT_Encode4(`48738`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 349 //
18648	/ 48714 / // MIs[0] Operand 1
18649	/ 48714 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLT),
18650	/ 48719 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18651	/ 48723 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18652	/ 48727 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOLT:{ :[Other] }) => (CMP_LT_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18653	/ 48727 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_D),
18654	/ 48730 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18655	/ 48732 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18656	/ 48734 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18657	/ 48736 / GIR_RootConstrainSelectedInstOperands,
18658	/ 48737 / // GIR_Coverage, 349,
18659	/ 48737 / GIR_EraseRootFromParent_Done,
18660	/ 48738 / // Label 1353: @48738
18661	/ 48738 / GIM_Try_CheckFeatures, /On fail goto//Label 1354/ GIMT_Encode4(`48769`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 350 //
18662	/ 48745 / // MIs[0] Operand 1
18663	/ 48745 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULT),
18664	/ 48750 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18665	/ 48754 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18666	/ 48758 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETULT:{ :[Other] }) => (CMP_ULT_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18667	/ 48758 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULT_D),
18668	/ 48761 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18669	/ 48763 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18670	/ 48765 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18671	/ 48767 / GIR_RootConstrainSelectedInstOperands,
18672	/ 48768 / // GIR_Coverage, 350,
18673	/ 48768 / GIR_EraseRootFromParent_Done,
18674	/ 48769 / // Label 1354: @48769
18675	/ 48769 / GIM_Try_CheckFeatures, /On fail goto//Label 1355/ GIMT_Encode4(`48800`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 351 //
18676	/ 48776 / // MIs[0] Operand 1
18677	/ 48776 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLE),
18678	/ 48781 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18679	/ 48785 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18680	/ 48789 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOLE:{ :[Other] }) => (CMP_LE_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18681	/ 48789 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_D),
18682	/ 48792 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18683	/ 48794 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18684	/ 48796 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18685	/ 48798 / GIR_RootConstrainSelectedInstOperands,
18686	/ 48799 / // GIR_Coverage, 351,
18687	/ 48799 / GIR_EraseRootFromParent_Done,
18688	/ 48800 / // Label 1355: @48800
18689	/ 48800 / GIM_Try_CheckFeatures, /On fail goto//Label 1356/ GIMT_Encode4(`48831`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 352 //
18690	/ 48807 / // MIs[0] Operand 1
18691	/ 48807 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULE),
18692	/ 48812 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18693	/ 48816 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18694	/ 48820 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETULE:{ :[Other] }) => (CMP_ULE_D:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18695	/ 48820 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULE_D),
18696	/ 48823 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18697	/ 48825 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18698	/ 48827 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18699	/ 48829 / GIR_RootConstrainSelectedInstOperands,
18700	/ 48830 / // GIR_Coverage, 352,
18701	/ 48830 / GIR_EraseRootFromParent_Done,
18702	/ 48831 / // Label 1356: @48831
18703	/ 48831 / GIM_Try_CheckFeatures, /On fail goto//Label 1357/ GIMT_Encode4(`48862`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1221 //
18704	/ 48838 / // MIs[0] Operand 1
18705	/ 48838 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UNO),
18706	/ 48843 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18707	/ 48847 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18708	/ 48851 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETUO:{ :[Other] }) => (CMP_UN_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)*
18709	/ 48851 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
18710	/ 48854 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18711	/ 48856 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18712	/ 48858 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18713	/ 48860 / GIR_RootConstrainSelectedInstOperands,
18714	/ 48861 / // GIR_Coverage, 1221,
18715	/ 48861 / GIR_EraseRootFromParent_Done,
18716	/ 48862 / // Label 1357: @48862
18717	/ 48862 / GIM_Try_CheckFeatures, /On fail goto//Label 1358/ GIMT_Encode4(`48893`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1222 //
18718	/ 48869 / // MIs[0] Operand 1
18719	/ 48869 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OEQ),
18720	/ 48874 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18721	/ 48878 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18722	/* 48882 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOEQ:{ :[Other] }) => (CMP_EQ_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18723	/ 48882 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
18724	/ 48885 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18725	/ 48887 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18726	/ 48889 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18727	/ 48891 / GIR_RootConstrainSelectedInstOperands,
18728	/ 48892 / // GIR_Coverage, 1222,
18729	/ 48892 / GIR_EraseRootFromParent_Done,
18730	/ 48893 / // Label 1358: @48893
18731	/ 48893 / GIM_Try_CheckFeatures, /On fail goto//Label 1359/ GIMT_Encode4(`48924`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1223 //
18732	/ 48900 / // MIs[0] Operand 1
18733	/ 48900 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_UEQ),
18734	/ 48905 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18735	/ 48909 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18736	/* 48913 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETUEQ:{ :[Other] }) => (CMP_UEQ_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18737	/ 48913 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
18738	/ 48916 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18739	/ 48918 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18740	/ 48920 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18741	/ 48922 / GIR_RootConstrainSelectedInstOperands,
18742	/ 48923 / // GIR_Coverage, 1223,
18743	/ 48923 / GIR_EraseRootFromParent_Done,
18744	/ 48924 / // Label 1359: @48924
18745	/ 48924 / GIM_Try_CheckFeatures, /On fail goto//Label 1360/ GIMT_Encode4(`48955`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1224 //
18746	/ 48931 / // MIs[0] Operand 1
18747	/ 48931 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLT),
18748	/ 48936 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18749	/ 48940 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18750	/* 48944 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOLT:{ :[Other] }) => (CMP_LT_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18751	/ 48944 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
18752	/ 48947 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18753	/ 48949 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18754	/ 48951 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18755	/ 48953 / GIR_RootConstrainSelectedInstOperands,
18756	/ 48954 / // GIR_Coverage, 1224,
18757	/ 48954 / GIR_EraseRootFromParent_Done,
18758	/ 48955 / // Label 1360: @48955
18759	/ 48955 / GIM_Try_CheckFeatures, /On fail goto//Label 1361/ GIMT_Encode4(`48986`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1225 //
18760	/ 48962 / // MIs[0] Operand 1
18761	/ 48962 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULT),
18762	/ 48967 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18763	/ 48971 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18764	/* 48975 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETULT:{ :[Other] }) => (CMP_ULT_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18765	/ 48975 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
18766	/ 48978 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18767	/ 48980 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18768	/ 48982 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18769	/ 48984 / GIR_RootConstrainSelectedInstOperands,
18770	/ 48985 / // GIR_Coverage, 1225,
18771	/ 48985 / GIR_EraseRootFromParent_Done,
18772	/ 48986 / // Label 1361: @48986
18773	/ 48986 / GIM_Try_CheckFeatures, /On fail goto//Label 1362/ GIMT_Encode4(`49017`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1226 //
18774	/ 48993 / // MIs[0] Operand 1
18775	/ 48993 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_OLE),
18776	/ 48998 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18777	/ 49002 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18778	/* 49006 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETOLE:{ :[Other] }) => (CMP_LE_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18779	/ 49006 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
18780	/ 49009 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18781	/ 49011 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18782	/ 49013 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18783	/ 49015 / GIR_RootConstrainSelectedInstOperands,
18784	/ 49016 / // GIR_Coverage, 1226,
18785	/ 49016 / GIR_EraseRootFromParent_Done,
18786	/ 49017 / // Label 1362: @49017
18787	/ 49017 / GIM_Try_CheckFeatures, /On fail goto//Label 1363/ GIMT_Encode4(`49048`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1227 //
18788	/ 49024 / // MIs[0] Operand 1
18789	/ 49024 / GIM_CheckCmpPredicate, /MI/`0`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::FCMP_ULE),
18790	/ 49029 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18791	/ 49033 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
18792	/* 49037 / // (setcc:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft, SETULE:{ :[Other] }) => (CMP_ULE_D_MMR6:{ :[i32] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
18793	/ 49037 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
18794	/ 49040 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18795	/ 49042 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
18796	/ 49044 / GIR_RootToRootCopy, /OpIdx/`3`, // ft
18797	/ 49046 / GIR_RootConstrainSelectedInstOperands,
18798	/ 49047 / // GIR_Coverage, 1227,
18799	/ 49047 / GIR_EraseRootFromParent_Done,
18800	/ 49048 / // Label 1363: @49048
18801	/ 49048 / GIM_Reject,
18802	/ 49049 / // Label 1349: @49049
18803	/ 49049 / GIM_Reject,
18804	/ 49050 / // Label 1333: @49050
18805	/ 49050 / GIM_Reject,
18806	/ 49051 / // Label 1330: @49051
18807	/ 49051 / GIM_Reject,
18808	/ 49052 / // Label 43: @49052
18809	/ 49052 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1370/ GIMT_Encode4(`58785`),
18810	/ 49063 / /GILLT_s32//Label 1364/ GIMT_Encode4(`49095`),
18811	/ 49067 / /GILLT_s64//Label 1365/ GIMT_Encode4(`54389`), GIMT_Encode4(`0`),
18812	/ 49075 / /GILLT_v16s8//Label 1366/ GIMT_Encode4(`58503`), GIMT_Encode4(`0`),
18813	/ 49083 / /GILLT_v8s16//Label 1367/ GIMT_Encode4(`58595`),
18814	/ 49087 / /GILLT_v4s32//Label 1368/ GIMT_Encode4(`58641`),
18815	/ 49091 / /GILLT_v2s64//Label 1369/ GIMT_Encode4(`58713`),
18816	/ 49095 / // Label 1364: @49095
18817	/ 49095 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1373/ GIMT_Encode4(`54388`),
18818	/ 49106 / /GILLT_s32//Label 1371/ GIMT_Encode4(`49114`),
18819	/ 49110 / /GILLT_s64//Label 1372/ GIMT_Encode4(`54303`),
18820	/ 49114 / // Label 1371: @49114
18821	/ 49114 / GIM_Try, /On fail goto//Label 1374/ GIMT_Encode4(`54302`),
18822	/ 49119 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
18823	/ 49122 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
18824	/ 49125 / GIM_Try, /On fail goto//Label 1375/ GIMT_Encode4(`49359`),
18825	/ 49130 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18826	/ 49134 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18827	/ 49138 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18828	/ 49142 / GIM_Try_CheckFeatures, /On fail goto//Label 1376/ GIMT_Encode4(`49196`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1746 //
18829	/ 49149 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18830	/ 49153 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18831	/ 49157 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
18832	/ 49161 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
18833	/ 49165 / // MIs[1] Operand 1
18834	/ 49165 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18835	/ 49170 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18836	/ 49175 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18837	/ 49179 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18838	/* 49181 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
18839	/ 49181 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
18840	/ 49184 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18841	/ 49186 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18842	/ 49188 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18843	/ 49192 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18844	/ 49194 / GIR_RootConstrainSelectedInstOperands,
18845	/ 49195 / // GIR_Coverage, 1746,
18846	/ 49195 / GIR_EraseRootFromParent_Done,
18847	/ 49196 / // Label 1376: @49196
18848	/ 49196 / GIM_Try_CheckFeatures, /On fail goto//Label 1377/ GIMT_Encode4(`49250`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1750 //
18849	/ 49203 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18850	/ 49207 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18851	/ 49211 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
18852	/ 49215 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
18853	/ 49219 / // MIs[1] Operand 1
18854	/ 49219 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18855	/ 49224 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18856	/ 49229 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18857	/ 49233 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18858	/* 49235 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
18859	/ 49235 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I),
18860	/ 49238 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18861	/ 49240 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18862	/ 49242 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18863	/ 49246 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18864	/ 49248 / GIR_RootConstrainSelectedInstOperands,
18865	/ 49249 / // GIR_Coverage, 1750,
18866	/ 49249 / GIR_EraseRootFromParent_Done,
18867	/ 49250 / // Label 1377: @49250
18868	/ 49250 / GIM_Try_CheckFeatures, /On fail goto//Label 1378/ GIMT_Encode4(`49304`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1778 //
18869	/ 49257 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18870	/ 49261 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18871	/ 49265 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
18872	/ 49269 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
18873	/ 49273 / // MIs[1] Operand 1
18874	/ 49273 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18875	/ 49278 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18876	/ 49283 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18877	/ 49287 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18878	/* 49289 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I64_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR64:{ :[i64] }:$lhs, GPR32:{ :[i32] }:$F)
18879	/ 49289 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_I),
18880	/ 49292 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18881	/ 49294 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18882	/ 49296 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18883	/ 49300 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18884	/ 49302 / GIR_RootConstrainSelectedInstOperands,
18885	/ 49303 / // GIR_Coverage, 1778,
18886	/ 49303 / GIR_EraseRootFromParent_Done,
18887	/ 49304 / // Label 1378: @49304
18888	/ 49304 / GIM_Try_CheckFeatures, /On fail goto//Label 1379/ GIMT_Encode4(`49358`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1789 //
18889	/ 49311 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18890	/ 49315 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18891	/ 49319 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
18892	/ 49323 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
18893	/ 49327 / // MIs[1] Operand 1
18894	/ 49327 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18895	/ 49332 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18896	/ 49337 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18897	/ 49341 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18898	/* 49343 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I64_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR64:{ :[i64] }:$lhs, GPR32:{ :[i32] }:$F)
18899	/ 49343 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I),
18900	/ 49346 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
18901	/ 49348 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18902	/ 49350 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18903	/ 49354 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18904	/ 49356 / GIR_RootConstrainSelectedInstOperands,
18905	/ 49357 / // GIR_Coverage, 1789,
18906	/ 49357 / GIR_EraseRootFromParent_Done,
18907	/ 49358 / // Label 1379: @49358
18908	/ 49358 / GIM_Reject,
18909	/ 49359 / // Label 1375: @49359
18910	/ 49359 / GIM_Try, /On fail goto//Label 1380/ GIMT_Encode4(`49593`),
18911	/ 49364 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18912	/ 49368 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18913	/ 49372 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
18914	/ 49376 / GIM_Try_CheckFeatures, /On fail goto//Label 1381/ GIMT_Encode4(`49430`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1802 //
18915	/ 49383 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18916	/ 49387 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18917	/ 49391 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
18918	/ 49395 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
18919	/ 49399 / // MIs[1] Operand 1
18920	/ 49399 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18921	/ 49404 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18922	/ 49409 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18923	/ 49413 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18924	/* 49415 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$lhs, FGR32:{ :[f32] }:$F)
18925	/ 49415 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
18926	/ 49418 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18927	/ 49420 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18928	/ 49422 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18929	/ 49426 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18930	/ 49428 / GIR_RootConstrainSelectedInstOperands,
18931	/ 49429 / // GIR_Coverage, 1802,
18932	/ 49429 / GIR_EraseRootFromParent_Done,
18933	/ 49430 / // Label 1381: @49430
18934	/ 49430 / GIM_Try_CheckFeatures, /On fail goto//Label 1382/ GIMT_Encode4(`49484`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1805 //
18935	/ 49437 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18936	/ 49441 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18937	/ 49445 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
18938	/ 49449 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
18939	/ 49453 / // MIs[1] Operand 1
18940	/ 49453 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18941	/ 49458 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
18942	/ 49463 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18943	/ 49467 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18944	/* 49469 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$lhs, FGR32:{ :[f32] }:$F)
18945	/ 49469 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S),
18946	/ 49472 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18947	/ 49474 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18948	/ 49476 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18949	/ 49480 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18950	/ 49482 / GIR_RootConstrainSelectedInstOperands,
18951	/ 49483 / // GIR_Coverage, 1805,
18952	/ 49483 / GIR_EraseRootFromParent_Done,
18953	/ 49484 / // Label 1382: @49484
18954	/ 49484 / GIM_Try_CheckFeatures, /On fail goto//Label 1383/ GIMT_Encode4(`49538`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1815 //
18955	/ 49491 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18956	/ 49495 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18957	/ 49499 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
18958	/ 49503 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
18959	/ 49507 / // MIs[1] Operand 1
18960	/ 49507 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
18961	/ 49512 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18962	/ 49517 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18963	/ 49521 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18964	/* 49523 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I64_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR64:{ :[i64] }:$lhs, FGR32:{ :[f32] }:$F)
18965	/ 49523 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_S),
18966	/ 49526 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18967	/ 49528 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18968	/ 49530 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18969	/ 49534 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18970	/ 49536 / GIR_RootConstrainSelectedInstOperands,
18971	/ 49537 / // GIR_Coverage, 1815,
18972	/ 49537 / GIR_EraseRootFromParent_Done,
18973	/ 49538 / // Label 1383: @49538
18974	/ 49538 / GIM_Try_CheckFeatures, /On fail goto//Label 1384/ GIMT_Encode4(`49592`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1818 //
18975	/ 49545 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
18976	/ 49549 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
18977	/ 49553 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
18978	/ 49557 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
18979	/ 49561 / // MIs[1] Operand 1
18980	/ 49561 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
18981	/ 49566 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
18982	/ 49571 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
18983	/ 49575 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
18984	/* 49577 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I64_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR64:{ :[i64] }:$lhs, FGR32:{ :[f32] }:$F)
18985	/ 49577 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_S),
18986	/ 49580 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
18987	/ 49582 / GIR_RootToRootCopy, /OpIdx/`2`, // T
18988	/ 49584 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
18989	/ 49588 / GIR_RootToRootCopy, /OpIdx/`3`, // F
18990	/ 49590 / GIR_RootConstrainSelectedInstOperands,
18991	/ 49591 / // GIR_Coverage, 1818,
18992	/ 49591 / GIR_EraseRootFromParent_Done,
18993	/ 49592 / // Label 1384: @49592
18994	/ 49592 / GIM_Reject,
18995	/ 49593 / // Label 1380: @49593
18996	/ 49593 / GIM_Try, /On fail goto//Label 1385/ GIMT_Encode4(`49719`),
18997	/ 49598 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18998	/ 49602 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18999	/ 49606 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19000	/ 49610 / GIM_Try_CheckFeatures, /On fail goto//Label 1386/ GIMT_Encode4(`49664`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2007 //
19001	/ 49617 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19002	/ 49621 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19003	/ 49625 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19004	/ 49629 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19005	/ 49633 / // MIs[1] Operand 1
19006	/ 49633 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19007	/ 49638 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19008	/ 49643 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19009	/ 49647 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19010	/* 49649 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, 0:{ :[i32] }, SETEQ:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelBeqZ:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$a)
19011	/ 49649 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelBeqZ),
19012	/ 49652 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19013	/ 49654 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19014	/ 49656 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19015	/ 49658 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19016	/ 49662 / GIR_RootConstrainSelectedInstOperands,
19017	/ 49663 / // GIR_Coverage, 2007,
19018	/ 49663 / GIR_EraseRootFromParent_Done,
19019	/ 49664 / // Label 1386: @49664
19020	/ 49664 / GIM_Try_CheckFeatures, /On fail goto//Label 1387/ GIMT_Encode4(`49718`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2010 //
19021	/ 49671 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19022	/ 49675 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19023	/ 49679 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19024	/ 49683 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19025	/ 49687 / // MIs[1] Operand 1
19026	/ 49687 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19027	/ 49692 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19028	/ 49697 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19029	/ 49701 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19030	/* 49703 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, 0:{ :[i32] }, SETNE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelBneZ:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$a)
19031	/ 49703 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelBneZ),
19032	/ 49706 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19033	/ 49708 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19034	/ 49710 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19035	/ 49712 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19036	/ 49716 / GIR_RootConstrainSelectedInstOperands,
19037	/ 49717 / // GIR_Coverage, 2010,
19038	/ 49717 / GIR_EraseRootFromParent_Done,
19039	/ 49718 / // Label 1387: @49718
19040	/ 49718 / GIM_Reject,
19041	/ 49719 / // Label 1385: @49719
19042	/ 49719 / GIM_Try, /On fail goto//Label 1388/ GIMT_Encode4(`49953`),
19043	/ 49724 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19044	/ 49728 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19045	/ 49732 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19046	/ 49736 / GIM_Try_CheckFeatures, /On fail goto//Label 1389/ GIMT_Encode4(`49790`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2354 //
19047	/ 49743 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19048	/ 49747 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19049	/ 49751 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19050	/ 49755 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19051	/ 49759 / // MIs[1] Operand 1
19052	/ 49759 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19053	/ 49764 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19054	/ 49769 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19055	/ 49773 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19056	/* 49775 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
19057	/ 49775 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
19058	/ 49778 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19059	/ 49780 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19060	/ 49782 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19061	/ 49786 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19062	/ 49788 / GIR_RootConstrainSelectedInstOperands,
19063	/ 49789 / // GIR_Coverage, 2354,
19064	/ 49789 / GIR_EraseRootFromParent_Done,
19065	/ 49790 / // Label 1389: @49790
19066	/ 49790 / GIM_Try_CheckFeatures, /On fail goto//Label 1390/ GIMT_Encode4(`49844`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2358 //
19067	/ 49797 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19068	/ 49801 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19069	/ 49805 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19070	/ 49809 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19071	/ 49813 / // MIs[1] Operand 1
19072	/ 49813 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19073	/ 49818 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19074	/ 49823 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19075	/ 49827 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19076	/* 49829 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
19077	/ 49829 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
19078	/ 49832 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19079	/ 49834 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19080	/ 49836 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19081	/ 49840 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19082	/ 49842 / GIR_RootConstrainSelectedInstOperands,
19083	/ 49843 / // GIR_Coverage, 2358,
19084	/ 49843 / GIR_EraseRootFromParent_Done,
19085	/ 49844 / // Label 1390: @49844
19086	/ 49844 / GIM_Try_CheckFeatures, /On fail goto//Label 1391/ GIMT_Encode4(`49898`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2368 //
19087	/ 49851 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19088	/ 49855 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19089	/ 49859 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19090	/ 49863 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19091	/ 49867 / // MIs[1] Operand 1
19092	/ 49867 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19093	/ 49872 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19094	/ 49877 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19095	/ 49881 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19096	/* 49883 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
19097	/ 49883 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
19098	/ 49886 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19099	/ 49888 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19100	/ 49890 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19101	/ 49894 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19102	/ 49896 / GIR_RootConstrainSelectedInstOperands,
19103	/ 49897 / // GIR_Coverage, 2368,
19104	/ 49897 / GIR_EraseRootFromParent_Done,
19105	/ 49898 / // Label 1391: @49898
19106	/ 49898 / GIM_Try_CheckFeatures, /On fail goto//Label 1392/ GIMT_Encode4(`49952`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2372 //
19107	/ 49905 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19108	/ 49909 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19109	/ 49913 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19110	/ 49917 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19111	/ 49921 / // MIs[1] Operand 1
19112	/ 49921 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19113	/ 49926 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19114	/ 49931 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19115	/ 49935 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19116	/* 49937 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$F)
19117	/ 49937 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
19118	/ 49940 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19119	/ 49942 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19120	/ 49944 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19121	/ 49948 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19122	/ 49950 / GIR_RootConstrainSelectedInstOperands,
19123	/ 49951 / // GIR_Coverage, 2372,
19124	/ 49951 / GIR_EraseRootFromParent_Done,
19125	/ 49952 / // Label 1392: @49952
19126	/ 49952 / GIM_Reject,
19127	/ 49953 / // Label 1388: @49953
19128	/ 49953 / GIM_Try, /On fail goto//Label 1393/ GIMT_Encode4(`50079`),
19129	/ 49958 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19130	/ 49962 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19131	/ 49966 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19132	/ 49970 / GIM_Try_CheckFeatures, /On fail goto//Label 1394/ GIMT_Encode4(`50024`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2415 //
19133	/ 49977 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19134	/ 49981 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19135	/ 49985 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19136	/ 49989 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19137	/ 49993 / // MIs[1] Operand 1
19138	/ 49993 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19139	/ 49998 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19140	/ 50003 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19141	/ 50007 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19142	/* 50009 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$lhs, FGR32:{ :[f32] }:$F)
19143	/ 50009 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
19144	/ 50012 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19145	/ 50014 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19146	/ 50016 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19147	/ 50020 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19148	/ 50022 / GIR_RootConstrainSelectedInstOperands,
19149	/ 50023 / // GIR_Coverage, 2415,
19150	/ 50023 / GIR_EraseRootFromParent_Done,
19151	/ 50024 / // Label 1394: @50024
19152	/ 50024 / GIM_Try_CheckFeatures, /On fail goto//Label 1395/ GIMT_Encode4(`50078`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2418 //
19153	/ 50031 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19154	/ 50035 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19155	/ 50039 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19156	/ 50043 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19157	/ 50047 / // MIs[1] Operand 1
19158	/ 50047 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19159	/ 50052 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19160	/ 50057 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
19161	/ 50061 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19162	/* 50063 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$lhs, FGR32:{ :[f32] }:$F)
19163	/ 50063 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S_MM),
19164	/ 50066 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19165	/ 50068 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19166	/ 50070 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19167	/ 50074 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19168	/ 50076 / GIR_RootConstrainSelectedInstOperands,
19169	/ 50077 / // GIR_Coverage, 2418,
19170	/ 50077 / GIR_EraseRootFromParent_Done,
19171	/ 50078 / // Label 1395: @50078
19172	/ 50078 / GIM_Reject,
19173	/ 50079 / // Label 1393: @50079
19174	/ 50079 / GIM_Try, /On fail goto//Label 1396/ GIMT_Encode4(`51009`),
19175	/ 50084 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19176	/ 50088 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19177	/ 50092 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19178	/ 50096 / GIM_Try_CheckFeatures, /On fail goto//Label 1397/ GIMT_Encode4(`50172`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1737 //
19179	/ 50103 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19180	/ 50107 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19181	/ 50111 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19182	/ 50115 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19183	/ 50119 / // MIs[1] Operand 1
19184	/ 50119 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19185	/ 50124 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19186	/ 50129 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19187	/ 50134 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19188	/* 50136 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
19189	/ 50136 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19190	/ 50139 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
19191	/ 50143 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19192	/ 50148 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19193	/ 50152 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19194	/ 50156 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19195	/ 50158 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19196	/ 50161 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19197	/ 50163 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19198	/ 50165 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19199	/ 50168 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19200	/ 50170 / GIR_RootConstrainSelectedInstOperands,
19201	/ 50171 / // GIR_Coverage, 1737,
19202	/ 50171 / GIR_EraseRootFromParent_Done,
19203	/ 50172 / // Label 1397: @50172
19204	/ 50172 / GIM_Try_CheckFeatures, /On fail goto//Label 1398/ GIMT_Encode4(`50248`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1738 //
19205	/ 50179 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19206	/ 50183 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19207	/ 50187 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19208	/ 50191 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19209	/ 50195 / // MIs[1] Operand 1
19210	/ 50195 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
19211	/ 50200 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19212	/ 50205 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19213	/ 50210 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19214	/* 50212 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
19215	/ 50212 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19216	/ 50215 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
19217	/ 50219 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19218	/ 50224 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19219	/ 50228 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19220	/ 50232 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19221	/ 50234 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19222	/ 50237 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19223	/ 50239 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19224	/ 50241 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19225	/ 50244 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19226	/ 50246 / GIR_RootConstrainSelectedInstOperands,
19227	/ 50247 / // GIR_Coverage, 1738,
19228	/ 50247 / GIR_EraseRootFromParent_Done,
19229	/ 50248 / // Label 1398: @50248
19230	/ 50248 / GIM_Try_CheckFeatures, /On fail goto//Label 1399/ GIMT_Encode4(`50324`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1741 //
19231	/ 50255 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19232	/ 50259 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19233	/ 50263 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19234	/ 50267 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19235	/ 50271 / // MIs[1] Operand 1
19236	/ 50271 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
19237	/ 50276 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19238	/ 50281 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19239	/ 50286 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19240	/* 50288 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
19241	/ 50288 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19242	/ 50291 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
19243	/ 50295 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19244	/ 50300 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19245	/ 50304 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19246	/ 50308 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19247	/ 50310 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19248	/ 50313 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19249	/ 50315 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19250	/ 50317 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19251	/ 50320 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19252	/ 50322 / GIR_RootConstrainSelectedInstOperands,
19253	/ 50323 / // GIR_Coverage, 1741,
19254	/ 50323 / GIR_EraseRootFromParent_Done,
19255	/ 50324 / // Label 1399: @50324
19256	/ 50324 / GIM_Try_CheckFeatures, /On fail goto//Label 1400/ GIMT_Encode4(`50400`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1742 //
19257	/ 50331 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19258	/ 50335 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19259	/ 50339 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19260	/ 50343 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19261	/ 50347 / // MIs[1] Operand 1
19262	/ 50347 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
19263	/ 50352 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19264	/ 50357 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19265	/ 50362 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19266	/* 50364 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
19267	/ 50364 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19268	/ 50367 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
19269	/ 50371 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19270	/ 50376 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19271	/ 50380 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19272	/ 50384 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19273	/ 50386 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19274	/ 50389 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19275	/ 50391 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19276	/ 50393 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19277	/ 50396 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19278	/ 50398 / GIR_RootConstrainSelectedInstOperands,
19279	/ 50399 / // GIR_Coverage, 1742,
19280	/ 50399 / GIR_EraseRootFromParent_Done,
19281	/ 50400 / // Label 1400: @50400
19282	/ 50400 / GIM_Try_CheckFeatures, /On fail goto//Label 1401/ GIMT_Encode4(`50476`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1745 //
19283	/ 50407 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19284	/ 50411 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19285	/ 50415 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19286	/ 50419 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19287	/ 50423 / // MIs[1] Operand 1
19288	/ 50423 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19289	/ 50428 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19290	/ 50433 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19291	/ 50438 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19292	/* 50440 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
19293	/ 50440 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19294	/ 50443 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
19295	/ 50447 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19296	/ 50452 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19297	/ 50456 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19298	/ 50460 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19299	/ 50462 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19300	/ 50465 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19301	/ 50467 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19302	/ 50469 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19303	/ 50472 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19304	/ 50474 / GIR_RootConstrainSelectedInstOperands,
19305	/ 50475 / // GIR_Coverage, 1745,
19306	/ 50475 / GIR_EraseRootFromParent_Done,
19307	/ 50476 / // Label 1401: @50476
19308	/ 50476 / GIM_Try_CheckFeatures, /On fail goto//Label 1402/ GIMT_Encode4(`50552`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1748 //
19309	/ 50483 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19310	/ 50487 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19311	/ 50491 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19312	/ 50495 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19313	/ 50499 / // MIs[1] Operand 1
19314	/ 50499 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19315	/ 50504 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19316	/ 50509 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19317	/ 50514 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19318	/* 50516 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
19319	/ 50516 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19320	/ 50519 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
19321	/ 50523 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19322	/ 50528 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19323	/ 50532 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19324	/ 50536 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19325	/ 50538 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I),
19326	/ 50541 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19327	/ 50543 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19328	/ 50545 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19329	/ 50548 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19330	/ 50550 / GIR_RootConstrainSelectedInstOperands,
19331	/ 50551 / // GIR_Coverage, 1748,
19332	/ 50551 / GIR_EraseRootFromParent_Done,
19333	/ 50552 / // Label 1402: @50552
19334	/ 50552 / GIM_Try_CheckFeatures, /On fail goto//Label 1403/ GIMT_Encode4(`50628`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1759 //
19335	/ 50559 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19336	/ 50563 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19337	/ 50567 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19338	/ 50571 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19339	/ 50575 / // MIs[1] Operand 1
19340	/ 50575 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19341	/ 50580 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19342	/ 50585 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19343	/ 50590 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19344	/* 50592 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR32:{ :[i32] }:$F)
19345	/ 50592 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19346	/ 50595 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
19347	/ 50599 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19348	/ 50604 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19349	/ 50608 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19350	/ 50612 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19351	/ 50614 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19352	/ 50617 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19353	/ 50619 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19354	/ 50621 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19355	/ 50624 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19356	/ 50626 / GIR_RootConstrainSelectedInstOperands,
19357	/ 50627 / // GIR_Coverage, 1759,
19358	/ 50627 / GIR_EraseRootFromParent_Done,
19359	/ 50628 / // Label 1403: @50628
19360	/ 50628 / GIM_Try_CheckFeatures, /On fail goto//Label 1404/ GIMT_Encode4(`50704`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1760 //
19361	/ 50635 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19362	/ 50639 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19363	/ 50643 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19364	/ 50647 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19365	/ 50651 / // MIs[1] Operand 1
19366	/ 50651 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
19367	/ 50656 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19368	/ 50661 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19369	/ 50666 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19370	/* 50668 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR32:{ :[i32] }:$F)
19371	/ 50668 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19372	/ 50671 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
19373	/ 50675 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19374	/ 50680 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19375	/ 50684 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19376	/ 50688 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19377	/ 50690 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19378	/ 50693 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19379	/ 50695 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19380	/ 50697 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19381	/ 50700 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19382	/ 50702 / GIR_RootConstrainSelectedInstOperands,
19383	/ 50703 / // GIR_Coverage, 1760,
19384	/ 50703 / GIR_EraseRootFromParent_Done,
19385	/ 50704 / // Label 1404: @50704
19386	/ 50704 / GIM_Try_CheckFeatures, /On fail goto//Label 1405/ GIMT_Encode4(`50780`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1763 //
19387	/ 50711 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19388	/ 50715 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19389	/ 50719 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19390	/ 50723 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19391	/ 50727 / // MIs[1] Operand 1
19392	/ 50727 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
19393	/ 50732 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19394	/ 50737 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19395	/ 50742 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19396	/* 50744 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), GPR32:{ :[i32] }:$F)
19397	/ 50744 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19398	/ 50747 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
19399	/ 50751 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19400	/ 50756 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19401	/ 50760 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19402	/ 50764 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19403	/ 50766 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19404	/ 50769 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19405	/ 50771 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19406	/ 50773 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19407	/ 50776 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19408	/ 50778 / GIR_RootConstrainSelectedInstOperands,
19409	/ 50779 / // GIR_Coverage, 1763,
19410	/ 50779 / GIR_EraseRootFromParent_Done,
19411	/ 50780 / // Label 1405: @50780
19412	/ 50780 / GIM_Try_CheckFeatures, /On fail goto//Label 1406/ GIMT_Encode4(`50856`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1764 //
19413	/ 50787 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19414	/ 50791 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19415	/ 50795 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19416	/ 50799 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19417	/ 50803 / // MIs[1] Operand 1
19418	/ 50803 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
19419	/ 50808 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19420	/ 50813 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19421	/ 50818 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19422	/* 50820 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), GPR32:{ :[i32] }:$F)
19423	/ 50820 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19424	/ 50823 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
19425	/ 50827 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19426	/ 50832 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19427	/ 50836 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19428	/ 50840 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19429	/ 50842 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I),
19430	/ 50845 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19431	/ 50847 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19432	/ 50849 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19433	/ 50852 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19434	/ 50854 / GIR_RootConstrainSelectedInstOperands,
19435	/ 50855 / // GIR_Coverage, 1764,
19436	/ 50855 / GIR_EraseRootFromParent_Done,
19437	/ 50856 / // Label 1406: @50856
19438	/ 50856 / GIM_Try_CheckFeatures, /On fail goto//Label 1407/ GIMT_Encode4(`50932`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1777 //
19439	/ 50863 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19440	/ 50867 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19441	/ 50871 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19442	/ 50875 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19443	/ 50879 / // MIs[1] Operand 1
19444	/ 50879 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19445	/ 50884 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19446	/ 50889 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19447	/ 50894 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19448	/* 50896 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I64_I:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR32:{ :[i32] }:$F)
19449	/ 50896 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
19450	/ 50899 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
19451	/ 50903 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19452	/ 50908 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19453	/ 50912 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19454	/ 50916 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19455	/ 50918 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_I),
19456	/ 50921 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19457	/ 50923 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19458	/ 50925 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19459	/ 50928 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19460	/ 50930 / GIR_RootConstrainSelectedInstOperands,
19461	/ 50931 / // GIR_Coverage, 1777,
19462	/ 50931 / GIR_EraseRootFromParent_Done,
19463	/ 50932 / // Label 1407: @50932
19464	/ 50932 / GIM_Try_CheckFeatures, /On fail goto//Label 1408/ GIMT_Encode4(`51008`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1787 //
19465	/ 50939 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19466	/ 50943 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19467	/ 50947 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19468	/ 50951 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19469	/ 50955 / // MIs[1] Operand 1
19470	/ 50955 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19471	/ 50960 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19472	/ 50965 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19473	/ 50970 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19474	/* 50972 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I64_I:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR32:{ :[i32] }:$F)
19475	/ 50972 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
19476	/ 50975 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
19477	/ 50979 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19478	/ 50984 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19479	/ 50988 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19480	/ 50992 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19481	/ 50994 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I),
19482	/ 50997 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
19483	/ 50999 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19484	/ 51001 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19485	/ 51004 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19486	/ 51006 / GIR_RootConstrainSelectedInstOperands,
19487	/ 51007 / // GIR_Coverage, 1787,
19488	/ 51007 / GIR_EraseRootFromParent_Done,
19489	/ 51008 / // Label 1408: @51008
19490	/ 51008 / GIM_Reject,
19491	/ 51009 / // Label 1396: @51009
19492	/ 51009 / GIM_Try, /On fail goto//Label 1409/ GIMT_Encode4(`51939`),
19493	/ 51014 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19494	/ 51018 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19495	/ 51022 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
19496	/ 51026 / GIM_Try_CheckFeatures, /On fail goto//Label 1410/ GIMT_Encode4(`51102`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1793 //
19497	/ 51033 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19498	/ 51037 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19499	/ 51041 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19500	/ 51045 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19501	/ 51049 / // MIs[1] Operand 1
19502	/ 51049 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19503	/ 51054 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19504	/ 51059 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19505	/ 51064 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19506	/* 51066 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
19507	/ 51066 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19508	/ 51069 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
19509	/ 51073 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19510	/ 51078 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19511	/ 51082 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19512	/ 51086 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19513	/ 51088 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19514	/ 51091 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19515	/ 51093 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19516	/ 51095 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19517	/ 51098 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19518	/ 51100 / GIR_RootConstrainSelectedInstOperands,
19519	/ 51101 / // GIR_Coverage, 1793,
19520	/ 51101 / GIR_EraseRootFromParent_Done,
19521	/ 51102 / // Label 1410: @51102
19522	/ 51102 / GIM_Try_CheckFeatures, /On fail goto//Label 1411/ GIMT_Encode4(`51178`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1794 //
19523	/ 51109 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19524	/ 51113 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19525	/ 51117 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19526	/ 51121 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19527	/ 51125 / // MIs[1] Operand 1
19528	/ 51125 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
19529	/ 51130 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19530	/ 51135 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19531	/ 51140 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19532	/* 51142 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
19533	/ 51142 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19534	/ 51145 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
19535	/ 51149 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19536	/ 51154 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19537	/ 51158 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19538	/ 51162 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19539	/ 51164 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19540	/ 51167 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19541	/ 51169 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19542	/ 51171 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19543	/ 51174 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19544	/ 51176 / GIR_RootConstrainSelectedInstOperands,
19545	/ 51177 / // GIR_Coverage, 1794,
19546	/ 51177 / GIR_EraseRootFromParent_Done,
19547	/ 51178 / // Label 1411: @51178
19548	/ 51178 / GIM_Try_CheckFeatures, /On fail goto//Label 1412/ GIMT_Encode4(`51254`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1797 //
19549	/ 51185 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19550	/ 51189 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19551	/ 51193 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19552	/ 51197 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19553	/ 51201 / // MIs[1] Operand 1
19554	/ 51201 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
19555	/ 51206 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19556	/ 51211 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19557	/ 51216 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19558	/* 51218 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR32:{ :[f32] }:$F)
19559	/ 51218 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19560	/ 51221 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
19561	/ 51225 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19562	/ 51230 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19563	/ 51234 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19564	/ 51238 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19565	/ 51240 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19566	/ 51243 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19567	/ 51245 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19568	/ 51247 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19569	/ 51250 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19570	/ 51252 / GIR_RootConstrainSelectedInstOperands,
19571	/ 51253 / // GIR_Coverage, 1797,
19572	/ 51253 / GIR_EraseRootFromParent_Done,
19573	/ 51254 / // Label 1412: @51254
19574	/ 51254 / GIM_Try_CheckFeatures, /On fail goto//Label 1413/ GIMT_Encode4(`51330`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1798 //
19575	/ 51261 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19576	/ 51265 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19577	/ 51269 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19578	/ 51273 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19579	/ 51277 / // MIs[1] Operand 1
19580	/ 51277 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
19581	/ 51282 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19582	/ 51287 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19583	/ 51292 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19584	/* 51294 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR32:{ :[f32] }:$F)
19585	/ 51294 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19586	/ 51297 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
19587	/ 51301 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19588	/ 51306 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19589	/ 51310 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19590	/ 51314 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19591	/ 51316 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19592	/ 51319 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19593	/ 51321 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19594	/ 51323 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19595	/ 51326 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19596	/ 51328 / GIR_RootConstrainSelectedInstOperands,
19597	/ 51329 / // GIR_Coverage, 1798,
19598	/ 51329 / GIR_EraseRootFromParent_Done,
19599	/ 51330 / // Label 1413: @51330
19600	/ 51330 / GIM_Try_CheckFeatures, /On fail goto//Label 1414/ GIMT_Encode4(`51406`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1801 //
19601	/ 51337 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19602	/ 51341 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19603	/ 51345 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19604	/ 51349 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19605	/ 51353 / // MIs[1] Operand 1
19606	/ 51353 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19607	/ 51358 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19608	/ 51363 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19609	/ 51368 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19610	/* 51370 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
19611	/ 51370 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19612	/ 51373 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
19613	/ 51377 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19614	/ 51382 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19615	/ 51386 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19616	/ 51390 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19617	/ 51392 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19618	/ 51395 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19619	/ 51397 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19620	/ 51399 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19621	/ 51402 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19622	/ 51404 / GIR_RootConstrainSelectedInstOperands,
19623	/ 51405 / // GIR_Coverage, 1801,
19624	/ 51405 / GIR_EraseRootFromParent_Done,
19625	/ 51406 / // Label 1414: @51406
19626	/ 51406 / GIM_Try_CheckFeatures, /On fail goto//Label 1415/ GIMT_Encode4(`51482`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1803 //
19627	/ 51413 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19628	/ 51417 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19629	/ 51421 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19630	/ 51425 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19631	/ 51429 / // MIs[1] Operand 1
19632	/ 51429 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19633	/ 51434 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19634	/ 51439 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19635	/ 51444 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19636	/* 51446 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
19637	/ 51446 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19638	/ 51449 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
19639	/ 51453 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19640	/ 51458 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19641	/ 51462 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19642	/ 51466 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19643	/ 51468 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S),
19644	/ 51471 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19645	/ 51473 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19646	/ 51475 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19647	/ 51478 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19648	/ 51480 / GIR_RootConstrainSelectedInstOperands,
19649	/ 51481 / // GIR_Coverage, 1803,
19650	/ 51481 / GIR_EraseRootFromParent_Done,
19651	/ 51482 / // Label 1415: @51482
19652	/ 51482 / GIM_Try_CheckFeatures, /On fail goto//Label 1416/ GIMT_Encode4(`51558`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1806 //
19653	/ 51489 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19654	/ 51493 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19655	/ 51497 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19656	/ 51501 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19657	/ 51505 / // MIs[1] Operand 1
19658	/ 51505 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19659	/ 51510 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19660	/ 51515 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19661	/ 51520 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19662	/* 51522 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR32:{ :[f32] }:$F)
19663	/ 51522 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19664	/ 51525 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
19665	/ 51529 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19666	/ 51534 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19667	/ 51538 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19668	/ 51542 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19669	/ 51544 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19670	/ 51547 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19671	/ 51549 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19672	/ 51551 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19673	/ 51554 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19674	/ 51556 / GIR_RootConstrainSelectedInstOperands,
19675	/ 51557 / // GIR_Coverage, 1806,
19676	/ 51557 / GIR_EraseRootFromParent_Done,
19677	/ 51558 / // Label 1416: @51558
19678	/ 51558 / GIM_Try_CheckFeatures, /On fail goto//Label 1417/ GIMT_Encode4(`51634`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1807 //
19679	/ 51565 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19680	/ 51569 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19681	/ 51573 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19682	/ 51577 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19683	/ 51581 / // MIs[1] Operand 1
19684	/ 51581 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
19685	/ 51586 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19686	/ 51591 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19687	/ 51596 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19688	/* 51598 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR32:{ :[f32] }:$F)
19689	/ 51598 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19690	/ 51601 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
19691	/ 51605 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19692	/ 51610 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19693	/ 51614 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19694	/ 51618 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19695	/ 51620 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19696	/ 51623 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19697	/ 51625 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19698	/ 51627 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19699	/ 51630 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19700	/ 51632 / GIR_RootConstrainSelectedInstOperands,
19701	/ 51633 / // GIR_Coverage, 1807,
19702	/ 51633 / GIR_EraseRootFromParent_Done,
19703	/ 51634 / // Label 1417: @51634
19704	/ 51634 / GIM_Try_CheckFeatures, /On fail goto//Label 1418/ GIMT_Encode4(`51710`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1810 //
19705	/ 51641 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19706	/ 51645 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19707	/ 51649 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19708	/ 51653 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19709	/ 51657 / // MIs[1] Operand 1
19710	/ 51657 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
19711	/ 51662 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19712	/ 51667 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19713	/ 51672 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19714	/* 51674 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), FGR32:{ :[f32] }:$F)
19715	/ 51674 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19716	/ 51677 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
19717	/ 51681 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19718	/ 51686 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19719	/ 51690 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19720	/ 51694 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19721	/ 51696 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19722	/ 51699 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19723	/ 51701 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19724	/ 51703 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19725	/ 51706 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19726	/ 51708 / GIR_RootConstrainSelectedInstOperands,
19727	/ 51709 / // GIR_Coverage, 1810,
19728	/ 51709 / GIR_EraseRootFromParent_Done,
19729	/ 51710 / // Label 1418: @51710
19730	/ 51710 / GIM_Try_CheckFeatures, /On fail goto//Label 1419/ GIMT_Encode4(`51786`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1811 //
19731	/ 51717 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19732	/ 51721 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19733	/ 51725 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19734	/ 51729 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19735	/ 51733 / // MIs[1] Operand 1
19736	/ 51733 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
19737	/ 51738 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19738	/ 51743 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19739	/ 51748 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19740	/* 51750 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), FGR32:{ :[f32] }:$F)
19741	/ 51750 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
19742	/ 51753 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
19743	/ 51757 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19744	/ 51762 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19745	/ 51766 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19746	/ 51770 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19747	/ 51772 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S),
19748	/ 51775 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19749	/ 51777 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19750	/ 51779 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19751	/ 51782 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19752	/ 51784 / GIR_RootConstrainSelectedInstOperands,
19753	/ 51785 / // GIR_Coverage, 1811,
19754	/ 51785 / GIR_EraseRootFromParent_Done,
19755	/ 51786 / // Label 1419: @51786
19756	/ 51786 / GIM_Try_CheckFeatures, /On fail goto//Label 1420/ GIMT_Encode4(`51862`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1814 //
19757	/ 51793 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19758	/ 51797 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19759	/ 51801 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19760	/ 51805 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19761	/ 51809 / // MIs[1] Operand 1
19762	/ 51809 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19763	/ 51814 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19764	/ 51819 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19765	/ 51824 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19766	/* 51826 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I64_S:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR32:{ :[f32] }:$F)
19767	/ 51826 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
19768	/ 51829 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
19769	/ 51833 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19770	/ 51838 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19771	/ 51842 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19772	/ 51846 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19773	/ 51848 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_S),
19774	/ 51851 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19775	/ 51853 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19776	/ 51855 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19777	/ 51858 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19778	/ 51860 / GIR_RootConstrainSelectedInstOperands,
19779	/ 51861 / // GIR_Coverage, 1814,
19780	/ 51861 / GIR_EraseRootFromParent_Done,
19781	/ 51862 / // Label 1420: @51862
19782	/ 51862 / GIM_Try_CheckFeatures, /On fail goto//Label 1421/ GIMT_Encode4(`51938`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1816 //
19783	/ 51869 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19784	/ 51873 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19785	/ 51877 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
19786	/ 51881 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
19787	/ 51885 / // MIs[1] Operand 1
19788	/ 51885 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19789	/ 51890 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19790	/ 51895 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
19791	/ 51900 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19792	/* 51902 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I64_S:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR32:{ :[f32] }:$F)
19793	/ 51902 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
19794	/ 51905 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
19795	/ 51909 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19796	/ 51914 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
19797	/ 51918 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
19798	/ 51922 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
19799	/ 51924 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_S),
19800	/ 51927 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
19801	/ 51929 / GIR_RootToRootCopy, /OpIdx/`2`, // T
19802	/ 51931 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
19803	/ 51934 / GIR_RootToRootCopy, /OpIdx/`3`, // F
19804	/ 51936 / GIR_RootConstrainSelectedInstOperands,
19805	/ 51937 / // GIR_Coverage, 1816,
19806	/ 51937 / GIR_EraseRootFromParent_Done,
19807	/ 51938 / // Label 1421: @51938
19808	/ 51938 / GIM_Reject,
19809	/ 51939 / // Label 1409: @51939
19810	/ 51939 / GIM_Try, /On fail goto//Label 1422/ GIMT_Encode4(`52429`),
19811	/ 51944 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19812	/ 51948 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19813	/ 51952 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19814	/ 51956 / GIM_Try_CheckFeatures, /On fail goto//Label 1423/ GIMT_Encode4(`52015`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1999 //
19815	/ 51963 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19816	/ 51967 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19817	/ 51971 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19818	/ 51975 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19819	/ 51979 / // MIs[1] Operand 1
19820	/ 51979 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19821	/ 51984 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19822	/ 51989 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19823	/ 51994 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19824	/* 51996 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETGE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBteqZSlt:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19825	/ 51996 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBteqZSlt),
19826	/ 51999 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19827	/ 52001 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19828	/ 52003 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19829	/ 52005 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19830	/ 52009 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19831	/ 52013 / GIR_RootConstrainSelectedInstOperands,
19832	/ 52014 / // GIR_Coverage, 1999,
19833	/ 52014 / GIR_EraseRootFromParent_Done,
19834	/ 52015 / // Label 1423: @52015
19835	/ 52015 / GIM_Try_CheckFeatures, /On fail goto//Label 1424/ GIMT_Encode4(`52074`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2000 //
19836	/ 52022 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19837	/ 52026 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19838	/ 52030 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19839	/ 52034 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19840	/ 52038 / // MIs[1] Operand 1
19841	/ 52038 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGT),
19842	/ 52043 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19843	/ 52048 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19844	/ 52053 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19845	/* 52055 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETGT:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBtneZSlt:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19846	/ 52055 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBtneZSlt),
19847	/ 52058 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19848	/ 52060 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19849	/ 52062 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19850	/ 52064 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19851	/ 52068 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19852	/ 52072 / GIR_RootConstrainSelectedInstOperands,
19853	/ 52073 / // GIR_Coverage, 2000,
19854	/ 52073 / GIR_EraseRootFromParent_Done,
19855	/ 52074 / // Label 1424: @52074
19856	/ 52074 / GIM_Try_CheckFeatures, /On fail goto//Label 1425/ GIMT_Encode4(`52133`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2001 //
19857	/ 52081 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19858	/ 52085 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19859	/ 52089 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19860	/ 52093 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19861	/ 52097 / // MIs[1] Operand 1
19862	/ 52097 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
19863	/ 52102 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19864	/ 52107 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19865	/ 52112 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19866	/* 52114 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETUGE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBteqZSltu:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19867	/ 52114 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBteqZSltu),
19868	/ 52117 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19869	/ 52119 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19870	/ 52121 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19871	/ 52123 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19872	/ 52127 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19873	/ 52131 / GIR_RootConstrainSelectedInstOperands,
19874	/ 52132 / // GIR_Coverage, 2001,
19875	/ 52132 / GIR_EraseRootFromParent_Done,
19876	/ 52133 / // Label 1425: @52133
19877	/ 52133 / GIM_Try_CheckFeatures, /On fail goto//Label 1426/ GIMT_Encode4(`52192`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2002 //
19878	/ 52140 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19879	/ 52144 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19880	/ 52148 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19881	/ 52152 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19882	/ 52156 / // MIs[1] Operand 1
19883	/ 52156 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGT),
19884	/ 52161 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19885	/ 52166 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19886	/ 52171 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19887	/* 52173 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETUGT:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBtneZSltu:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19888	/ 52173 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBtneZSltu),
19889	/ 52176 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19890	/ 52178 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19891	/ 52180 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19892	/ 52182 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19893	/ 52186 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19894	/ 52190 / GIR_RootConstrainSelectedInstOperands,
19895	/ 52191 / // GIR_Coverage, 2002,
19896	/ 52191 / GIR_EraseRootFromParent_Done,
19897	/ 52192 / // Label 1426: @52192
19898	/ 52192 / GIM_Try_CheckFeatures, /On fail goto//Label 1427/ GIMT_Encode4(`52251`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2004 //
19899	/ 52199 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19900	/ 52203 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19901	/ 52207 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19902	/ 52211 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19903	/ 52215 / // MIs[1] Operand 1
19904	/ 52215 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
19905	/ 52220 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19906	/ 52225 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19907	/ 52230 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19908	/* 52232 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETLE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBteqZSlt:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19909	/ 52232 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBteqZSlt),
19910	/ 52235 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19911	/ 52237 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19912	/ 52239 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19913	/ 52241 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19914	/ 52245 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19915	/ 52249 / GIR_RootConstrainSelectedInstOperands,
19916	/ 52250 / // GIR_Coverage, 2004,
19917	/ 52250 / GIR_EraseRootFromParent_Done,
19918	/ 52251 / // Label 1427: @52251
19919	/ 52251 / GIM_Try_CheckFeatures, /On fail goto//Label 1428/ GIMT_Encode4(`52310`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2005 //
19920	/ 52258 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19921	/ 52262 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19922	/ 52266 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19923	/ 52270 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19924	/ 52274 / // MIs[1] Operand 1
19925	/ 52274 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
19926	/ 52279 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19927	/ 52284 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19928	/ 52289 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19929	/* 52291 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETULE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBteqZSltu:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19930	/ 52291 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBteqZSltu),
19931	/ 52294 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19932	/ 52296 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19933	/ 52298 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19934	/ 52300 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19935	/ 52304 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19936	/ 52308 / GIR_RootConstrainSelectedInstOperands,
19937	/ 52309 / // GIR_Coverage, 2005,
19938	/ 52309 / GIR_EraseRootFromParent_Done,
19939	/ 52310 / // Label 1428: @52310
19940	/ 52310 / GIM_Try_CheckFeatures, /On fail goto//Label 1429/ GIMT_Encode4(`52369`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2006 //
19941	/ 52317 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19942	/ 52321 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19943	/ 52325 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19944	/ 52329 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19945	/ 52333 / // MIs[1] Operand 1
19946	/ 52333 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
19947	/ 52338 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19948	/ 52343 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19949	/ 52348 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19950	/* 52350 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETEQ:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBteqZCmp:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19951	/ 52350 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBteqZCmp),
19952	/ 52353 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19953	/ 52355 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19954	/ 52357 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19955	/ 52359 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19956	/ 52363 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19957	/ 52367 / GIR_RootConstrainSelectedInstOperands,
19958	/ 52368 / // GIR_Coverage, 2006,
19959	/ 52368 / GIR_EraseRootFromParent_Done,
19960	/ 52369 / // Label 1429: @52369
19961	/ 52369 / GIM_Try_CheckFeatures, /On fail goto//Label 1430/ GIMT_Encode4(`52428`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2009 //
19962	/ 52376 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19963	/ 52380 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19964	/ 52384 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19965	/ 52388 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19966	/ 52392 / // MIs[1] Operand 1
19967	/ 52392 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
19968	/ 52397 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19969	/ 52402 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19970	/ 52407 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19971	/* 52409 / // (select:{ :[i32] } (setcc:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$b, SETNE:{ :[Other] }), CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelTBtneZCmp:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ :[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19972	/ 52409 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelTBtneZCmp),
19973	/ 52412 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
19974	/ 52414 / GIR_RootToRootCopy, /OpIdx/`2`, // x
19975	/ 52416 / GIR_RootToRootCopy, /OpIdx/`3`, // y
19976	/ 52418 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`3`, // b
19977	/ 52422 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // a
19978	/ 52426 / GIR_RootConstrainSelectedInstOperands,
19979	/ 52427 / // GIR_Coverage, 2009,
19980	/ 52427 / GIR_EraseRootFromParent_Done,
19981	/ 52428 / // Label 1430: @52428
19982	/ 52428 / GIM_Reject,
19983	/ 52429 / // Label 1422: @52429
19984	/ 52429 / GIM_Try, /On fail goto//Label 1431/ GIMT_Encode4(`53359`),
19985	/ 52434 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19986	/ 52438 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19987	/ 52442 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19988	/ 52446 / GIM_Try_CheckFeatures, /On fail goto//Label 1432/ GIMT_Encode4(`52522`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2345 //
19989	/ 52453 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
19990	/ 52457 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
19991	/ 52461 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
19992	/ 52465 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
19993	/ 52469 / // MIs[1] Operand 1
19994	/ 52469 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
19995	/ 52474 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19996	/ 52479 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
19997	/ 52484 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
19998	/* 52486 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
19999	/ 52486 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20000	/ 52489 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20001	/ 52493 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20002	/ 52498 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20003	/ 52502 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20004	/ 52506 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20005	/ 52508 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20006	/ 52511 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20007	/ 52513 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20008	/ 52515 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20009	/ 52518 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20010	/ 52520 / GIR_RootConstrainSelectedInstOperands,
20011	/ 52521 / // GIR_Coverage, 2345,
20012	/ 52521 / GIR_EraseRootFromParent_Done,
20013	/ 52522 / // Label 1432: @52522
20014	/ 52522 / GIM_Try_CheckFeatures, /On fail goto//Label 1433/ GIMT_Encode4(`52598`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2346 //
20015	/ 52529 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20016	/ 52533 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20017	/ 52537 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20018	/ 52541 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20019	/ 52545 / // MIs[1] Operand 1
20020	/ 52545 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
20021	/ 52550 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20022	/ 52555 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20023	/ 52560 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20024	/* 52562 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20025	/ 52562 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20026	/ 52565 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20027	/ 52569 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20028	/ 52574 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20029	/ 52578 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20030	/ 52582 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20031	/ 52584 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20032	/ 52587 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20033	/ 52589 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20034	/ 52591 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20035	/ 52594 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20036	/ 52596 / GIR_RootConstrainSelectedInstOperands,
20037	/ 52597 / // GIR_Coverage, 2346,
20038	/ 52597 / GIR_EraseRootFromParent_Done,
20039	/ 52598 / // Label 1433: @52598
20040	/ 52598 / GIM_Try_CheckFeatures, /On fail goto//Label 1434/ GIMT_Encode4(`52674`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2349 //
20041	/ 52605 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20042	/ 52609 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20043	/ 52613 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20044	/ 52617 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20045	/ 52621 / // MIs[1] Operand 1
20046	/ 52621 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
20047	/ 52626 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20048	/ 52631 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20049	/ 52636 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20050	/* 52638 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
20051	/ 52638 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20052	/ 52641 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20053	/ 52645 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20054	/ 52650 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20055	/ 52654 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20056	/ 52658 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20057	/ 52660 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20058	/ 52663 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20059	/ 52665 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20060	/ 52667 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20061	/ 52670 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20062	/ 52672 / GIR_RootConstrainSelectedInstOperands,
20063	/ 52673 / // GIR_Coverage, 2349,
20064	/ 52673 / GIR_EraseRootFromParent_Done,
20065	/ 52674 / // Label 1434: @52674
20066	/ 52674 / GIM_Try_CheckFeatures, /On fail goto//Label 1435/ GIMT_Encode4(`52750`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2350 //
20067	/ 52681 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20068	/ 52685 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20069	/ 52689 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20070	/ 52693 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20071	/ 52697 / // MIs[1] Operand 1
20072	/ 52697 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
20073	/ 52702 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20074	/ 52707 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20075	/ 52712 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20076	/* 52714 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
20077	/ 52714 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20078	/ 52717 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20079	/ 52721 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20080	/ 52726 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20081	/ 52730 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20082	/ 52734 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20083	/ 52736 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20084	/ 52739 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20085	/ 52741 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20086	/ 52743 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20087	/ 52746 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20088	/ 52748 / GIR_RootConstrainSelectedInstOperands,
20089	/ 52749 / // GIR_Coverage, 2350,
20090	/ 52749 / GIR_EraseRootFromParent_Done,
20091	/ 52750 / // Label 1435: @52750
20092	/ 52750 / GIM_Try_CheckFeatures, /On fail goto//Label 1436/ GIMT_Encode4(`52826`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2353 //
20093	/ 52757 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20094	/ 52761 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20095	/ 52765 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20096	/ 52769 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20097	/ 52773 / // MIs[1] Operand 1
20098	/ 52773 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20099	/ 52778 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20100	/ 52783 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20101	/ 52788 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20102	/* 52790 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20103	/ 52790 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20104	/ 52793 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20105	/ 52797 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20106	/ 52802 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20107	/ 52806 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20108	/ 52810 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20109	/ 52812 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20110	/ 52815 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20111	/ 52817 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20112	/ 52819 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20113	/ 52822 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20114	/ 52824 / GIR_RootConstrainSelectedInstOperands,
20115	/ 52825 / // GIR_Coverage, 2353,
20116	/ 52825 / GIR_EraseRootFromParent_Done,
20117	/ 52826 / // Label 1436: @52826
20118	/ 52826 / GIM_Try_CheckFeatures, /On fail goto//Label 1437/ GIMT_Encode4(`52902`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2356 //
20119	/ 52833 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20120	/ 52837 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20121	/ 52841 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20122	/ 52845 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20123	/ 52849 / // MIs[1] Operand 1
20124	/ 52849 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20125	/ 52854 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20126	/ 52859 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20127	/ 52864 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20128	/* 52866 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20129	/ 52866 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20130	/ 52869 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20131	/ 52873 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20132	/ 52878 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20133	/ 52882 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20134	/ 52886 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20135	/ 52888 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
20136	/ 52891 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20137	/ 52893 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20138	/ 52895 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20139	/ 52898 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20140	/ 52900 / GIR_RootConstrainSelectedInstOperands,
20141	/ 52901 / // GIR_Coverage, 2356,
20142	/ 52901 / GIR_EraseRootFromParent_Done,
20143	/ 52902 / // Label 1437: @52902
20144	/ 52902 / GIM_Try_CheckFeatures, /On fail goto//Label 1438/ GIMT_Encode4(`52978`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2359 //
20145	/ 52909 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20146	/ 52913 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20147	/ 52917 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20148	/ 52921 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20149	/ 52925 / // MIs[1] Operand 1
20150	/ 52925 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
20151	/ 52930 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20152	/ 52935 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20153	/ 52940 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20154	/* 52942 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20155	/ 52942 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20156	/ 52945 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20157	/ 52949 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20158	/ 52954 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20159	/ 52958 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20160	/ 52962 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20161	/ 52964 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20162	/ 52967 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20163	/ 52969 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20164	/ 52971 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20165	/ 52974 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20166	/ 52976 / GIR_RootConstrainSelectedInstOperands,
20167	/ 52977 / // GIR_Coverage, 2359,
20168	/ 52977 / GIR_EraseRootFromParent_Done,
20169	/ 52978 / // Label 1438: @52978
20170	/ 52978 / GIM_Try_CheckFeatures, /On fail goto//Label 1439/ GIMT_Encode4(`53054`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2360 //
20171	/ 52985 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20172	/ 52989 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20173	/ 52993 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20174	/ 52997 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20175	/ 53001 / // MIs[1] Operand 1
20176	/ 53001 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
20177	/ 53006 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20178	/ 53011 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20179	/ 53016 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20180	/* 53018 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20181	/ 53018 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20182	/ 53021 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20183	/ 53025 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20184	/ 53030 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20185	/ 53034 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20186	/ 53038 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20187	/ 53040 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20188	/ 53043 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20189	/ 53045 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20190	/ 53047 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20191	/ 53050 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20192	/ 53052 / GIR_RootConstrainSelectedInstOperands,
20193	/ 53053 / // GIR_Coverage, 2360,
20194	/ 53053 / GIR_EraseRootFromParent_Done,
20195	/ 53054 / // Label 1439: @53054
20196	/ 53054 / GIM_Try_CheckFeatures, /On fail goto//Label 1440/ GIMT_Encode4(`53130`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2363 //
20197	/ 53061 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20198	/ 53065 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20199	/ 53069 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20200	/ 53073 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20201	/ 53077 / // MIs[1] Operand 1
20202	/ 53077 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
20203	/ 53082 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20204	/ 53087 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20205	/ 53092 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20206	/* 53094 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
20207	/ 53094 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20208	/ 53097 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20209	/ 53101 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20210	/ 53106 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20211	/ 53110 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20212	/ 53114 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20213	/ 53116 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20214	/ 53119 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20215	/ 53121 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20216	/ 53123 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20217	/ 53126 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20218	/ 53128 / GIR_RootConstrainSelectedInstOperands,
20219	/ 53129 / // GIR_Coverage, 2363,
20220	/ 53129 / GIR_EraseRootFromParent_Done,
20221	/ 53130 / // Label 1440: @53130
20222	/ 53130 / GIM_Try_CheckFeatures, /On fail goto//Label 1441/ GIMT_Encode4(`53206`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2364 //
20223	/ 53137 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20224	/ 53141 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20225	/ 53145 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20226	/ 53149 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20227	/ 53153 / // MIs[1] Operand 1
20228	/ 53153 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
20229	/ 53158 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20230	/ 53163 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20231	/ 53168 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20232	/* 53170 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR32:{ :[i32] }:$F)
20233	/ 53170 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20234	/ 53173 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20235	/ 53177 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20236	/ 53182 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20237	/ 53186 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20238	/ 53190 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20239	/ 53192 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20240	/ 53195 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20241	/ 53197 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20242	/ 53199 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20243	/ 53202 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20244	/ 53204 / GIR_RootConstrainSelectedInstOperands,
20245	/ 53205 / // GIR_Coverage, 2364,
20246	/ 53205 / GIR_EraseRootFromParent_Done,
20247	/ 53206 / // Label 1441: @53206
20248	/ 53206 / GIM_Try_CheckFeatures, /On fail goto//Label 1442/ GIMT_Encode4(`53282`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2367 //
20249	/ 53213 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20250	/ 53217 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20251	/ 53221 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20252	/ 53225 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20253	/ 53229 / // MIs[1] Operand 1
20254	/ 53229 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20255	/ 53234 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20256	/ 53239 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20257	/ 53244 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20258	/* 53246 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVZ_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20259	/ 53246 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20260	/ 53249 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20261	/ 53253 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20262	/ 53258 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20263	/ 53262 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20264	/ 53266 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20265	/ 53268 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_MM),
20266	/ 53271 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20267	/ 53273 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20268	/ 53275 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20269	/ 53278 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20270	/ 53280 / GIR_RootConstrainSelectedInstOperands,
20271	/ 53281 / // GIR_Coverage, 2367,
20272	/ 53281 / GIR_EraseRootFromParent_Done,
20273	/ 53282 / // Label 1442: @53282
20274	/ 53282 / GIM_Try_CheckFeatures, /On fail goto//Label 1443/ GIMT_Encode4(`53358`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2370 //
20275	/ 53289 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20276	/ 53293 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20277	/ 53297 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20278	/ 53301 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20279	/ 53305 / // MIs[1] Operand 1
20280	/ 53305 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20281	/ 53310 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20282	/ 53315 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20283	/ 53320 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20284	/* 53322 / // (select:{ :[i32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR32:{ :[i32] }:$F)
20285	/ 53322 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20286	/ 53325 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20287	/ 53329 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20288	/ 53334 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20289	/ 53338 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20290	/ 53342 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20291	/ 53344 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
20292	/ 53347 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20293	/ 53349 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20294	/ 53351 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20295	/ 53354 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20296	/ 53356 / GIR_RootConstrainSelectedInstOperands,
20297	/ 53357 / // GIR_Coverage, 2370,
20298	/ 53357 / GIR_EraseRootFromParent_Done,
20299	/ 53358 / // Label 1443: @53358
20300	/ 53358 / GIM_Reject,
20301	/ 53359 / // Label 1431: @53359
20302	/ 53359 / GIM_Try, /On fail goto//Label 1444/ GIMT_Encode4(`53833`),
20303	/ 53364 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20304	/ 53368 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20305	/ 53372 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20306	/ 53376 / GIM_Try_CheckFeatures, /On fail goto//Label 1445/ GIMT_Encode4(`53452`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2406 //
20307	/ 53383 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20308	/ 53387 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20309	/ 53391 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20310	/ 53395 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20311	/ 53399 / // MIs[1] Operand 1
20312	/ 53399 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
20313	/ 53404 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20314	/ 53409 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20315	/ 53414 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20316	/* 53416 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
20317	/ 53416 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20318	/ 53419 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20319	/ 53423 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20320	/ 53428 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20321	/ 53432 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20322	/ 53436 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20323	/ 53438 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20324	/ 53441 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20325	/ 53443 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20326	/ 53445 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20327	/ 53448 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20328	/ 53450 / GIR_RootConstrainSelectedInstOperands,
20329	/ 53451 / // GIR_Coverage, 2406,
20330	/ 53451 / GIR_EraseRootFromParent_Done,
20331	/ 53452 / // Label 1445: @53452
20332	/ 53452 / GIM_Try_CheckFeatures, /On fail goto//Label 1446/ GIMT_Encode4(`53528`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2407 //
20333	/ 53459 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20334	/ 53463 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20335	/ 53467 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20336	/ 53471 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20337	/ 53475 / // MIs[1] Operand 1
20338	/ 53475 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
20339	/ 53480 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20340	/ 53485 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20341	/ 53490 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20342	/* 53492 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
20343	/ 53492 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20344	/ 53495 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20345	/ 53499 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20346	/ 53504 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20347	/ 53508 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20348	/ 53512 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20349	/ 53514 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20350	/ 53517 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20351	/ 53519 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20352	/ 53521 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20353	/ 53524 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20354	/ 53526 / GIR_RootConstrainSelectedInstOperands,
20355	/ 53527 / // GIR_Coverage, 2407,
20356	/ 53527 / GIR_EraseRootFromParent_Done,
20357	/ 53528 / // Label 1446: @53528
20358	/ 53528 / GIM_Try_CheckFeatures, /On fail goto//Label 1447/ GIMT_Encode4(`53604`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2410 //
20359	/ 53535 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20360	/ 53539 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20361	/ 53543 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20362	/ 53547 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20363	/ 53551 / // MIs[1] Operand 1
20364	/ 53551 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
20365	/ 53556 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20366	/ 53561 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20367	/ 53566 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20368	/* 53568 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR32:{ :[f32] }:$F)
20369	/ 53568 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20370	/ 53571 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
20371	/ 53575 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20372	/ 53580 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20373	/ 53584 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20374	/ 53588 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20375	/ 53590 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20376	/ 53593 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20377	/ 53595 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20378	/ 53597 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20379	/ 53600 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20380	/ 53602 / GIR_RootConstrainSelectedInstOperands,
20381	/ 53603 / // GIR_Coverage, 2410,
20382	/ 53603 / GIR_EraseRootFromParent_Done,
20383	/ 53604 / // Label 1447: @53604
20384	/ 53604 / GIM_Try_CheckFeatures, /On fail goto//Label 1448/ GIMT_Encode4(`53680`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2411 //
20385	/ 53611 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20386	/ 53615 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20387	/ 53619 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20388	/ 53623 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20389	/ 53627 / // MIs[1] Operand 1
20390	/ 53627 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
20391	/ 53632 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20392	/ 53637 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20393	/ 53642 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20394	/* 53644 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR32:{ :[f32] }:$F)
20395	/ 53644 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20396	/ 53647 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
20397	/ 53651 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20398	/ 53656 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20399	/ 53660 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20400	/ 53664 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20401	/ 53666 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20402	/ 53669 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20403	/ 53671 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20404	/ 53673 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20405	/ 53676 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20406	/ 53678 / GIR_RootConstrainSelectedInstOperands,
20407	/ 53679 / // GIR_Coverage, 2411,
20408	/ 53679 / GIR_EraseRootFromParent_Done,
20409	/ 53680 / // Label 1448: @53680
20410	/ 53680 / GIM_Try_CheckFeatures, /On fail goto//Label 1449/ GIMT_Encode4(`53756`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2414 //
20411	/ 53687 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20412	/ 53691 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20413	/ 53695 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20414	/ 53699 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20415	/ 53703 / // MIs[1] Operand 1
20416	/ 53703 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20417	/ 53708 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20418	/ 53713 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20419	/ 53718 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20420	/* 53720 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVZ_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
20421	/ 53720 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20422	/ 53723 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20423	/ 53727 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20424	/ 53732 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20425	/ 53736 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20426	/ 53740 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20427	/ 53742 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20428	/ 53745 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20429	/ 53747 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20430	/ 53749 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20431	/ 53752 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20432	/ 53754 / GIR_RootConstrainSelectedInstOperands,
20433	/ 53755 / // GIR_Coverage, 2414,
20434	/ 53755 / GIR_EraseRootFromParent_Done,
20435	/ 53756 / // Label 1449: @53756
20436	/ 53756 / GIM_Try_CheckFeatures, /On fail goto//Label 1450/ GIMT_Encode4(`53832`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2416 //
20437	/ 53763 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20438	/ 53767 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20439	/ 53771 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20440	/ 53775 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20441	/ 53779 / // MIs[1] Operand 1
20442	/ 53779 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20443	/ 53784 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20444	/ 53789 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20445	/ 53794 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20446	/* 53796 / // (select:{ :[f32] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR32:{ :[f32] }:$F)
20447	/ 53796 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20448	/ 53799 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
20449	/ 53803 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20450	/ 53808 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20451	/ 53812 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20452	/ 53816 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20453	/ 53818 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S_MM),
20454	/ 53821 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20455	/ 53823 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20456	/ 53825 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20457	/ 53828 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20458	/ 53830 / GIR_RootConstrainSelectedInstOperands,
20459	/ 53831 / // GIR_Coverage, 2416,
20460	/ 53831 / GIR_EraseRootFromParent_Done,
20461	/ 53832 / // Label 1450: @53832
20462	/ 53832 / GIM_Reject,
20463	/ 53833 / // Label 1444: @53833
20464	/ 53833 / GIM_Try_CheckFeatures, /On fail goto//Label 1451/ GIMT_Encode4(`53863`), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 322 //
20465	/ 53840 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20466	/ 53844 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20467	/ 53848 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20468	/ 53852 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20469	/* 53856 / // (select:{ :[i32] } GPR32Opnd:{ :[i32] }:$cond, GPR32Opnd:{ :[i32] }:$T, GPR32Opnd:{ :[i32] }:$F) => (PseudoSELECT_I:{ :[i32] } GPR32Opnd:{ :[i32] }:$cond, GPR32Opnd:{ :[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
20470	/ 53856 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoSELECT_I),
20471	/ 53861 / GIR_RootConstrainSelectedInstOperands,
20472	/ 53862 / // GIR_Coverage, 322,
20473	/ 53862 / GIR_Done,
20474	/ 53863 / // Label 1451: @53863
20475	/ 53863 / GIM_Try, /On fail goto//Label 1452/ GIMT_Encode4(`53957`),
20476	/ 53868 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20477	/ 53872 / GIM_Try_CheckFeatures, /On fail goto//Label 1453/ GIMT_Encode4(`53898`), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 324 //
20478	/ 53879 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20479	/ 53883 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20480	/ 53887 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20481	/* 53891 / // (select:{ :[f32] } GPR32Opnd:{ :[i32] }:$cond, FGR32Opnd:{ :[f32] }:$T, FGR32Opnd:{ :[f32] }:$F) => (PseudoSELECT_S:{ :[f32] } GPR32Opnd:{ :[i32] }:$cond, FGR32Opnd:{ :[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
20482	/ 53891 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoSELECT_S),
20483	/ 53896 / GIR_RootConstrainSelectedInstOperands,
20484	/ 53897 / // GIR_Coverage, 324,
20485	/ 53897 / GIR_Done,
20486	/ 53898 / // Label 1453: @53898
20487	/ 53898 / GIM_Try, /On fail goto//Label 1454/ GIMT_Encode4(`53956`),
20488	/ 53903 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32CCRegClassID),
20489	/ 53907 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20490	/ 53911 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20491	/ 53915 / GIM_Try_CheckFeatures, /On fail goto//Label 1455/ GIMT_Encode4(`53935`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 361 //
20492	/* 53922 / // (select:{ :[f32] } FGR32CCOpnd:{ :[i32] }:$fd_in, FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs) => (SEL_S:{ :[f32] } FGR32CCOpnd:{ :[i32] }:$fd_in, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20493	/ 53922 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEL_S),
20494	/ 53925 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20495	/ 53927 / GIR_RootToRootCopy, /OpIdx/`1`, // fd_in
20496	/ 53929 / GIR_RootToRootCopy, /OpIdx/`3`, // fs
20497	/ 53931 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
20498	/ 53933 / GIR_RootConstrainSelectedInstOperands,
20499	/ 53934 / // GIR_Coverage, 361,
20500	/ 53934 / GIR_EraseRootFromParent_Done,
20501	/ 53935 / // Label 1455: @53935
20502	/ 53935 / GIM_Try_CheckFeatures, /On fail goto//Label 1456/ GIMT_Encode4(`53955`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1234 //
20503	/* 53942 / // (select:{ :[f32] } FGR32CCOpnd:{ :[i32] }:$fd_in, FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs) => (SEL_S_MMR6:{ :[f32] } FGR32CCOpnd:{ :[i32] }:$fd_in, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20504	/ 53942 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEL_S_MMR6),
20505	/ 53945 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20506	/ 53947 / GIR_RootToRootCopy, /OpIdx/`1`, // fd_in
20507	/ 53949 / GIR_RootToRootCopy, /OpIdx/`3`, // fs
20508	/ 53951 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
20509	/ 53953 / GIR_RootConstrainSelectedInstOperands,
20510	/ 53954 / // GIR_Coverage, 1234,
20511	/ 53954 / GIR_EraseRootFromParent_Done,
20512	/ 53955 / // Label 1456: @53955
20513	/ 53955 / GIM_Reject,
20514	/ 53956 / // Label 1454: @53956
20515	/ 53956 / GIM_Reject,
20516	/ 53957 / // Label 1452: @53957
20517	/ 53957 / GIM_Try_CheckFeatures, /On fail goto//Label 1457/ GIMT_Encode4(`53993`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1749 //
20518	/ 53964 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20519	/ 53968 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20520	/ 53972 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20521	/ 53976 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20522	/* 53980 / // (select:{ :[i32] } GPR32:{ :[i32] }:$cond, GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20523	/ 53980 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I),
20524	/ 53983 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20525	/ 53985 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20526	/ 53987 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20527	/ 53989 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20528	/ 53991 / GIR_RootConstrainSelectedInstOperands,
20529	/ 53992 / // GIR_Coverage, 1749,
20530	/ 53992 / GIR_EraseRootFromParent_Done,
20531	/ 53993 / // Label 1457: @53993
20532	/ 53993 / GIM_Try_CheckFeatures, /On fail goto//Label 1458/ GIMT_Encode4(`54029`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1804 //
20533	/ 54000 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20534	/ 54004 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20535	/ 54008 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20536	/ 54012 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20537	/* 54016 / // (select:{ :[f32] } GPR32:{ :[i32] }:$cond, FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20538	/ 54016 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S),
20539	/ 54019 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20540	/ 54021 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20541	/ 54023 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20542	/ 54025 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20543	/ 54027 / GIR_RootConstrainSelectedInstOperands,
20544	/ 54028 / // GIR_Coverage, 1804,
20545	/ 54028 / GIR_EraseRootFromParent_Done,
20546	/ 54029 / // Label 1458: @54029
20547	/ 54029 / GIM_Try_CheckFeatures, /On fail goto//Label 1459/ GIMT_Encode4(`54065`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2011 //
20548	/ 54036 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20549	/ 54040 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20550	/ 54044 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20551	/ 54048 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20552	/* 54052 / // (select:{ :[i32] } CPU16Regs:{ :[i32] }:$a, CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y) => (SelBneZ:{ :[i32] } CPU16Regs:{ :[i32] }:$x, CPU16Regs:{ :[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20553	/ 54052 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SelBneZ),
20554	/ 54055 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd_]
20555	/ 54057 / GIR_RootToRootCopy, /OpIdx/`2`, // x
20556	/ 54059 / GIR_RootToRootCopy, /OpIdx/`3`, // y
20557	/ 54061 / GIR_RootToRootCopy, /OpIdx/`1`, // a
20558	/ 54063 / GIR_RootConstrainSelectedInstOperands,
20559	/ 54064 / // GIR_Coverage, 2011,
20560	/ 54064 / GIR_EraseRootFromParent_Done,
20561	/ 54065 / // Label 1459: @54065
20562	/ 54065 / GIM_Try, /On fail goto//Label 1460/ GIMT_Encode4(`54127`),
20563	/ 54070 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20564	/ 54074 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20565	/ 54078 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20566	/ 54082 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20567	/ 54086 / GIM_Try_CheckFeatures, /On fail goto//Label 1461/ GIMT_Encode4(`54106`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2357 //
20568	/* 54093 / // (select:{ :[i32] } GPR32:{ :[i32] }:$cond, GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20569	/ 54093 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
20570	/ 54096 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20571	/ 54098 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20572	/ 54100 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20573	/ 54102 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20574	/ 54104 / GIR_RootConstrainSelectedInstOperands,
20575	/ 54105 / // GIR_Coverage, 2357,
20576	/ 54105 / GIR_EraseRootFromParent_Done,
20577	/ 54106 / // Label 1461: @54106
20578	/ 54106 / GIM_Try_CheckFeatures, /On fail goto//Label 1462/ GIMT_Encode4(`54126`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2371 //
20579	/* 54113 / // (select:{ :[i32] } GPR32:{ :[i32] }:$cond, GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I_MM:{ :[i32] } GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20580	/ 54113 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_MM),
20581	/ 54116 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20582	/ 54118 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20583	/ 54120 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20584	/ 54122 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20585	/ 54124 / GIR_RootConstrainSelectedInstOperands,
20586	/ 54125 / // GIR_Coverage, 2371,
20587	/ 54125 / GIR_EraseRootFromParent_Done,
20588	/ 54126 / // Label 1462: @54126
20589	/ 54126 / GIM_Reject,
20590	/ 54127 / // Label 1460: @54127
20591	/ 54127 / GIM_Try_CheckFeatures, /On fail goto//Label 1463/ GIMT_Encode4(`54163`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2417 //
20592	/ 54134 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20593	/ 54138 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20594	/ 54142 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20595	/ 54146 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20596	/* 54150 / // (select:{ :[f32] } GPR32:{ :[i32] }:$cond, FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I_S_MM:{ :[f32] } FGR32:{ :[f32] }:$T, GPR32:{ :[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20597	/ 54150 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_S_MM),
20598	/ 54153 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20599	/ 54155 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20600	/ 54157 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20601	/ 54159 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20602	/ 54161 / GIR_RootConstrainSelectedInstOperands,
20603	/ 54162 / // GIR_Coverage, 2417,
20604	/ 54162 / GIR_EraseRootFromParent_Done,
20605	/ 54163 / // Label 1463: @54163
20606	/ 54163 / GIM_Try, /On fail goto//Label 1464/ GIMT_Encode4(`54301`),
20607	/ 54168 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20608	/ 54172 / GIM_Try_CheckFeatures, /On fail goto//Label 1465/ GIMT_Encode4(`54236`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1878 //
20609	/* 54179 / // (select:{ :[i32] } i32:{ :[i32] }:$cond, i32:{ :[i32] }:$t, i32:{ :[i32] }:$f) => (OR:{ :[i32] } (SELNEZ:{ :[i32] } i32:{ :[i32] }:$t, i32:{ :[i32] }:$cond), (SELEQZ:{ :[i32] } i32:{ :[i32] }:$f, i32:{ :[i32] }:$cond))
20610	/ 54179 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
20611	/ 54182 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SELEQZ),
20612	/ 54186 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20613	/ 54191 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`3`, // f
20614	/ 54195 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // cond
20615	/ 54199 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
20616	/ 54201 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20617	/ 54204 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SELNEZ),
20618	/ 54208 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20619	/ 54213 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // t
20620	/ 54217 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // cond
20621	/ 54221 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20622	/ 54223 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::OR),
20623	/ 54226 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20624	/ 54228 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20625	/ 54231 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
20626	/ 54234 / GIR_RootConstrainSelectedInstOperands,
20627	/ 54235 / // GIR_Coverage, 1878,
20628	/ 54235 / GIR_EraseRootFromParent_Done,
20629	/ 54236 / // Label 1465: @54236
20630	/ 54236 / GIM_Try_CheckFeatures, /On fail goto//Label 1466/ GIMT_Encode4(`54300`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2434 //
20631	/* 54243 / // (select:{ :[i32] } i32:{ :[i32] }:$cond, i32:{ :[i32] }:$t, i32:{ :[i32] }:$f) => (OR_MM:{ :[i32] } (SELNEZ_MMR6:{ :[i32] } i32:{ :[i32] }:$t, i32:{ :[i32] }:$cond), (SELEQZ_MMR6:{ :[i32] } i32:{ :[i32] }:$f, i32:{ :[i32] }:$cond))
20632	/ 54243 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s32,
20633	/ 54246 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SELEQZ_MMR6),
20634	/ 54250 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20635	/ 54255 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`3`, // f
20636	/ 54259 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // cond
20637	/ 54263 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
20638	/ 54265 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20639	/ 54268 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SELNEZ_MMR6),
20640	/ 54272 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20641	/ 54277 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // t
20642	/ 54281 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // cond
20643	/ 54285 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20644	/ 54287 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::OR_MM),
20645	/ 54290 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20646	/ 54292 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20647	/ 54295 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
20648	/ 54298 / GIR_RootConstrainSelectedInstOperands,
20649	/ 54299 / // GIR_Coverage, 2434,
20650	/ 54299 / GIR_EraseRootFromParent_Done,
20651	/ 54300 / // Label 1466: @54300
20652	/ 54300 / GIM_Reject,
20653	/ 54301 / // Label 1464: @54301
20654	/ 54301 / GIM_Reject,
20655	/ 54302 / // Label 1374: @54302
20656	/ 54302 / GIM_Reject,
20657	/ 54303 / // Label 1372: @54303
20658	/ 54303 / GIM_Try, /On fail goto//Label 1467/ GIMT_Encode4(`54387`),
20659	/ 54308 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
20660	/ 54311 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s32,
20661	/ 54314 / GIM_Try_CheckFeatures, /On fail goto//Label 1468/ GIMT_Encode4(`54350`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1788 //
20662	/ 54321 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20663	/ 54325 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20664	/ 54329 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20665	/ 54333 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20666	/* 54337 / // (select:{ :[i32] } GPR64:{ :[i64] }:$cond, GPR32:{ :[i32] }:$T, GPR32:{ :[i32] }:$F) => (MOVN_I64_I:{ :[i32] } GPR32:{ :[i32] }:$T, GPR64:{ :[i64] }:$cond, GPR32:{ *:[i32] }:$F)
20667	/ 54337 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I),
20668	/ 54340 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20669	/ 54342 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20670	/ 54344 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20671	/ 54346 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20672	/ 54348 / GIR_RootConstrainSelectedInstOperands,
20673	/ 54349 / // GIR_Coverage, 1788,
20674	/ 54349 / GIR_EraseRootFromParent_Done,
20675	/ 54350 / // Label 1468: @54350
20676	/ 54350 / GIM_Try_CheckFeatures, /On fail goto//Label 1469/ GIMT_Encode4(`54386`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1817 //
20677	/ 54357 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20678	/ 54361 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20679	/ 54365 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20680	/ 54369 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
20681	/* 54373 / // (select:{ :[f32] } GPR64:{ :[i64] }:$cond, FGR32:{ :[f32] }:$T, FGR32:{ :[f32] }:$F) => (MOVN_I64_S:{ :[f32] } FGR32:{ :[f32] }:$T, GPR64:{ :[i64] }:$cond, FGR32:{ *:[f32] }:$F)
20682	/ 54373 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_S),
20683	/ 54376 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20684	/ 54378 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20685	/ 54380 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
20686	/ 54382 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20687	/ 54384 / GIR_RootConstrainSelectedInstOperands,
20688	/ 54385 / // GIR_Coverage, 1817,
20689	/ 54385 / GIR_EraseRootFromParent_Done,
20690	/ 54386 / // Label 1469: @54386
20691	/ 54386 / GIM_Reject,
20692	/ 54387 / // Label 1467: @54387
20693	/ 54387 / GIM_Reject,
20694	/ 54388 / // Label 1373: @54388
20695	/ 54388 / GIM_Reject,
20696	/ 54389 / // Label 1365: @54389
20697	/ 54389 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1472/ GIMT_Encode4(`58502`),
20698	/ 54400 / /GILLT_s32//Label 1470/ GIMT_Encode4(`54408`),
20699	/ 54404 / /GILLT_s64//Label 1471/ GIMT_Encode4(`58349`),
20700	/ 54408 / // Label 1470: @54408
20701	/ 54408 / GIM_Try, /On fail goto//Label 1473/ GIMT_Encode4(`58348`),
20702	/ 54413 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
20703	/ 54416 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s64,
20704	/ 54419 / GIM_Try, /On fail goto//Label 1474/ GIMT_Encode4(`54653`),
20705	/ 54424 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20706	/ 54428 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20707	/ 54432 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20708	/ 54436 / GIM_Try_CheckFeatures, /On fail goto//Label 1475/ GIMT_Encode4(`54490`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1776 //
20709	/ 54443 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20710	/ 54447 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20711	/ 54451 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20712	/ 54455 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20713	/ 54459 / // MIs[1] Operand 1
20714	/ 54459 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20715	/ 54464 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20716	/ 54469 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20717	/ 54473 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20718	/* 54475 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR32:{ :[i32] }:$lhs, GPR64:{ :[i64] }:$F)
20719	/ 54475 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
20720	/ 54478 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20721	/ 54480 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20722	/ 54482 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20723	/ 54486 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20724	/ 54488 / GIR_RootConstrainSelectedInstOperands,
20725	/ 54489 / // GIR_Coverage, 1776,
20726	/ 54489 / GIR_EraseRootFromParent_Done,
20727	/ 54490 / // Label 1475: @54490
20728	/ 54490 / GIM_Try_CheckFeatures, /On fail goto//Label 1476/ GIMT_Encode4(`54544`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1780 //
20729	/ 54497 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20730	/ 54501 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20731	/ 54505 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
20732	/ 54509 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
20733	/ 54513 / // MIs[1] Operand 1
20734	/ 54513 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20735	/ 54518 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20736	/ 54523 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20737	/ 54527 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20738	/* 54529 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I64_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$F)
20739	/ 54529 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_I64),
20740	/ 54532 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20741	/ 54534 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20742	/ 54536 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20743	/ 54540 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20744	/ 54542 / GIR_RootConstrainSelectedInstOperands,
20745	/ 54543 / // GIR_Coverage, 1780,
20746	/ 54543 / GIR_EraseRootFromParent_Done,
20747	/ 54544 / // Label 1476: @54544
20748	/ 54544 / GIM_Try_CheckFeatures, /On fail goto//Label 1477/ GIMT_Encode4(`54598`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1786 //
20749	/ 54551 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20750	/ 54555 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20751	/ 54559 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20752	/ 54563 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20753	/ 54567 / // MIs[1] Operand 1
20754	/ 54567 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20755	/ 54572 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20756	/ 54577 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20757	/ 54581 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20758	/* 54583 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR32:{ :[i32] }:$lhs, GPR64:{ :[i64] }:$F)
20759	/ 54583 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I64),
20760	/ 54586 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20761	/ 54588 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20762	/ 54590 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20763	/ 54594 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20764	/ 54596 / GIR_RootConstrainSelectedInstOperands,
20765	/ 54597 / // GIR_Coverage, 1786,
20766	/ 54597 / GIR_EraseRootFromParent_Done,
20767	/ 54598 / // Label 1477: @54598
20768	/ 54598 / GIM_Try_CheckFeatures, /On fail goto//Label 1478/ GIMT_Encode4(`54652`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1792 //
20769	/ 54605 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20770	/ 54609 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20771	/ 54613 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
20772	/ 54617 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
20773	/ 54621 / // MIs[1] Operand 1
20774	/ 54621 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20775	/ 54626 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20776	/ 54631 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20777	/ 54635 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20778	/* 54637 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I64_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$F)
20779	/ 54637 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I64),
20780	/ 54640 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20781	/ 54642 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20782	/ 54644 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20783	/ 54648 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20784	/ 54650 / GIR_RootConstrainSelectedInstOperands,
20785	/ 54651 / // GIR_Coverage, 1792,
20786	/ 54651 / GIR_EraseRootFromParent_Done,
20787	/ 54652 / // Label 1478: @54652
20788	/ 54652 / GIM_Reject,
20789	/ 54653 / // Label 1474: @54653
20790	/ 54653 / GIM_Try, /On fail goto//Label 1479/ GIMT_Encode4(`54779`),
20791	/ 54658 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20792	/ 54662 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20793	/ 54666 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20794	/ 54670 / GIM_Try_CheckFeatures, /On fail goto//Label 1480/ GIMT_Encode4(`54724`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1828 //
20795	/ 54677 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20796	/ 54681 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20797	/ 54685 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20798	/ 54689 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20799	/ 54693 / // MIs[1] Operand 1
20800	/ 54693 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20801	/ 54698 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20802	/ 54703 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20803	/ 54707 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20804	/* 54709 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, AFGR64:{ :[f64] }:$F)
20805	/ 54709 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
20806	/ 54712 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20807	/ 54714 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20808	/ 54716 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20809	/ 54720 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20810	/ 54722 / GIR_RootConstrainSelectedInstOperands,
20811	/ 54723 / // GIR_Coverage, 1828,
20812	/ 54723 / GIR_EraseRootFromParent_Done,
20813	/ 54724 / // Label 1480: @54724
20814	/ 54724 / GIM_Try_CheckFeatures, /On fail goto//Label 1481/ GIMT_Encode4(`54778`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1831 //
20815	/ 54731 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20816	/ 54735 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20817	/ 54739 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20818	/ 54743 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20819	/ 54747 / // MIs[1] Operand 1
20820	/ 54747 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20821	/ 54752 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20822	/ 54757 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20823	/ 54761 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20824	/* 54763 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, AFGR64:{ :[f64] }:$F)
20825	/ 54763 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32),
20826	/ 54766 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20827	/ 54768 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20828	/ 54770 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20829	/ 54774 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20830	/ 54776 / GIR_RootConstrainSelectedInstOperands,
20831	/ 54777 / // GIR_Coverage, 1831,
20832	/ 54777 / GIR_EraseRootFromParent_Done,
20833	/ 54778 / // Label 1481: @54778
20834	/ 54778 / GIM_Reject,
20835	/ 54779 / // Label 1479: @54779
20836	/ 54779 / GIM_Try, /On fail goto//Label 1482/ GIMT_Encode4(`55013`),
20837	/ 54784 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
20838	/ 54788 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
20839	/ 54792 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
20840	/ 54796 / GIM_Try_CheckFeatures, /On fail goto//Label 1483/ GIMT_Encode4(`54850`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1849 //
20841	/ 54803 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20842	/ 54807 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20843	/ 54811 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20844	/ 54815 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20845	/ 54819 / // MIs[1] Operand 1
20846	/ 54819 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20847	/ 54824 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20848	/ 54829 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20849	/ 54833 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20850	/* 54835 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, FGR64:{ :[f64] }:$F)
20851	/ 54835 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
20852	/ 54838 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20853	/ 54840 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20854	/ 54842 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20855	/ 54846 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20856	/ 54848 / GIR_RootConstrainSelectedInstOperands,
20857	/ 54849 / // GIR_Coverage, 1849,
20858	/ 54849 / GIR_EraseRootFromParent_Done,
20859	/ 54850 / // Label 1483: @54850
20860	/ 54850 / GIM_Try_CheckFeatures, /On fail goto//Label 1484/ GIMT_Encode4(`54904`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1851 //
20861	/ 54857 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20862	/ 54861 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20863	/ 54865 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
20864	/ 54869 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
20865	/ 54873 / // MIs[1] Operand 1
20866	/ 54873 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20867	/ 54878 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20868	/ 54883 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20869	/ 54887 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20870	/* 54889 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETEQ:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I64_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR64:{ :[i64] }:$lhs, FGR64:{ :[f64] }:$F)
20871	/ 54889 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_D64),
20872	/ 54892 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20873	/ 54894 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20874	/ 54896 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20875	/ 54900 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20876	/ 54902 / GIR_RootConstrainSelectedInstOperands,
20877	/ 54903 / // GIR_Coverage, 1851,
20878	/ 54903 / GIR_EraseRootFromParent_Done,
20879	/ 54904 / // Label 1484: @54904
20880	/ 54904 / GIM_Try_CheckFeatures, /On fail goto//Label 1485/ GIMT_Encode4(`54958`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1854 //
20881	/ 54911 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20882	/ 54915 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20883	/ 54919 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20884	/ 54923 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20885	/ 54927 / // MIs[1] Operand 1
20886	/ 54927 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20887	/ 54932 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20888	/ 54937 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20889	/ 54941 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20890	/* 54943 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, FGR64:{ :[f64] }:$F)
20891	/ 54943 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D64),
20892	/ 54946 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20893	/ 54948 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20894	/ 54950 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20895	/ 54954 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20896	/ 54956 / GIR_RootConstrainSelectedInstOperands,
20897	/ 54957 / // GIR_Coverage, 1854,
20898	/ 54957 / GIR_EraseRootFromParent_Done,
20899	/ 54958 / // Label 1485: @54958
20900	/ 54958 / GIM_Try_CheckFeatures, /On fail goto//Label 1486/ GIMT_Encode4(`55012`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1857 //
20901	/ 54965 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20902	/ 54969 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20903	/ 54973 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
20904	/ 54977 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
20905	/ 54981 / // MIs[1] Operand 1
20906	/ 54981 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20907	/ 54986 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20908	/ 54991 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20909	/ 54995 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20910	/* 54997 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, 0:{ :[i64] }, SETNE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I64_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR64:{ :[i64] }:$lhs, FGR64:{ :[f64] }:$F)
20911	/ 54997 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_D64),
20912	/ 55000 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20913	/ 55002 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20914	/ 55004 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20915	/ 55008 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20916	/ 55010 / GIR_RootConstrainSelectedInstOperands,
20917	/ 55011 / // GIR_Coverage, 1857,
20918	/ 55011 / GIR_EraseRootFromParent_Done,
20919	/ 55012 / // Label 1486: @55012
20920	/ 55012 / GIM_Reject,
20921	/ 55013 / // Label 1482: @55013
20922	/ 55013 / GIM_Try, /On fail goto//Label 1487/ GIMT_Encode4(`55139`),
20923	/ 55018 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20924	/ 55022 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20925	/ 55026 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
20926	/ 55030 / GIM_Try_CheckFeatures, /On fail goto//Label 1488/ GIMT_Encode4(`55084`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2428 //
20927	/ 55037 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20928	/ 55041 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20929	/ 55045 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20930	/ 55049 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20931	/ 55053 / // MIs[1] Operand 1
20932	/ 55053 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
20933	/ 55058 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20934	/ 55063 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20935	/ 55067 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20936	/* 55069 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETEQ:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, AFGR64:{ :[f64] }:$F)
20937	/ 55069 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
20938	/ 55072 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20939	/ 55074 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20940	/ 55076 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20941	/ 55080 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20942	/ 55082 / GIR_RootConstrainSelectedInstOperands,
20943	/ 55083 / // GIR_Coverage, 2428,
20944	/ 55083 / GIR_EraseRootFromParent_Done,
20945	/ 55084 / // Label 1488: @55084
20946	/ 55084 / GIM_Try_CheckFeatures, /On fail goto//Label 1489/ GIMT_Encode4(`55138`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2431 //
20947	/ 55091 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20948	/ 55095 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20949	/ 55099 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20950	/ 55103 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20951	/ 55107 / // MIs[1] Operand 1
20952	/ 55107 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
20953	/ 55112 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20954	/ 55117 / GIM_CheckConstantInt8, /MI/`1`, /Op/`3`, `0`,
20955	/ 55121 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20956	/* 55123 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, 0:{ :[i32] }, SETNE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$lhs, AFGR64:{ :[f64] }:$F)
20957	/ 55123 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32_MM),
20958	/ 55126 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
20959	/ 55128 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20960	/ 55130 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20961	/ 55134 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20962	/ 55136 / GIR_RootConstrainSelectedInstOperands,
20963	/ 55137 / // GIR_Coverage, 2431,
20964	/ 55137 / GIR_EraseRootFromParent_Done,
20965	/ 55138 / // Label 1489: @55138
20966	/ 55138 / GIM_Reject,
20967	/ 55139 / // Label 1487: @55139
20968	/ 55139 / GIM_Try, /On fail goto//Label 1490/ GIMT_Encode4(`56069`),
20969	/ 55144 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20970	/ 55148 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20971	/ 55152 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
20972	/ 55156 / GIM_Try_CheckFeatures, /On fail goto//Label 1491/ GIMT_Encode4(`55232`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1751 //
20973	/ 55163 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
20974	/ 55167 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
20975	/ 55171 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
20976	/ 55175 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
20977	/ 55179 / // MIs[1] Operand 1
20978	/ 55179 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
20979	/ 55184 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20980	/ 55189 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
20981	/ 55194 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
20982	/* 55196 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR64:{ :[i64] }:$F)
20983	/ 55196 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
20984	/ 55199 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
20985	/ 55203 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20986	/ 55208 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
20987	/ 55212 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
20988	/ 55216 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
20989	/ 55218 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
20990	/ 55221 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
20991	/ 55223 / GIR_RootToRootCopy, /OpIdx/`2`, // T
20992	/ 55225 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
20993	/ 55228 / GIR_RootToRootCopy, /OpIdx/`3`, // F
20994	/ 55230 / GIR_RootConstrainSelectedInstOperands,
20995	/ 55231 / // GIR_Coverage, 1751,
20996	/ 55231 / GIR_EraseRootFromParent_Done,
20997	/ 55232 / // Label 1491: @55232
20998	/ 55232 / GIM_Try_CheckFeatures, /On fail goto//Label 1492/ GIMT_Encode4(`55308`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1752 //
20999	/ 55239 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21000	/ 55243 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21001	/ 55247 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21002	/ 55251 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21003	/ 55255 / // MIs[1] Operand 1
21004	/ 55255 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21005	/ 55260 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21006	/ 55265 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21007	/ 55270 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21008	/* 55272 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR64:{ :[i64] }:$F)
21009	/ 55272 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21010	/ 55275 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21011	/ 55279 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21012	/ 55284 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21013	/ 55288 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21014	/ 55292 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21015	/ 55294 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21016	/ 55297 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21017	/ 55299 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21018	/ 55301 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21019	/ 55304 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21020	/ 55306 / GIR_RootConstrainSelectedInstOperands,
21021	/ 55307 / // GIR_Coverage, 1752,
21022	/ 55307 / GIR_EraseRootFromParent_Done,
21023	/ 55308 / // Label 1492: @55308
21024	/ 55308 / GIM_Try_CheckFeatures, /On fail goto//Label 1493/ GIMT_Encode4(`55384`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1755 //
21025	/ 55315 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21026	/ 55319 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21027	/ 55323 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21028	/ 55327 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21029	/ 55331 / // MIs[1] Operand 1
21030	/ 55331 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21031	/ 55336 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21032	/ 55341 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21033	/ 55346 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21034	/* 55348 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR64:{ :[i64] }:$F)
21035	/ 55348 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21036	/ 55351 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
21037	/ 55355 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21038	/ 55360 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21039	/ 55364 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21040	/ 55368 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21041	/ 55370 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21042	/ 55373 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21043	/ 55375 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21044	/ 55377 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21045	/ 55380 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21046	/ 55382 / GIR_RootConstrainSelectedInstOperands,
21047	/ 55383 / // GIR_Coverage, 1755,
21048	/ 55383 / GIR_EraseRootFromParent_Done,
21049	/ 55384 / // Label 1493: @55384
21050	/ 55384 / GIM_Try_CheckFeatures, /On fail goto//Label 1494/ GIMT_Encode4(`55460`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1756 //
21051	/ 55391 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21052	/ 55395 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21053	/ 55399 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21054	/ 55403 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21055	/ 55407 / // MIs[1] Operand 1
21056	/ 55407 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21057	/ 55412 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21058	/ 55417 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21059	/ 55422 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21060	/* 55424 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), GPR64:{ :[i64] }:$F)
21061	/ 55424 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21062	/ 55427 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21063	/ 55431 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21064	/ 55436 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21065	/ 55440 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21066	/ 55444 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21067	/ 55446 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21068	/ 55449 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21069	/ 55451 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21070	/ 55453 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21071	/ 55456 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21072	/ 55458 / GIR_RootConstrainSelectedInstOperands,
21073	/ 55459 / // GIR_Coverage, 1756,
21074	/ 55459 / GIR_EraseRootFromParent_Done,
21075	/ 55460 / // Label 1494: @55460
21076	/ 55460 / GIM_Try_CheckFeatures, /On fail goto//Label 1495/ GIMT_Encode4(`55536`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1767 //
21077	/ 55467 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21078	/ 55471 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21079	/ 55475 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21080	/ 55479 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21081	/ 55483 / // MIs[1] Operand 1
21082	/ 55483 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
21083	/ 55488 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21084	/ 55493 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21085	/ 55498 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21086	/* 55500 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR64:{ :[i64] }:$F)
21087	/ 55500 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21088	/ 55503 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
21089	/ 55507 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21090	/ 55512 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21091	/ 55516 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21092	/ 55520 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21093	/ 55522 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21094	/ 55525 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21095	/ 55527 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21096	/ 55529 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21097	/ 55532 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21098	/ 55534 / GIR_RootConstrainSelectedInstOperands,
21099	/ 55535 / // GIR_Coverage, 1767,
21100	/ 55535 / GIR_EraseRootFromParent_Done,
21101	/ 55536 / // Label 1495: @55536
21102	/ 55536 / GIM_Try_CheckFeatures, /On fail goto//Label 1496/ GIMT_Encode4(`55612`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1768 //
21103	/ 55543 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21104	/ 55547 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21105	/ 55551 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21106	/ 55555 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21107	/ 55559 / // MIs[1] Operand 1
21108	/ 55559 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21109	/ 55564 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21110	/ 55569 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21111	/ 55574 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21112	/* 55576 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR64:{ :[i64] }:$F)
21113	/ 55576 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21114	/ 55579 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
21115	/ 55583 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21116	/ 55588 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21117	/ 55592 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21118	/ 55596 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21119	/ 55598 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21120	/ 55601 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21121	/ 55603 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21122	/ 55605 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21123	/ 55608 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21124	/ 55610 / GIR_RootConstrainSelectedInstOperands,
21125	/ 55611 / // GIR_Coverage, 1768,
21126	/ 55611 / GIR_EraseRootFromParent_Done,
21127	/ 55612 / // Label 1496: @55612
21128	/ 55612 / GIM_Try_CheckFeatures, /On fail goto//Label 1497/ GIMT_Encode4(`55688`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1771 //
21129	/ 55619 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21130	/ 55623 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21131	/ 55627 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21132	/ 55631 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21133	/ 55635 / // MIs[1] Operand 1
21134	/ 55635 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21135	/ 55640 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21136	/ 55645 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21137	/ 55650 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21138	/* 55652 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), GPR64:{ :[i64] }:$F)
21139	/ 55652 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21140	/ 55655 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
21141	/ 55659 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21142	/ 55664 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21143	/ 55668 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21144	/ 55672 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21145	/ 55674 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21146	/ 55677 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21147	/ 55679 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21148	/ 55681 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21149	/ 55684 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21150	/ 55686 / GIR_RootConstrainSelectedInstOperands,
21151	/ 55687 / // GIR_Coverage, 1771,
21152	/ 55687 / GIR_EraseRootFromParent_Done,
21153	/ 55688 / // Label 1497: @55688
21154	/ 55688 / GIM_Try_CheckFeatures, /On fail goto//Label 1498/ GIMT_Encode4(`55764`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1772 //
21155	/ 55695 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21156	/ 55699 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21157	/ 55703 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21158	/ 55707 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21159	/ 55711 / // MIs[1] Operand 1
21160	/ 55711 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21161	/ 55716 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21162	/ 55721 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21163	/ 55726 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21164	/* 55728 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), GPR64:{ :[i64] }:$F)
21165	/ 55728 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21166	/ 55731 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
21167	/ 55735 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21168	/ 55740 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21169	/ 55744 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21170	/ 55748 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21171	/ 55750 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21172	/ 55753 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21173	/ 55755 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21174	/ 55757 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21175	/ 55760 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21176	/ 55762 / GIR_RootConstrainSelectedInstOperands,
21177	/ 55763 / // GIR_Coverage, 1772,
21178	/ 55763 / GIR_EraseRootFromParent_Done,
21179	/ 55764 / // Label 1498: @55764
21180	/ 55764 / GIM_Try_CheckFeatures, /On fail goto//Label 1499/ GIMT_Encode4(`55840`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1775 //
21181	/ 55771 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21182	/ 55775 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21183	/ 55779 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21184	/ 55783 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21185	/ 55787 / // MIs[1] Operand 1
21186	/ 55787 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21187	/ 55792 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21188	/ 55797 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21189	/ 55802 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21190	/* 55804 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR64:{ :[i64] }:$F)
21191	/ 55804 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21192	/ 55807 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21193	/ 55811 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21194	/ 55816 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21195	/ 55820 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21196	/ 55824 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21197	/ 55826 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_I64),
21198	/ 55829 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21199	/ 55831 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21200	/ 55833 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21201	/ 55836 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21202	/ 55838 / GIR_RootConstrainSelectedInstOperands,
21203	/ 55839 / // GIR_Coverage, 1775,
21204	/ 55839 / GIR_EraseRootFromParent_Done,
21205	/ 55840 / // Label 1499: @55840
21206	/ 55840 / GIM_Try_CheckFeatures, /On fail goto//Label 1500/ GIMT_Encode4(`55916`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1779 //
21207	/ 55847 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21208	/ 55851 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21209	/ 55855 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21210	/ 55859 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21211	/ 55863 / // MIs[1] Operand 1
21212	/ 55863 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21213	/ 55868 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21214	/ 55873 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21215	/ 55878 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21216	/* 55880 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETEQ:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVZ_I64_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR64:{ :[i64] }:$F)
21217	/ 55880 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
21218	/ 55883 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
21219	/ 55887 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21220	/ 55892 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21221	/ 55896 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21222	/ 55900 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21223	/ 55902 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_I64),
21224	/ 55905 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21225	/ 55907 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21226	/ 55909 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21227	/ 55912 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21228	/ 55914 / GIR_RootConstrainSelectedInstOperands,
21229	/ 55915 / // GIR_Coverage, 1779,
21230	/ 55915 / GIR_EraseRootFromParent_Done,
21231	/ 55916 / // Label 1500: @55916
21232	/ 55916 / GIM_Try_CheckFeatures, /On fail goto//Label 1501/ GIMT_Encode4(`55992`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1784 //
21233	/ 55923 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21234	/ 55927 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21235	/ 55931 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21236	/ 55935 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21237	/ 55939 / // MIs[1] Operand 1
21238	/ 55939 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21239	/ 55944 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21240	/ 55949 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21241	/ 55954 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21242	/* 55956 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), GPR64:{ :[i64] }:$F)
21243	/ 55956 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21244	/ 55959 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21245	/ 55963 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21246	/ 55968 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21247	/ 55972 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21248	/ 55976 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21249	/ 55978 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I64),
21250	/ 55981 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21251	/ 55983 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21252	/ 55985 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21253	/ 55988 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21254	/ 55990 / GIR_RootConstrainSelectedInstOperands,
21255	/ 55991 / // GIR_Coverage, 1784,
21256	/ 55991 / GIR_EraseRootFromParent_Done,
21257	/ 55992 / // Label 1501: @55992
21258	/ 55992 / GIM_Try_CheckFeatures, /On fail goto//Label 1502/ GIMT_Encode4(`56068`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1790 //
21259	/ 55999 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21260	/ 56003 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21261	/ 56007 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21262	/ 56011 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21263	/ 56015 / // MIs[1] Operand 1
21264	/ 56015 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21265	/ 56020 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21266	/ 56025 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21267	/ 56030 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21268	/* 56032 / // (select:{ :[i64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETNE:{ :[Other] }), GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I64_I64:{ :[i64] } GPR64:{ :[i64] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), GPR64:{ :[i64] }:$F)
21269	/ 56032 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
21270	/ 56035 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
21271	/ 56039 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21272	/ 56044 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21273	/ 56048 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21274	/ 56052 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21275	/ 56054 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I64),
21276	/ 56057 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
21277	/ 56059 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21278	/ 56061 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21279	/ 56064 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21280	/ 56066 / GIR_RootConstrainSelectedInstOperands,
21281	/ 56067 / // GIR_Coverage, 1790,
21282	/ 56067 / GIR_EraseRootFromParent_Done,
21283	/ 56068 / // Label 1502: @56068
21284	/ 56068 / GIM_Reject,
21285	/ 56069 / // Label 1490: @56069
21286	/ 56069 / GIM_Try, /On fail goto//Label 1503/ GIMT_Encode4(`56543`),
21287	/ 56074 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21288	/ 56078 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21289	/ 56082 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21290	/ 56086 / GIM_Try_CheckFeatures, /On fail goto//Label 1504/ GIMT_Encode4(`56162`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1819 //
21291	/ 56093 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21292	/ 56097 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21293	/ 56101 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21294	/ 56105 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21295	/ 56109 / // MIs[1] Operand 1
21296	/ 56109 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
21297	/ 56114 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21298	/ 56119 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21299	/ 56124 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21300	/* 56126 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21301	/ 56126 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21302	/ 56129 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
21303	/ 56133 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21304	/ 56138 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21305	/ 56142 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21306	/ 56146 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21307	/ 56148 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
21308	/ 56151 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21309	/ 56153 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21310	/ 56155 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21311	/ 56158 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21312	/ 56160 / GIR_RootConstrainSelectedInstOperands,
21313	/ 56161 / // GIR_Coverage, 1819,
21314	/ 56161 / GIR_EraseRootFromParent_Done,
21315	/ 56162 / // Label 1504: @56162
21316	/ 56162 / GIM_Try_CheckFeatures, /On fail goto//Label 1505/ GIMT_Encode4(`56238`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1820 //
21317	/ 56169 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21318	/ 56173 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21319	/ 56177 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21320	/ 56181 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21321	/ 56185 / // MIs[1] Operand 1
21322	/ 56185 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21323	/ 56190 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21324	/ 56195 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21325	/ 56200 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21326	/* 56202 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21327	/ 56202 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21328	/ 56205 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21329	/ 56209 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21330	/ 56214 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21331	/ 56218 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21332	/ 56222 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21333	/ 56224 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
21334	/ 56227 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21335	/ 56229 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21336	/ 56231 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21337	/ 56234 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21338	/ 56236 / GIR_RootConstrainSelectedInstOperands,
21339	/ 56237 / // GIR_Coverage, 1820,
21340	/ 56237 / GIR_EraseRootFromParent_Done,
21341	/ 56238 / // Label 1505: @56238
21342	/ 56238 / GIM_Try_CheckFeatures, /On fail goto//Label 1506/ GIMT_Encode4(`56314`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1823 //
21343	/ 56245 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21344	/ 56249 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21345	/ 56253 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21346	/ 56257 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21347	/ 56261 / // MIs[1] Operand 1
21348	/ 56261 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21349	/ 56266 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21350	/ 56271 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21351	/ 56276 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21352	/* 56278 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), AFGR64:{ :[f64] }:$F)
21353	/ 56278 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21354	/ 56281 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
21355	/ 56285 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21356	/ 56290 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21357	/ 56294 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21358	/ 56298 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21359	/ 56300 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
21360	/ 56303 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21361	/ 56305 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21362	/ 56307 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21363	/ 56310 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21364	/ 56312 / GIR_RootConstrainSelectedInstOperands,
21365	/ 56313 / // GIR_Coverage, 1823,
21366	/ 56313 / GIR_EraseRootFromParent_Done,
21367	/ 56314 / // Label 1506: @56314
21368	/ 56314 / GIM_Try_CheckFeatures, /On fail goto//Label 1507/ GIMT_Encode4(`56390`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1824 //
21369	/ 56321 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21370	/ 56325 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21371	/ 56329 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21372	/ 56333 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21373	/ 56337 / // MIs[1] Operand 1
21374	/ 56337 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21375	/ 56342 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21376	/ 56347 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21377	/ 56352 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21378	/* 56354 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), AFGR64:{ :[f64] }:$F)
21379	/ 56354 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21380	/ 56357 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21381	/ 56361 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21382	/ 56366 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21383	/ 56370 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21384	/ 56374 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21385	/ 56376 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
21386	/ 56379 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21387	/ 56381 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21388	/ 56383 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21389	/ 56386 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21390	/ 56388 / GIR_RootConstrainSelectedInstOperands,
21391	/ 56389 / // GIR_Coverage, 1824,
21392	/ 56389 / GIR_EraseRootFromParent_Done,
21393	/ 56390 / // Label 1507: @56390
21394	/ 56390 / GIM_Try_CheckFeatures, /On fail goto//Label 1508/ GIMT_Encode4(`56466`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1827 //
21395	/ 56397 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21396	/ 56401 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21397	/ 56405 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21398	/ 56409 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21399	/ 56413 / // MIs[1] Operand 1
21400	/ 56413 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21401	/ 56418 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21402	/ 56423 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21403	/ 56428 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21404	/* 56430 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21405	/ 56430 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21406	/ 56433 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21407	/ 56437 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21408	/ 56442 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21409	/ 56446 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21410	/ 56450 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21411	/ 56452 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32),
21412	/ 56455 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21413	/ 56457 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21414	/ 56459 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21415	/ 56462 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21416	/ 56464 / GIR_RootConstrainSelectedInstOperands,
21417	/ 56465 / // GIR_Coverage, 1827,
21418	/ 56465 / GIR_EraseRootFromParent_Done,
21419	/ 56466 / // Label 1508: @56466
21420	/ 56466 / GIM_Try_CheckFeatures, /On fail goto//Label 1509/ GIMT_Encode4(`56542`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1829 //
21421	/ 56473 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21422	/ 56477 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21423	/ 56481 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21424	/ 56485 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21425	/ 56489 / // MIs[1] Operand 1
21426	/ 56489 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21427	/ 56494 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21428	/ 56499 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21429	/ 56504 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21430	/* 56506 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21431	/ 56506 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21432	/ 56509 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21433	/ 56513 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21434	/ 56518 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21435	/ 56522 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21436	/ 56526 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21437	/ 56528 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32),
21438	/ 56531 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21439	/ 56533 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21440	/ 56535 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21441	/ 56538 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21442	/ 56540 / GIR_RootConstrainSelectedInstOperands,
21443	/ 56541 / // GIR_Coverage, 1829,
21444	/ 56541 / GIR_EraseRootFromParent_Done,
21445	/ 56542 / // Label 1509: @56542
21446	/ 56542 / GIM_Reject,
21447	/ 56543 / // Label 1503: @56543
21448	/ 56543 / GIM_Try, /On fail goto//Label 1510/ GIMT_Encode4(`57473`),
21449	/ 56548 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21450	/ 56552 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21451	/ 56556 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21452	/ 56560 / GIM_Try_CheckFeatures, /On fail goto//Label 1511/ GIMT_Encode4(`56636`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1832 //
21453	/ 56567 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21454	/ 56571 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21455	/ 56575 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21456	/ 56579 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21457	/ 56583 / // MIs[1] Operand 1
21458	/ 56583 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
21459	/ 56588 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21460	/ 56593 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21461	/ 56598 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21462	/* 56600 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR64:{ :[f64] }:$F)
21463	/ 56600 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21464	/ 56603 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
21465	/ 56607 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21466	/ 56612 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21467	/ 56616 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21468	/ 56620 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21469	/ 56622 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21470	/ 56625 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21471	/ 56627 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21472	/ 56629 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21473	/ 56632 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21474	/ 56634 / GIR_RootConstrainSelectedInstOperands,
21475	/ 56635 / // GIR_Coverage, 1832,
21476	/ 56635 / GIR_EraseRootFromParent_Done,
21477	/ 56636 / // Label 1511: @56636
21478	/ 56636 / GIM_Try_CheckFeatures, /On fail goto//Label 1512/ GIMT_Encode4(`56712`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1833 //
21479	/ 56643 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21480	/ 56647 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21481	/ 56651 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21482	/ 56655 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21483	/ 56659 / // MIs[1] Operand 1
21484	/ 56659 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21485	/ 56664 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21486	/ 56669 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21487	/ 56674 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21488	/* 56676 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR64:{ :[f64] }:$F)
21489	/ 56676 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21490	/ 56679 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21491	/ 56683 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21492	/ 56688 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21493	/ 56692 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21494	/ 56696 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21495	/ 56698 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21496	/ 56701 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21497	/ 56703 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21498	/ 56705 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21499	/ 56708 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21500	/ 56710 / GIR_RootConstrainSelectedInstOperands,
21501	/ 56711 / // GIR_Coverage, 1833,
21502	/ 56711 / GIR_EraseRootFromParent_Done,
21503	/ 56712 / // Label 1512: @56712
21504	/ 56712 / GIM_Try_CheckFeatures, /On fail goto//Label 1513/ GIMT_Encode4(`56788`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1836 //
21505	/ 56719 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21506	/ 56723 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21507	/ 56727 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21508	/ 56731 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21509	/ 56735 / // MIs[1] Operand 1
21510	/ 56735 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21511	/ 56740 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21512	/ 56745 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21513	/ 56750 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21514	/* 56752 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLT:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR64:{ :[f64] }:$F)
21515	/ 56752 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21516	/ 56755 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT),
21517	/ 56759 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21518	/ 56764 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21519	/ 56768 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21520	/ 56772 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21521	/ 56774 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21522	/ 56777 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21523	/ 56779 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21524	/ 56781 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21525	/ 56784 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21526	/ 56786 / GIR_RootConstrainSelectedInstOperands,
21527	/ 56787 / // GIR_Coverage, 1836,
21528	/ 56787 / GIR_EraseRootFromParent_Done,
21529	/ 56788 / // Label 1513: @56788
21530	/ 56788 / GIM_Try_CheckFeatures, /On fail goto//Label 1514/ GIMT_Encode4(`56864`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1837 //
21531	/ 56795 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21532	/ 56799 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21533	/ 56803 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21534	/ 56807 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21535	/ 56811 / // MIs[1] Operand 1
21536	/ 56811 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21537	/ 56816 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21538	/ 56821 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21539	/ 56826 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21540	/* 56828 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLTu:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), FGR64:{ :[f64] }:$F)
21541	/ 56828 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21542	/ 56831 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu),
21543	/ 56835 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21544	/ 56840 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21545	/ 56844 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21546	/ 56848 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21547	/ 56850 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21548	/ 56853 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21549	/ 56855 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21550	/ 56857 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21551	/ 56860 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21552	/ 56862 / GIR_RootConstrainSelectedInstOperands,
21553	/ 56863 / // GIR_Coverage, 1837,
21554	/ 56863 / GIR_EraseRootFromParent_Done,
21555	/ 56864 / // Label 1514: @56864
21556	/ 56864 / GIM_Try_CheckFeatures, /On fail goto//Label 1515/ GIMT_Encode4(`56940`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1840 //
21557	/ 56871 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21558	/ 56875 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21559	/ 56879 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21560	/ 56883 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21561	/ 56887 / // MIs[1] Operand 1
21562	/ 56887 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
21563	/ 56892 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21564	/ 56897 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21565	/ 56902 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21566	/* 56904 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETGE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR64:{ :[f64] }:$F)
21567	/ 56904 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21568	/ 56907 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
21569	/ 56911 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21570	/ 56916 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21571	/ 56920 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21572	/ 56924 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21573	/ 56926 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21574	/ 56929 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21575	/ 56931 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21576	/ 56933 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21577	/ 56936 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21578	/ 56938 / GIR_RootConstrainSelectedInstOperands,
21579	/ 56939 / // GIR_Coverage, 1840,
21580	/ 56939 / GIR_EraseRootFromParent_Done,
21581	/ 56940 / // Label 1515: @56940
21582	/ 56940 / GIM_Try_CheckFeatures, /On fail goto//Label 1516/ GIMT_Encode4(`57016`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1841 //
21583	/ 56947 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21584	/ 56951 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21585	/ 56955 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21586	/ 56959 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21587	/ 56963 / // MIs[1] Operand 1
21588	/ 56963 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21589	/ 56968 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21590	/ 56973 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21591	/ 56978 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21592	/* 56980 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETUGE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR64:{ :[f64] }:$F)
21593	/ 56980 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21594	/ 56983 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
21595	/ 56987 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21596	/ 56992 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21597	/ 56996 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21598	/ 57000 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21599	/ 57002 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21600	/ 57005 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21601	/ 57007 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21602	/ 57009 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21603	/ 57012 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21604	/ 57014 / GIR_RootConstrainSelectedInstOperands,
21605	/ 57015 / // GIR_Coverage, 1841,
21606	/ 57015 / GIR_EraseRootFromParent_Done,
21607	/ 57016 / // Label 1516: @57016
21608	/ 57016 / GIM_Try_CheckFeatures, /On fail goto//Label 1517/ GIMT_Encode4(`57092`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1844 //
21609	/ 57023 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21610	/ 57027 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21611	/ 57031 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21612	/ 57035 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21613	/ 57039 / // MIs[1] Operand 1
21614	/ 57039 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21615	/ 57044 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21616	/ 57049 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21617	/ 57054 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21618	/* 57056 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETLE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLT64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), FGR64:{ :[f64] }:$F)
21619	/ 57056 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21620	/ 57059 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT64),
21621	/ 57063 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21622	/ 57068 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21623	/ 57072 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21624	/ 57076 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21625	/ 57078 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21626	/ 57081 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21627	/ 57083 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21628	/ 57085 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21629	/ 57088 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21630	/ 57090 / GIR_RootConstrainSelectedInstOperands,
21631	/ 57091 / // GIR_Coverage, 1844,
21632	/ 57091 / GIR_EraseRootFromParent_Done,
21633	/ 57092 / // Label 1517: @57092
21634	/ 57092 / GIM_Try_CheckFeatures, /On fail goto//Label 1518/ GIMT_Encode4(`57168`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1845 //
21635	/ 57099 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21636	/ 57103 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21637	/ 57107 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21638	/ 57111 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21639	/ 57115 / // MIs[1] Operand 1
21640	/ 57115 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21641	/ 57120 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21642	/ 57125 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21643	/ 57130 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21644	/* 57132 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETULE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (SLTu64:{ :[i32] } GPR64:{ :[i64] }:$rhs, GPR64:{ :[i64] }:$lhs), FGR64:{ :[f64] }:$F)
21645	/ 57132 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21646	/ 57135 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu64),
21647	/ 57139 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21648	/ 57144 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21649	/ 57148 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21650	/ 57152 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21651	/ 57154 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21652	/ 57157 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21653	/ 57159 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21654	/ 57161 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21655	/ 57164 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21656	/ 57166 / GIR_RootConstrainSelectedInstOperands,
21657	/ 57167 / // GIR_Coverage, 1845,
21658	/ 57167 / GIR_EraseRootFromParent_Done,
21659	/ 57168 / // Label 1518: @57168
21660	/ 57168 / GIM_Try_CheckFeatures, /On fail goto//Label 1519/ GIMT_Encode4(`57244`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1848 //
21661	/ 57175 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21662	/ 57179 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21663	/ 57183 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21664	/ 57187 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21665	/ 57191 / // MIs[1] Operand 1
21666	/ 57191 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21667	/ 57196 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21668	/ 57201 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21669	/ 57206 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21670	/* 57208 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR64:{ :[f64] }:$F)
21671	/ 57208 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21672	/ 57211 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21673	/ 57215 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21674	/ 57220 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21675	/ 57224 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21676	/ 57228 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21677	/ 57230 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D64),
21678	/ 57233 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21679	/ 57235 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21680	/ 57237 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21681	/ 57240 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21682	/ 57242 / GIR_RootConstrainSelectedInstOperands,
21683	/ 57243 / // GIR_Coverage, 1848,
21684	/ 57243 / GIR_EraseRootFromParent_Done,
21685	/ 57244 / // Label 1519: @57244
21686	/ 57244 / GIM_Try_CheckFeatures, /On fail goto//Label 1520/ GIMT_Encode4(`57320`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1850 //
21687	/ 57251 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21688	/ 57255 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21689	/ 57259 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21690	/ 57263 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21691	/ 57267 / // MIs[1] Operand 1
21692	/ 57267 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21693	/ 57272 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21694	/ 57277 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21695	/ 57282 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21696	/* 57284 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETEQ:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVZ_I64_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR64:{ :[f64] }:$F)
21697	/ 57284 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
21698	/ 57287 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
21699	/ 57291 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21700	/ 57296 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21701	/ 57300 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21702	/ 57304 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21703	/ 57306 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I64_D64),
21704	/ 57309 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21705	/ 57311 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21706	/ 57313 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21707	/ 57316 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21708	/ 57318 / GIR_RootConstrainSelectedInstOperands,
21709	/ 57319 / // GIR_Coverage, 1850,
21710	/ 57319 / GIR_EraseRootFromParent_Done,
21711	/ 57320 / // Label 1520: @57320
21712	/ 57320 / GIM_Try_CheckFeatures, /On fail goto//Label 1521/ GIMT_Encode4(`57396`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1852 //
21713	/ 57327 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21714	/ 57331 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21715	/ 57335 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21716	/ 57339 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21717	/ 57343 / // MIs[1] Operand 1
21718	/ 57343 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21719	/ 57348 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21720	/ 57353 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21721	/ 57358 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21722	/* 57360 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (XOR:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), FGR64:{ :[f64] }:$F)
21723	/ 57360 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21724	/ 57363 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR),
21725	/ 57367 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21726	/ 57372 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21727	/ 57376 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21728	/ 57380 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21729	/ 57382 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D64),
21730	/ 57385 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21731	/ 57387 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21732	/ 57389 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21733	/ 57392 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21734	/ 57394 / GIR_RootConstrainSelectedInstOperands,
21735	/ 57395 / // GIR_Coverage, 1852,
21736	/ 57395 / GIR_EraseRootFromParent_Done,
21737	/ 57396 / // Label 1521: @57396
21738	/ 57396 / GIM_Try_CheckFeatures, /On fail goto//Label 1522/ GIMT_Encode4(`57472`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1855 //
21739	/ 57403 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21740	/ 57407 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21741	/ 57411 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
21742	/ 57415 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s64,
21743	/ 57419 / // MIs[1] Operand 1
21744	/ 57419 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21745	/ 57424 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21746	/ 57429 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21747	/ 57434 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21748	/* 57436 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs, SETNE:{ :[Other] }), FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I64_D64:{ :[f64] } FGR64:{ :[f64] }:$T, (XOR64:{ :[i64] } GPR64:{ :[i64] }:$lhs, GPR64:{ :[i64] }:$rhs), FGR64:{ :[f64] }:$F)
21749	/ 57436 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
21750	/ 57439 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR64),
21751	/ 57443 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21752	/ 57448 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21753	/ 57452 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21754	/ 57456 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21755	/ 57458 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_D64),
21756	/ 57461 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21757	/ 57463 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21758	/ 57465 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21759	/ 57468 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21760	/ 57470 / GIR_RootConstrainSelectedInstOperands,
21761	/ 57471 / // GIR_Coverage, 1855,
21762	/ 57471 / GIR_EraseRootFromParent_Done,
21763	/ 57472 / // Label 1522: @57472
21764	/ 57472 / GIM_Reject,
21765	/ 57473 / // Label 1510: @57473
21766	/ 57473 / GIM_Try, /On fail goto//Label 1523/ GIMT_Encode4(`57947`),
21767	/ 57478 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21768	/ 57482 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21769	/ 57486 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21770	/ 57490 / GIM_Try_CheckFeatures, /On fail goto//Label 1524/ GIMT_Encode4(`57566`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2419 //
21771	/ 57497 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21772	/ 57501 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21773	/ 57505 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21774	/ 57509 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21775	/ 57513 / // MIs[1] Operand 1
21776	/ 57513 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SGE),
21777	/ 57518 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21778	/ 57523 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21779	/ 57528 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21780	/* 57530 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETGE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21781	/ 57530 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21782	/ 57533 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
21783	/ 57537 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21784	/ 57542 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21785	/ 57546 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21786	/ 57550 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21787	/ 57552 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21788	/ 57555 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21789	/ 57557 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21790	/ 57559 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21791	/ 57562 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21792	/ 57564 / GIR_RootConstrainSelectedInstOperands,
21793	/ 57565 / // GIR_Coverage, 2419,
21794	/ 57565 / GIR_EraseRootFromParent_Done,
21795	/ 57566 / // Label 1524: @57566
21796	/ 57566 / GIM_Try_CheckFeatures, /On fail goto//Label 1525/ GIMT_Encode4(`57642`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2420 //
21797	/ 57573 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21798	/ 57577 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21799	/ 57581 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21800	/ 57585 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21801	/ 57589 / // MIs[1] Operand 1
21802	/ 57589 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_UGE),
21803	/ 57594 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21804	/ 57599 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21805	/ 57604 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21806	/* 57606 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETUGE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21807	/ 57606 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21808	/ 57609 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
21809	/ 57613 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21810	/ 57618 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21811	/ 57622 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21812	/ 57626 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21813	/ 57628 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21814	/ 57631 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21815	/ 57633 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21816	/ 57635 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21817	/ 57638 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21818	/ 57640 / GIR_RootConstrainSelectedInstOperands,
21819	/ 57641 / // GIR_Coverage, 2420,
21820	/ 57641 / GIR_EraseRootFromParent_Done,
21821	/ 57642 / // Label 1525: @57642
21822	/ 57642 / GIM_Try_CheckFeatures, /On fail goto//Label 1526/ GIMT_Encode4(`57718`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2423 //
21823	/ 57649 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21824	/ 57653 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21825	/ 57657 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21826	/ 57661 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21827	/ 57665 / // MIs[1] Operand 1
21828	/ 57665 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_SLE),
21829	/ 57670 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21830	/ 57675 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21831	/ 57680 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21832	/* 57682 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETLE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLT_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), AFGR64:{ :[f64] }:$F)
21833	/ 57682 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21834	/ 57685 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLT_MM),
21835	/ 57689 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21836	/ 57694 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21837	/ 57698 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21838	/ 57702 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21839	/ 57704 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21840	/ 57707 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21841	/ 57709 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21842	/ 57711 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21843	/ 57714 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21844	/ 57716 / GIR_RootConstrainSelectedInstOperands,
21845	/ 57717 / // GIR_Coverage, 2423,
21846	/ 57717 / GIR_EraseRootFromParent_Done,
21847	/ 57718 / // Label 1526: @57718
21848	/ 57718 / GIM_Try_CheckFeatures, /On fail goto//Label 1527/ GIMT_Encode4(`57794`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2424 //
21849	/ 57725 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21850	/ 57729 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21851	/ 57733 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21852	/ 57737 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21853	/ 57741 / // MIs[1] Operand 1
21854	/ 57741 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_ULE),
21855	/ 57746 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21856	/ 57751 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21857	/ 57756 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21858	/* 57758 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETULE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (SLTu_MM:{ :[i32] } GPR32:{ :[i32] }:$rhs, GPR32:{ :[i32] }:$lhs), AFGR64:{ :[f64] }:$F)
21859	/ 57758 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21860	/ 57761 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SLTu_MM),
21861	/ 57765 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21862	/ 57770 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21863	/ 57774 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21864	/ 57778 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21865	/ 57780 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21866	/ 57783 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21867	/ 57785 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21868	/ 57787 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21869	/ 57790 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21870	/ 57792 / GIR_RootConstrainSelectedInstOperands,
21871	/ 57793 / // GIR_Coverage, 2424,
21872	/ 57793 / GIR_EraseRootFromParent_Done,
21873	/ 57794 / // Label 1527: @57794
21874	/ 57794 / GIM_Try_CheckFeatures, /On fail goto//Label 1528/ GIMT_Encode4(`57870`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2427 //
21875	/ 57801 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21876	/ 57805 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21877	/ 57809 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21878	/ 57813 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21879	/ 57817 / // MIs[1] Operand 1
21880	/ 57817 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_EQ),
21881	/ 57822 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21882	/ 57827 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21883	/ 57832 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21884	/* 57834 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETEQ:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVZ_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21885	/ 57834 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21886	/ 57837 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
21887	/ 57841 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21888	/ 57846 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21889	/ 57850 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21890	/ 57854 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21891	/ 57856 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21892	/ 57859 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21893	/ 57861 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21894	/ 57863 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21895	/ 57866 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21896	/ 57868 / GIR_RootConstrainSelectedInstOperands,
21897	/ 57869 / // GIR_Coverage, 2427,
21898	/ 57869 / GIR_EraseRootFromParent_Done,
21899	/ 57870 / // Label 1528: @57870
21900	/ 57870 / GIM_Try_CheckFeatures, /On fail goto//Label 1529/ GIMT_Encode4(`57946`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2429 //
21901	/ 57877 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
21902	/ 57881 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_ICMP),
21903	/ 57885 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
21904	/ 57889 / GIM_CheckType, /MI/`1`, /Op/`3`, /Type/GILLT_s32,
21905	/ 57893 / // MIs[1] Operand 1
21906	/ 57893 / GIM_CheckCmpPredicate, /MI/`1`, /Op/`1`, /Predicate/GIMT_Encode2(CmpInst::ICMP_NE),
21907	/ 57898 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21908	/ 57903 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21909	/ 57908 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
21910	/* 57910 / // (select:{ :[f64] } (setcc:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs, SETNE:{ :[Other] }), AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, (XOR_MM:{ :[i32] } GPR32:{ :[i32] }:$lhs, GPR32:{ :[i32] }:$rhs), AFGR64:{ :[f64] }:$F)
21911	/ 57910 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
21912	/ 57913 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::XOR_MM),
21913	/ 57917 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21914	/ 57922 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`2`, // lhs
21915	/ 57926 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`1`, /OpIdx/`3`, // rhs
21916	/ 57930 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
21917	/ 57932 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32_MM),
21918	/ 57935 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21919	/ 57937 / GIR_RootToRootCopy, /OpIdx/`2`, // T
21920	/ 57939 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
21921	/ 57942 / GIR_RootToRootCopy, /OpIdx/`3`, // F
21922	/ 57944 / GIR_RootConstrainSelectedInstOperands,
21923	/ 57945 / // GIR_Coverage, 2429,
21924	/ 57945 / GIR_EraseRootFromParent_Done,
21925	/ 57946 / // Label 1529: @57946
21926	/ 57946 / GIM_Reject,
21927	/ 57947 / // Label 1523: @57947
21928	/ 57947 / GIM_Try_CheckFeatures, /On fail goto//Label 1530/ GIMT_Encode4(`57977`), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 323 //
21929	/ 57954 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21930	/ 57958 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21931	/ 57962 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21932	/ 57966 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21933	/* 57970 / // (select:{ :[i64] } GPR32Opnd:{ :[i32] }:$cond, GPR64Opnd:{ :[i64] }:$T, GPR64Opnd:{ :[i64] }:$F) => (PseudoSELECT_I64:{ :[i64] } GPR32Opnd:{ :[i32] }:$cond, GPR64Opnd:{ :[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
21934	/ 57970 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoSELECT_I64),
21935	/ 57975 / GIR_RootConstrainSelectedInstOperands,
21936	/ 57976 / // GIR_Coverage, 323,
21937	/ 57976 / GIR_Done,
21938	/ 57977 / // Label 1530: @57977
21939	/ 57977 / GIM_Try_CheckFeatures, /On fail goto//Label 1531/ GIMT_Encode4(`58007`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32), // Rule ID 325 //
21940	/ 57984 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21941	/ 57988 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21942	/ 57992 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21943	/ 57996 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
21944	/* 58000 / // (select:{ :[f64] } GPR32Opnd:{ :[i32] }:$cond, AFGR64Opnd:{ :[f64] }:$T, AFGR64Opnd:{ :[f64] }:$F) => (PseudoSELECT_D32:{ :[f64] } GPR32Opnd:{ :[i32] }:$cond, AFGR64Opnd:{ :[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
21945	/ 58000 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoSELECT_D32),
21946	/ 58005 / GIR_RootConstrainSelectedInstOperands,
21947	/ 58006 / // GIR_Coverage, 325,
21948	/ 58006 / GIR_Done,
21949	/ 58007 / // Label 1531: @58007
21950	/ 58007 / GIM_Try, /On fail goto//Label 1532/ GIMT_Encode4(`58101`),
21951	/ 58012 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21952	/ 58016 / GIM_Try_CheckFeatures, /On fail goto//Label 1533/ GIMT_Encode4(`58042`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32), // Rule ID 326 //
21953	/ 58023 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21954	/ 58027 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21955	/ 58031 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21956	/* 58035 / // (select:{ :[f64] } GPR32Opnd:{ :[i32] }:$cond, FGR64Opnd:{ :[f64] }:$T, FGR64Opnd:{ :[f64] }:$F) => (PseudoSELECT_D64:{ :[f64] } GPR32Opnd:{ :[i32] }:$cond, FGR64Opnd:{ :[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
21957	/ 58035 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoSELECT_D64),
21958	/ 58040 / GIR_RootConstrainSelectedInstOperands,
21959	/ 58041 / // GIR_Coverage, 326,
21960	/ 58041 / GIR_Done,
21961	/ 58042 / // Label 1533: @58042
21962	/ 58042 / GIM_Try, /On fail goto//Label 1534/ GIMT_Encode4(`58100`),
21963	/ 58047 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64CCRegClassID),
21964	/ 58051 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21965	/ 58055 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
21966	/ 58059 / GIM_Try_CheckFeatures, /On fail goto//Label 1535/ GIMT_Encode4(`58079`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 360 //
21967	/* 58066 / // (select:{ :[f64] } FGR64CCOpnd:{ :[i32] }:$fd_in, FGR64Opnd:{ :[f64] }:$ft, FGR64Opnd:{ :[f64] }:$fs) => (SEL_D:{ :[f64] } FGR64CCOpnd:{ :[i32] }:$fd_in, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21968	/ 58066 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEL_D),
21969	/ 58069 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21970	/ 58071 / GIR_RootToRootCopy, /OpIdx/`1`, // fd_in
21971	/ 58073 / GIR_RootToRootCopy, /OpIdx/`3`, // fs
21972	/ 58075 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
21973	/ 58077 / GIR_RootConstrainSelectedInstOperands,
21974	/ 58078 / // GIR_Coverage, 360,
21975	/ 58078 / GIR_EraseRootFromParent_Done,
21976	/ 58079 / // Label 1535: @58079
21977	/ 58079 / GIM_Try_CheckFeatures, /On fail goto//Label 1536/ GIMT_Encode4(`58099`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1235 //
21978	/* 58086 / // (select:{ :[f64] } FGR64CCOpnd:{ :[i32] }:$fd_in, FGR64Opnd:{ :[f64] }:$ft, FGR64Opnd:{ :[f64] }:$fs) => (SEL_D_MMR6:{ :[f64] } FGR64CCOpnd:{ :[i32] }:$fd_in, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
21979	/ 58086 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::SEL_D_MMR6),
21980	/ 58089 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
21981	/ 58091 / GIR_RootToRootCopy, /OpIdx/`1`, // fd_in
21982	/ 58093 / GIR_RootToRootCopy, /OpIdx/`3`, // fs
21983	/ 58095 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
21984	/ 58097 / GIR_RootConstrainSelectedInstOperands,
21985	/ 58098 / // GIR_Coverage, 1235,
21986	/ 58098 / GIR_EraseRootFromParent_Done,
21987	/ 58099 / // Label 1536: @58099
21988	/ 58099 / GIM_Reject,
21989	/ 58100 / // Label 1534: @58100
21990	/ 58100 / GIM_Reject,
21991	/ 58101 / // Label 1532: @58101
21992	/ 58101 / GIM_Try_CheckFeatures, /On fail goto//Label 1537/ GIMT_Encode4(`58137`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1785 //
21993	/ 58108 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21994	/ 58112 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
21995	/ 58116 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21996	/ 58120 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
21997	/* 58124 / // (select:{ :[i64] } GPR32:{ :[i32] }:$cond, GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR32:{ :[i32] }:$cond, GPR64:{ *:[i64] }:$F)
21998	/ 58124 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_I64),
21999	/ 58127 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
22000	/ 58129 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22001	/ 58131 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22002	/ 58133 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22003	/ 58135 / GIR_RootConstrainSelectedInstOperands,
22004	/ 58136 / // GIR_Coverage, 1785,
22005	/ 58136 / GIR_EraseRootFromParent_Done,
22006	/ 58137 / // Label 1537: @58137
22007	/ 58137 / GIM_Try_CheckFeatures, /On fail goto//Label 1538/ GIMT_Encode4(`58173`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1830 //
22008	/ 58144 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22009	/ 58148 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22010	/ 58152 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22011	/ 58156 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22012	/* 58160 / // (select:{ :[f64] } GPR32:{ :[i32] }:$cond, AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22013	/ 58160 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32),
22014	/ 58163 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22015	/ 58165 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22016	/ 58167 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22017	/ 58169 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22018	/ 58171 / GIR_RootConstrainSelectedInstOperands,
22019	/ 58172 / // GIR_Coverage, 1830,
22020	/ 58172 / GIR_EraseRootFromParent_Done,
22021	/ 58173 / // Label 1538: @58173
22022	/ 58173 / GIM_Try_CheckFeatures, /On fail goto//Label 1539/ GIMT_Encode4(`58209`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1853 //
22023	/ 58180 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22024	/ 58184 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22025	/ 58188 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22026	/ 58192 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22027	/* 58196 / // (select:{ :[f64] } GPR32:{ :[i32] }:$cond, FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$cond, FGR64:{ *:[f64] }:$F)
22028	/ 58196 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D64),
22029	/ 58199 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22030	/ 58201 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22031	/ 58203 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22032	/ 58205 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22033	/ 58207 / GIR_RootConstrainSelectedInstOperands,
22034	/ 58208 / // GIR_Coverage, 1853,
22035	/ 58208 / GIR_EraseRootFromParent_Done,
22036	/ 58209 / // Label 1539: @58209
22037	/ 58209 / GIM_Try_CheckFeatures, /On fail goto//Label 1540/ GIMT_Encode4(`58245`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2430 //
22038	/ 58216 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22039	/ 58220 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22040	/ 58224 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22041	/ 58228 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22042	/* 58232 / // (select:{ :[f64] } GPR32:{ :[i32] }:$cond, AFGR64:{ :[f64] }:$T, AFGR64:{ :[f64] }:$F) => (MOVN_I_D32_MM:{ :[f64] } AFGR64:{ :[f64] }:$T, GPR32:{ :[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22043	/ 58232 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22044	/ 58235 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22045	/ 58237 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22046	/ 58239 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22047	/ 58241 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22048	/ 58243 / GIR_RootConstrainSelectedInstOperands,
22049	/ 58244 / // GIR_Coverage, 2430,
22050	/ 58244 / GIR_EraseRootFromParent_Done,
22051	/ 58245 / // Label 1540: @58245
22052	/ 58245 / GIM_Try_CheckFeatures, /On fail goto//Label 1541/ GIMT_Encode4(`58347`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1920 //
22053	/ 58252 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22054	/* 58256 / // (select:{ :[i64] } i32:{ :[i32] }:$cond, i64:{ :[i64] }:$t, i64:{ :[i64] }:$f) => (OR64:{ :[i64] } (SELNEZ64:{ :[i64] } i64:{ :[i64] }:$t, (SLL64_32:{ :[i64] } i32:{ :[i32] }:$cond)), (SELEQZ64:{ :[i64] } i64:{ :[i64] }:$f, (SLL64_32:{ :[i64] } i32:{ :[i32] }:$cond)))
22055	/ 58256 / GIR_MakeTempReg, /TempRegID/`3`, /TypeID/GILLT_s64,
22056	/ 58259 / GIR_BuildMI, /InsnID/`4`, /Opcode/GIMT_Encode2(Mips::SLL64_32),
22057	/ 58263 / GIR_AddTempRegister, /InsnID/`4`, /TempRegID/`3`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22058	/ 58268 / GIR_Copy, /NewInsnID/`4`, /OldInsnID/`0`, /OpIdx/`1`, // cond
22059	/ 58272 / GIR_ConstrainSelectedInstOperands, /InsnID/`4`,
22060	/ 58274 / GIR_MakeTempReg, /TempRegID/`2`, /TypeID/GILLT_s64,
22061	/ 58277 / GIR_BuildMI, /InsnID/`3`, /Opcode/GIMT_Encode2(Mips::SELEQZ64),
22062	/ 58281 / GIR_AddTempRegister, /InsnID/`3`, /TempRegID/`2`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22063	/ 58286 / GIR_Copy, /NewInsnID/`3`, /OldInsnID/`0`, /OpIdx/`3`, // f
22064	/ 58290 / GIR_AddSimpleTempRegister, /InsnID/`3`, /TempRegID/`3`,
22065	/ 58293 / GIR_ConstrainSelectedInstOperands, /InsnID/`3`,
22066	/ 58295 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s64,
22067	/ 58298 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SLL64_32),
22068	/ 58302 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22069	/ 58307 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // cond
22070	/ 58311 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
22071	/ 58313 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
22072	/ 58316 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SELNEZ64),
22073	/ 58320 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22074	/ 58325 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // t
22075	/ 58329 / GIR_AddSimpleTempRegister, /InsnID/`1`, /TempRegID/`1`,
22076	/ 58332 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
22077	/ 58334 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::OR64),
22078	/ 58337 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
22079	/ 58339 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
22080	/ 58342 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`2`,
22081	/ 58345 / GIR_RootConstrainSelectedInstOperands,
22082	/ 58346 / // GIR_Coverage, 1920,
22083	/ 58346 / GIR_EraseRootFromParent_Done,
22084	/ 58347 / // Label 1541: @58347
22085	/ 58347 / GIM_Reject,
22086	/ 58348 / // Label 1473: @58348
22087	/ 58348 / GIM_Reject,
22088	/ 58349 / // Label 1471: @58349
22089	/ 58349 / GIM_Try, /On fail goto//Label 1542/ GIMT_Encode4(`58501`),
22090	/ 58354 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
22091	/ 58357 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_s64,
22092	/ 58360 / GIM_Try_CheckFeatures, /On fail goto//Label 1543/ GIMT_Encode4(`58396`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1791 //
22093	/ 58367 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22094	/ 58371 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22095	/ 58375 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22096	/ 58379 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22097	/* 58383 / // (select:{ :[i64] } GPR64:{ :[i64] }:$cond, GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$F) => (MOVN_I64_I64:{ :[i64] } GPR64:{ :[i64] }:$T, GPR64:{ :[i64] }:$cond, GPR64:{ *:[i64] }:$F)
22098	/ 58383 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_I64),
22099	/ 58386 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
22100	/ 58388 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22101	/ 58390 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22102	/ 58392 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22103	/ 58394 / GIR_RootConstrainSelectedInstOperands,
22104	/ 58395 / // GIR_Coverage, 1791,
22105	/ 58395 / GIR_EraseRootFromParent_Done,
22106	/ 58396 / // Label 1543: @58396
22107	/ 58396 / GIM_Try_CheckFeatures, /On fail goto//Label 1544/ GIMT_Encode4(`58432`), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1856 //
22108	/ 58403 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22109	/ 58407 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22110	/ 58411 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22111	/ 58415 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22112	/* 58419 / // (select:{ :[f64] } GPR64:{ :[i64] }:$cond, FGR64:{ :[f64] }:$T, FGR64:{ :[f64] }:$F) => (MOVN_I64_D64:{ :[f64] } FGR64:{ :[f64] }:$T, GPR64:{ :[i64] }:$cond, FGR64:{ *:[f64] }:$F)
22113	/ 58419 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MOVN_I64_D64),
22114	/ 58422 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22115	/ 58424 / GIR_RootToRootCopy, /OpIdx/`2`, // T
22116	/ 58426 / GIR_RootToRootCopy, /OpIdx/`1`, // cond
22117	/ 58428 / GIR_RootToRootCopy, /OpIdx/`3`, // F
22118	/ 58430 / GIR_RootConstrainSelectedInstOperands,
22119	/ 58431 / // GIR_Coverage, 1856,
22120	/ 58431 / GIR_EraseRootFromParent_Done,
22121	/ 58432 / // Label 1544: @58432
22122	/ 58432 / GIM_Try_CheckFeatures, /On fail goto//Label 1545/ GIMT_Encode4(`58500`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1909 //
22123	/ 58439 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22124	/* 58443 / // (select:{ :[i64] } i64:{ :[i64] }:$cond, i64:{ :[i64] }:$t, i64:{ :[i64] }:$f) => (OR64:{ :[i64] } (SELNEZ64:{ :[i64] } i64:{ :[i64] }:$t, i64:{ :[i64] }:$cond), (SELEQZ64:{ :[i64] } i64:{ :[i64] }:$f, i64:{ :[i64] }:$cond))
22125	/ 58443 / GIR_MakeTempReg, /TempRegID/`1`, /TypeID/GILLT_s64,
22126	/ 58446 / GIR_BuildMI, /InsnID/`2`, /Opcode/GIMT_Encode2(Mips::SELEQZ64),
22127	/ 58450 / GIR_AddTempRegister, /InsnID/`2`, /TempRegID/`1`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22128	/ 58455 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`3`, // f
22129	/ 58459 / GIR_Copy, /NewInsnID/`2`, /OldInsnID/`0`, /OpIdx/`1`, // cond
22130	/ 58463 / GIR_ConstrainSelectedInstOperands, /InsnID/`2`,
22131	/ 58465 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
22132	/ 58468 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::SELNEZ64),
22133	/ 58472 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22134	/ 58477 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`2`, // t
22135	/ 58481 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // cond
22136	/ 58485 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
22137	/ 58487 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::OR64),
22138	/ 58490 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
22139	/ 58492 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
22140	/ 58495 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`1`,
22141	/ 58498 / GIR_RootConstrainSelectedInstOperands,
22142	/ 58499 / // GIR_Coverage, 1909,
22143	/ 58499 / GIR_EraseRootFromParent_Done,
22144	/ 58500 / // Label 1545: @58500
22145	/ 58500 / GIM_Reject,
22146	/ 58501 / // Label 1542: @58501
22147	/ 58501 / GIM_Reject,
22148	/ 58502 / // Label 1472: @58502
22149	/ 58502 / GIM_Reject,
22150	/ 58503 / // Label 1366: @58503
22151	/ 58503 / GIM_Try, /On fail goto//Label 1546/ GIMT_Encode4(`58594`),
22152	/ 58508 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
22153	/ 58511 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
22154	/ 58514 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v16s8,
22155	/ 58517 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
22156	/ 58521 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
22157	/ 58525 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
22158	/ 58529 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
22159	/ 58533 / GIM_Try_CheckFeatures, /On fail goto//Label 1547/ GIMT_Encode4(`58553`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 595 //
22160	/* 58540 / // (vselect:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wt, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wd_in) => (BMNZ_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22161	/ 58540 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BMNZ_V),
22162	/ 58543 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22163	/ 58545 / GIR_RootToRootCopy, /OpIdx/`3`, // wd_in
22164	/ 58547 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
22165	/ 58549 / GIR_RootToRootCopy, /OpIdx/`1`, // wt
22166	/ 58551 / GIR_RootConstrainSelectedInstOperands,
22167	/ 58552 / // GIR_Coverage, 595,
22168	/ 58552 / GIR_EraseRootFromParent_Done,
22169	/ 58553 / // Label 1547: @58553
22170	/ 58553 / GIM_Try_CheckFeatures, /On fail goto//Label 1548/ GIMT_Encode4(`58573`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 597 //
22171	/* 58560 / // (vselect:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wt, MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws) => (BMZ_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22172	/ 58560 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BMZ_V),
22173	/ 58563 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22174	/ 58565 / GIR_RootToRootCopy, /OpIdx/`2`, // wd_in
22175	/ 58567 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22176	/ 58569 / GIR_RootToRootCopy, /OpIdx/`1`, // wt
22177	/ 58571 / GIR_RootConstrainSelectedInstOperands,
22178	/ 58572 / // GIR_Coverage, 597,
22179	/ 58572 / GIR_EraseRootFromParent_Done,
22180	/ 58573 / // Label 1548: @58573
22181	/ 58573 / GIM_Try_CheckFeatures, /On fail goto//Label 1549/ GIMT_Encode4(`58593`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 607 //
22182	/* 58580 / // (vselect:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$wt, MSA128BOpnd:{ :[v16i8] }:$ws) => (BSEL_V:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22183	/ 58580 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_V),
22184	/ 58583 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22185	/ 58585 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22186	/ 58587 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22187	/ 58589 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22188	/ 58591 / GIR_RootConstrainSelectedInstOperands,
22189	/ 58592 / // GIR_Coverage, 607,
22190	/ 58592 / GIR_EraseRootFromParent_Done,
22191	/ 58593 / // Label 1549: @58593
22192	/ 58593 / GIM_Reject,
22193	/ 58594 / // Label 1546: @58594
22194	/ 58594 / GIM_Reject,
22195	/ 58595 / // Label 1367: @58595
22196	/ 58595 / GIM_Try_CheckFeatures, /On fail goto//Label 1550/ GIMT_Encode4(`58640`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 608 //
22197	/ 58602 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
22198	/ 58605 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
22199	/ 58608 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v8s16,
22200	/ 58611 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
22201	/ 58615 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
22202	/ 58619 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
22203	/ 58623 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
22204	/* 58627 / // (vselect:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$wt, MSA128HOpnd:{ :[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
22205	/ 58627 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
22206	/ 58630 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22207	/ 58632 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22208	/ 58634 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22209	/ 58636 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22210	/ 58638 / GIR_RootConstrainSelectedInstOperands,
22211	/ 58639 / // GIR_Coverage, 608,
22212	/ 58639 / GIR_EraseRootFromParent_Done,
22213	/ 58640 / // Label 1550: @58640
22214	/ 58640 / GIM_Reject,
22215	/ 58641 / // Label 1368: @58641
22216	/ 58641 / GIM_Try, /On fail goto//Label 1551/ GIMT_Encode4(`58712`),
22217	/ 58646 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
22218	/ 58649 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
22219	/ 58652 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
22220	/ 58655 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22221	/ 58659 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22222	/ 58663 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22223	/ 58667 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22224	/ 58671 / GIM_Try_CheckFeatures, /On fail goto//Label 1552/ GIMT_Encode4(`58691`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 609 //
22225	/* 58678 / // (vselect:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$wt, MSA128WOpnd:{ :[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
22226	/ 58678 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
22227	/ 58681 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22228	/ 58683 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22229	/ 58685 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22230	/ 58687 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22231	/ 58689 / GIR_RootConstrainSelectedInstOperands,
22232	/ 58690 / // GIR_Coverage, 609,
22233	/ 58690 / GIR_EraseRootFromParent_Done,
22234	/ 58691 / // Label 1552: @58691
22235	/ 58691 / GIM_Try_CheckFeatures, /On fail goto//Label 1553/ GIMT_Encode4(`58711`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 611 //
22236	/* 58698 / // (vselect:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4f32] }:$wt, MSA128WOpnd:{ :[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22237	/ 58698 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
22238	/ 58701 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22239	/ 58703 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22240	/ 58705 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22241	/ 58707 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22242	/ 58709 / GIR_RootConstrainSelectedInstOperands,
22243	/ 58710 / // GIR_Coverage, 611,
22244	/ 58710 / GIR_EraseRootFromParent_Done,
22245	/ 58711 / // Label 1553: @58711
22246	/ 58711 / GIM_Reject,
22247	/ 58712 / // Label 1551: @58712
22248	/ 58712 / GIM_Reject,
22249	/ 58713 / // Label 1369: @58713
22250	/ 58713 / GIM_Try, /On fail goto//Label 1554/ GIMT_Encode4(`58784`),
22251	/ 58718 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
22252	/ 58721 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
22253	/ 58724 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
22254	/ 58727 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22255	/ 58731 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22256	/ 58735 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22257	/ 58739 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22258	/ 58743 / GIM_Try_CheckFeatures, /On fail goto//Label 1555/ GIMT_Encode4(`58763`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 610 //
22259	/* 58750 / // (vselect:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$wt, MSA128DOpnd:{ :[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
22260	/ 58750 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
22261	/ 58753 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22262	/ 58755 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22263	/ 58757 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22264	/ 58759 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22265	/ 58761 / GIR_RootConstrainSelectedInstOperands,
22266	/ 58762 / // GIR_Coverage, 610,
22267	/ 58762 / GIR_EraseRootFromParent_Done,
22268	/ 58763 / // Label 1555: @58763
22269	/ 58763 / GIM_Try_CheckFeatures, /On fail goto//Label 1556/ GIMT_Encode4(`58783`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 612 //
22270	/* 58770 / // (vselect:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2f64] }:$wt, MSA128DOpnd:{ :[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22271	/ 58770 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
22272	/ 58773 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22273	/ 58775 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
22274	/ 58777 / GIR_RootToRootCopy, /OpIdx/`3`, // ws
22275	/ 58779 / GIR_RootToRootCopy, /OpIdx/`2`, // wt
22276	/ 58781 / GIR_RootConstrainSelectedInstOperands,
22277	/ 58782 / // GIR_Coverage, 612,
22278	/ 58782 / GIR_EraseRootFromParent_Done,
22279	/ 58783 / // Label 1556: @58783
22280	/ 58783 / GIM_Reject,
22281	/ 58784 / // Label 1554: @58784
22282	/ 58784 / GIM_Reject,
22283	/ 58785 / // Label 1370: @58785
22284	/ 58785 / GIM_Reject,
22285	/ 58786 / // Label 44: @58786
22286	/ 58786 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1559/ GIMT_Encode4(`58891`),
22287	/ 58797 / /GILLT_s32//Label 1557/ GIMT_Encode4(`58805`),
22288	/ 58801 / /GILLT_s64//Label 1558/ GIMT_Encode4(`58858`),
22289	/ 58805 / // Label 1557: @58805
22290	/ 58805 / GIM_Try, /On fail goto//Label 1560/ GIMT_Encode4(`58857`),
22291	/ 58810 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
22292	/ 58813 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
22293	/ 58816 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22294	/ 58820 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22295	/ 58824 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22296	/ 58828 / GIM_Try_CheckFeatures, /On fail goto//Label 1561/ GIMT_Encode4(`58842`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 358 //
22297	/ 58835 / // (mulhu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUHU:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
22298	/ 58835 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUHU),
22299	/ 58840 / GIR_RootConstrainSelectedInstOperands,
22300	/ 58841 / // GIR_Coverage, 358,
22301	/ 58841 / GIR_Done,
22302	/ 58842 / // Label 1561: @58842
22303	/ 58842 / GIM_Try_CheckFeatures, /On fail goto//Label 1562/ GIMT_Encode4(`58856`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1202 //
22304	/ 58849 / // (mulhu:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUHU_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
22305	/ 58849 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUHU_MMR6),
22306	/ 58854 / GIR_RootConstrainSelectedInstOperands,
22307	/ 58855 / // GIR_Coverage, 1202,
22308	/ 58855 / GIR_Done,
22309	/ 58856 / // Label 1562: @58856
22310	/ 58856 / GIM_Reject,
22311	/ 58857 / // Label 1560: @58857
22312	/ 58857 / GIM_Reject,
22313	/ 58858 / // Label 1558: @58858
22314	/ 58858 / GIM_Try_CheckFeatures, /On fail goto//Label 1563/ GIMT_Encode4(`58890`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 373 //
22315	/ 58865 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
22316	/ 58868 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
22317	/ 58871 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22318	/ 58875 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22319	/ 58879 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22320	/ 58883 / // (mulhu:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMUHU:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
22321	/ 58883 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMUHU),
22322	/ 58888 / GIR_RootConstrainSelectedInstOperands,
22323	/ 58889 / // GIR_Coverage, 373,
22324	/ 58889 / GIR_Done,
22325	/ 58890 / // Label 1563: @58890
22326	/ 58890 / GIM_Reject,
22327	/ 58891 / // Label 1559: @58891
22328	/ 58891 / GIM_Reject,
22329	/ 58892 / // Label 45: @58892
22330	/ 58892 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1566/ GIMT_Encode4(`58997`),
22331	/ 58903 / /GILLT_s32//Label 1564/ GIMT_Encode4(`58911`),
22332	/ 58907 / /GILLT_s64//Label 1565/ GIMT_Encode4(`58964`),
22333	/ 58911 / // Label 1564: @58911
22334	/ 58911 / GIM_Try, /On fail goto//Label 1567/ GIMT_Encode4(`58963`),
22335	/ 58916 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
22336	/ 58919 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
22337	/ 58922 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22338	/ 58926 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22339	/ 58930 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
22340	/ 58934 / GIM_Try_CheckFeatures, /On fail goto//Label 1568/ GIMT_Encode4(`58948`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 357 //
22341	/ 58941 / // (mulhs:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUH:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
22342	/ 58941 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUH),
22343	/ 58946 / GIR_RootConstrainSelectedInstOperands,
22344	/ 58947 / // GIR_Coverage, 357,
22345	/ 58947 / GIR_Done,
22346	/ 58948 / // Label 1568: @58948
22347	/ 58948 / GIM_Try_CheckFeatures, /On fail goto//Label 1569/ GIMT_Encode4(`58962`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1201 //
22348	/ 58955 / // (mulhs:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt) => (MUH_MMR6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, GPR32Opnd:{ :[i32] }:$rt)
22349	/ 58955 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MUH_MMR6),
22350	/ 58960 / GIR_RootConstrainSelectedInstOperands,
22351	/ 58961 / // GIR_Coverage, 1201,
22352	/ 58961 / GIR_Done,
22353	/ 58962 / // Label 1569: @58962
22354	/ 58962 / GIM_Reject,
22355	/ 58963 / // Label 1567: @58963
22356	/ 58963 / GIM_Reject,
22357	/ 58964 / // Label 1565: @58964
22358	/ 58964 / GIM_Try_CheckFeatures, /On fail goto//Label 1570/ GIMT_Encode4(`58996`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 372 //
22359	/ 58971 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
22360	/ 58974 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
22361	/ 58977 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22362	/ 58981 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22363	/ 58985 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
22364	/ 58989 / // (mulhs:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt) => (DMUH:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, GPR64Opnd:{ :[i64] }:$rt)
22365	/ 58989 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DMUH),
22366	/ 58994 / GIR_RootConstrainSelectedInstOperands,
22367	/ 58995 / // GIR_Coverage, 372,
22368	/ 58995 / GIR_Done,
22369	/ 58996 / // Label 1570: @58996
22370	/ 58996 / GIM_Reject,
22371	/ 58997 / // Label 1566: @58997
22372	/ 58997 / GIM_Reject,
22373	/ 58998 / // Label 46: @58998
22374	/ 58998 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1575/ GIMT_Encode4(`60269`),
22375	/ 59009 / /GILLT_s32//Label 1571/ GIMT_Encode4(`59041`),
22376	/ 59013 / /GILLT_s64//Label 1572/ GIMT_Encode4(`59350`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
22377	/ 59033 / /GILLT_v4s32//Label 1573/ GIMT_Encode4(`59963`),
22378	/ 59037 / /GILLT_v2s64//Label 1574/ GIMT_Encode4(`60116`),
22379	/ 59041 / // Label 1571: @59041
22380	/ 59041 / GIM_Try, /On fail goto//Label 1576/ GIMT_Encode4(`59349`),
22381	/ 59046 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
22382	/ 59049 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
22383	/ 59052 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22384	/ 59056 / GIM_Try, /On fail goto//Label 1577/ GIMT_Encode4(`59170`),
22385	/ 59061 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22386	/ 59065 / GIM_Try_CheckFeatures, /On fail goto//Label 1578/ GIMT_Encode4(`59117`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 181 //
22387	/ 59072 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22388	/ 59076 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22389	/ 59080 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22390	/ 59084 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22391	/ 59088 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22392	/ 59093 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22393	/ 59098 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22394	/* 59100 / // (fadd:{ :[f32] } (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22395	/ 59100 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
22396	/ 59103 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22397	/ 59105 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22398	/ 59107 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22399	/ 59111 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22400	/ 59115 / GIR_RootConstrainSelectedInstOperands,
22401	/ 59116 / // GIR_Coverage, 181,
22402	/ 59116 / GIR_EraseRootFromParent_Done,
22403	/ 59117 / // Label 1578: @59117
22404	/ 59117 / GIM_Try_CheckFeatures, /On fail goto//Label 1579/ GIMT_Encode4(`59169`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 180 //
22405	/ 59124 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22406	/ 59128 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22407	/ 59132 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22408	/ 59136 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22409	/ 59140 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22410	/ 59145 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22411	/ 59150 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22412	/* 59152 / // (fadd:{ :[f32] } (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22413	/ 59152 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
22414	/ 59155 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22415	/ 59157 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22416	/ 59159 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22417	/ 59163 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22418	/ 59167 / GIR_RootConstrainSelectedInstOperands,
22419	/ 59168 / // GIR_Coverage, 180,
22420	/ 59168 / GIR_EraseRootFromParent_Done,
22421	/ 59169 / // Label 1579: @59169
22422	/ 59169 / GIM_Reject,
22423	/ 59170 / // Label 1577: @59170
22424	/ 59170 / GIM_Try, /On fail goto//Label 1580/ GIMT_Encode4(`59348`),
22425	/ 59175 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22426	/ 59179 / GIM_Try_CheckFeatures, /On fail goto//Label 1581/ GIMT_Encode4(`59231`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2489 //
22427	/ 59186 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22428	/ 59190 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22429	/ 59194 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22430	/ 59198 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22431	/ 59202 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22432	/ 59207 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22433	/ 59212 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22434	/* 59214 / // (fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22435	/ 59214 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
22436	/ 59217 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22437	/ 59219 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22438	/ 59221 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22439	/ 59225 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22440	/ 59229 / GIR_RootConstrainSelectedInstOperands,
22441	/ 59230 / // GIR_Coverage, 2489,
22442	/ 59230 / GIR_EraseRootFromParent_Done,
22443	/ 59231 / // Label 1581: @59231
22444	/ 59231 / GIM_Try_CheckFeatures, /On fail goto//Label 1582/ GIMT_Encode4(`59283`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2488 //
22445	/ 59238 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22446	/ 59242 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22447	/ 59246 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22448	/ 59250 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22449	/ 59254 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22450	/ 59259 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22451	/ 59264 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22452	/* 59266 / // (fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22453	/ 59266 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
22454	/ 59269 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22455	/ 59271 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22456	/ 59273 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22457	/ 59277 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22458	/ 59281 / GIR_RootConstrainSelectedInstOperands,
22459	/ 59282 / // GIR_Coverage, 2488,
22460	/ 59282 / GIR_EraseRootFromParent_Done,
22461	/ 59283 / // Label 1582: @59283
22462	/ 59283 / GIM_Try, /On fail goto//Label 1583/ GIMT_Encode4(`59347`),
22463	/ 59288 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22464	/ 59292 / GIM_Try_CheckFeatures, /On fail goto//Label 1584/ GIMT_Encode4(`59310`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 155 //
22465	/ 59299 / // (fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22466	/ 59299 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_S),
22467	/ 59304 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22468	/ 59308 / GIR_RootConstrainSelectedInstOperands,
22469	/ 59309 / // GIR_Coverage, 155,
22470	/ 59309 / GIR_Done,
22471	/ 59310 / // Label 1584: @59310
22472	/ 59310 / GIM_Try_CheckFeatures, /On fail goto//Label 1585/ GIMT_Encode4(`59328`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1151 //
22473	/ 59317 / // (fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FADD_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22474	/ 59317 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_S_MM),
22475	/ 59322 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22476	/ 59326 / GIR_RootConstrainSelectedInstOperands,
22477	/ 59327 / // GIR_Coverage, 1151,
22478	/ 59327 / GIR_Done,
22479	/ 59328 / // Label 1585: @59328
22480	/ 59328 / GIM_Try_CheckFeatures, /On fail goto//Label 1586/ GIMT_Encode4(`59346`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1209 //
22481	/ 59335 / // (fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FADD_S_MMR6:{ :[f32] } FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs)
22482	/ 59335 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FADD_S_MMR6),
22483	/ 59338 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22484	/ 59340 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
22485	/ 59342 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
22486	/ 59344 / GIR_RootConstrainSelectedInstOperands,
22487	/ 59345 / // GIR_Coverage, 1209,
22488	/ 59345 / GIR_EraseRootFromParent_Done,
22489	/ 59346 / // Label 1586: @59346
22490	/ 59346 / GIM_Reject,
22491	/ 59347 / // Label 1583: @59347
22492	/ 59347 / GIM_Reject,
22493	/ 59348 / // Label 1580: @59348
22494	/ 59348 / GIM_Reject,
22495	/ 59349 / // Label 1576: @59349
22496	/ 59349 / GIM_Reject,
22497	/ 59350 / // Label 1572: @59350
22498	/ 59350 / GIM_Try, /On fail goto//Label 1587/ GIMT_Encode4(`59962`),
22499	/ 59355 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
22500	/ 59358 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
22501	/ 59361 / GIM_Try_CheckFeatures, /On fail goto//Label 1588/ GIMT_Encode4(`59421`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 189 //
22502	/ 59368 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22503	/ 59372 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22504	/ 59376 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22505	/ 59380 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22506	/ 59384 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22507	/ 59388 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22508	/ 59393 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22509	/ 59398 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22510	/ 59402 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22511	/* 59404 / // (fadd:{ :[f64] } (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22512	/ 59404 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
22513	/ 59407 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22514	/ 59409 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22515	/ 59411 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22516	/ 59415 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22517	/ 59419 / GIR_RootConstrainSelectedInstOperands,
22518	/ 59420 / // GIR_Coverage, 189,
22519	/ 59420 / GIR_EraseRootFromParent_Done,
22520	/ 59421 / // Label 1588: @59421
22521	/ 59421 / GIM_Try_CheckFeatures, /On fail goto//Label 1589/ GIMT_Encode4(`59481`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 197 //
22522	/ 59428 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22523	/ 59432 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22524	/ 59436 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22525	/ 59440 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22526	/ 59444 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22527	/ 59448 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22528	/ 59453 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22529	/ 59458 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22530	/ 59462 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22531	/* 59464 / // (fadd:{ :[f64] } (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22532	/ 59464 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
22533	/ 59467 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22534	/ 59469 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22535	/ 59471 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22536	/ 59475 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22537	/ 59479 / GIR_RootConstrainSelectedInstOperands,
22538	/ 59480 / // GIR_Coverage, 197,
22539	/ 59480 / GIR_EraseRootFromParent_Done,
22540	/ 59481 / // Label 1589: @59481
22541	/ 59481 / GIM_Try_CheckFeatures, /On fail goto//Label 1590/ GIMT_Encode4(`59541`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 188 //
22542	/ 59488 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22543	/ 59492 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22544	/ 59496 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22545	/ 59500 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22546	/ 59504 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22547	/ 59508 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22548	/ 59513 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22549	/ 59518 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22550	/ 59522 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22551	/* 59524 / // (fadd:{ :[f64] } (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22552	/ 59524 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
22553	/ 59527 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22554	/ 59529 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22555	/ 59531 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22556	/ 59535 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22557	/ 59539 / GIR_RootConstrainSelectedInstOperands,
22558	/ 59540 / // GIR_Coverage, 188,
22559	/ 59540 / GIR_EraseRootFromParent_Done,
22560	/ 59541 / // Label 1590: @59541
22561	/ 59541 / GIM_Try_CheckFeatures, /On fail goto//Label 1591/ GIMT_Encode4(`59601`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 196 //
22562	/ 59548 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22563	/ 59552 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22564	/ 59556 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22565	/ 59560 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22566	/ 59564 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22567	/ 59568 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22568	/ 59573 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22569	/ 59578 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22570	/ 59582 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22571	/* 59584 / // (fadd:{ :[f64] } (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22572	/ 59584 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
22573	/ 59587 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22574	/ 59589 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22575	/ 59591 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22576	/ 59595 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22577	/ 59599 / GIR_RootConstrainSelectedInstOperands,
22578	/ 59600 / // GIR_Coverage, 196,
22579	/ 59600 / GIR_EraseRootFromParent_Done,
22580	/ 59601 / // Label 1591: @59601
22581	/ 59601 / GIM_Try_CheckFeatures, /On fail goto//Label 1592/ GIMT_Encode4(`59661`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2493 //
22582	/ 59608 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22583	/ 59612 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22584	/ 59616 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22585	/ 59620 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22586	/ 59624 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22587	/ 59628 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22588	/ 59632 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22589	/ 59637 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22590	/ 59642 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22591	/* 59644 / // (fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22592	/ 59644 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
22593	/ 59647 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22594	/ 59649 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22595	/ 59651 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22596	/ 59655 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22597	/ 59659 / GIR_RootConstrainSelectedInstOperands,
22598	/ 59660 / // GIR_Coverage, 2493,
22599	/ 59660 / GIR_EraseRootFromParent_Done,
22600	/ 59661 / // Label 1592: @59661
22601	/ 59661 / GIM_Try_CheckFeatures, /On fail goto//Label 1593/ GIMT_Encode4(`59721`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2497 //
22602	/ 59668 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22603	/ 59672 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22604	/ 59676 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22605	/ 59680 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22606	/ 59684 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22607	/ 59688 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22608	/ 59692 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22609	/ 59697 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22610	/ 59702 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22611	/* 59704 / // (fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22612	/ 59704 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
22613	/ 59707 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22614	/ 59709 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22615	/ 59711 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22616	/ 59715 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22617	/ 59719 / GIR_RootConstrainSelectedInstOperands,
22618	/ 59720 / // GIR_Coverage, 2497,
22619	/ 59720 / GIR_EraseRootFromParent_Done,
22620	/ 59721 / // Label 1593: @59721
22621	/ 59721 / GIM_Try_CheckFeatures, /On fail goto//Label 1594/ GIMT_Encode4(`59781`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2492 //
22622	/ 59728 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22623	/ 59732 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22624	/ 59736 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22625	/ 59740 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22626	/ 59744 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22627	/ 59748 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22628	/ 59752 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22629	/ 59757 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22630	/ 59762 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22631	/* 59764 / // (fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22632	/ 59764 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
22633	/ 59767 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22634	/ 59769 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22635	/ 59771 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22636	/ 59775 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22637	/ 59779 / GIR_RootConstrainSelectedInstOperands,
22638	/ 59780 / // GIR_Coverage, 2492,
22639	/ 59780 / GIR_EraseRootFromParent_Done,
22640	/ 59781 / // Label 1594: @59781
22641	/ 59781 / GIM_Try_CheckFeatures, /On fail goto//Label 1595/ GIMT_Encode4(`59841`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2496 //
22642	/ 59788 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22643	/ 59792 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22644	/ 59796 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22645	/ 59800 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22646	/ 59804 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22647	/ 59808 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22648	/ 59812 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22649	/ 59817 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22650	/ 59822 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22651	/* 59824 / // (fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22652	/ 59824 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
22653	/ 59827 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22654	/ 59829 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
22655	/ 59831 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22656	/ 59835 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22657	/ 59839 / GIR_RootConstrainSelectedInstOperands,
22658	/ 59840 / // GIR_Coverage, 2496,
22659	/ 59840 / GIR_EraseRootFromParent_Done,
22660	/ 59841 / // Label 1595: @59841
22661	/ 59841 / GIM_Try_CheckFeatures, /On fail goto//Label 1596/ GIMT_Encode4(`59871`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 157 //
22662	/ 59848 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22663	/ 59852 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22664	/ 59856 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22665	/ 59860 / // (fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22666	/ 59860 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D32),
22667	/ 59865 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22668	/ 59869 / GIR_RootConstrainSelectedInstOperands,
22669	/ 59870 / // GIR_Coverage, 157,
22670	/ 59870 / GIR_Done,
22671	/ 59871 / // Label 1596: @59871
22672	/ 59871 / GIM_Try_CheckFeatures, /On fail goto//Label 1597/ GIMT_Encode4(`59901`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 159 //
22673	/ 59878 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22674	/ 59882 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22675	/ 59886 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22676	/ 59890 / // (fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22677	/ 59890 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D64),
22678	/ 59895 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22679	/ 59899 / GIR_RootConstrainSelectedInstOperands,
22680	/ 59900 / // GIR_Coverage, 159,
22681	/ 59900 / GIR_Done,
22682	/ 59901 / // Label 1597: @59901
22683	/ 59901 / GIM_Try_CheckFeatures, /On fail goto//Label 1598/ GIMT_Encode4(`59931`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1155 //
22684	/ 59908 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22685	/ 59912 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22686	/ 59916 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22687	/ 59920 / // (fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FADD_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22688	/ 59920 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D32_MM),
22689	/ 59925 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22690	/ 59929 / GIR_RootConstrainSelectedInstOperands,
22691	/ 59930 / // GIR_Coverage, 1155,
22692	/ 59930 / GIR_Done,
22693	/ 59931 / // Label 1598: @59931
22694	/ 59931 / GIM_Try_CheckFeatures, /On fail goto//Label 1599/ GIMT_Encode4(`59961`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1156 //
22695	/ 59938 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22696	/ 59942 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22697	/ 59946 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22698	/ 59950 / // (fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FADD_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22699	/ 59950 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D64_MM),
22700	/ 59955 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22701	/ 59959 / GIR_RootConstrainSelectedInstOperands,
22702	/ 59960 / // GIR_Coverage, 1156,
22703	/ 59960 / GIR_Done,
22704	/ 59961 / // Label 1599: @59961
22705	/ 59961 / GIM_Reject,
22706	/ 59962 / // Label 1587: @59962
22707	/ 59962 / GIM_Reject,
22708	/ 59963 / // Label 1573: @59963
22709	/ 59963 / GIM_Try, /On fail goto//Label 1600/ GIMT_Encode4(`60115`),
22710	/ 59968 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
22711	/ 59971 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
22712	/ 59974 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22713	/ 59978 / GIM_Try_CheckFeatures, /On fail goto//Label 1601/ GIMT_Encode4(`60034`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2631 //
22714	/ 59985 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22715	/ 59989 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22716	/ 59993 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
22717	/ 59997 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
22718	/ 60001 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22719	/ 60006 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22720	/ 60011 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22721	/ 60015 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22722	/* 60017 / // (fadd:{ :[v4f32] } (fmul:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt), MSA128WOpnd:{ :[v4f32] }:$wd) => (FMADD_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
22723	/ 60017 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMADD_W),
22724	/ 60020 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22725	/ 60022 / GIR_RootToRootCopy, /OpIdx/`2`, // wd
22726	/ 60024 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
22727	/ 60028 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
22728	/ 60032 / GIR_RootConstrainSelectedInstOperands,
22729	/ 60033 / // GIR_Coverage, 2631,
22730	/ 60033 / GIR_EraseRootFromParent_Done,
22731	/ 60034 / // Label 1601: @60034
22732	/ 60034 / GIM_Try, /On fail goto//Label 1602/ GIMT_Encode4(`60114`),
22733	/ 60039 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22734	/ 60043 / GIM_Try_CheckFeatures, /On fail goto//Label 1603/ GIMT_Encode4(`60095`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2119 //
22735	/ 60050 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22736	/ 60054 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22737	/ 60058 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
22738	/ 60062 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
22739	/ 60066 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22740	/ 60071 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22741	/ 60076 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22742	/* 60078 / // (fadd:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd, (fmul:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)) => (FMADD_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
22743	/ 60078 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMADD_W),
22744	/ 60081 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22745	/ 60083 / GIR_RootToRootCopy, /OpIdx/`1`, // wd
22746	/ 60085 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
22747	/ 60089 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
22748	/ 60093 / GIR_RootConstrainSelectedInstOperands,
22749	/ 60094 / // GIR_Coverage, 2119,
22750	/ 60094 / GIR_EraseRootFromParent_Done,
22751	/ 60095 / // Label 1603: @60095
22752	/ 60095 / GIM_Try_CheckFeatures, /On fail goto//Label 1604/ GIMT_Encode4(`60113`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 697 //
22753	/ 60102 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
22754	/ 60106 / // (fadd:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FADD_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
22755	/ 60106 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_W),
22756	/ 60111 / GIR_RootConstrainSelectedInstOperands,
22757	/ 60112 / // GIR_Coverage, 697,
22758	/ 60112 / GIR_Done,
22759	/ 60113 / // Label 1604: @60113
22760	/ 60113 / GIM_Reject,
22761	/ 60114 / // Label 1602: @60114
22762	/ 60114 / GIM_Reject,
22763	/ 60115 / // Label 1600: @60115
22764	/ 60115 / GIM_Reject,
22765	/ 60116 / // Label 1574: @60116
22766	/ 60116 / GIM_Try, /On fail goto//Label 1605/ GIMT_Encode4(`60268`),
22767	/ 60121 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
22768	/ 60124 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
22769	/ 60127 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22770	/ 60131 / GIM_Try_CheckFeatures, /On fail goto//Label 1606/ GIMT_Encode4(`60187`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2632 //
22771	/ 60138 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22772	/ 60142 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22773	/ 60146 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
22774	/ 60150 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
22775	/ 60154 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22776	/ 60159 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22777	/ 60164 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22778	/ 60168 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22779	/* 60170 / // (fadd:{ :[v2f64] } (fmul:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt), MSA128DOpnd:{ :[v2f64] }:$wd) => (FMADD_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
22780	/ 60170 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMADD_D),
22781	/ 60173 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22782	/ 60175 / GIR_RootToRootCopy, /OpIdx/`2`, // wd
22783	/ 60177 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
22784	/ 60181 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
22785	/ 60185 / GIR_RootConstrainSelectedInstOperands,
22786	/ 60186 / // GIR_Coverage, 2632,
22787	/ 60186 / GIR_EraseRootFromParent_Done,
22788	/ 60187 / // Label 1606: @60187
22789	/ 60187 / GIM_Try, /On fail goto//Label 1607/ GIMT_Encode4(`60267`),
22790	/ 60192 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22791	/ 60196 / GIM_Try_CheckFeatures, /On fail goto//Label 1608/ GIMT_Encode4(`60248`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2120 //
22792	/ 60203 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
22793	/ 60207 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22794	/ 60211 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
22795	/ 60215 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
22796	/ 60219 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22797	/ 60224 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22798	/ 60229 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22799	/* 60231 / // (fadd:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd, (fmul:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)) => (FMADD_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
22800	/ 60231 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMADD_D),
22801	/ 60234 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
22802	/ 60236 / GIR_RootToRootCopy, /OpIdx/`1`, // wd
22803	/ 60238 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
22804	/ 60242 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
22805	/ 60246 / GIR_RootConstrainSelectedInstOperands,
22806	/ 60247 / // GIR_Coverage, 2120,
22807	/ 60247 / GIR_EraseRootFromParent_Done,
22808	/ 60248 / // Label 1608: @60248
22809	/ 60248 / GIM_Try_CheckFeatures, /On fail goto//Label 1609/ GIMT_Encode4(`60266`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 698 //
22810	/ 60255 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
22811	/ 60259 / // (fadd:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FADD_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
22812	/ 60259 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D),
22813	/ 60264 / GIR_RootConstrainSelectedInstOperands,
22814	/ 60265 / // GIR_Coverage, 698,
22815	/ 60265 / GIR_Done,
22816	/ 60266 / // Label 1609: @60266
22817	/ 60266 / GIM_Reject,
22818	/ 60267 / // Label 1607: @60267
22819	/ 60267 / GIM_Reject,
22820	/ 60268 / // Label 1605: @60268
22821	/ 60268 / GIM_Reject,
22822	/ 60269 / // Label 1575: @60269
22823	/ 60269 / GIM_Reject,
22824	/ 60270 / // Label 47: @60270
22825	/ 60270 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1614/ GIMT_Encode4(`61067`),
22826	/ 60281 / /GILLT_s32//Label 1610/ GIMT_Encode4(`60313`),
22827	/ 60285 / /GILLT_s64//Label 1611/ GIMT_Encode4(`60512`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
22828	/ 60305 / /GILLT_v4s32//Label 1612/ GIMT_Encode4(`60885`),
22829	/ 60309 / /GILLT_v2s64//Label 1613/ GIMT_Encode4(`60976`),
22830	/ 60313 / // Label 1610: @60313
22831	/ 60313 / GIM_Try, /On fail goto//Label 1615/ GIMT_Encode4(`60511`),
22832	/ 60318 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
22833	/ 60321 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
22834	/ 60324 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22835	/ 60328 / GIM_Try, /On fail goto//Label 1616/ GIMT_Encode4(`60442`),
22836	/ 60333 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22837	/ 60337 / GIM_Try_CheckFeatures, /On fail goto//Label 1617/ GIMT_Encode4(`60389`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 185 //
22838	/ 60344 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22839	/ 60348 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22840	/ 60352 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22841	/ 60356 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22842	/ 60360 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22843	/ 60365 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22844	/ 60370 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22845	/* 60372 / // (fsub:{ :[f32] } (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22846	/ 60372 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_S),
22847	/ 60375 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22848	/ 60377 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22849	/ 60379 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22850	/ 60383 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22851	/ 60387 / GIR_RootConstrainSelectedInstOperands,
22852	/ 60388 / // GIR_Coverage, 185,
22853	/ 60388 / GIR_EraseRootFromParent_Done,
22854	/ 60389 / // Label 1617: @60389
22855	/ 60389 / GIM_Try_CheckFeatures, /On fail goto//Label 1618/ GIMT_Encode4(`60441`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 184 //
22856	/ 60396 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22857	/ 60400 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22858	/ 60404 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
22859	/ 60408 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
22860	/ 60412 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22861	/ 60417 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22862	/ 60422 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22863	/* 60424 / // (fsub:{ :[f32] } (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22864	/ 60424 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_S),
22865	/ 60427 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22866	/ 60429 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22867	/ 60431 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22868	/ 60435 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22869	/ 60439 / GIR_RootConstrainSelectedInstOperands,
22870	/ 60440 / // GIR_Coverage, 184,
22871	/ 60440 / GIR_EraseRootFromParent_Done,
22872	/ 60441 / // Label 1618: @60441
22873	/ 60441 / GIM_Reject,
22874	/ 60442 / // Label 1616: @60442
22875	/ 60442 / GIM_Try, /On fail goto//Label 1619/ GIMT_Encode4(`60510`),
22876	/ 60447 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22877	/ 60451 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
22878	/ 60455 / GIM_Try_CheckFeatures, /On fail goto//Label 1620/ GIMT_Encode4(`60473`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 173 //
22879	/ 60462 / // (fsub:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22880	/ 60462 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_S),
22881	/ 60467 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22882	/ 60471 / GIR_RootConstrainSelectedInstOperands,
22883	/ 60472 / // GIR_Coverage, 173,
22884	/ 60472 / GIR_Done,
22885	/ 60473 / // Label 1620: @60473
22886	/ 60473 / GIM_Try_CheckFeatures, /On fail goto//Label 1621/ GIMT_Encode4(`60491`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1154 //
22887	/ 60480 / // (fsub:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FSUB_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
22888	/ 60480 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_S_MM),
22889	/ 60485 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
22890	/ 60489 / GIR_RootConstrainSelectedInstOperands,
22891	/ 60490 / // GIR_Coverage, 1154,
22892	/ 60490 / GIR_Done,
22893	/ 60491 / // Label 1621: @60491
22894	/ 60491 / GIM_Try_CheckFeatures, /On fail goto//Label 1622/ GIMT_Encode4(`60509`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1210 //
22895	/ 60498 / // (fsub:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FSUB_S_MMR6:{ :[f32] } FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs)
22896	/ 60498 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FSUB_S_MMR6),
22897	/ 60501 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22898	/ 60503 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
22899	/ 60505 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
22900	/ 60507 / GIR_RootConstrainSelectedInstOperands,
22901	/ 60508 / // GIR_Coverage, 1210,
22902	/ 60508 / GIR_EraseRootFromParent_Done,
22903	/ 60509 / // Label 1622: @60509
22904	/ 60509 / GIM_Reject,
22905	/ 60510 / // Label 1619: @60510
22906	/ 60510 / GIM_Reject,
22907	/ 60511 / // Label 1615: @60511
22908	/ 60511 / GIM_Reject,
22909	/ 60512 / // Label 1611: @60512
22910	/ 60512 / GIM_Try, /On fail goto//Label 1623/ GIMT_Encode4(`60884`),
22911	/ 60517 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
22912	/ 60520 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
22913	/ 60523 / GIM_Try_CheckFeatures, /On fail goto//Label 1624/ GIMT_Encode4(`60583`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 193 //
22914	/ 60530 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22915	/ 60534 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22916	/ 60538 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22917	/ 60542 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22918	/ 60546 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22919	/ 60550 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22920	/ 60555 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22921	/ 60560 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22922	/ 60564 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22923	/* 60566 / // (fsub:{ :[f64] } (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22924	/ 60566 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D32),
22925	/ 60569 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22926	/ 60571 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22927	/ 60573 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22928	/ 60577 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22929	/ 60581 / GIR_RootConstrainSelectedInstOperands,
22930	/ 60582 / // GIR_Coverage, 193,
22931	/ 60582 / GIR_EraseRootFromParent_Done,
22932	/ 60583 / // Label 1624: @60583
22933	/ 60583 / GIM_Try_CheckFeatures, /On fail goto//Label 1625/ GIMT_Encode4(`60643`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 201 //
22934	/ 60590 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22935	/ 60594 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22936	/ 60598 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
22937	/ 60602 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22938	/ 60606 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22939	/ 60610 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22940	/ 60615 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22941	/ 60620 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22942	/ 60624 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22943	/* 60626 / // (fsub:{ :[f64] } (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22944	/ 60626 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D64),
22945	/ 60629 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22946	/ 60631 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22947	/ 60633 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22948	/ 60637 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22949	/ 60641 / GIR_RootConstrainSelectedInstOperands,
22950	/ 60642 / // GIR_Coverage, 201,
22951	/ 60642 / GIR_EraseRootFromParent_Done,
22952	/ 60643 / // Label 1625: @60643
22953	/ 60643 / GIM_Try_CheckFeatures, /On fail goto//Label 1626/ GIMT_Encode4(`60703`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 192 //
22954	/ 60650 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22955	/ 60654 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22956	/ 60658 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22957	/ 60662 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22958	/ 60666 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22959	/ 60670 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22960	/ 60675 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22961	/ 60680 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22962	/ 60684 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22963	/* 60686 / // (fsub:{ :[f64] } (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22964	/ 60686 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D32),
22965	/ 60689 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22966	/ 60691 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22967	/ 60693 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22968	/ 60697 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22969	/ 60701 / GIR_RootConstrainSelectedInstOperands,
22970	/ 60702 / // GIR_Coverage, 192,
22971	/ 60702 / GIR_EraseRootFromParent_Done,
22972	/ 60703 / // Label 1626: @60703
22973	/ 60703 / GIM_Try_CheckFeatures, /On fail goto//Label 1627/ GIMT_Encode4(`60763`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 200 //
22974	/ 60710 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22975	/ 60714 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
22976	/ 60718 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22977	/ 60722 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
22978	/ 60726 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
22979	/ 60730 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22980	/ 60735 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22981	/ 60740 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
22982	/ 60744 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
22983	/* 60746 / // (fsub:{ :[f64] } (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
22984	/ 60746 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D64),
22985	/ 60749 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
22986	/ 60751 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
22987	/ 60753 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
22988	/ 60757 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
22989	/ 60761 / GIR_RootConstrainSelectedInstOperands,
22990	/ 60762 / // GIR_Coverage, 200,
22991	/ 60762 / GIR_EraseRootFromParent_Done,
22992	/ 60763 / // Label 1627: @60763
22993	/ 60763 / GIM_Try_CheckFeatures, /On fail goto//Label 1628/ GIMT_Encode4(`60793`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 175 //
22994	/ 60770 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22995	/ 60774 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22996	/ 60778 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
22997	/ 60782 / // (fsub:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
22998	/ 60782 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D32),
22999	/ 60787 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23000	/ 60791 / GIR_RootConstrainSelectedInstOperands,
23001	/ 60792 / // GIR_Coverage, 175,
23002	/ 60792 / GIR_Done,
23003	/ 60793 / // Label 1628: @60793
23004	/ 60793 / GIM_Try_CheckFeatures, /On fail goto//Label 1629/ GIMT_Encode4(`60823`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 177 //
23005	/ 60800 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23006	/ 60804 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23007	/ 60808 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23008	/ 60812 / // (fsub:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23009	/ 60812 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D64),
23010	/ 60817 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23011	/ 60821 / GIR_RootConstrainSelectedInstOperands,
23012	/ 60822 / // GIR_Coverage, 177,
23013	/ 60822 / GIR_Done,
23014	/ 60823 / // Label 1629: @60823
23015	/ 60823 / GIM_Try_CheckFeatures, /On fail goto//Label 1630/ GIMT_Encode4(`60853`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1161 //
23016	/ 60830 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23017	/ 60834 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23018	/ 60838 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23019	/ 60842 / // (fsub:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FSUB_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
23020	/ 60842 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D32_MM),
23021	/ 60847 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23022	/ 60851 / GIR_RootConstrainSelectedInstOperands,
23023	/ 60852 / // GIR_Coverage, 1161,
23024	/ 60852 / GIR_Done,
23025	/ 60853 / // Label 1630: @60853
23026	/ 60853 / GIM_Try_CheckFeatures, /On fail goto//Label 1631/ GIMT_Encode4(`60883`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1162 //
23027	/ 60860 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23028	/ 60864 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23029	/ 60868 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23030	/ 60872 / // (fsub:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FSUB_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23031	/ 60872 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D64_MM),
23032	/ 60877 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23033	/ 60881 / GIR_RootConstrainSelectedInstOperands,
23034	/ 60882 / // GIR_Coverage, 1162,
23035	/ 60882 / GIR_Done,
23036	/ 60883 / // Label 1631: @60883
23037	/ 60883 / GIM_Reject,
23038	/ 60884 / // Label 1623: @60884
23039	/ 60884 / GIM_Reject,
23040	/ 60885 / // Label 1612: @60885
23041	/ 60885 / GIM_Try, /On fail goto//Label 1632/ GIMT_Encode4(`60975`),
23042	/ 60890 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23043	/ 60893 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
23044	/ 60896 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23045	/ 60900 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23046	/ 60904 / GIM_Try_CheckFeatures, /On fail goto//Label 1633/ GIMT_Encode4(`60956`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2117 //
23047	/ 60911 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
23048	/ 60915 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
23049	/ 60919 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
23050	/ 60923 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v4s32,
23051	/ 60927 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23052	/ 60932 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23053	/ 60937 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23054	/* 60939 / // (fsub:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd, (fmul:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)) => (FMSUB_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23055	/ 60939 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMSUB_W),
23056	/ 60942 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23057	/ 60944 / GIR_RootToRootCopy, /OpIdx/`1`, // wd
23058	/ 60946 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
23059	/ 60950 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
23060	/ 60954 / GIR_RootConstrainSelectedInstOperands,
23061	/ 60955 / // GIR_Coverage, 2117,
23062	/ 60955 / GIR_EraseRootFromParent_Done,
23063	/ 60956 / // Label 1633: @60956
23064	/ 60956 / GIM_Try_CheckFeatures, /On fail goto//Label 1634/ GIMT_Encode4(`60974`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 785 //
23065	/ 60963 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23066	/ 60967 / // (fsub:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FSUB_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23067	/ 60967 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_W),
23068	/ 60972 / GIR_RootConstrainSelectedInstOperands,
23069	/ 60973 / // GIR_Coverage, 785,
23070	/ 60973 / GIR_Done,
23071	/ 60974 / // Label 1634: @60974
23072	/ 60974 / GIM_Reject,
23073	/ 60975 / // Label 1632: @60975
23074	/ 60975 / GIM_Reject,
23075	/ 60976 / // Label 1613: @60976
23076	/ 60976 / GIM_Try, /On fail goto//Label 1635/ GIMT_Encode4(`61066`),
23077	/ 60981 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23078	/ 60984 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
23079	/ 60987 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23080	/ 60991 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23081	/ 60995 / GIM_Try_CheckFeatures, /On fail goto//Label 1636/ GIMT_Encode4(`61047`), GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc), // Rule ID 2118 //
23082	/ 61002 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
23083	/ 61006 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
23084	/ 61010 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
23085	/ 61014 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_v2s64,
23086	/ 61018 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23087	/ 61023 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23088	/ 61028 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23089	/* 61030 / // (fsub:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd, (fmul:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)) => (FMSUB_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23090	/ 61030 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMSUB_D),
23091	/ 61033 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23092	/ 61035 / GIR_RootToRootCopy, /OpIdx/`1`, // wd
23093	/ 61037 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // ws
23094	/ 61041 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // wt
23095	/ 61045 / GIR_RootConstrainSelectedInstOperands,
23096	/ 61046 / // GIR_Coverage, 2118,
23097	/ 61046 / GIR_EraseRootFromParent_Done,
23098	/ 61047 / // Label 1636: @61047
23099	/ 61047 / GIM_Try_CheckFeatures, /On fail goto//Label 1637/ GIMT_Encode4(`61065`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 786 //
23100	/ 61054 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23101	/ 61058 / // (fsub:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FSUB_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23102	/ 61058 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D),
23103	/ 61063 / GIR_RootConstrainSelectedInstOperands,
23104	/ 61064 / // GIR_Coverage, 786,
23105	/ 61064 / GIR_Done,
23106	/ 61065 / // Label 1637: @61065
23107	/ 61065 / GIM_Reject,
23108	/ 61066 / // Label 1635: @61066
23109	/ 61066 / GIM_Reject,
23110	/ 61067 / // Label 1614: @61067
23111	/ 61067 / GIM_Reject,
23112	/ 61068 / // Label 48: @61068
23113	/ 61068 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1642/ GIMT_Encode4(`61577`),
23114	/ 61079 / /GILLT_s32//Label 1638/ GIMT_Encode4(`61111`),
23115	/ 61083 / /GILLT_s64//Label 1639/ GIMT_Encode4(`61190`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
23116	/ 61103 / /GILLT_v4s32//Label 1640/ GIMT_Encode4(`61323`),
23117	/ 61107 / /GILLT_v2s64//Label 1641/ GIMT_Encode4(`61450`),
23118	/ 61111 / // Label 1638: @61111
23119	/ 61111 / GIM_Try, /On fail goto//Label 1643/ GIMT_Encode4(`61189`),
23120	/ 61116 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23121	/ 61119 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
23122	/ 61122 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23123	/ 61126 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23124	/ 61130 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23125	/ 61134 / GIM_Try_CheckFeatures, /On fail goto//Label 1644/ GIMT_Encode4(`61152`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 167 //
23126	/ 61141 / // (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FMUL_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
23127	/ 61141 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_S),
23128	/ 61146 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23129	/ 61150 / GIR_RootConstrainSelectedInstOperands,
23130	/ 61151 / // GIR_Coverage, 167,
23131	/ 61151 / GIR_Done,
23132	/ 61152 / // Label 1644: @61152
23133	/ 61152 / GIM_Try_CheckFeatures, /On fail goto//Label 1645/ GIMT_Encode4(`61170`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1153 //
23134	/ 61159 / // (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FMUL_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
23135	/ 61159 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_S_MM),
23136	/ 61164 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23137	/ 61168 / GIR_RootConstrainSelectedInstOperands,
23138	/ 61169 / // GIR_Coverage, 1153,
23139	/ 61169 / GIR_Done,
23140	/ 61170 / // Label 1645: @61170
23141	/ 61170 / GIM_Try_CheckFeatures, /On fail goto//Label 1646/ GIMT_Encode4(`61188`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1211 //
23142	/ 61177 / // (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FMUL_S_MMR6:{ :[f32] } FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs)
23143	/ 61177 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FMUL_S_MMR6),
23144	/ 61180 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
23145	/ 61182 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
23146	/ 61184 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
23147	/ 61186 / GIR_RootConstrainSelectedInstOperands,
23148	/ 61187 / // GIR_Coverage, 1211,
23149	/ 61187 / GIR_EraseRootFromParent_Done,
23150	/ 61188 / // Label 1646: @61188
23151	/ 61188 / GIM_Reject,
23152	/ 61189 / // Label 1643: @61189
23153	/ 61189 / GIM_Reject,
23154	/ 61190 / // Label 1639: @61190
23155	/ 61190 / GIM_Try, /On fail goto//Label 1647/ GIMT_Encode4(`61322`),
23156	/ 61195 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
23157	/ 61198 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
23158	/ 61201 / GIM_Try_CheckFeatures, /On fail goto//Label 1648/ GIMT_Encode4(`61231`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 169 //
23159	/ 61208 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23160	/ 61212 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23161	/ 61216 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23162	/ 61220 / // (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FMUL_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
23163	/ 61220 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D32),
23164	/ 61225 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23165	/ 61229 / GIR_RootConstrainSelectedInstOperands,
23166	/ 61230 / // GIR_Coverage, 169,
23167	/ 61230 / GIR_Done,
23168	/ 61231 / // Label 1648: @61231
23169	/ 61231 / GIM_Try_CheckFeatures, /On fail goto//Label 1649/ GIMT_Encode4(`61261`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 171 //
23170	/ 61238 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23171	/ 61242 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23172	/ 61246 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23173	/ 61250 / // (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FMUL_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23174	/ 61250 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D64),
23175	/ 61255 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23176	/ 61259 / GIR_RootConstrainSelectedInstOperands,
23177	/ 61260 / // GIR_Coverage, 171,
23178	/ 61260 / GIR_Done,
23179	/ 61261 / // Label 1649: @61261
23180	/ 61261 / GIM_Try_CheckFeatures, /On fail goto//Label 1650/ GIMT_Encode4(`61291`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1159 //
23181	/ 61268 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23182	/ 61272 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23183	/ 61276 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23184	/ 61280 / // (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FMUL_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
23185	/ 61280 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D32_MM),
23186	/ 61285 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23187	/ 61289 / GIR_RootConstrainSelectedInstOperands,
23188	/ 61290 / // GIR_Coverage, 1159,
23189	/ 61290 / GIR_Done,
23190	/ 61291 / // Label 1650: @61291
23191	/ 61291 / GIM_Try_CheckFeatures, /On fail goto//Label 1651/ GIMT_Encode4(`61321`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1160 //
23192	/ 61298 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23193	/ 61302 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23194	/ 61306 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23195	/ 61310 / // (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FMUL_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23196	/ 61310 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D64_MM),
23197	/ 61315 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23198	/ 61319 / GIR_RootConstrainSelectedInstOperands,
23199	/ 61320 / // GIR_Coverage, 1160,
23200	/ 61320 / GIR_Done,
23201	/ 61321 / // Label 1651: @61321
23202	/ 61321 / GIM_Reject,
23203	/ 61322 / // Label 1647: @61322
23204	/ 61322 / GIM_Reject,
23205	/ 61323 / // Label 1640: @61323
23206	/ 61323 / GIM_Try, /On fail goto//Label 1652/ GIMT_Encode4(`61449`),
23207	/ 61328 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23208	/ 61331 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
23209	/ 61334 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23210	/ 61338 / GIM_Try_CheckFeatures, /On fail goto//Label 1653/ GIMT_Encode4(`61381`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2534 //
23211	/ 61345 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
23212	/ 61349 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FEXP2),
23213	/ 61353 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
23214	/ 61357 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23215	/ 61362 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23216	/ 61366 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23217	/* 61368 / // (fmul:{ :[v4f32] } (fexp2:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wt), MSA128WOpnd:{ :[v4f32] }:$ws) => (FEXP2_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23218	/ 61368 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXP2_W),
23219	/ 61371 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23220	/ 61373 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
23221	/ 61375 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
23222	/ 61379 / GIR_RootConstrainSelectedInstOperands,
23223	/ 61380 / // GIR_Coverage, 2534,
23224	/ 61380 / GIR_EraseRootFromParent_Done,
23225	/ 61381 / // Label 1653: @61381
23226	/ 61381 / GIM_Try, /On fail goto//Label 1654/ GIMT_Encode4(`61448`),
23227	/ 61386 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23228	/ 61390 / GIM_Try_CheckFeatures, /On fail goto//Label 1655/ GIMT_Encode4(`61429`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 727 //
23229	/ 61397 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
23230	/ 61401 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FEXP2),
23231	/ 61405 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v4s32,
23232	/ 61409 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23233	/ 61414 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23234	/* 61416 / // (fmul:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, (fexp2:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wt)) => (FEXP2_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23235	/ 61416 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXP2_W),
23236	/ 61419 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23237	/ 61421 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
23238	/ 61423 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
23239	/ 61427 / GIR_RootConstrainSelectedInstOperands,
23240	/ 61428 / // GIR_Coverage, 727,
23241	/ 61428 / GIR_EraseRootFromParent_Done,
23242	/ 61429 / // Label 1655: @61429
23243	/ 61429 / GIM_Try_CheckFeatures, /On fail goto//Label 1656/ GIMT_Encode4(`61447`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 763 //
23244	/ 61436 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23245	/ 61440 / // (fmul:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMUL_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23246	/ 61440 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_W),
23247	/ 61445 / GIR_RootConstrainSelectedInstOperands,
23248	/ 61446 / // GIR_Coverage, 763,
23249	/ 61446 / GIR_Done,
23250	/ 61447 / // Label 1656: @61447
23251	/ 61447 / GIM_Reject,
23252	/ 61448 / // Label 1654: @61448
23253	/ 61448 / GIM_Reject,
23254	/ 61449 / // Label 1652: @61449
23255	/ 61449 / GIM_Reject,
23256	/ 61450 / // Label 1641: @61450
23257	/ 61450 / GIM_Try, /On fail goto//Label 1657/ GIMT_Encode4(`61576`),
23258	/ 61455 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23259	/ 61458 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
23260	/ 61461 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23261	/ 61465 / GIM_Try_CheckFeatures, /On fail goto//Label 1658/ GIMT_Encode4(`61508`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2535 //
23262	/ 61472 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
23263	/ 61476 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FEXP2),
23264	/ 61480 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
23265	/ 61484 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23266	/ 61489 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23267	/ 61493 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23268	/* 61495 / // (fmul:{ :[v2f64] } (fexp2:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wt), MSA128DOpnd:{ :[v2f64] }:$ws) => (FEXP2_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23269	/ 61495 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXP2_D),
23270	/ 61498 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23271	/ 61500 / GIR_RootToRootCopy, /OpIdx/`2`, // ws
23272	/ 61502 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
23273	/ 61506 / GIR_RootConstrainSelectedInstOperands,
23274	/ 61507 / // GIR_Coverage, 2535,
23275	/ 61507 / GIR_EraseRootFromParent_Done,
23276	/ 61508 / // Label 1658: @61508
23277	/ 61508 / GIM_Try, /On fail goto//Label 1659/ GIMT_Encode4(`61575`),
23278	/ 61513 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23279	/ 61517 / GIM_Try_CheckFeatures, /On fail goto//Label 1660/ GIMT_Encode4(`61556`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 728 //
23280	/ 61524 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
23281	/ 61528 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FEXP2),
23282	/ 61532 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_v2s64,
23283	/ 61536 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23284	/ 61541 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
23285	/* 61543 / // (fmul:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, (fexp2:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wt)) => (FEXP2_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23286	/ 61543 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FEXP2_D),
23287	/ 61546 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
23288	/ 61548 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
23289	/ 61550 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // wt
23290	/ 61554 / GIR_RootConstrainSelectedInstOperands,
23291	/ 61555 / // GIR_Coverage, 728,
23292	/ 61555 / GIR_EraseRootFromParent_Done,
23293	/ 61556 / // Label 1660: @61556
23294	/ 61556 / GIM_Try_CheckFeatures, /On fail goto//Label 1661/ GIMT_Encode4(`61574`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 764 //
23295	/ 61563 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23296	/ 61567 / // (fmul:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMUL_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23297	/ 61567 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D),
23298	/ 61572 / GIR_RootConstrainSelectedInstOperands,
23299	/ 61573 / // GIR_Coverage, 764,
23300	/ 61573 / GIR_Done,
23301	/ 61574 / // Label 1661: @61574
23302	/ 61574 / GIM_Reject,
23303	/ 61575 / // Label 1659: @61575
23304	/ 61575 / GIM_Reject,
23305	/ 61576 / // Label 1657: @61576
23306	/ 61576 / GIM_Reject,
23307	/ 61577 / // Label 1642: @61577
23308	/ 61577 / GIM_Reject,
23309	/ 61578 / // Label 49: @61578
23310	/ 61578 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1664/ GIMT_Encode4(`61677`),
23311	/ 61589 / /GILLT_v4s32//Label 1662/ GIMT_Encode4(`61597`),
23312	/ 61593 / /GILLT_v2s64//Label 1663/ GIMT_Encode4(`61637`),
23313	/ 61597 / // Label 1662: @61597
23314	/ 61597 / GIM_Try_CheckFeatures, /On fail goto//Label 1665/ GIMT_Encode4(`61636`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 751 //
23315	/ 61604 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23316	/ 61607 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
23317	/ 61610 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v4s32,
23318	/ 61613 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23319	/ 61617 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23320	/ 61621 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23321	/ 61625 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23322	/* 61629 / // (fma:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FMADD_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23323	/ 61629 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMADD_W),
23324	/ 61634 / GIR_RootConstrainSelectedInstOperands,
23325	/ 61635 / // GIR_Coverage, 751,
23326	/ 61635 / GIR_Done,
23327	/ 61636 / // Label 1665: @61636
23328	/ 61636 / GIM_Reject,
23329	/ 61637 / // Label 1663: @61637
23330	/ 61637 / GIM_Try_CheckFeatures, /On fail goto//Label 1666/ GIMT_Encode4(`61676`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 752 //
23331	/ 61644 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23332	/ 61647 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
23333	/ 61650 / GIM_RootCheckType, /Op/`3`, /Type/GILLT_v2s64,
23334	/ 61653 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23335	/ 61657 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23336	/ 61661 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23337	/ 61665 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23338	/* 61669 / // (fma:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FMADD_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23339	/ 61669 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMADD_D),
23340	/ 61674 / GIR_RootConstrainSelectedInstOperands,
23341	/ 61675 / // GIR_Coverage, 752,
23342	/ 61675 / GIR_Done,
23343	/ 61676 / // Label 1666: @61676
23344	/ 61676 / GIM_Reject,
23345	/ 61677 / // Label 1664: @61677
23346	/ 61677 / GIM_Reject,
23347	/ 61678 / // Label 50: @61678
23348	/ 61678 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1671/ GIMT_Encode4(`61999`),
23349	/ 61689 / /GILLT_s32//Label 1667/ GIMT_Encode4(`61721`),
23350	/ 61693 / /GILLT_s64//Label 1668/ GIMT_Encode4(`61800`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
23351	/ 61713 / /GILLT_v4s32//Label 1669/ GIMT_Encode4(`61933`),
23352	/ 61717 / /GILLT_v2s64//Label 1670/ GIMT_Encode4(`61966`),
23353	/ 61721 / // Label 1667: @61721
23354	/ 61721 / GIM_Try, /On fail goto//Label 1672/ GIMT_Encode4(`61799`),
23355	/ 61726 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23356	/ 61729 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
23357	/ 61732 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23358	/ 61736 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23359	/ 61740 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23360	/ 61744 / GIM_Try_CheckFeatures, /On fail goto//Label 1673/ GIMT_Encode4(`61762`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 161 //
23361	/ 61751 / // (fdiv:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FDIV_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
23362	/ 61751 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_S),
23363	/ 61756 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23364	/ 61760 / GIR_RootConstrainSelectedInstOperands,
23365	/ 61761 / // GIR_Coverage, 161,
23366	/ 61761 / GIR_Done,
23367	/ 61762 / // Label 1673: @61762
23368	/ 61762 / GIM_Try_CheckFeatures, /On fail goto//Label 1674/ GIMT_Encode4(`61780`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1152 //
23369	/ 61769 / // (fdiv:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FDIV_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
23370	/ 61769 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_S_MM),
23371	/ 61774 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23372	/ 61778 / GIR_RootConstrainSelectedInstOperands,
23373	/ 61779 / // GIR_Coverage, 1152,
23374	/ 61779 / GIR_Done,
23375	/ 61780 / // Label 1674: @61780
23376	/ 61780 / GIM_Try_CheckFeatures, /On fail goto//Label 1675/ GIMT_Encode4(`61798`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1212 //
23377	/ 61787 / // (fdiv:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FDIV_S_MMR6:{ :[f32] } FGR32Opnd:{ :[f32] }:$ft, FGR32Opnd:{ :[f32] }:$fs)
23378	/ 61787 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::FDIV_S_MMR6),
23379	/ 61790 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
23380	/ 61792 / GIR_RootToRootCopy, /OpIdx/`2`, // ft
23381	/ 61794 / GIR_RootToRootCopy, /OpIdx/`1`, // fs
23382	/ 61796 / GIR_RootConstrainSelectedInstOperands,
23383	/ 61797 / // GIR_Coverage, 1212,
23384	/ 61797 / GIR_EraseRootFromParent_Done,
23385	/ 61798 / // Label 1675: @61798
23386	/ 61798 / GIM_Reject,
23387	/ 61799 / // Label 1672: @61799
23388	/ 61799 / GIM_Reject,
23389	/ 61800 / // Label 1668: @61800
23390	/ 61800 / GIM_Try, /On fail goto//Label 1676/ GIMT_Encode4(`61932`),
23391	/ 61805 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
23392	/ 61808 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
23393	/ 61811 / GIM_Try_CheckFeatures, /On fail goto//Label 1677/ GIMT_Encode4(`61841`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 163 //
23394	/ 61818 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23395	/ 61822 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23396	/ 61826 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23397	/ 61830 / // (fdiv:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FDIV_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
23398	/ 61830 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D32),
23399	/ 61835 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23400	/ 61839 / GIR_RootConstrainSelectedInstOperands,
23401	/ 61840 / // GIR_Coverage, 163,
23402	/ 61840 / GIR_Done,
23403	/ 61841 / // Label 1677: @61841
23404	/ 61841 / GIM_Try_CheckFeatures, /On fail goto//Label 1678/ GIMT_Encode4(`61871`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 165 //
23405	/ 61848 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23406	/ 61852 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23407	/ 61856 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23408	/ 61860 / // (fdiv:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FDIV_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23409	/ 61860 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D64),
23410	/ 61865 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23411	/ 61869 / GIR_RootConstrainSelectedInstOperands,
23412	/ 61870 / // GIR_Coverage, 165,
23413	/ 61870 / GIR_Done,
23414	/ 61871 / // Label 1678: @61871
23415	/ 61871 / GIM_Try_CheckFeatures, /On fail goto//Label 1679/ GIMT_Encode4(`61901`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1157 //
23416	/ 61878 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23417	/ 61882 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23418	/ 61886 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23419	/ 61890 / // (fdiv:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FDIV_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
23420	/ 61890 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D32_MM),
23421	/ 61895 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23422	/ 61899 / GIR_RootConstrainSelectedInstOperands,
23423	/ 61900 / // GIR_Coverage, 1157,
23424	/ 61900 / GIR_Done,
23425	/ 61901 / // Label 1679: @61901
23426	/ 61901 / GIM_Try_CheckFeatures, /On fail goto//Label 1680/ GIMT_Encode4(`61931`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1158 //
23427	/ 61908 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23428	/ 61912 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23429	/ 61916 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23430	/ 61920 / // (fdiv:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FDIV_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
23431	/ 61920 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D64_MM),
23432	/ 61925 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23433	/ 61929 / GIR_RootConstrainSelectedInstOperands,
23434	/ 61930 / // GIR_Coverage, 1158,
23435	/ 61930 / GIR_Done,
23436	/ 61931 / // Label 1680: @61931
23437	/ 61931 / GIM_Reject,
23438	/ 61932 / // Label 1676: @61932
23439	/ 61932 / GIM_Reject,
23440	/ 61933 / // Label 1669: @61933
23441	/ 61933 / GIM_Try_CheckFeatures, /On fail goto//Label 1681/ GIMT_Encode4(`61965`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 723 //
23442	/ 61940 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23443	/ 61943 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
23444	/ 61946 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23445	/ 61950 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23446	/ 61954 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23447	/ 61958 / // (fdiv:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt) => (FDIV_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ :[v4f32] }:$wt)
23448	/ 61958 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_W),
23449	/ 61963 / GIR_RootConstrainSelectedInstOperands,
23450	/ 61964 / // GIR_Coverage, 723,
23451	/ 61964 / GIR_Done,
23452	/ 61965 / // Label 1681: @61965
23453	/ 61965 / GIM_Reject,
23454	/ 61966 / // Label 1670: @61966
23455	/ 61966 / GIM_Try_CheckFeatures, /On fail goto//Label 1682/ GIMT_Encode4(`61998`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 724 //
23456	/ 61973 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23457	/ 61976 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
23458	/ 61979 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23459	/ 61983 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23460	/ 61987 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23461	/ 61991 / // (fdiv:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt) => (FDIV_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws, MSA128DOpnd:{ :[v2f64] }:$wt)
23462	/ 61991 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D),
23463	/ 61996 / GIR_RootConstrainSelectedInstOperands,
23464	/ 61997 / // GIR_Coverage, 724,
23465	/ 61997 / GIR_Done,
23466	/ 61998 / // Label 1682: @61998
23467	/ 61998 / GIM_Reject,
23468	/ 61999 / // Label 1671: @61999
23469	/ 61999 / GIM_Reject,
23470	/ 62000 / // Label 51: @62000
23471	/ 62000 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1685/ GIMT_Encode4(`62071`),
23472	/ 62011 / /GILLT_v4s32//Label 1683/ GIMT_Encode4(`62019`),
23473	/ 62015 / /GILLT_v2s64//Label 1684/ GIMT_Encode4(`62045`),
23474	/ 62019 / // Label 1683: @62019
23475	/ 62019 / GIM_Try_CheckFeatures, /On fail goto//Label 1686/ GIMT_Encode4(`62044`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 729 //
23476	/ 62026 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23477	/ 62029 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23478	/ 62033 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23479	/ 62037 / // (fexp2:{ :[v4f32] } MSA128W:{ :[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ :[v4f32] } MSA128W:{ :[v4f32] }:$ws)
23480	/ 62037 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
23481	/ 62042 / GIR_RootConstrainSelectedInstOperands,
23482	/ 62043 / // GIR_Coverage, 729,
23483	/ 62043 / GIR_Done,
23484	/ 62044 / // Label 1686: @62044
23485	/ 62044 / GIM_Reject,
23486	/ 62045 / // Label 1684: @62045
23487	/ 62045 / GIM_Try_CheckFeatures, /On fail goto//Label 1687/ GIMT_Encode4(`62070`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 730 //
23488	/ 62052 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23489	/ 62055 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23490	/ 62059 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23491	/ 62063 / // (fexp2:{ :[v2f64] } MSA128D:{ :[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ :[v2f64] } MSA128D:{ :[v2f64] }:$ws)
23492	/ 62063 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
23493	/ 62068 / GIR_RootConstrainSelectedInstOperands,
23494	/ 62069 / // GIR_Coverage, 730,
23495	/ 62069 / GIR_Done,
23496	/ 62070 / // Label 1687: @62070
23497	/ 62070 / GIM_Reject,
23498	/ 62071 / // Label 1685: @62071
23499	/ 62071 / GIM_Reject,
23500	/ 62072 / // Label 52: @62072
23501	/ 62072 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1690/ GIMT_Encode4(`62143`),
23502	/ 62083 / /GILLT_v4s32//Label 1688/ GIMT_Encode4(`62091`),
23503	/ 62087 / /GILLT_v2s64//Label 1689/ GIMT_Encode4(`62117`),
23504	/ 62091 / // Label 1688: @62091
23505	/ 62091 / GIM_Try_CheckFeatures, /On fail goto//Label 1691/ GIMT_Encode4(`62116`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 749 //
23506	/ 62098 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23507	/ 62101 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23508	/ 62105 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23509	/ 62109 / // (flog2:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FLOG2_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)
23510	/ 62109 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FLOG2_W),
23511	/ 62114 / GIR_RootConstrainSelectedInstOperands,
23512	/ 62115 / // GIR_Coverage, 749,
23513	/ 62115 / GIR_Done,
23514	/ 62116 / // Label 1691: @62116
23515	/ 62116 / GIM_Reject,
23516	/ 62117 / // Label 1689: @62117
23517	/ 62117 / GIM_Try_CheckFeatures, /On fail goto//Label 1692/ GIMT_Encode4(`62142`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 750 //
23518	/ 62124 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23519	/ 62127 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23520	/ 62131 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23521	/ 62135 / // (flog2:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FLOG2_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)
23522	/ 62135 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FLOG2_D),
23523	/ 62140 / GIR_RootConstrainSelectedInstOperands,
23524	/ 62141 / // GIR_Coverage, 750,
23525	/ 62141 / GIR_Done,
23526	/ 62142 / // Label 1692: @62142
23527	/ 62142 / GIM_Reject,
23528	/ 62143 / // Label 1690: @62143
23529	/ 62143 / GIM_Reject,
23530	/ 62144 / // Label 53: @62144
23531	/ 62144 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1695/ GIMT_Encode4(`62321`),
23532	/ 62155 / /GILLT_s32//Label 1693/ GIMT_Encode4(`62163`),
23533	/ 62159 / /GILLT_s64//Label 1694/ GIMT_Encode4(`62223`),
23534	/ 62163 / // Label 1693: @62163
23535	/ 62163 / GIM_Try, /On fail goto//Label 1696/ GIMT_Encode4(`62222`),
23536	/ 62168 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23537	/ 62171 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23538	/ 62175 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23539	/ 62179 / GIM_Try_CheckFeatures, /On fail goto//Label 1697/ GIMT_Encode4(`62193`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat), // Rule ID 129 //
23540	/ 62186 / // (fneg:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FNEG_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
23541	/ 62186 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_S),
23542	/ 62191 / GIR_RootConstrainSelectedInstOperands,
23543	/ 62192 / // GIR_Coverage, 129,
23544	/ 62192 / GIR_Done,
23545	/ 62193 / // Label 1697: @62193
23546	/ 62193 / GIM_Try_CheckFeatures, /On fail goto//Label 1698/ GIMT_Encode4(`62207`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1174 //
23547	/ 62200 / // (fneg:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FNEG_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
23548	/ 62200 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_S_MM),
23549	/ 62205 / GIR_RootConstrainSelectedInstOperands,
23550	/ 62206 / // GIR_Coverage, 1174,
23551	/ 62206 / GIR_Done,
23552	/ 62207 / // Label 1698: @62207
23553	/ 62207 / GIM_Try_CheckFeatures, /On fail goto//Label 1699/ GIMT_Encode4(`62221`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1213 //
23554	/ 62214 / // (fneg:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FNEG_S_MMR6:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
23555	/ 62214 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_S_MMR6),
23556	/ 62219 / GIR_RootConstrainSelectedInstOperands,
23557	/ 62220 / // GIR_Coverage, 1213,
23558	/ 62220 / GIR_Done,
23559	/ 62221 / // Label 1699: @62221
23560	/ 62221 / GIM_Reject,
23561	/ 62222 / // Label 1696: @62222
23562	/ 62222 / GIM_Reject,
23563	/ 62223 / // Label 1694: @62223
23564	/ 62223 / GIM_Try, /On fail goto//Label 1700/ GIMT_Encode4(`62320`),
23565	/ 62228 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
23566	/ 62231 / GIM_Try_CheckFeatures, /On fail goto//Label 1701/ GIMT_Encode4(`62253`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 130 //
23567	/ 62238 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23568	/ 62242 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23569	/ 62246 / // (fneg:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FNEG_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
23570	/ 62246 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_D32),
23571	/ 62251 / GIR_RootConstrainSelectedInstOperands,
23572	/ 62252 / // GIR_Coverage, 130,
23573	/ 62252 / GIR_Done,
23574	/ 62253 / // Label 1701: @62253
23575	/ 62253 / GIM_Try_CheckFeatures, /On fail goto//Label 1702/ GIMT_Encode4(`62275`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 131 //
23576	/ 62260 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23577	/ 62264 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23578	/ 62268 / // (fneg:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FNEG_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
23579	/ 62268 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_D64),
23580	/ 62273 / GIR_RootConstrainSelectedInstOperands,
23581	/ 62274 / // GIR_Coverage, 131,
23582	/ 62274 / GIR_Done,
23583	/ 62275 / // Label 1702: @62275
23584	/ 62275 / GIM_Try_CheckFeatures, /On fail goto//Label 1703/ GIMT_Encode4(`62297`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1175 //
23585	/ 62282 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23586	/ 62286 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23587	/ 62290 / // (fneg:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FNEG_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
23588	/ 62290 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_D32_MM),
23589	/ 62295 / GIR_RootConstrainSelectedInstOperands,
23590	/ 62296 / // GIR_Coverage, 1175,
23591	/ 62296 / GIR_Done,
23592	/ 62297 / // Label 1703: @62297
23593	/ 62297 / GIM_Try_CheckFeatures, /On fail goto//Label 1704/ GIMT_Encode4(`62319`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1176 //
23594	/ 62304 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23595	/ 62308 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23596	/ 62312 / // (fneg:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FNEG_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
23597	/ 62312 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FNEG_D64_MM),
23598	/ 62317 / GIR_RootConstrainSelectedInstOperands,
23599	/ 62318 / // GIR_Coverage, 1176,
23600	/ 62318 / GIR_Done,
23601	/ 62319 / // Label 1704: @62319
23602	/ 62319 / GIM_Reject,
23603	/ 62320 / // Label 1700: @62320
23604	/ 62320 / GIM_Reject,
23605	/ 62321 / // Label 1695: @62321
23606	/ 62321 / GIM_Reject,
23607	/ 62322 / // Label 54: @62322
23608	/ 62322 / GIM_Try, /On fail goto//Label 1705/ GIMT_Encode4(`62436`),
23609	/ 62327 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s64,
23610	/ 62330 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23611	/ 62333 / GIM_Try_CheckFeatures, /On fail goto//Label 1706/ GIMT_Encode4(`62359`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1528 //
23612	/ 62340 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23613	/ 62344 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23614	/ 62348 / // (fpextend:{ :[f64] } FGR32Opnd:{ :[f32] }:$src) => (CVT_D32_S:{ :[f64] } FGR32Opnd:{ :[f32] }:$src)
23615	/ 62348 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_D32_S),
23616	/ 62353 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23617	/ 62357 / GIR_RootConstrainSelectedInstOperands,
23618	/ 62358 / // GIR_Coverage, 1528,
23619	/ 62358 / GIR_Done,
23620	/ 62359 / // Label 1706: @62359
23621	/ 62359 / GIM_Try, /On fail goto//Label 1707/ GIMT_Encode4(`62409`),
23622	/ 62364 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23623	/ 62368 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23624	/ 62372 / GIM_Try_CheckFeatures, /On fail goto//Label 1708/ GIMT_Encode4(`62390`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1543 //
23625	/ 62379 / // (fpextend:{ :[f64] } FGR32Opnd:{ :[f32] }:$src) => (CVT_D64_S:{ :[f64] } FGR32Opnd:{ :[f32] }:$src)
23626	/ 62379 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_D64_S),
23627	/ 62384 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23628	/ 62388 / GIR_RootConstrainSelectedInstOperands,
23629	/ 62389 / // GIR_Coverage, 1543,
23630	/ 62389 / GIR_Done,
23631	/ 62390 / // Label 1708: @62390
23632	/ 62390 / GIM_Try_CheckFeatures, /On fail goto//Label 1709/ GIMT_Encode4(`62408`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2400 //
23633	/ 62397 / // (fpextend:{ :[f64] } FGR32Opnd:{ :[f32] }:$src) => (CVT_D64_S_MM:{ :[f64] } FGR32Opnd:{ :[f32] }:$src)
23634	/ 62397 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_D64_S_MM),
23635	/ 62402 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23636	/ 62406 / GIR_RootConstrainSelectedInstOperands,
23637	/ 62407 / // GIR_Coverage, 2400,
23638	/ 62407 / GIR_Done,
23639	/ 62408 / // Label 1709: @62408
23640	/ 62408 / GIM_Reject,
23641	/ 62409 / // Label 1707: @62409
23642	/ 62409 / GIM_Try_CheckFeatures, /On fail goto//Label 1710/ GIMT_Encode4(`62435`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2402 //
23643	/ 62416 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23644	/ 62420 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23645	/ 62424 / // (fpextend:{ :[f64] } FGR32Opnd:{ :[f32] }:$src) => (CVT_D32_S_MM:{ :[f64] } FGR32Opnd:{ :[f32] }:$src)
23646	/ 62424 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_D32_S_MM),
23647	/ 62429 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23648	/ 62433 / GIR_RootConstrainSelectedInstOperands,
23649	/ 62434 / // GIR_Coverage, 2402,
23650	/ 62434 / GIR_Done,
23651	/ 62435 / // Label 1710: @62435
23652	/ 62435 / GIM_Reject,
23653	/ 62436 / // Label 1705: @62436
23654	/ 62436 / GIM_Reject,
23655	/ 62437 / // Label 55: @62437
23656	/ 62437 / GIM_Try, /On fail goto//Label 1711/ GIMT_Encode4(`62543`),
23657	/ 62442 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
23658	/ 62445 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
23659	/ 62448 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23660	/ 62452 / GIM_Try_CheckFeatures, /On fail goto//Label 1712/ GIMT_Encode4(`62474`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1526 //
23661	/ 62459 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23662	/ 62463 / // (fpround:{ :[f32] } AFGR64Opnd:{ :[f64] }:$src) => (CVT_S_D32:{ :[f32] } AFGR64Opnd:{ :[f64] }:$src)
23663	/ 62463 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_S_D32),
23664	/ 62468 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23665	/ 62472 / GIR_RootConstrainSelectedInstOperands,
23666	/ 62473 / // GIR_Coverage, 1526,
23667	/ 62473 / GIR_Done,
23668	/ 62474 / // Label 1712: @62474
23669	/ 62474 / GIM_Try, /On fail goto//Label 1713/ GIMT_Encode4(`62520`),
23670	/ 62479 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23671	/ 62483 / GIM_Try_CheckFeatures, /On fail goto//Label 1714/ GIMT_Encode4(`62501`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1541 //
23672	/ 62490 / // (fpround:{ :[f32] } FGR64Opnd:{ :[f64] }:$src) => (CVT_S_D64:{ :[f32] } FGR64Opnd:{ :[f64] }:$src)
23673	/ 62490 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_S_D64),
23674	/ 62495 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23675	/ 62499 / GIR_RootConstrainSelectedInstOperands,
23676	/ 62500 / // GIR_Coverage, 1541,
23677	/ 62500 / GIR_Done,
23678	/ 62501 / // Label 1714: @62501
23679	/ 62501 / GIM_Try_CheckFeatures, /On fail goto//Label 1715/ GIMT_Encode4(`62519`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2399 //
23680	/ 62508 / // (fpround:{ :[f32] } FGR64Opnd:{ :[f64] }:$src) => (CVT_S_D64_MM:{ :[f32] } FGR64Opnd:{ :[f64] }:$src)
23681	/ 62508 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_S_D64_MM),
23682	/ 62513 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23683	/ 62517 / GIR_RootConstrainSelectedInstOperands,
23684	/ 62518 / // GIR_Coverage, 2399,
23685	/ 62518 / GIR_Done,
23686	/ 62519 / // Label 1715: @62519
23687	/ 62519 / GIM_Reject,
23688	/ 62520 / // Label 1713: @62520
23689	/ 62520 / GIM_Try_CheckFeatures, /On fail goto//Label 1716/ GIMT_Encode4(`62542`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2401 //
23690	/ 62527 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23691	/ 62531 / // (fpround:{ :[f32] } AFGR64Opnd:{ :[f64] }:$src) => (CVT_S_D32_MM:{ :[f32] } AFGR64Opnd:{ :[f64] }:$src)
23692	/ 62531 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CVT_S_D32_MM),
23693	/ 62536 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
23694	/ 62540 / GIR_RootConstrainSelectedInstOperands,
23695	/ 62541 / // GIR_Coverage, 2401,
23696	/ 62541 / GIR_Done,
23697	/ 62542 / // Label 1716: @62542
23698	/ 62542 / GIM_Reject,
23699	/ 62543 / // Label 1711: @62543
23700	/ 62543 / GIM_Reject,
23701	/ 62544 / // Label 56: @62544
23702	/ 62544 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1719/ GIMT_Encode4(`62615`),
23703	/ 62555 / /GILLT_v4s32//Label 1717/ GIMT_Encode4(`62563`),
23704	/ 62559 / /GILLT_v2s64//Label 1718/ GIMT_Encode4(`62589`),
23705	/ 62563 / // Label 1717: @62563
23706	/ 62563 / GIM_Try_CheckFeatures, /On fail goto//Label 1720/ GIMT_Encode4(`62588`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 803 //
23707	/ 62570 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23708	/ 62573 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23709	/ 62577 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23710	/ 62581 / // (fp_to_sint:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FTRUNC_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws)
23711	/ 62581 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FTRUNC_S_W),
23712	/ 62586 / GIR_RootConstrainSelectedInstOperands,
23713	/ 62587 / // GIR_Coverage, 803,
23714	/ 62587 / GIR_Done,
23715	/ 62588 / // Label 1720: @62588
23716	/ 62588 / GIM_Reject,
23717	/ 62589 / // Label 1718: @62589
23718	/ 62589 / GIM_Try_CheckFeatures, /On fail goto//Label 1721/ GIMT_Encode4(`62614`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 804 //
23719	/ 62596 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23720	/ 62599 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23721	/ 62603 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23722	/ 62607 / // (fp_to_sint:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FTRUNC_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws)
23723	/ 62607 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FTRUNC_S_D),
23724	/ 62612 / GIR_RootConstrainSelectedInstOperands,
23725	/ 62613 / // GIR_Coverage, 804,
23726	/ 62613 / GIR_Done,
23727	/ 62614 / // Label 1721: @62614
23728	/ 62614 / GIM_Reject,
23729	/ 62615 / // Label 1719: @62615
23730	/ 62615 / GIM_Reject,
23731	/ 62616 / // Label 57: @62616
23732	/ 62616 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1724/ GIMT_Encode4(`62687`),
23733	/ 62627 / /GILLT_v4s32//Label 1722/ GIMT_Encode4(`62635`),
23734	/ 62631 / /GILLT_v2s64//Label 1723/ GIMT_Encode4(`62661`),
23735	/ 62635 / // Label 1722: @62635
23736	/ 62635 / GIM_Try_CheckFeatures, /On fail goto//Label 1725/ GIMT_Encode4(`62660`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 805 //
23737	/ 62642 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23738	/ 62645 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23739	/ 62649 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23740	/ 62653 / // (fp_to_uint:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FTRUNC_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4f32] }:$ws)
23741	/ 62653 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FTRUNC_U_W),
23742	/ 62658 / GIR_RootConstrainSelectedInstOperands,
23743	/ 62659 / // GIR_Coverage, 805,
23744	/ 62659 / GIR_Done,
23745	/ 62660 / // Label 1725: @62660
23746	/ 62660 / GIM_Reject,
23747	/ 62661 / // Label 1723: @62661
23748	/ 62661 / GIM_Try_CheckFeatures, /On fail goto//Label 1726/ GIMT_Encode4(`62686`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 806 //
23749	/ 62668 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23750	/ 62671 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23751	/ 62675 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23752	/ 62679 / // (fp_to_uint:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FTRUNC_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2f64] }:$ws)
23753	/ 62679 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FTRUNC_U_D),
23754	/ 62684 / GIR_RootConstrainSelectedInstOperands,
23755	/ 62685 / // GIR_Coverage, 806,
23756	/ 62685 / GIR_Done,
23757	/ 62686 / // Label 1726: @62686
23758	/ 62686 / GIM_Reject,
23759	/ 62687 / // Label 1724: @62687
23760	/ 62687 / GIM_Reject,
23761	/ 62688 / // Label 58: @62688
23762	/ 62688 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1731/ GIMT_Encode4(`62969`),
23763	/ 62699 / /GILLT_s32//Label 1727/ GIMT_Encode4(`62731`),
23764	/ 62703 / /GILLT_s64//Label 1728/ GIMT_Encode4(`62829`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
23765	/ 62723 / /GILLT_v4s32//Label 1729/ GIMT_Encode4(`62917`),
23766	/ 62727 / /GILLT_v2s64//Label 1730/ GIMT_Encode4(`62943`),
23767	/ 62731 / // Label 1727: @62731
23768	/ 62731 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1734/ GIMT_Encode4(`62828`),
23769	/ 62742 / /GILLT_s32//Label 1732/ GIMT_Encode4(`62750`),
23770	/ 62746 / /GILLT_s64//Label 1733/ GIMT_Encode4(`62771`),
23771	/ 62750 / // Label 1732: @62750
23772	/ 62750 / GIM_Try, /On fail goto//Label 1735/ GIMT_Encode4(`62770`), // Rule ID 1516 //
23773	/ 62755 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23774	/ 62759 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
23775	/ 62763 / // (sint_to_fp:{ :[f32] } GPR32Opnd:{ :[i32] }:$src) => (PseudoCVT_S_W:{ :[f32] } GPR32Opnd:{ :[i32] }:$src)
23776	/ 62763 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoCVT_S_W),
23777	/ 62768 / GIR_RootConstrainSelectedInstOperands,
23778	/ 62769 / // GIR_Coverage, 1516,
23779	/ 62769 / GIR_Done,
23780	/ 62770 / // Label 1735: @62770
23781	/ 62770 / GIM_Reject,
23782	/ 62771 / // Label 1733: @62771
23783	/ 62771 / GIM_Try_CheckFeatures, /On fail goto//Label 1736/ GIMT_Encode4(`62827`), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1534 //
23784	/ 62778 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23785	/ 62782 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
23786	/ 62786 / // (sint_to_fp:{ :[f32] } GPR64Opnd:{ :[i64] }:$src) => (EXTRACT_SUBREG:{ :[f32] } (PseudoCVT_S_L:{ :[f64] } GPR64Opnd:{ :[i64] }:$src), sub_lo:{ :[i32] })
23787	/ 62786 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
23788	/ 62789 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::PseudoCVT_S_L),
23789	/ 62793 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23790	/ 62798 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // src
23791	/ 62802 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
23792	/ 62804 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(TargetOpcode::COPY),
23793	/ 62807 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[dst]
23794	/ 62809 / GIR_AddTempSubRegister, /InsnID/`0`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(`0`), GIMT_Encode2(Mips::sub_lo),
23795	/ 62816 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`0`, GIMT_Encode2(Mips::FGR32RegClassID),
23796	/ 62821 / GIR_ConstrainOperandRC, /InsnID/`0`, /Op/`1`, GIMT_Encode2(Mips::FGR64RegClassID),
23797	/ 62826 / // GIR_Coverage, 1534,
23798	/ 62826 / GIR_EraseRootFromParent_Done,
23799	/ 62827 / // Label 1736: @62827
23800	/ 62827 / GIM_Reject,
23801	/ 62828 / // Label 1734: @62828
23802	/ 62828 / GIM_Reject,
23803	/ 62829 / // Label 1728: @62829
23804	/ 62829 / GIM_SwitchType, /MI/`0`, /Op/`1`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1739/ GIMT_Encode4(`62916`),
23805	/ 62840 / /GILLT_s32//Label 1737/ GIMT_Encode4(`62848`),
23806	/ 62844 / /GILLT_s64//Label 1738/ GIMT_Encode4(`62893`),
23807	/ 62848 / // Label 1737: @62848
23808	/ 62848 / GIM_Try_CheckFeatures, /On fail goto//Label 1740/ GIMT_Encode4(`62870`), GIMT_Encode2(GIFBS_IsNotSingleFloat_NotFP64bit), // Rule ID 1523 //
23809	/ 62855 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23810	/ 62859 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
23811	/ 62863 / // (sint_to_fp:{ :[f64] } GPR32Opnd:{ :[i32] }:$src) => (PseudoCVT_D32_W:{ :[f64] } GPR32Opnd:{ :[i32] }:$src)
23812	/ 62863 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoCVT_D32_W),
23813	/ 62868 / GIR_RootConstrainSelectedInstOperands,
23814	/ 62869 / // GIR_Coverage, 1523,
23815	/ 62869 / GIR_Done,
23816	/ 62870 / // Label 1740: @62870
23817	/ 62870 / GIM_Try_CheckFeatures, /On fail goto//Label 1741/ GIMT_Encode4(`62892`), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1532 //
23818	/ 62877 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23819	/ 62881 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
23820	/ 62885 / // (sint_to_fp:{ :[f64] } GPR32Opnd:{ :[i32] }:$src) => (PseudoCVT_D64_W:{ :[f64] } GPR32Opnd:{ :[i32] }:$src)
23821	/ 62885 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoCVT_D64_W),
23822	/ 62890 / GIR_RootConstrainSelectedInstOperands,
23823	/ 62891 / // GIR_Coverage, 1532,
23824	/ 62891 / GIR_Done,
23825	/ 62892 / // Label 1741: @62892
23826	/ 62892 / GIM_Reject,
23827	/ 62893 / // Label 1738: @62893
23828	/ 62893 / GIM_Try_CheckFeatures, /On fail goto//Label 1742/ GIMT_Encode4(`62915`), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1536 //
23829	/ 62900 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23830	/ 62904 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
23831	/ 62908 / // (sint_to_fp:{ :[f64] } GPR64Opnd:{ :[i64] }:$src) => (PseudoCVT_D64_L:{ :[f64] } GPR64Opnd:{ :[i64] }:$src)
23832	/ 62908 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PseudoCVT_D64_L),
23833	/ 62913 / GIR_RootConstrainSelectedInstOperands,
23834	/ 62914 / // GIR_Coverage, 1536,
23835	/ 62914 / GIR_Done,
23836	/ 62915 / // Label 1742: @62915
23837	/ 62915 / GIM_Reject,
23838	/ 62916 / // Label 1739: @62916
23839	/ 62916 / GIM_Reject,
23840	/ 62917 / // Label 1729: @62917
23841	/ 62917 / GIM_Try_CheckFeatures, /On fail goto//Label 1743/ GIMT_Encode4(`62942`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 735 //
23842	/ 62924 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23843	/ 62927 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23844	/ 62931 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23845	/ 62935 / // (sint_to_fp:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$ws) => (FFINT_S_W:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$ws)
23846	/ 62935 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FFINT_S_W),
23847	/ 62940 / GIR_RootConstrainSelectedInstOperands,
23848	/ 62941 / // GIR_Coverage, 735,
23849	/ 62941 / GIR_Done,
23850	/ 62942 / // Label 1743: @62942
23851	/ 62942 / GIM_Reject,
23852	/ 62943 / // Label 1730: @62943
23853	/ 62943 / GIM_Try_CheckFeatures, /On fail goto//Label 1744/ GIMT_Encode4(`62968`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 736 //
23854	/ 62950 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23855	/ 62953 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23856	/ 62957 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23857	/ 62961 / // (sint_to_fp:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$ws) => (FFINT_S_D:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$ws)
23858	/ 62961 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FFINT_S_D),
23859	/ 62966 / GIR_RootConstrainSelectedInstOperands,
23860	/ 62967 / // GIR_Coverage, 736,
23861	/ 62967 / GIR_Done,
23862	/ 62968 / // Label 1744: @62968
23863	/ 62968 / GIM_Reject,
23864	/ 62969 / // Label 1731: @62969
23865	/ 62969 / GIM_Reject,
23866	/ 62970 / // Label 59: @62970
23867	/ 62970 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1747/ GIMT_Encode4(`63041`),
23868	/ 62981 / /GILLT_v4s32//Label 1745/ GIMT_Encode4(`62989`),
23869	/ 62985 / /GILLT_v2s64//Label 1746/ GIMT_Encode4(`63015`),
23870	/ 62989 / // Label 1745: @62989
23871	/ 62989 / GIM_Try_CheckFeatures, /On fail goto//Label 1748/ GIMT_Encode4(`63014`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 737 //
23872	/ 62996 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23873	/ 62999 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23874	/ 63003 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23875	/ 63007 / // (uint_to_fp:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$ws) => (FFINT_U_W:{ :[v4f32] } MSA128WOpnd:{ :[v4i32] }:$ws)
23876	/ 63007 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FFINT_U_W),
23877	/ 63012 / GIR_RootConstrainSelectedInstOperands,
23878	/ 63013 / // GIR_Coverage, 737,
23879	/ 63013 / GIR_Done,
23880	/ 63014 / // Label 1748: @63014
23881	/ 63014 / GIM_Reject,
23882	/ 63015 / // Label 1746: @63015
23883	/ 63015 / GIM_Try_CheckFeatures, /On fail goto//Label 1749/ GIMT_Encode4(`63040`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 738 //
23884	/ 63022 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23885	/ 63025 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23886	/ 63029 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23887	/ 63033 / // (uint_to_fp:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$ws) => (FFINT_U_D:{ :[v2f64] } MSA128DOpnd:{ :[v2i64] }:$ws)
23888	/ 63033 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FFINT_U_D),
23889	/ 63038 / GIR_RootConstrainSelectedInstOperands,
23890	/ 63039 / // GIR_Coverage, 738,
23891	/ 63039 / GIR_Done,
23892	/ 63040 / // Label 1749: @63040
23893	/ 63040 / GIM_Reject,
23894	/ 63041 / // Label 1747: @63041
23895	/ 63041 / GIM_Reject,
23896	/ 63042 / // Label 60: @63042
23897	/ 63042 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1754/ GIMT_Encode4(`63281`),
23898	/ 63053 / /GILLT_s32//Label 1750/ GIMT_Encode4(`63085`),
23899	/ 63057 / /GILLT_s64//Label 1751/ GIMT_Encode4(`63131`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
23900	/ 63077 / /GILLT_v4s32//Label 1752/ GIMT_Encode4(`63229`),
23901	/ 63081 / /GILLT_v2s64//Label 1753/ GIMT_Encode4(`63255`),
23902	/ 63085 / // Label 1750: @63085
23903	/ 63085 / GIM_Try, /On fail goto//Label 1755/ GIMT_Encode4(`63130`),
23904	/ 63090 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23905	/ 63093 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23906	/ 63097 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
23907	/ 63101 / GIM_Try_CheckFeatures, /On fail goto//Label 1756/ GIMT_Encode4(`63115`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 126 //
23908	/ 63108 / // (fabs:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FABS_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
23909	/ 63108 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_S),
23910	/ 63113 / GIR_RootConstrainSelectedInstOperands,
23911	/ 63114 / // GIR_Coverage, 126,
23912	/ 63114 / GIR_Done,
23913	/ 63115 / // Label 1756: @63115
23914	/ 63115 / GIM_Try_CheckFeatures, /On fail goto//Label 1757/ GIMT_Encode4(`63129`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1173 //
23915	/ 63122 / // (fabs:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FABS_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
23916	/ 63122 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_S_MM),
23917	/ 63127 / GIR_RootConstrainSelectedInstOperands,
23918	/ 63128 / // GIR_Coverage, 1173,
23919	/ 63128 / GIR_Done,
23920	/ 63129 / // Label 1757: @63129
23921	/ 63129 / GIM_Reject,
23922	/ 63130 / // Label 1755: @63130
23923	/ 63130 / GIM_Reject,
23924	/ 63131 / // Label 1751: @63131
23925	/ 63131 / GIM_Try, /On fail goto//Label 1758/ GIMT_Encode4(`63228`),
23926	/ 63136 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
23927	/ 63139 / GIM_Try_CheckFeatures, /On fail goto//Label 1759/ GIMT_Encode4(`63161`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 127 //
23928	/ 63146 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23929	/ 63150 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23930	/ 63154 / // (fabs:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FABS_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
23931	/ 63154 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_D32),
23932	/ 63159 / GIR_RootConstrainSelectedInstOperands,
23933	/ 63160 / // GIR_Coverage, 127,
23934	/ 63160 / GIR_Done,
23935	/ 63161 / // Label 1759: @63161
23936	/ 63161 / GIM_Try_CheckFeatures, /On fail goto//Label 1760/ GIMT_Encode4(`63183`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 128 //
23937	/ 63168 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23938	/ 63172 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23939	/ 63176 / // (fabs:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FABS_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
23940	/ 63176 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_D64),
23941	/ 63181 / GIR_RootConstrainSelectedInstOperands,
23942	/ 63182 / // GIR_Coverage, 128,
23943	/ 63182 / GIR_Done,
23944	/ 63183 / // Label 1760: @63183
23945	/ 63183 / GIM_Try_CheckFeatures, /On fail goto//Label 1761/ GIMT_Encode4(`63205`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1171 //
23946	/ 63190 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23947	/ 63194 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
23948	/ 63198 / // (fabs:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FABS_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
23949	/ 63198 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_D32_MM),
23950	/ 63203 / GIR_RootConstrainSelectedInstOperands,
23951	/ 63204 / // GIR_Coverage, 1171,
23952	/ 63204 / GIR_Done,
23953	/ 63205 / // Label 1761: @63205
23954	/ 63205 / GIM_Try_CheckFeatures, /On fail goto//Label 1762/ GIMT_Encode4(`63227`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1172 //
23955	/ 63212 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23956	/ 63216 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
23957	/ 63220 / // (fabs:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FABS_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
23958	/ 63220 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_D64_MM),
23959	/ 63225 / GIR_RootConstrainSelectedInstOperands,
23960	/ 63226 / // GIR_Coverage, 1172,
23961	/ 63226 / GIR_Done,
23962	/ 63227 / // Label 1762: @63227
23963	/ 63227 / GIM_Reject,
23964	/ 63228 / // Label 1758: @63228
23965	/ 63228 / GIM_Reject,
23966	/ 63229 / // Label 1752: @63229
23967	/ 63229 / GIM_Try_CheckFeatures, /On fail goto//Label 1763/ GIMT_Encode4(`63254`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1069 //
23968	/ 63236 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
23969	/ 63239 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23970	/ 63243 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
23971	/ 63247 / // (fabs:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FABS_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)
23972	/ 63247 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_W),
23973	/ 63252 / GIR_RootConstrainSelectedInstOperands,
23974	/ 63253 / // GIR_Coverage, 1069,
23975	/ 63253 / GIR_Done,
23976	/ 63254 / // Label 1763: @63254
23977	/ 63254 / GIM_Reject,
23978	/ 63255 / // Label 1753: @63255
23979	/ 63255 / GIM_Try_CheckFeatures, /On fail goto//Label 1764/ GIMT_Encode4(`63280`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1070 //
23980	/ 63262 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
23981	/ 63265 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23982	/ 63269 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
23983	/ 63273 / // (fabs:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FABS_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)
23984	/ 63273 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FABS_D),
23985	/ 63278 / GIR_RootConstrainSelectedInstOperands,
23986	/ 63279 / // GIR_Coverage, 1070,
23987	/ 63279 / GIR_Done,
23988	/ 63280 / // Label 1764: @63280
23989	/ 63280 / GIM_Reject,
23990	/ 63281 / // Label 1754: @63281
23991	/ 63281 / GIM_Reject,
23992	/ 63282 / // Label 61: @63282
23993	/ 63282 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1767/ GIMT_Encode4(`63353`),
23994	/ 63293 / /GILLT_s32//Label 1765/ GIMT_Encode4(`63301`),
23995	/ 63297 / /GILLT_s64//Label 1766/ GIMT_Encode4(`63327`),
23996	/ 63301 / // Label 1765: @63301
23997	/ 63301 / GIM_Try_CheckFeatures, /On fail goto//Label 1768/ GIMT_Encode4(`63326`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1889 //
23998	/ 63308 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
23999	/ 63311 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24000	/ 63315 / // (fcanonicalize:{ :[f32] } f32:{ :[f32] }:$src) => (MIN_S:{ :[f32] } f32:{ :[f32] }:$src, f32:{ :[f32] }:$src)*
24001	/ 63315 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_S),
24002	/ 63318 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
24003	/ 63320 / GIR_RootToRootCopy, /OpIdx/`1`, // src
24004	/ 63322 / GIR_RootToRootCopy, /OpIdx/`1`, // src
24005	/ 63324 / GIR_RootConstrainSelectedInstOperands,
24006	/ 63325 / // GIR_Coverage, 1889,
24007	/ 63325 / GIR_EraseRootFromParent_Done,
24008	/ 63326 / // Label 1768: @63326
24009	/ 63326 / GIM_Reject,
24010	/ 63327 / // Label 1766: @63327
24011	/ 63327 / GIM_Try_CheckFeatures, /On fail goto//Label 1769/ GIMT_Encode4(`63352`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1890 //
24012	/ 63334 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24013	/ 63337 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24014	/ 63341 / // (fcanonicalize:{ :[f64] } f64:{ :[f64] }:$src) => (MIN_D:{ :[f64] } f64:{ :[f64] }:$src, f64:{ :[f64] }:$src)*
24015	/ 63341 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MIN_D),
24016	/ 63344 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
24017	/ 63346 / GIR_RootToRootCopy, /OpIdx/`1`, // src
24018	/ 63348 / GIR_RootToRootCopy, /OpIdx/`1`, // src
24019	/ 63350 / GIR_RootConstrainSelectedInstOperands,
24020	/ 63351 / // GIR_Coverage, 1890,
24021	/ 63351 / GIR_EraseRootFromParent_Done,
24022	/ 63352 / // Label 1769: @63352
24023	/ 63352 / GIM_Reject,
24024	/ 63353 / // Label 1767: @63353
24025	/ 63353 / GIM_Reject,
24026	/ 63354 / // Label 62: @63354
24027	/ 63354 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1772/ GIMT_Encode4(`63423`),
24028	/ 63365 / /GILLT_s32//Label 1770/ GIMT_Encode4(`63373`),
24029	/ 63369 / /GILLT_s64//Label 1771/ GIMT_Encode4(`63398`),
24030	/ 63373 / // Label 1770: @63373
24031	/ 63373 / GIM_Try_CheckFeatures, /On fail goto//Label 1773/ GIMT_Encode4(`63397`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1886 //
24032	/ 63380 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24033	/ 63383 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24034	/ 63386 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24035	/ 63390 / // (fminnum:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs) => (MIN_S:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs)
24036	/ 63390 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S),
24037	/ 63395 / GIR_RootConstrainSelectedInstOperands,
24038	/ 63396 / // GIR_Coverage, 1886,
24039	/ 63396 / GIR_Done,
24040	/ 63397 / // Label 1773: @63397
24041	/ 63397 / GIM_Reject,
24042	/ 63398 / // Label 1771: @63398
24043	/ 63398 / GIM_Try_CheckFeatures, /On fail goto//Label 1774/ GIMT_Encode4(`63422`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1888 //
24044	/ 63405 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24045	/ 63408 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
24046	/ 63411 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24047	/ 63415 / // (fminnum:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs) => (MIN_D:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs)
24048	/ 63415 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_D),
24049	/ 63420 / GIR_RootConstrainSelectedInstOperands,
24050	/ 63421 / // GIR_Coverage, 1888,
24051	/ 63421 / GIR_Done,
24052	/ 63422 / // Label 1774: @63422
24053	/ 63422 / GIM_Reject,
24054	/ 63423 / // Label 1772: @63423
24055	/ 63423 / GIM_Reject,
24056	/ 63424 / // Label 63: @63424
24057	/ 63424 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1777/ GIMT_Encode4(`63493`),
24058	/ 63435 / /GILLT_s32//Label 1775/ GIMT_Encode4(`63443`),
24059	/ 63439 / /GILLT_s64//Label 1776/ GIMT_Encode4(`63468`),
24060	/ 63443 / // Label 1775: @63443
24061	/ 63443 / GIM_Try_CheckFeatures, /On fail goto//Label 1778/ GIMT_Encode4(`63467`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1882 //
24062	/ 63450 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24063	/ 63453 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24064	/ 63456 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24065	/ 63460 / // (fmaxnum:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs) => (MAX_S:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs)
24066	/ 63460 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S),
24067	/ 63465 / GIR_RootConstrainSelectedInstOperands,
24068	/ 63466 / // GIR_Coverage, 1882,
24069	/ 63466 / GIR_Done,
24070	/ 63467 / // Label 1778: @63467
24071	/ 63467 / GIM_Reject,
24072	/ 63468 / // Label 1776: @63468
24073	/ 63468 / GIM_Try_CheckFeatures, /On fail goto//Label 1779/ GIMT_Encode4(`63492`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1884 //
24074	/ 63475 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24075	/ 63478 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
24076	/ 63481 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24077	/ 63485 / // (fmaxnum:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs) => (MAX_D:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs)
24078	/ 63485 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_D),
24079	/ 63490 / GIR_RootConstrainSelectedInstOperands,
24080	/ 63491 / // GIR_Coverage, 1884,
24081	/ 63491 / GIR_Done,
24082	/ 63492 / // Label 1779: @63492
24083	/ 63492 / GIM_Reject,
24084	/ 63493 / // Label 1777: @63493
24085	/ 63493 / GIM_Reject,
24086	/ 63494 / // Label 64: @63494
24087	/ 63494 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1782/ GIMT_Encode4(`63563`),
24088	/ 63505 / /GILLT_s32//Label 1780/ GIMT_Encode4(`63513`),
24089	/ 63509 / /GILLT_s64//Label 1781/ GIMT_Encode4(`63538`),
24090	/ 63513 / // Label 1780: @63513
24091	/ 63513 / GIM_Try_CheckFeatures, /On fail goto//Label 1783/ GIMT_Encode4(`63537`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1885 //
24092	/ 63520 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24093	/ 63523 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24094	/ 63526 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24095	/ 63530 / // (fminnum_ieee:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs) => (MIN_S:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs)
24096	/ 63530 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S),
24097	/ 63535 / GIR_RootConstrainSelectedInstOperands,
24098	/ 63536 / // GIR_Coverage, 1885,
24099	/ 63536 / GIR_Done,
24100	/ 63537 / // Label 1783: @63537
24101	/ 63537 / GIM_Reject,
24102	/ 63538 / // Label 1781: @63538
24103	/ 63538 / GIM_Try_CheckFeatures, /On fail goto//Label 1784/ GIMT_Encode4(`63562`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1887 //
24104	/ 63545 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24105	/ 63548 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
24106	/ 63551 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24107	/ 63555 / // (fminnum_ieee:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs) => (MIN_D:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs)
24108	/ 63555 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_D),
24109	/ 63560 / GIR_RootConstrainSelectedInstOperands,
24110	/ 63561 / // GIR_Coverage, 1887,
24111	/ 63561 / GIR_Done,
24112	/ 63562 / // Label 1784: @63562
24113	/ 63562 / GIM_Reject,
24114	/ 63563 / // Label 1782: @63563
24115	/ 63563 / GIM_Reject,
24116	/ 63564 / // Label 65: @63564
24117	/ 63564 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1787/ GIMT_Encode4(`63633`),
24118	/ 63575 / /GILLT_s32//Label 1785/ GIMT_Encode4(`63583`),
24119	/ 63579 / /GILLT_s64//Label 1786/ GIMT_Encode4(`63608`),
24120	/ 63583 / // Label 1785: @63583
24121	/ 63583 / GIM_Try_CheckFeatures, /On fail goto//Label 1788/ GIMT_Encode4(`63607`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1881 //
24122	/ 63590 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24123	/ 63593 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24124	/ 63596 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24125	/ 63600 / // (fmaxnum_ieee:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs) => (MAX_S:{ :[f32] } f32:{ :[f32] }:$lhs, f32:{ :[f32] }:$rhs)
24126	/ 63600 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S),
24127	/ 63605 / GIR_RootConstrainSelectedInstOperands,
24128	/ 63606 / // GIR_Coverage, 1881,
24129	/ 63606 / GIR_Done,
24130	/ 63607 / // Label 1788: @63607
24131	/ 63607 / GIM_Reject,
24132	/ 63608 / // Label 1786: @63608
24133	/ 63608 / GIM_Try_CheckFeatures, /On fail goto//Label 1789/ GIMT_Encode4(`63632`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1883 //
24134	/ 63615 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24135	/ 63618 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
24136	/ 63621 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24137	/ 63625 / // (fmaxnum_ieee:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs) => (MAX_D:{ :[f64] } f64:{ :[f64] }:$lhs, f64:{ :[f64] }:$rhs)
24138	/ 63625 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_D),
24139	/ 63630 / GIR_RootConstrainSelectedInstOperands,
24140	/ 63631 / // GIR_Coverage, 1883,
24141	/ 63631 / GIR_Done,
24142	/ 63632 / // Label 1789: @63632
24143	/ 63632 / GIM_Reject,
24144	/ 63633 / // Label 1787: @63633
24145	/ 63633 / GIM_Reject,
24146	/ 63634 / // Label 66: @63634
24147	/ 63634 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 1794/ GIMT_Encode4(`63797`),
24148	/ 63645 / /GILLT_v16s8//Label 1790/ GIMT_Encode4(`63665`), GIMT_Encode4(`0`),
24149	/ 63653 / /GILLT_v8s16//Label 1791/ GIMT_Encode4(`63698`),
24150	/ 63657 / /GILLT_v4s32//Label 1792/ GIMT_Encode4(`63731`),
24151	/ 63661 / /GILLT_v2s64//Label 1793/ GIMT_Encode4(`63764`),
24152	/ 63665 / // Label 1790: @63665
24153	/ 63665 / GIM_Try_CheckFeatures, /On fail goto//Label 1795/ GIMT_Encode4(`63697`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 895 //
24154	/ 63672 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24155	/ 63675 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
24156	/ 63678 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24157	/ 63682 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24158	/ 63686 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24159	/ 63690 / // (smin:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MIN_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
24160	/ 63690 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S_B),
24161	/ 63695 / GIR_RootConstrainSelectedInstOperands,
24162	/ 63696 / // GIR_Coverage, 895,
24163	/ 63696 / GIR_Done,
24164	/ 63697 / // Label 1795: @63697
24165	/ 63697 / GIM_Reject,
24166	/ 63698 / // Label 1791: @63698
24167	/ 63698 / GIM_Try_CheckFeatures, /On fail goto//Label 1796/ GIMT_Encode4(`63730`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 896 //
24168	/ 63705 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24169	/ 63708 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
24170	/ 63711 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24171	/ 63715 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24172	/ 63719 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24173	/ 63723 / // (smin:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MIN_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
24174	/ 63723 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S_H),
24175	/ 63728 / GIR_RootConstrainSelectedInstOperands,
24176	/ 63729 / // GIR_Coverage, 896,
24177	/ 63729 / GIR_Done,
24178	/ 63730 / // Label 1796: @63730
24179	/ 63730 / GIM_Reject,
24180	/ 63731 / // Label 1792: @63731
24181	/ 63731 / GIM_Try_CheckFeatures, /On fail goto//Label 1797/ GIMT_Encode4(`63763`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 897 //
24182	/ 63738 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24183	/ 63741 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
24184	/ 63744 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24185	/ 63748 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24186	/ 63752 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24187	/ 63756 / // (smin:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MIN_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
24188	/ 63756 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S_W),
24189	/ 63761 / GIR_RootConstrainSelectedInstOperands,
24190	/ 63762 / // GIR_Coverage, 897,
24191	/ 63762 / GIR_Done,
24192	/ 63763 / // Label 1797: @63763
24193	/ 63763 / GIM_Reject,
24194	/ 63764 / // Label 1793: @63764
24195	/ 63764 / GIM_Try_CheckFeatures, /On fail goto//Label 1798/ GIMT_Encode4(`63796`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 898 //
24196	/ 63771 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24197	/ 63774 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
24198	/ 63777 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24199	/ 63781 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24200	/ 63785 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24201	/ 63789 / // (smin:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MIN_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
24202	/ 63789 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_S_D),
24203	/ 63794 / GIR_RootConstrainSelectedInstOperands,
24204	/ 63795 / // GIR_Coverage, 898,
24205	/ 63795 / GIR_Done,
24206	/ 63796 / // Label 1798: @63796
24207	/ 63796 / GIM_Reject,
24208	/ 63797 / // Label 1794: @63797
24209	/ 63797 / GIM_Reject,
24210	/ 63798 / // Label 67: @63798
24211	/ 63798 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 1803/ GIMT_Encode4(`63961`),
24212	/ 63809 / /GILLT_v16s8//Label 1799/ GIMT_Encode4(`63829`), GIMT_Encode4(`0`),
24213	/ 63817 / /GILLT_v8s16//Label 1800/ GIMT_Encode4(`63862`),
24214	/ 63821 / /GILLT_v4s32//Label 1801/ GIMT_Encode4(`63895`),
24215	/ 63825 / /GILLT_v2s64//Label 1802/ GIMT_Encode4(`63928`),
24216	/ 63829 / // Label 1799: @63829
24217	/ 63829 / GIM_Try_CheckFeatures, /On fail goto//Label 1804/ GIMT_Encode4(`63861`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 875 //
24218	/ 63836 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24219	/ 63839 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
24220	/ 63842 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24221	/ 63846 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24222	/ 63850 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24223	/ 63854 / // (smax:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MAX_S_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
24224	/ 63854 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S_B),
24225	/ 63859 / GIR_RootConstrainSelectedInstOperands,
24226	/ 63860 / // GIR_Coverage, 875,
24227	/ 63860 / GIR_Done,
24228	/ 63861 / // Label 1804: @63861
24229	/ 63861 / GIM_Reject,
24230	/ 63862 / // Label 1800: @63862
24231	/ 63862 / GIM_Try_CheckFeatures, /On fail goto//Label 1805/ GIMT_Encode4(`63894`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 876 //
24232	/ 63869 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24233	/ 63872 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
24234	/ 63875 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24235	/ 63879 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24236	/ 63883 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24237	/ 63887 / // (smax:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MAX_S_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
24238	/ 63887 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S_H),
24239	/ 63892 / GIR_RootConstrainSelectedInstOperands,
24240	/ 63893 / // GIR_Coverage, 876,
24241	/ 63893 / GIR_Done,
24242	/ 63894 / // Label 1805: @63894
24243	/ 63894 / GIM_Reject,
24244	/ 63895 / // Label 1801: @63895
24245	/ 63895 / GIM_Try_CheckFeatures, /On fail goto//Label 1806/ GIMT_Encode4(`63927`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 877 //
24246	/ 63902 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24247	/ 63905 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
24248	/ 63908 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24249	/ 63912 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24250	/ 63916 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24251	/ 63920 / // (smax:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MAX_S_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
24252	/ 63920 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S_W),
24253	/ 63925 / GIR_RootConstrainSelectedInstOperands,
24254	/ 63926 / // GIR_Coverage, 877,
24255	/ 63926 / GIR_Done,
24256	/ 63927 / // Label 1806: @63927
24257	/ 63927 / GIM_Reject,
24258	/ 63928 / // Label 1802: @63928
24259	/ 63928 / GIM_Try_CheckFeatures, /On fail goto//Label 1807/ GIMT_Encode4(`63960`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 878 //
24260	/ 63935 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24261	/ 63938 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
24262	/ 63941 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24263	/ 63945 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24264	/ 63949 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24265	/ 63953 / // (smax:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MAX_S_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
24266	/ 63953 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_S_D),
24267	/ 63958 / GIR_RootConstrainSelectedInstOperands,
24268	/ 63959 / // GIR_Coverage, 878,
24269	/ 63959 / GIR_Done,
24270	/ 63960 / // Label 1807: @63960
24271	/ 63960 / GIM_Reject,
24272	/ 63961 / // Label 1803: @63961
24273	/ 63961 / GIM_Reject,
24274	/ 63962 / // Label 68: @63962
24275	/ 63962 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 1812/ GIMT_Encode4(`64125`),
24276	/ 63973 / /GILLT_v16s8//Label 1808/ GIMT_Encode4(`63993`), GIMT_Encode4(`0`),
24277	/ 63981 / /GILLT_v8s16//Label 1809/ GIMT_Encode4(`64026`),
24278	/ 63985 / /GILLT_v4s32//Label 1810/ GIMT_Encode4(`64059`),
24279	/ 63989 / /GILLT_v2s64//Label 1811/ GIMT_Encode4(`64092`),
24280	/ 63993 / // Label 1808: @63993
24281	/ 63993 / GIM_Try_CheckFeatures, /On fail goto//Label 1813/ GIMT_Encode4(`64025`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 899 //
24282	/ 64000 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24283	/ 64003 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
24284	/ 64006 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24285	/ 64010 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24286	/ 64014 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24287	/ 64018 / // (umin:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MIN_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
24288	/ 64018 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_U_B),
24289	/ 64023 / GIR_RootConstrainSelectedInstOperands,
24290	/ 64024 / // GIR_Coverage, 899,
24291	/ 64024 / GIR_Done,
24292	/ 64025 / // Label 1813: @64025
24293	/ 64025 / GIM_Reject,
24294	/ 64026 / // Label 1809: @64026
24295	/ 64026 / GIM_Try_CheckFeatures, /On fail goto//Label 1814/ GIMT_Encode4(`64058`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 900 //
24296	/ 64033 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24297	/ 64036 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
24298	/ 64039 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24299	/ 64043 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24300	/ 64047 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24301	/ 64051 / // (umin:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MIN_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
24302	/ 64051 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_U_H),
24303	/ 64056 / GIR_RootConstrainSelectedInstOperands,
24304	/ 64057 / // GIR_Coverage, 900,
24305	/ 64057 / GIR_Done,
24306	/ 64058 / // Label 1814: @64058
24307	/ 64058 / GIM_Reject,
24308	/ 64059 / // Label 1810: @64059
24309	/ 64059 / GIM_Try_CheckFeatures, /On fail goto//Label 1815/ GIMT_Encode4(`64091`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 901 //
24310	/ 64066 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24311	/ 64069 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
24312	/ 64072 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24313	/ 64076 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24314	/ 64080 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24315	/ 64084 / // (umin:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MIN_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
24316	/ 64084 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_U_W),
24317	/ 64089 / GIR_RootConstrainSelectedInstOperands,
24318	/ 64090 / // GIR_Coverage, 901,
24319	/ 64090 / GIR_Done,
24320	/ 64091 / // Label 1815: @64091
24321	/ 64091 / GIM_Reject,
24322	/ 64092 / // Label 1811: @64092
24323	/ 64092 / GIM_Try_CheckFeatures, /On fail goto//Label 1816/ GIMT_Encode4(`64124`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 902 //
24324	/ 64099 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24325	/ 64102 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
24326	/ 64105 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24327	/ 64109 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24328	/ 64113 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24329	/ 64117 / // (umin:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MIN_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
24330	/ 64117 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MIN_U_D),
24331	/ 64122 / GIR_RootConstrainSelectedInstOperands,
24332	/ 64123 / // GIR_Coverage, 902,
24333	/ 64123 / GIR_Done,
24334	/ 64124 / // Label 1816: @64124
24335	/ 64124 / GIM_Reject,
24336	/ 64125 / // Label 1812: @64125
24337	/ 64125 / GIM_Reject,
24338	/ 64126 / // Label 69: @64126
24339	/ 64126 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 1821/ GIMT_Encode4(`64289`),
24340	/ 64137 / /GILLT_v16s8//Label 1817/ GIMT_Encode4(`64157`), GIMT_Encode4(`0`),
24341	/ 64145 / /GILLT_v8s16//Label 1818/ GIMT_Encode4(`64190`),
24342	/ 64149 / /GILLT_v4s32//Label 1819/ GIMT_Encode4(`64223`),
24343	/ 64153 / /GILLT_v2s64//Label 1820/ GIMT_Encode4(`64256`),
24344	/ 64157 / // Label 1817: @64157
24345	/ 64157 / GIM_Try_CheckFeatures, /On fail goto//Label 1822/ GIMT_Encode4(`64189`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 879 //
24346	/ 64164 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24347	/ 64167 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v16s8,
24348	/ 64170 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24349	/ 64174 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24350	/ 64178 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24351	/ 64182 / // (umax:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt) => (MAX_U_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws, MSA128BOpnd:{ :[v16i8] }:$wt)
24352	/ 64182 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_U_B),
24353	/ 64187 / GIR_RootConstrainSelectedInstOperands,
24354	/ 64188 / // GIR_Coverage, 879,
24355	/ 64188 / GIR_Done,
24356	/ 64189 / // Label 1822: @64189
24357	/ 64189 / GIM_Reject,
24358	/ 64190 / // Label 1818: @64190
24359	/ 64190 / GIM_Try_CheckFeatures, /On fail goto//Label 1823/ GIMT_Encode4(`64222`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 880 //
24360	/ 64197 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24361	/ 64200 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v8s16,
24362	/ 64203 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24363	/ 64207 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24364	/ 64211 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24365	/ 64215 / // (umax:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt) => (MAX_U_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws, MSA128HOpnd:{ :[v8i16] }:$wt)
24366	/ 64215 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_U_H),
24367	/ 64220 / GIR_RootConstrainSelectedInstOperands,
24368	/ 64221 / // GIR_Coverage, 880,
24369	/ 64221 / GIR_Done,
24370	/ 64222 / // Label 1823: @64222
24371	/ 64222 / GIM_Reject,
24372	/ 64223 / // Label 1819: @64223
24373	/ 64223 / GIM_Try_CheckFeatures, /On fail goto//Label 1824/ GIMT_Encode4(`64255`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 881 //
24374	/ 64230 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24375	/ 64233 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v4s32,
24376	/ 64236 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24377	/ 64240 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24378	/ 64244 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24379	/ 64248 / // (umax:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt) => (MAX_U_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws, MSA128WOpnd:{ :[v4i32] }:$wt)
24380	/ 64248 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_U_W),
24381	/ 64253 / GIR_RootConstrainSelectedInstOperands,
24382	/ 64254 / // GIR_Coverage, 881,
24383	/ 64254 / GIR_Done,
24384	/ 64255 / // Label 1824: @64255
24385	/ 64255 / GIM_Reject,
24386	/ 64256 / // Label 1820: @64256
24387	/ 64256 / GIM_Try_CheckFeatures, /On fail goto//Label 1825/ GIMT_Encode4(`64288`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 882 //
24388	/ 64263 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24389	/ 64266 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_v2s64,
24390	/ 64269 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24391	/ 64273 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24392	/ 64277 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24393	/ 64281 / // (umax:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt) => (MAX_U_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws, MSA128DOpnd:{ :[v2i64] }:$wt)
24394	/ 64281 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::MAX_U_D),
24395	/ 64286 / GIR_RootConstrainSelectedInstOperands,
24396	/ 64287 / // GIR_Coverage, 882,
24397	/ 64287 / GIR_Done,
24398	/ 64288 / // Label 1825: @64288
24399	/ 64288 / GIM_Reject,
24400	/ 64289 / // Label 1821: @64289
24401	/ 64289 / GIM_Reject,
24402	/ 64290 / // Label 70: @64290
24403	/ 64290 / GIM_Try, /On fail goto//Label 1826/ GIMT_Encode4(`64407`),
24404	/ 64295 / GIM_CheckIsMBB, /MI/`0`, /Op/`0`,
24405	/ 64298 / GIM_Try_CheckFeatures, /On fail goto//Label 1827/ GIMT_Encode4(`64318`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC), // Rule ID 91 //
24406	/ 64305 / // (br (bb:{ :[Other] }):$target) => (J (bb:{ :[Other] }):$target)
24407	/ 64305 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::J),
24408	/ 64310 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24409	/ 64316 / GIR_RootConstrainSelectedInstOperands,
24410	/ 64317 / // GIR_Coverage, 91,
24411	/ 64317 / GIR_Done,
24412	/ 64318 / // Label 1827: @64318
24413	/ 64318 / GIM_Try_CheckFeatures, /On fail goto//Label 1828/ GIMT_Encode4(`64338`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 98 //
24414	/ 64325 / // (br (bb:{ :[Other] }):$offset) => (B (bb:{ :[Other] }):$offset)
24415	/ 64325 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::B),
24416	/ 64330 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24417	/ 64336 / GIR_RootConstrainSelectedInstOperands,
24418	/ 64337 / // GIR_Coverage, 98,
24419	/ 64337 / GIR_Done,
24420	/ 64338 / // Label 1828: @64338
24421	/ 64338 / GIM_Try_CheckFeatures, /On fail goto//Label 1829/ GIMT_Encode4(`64358`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC), // Rule ID 1125 //
24422	/ 64345 / // (br (bb:{ :[Other] }):$target) => (J_MM (bb:{ :[Other] }):$target)
24423	/ 64345 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::J_MM),
24424	/ 64350 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24425	/ 64356 / GIR_RootConstrainSelectedInstOperands,
24426	/ 64357 / // GIR_Coverage, 1125,
24427	/ 64357 / GIR_Done,
24428	/ 64358 / // Label 1829: @64358
24429	/ 64358 / GIM_Try_CheckFeatures, /On fail goto//Label 1830/ GIMT_Encode4(`64378`), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC), // Rule ID 1134 //
24430	/ 64365 / // (br (bb:{ :[Other] }):$offset) => (B_MM (bb:{ :[Other] }):$offset)
24431	/ 64365 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::B_MM),
24432	/ 64370 / GIR_AddImplicitDef, /InsnID/`0`, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24433	/ 64376 / GIR_RootConstrainSelectedInstOperands,
24434	/ 64377 / // GIR_Coverage, 1134,
24435	/ 64377 / GIR_Done,
24436	/ 64378 / // Label 1830: @64378
24437	/ 64378 / GIM_Try_CheckFeatures, /On fail goto//Label 1831/ GIMT_Encode4(`64392`), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1192 //
24438	/ 64385 / // (br (bb:{ :[Other] }):$offset) => (BC_MMR6 (bb:{ :[Other] }):$offset)
24439	/ 64385 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::BC_MMR6),
24440	/ 64390 / GIR_RootConstrainSelectedInstOperands,
24441	/ 64391 / // GIR_Coverage, 1192,
24442	/ 64391 / GIR_Done,
24443	/ 64392 / // Label 1831: @64392
24444	/ 64392 / GIM_Try_CheckFeatures, /On fail goto//Label 1832/ GIMT_Encode4(`64406`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1994 //
24445	/ 64399 / // (br (bb:{ :[Other] }):$imm16) => (Bimm16 (bb:{ :[Other] }):$imm16)
24446	/ 64399 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::Bimm16),
24447	/ 64404 / GIR_RootConstrainSelectedInstOperands,
24448	/ 64405 / // GIR_Coverage, 1994,
24449	/ 64405 / GIR_Done,
24450	/ 64406 / // Label 1832: @64406
24451	/ 64406 / GIM_Reject,
24452	/ 64407 / // Label 1826: @64407
24453	/ 64407 / GIM_Reject,
24454	/ 64408 / // Label 71: @64408
24455	/ 64408 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`3`), GIMT_Encode2(`8`), /)//default://Label 1837/ GIMT_Encode4(`64999`),
24456	/ 64419 / /GILLT_v16s8//Label 1833/ GIMT_Encode4(`64439`), GIMT_Encode4(`0`),
24457	/ 64427 / /GILLT_v8s16//Label 1834/ GIMT_Encode4(`64545`),
24458	/ 64431 / /GILLT_v4s32//Label 1835/ GIMT_Encode4(`64651`),
24459	/ 64435 / /GILLT_v2s64//Label 1836/ GIMT_Encode4(`64825`),
24460	/ 64439 / // Label 1833: @64439
24461	/ 64439 / GIM_Try, /On fail goto//Label 1838/ GIMT_Encode4(`64544`),
24462	/ 64444 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24463	/ 64447 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24464	/ 64450 / GIM_SwitchType, /MI/`0`, /Op/`3`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1841/ GIMT_Encode4(`64543`),
24465	/ 64461 / /GILLT_s32//Label 1839/ GIMT_Encode4(`64469`),
24466	/ 64465 / /GILLT_s64//Label 1840/ GIMT_Encode4(`64506`),
24467	/ 64469 / // Label 1839: @64469
24468	/ 64469 / GIM_Try_CheckFeatures, /On fail goto//Label 1842/ GIMT_Encode4(`64505`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 845 //
24469	/ 64476 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24470	/ 64480 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24471	/ 64484 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24472	/ 64488 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24473	/* 64492 / // (vector_insert:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24474	/ 64492 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
24475	/ 64495 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24476	/ 64497 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24477	/ 64499 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24478	/ 64501 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24479	/ 64503 / GIR_RootConstrainSelectedInstOperands,
24480	/ 64504 / // GIR_Coverage, 845,
24481	/ 64504 / GIR_EraseRootFromParent_Done,
24482	/ 64505 / // Label 1842: @64505
24483	/ 64505 / GIM_Reject,
24484	/ 64506 / // Label 1840: @64506
24485	/ 64506 / GIM_Try_CheckFeatures, /On fail goto//Label 1843/ GIMT_Encode4(`64542`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 851 //
24486	/ 64513 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24487	/ 64517 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24488	/ 64521 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24489	/ 64525 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24490	/* 64529 / // (vector_insert:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24491	/ 64529 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
24492	/ 64532 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24493	/ 64534 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24494	/ 64536 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24495	/ 64538 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24496	/ 64540 / GIR_RootConstrainSelectedInstOperands,
24497	/ 64541 / // GIR_Coverage, 851,
24498	/ 64541 / GIR_EraseRootFromParent_Done,
24499	/ 64542 / // Label 1843: @64542
24500	/ 64542 / GIM_Reject,
24501	/ 64543 / // Label 1841: @64543
24502	/ 64543 / GIM_Reject,
24503	/ 64544 / // Label 1838: @64544
24504	/ 64544 / GIM_Reject,
24505	/ 64545 / // Label 1834: @64545
24506	/ 64545 / GIM_Try, /On fail goto//Label 1844/ GIMT_Encode4(`64650`),
24507	/ 64550 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24508	/ 64553 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24509	/ 64556 / GIM_SwitchType, /MI/`0`, /Op/`3`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1847/ GIMT_Encode4(`64649`),
24510	/ 64567 / /GILLT_s32//Label 1845/ GIMT_Encode4(`64575`),
24511	/ 64571 / /GILLT_s64//Label 1846/ GIMT_Encode4(`64612`),
24512	/ 64575 / // Label 1845: @64575
24513	/ 64575 / GIM_Try_CheckFeatures, /On fail goto//Label 1848/ GIMT_Encode4(`64611`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 846 //
24514	/ 64582 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24515	/ 64586 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24516	/ 64590 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24517	/ 64594 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24518	/* 64598 / // (vector_insert:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24519	/ 64598 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
24520	/ 64601 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24521	/ 64603 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24522	/ 64605 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24523	/ 64607 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24524	/ 64609 / GIR_RootConstrainSelectedInstOperands,
24525	/ 64610 / // GIR_Coverage, 846,
24526	/ 64610 / GIR_EraseRootFromParent_Done,
24527	/ 64611 / // Label 1848: @64611
24528	/ 64611 / GIM_Reject,
24529	/ 64612 / // Label 1846: @64612
24530	/ 64612 / GIM_Try_CheckFeatures, /On fail goto//Label 1849/ GIMT_Encode4(`64648`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 852 //
24531	/ 64619 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24532	/ 64623 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24533	/ 64627 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24534	/ 64631 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24535	/* 64635 / // (vector_insert:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24536	/ 64635 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
24537	/ 64638 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24538	/ 64640 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24539	/ 64642 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24540	/ 64644 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24541	/ 64646 / GIR_RootConstrainSelectedInstOperands,
24542	/ 64647 / // GIR_Coverage, 852,
24543	/ 64647 / GIR_EraseRootFromParent_Done,
24544	/ 64648 / // Label 1849: @64648
24545	/ 64648 / GIM_Reject,
24546	/ 64649 / // Label 1847: @64649
24547	/ 64649 / GIM_Reject,
24548	/ 64650 / // Label 1844: @64650
24549	/ 64650 / GIM_Reject,
24550	/ 64651 / // Label 1835: @64651
24551	/ 64651 / GIM_Try, /On fail goto//Label 1850/ GIMT_Encode4(`64824`),
24552	/ 64656 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24553	/ 64659 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24554	/ 64662 / GIM_SwitchType, /MI/`0`, /Op/`3`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1853/ GIMT_Encode4(`64823`),
24555	/ 64673 / /GILLT_s32//Label 1851/ GIMT_Encode4(`64681`),
24556	/ 64677 / /GILLT_s64//Label 1852/ GIMT_Encode4(`64752`),
24557	/ 64681 / // Label 1851: @64681
24558	/ 64681 / GIM_Try, /On fail goto//Label 1854/ GIMT_Encode4(`64751`),
24559	/ 64686 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24560	/ 64690 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24561	/ 64694 / GIM_Try_CheckFeatures, /On fail goto//Label 1855/ GIMT_Encode4(`64722`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 847 //
24562	/ 64701 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24563	/ 64705 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24564	/* 64709 / // (vector_insert:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24565	/ 64709 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
24566	/ 64712 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24567	/ 64714 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24568	/ 64716 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24569	/ 64718 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24570	/ 64720 / GIR_RootConstrainSelectedInstOperands,
24571	/ 64721 / // GIR_Coverage, 847,
24572	/ 64721 / GIR_EraseRootFromParent_Done,
24573	/ 64722 / // Label 1855: @64722
24574	/ 64722 / GIM_Try_CheckFeatures, /On fail goto//Label 1856/ GIMT_Encode4(`64750`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 849 //
24575	/ 64729 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24576	/ 64733 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24577	/* 64737 / // (vector_insert:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, FGR32Opnd:{ :[f32] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24578	/ 64737 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
24579	/ 64740 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24580	/ 64742 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24581	/ 64744 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24582	/ 64746 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24583	/ 64748 / GIR_RootConstrainSelectedInstOperands,
24584	/ 64749 / // GIR_Coverage, 849,
24585	/ 64749 / GIR_EraseRootFromParent_Done,
24586	/ 64750 / // Label 1856: @64750
24587	/ 64750 / GIM_Reject,
24588	/ 64751 / // Label 1854: @64751
24589	/ 64751 / GIM_Reject,
24590	/ 64752 / // Label 1852: @64752
24591	/ 64752 / GIM_Try, /On fail goto//Label 1857/ GIMT_Encode4(`64822`),
24592	/ 64757 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24593	/ 64761 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24594	/ 64765 / GIM_Try_CheckFeatures, /On fail goto//Label 1858/ GIMT_Encode4(`64793`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 853 //
24595	/ 64772 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24596	/ 64776 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24597	/* 64780 / // (vector_insert:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, GPR32Opnd:{ :[i32] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24598	/ 64780 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
24599	/ 64783 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24600	/ 64785 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24601	/ 64787 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24602	/ 64789 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24603	/ 64791 / GIR_RootConstrainSelectedInstOperands,
24604	/ 64792 / // GIR_Coverage, 853,
24605	/ 64792 / GIR_EraseRootFromParent_Done,
24606	/ 64793 / // Label 1858: @64793
24607	/ 64793 / GIM_Try_CheckFeatures, /On fail goto//Label 1859/ GIMT_Encode4(`64821`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 855 //
24608	/ 64800 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
24609	/ 64804 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24610	/* 64808 / // (vector_insert:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, FGR32Opnd:{ :[f32] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24611	/ 64808 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
24612	/ 64811 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24613	/ 64813 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24614	/ 64815 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24615	/ 64817 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24616	/ 64819 / GIR_RootConstrainSelectedInstOperands,
24617	/ 64820 / // GIR_Coverage, 855,
24618	/ 64820 / GIR_EraseRootFromParent_Done,
24619	/ 64821 / // Label 1859: @64821
24620	/ 64821 / GIM_Reject,
24621	/ 64822 / // Label 1857: @64822
24622	/ 64822 / GIM_Reject,
24623	/ 64823 / // Label 1853: @64823
24624	/ 64823 / GIM_Reject,
24625	/ 64824 / // Label 1850: @64824
24626	/ 64824 / GIM_Reject,
24627	/ 64825 / // Label 1836: @64825
24628	/ 64825 / GIM_Try, /On fail goto//Label 1860/ GIMT_Encode4(`64998`),
24629	/ 64830 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24630	/ 64833 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
24631	/ 64836 / GIM_SwitchType, /MI/`0`, /Op/`3`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1863/ GIMT_Encode4(`64997`),
24632	/ 64847 / /GILLT_s32//Label 1861/ GIMT_Encode4(`64855`),
24633	/ 64851 / /GILLT_s64//Label 1862/ GIMT_Encode4(`64926`),
24634	/ 64855 / // Label 1861: @64855
24635	/ 64855 / GIM_Try, /On fail goto//Label 1864/ GIMT_Encode4(`64925`),
24636	/ 64860 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24637	/ 64864 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24638	/ 64868 / GIM_Try_CheckFeatures, /On fail goto//Label 1865/ GIMT_Encode4(`64896`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 848 //
24639	/ 64875 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24640	/ 64879 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24641	/* 64883 / // (vector_insert:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, GPR64Opnd:{ :[i64] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24642	/ 64883 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
24643	/ 64886 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24644	/ 64888 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24645	/ 64890 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24646	/ 64892 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24647	/ 64894 / GIR_RootConstrainSelectedInstOperands,
24648	/ 64895 / // GIR_Coverage, 848,
24649	/ 64895 / GIR_EraseRootFromParent_Done,
24650	/ 64896 / // Label 1865: @64896
24651	/ 64896 / GIM_Try_CheckFeatures, /On fail goto//Label 1866/ GIMT_Encode4(`64924`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 850 //
24652	/ 64903 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24653	/ 64907 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24654	/* 64911 / // (vector_insert:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, FGR64Opnd:{ :[f64] }:$fs, GPR32Opnd:{ :[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, GPR32Opnd:{ :[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24655	/ 64911 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
24656	/ 64914 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24657	/ 64916 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24658	/ 64918 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24659	/ 64920 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24660	/ 64922 / GIR_RootConstrainSelectedInstOperands,
24661	/ 64923 / // GIR_Coverage, 850,
24662	/ 64923 / GIR_EraseRootFromParent_Done,
24663	/ 64924 / // Label 1866: @64924
24664	/ 64924 / GIM_Reject,
24665	/ 64925 / // Label 1864: @64925
24666	/ 64925 / GIM_Reject,
24667	/ 64926 / // Label 1862: @64926
24668	/ 64926 / GIM_Try, /On fail goto//Label 1867/ GIMT_Encode4(`64996`),
24669	/ 64931 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24670	/ 64935 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24671	/ 64939 / GIM_Try_CheckFeatures, /On fail goto//Label 1868/ GIMT_Encode4(`64967`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 854 //
24672	/ 64946 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24673	/ 64950 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24674	/* 64954 / // (vector_insert:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, GPR64Opnd:{ :[i64] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24675	/ 64954 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
24676	/ 64957 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24677	/ 64959 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24678	/ 64961 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24679	/ 64963 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24680	/ 64965 / GIR_RootConstrainSelectedInstOperands,
24681	/ 64966 / // GIR_Coverage, 854,
24682	/ 64966 / GIR_EraseRootFromParent_Done,
24683	/ 64967 / // Label 1868: @64967
24684	/ 64967 / GIM_Try_CheckFeatures, /On fail goto//Label 1869/ GIMT_Encode4(`64995`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 856 //
24685	/ 64974 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
24686	/ 64978 / GIM_RootCheckRegBankForClass, /Op/`3`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24687	/* 64982 / // (vector_insert:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, FGR64Opnd:{ :[f64] }:$fs, GPR64Opnd:{ :[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$wd_in, GPR64Opnd:{ :[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24688	/ 64982 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
24689	/ 64985 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[wd]
24690	/ 64987 / GIR_RootToRootCopy, /OpIdx/`1`, // wd_in
24691	/ 64989 / GIR_RootToRootCopy, /OpIdx/`3`, // n
24692	/ 64991 / GIR_RootToRootCopy, /OpIdx/`2`, // fs
24693	/ 64993 / GIR_RootConstrainSelectedInstOperands,
24694	/ 64994 / // GIR_Coverage, 856,
24695	/ 64994 / GIR_EraseRootFromParent_Done,
24696	/ 64995 / // Label 1869: @64995
24697	/ 64995 / GIM_Reject,
24698	/ 64996 / // Label 1867: @64996
24699	/ 64996 / GIM_Reject,
24700	/ 64997 / // Label 1863: @64997
24701	/ 64997 / GIM_Reject,
24702	/ 64998 / // Label 1860: @64998
24703	/ 64998 / GIM_Reject,
24704	/ 64999 / // Label 1837: @64999
24705	/ 64999 / GIM_Reject,
24706	/ 65000 / // Label 72: @65000
24707	/ 65000 / GIM_Try_CheckFeatures, /On fail goto//Label 1870/ GIMT_Encode4(`65050`), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2121 //
24708	/ 65007 / GIM_RootCheckType, /Op/`0`, /Type/GILLT_s32,
24709	/ 65010 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24710	/ 65013 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
24711	/ 65016 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24712	/ 65020 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24713	/ 65024 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
24714	/ 65028 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24715	/ 65032 / GIM_CheckI64ImmPredicate, /MI/`1`, /Predicate/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
24716	/ 65036 / // MIs[1] Operand 1
24717	/ 65036 / // No operand predicates
24718	/ 65036 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24719	/* 65038 / // (extractelt:{ :[i32] } MSA128W:{ :[v4i32] }:$ws, (imm:{ :[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ :[i32] } MSA128W:{ :[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
24720	/ 65038 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::COPY_S_W),
24721	/ 65041 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24722	/ 65043 / GIR_RootToRootCopy, /OpIdx/`1`, // ws
24723	/ 65045 / GIR_CopyConstantAsSImm, /NewInsnID/`0`, /OldInsnID/`1`, // idx
24724	/ 65048 / GIR_RootConstrainSelectedInstOperands,
24725	/ 65049 / // GIR_Coverage, 2121,
24726	/ 65049 / GIR_EraseRootFromParent_Done,
24727	/ 65050 / // Label 1870: @65050
24728	/ 65050 / GIM_Reject,
24729	/ 65051 / // Label 73: @65051
24730	/ 65051 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1877/ GIMT_Encode4(`65541`),
24731	/ 65062 / /GILLT_s32//Label 1871/ GIMT_Encode4(`65094`),
24732	/ 65066 / /GILLT_s64//Label 1872/ GIMT_Encode4(`65295`), GIMT_Encode4(`0`),
24733	/ 65074 / /GILLT_v16s8//Label 1873/ GIMT_Encode4(`65437`), GIMT_Encode4(`0`),
24734	/ 65082 / /GILLT_v8s16//Label 1874/ GIMT_Encode4(`65463`),
24735	/ 65086 / /GILLT_v4s32//Label 1875/ GIMT_Encode4(`65489`),
24736	/ 65090 / /GILLT_v2s64//Label 1876/ GIMT_Encode4(`65515`),
24737	/ 65094 / // Label 1871: @65094
24738	/ 65094 / GIM_Try, /On fail goto//Label 1878/ GIMT_Encode4(`65294`),
24739	/ 65099 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24740	/ 65102 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24741	/ 65106 / GIM_Try_CheckFeatures, /On fail goto//Label 1879/ GIMT_Encode4(`65151`), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 109 //
24742	/ 65113 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
24743	/ 65117 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_XOR),
24744	/ 65121 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
24745	/ 65125 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
24746	/ 65129 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24747	/ 65134 / GIM_CheckConstantInt8, /MI/`1`, /Op/`2`, `255`,
24748	/ 65138 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24749	/ 65140 / // (ctlz:{ :[i32] } (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, -1:{ :[i32] })) => (CLO:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24750	/ 65140 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CLO),
24751	/ 65143 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24752	/ 65145 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
24753	/ 65149 / GIR_RootConstrainSelectedInstOperands,
24754	/ 65150 / // GIR_Coverage, 109,
24755	/ 65150 / GIR_EraseRootFromParent_Done,
24756	/ 65151 / // Label 1879: @65151
24757	/ 65151 / GIM_Try_CheckFeatures, /On fail goto//Label 1880/ GIMT_Encode4(`65196`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 337 //
24758	/ 65158 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
24759	/ 65162 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_XOR),
24760	/ 65166 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
24761	/ 65170 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
24762	/ 65174 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24763	/ 65179 / GIM_CheckConstantInt8, /MI/`1`, /Op/`2`, `255`,
24764	/ 65183 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24765	/ 65185 / // (ctlz:{ :[i32] } (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, -1:{ :[i32] })) => (CLO_R6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24766	/ 65185 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CLO_R6),
24767	/ 65188 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24768	/ 65190 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
24769	/ 65194 / GIR_RootConstrainSelectedInstOperands,
24770	/ 65195 / // GIR_Coverage, 337,
24771	/ 65195 / GIR_EraseRootFromParent_Done,
24772	/ 65196 / // Label 1880: @65196
24773	/ 65196 / GIM_Try_CheckFeatures, /On fail goto//Label 1881/ GIMT_Encode4(`65241`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1121 //
24774	/ 65203 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
24775	/ 65207 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_XOR),
24776	/ 65211 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
24777	/ 65215 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
24778	/ 65219 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24779	/ 65224 / GIM_CheckConstantInt8, /MI/`1`, /Op/`2`, `255`,
24780	/ 65228 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24781	/ 65230 / // (ctlz:{ :[i32] } (xor:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs, -1:{ :[i32] })) => (CLO_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24782	/ 65230 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::CLO_MM),
24783	/ 65233 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24784	/ 65235 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
24785	/ 65239 / GIR_RootConstrainSelectedInstOperands,
24786	/ 65240 / // GIR_Coverage, 1121,
24787	/ 65240 / GIR_EraseRootFromParent_Done,
24788	/ 65241 / // Label 1881: @65241
24789	/ 65241 / GIM_Try, /On fail goto//Label 1882/ GIMT_Encode4(`65293`),
24790	/ 65246 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24791	/ 65250 / GIM_Try_CheckFeatures, /On fail goto//Label 1883/ GIMT_Encode4(`65264`), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 108 //
24792	/ 65257 / // (ctlz:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs) => (CLZ:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24793	/ 65257 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CLZ),
24794	/ 65262 / GIR_RootConstrainSelectedInstOperands,
24795	/ 65263 / // GIR_Coverage, 108,
24796	/ 65263 / GIR_Done,
24797	/ 65264 / // Label 1883: @65264
24798	/ 65264 / GIM_Try_CheckFeatures, /On fail goto//Label 1884/ GIMT_Encode4(`65278`), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 338 //
24799	/ 65271 / // (ctlz:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs) => (CLZ_R6:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24800	/ 65271 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CLZ_R6),
24801	/ 65276 / GIR_RootConstrainSelectedInstOperands,
24802	/ 65277 / // GIR_Coverage, 338,
24803	/ 65277 / GIR_Done,
24804	/ 65278 / // Label 1884: @65278
24805	/ 65278 / GIM_Try_CheckFeatures, /On fail goto//Label 1885/ GIMT_Encode4(`65292`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1120 //
24806	/ 65285 / // (ctlz:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs) => (CLZ_MM:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24807	/ 65285 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::CLZ_MM),
24808	/ 65290 / GIR_RootConstrainSelectedInstOperands,
24809	/ 65291 / // GIR_Coverage, 1120,
24810	/ 65291 / GIR_Done,
24811	/ 65292 / // Label 1885: @65292
24812	/ 65292 / GIM_Reject,
24813	/ 65293 / // Label 1882: @65293
24814	/ 65293 / GIM_Reject,
24815	/ 65294 / // Label 1878: @65294
24816	/ 65294 / GIM_Reject,
24817	/ 65295 / // Label 1872: @65295
24818	/ 65295 / GIM_Try, /On fail goto//Label 1886/ GIMT_Encode4(`65436`),
24819	/ 65300 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24820	/ 65303 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24821	/ 65307 / GIM_Try_CheckFeatures, /On fail goto//Label 1887/ GIMT_Encode4(`65352`), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 291 //
24822	/ 65314 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
24823	/ 65318 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_XOR),
24824	/ 65322 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
24825	/ 65326 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
24826	/ 65330 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24827	/ 65335 / GIM_CheckConstantInt8, /MI/`1`, /Op/`2`, `255`,
24828	/ 65339 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24829	/ 65341 / // (ctlz:{ :[i64] } (xor:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, -1:{ :[i64] })) => (DCLO:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs)
24830	/ 65341 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DCLO),
24831	/ 65344 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24832	/ 65346 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
24833	/ 65350 / GIR_RootConstrainSelectedInstOperands,
24834	/ 65351 / // GIR_Coverage, 291,
24835	/ 65351 / GIR_EraseRootFromParent_Done,
24836	/ 65352 / // Label 1887: @65352
24837	/ 65352 / GIM_Try_CheckFeatures, /On fail goto//Label 1888/ GIMT_Encode4(`65397`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 366 //
24838	/ 65359 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
24839	/ 65363 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_XOR),
24840	/ 65367 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
24841	/ 65371 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
24842	/ 65375 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24843	/ 65380 / GIM_CheckConstantInt8, /MI/`1`, /Op/`2`, `255`,
24844	/ 65384 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
24845	/ 65386 / // (ctlz:{ :[i64] } (xor:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs, -1:{ :[i64] })) => (DCLO_R6:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs)
24846	/ 65386 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DCLO_R6),
24847	/ 65389 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
24848	/ 65391 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // rs
24849	/ 65395 / GIR_RootConstrainSelectedInstOperands,
24850	/ 65396 / // GIR_Coverage, 366,
24851	/ 65396 / GIR_EraseRootFromParent_Done,
24852	/ 65397 / // Label 1888: @65397
24853	/ 65397 / GIM_Try, /On fail goto//Label 1889/ GIMT_Encode4(`65435`),
24854	/ 65402 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24855	/ 65406 / GIM_Try_CheckFeatures, /On fail goto//Label 1890/ GIMT_Encode4(`65420`), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 290 //
24856	/ 65413 / // (ctlz:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs) => (DCLZ:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs)
24857	/ 65413 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DCLZ),
24858	/ 65418 / GIR_RootConstrainSelectedInstOperands,
24859	/ 65419 / // GIR_Coverage, 290,
24860	/ 65419 / GIR_Done,
24861	/ 65420 / // Label 1890: @65420
24862	/ 65420 / GIM_Try_CheckFeatures, /On fail goto//Label 1891/ GIMT_Encode4(`65434`), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 367 //
24863	/ 65427 / // (ctlz:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs) => (DCLZ_R6:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs)
24864	/ 65427 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DCLZ_R6),
24865	/ 65432 / GIR_RootConstrainSelectedInstOperands,
24866	/ 65433 / // GIR_Coverage, 367,
24867	/ 65433 / GIR_Done,
24868	/ 65434 / // Label 1891: @65434
24869	/ 65434 / GIM_Reject,
24870	/ 65435 / // Label 1889: @65435
24871	/ 65435 / GIM_Reject,
24872	/ 65436 / // Label 1886: @65436
24873	/ 65436 / GIM_Reject,
24874	/ 65437 / // Label 1873: @65437
24875	/ 65437 / GIM_Try_CheckFeatures, /On fail goto//Label 1892/ GIMT_Encode4(`65462`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 939 //
24876	/ 65444 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24877	/ 65447 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24878	/ 65451 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24879	/ 65455 / // (ctlz:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws) => (NLZC_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws)
24880	/ 65455 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::NLZC_B),
24881	/ 65460 / GIR_RootConstrainSelectedInstOperands,
24882	/ 65461 / // GIR_Coverage, 939,
24883	/ 65461 / GIR_Done,
24884	/ 65462 / // Label 1892: @65462
24885	/ 65462 / GIM_Reject,
24886	/ 65463 / // Label 1874: @65463
24887	/ 65463 / GIM_Try_CheckFeatures, /On fail goto//Label 1893/ GIMT_Encode4(`65488`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 940 //
24888	/ 65470 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24889	/ 65473 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24890	/ 65477 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24891	/ 65481 / // (ctlz:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws) => (NLZC_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws)
24892	/ 65481 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::NLZC_H),
24893	/ 65486 / GIR_RootConstrainSelectedInstOperands,
24894	/ 65487 / // GIR_Coverage, 940,
24895	/ 65487 / GIR_Done,
24896	/ 65488 / // Label 1893: @65488
24897	/ 65488 / GIM_Reject,
24898	/ 65489 / // Label 1875: @65489
24899	/ 65489 / GIM_Try_CheckFeatures, /On fail goto//Label 1894/ GIMT_Encode4(`65514`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 941 //
24900	/ 65496 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24901	/ 65499 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24902	/ 65503 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24903	/ 65507 / // (ctlz:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws) => (NLZC_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws)
24904	/ 65507 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::NLZC_W),
24905	/ 65512 / GIR_RootConstrainSelectedInstOperands,
24906	/ 65513 / // GIR_Coverage, 941,
24907	/ 65513 / GIR_Done,
24908	/ 65514 / // Label 1894: @65514
24909	/ 65514 / GIM_Reject,
24910	/ 65515 / // Label 1876: @65515
24911	/ 65515 / GIM_Try_CheckFeatures, /On fail goto//Label 1895/ GIMT_Encode4(`65540`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 942 //
24912	/ 65522 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24913	/ 65525 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24914	/ 65529 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24915	/ 65533 / // (ctlz:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws) => (NLZC_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws)
24916	/ 65533 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::NLZC_D),
24917	/ 65538 / GIR_RootConstrainSelectedInstOperands,
24918	/ 65539 / // GIR_Coverage, 942,
24919	/ 65539 / GIR_Done,
24920	/ 65540 / // Label 1895: @65540
24921	/ 65540 / GIM_Reject,
24922	/ 65541 / // Label 1877: @65541
24923	/ 65541 / GIM_Reject,
24924	/ 65542 / // Label 74: @65542
24925	/ 65542 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1902/ GIMT_Encode4(`65741`),
24926	/ 65553 / /GILLT_s32//Label 1896/ GIMT_Encode4(`65585`),
24927	/ 65557 / /GILLT_s64//Label 1897/ GIMT_Encode4(`65611`), GIMT_Encode4(`0`),
24928	/ 65565 / /GILLT_v16s8//Label 1898/ GIMT_Encode4(`65637`), GIMT_Encode4(`0`),
24929	/ 65573 / /GILLT_v8s16//Label 1899/ GIMT_Encode4(`65663`),
24930	/ 65577 / /GILLT_v4s32//Label 1900/ GIMT_Encode4(`65689`),
24931	/ 65581 / /GILLT_v2s64//Label 1901/ GIMT_Encode4(`65715`),
24932	/ 65585 / // Label 1896: @65585
24933	/ 65585 / GIM_Try_CheckFeatures, /On fail goto//Label 1903/ GIMT_Encode4(`65610`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 305 //
24934	/ 65592 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
24935	/ 65595 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24936	/ 65599 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
24937	/ 65603 / // (ctpop:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs) => (POP:{ :[i32] } GPR32Opnd:{ :[i32] }:$rs)
24938	/ 65603 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::POP),
24939	/ 65608 / GIR_RootConstrainSelectedInstOperands,
24940	/ 65609 / // GIR_Coverage, 305,
24941	/ 65609 / GIR_Done,
24942	/ 65610 / // Label 1903: @65610
24943	/ 65610 / GIM_Reject,
24944	/ 65611 / // Label 1897: @65611
24945	/ 65611 / GIM_Try_CheckFeatures, /On fail goto//Label 1904/ GIMT_Encode4(`65636`), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 306 //
24946	/ 65618 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
24947	/ 65621 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24948	/ 65625 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
24949	/ 65629 / // (ctpop:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs) => (DPOP:{ :[i64] } GPR64Opnd:{ :[i64] }:$rs)
24950	/ 65629 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::DPOP),
24951	/ 65634 / GIR_RootConstrainSelectedInstOperands,
24952	/ 65635 / // GIR_Coverage, 306,
24953	/ 65635 / GIR_Done,
24954	/ 65636 / // Label 1904: @65636
24955	/ 65636 / GIM_Reject,
24956	/ 65637 / // Label 1898: @65637
24957	/ 65637 / GIM_Try_CheckFeatures, /On fail goto//Label 1905/ GIMT_Encode4(`65662`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 961 //
24958	/ 65644 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v16s8,
24959	/ 65647 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24960	/ 65651 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128BRegClassID),
24961	/ 65655 / // (ctpop:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws) => (PCNT_B:{ :[v16i8] } MSA128BOpnd:{ :[v16i8] }:$ws)
24962	/ 65655 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PCNT_B),
24963	/ 65660 / GIR_RootConstrainSelectedInstOperands,
24964	/ 65661 / // GIR_Coverage, 961,
24965	/ 65661 / GIR_Done,
24966	/ 65662 / // Label 1905: @65662
24967	/ 65662 / GIM_Reject,
24968	/ 65663 / // Label 1899: @65663
24969	/ 65663 / GIM_Try_CheckFeatures, /On fail goto//Label 1906/ GIMT_Encode4(`65688`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 962 //
24970	/ 65670 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v8s16,
24971	/ 65673 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24972	/ 65677 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128HRegClassID),
24973	/ 65681 / // (ctpop:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws) => (PCNT_H:{ :[v8i16] } MSA128HOpnd:{ :[v8i16] }:$ws)
24974	/ 65681 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PCNT_H),
24975	/ 65686 / GIR_RootConstrainSelectedInstOperands,
24976	/ 65687 / // GIR_Coverage, 962,
24977	/ 65687 / GIR_Done,
24978	/ 65688 / // Label 1906: @65688
24979	/ 65688 / GIM_Reject,
24980	/ 65689 / // Label 1900: @65689
24981	/ 65689 / GIM_Try_CheckFeatures, /On fail goto//Label 1907/ GIMT_Encode4(`65714`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 963 //
24982	/ 65696 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
24983	/ 65699 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24984	/ 65703 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
24985	/ 65707 / // (ctpop:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws) => (PCNT_W:{ :[v4i32] } MSA128WOpnd:{ :[v4i32] }:$ws)
24986	/ 65707 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PCNT_W),
24987	/ 65712 / GIR_RootConstrainSelectedInstOperands,
24988	/ 65713 / // GIR_Coverage, 963,
24989	/ 65713 / GIR_Done,
24990	/ 65714 / // Label 1907: @65714
24991	/ 65714 / GIM_Reject,
24992	/ 65715 / // Label 1901: @65715
24993	/ 65715 / GIM_Try_CheckFeatures, /On fail goto//Label 1908/ GIMT_Encode4(`65740`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 964 //
24994	/ 65722 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
24995	/ 65725 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24996	/ 65729 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
24997	/ 65733 / // (ctpop:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws) => (PCNT_D:{ :[v2i64] } MSA128DOpnd:{ :[v2i64] }:$ws)
24998	/ 65733 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::PCNT_D),
24999	/ 65738 / GIR_RootConstrainSelectedInstOperands,
25000	/ 65739 / // GIR_Coverage, 964,
25001	/ 65739 / GIR_Done,
25002	/ 65740 / // Label 1908: @65740
25003	/ 65740 / GIM_Reject,
25004	/ 65741 / // Label 1902: @65741
25005	/ 65741 / GIM_Reject,
25006	/ 65742 / // Label 75: @65742
25007	/ 65742 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1911/ GIMT_Encode4(`65902`),
25008	/ 65753 / /GILLT_s32//Label 1909/ GIMT_Encode4(`65761`),
25009	/ 65757 / /GILLT_s64//Label 1910/ GIMT_Encode4(`65855`),
25010	/ 65761 / // Label 1909: @65761
25011	/ 65761 / GIM_Try, /On fail goto//Label 1912/ GIMT_Encode4(`65854`),
25012	/ 65766 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25013	/ 65769 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
25014	/ 65773 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR32RegClassID),
25015	/ 65777 / GIM_Try_CheckFeatures, /On fail goto//Label 1913/ GIMT_Encode4(`65815`), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 1448 //
25016	/ 65784 / // (bswap:{ :[i32] } GPR32:{ :[i32] }:$rt) => (ROTR:{ :[i32] } (WSBH:{ :[i32] } GPR32:{ :[i32] }:$rt), 16:{ :[i32] })
25017	/ 65784 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
25018	/ 65787 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::WSBH),
25019	/ 65791 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25020	/ 65796 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // rt
25021	/ 65800 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
25022	/ 65802 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ROTR),
25023	/ 65805 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
25024	/ 65807 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
25025	/ 65810 / GIR_AddImm8, /InsnID/`0`, /Imm/`16`,
25026	/ 65813 / GIR_RootConstrainSelectedInstOperands,
25027	/ 65814 / // GIR_Coverage, 1448,
25028	/ 65814 / GIR_EraseRootFromParent_Done,
25029	/ 65815 / // Label 1913: @65815
25030	/ 65815 / GIM_Try_CheckFeatures, /On fail goto//Label 1914/ GIMT_Encode4(`65853`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2316 //
25031	/ 65822 / // (bswap:{ :[i32] } GPR32:{ :[i32] }:$rt) => (ROTR_MM:{ :[i32] } (WSBH_MM:{ :[i32] } GPR32:{ :[i32] }:$rt), 16:{ :[i32] })
25032	/ 65822 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s32,
25033	/ 65825 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::WSBH_MM),
25034	/ 65829 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25035	/ 65834 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // rt
25036	/ 65838 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
25037	/ 65840 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::ROTR_MM),
25038	/ 65843 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
25039	/ 65845 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
25040	/ 65848 / GIR_AddImm8, /InsnID/`0`, /Imm/`16`,
25041	/ 65851 / GIR_RootConstrainSelectedInstOperands,
25042	/ 65852 / // GIR_Coverage, 2316,
25043	/ 65852 / GIR_EraseRootFromParent_Done,
25044	/ 65853 / // Label 1914: @65853
25045	/ 65853 / GIM_Reject,
25046	/ 65854 / // Label 1912: @65854
25047	/ 65854 / GIM_Reject,
25048	/ 65855 / // Label 1910: @65855
25049	/ 65855 / GIM_Try_CheckFeatures, /On fail goto//Label 1915/ GIMT_Encode4(`65901`), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc), // Rule ID 1692 //
25050	/ 65862 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25051	/ 65865 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
25052	/ 65869 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::GPR64RegClassID),
25053	/ 65873 / // (bswap:{ :[i64] } GPR64:{ :[i64] }:$rt) => (DSHD:{ :[i64] } (DSBH:{ :[i64] } GPR64:{ :[i64] }:$rt))*
25054	/ 65873 / GIR_MakeTempReg, /TempRegID/`0`, /TypeID/GILLT_s64,
25055	/ 65876 / GIR_BuildMI, /InsnID/`1`, /Opcode/GIMT_Encode2(Mips::DSBH),
25056	/ 65880 / GIR_AddTempRegister, /InsnID/`1`, /TempRegID/`0`, /TempRegFlags/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25057	/ 65885 / GIR_Copy, /NewInsnID/`1`, /OldInsnID/`0`, /OpIdx/`1`, // rt
25058	/ 65889 / GIR_ConstrainSelectedInstOperands, /InsnID/`1`,
25059	/ 65891 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::DSHD),
25060	/ 65894 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[rd]
25061	/ 65896 / GIR_AddSimpleTempRegister, /InsnID/`0`, /TempRegID/`0`,
25062	/ 65899 / GIR_RootConstrainSelectedInstOperands,
25063	/ 65900 / // GIR_Coverage, 1692,
25064	/ 65900 / GIR_EraseRootFromParent_Done,
25065	/ 65901 / // Label 1915: @65901
25066	/ 65901 / GIM_Reject,
25067	/ 65902 / // Label 1911: @65902
25068	/ 65902 / GIM_Reject,
25069	/ 65903 / // Label 76: @65903
25070	/ 65903 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`8`), /)//default://Label 1920/ GIMT_Encode4(`66166`),
25071	/ 65914 / /GILLT_s32//Label 1916/ GIMT_Encode4(`65946`),
25072	/ 65918 / /GILLT_s64//Label 1917/ GIMT_Encode4(`66000`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`), GIMT_Encode4(`0`),
25073	/ 65938 / /GILLT_v4s32//Label 1918/ GIMT_Encode4(`66114`),
25074	/ 65942 / /GILLT_v2s64//Label 1919/ GIMT_Encode4(`66140`),
25075	/ 65946 / // Label 1916: @65946
25076	/ 65946 / GIM_Try, /On fail goto//Label 1921/ GIMT_Encode4(`65999`),
25077	/ 65951 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25078	/ 65954 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25079	/ 65958 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25080	/ 65962 / GIM_Try_CheckFeatures, /On fail goto//Label 1922/ GIMT_Encode4(`65980`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 133 //
25081	/ 65969 / // (fsqrt:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FSQRT_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
25082	/ 65969 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_S),
25083	/ 65974 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25084	/ 65978 / GIR_RootConstrainSelectedInstOperands,
25085	/ 65979 / // GIR_Coverage, 133,
25086	/ 65979 / GIR_Done,
25087	/ 65980 / // Label 1922: @65980
25088	/ 65980 / GIM_Try_CheckFeatures, /On fail goto//Label 1923/ GIMT_Encode4(`65998`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1183 //
25089	/ 65987 / // (fsqrt:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FSQRT_S_MM:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
25090	/ 65987 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_S_MM),
25091	/ 65992 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25092	/ 65996 / GIR_RootConstrainSelectedInstOperands,
25093	/ 65997 / // GIR_Coverage, 1183,
25094	/ 65997 / GIR_Done,
25095	/ 65998 / // Label 1923: @65998
25096	/ 65998 / GIM_Reject,
25097	/ 65999 / // Label 1921: @65999
25098	/ 65999 / GIM_Reject,
25099	/ 66000 / // Label 1917: @66000
25100	/ 66000 / GIM_Try, /On fail goto//Label 1924/ GIMT_Encode4(`66113`),
25101	/ 66005 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25102	/ 66008 / GIM_Try_CheckFeatures, /On fail goto//Label 1925/ GIMT_Encode4(`66034`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 135 //
25103	/ 66015 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25104	/ 66019 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25105	/ 66023 / // (fsqrt:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
25106	/ 66023 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D32),
25107	/ 66028 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25108	/ 66032 / GIR_RootConstrainSelectedInstOperands,
25109	/ 66033 / // GIR_Coverage, 135,
25110	/ 66033 / GIR_Done,
25111	/ 66034 / // Label 1925: @66034
25112	/ 66034 / GIM_Try_CheckFeatures, /On fail goto//Label 1926/ GIMT_Encode4(`66060`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 137 //
25113	/ 66041 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25114	/ 66045 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25115	/ 66049 / // (fsqrt:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
25116	/ 66049 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D64),
25117	/ 66054 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25118	/ 66058 / GIR_RootConstrainSelectedInstOperands,
25119	/ 66059 / // GIR_Coverage, 137,
25120	/ 66059 / GIR_Done,
25121	/ 66060 / // Label 1926: @66060
25122	/ 66060 / GIM_Try_CheckFeatures, /On fail goto//Label 1927/ GIMT_Encode4(`66086`), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1169 //
25123	/ 66067 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25124	/ 66071 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25125	/ 66075 / // (fsqrt:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D32_MM:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
25126	/ 66075 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D32_MM),
25127	/ 66080 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25128	/ 66084 / GIR_RootConstrainSelectedInstOperands,
25129	/ 66085 / // GIR_Coverage, 1169,
25130	/ 66085 / GIR_Done,
25131	/ 66086 / // Label 1927: @66086
25132	/ 66086 / GIM_Try_CheckFeatures, /On fail goto//Label 1928/ GIMT_Encode4(`66112`), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1170 //
25133	/ 66093 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25134	/ 66097 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25135	/ 66101 / // (fsqrt:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D64_MM:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
25136	/ 66101 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D64_MM),
25137	/ 66106 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25138	/ 66110 / GIR_RootConstrainSelectedInstOperands,
25139	/ 66111 / // GIR_Coverage, 1170,
25140	/ 66111 / GIR_Done,
25141	/ 66112 / // Label 1928: @66112
25142	/ 66112 / GIM_Reject,
25143	/ 66113 / // Label 1924: @66113
25144	/ 66113 / GIM_Reject,
25145	/ 66114 / // Label 1918: @66114
25146	/ 66114 / GIM_Try_CheckFeatures, /On fail goto//Label 1929/ GIMT_Encode4(`66139`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 783 //
25147	/ 66121 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
25148	/ 66124 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
25149	/ 66128 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
25150	/ 66132 / // (fsqrt:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FSQRT_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)
25151	/ 66132 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_W),
25152	/ 66137 / GIR_RootConstrainSelectedInstOperands,
25153	/ 66138 / // GIR_Coverage, 783,
25154	/ 66138 / GIR_Done,
25155	/ 66139 / // Label 1929: @66139
25156	/ 66139 / GIM_Reject,
25157	/ 66140 / // Label 1919: @66140
25158	/ 66140 / GIM_Try_CheckFeatures, /On fail goto//Label 1930/ GIMT_Encode4(`66165`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 784 //
25159	/ 66147 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
25160	/ 66150 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
25161	/ 66154 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
25162	/ 66158 / // (fsqrt:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FSQRT_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)
25163	/ 66158 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D),
25164	/ 66163 / GIR_RootConstrainSelectedInstOperands,
25165	/ 66164 / // GIR_Coverage, 784,
25166	/ 66164 / GIR_Done,
25167	/ 66165 / // Label 1930: @66165
25168	/ 66165 / GIM_Reject,
25169	/ 66166 / // Label 1920: @66166
25170	/ 66166 / GIM_Reject,
25171	/ 66167 / // Label 77: @66167
25172	/ 66167 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`6`), GIMT_Encode2(`8`), /)//default://Label 1933/ GIMT_Encode4(`66238`),
25173	/ 66178 / /GILLT_v4s32//Label 1931/ GIMT_Encode4(`66186`),
25174	/ 66182 / /GILLT_v2s64//Label 1932/ GIMT_Encode4(`66212`),
25175	/ 66186 / // Label 1931: @66186
25176	/ 66186 / GIM_Try_CheckFeatures, /On fail goto//Label 1934/ GIMT_Encode4(`66211`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 765 //
25177	/ 66193 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v4s32,
25178	/ 66196 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
25179	/ 66200 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128WRegClassID),
25180	/ 66204 / // (frint:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws) => (FRINT_W:{ :[v4f32] } MSA128WOpnd:{ :[v4f32] }:$ws)
25181	/ 66204 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FRINT_W),
25182	/ 66209 / GIR_RootConstrainSelectedInstOperands,
25183	/ 66210 / // GIR_Coverage, 765,
25184	/ 66210 / GIR_Done,
25185	/ 66211 / // Label 1934: @66211
25186	/ 66211 / GIM_Reject,
25187	/ 66212 / // Label 1932: @66212
25188	/ 66212 / GIM_Try_CheckFeatures, /On fail goto//Label 1935/ GIMT_Encode4(`66237`), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 766 //
25189	/ 66219 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_v2s64,
25190	/ 66222 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
25191	/ 66226 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::MSA128DRegClassID),
25192	/ 66230 / // (frint:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws) => (FRINT_D:{ :[v2f64] } MSA128DOpnd:{ :[v2f64] }:$ws)
25193	/ 66230 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FRINT_D),
25194	/ 66235 / GIR_RootConstrainSelectedInstOperands,
25195	/ 66236 / // GIR_Coverage, 766,
25196	/ 66236 / GIR_Done,
25197	/ 66237 / // Label 1935: @66237
25198	/ 66237 / GIM_Reject,
25199	/ 66238 / // Label 1933: @66238
25200	/ 66238 / GIM_Reject,
25201	/ 66239 / // Label 78: @66239
25202	/ 66239 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1938/ GIMT_Encode4(`67078`),
25203	/ 66250 / /GILLT_s32//Label 1936/ GIMT_Encode4(`66258`),
25204	/ 66254 / /GILLT_s64//Label 1937/ GIMT_Encode4(`66525`),
25205	/ 66258 / // Label 1936: @66258
25206	/ 66258 / GIM_Try, /On fail goto//Label 1939/ GIMT_Encode4(`66524`),
25207	/ 66263 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25208	/ 66266 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
25209	/ 66269 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25210	/ 66273 / GIM_Try, /On fail goto//Label 1940/ GIMT_Encode4(`66387`),
25211	/ 66278 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25212	/ 66282 / GIM_Try_CheckFeatures, /On fail goto//Label 1941/ GIMT_Encode4(`66334`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 179 //
25213	/ 66289 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25214	/ 66293 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25215	/ 66297 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25216	/ 66301 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25217	/ 66305 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25218	/ 66310 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25219	/ 66315 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25220	/* 66317 / // (strict_fadd:{ :[f32] } (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25221	/ 66317 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
25222	/ 66320 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25223	/ 66322 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25224	/ 66324 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25225	/ 66328 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25226	/ 66332 / GIR_RootConstrainSelectedInstOperands,
25227	/ 66333 / // GIR_Coverage, 179,
25228	/ 66333 / GIR_EraseRootFromParent_Done,
25229	/ 66334 / // Label 1941: @66334
25230	/ 66334 / GIM_Try_CheckFeatures, /On fail goto//Label 1942/ GIMT_Encode4(`66386`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 178 //
25231	/ 66341 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25232	/ 66345 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25233	/ 66349 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25234	/ 66353 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25235	/ 66357 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25236	/ 66362 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25237	/ 66367 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25238	/* 66369 / // (strict_fadd:{ :[f32] } (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25239	/ 66369 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
25240	/ 66372 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25241	/ 66374 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25242	/ 66376 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25243	/ 66380 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25244	/ 66384 / GIR_RootConstrainSelectedInstOperands,
25245	/ 66385 / // GIR_Coverage, 178,
25246	/ 66385 / GIR_EraseRootFromParent_Done,
25247	/ 66386 / // Label 1942: @66386
25248	/ 66386 / GIM_Reject,
25249	/ 66387 / // Label 1940: @66387
25250	/ 66387 / GIM_Try, /On fail goto//Label 1943/ GIMT_Encode4(`66523`),
25251	/ 66392 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25252	/ 66396 / GIM_Try_CheckFeatures, /On fail goto//Label 1944/ GIMT_Encode4(`66448`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2487 //
25253	/ 66403 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25254	/ 66407 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25255	/ 66411 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25256	/ 66415 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25257	/ 66419 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25258	/ 66424 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25259	/ 66429 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25260	/* 66431 / // (strict_fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25261	/ 66431 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
25262	/ 66434 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25263	/ 66436 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25264	/ 66438 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25265	/ 66442 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25266	/ 66446 / GIR_RootConstrainSelectedInstOperands,
25267	/ 66447 / // GIR_Coverage, 2487,
25268	/ 66447 / GIR_EraseRootFromParent_Done,
25269	/ 66448 / // Label 1944: @66448
25270	/ 66448 / GIM_Try_CheckFeatures, /On fail goto//Label 1945/ GIMT_Encode4(`66500`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2486 //
25271	/ 66455 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25272	/ 66459 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25273	/ 66463 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25274	/ 66467 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25275	/ 66471 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25276	/ 66476 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25277	/ 66481 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25278	/* 66483 / // (strict_fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)) => (MADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25279	/ 66483 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_S),
25280	/ 66486 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25281	/ 66488 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25282	/ 66490 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25283	/ 66494 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25284	/ 66498 / GIR_RootConstrainSelectedInstOperands,
25285	/ 66499 / // GIR_Coverage, 2486,
25286	/ 66499 / GIR_EraseRootFromParent_Done,
25287	/ 66500 / // Label 1945: @66500
25288	/ 66500 / GIM_Try_CheckFeatures, /On fail goto//Label 1946/ GIMT_Encode4(`66522`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 154 //
25289	/ 66507 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25290	/ 66511 / // (strict_fadd:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FADD_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25291	/ 66511 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_S),
25292	/ 66516 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25293	/ 66520 / GIR_RootConstrainSelectedInstOperands,
25294	/ 66521 / // GIR_Coverage, 154,
25295	/ 66521 / GIR_Done,
25296	/ 66522 / // Label 1946: @66522
25297	/ 66522 / GIM_Reject,
25298	/ 66523 / // Label 1943: @66523
25299	/ 66523 / GIM_Reject,
25300	/ 66524 / // Label 1939: @66524
25301	/ 66524 / GIM_Reject,
25302	/ 66525 / // Label 1937: @66525
25303	/ 66525 / GIM_Try, /On fail goto//Label 1947/ GIMT_Encode4(`67077`),
25304	/ 66530 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25305	/ 66533 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
25306	/ 66536 / GIM_Try_CheckFeatures, /On fail goto//Label 1948/ GIMT_Encode4(`66596`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 187 //
25307	/ 66543 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25308	/ 66547 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25309	/ 66551 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25310	/ 66555 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25311	/ 66559 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25312	/ 66563 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25313	/ 66568 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25314	/ 66573 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25315	/ 66577 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25316	/* 66579 / // (strict_fadd:{ :[f64] } (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25317	/ 66579 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
25318	/ 66582 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25319	/ 66584 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25320	/ 66586 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25321	/ 66590 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25322	/ 66594 / GIR_RootConstrainSelectedInstOperands,
25323	/ 66595 / // GIR_Coverage, 187,
25324	/ 66595 / GIR_EraseRootFromParent_Done,
25325	/ 66596 / // Label 1948: @66596
25326	/ 66596 / GIM_Try_CheckFeatures, /On fail goto//Label 1949/ GIMT_Encode4(`66656`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 195 //
25327	/ 66603 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25328	/ 66607 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25329	/ 66611 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25330	/ 66615 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25331	/ 66619 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25332	/ 66623 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25333	/ 66628 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25334	/ 66633 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25335	/ 66637 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25336	/* 66639 / // (strict_fadd:{ :[f64] } (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25337	/ 66639 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
25338	/ 66642 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25339	/ 66644 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25340	/ 66646 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25341	/ 66650 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25342	/ 66654 / GIR_RootConstrainSelectedInstOperands,
25343	/ 66655 / // GIR_Coverage, 195,
25344	/ 66655 / GIR_EraseRootFromParent_Done,
25345	/ 66656 / // Label 1949: @66656
25346	/ 66656 / GIM_Try_CheckFeatures, /On fail goto//Label 1950/ GIMT_Encode4(`66716`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 186 //
25347	/ 66663 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25348	/ 66667 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25349	/ 66671 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25350	/ 66675 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25351	/ 66679 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25352	/ 66683 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25353	/ 66688 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25354	/ 66693 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25355	/ 66697 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25356	/* 66699 / // (strict_fadd:{ :[f64] } (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25357	/ 66699 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
25358	/ 66702 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25359	/ 66704 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25360	/ 66706 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25361	/ 66710 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25362	/ 66714 / GIR_RootConstrainSelectedInstOperands,
25363	/ 66715 / // GIR_Coverage, 186,
25364	/ 66715 / GIR_EraseRootFromParent_Done,
25365	/ 66716 / // Label 1950: @66716
25366	/ 66716 / GIM_Try_CheckFeatures, /On fail goto//Label 1951/ GIMT_Encode4(`66776`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 194 //
25367	/ 66723 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25368	/ 66727 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25369	/ 66731 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25370	/ 66735 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25371	/ 66739 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25372	/ 66743 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25373	/ 66748 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25374	/ 66753 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25375	/ 66757 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25376	/* 66759 / // (strict_fadd:{ :[f64] } (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25377	/ 66759 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
25378	/ 66762 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25379	/ 66764 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25380	/ 66766 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25381	/ 66770 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25382	/ 66774 / GIR_RootConstrainSelectedInstOperands,
25383	/ 66775 / // GIR_Coverage, 194,
25384	/ 66775 / GIR_EraseRootFromParent_Done,
25385	/ 66776 / // Label 1951: @66776
25386	/ 66776 / GIM_Try_CheckFeatures, /On fail goto//Label 1952/ GIMT_Encode4(`66836`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2491 //
25387	/ 66783 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25388	/ 66787 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25389	/ 66791 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25390	/ 66795 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25391	/ 66799 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25392	/ 66803 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25393	/ 66807 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25394	/ 66812 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25395	/ 66817 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25396	/* 66819 / // (strict_fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25397	/ 66819 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
25398	/ 66822 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25399	/ 66824 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25400	/ 66826 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25401	/ 66830 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25402	/ 66834 / GIR_RootConstrainSelectedInstOperands,
25403	/ 66835 / // GIR_Coverage, 2491,
25404	/ 66835 / GIR_EraseRootFromParent_Done,
25405	/ 66836 / // Label 1952: @66836
25406	/ 66836 / GIM_Try_CheckFeatures, /On fail goto//Label 1953/ GIMT_Encode4(`66896`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2495 //
25407	/ 66843 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25408	/ 66847 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25409	/ 66851 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25410	/ 66855 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25411	/ 66859 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25412	/ 66863 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25413	/ 66867 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25414	/ 66872 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25415	/ 66877 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25416	/* 66879 / // (strict_fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25417	/ 66879 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
25418	/ 66882 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25419	/ 66884 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25420	/ 66886 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25421	/ 66890 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25422	/ 66894 / GIR_RootConstrainSelectedInstOperands,
25423	/ 66895 / // GIR_Coverage, 2495,
25424	/ 66895 / GIR_EraseRootFromParent_Done,
25425	/ 66896 / // Label 1953: @66896
25426	/ 66896 / GIM_Try_CheckFeatures, /On fail goto//Label 1954/ GIMT_Encode4(`66956`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2490 //
25427	/ 66903 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25428	/ 66907 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25429	/ 66911 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25430	/ 66915 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25431	/ 66919 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25432	/ 66923 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25433	/ 66927 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25434	/ 66932 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25435	/ 66937 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25436	/* 66939 / // (strict_fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)) => (MADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25437	/ 66939 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D32),
25438	/ 66942 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25439	/ 66944 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25440	/ 66946 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25441	/ 66950 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25442	/ 66954 / GIR_RootConstrainSelectedInstOperands,
25443	/ 66955 / // GIR_Coverage, 2490,
25444	/ 66955 / GIR_EraseRootFromParent_Done,
25445	/ 66956 / // Label 1954: @66956
25446	/ 66956 / GIM_Try_CheckFeatures, /On fail goto//Label 1955/ GIMT_Encode4(`67016`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2494 //
25447	/ 66963 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25448	/ 66967 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25449	/ 66971 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`2`, // MIs[1]
25450	/ 66975 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25451	/ 66979 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25452	/ 66983 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25453	/ 66987 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25454	/ 66992 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25455	/ 66997 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25456	/* 66999 / // (strict_fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)) => (MADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25457	/ 66999 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MADD_D64),
25458	/ 67002 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25459	/ 67004 / GIR_RootToRootCopy, /OpIdx/`1`, // fr
25460	/ 67006 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25461	/ 67010 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25462	/ 67014 / GIR_RootConstrainSelectedInstOperands,
25463	/ 67015 / // GIR_Coverage, 2494,
25464	/ 67015 / GIR_EraseRootFromParent_Done,
25465	/ 67016 / // Label 1955: @67016
25466	/ 67016 / GIM_Try_CheckFeatures, /On fail goto//Label 1956/ GIMT_Encode4(`67046`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 156 //
25467	/ 67023 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25468	/ 67027 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25469	/ 67031 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25470	/ 67035 / // (strict_fadd:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FADD_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25471	/ 67035 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D32),
25472	/ 67040 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25473	/ 67044 / GIR_RootConstrainSelectedInstOperands,
25474	/ 67045 / // GIR_Coverage, 156,
25475	/ 67045 / GIR_Done,
25476	/ 67046 / // Label 1956: @67046
25477	/ 67046 / GIM_Try_CheckFeatures, /On fail goto//Label 1957/ GIMT_Encode4(`67076`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 158 //
25478	/ 67053 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25479	/ 67057 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25480	/ 67061 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25481	/ 67065 / // (strict_fadd:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FADD_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25482	/ 67065 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FADD_D64),
25483	/ 67070 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25484	/ 67074 / GIR_RootConstrainSelectedInstOperands,
25485	/ 67075 / // GIR_Coverage, 158,
25486	/ 67075 / GIR_Done,
25487	/ 67076 / // Label 1957: @67076
25488	/ 67076 / GIM_Reject,
25489	/ 67077 / // Label 1947: @67077
25490	/ 67077 / GIM_Reject,
25491	/ 67078 / // Label 1938: @67078
25492	/ 67078 / GIM_Reject,
25493	/ 67079 / // Label 79: @67079
25494	/ 67079 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1960/ GIMT_Encode4(`67568`),
25495	/ 67090 / /GILLT_s32//Label 1958/ GIMT_Encode4(`67098`),
25496	/ 67094 / /GILLT_s64//Label 1959/ GIMT_Encode4(`67255`),
25497	/ 67098 / // Label 1958: @67098
25498	/ 67098 / GIM_Try, /On fail goto//Label 1961/ GIMT_Encode4(`67254`),
25499	/ 67103 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25500	/ 67106 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
25501	/ 67109 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25502	/ 67113 / GIM_Try, /On fail goto//Label 1962/ GIMT_Encode4(`67227`),
25503	/ 67118 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25504	/ 67122 / GIM_Try_CheckFeatures, /On fail goto//Label 1963/ GIMT_Encode4(`67174`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 183 //
25505	/ 67129 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25506	/ 67133 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25507	/ 67137 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25508	/ 67141 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25509	/ 67145 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25510	/ 67150 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25511	/ 67155 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25512	/* 67157 / // (strict_fsub:{ :[f32] } (fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25513	/ 67157 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_S),
25514	/ 67160 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25515	/ 67162 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25516	/ 67164 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25517	/ 67168 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25518	/ 67172 / GIR_RootConstrainSelectedInstOperands,
25519	/ 67173 / // GIR_Coverage, 183,
25520	/ 67173 / GIR_EraseRootFromParent_Done,
25521	/ 67174 / // Label 1963: @67174
25522	/ 67174 / GIM_Try_CheckFeatures, /On fail goto//Label 1964/ GIMT_Encode4(`67226`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 182 //
25523	/ 67181 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25524	/ 67185 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25525	/ 67189 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s32,
25526	/ 67193 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s32,
25527	/ 67197 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25528	/ 67202 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25529	/ 67207 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25530	/* 67209 / // (strict_fsub:{ :[f32] } (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft), FGR32Opnd:{ :[f32] }:$fr) => (MSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fr, FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25531	/ 67209 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_S),
25532	/ 67212 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25533	/ 67214 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25534	/ 67216 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25535	/ 67220 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25536	/ 67224 / GIR_RootConstrainSelectedInstOperands,
25537	/ 67225 / // GIR_Coverage, 182,
25538	/ 67225 / GIR_EraseRootFromParent_Done,
25539	/ 67226 / // Label 1964: @67226
25540	/ 67226 / GIM_Reject,
25541	/ 67227 / // Label 1962: @67227
25542	/ 67227 / GIM_Try_CheckFeatures, /On fail goto//Label 1965/ GIMT_Encode4(`67253`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 172 //
25543	/ 67234 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25544	/ 67238 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25545	/ 67242 / // (strict_fsub:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FSUB_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25546	/ 67242 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_S),
25547	/ 67247 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25548	/ 67251 / GIR_RootConstrainSelectedInstOperands,
25549	/ 67252 / // GIR_Coverage, 172,
25550	/ 67252 / GIR_Done,
25551	/ 67253 / // Label 1965: @67253
25552	/ 67253 / GIM_Reject,
25553	/ 67254 / // Label 1961: @67254
25554	/ 67254 / GIM_Reject,
25555	/ 67255 / // Label 1959: @67255
25556	/ 67255 / GIM_Try, /On fail goto//Label 1966/ GIMT_Encode4(`67567`),
25557	/ 67260 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25558	/ 67263 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
25559	/ 67266 / GIM_Try_CheckFeatures, /On fail goto//Label 1967/ GIMT_Encode4(`67326`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 191 //
25560	/ 67273 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25561	/ 67277 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25562	/ 67281 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25563	/ 67285 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25564	/ 67289 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25565	/ 67293 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25566	/ 67298 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25567	/ 67303 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25568	/ 67307 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25569	/* 67309 / // (strict_fsub:{ :[f64] } (fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25570	/ 67309 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D32),
25571	/ 67312 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25572	/ 67314 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25573	/ 67316 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25574	/ 67320 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25575	/ 67324 / GIR_RootConstrainSelectedInstOperands,
25576	/ 67325 / // GIR_Coverage, 191,
25577	/ 67325 / GIR_EraseRootFromParent_Done,
25578	/ 67326 / // Label 1967: @67326
25579	/ 67326 / GIM_Try_CheckFeatures, /On fail goto//Label 1968/ GIMT_Encode4(`67386`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 199 //
25580	/ 67333 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25581	/ 67337 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25582	/ 67341 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_FMUL),
25583	/ 67345 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25584	/ 67349 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25585	/ 67353 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25586	/ 67358 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25587	/ 67363 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25588	/ 67367 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25589	/* 67369 / // (strict_fsub:{ :[f64] } (fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25590	/ 67369 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D64),
25591	/ 67372 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25592	/ 67374 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25593	/ 67376 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25594	/ 67380 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25595	/ 67384 / GIR_RootConstrainSelectedInstOperands,
25596	/ 67385 / // GIR_Coverage, 199,
25597	/ 67385 / GIR_EraseRootFromParent_Done,
25598	/ 67386 / // Label 1968: @67386
25599	/ 67386 / GIM_Try_CheckFeatures, /On fail goto//Label 1969/ GIMT_Encode4(`67446`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 190 //
25600	/ 67393 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25601	/ 67397 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25602	/ 67401 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25603	/ 67405 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25604	/ 67409 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25605	/ 67413 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25606	/ 67418 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25607	/ 67423 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25608	/ 67427 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25609	/* 67429 / // (strict_fsub:{ :[f64] } (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft), AFGR64Opnd:{ :[f64] }:$fr) => (MSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fr, AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25610	/ 67429 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D32),
25611	/ 67432 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25612	/ 67434 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25613	/ 67436 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25614	/ 67440 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25615	/ 67444 / GIR_RootConstrainSelectedInstOperands,
25616	/ 67445 / // GIR_Coverage, 190,
25617	/ 67445 / GIR_EraseRootFromParent_Done,
25618	/ 67446 / // Label 1969: @67446
25619	/ 67446 / GIM_Try_CheckFeatures, /On fail goto//Label 1970/ GIMT_Encode4(`67506`), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 198 //
25620	/ 67453 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25621	/ 67457 / GIM_RecordInsn, /DefineMI/`1`, /MI/`0`, /OpIdx/`1`, // MIs[1]
25622	/ 67461 / GIM_CheckOpcode, /MI/`1`, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25623	/ 67465 / GIM_CheckType, /MI/`1`, /Op/`1`, /Type/GILLT_s64,
25624	/ 67469 / GIM_CheckType, /MI/`1`, /Op/`2`, /Type/GILLT_s64,
25625	/ 67473 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25626	/ 67478 / GIM_CheckRegBankForClass, /MI/`1`, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25627	/ 67483 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25628	/ 67487 / GIM_CheckIsSafeToFold, /NumInsns/`1`,
25629	/* 67489 / // (strict_fsub:{ :[f64] } (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft), FGR64Opnd:{ :[f64] }:$fr) => (MSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fr, FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25630	/ 67489 / GIR_BuildRootMI, /Opcode/GIMT_Encode2(Mips::MSUB_D64),
25631	/ 67492 / GIR_RootToRootCopy, /OpIdx/`0`, // DstI[fd]
25632	/ 67494 / GIR_RootToRootCopy, /OpIdx/`2`, // fr
25633	/ 67496 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`1`, // fs
25634	/ 67500 / GIR_Copy, /NewInsnID/`0`, /OldInsnID/`1`, /OpIdx/`2`, // ft
25635	/ 67504 / GIR_RootConstrainSelectedInstOperands,
25636	/ 67505 / // GIR_Coverage, 198,
25637	/ 67505 / GIR_EraseRootFromParent_Done,
25638	/ 67506 / // Label 1970: @67506
25639	/ 67506 / GIM_Try_CheckFeatures, /On fail goto//Label 1971/ GIMT_Encode4(`67536`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 174 //
25640	/ 67513 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25641	/ 67517 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25642	/ 67521 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25643	/ 67525 / // (strict_fsub:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FSUB_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25644	/ 67525 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D32),
25645	/ 67530 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25646	/ 67534 / GIR_RootConstrainSelectedInstOperands,
25647	/ 67535 / // GIR_Coverage, 174,
25648	/ 67535 / GIR_Done,
25649	/ 67536 / // Label 1971: @67536
25650	/ 67536 / GIM_Try_CheckFeatures, /On fail goto//Label 1972/ GIMT_Encode4(`67566`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 176 //
25651	/ 67543 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25652	/ 67547 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25653	/ 67551 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25654	/ 67555 / // (strict_fsub:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FSUB_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25655	/ 67555 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSUB_D64),
25656	/ 67560 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25657	/ 67564 / GIR_RootConstrainSelectedInstOperands,
25658	/ 67565 / // GIR_Coverage, 176,
25659	/ 67565 / GIR_Done,
25660	/ 67566 / // Label 1972: @67566
25661	/ 67566 / GIM_Reject,
25662	/ 67567 / // Label 1966: @67567
25663	/ 67567 / GIM_Reject,
25664	/ 67568 / // Label 1960: @67568
25665	/ 67568 / GIM_Reject,
25666	/ 67569 / // Label 80: @67569
25667	/ 67569 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1975/ GIMT_Encode4(`67698`),
25668	/ 67580 / /GILLT_s32//Label 1973/ GIMT_Encode4(`67588`),
25669	/ 67584 / /GILLT_s64//Label 1974/ GIMT_Encode4(`67625`),
25670	/ 67588 / // Label 1973: @67588
25671	/ 67588 / GIM_Try_CheckFeatures, /On fail goto//Label 1976/ GIMT_Encode4(`67624`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 166 //
25672	/ 67595 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25673	/ 67598 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
25674	/ 67601 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25675	/ 67605 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25676	/ 67609 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25677	/ 67613 / // (strict_fmul:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FMUL_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25678	/ 67613 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_S),
25679	/ 67618 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25680	/ 67622 / GIR_RootConstrainSelectedInstOperands,
25681	/ 67623 / // GIR_Coverage, 166,
25682	/ 67623 / GIR_Done,
25683	/ 67624 / // Label 1976: @67624
25684	/ 67624 / GIM_Reject,
25685	/ 67625 / // Label 1974: @67625
25686	/ 67625 / GIM_Try, /On fail goto//Label 1977/ GIMT_Encode4(`67697`),
25687	/ 67630 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25688	/ 67633 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
25689	/ 67636 / GIM_Try_CheckFeatures, /On fail goto//Label 1978/ GIMT_Encode4(`67666`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 168 //
25690	/ 67643 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25691	/ 67647 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25692	/ 67651 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25693	/ 67655 / // (strict_fmul:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FMUL_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25694	/ 67655 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D32),
25695	/ 67660 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25696	/ 67664 / GIR_RootConstrainSelectedInstOperands,
25697	/ 67665 / // GIR_Coverage, 168,
25698	/ 67665 / GIR_Done,
25699	/ 67666 / // Label 1978: @67666
25700	/ 67666 / GIM_Try_CheckFeatures, /On fail goto//Label 1979/ GIMT_Encode4(`67696`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 170 //
25701	/ 67673 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25702	/ 67677 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25703	/ 67681 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25704	/ 67685 / // (strict_fmul:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FMUL_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25705	/ 67685 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FMUL_D64),
25706	/ 67690 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25707	/ 67694 / GIR_RootConstrainSelectedInstOperands,
25708	/ 67695 / // GIR_Coverage, 170,
25709	/ 67695 / GIR_Done,
25710	/ 67696 / // Label 1979: @67696
25711	/ 67696 / GIM_Reject,
25712	/ 67697 / // Label 1977: @67697
25713	/ 67697 / GIM_Reject,
25714	/ 67698 / // Label 1975: @67698
25715	/ 67698 / GIM_Reject,
25716	/ 67699 / // Label 81: @67699
25717	/ 67699 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1982/ GIMT_Encode4(`67828`),
25718	/ 67710 / /GILLT_s32//Label 1980/ GIMT_Encode4(`67718`),
25719	/ 67714 / /GILLT_s64//Label 1981/ GIMT_Encode4(`67755`),
25720	/ 67718 / // Label 1980: @67718
25721	/ 67718 / GIM_Try_CheckFeatures, /On fail goto//Label 1983/ GIMT_Encode4(`67754`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 160 //
25722	/ 67725 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25723	/ 67728 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s32,
25724	/ 67731 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25725	/ 67735 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25726	/ 67739 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25727	/ 67743 / // (strict_fdiv:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft) => (FDIV_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs, FGR32Opnd:{ :[f32] }:$ft)
25728	/ 67743 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_S),
25729	/ 67748 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25730	/ 67752 / GIR_RootConstrainSelectedInstOperands,
25731	/ 67753 / // GIR_Coverage, 160,
25732	/ 67753 / GIR_Done,
25733	/ 67754 / // Label 1983: @67754
25734	/ 67754 / GIM_Reject,
25735	/ 67755 / // Label 1981: @67755
25736	/ 67755 / GIM_Try, /On fail goto//Label 1984/ GIMT_Encode4(`67827`),
25737	/ 67760 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25738	/ 67763 / GIM_RootCheckType, /Op/`2`, /Type/GILLT_s64,
25739	/ 67766 / GIM_Try_CheckFeatures, /On fail goto//Label 1985/ GIMT_Encode4(`67796`), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 162 //
25740	/ 67773 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25741	/ 67777 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25742	/ 67781 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25743	/ 67785 / // (strict_fdiv:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft) => (FDIV_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs, AFGR64Opnd:{ :[f64] }:$ft)
25744	/ 67785 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D32),
25745	/ 67790 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25746	/ 67794 / GIR_RootConstrainSelectedInstOperands,
25747	/ 67795 / // GIR_Coverage, 162,
25748	/ 67795 / GIR_Done,
25749	/ 67796 / // Label 1985: @67796
25750	/ 67796 / GIM_Try_CheckFeatures, /On fail goto//Label 1986/ GIMT_Encode4(`67826`), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 164 //
25751	/ 67803 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25752	/ 67807 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25753	/ 67811 / GIM_RootCheckRegBankForClass, /Op/`2`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25754	/ 67815 / // (strict_fdiv:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft) => (FDIV_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs, FGR64Opnd:{ :[f64] }:$ft)
25755	/ 67815 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FDIV_D64),
25756	/ 67820 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25757	/ 67824 / GIR_RootConstrainSelectedInstOperands,
25758	/ 67825 / // GIR_Coverage, 164,
25759	/ 67825 / GIR_Done,
25760	/ 67826 / // Label 1986: @67826
25761	/ 67826 / GIM_Reject,
25762	/ 67827 / // Label 1984: @67827
25763	/ 67827 / GIM_Reject,
25764	/ 67828 / // Label 1982: @67828
25765	/ 67828 / GIM_Reject,
25766	/ 67829 / // Label 82: @67829
25767	/ 67829 / GIM_SwitchType, /MI/`0`, /Op/`0`, /[/GIMT_Encode2(`0`), GIMT_Encode2(`2`), /)//default://Label 1989/ GIMT_Encode4(`67940`),
25768	/ 67840 / /GILLT_s32//Label 1987/ GIMT_Encode4(`67848`),
25769	/ 67844 / /GILLT_s64//Label 1988/ GIMT_Encode4(`67878`),
25770	/ 67848 / // Label 1987: @67848
25771	/ 67848 / GIM_Try_CheckFeatures, /On fail goto//Label 1990/ GIMT_Encode4(`67877`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 132 //
25772	/ 67855 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s32,
25773	/ 67858 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25774	/ 67862 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR32RegClassID),
25775	/ 67866 / // (strict_fsqrt:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs) => (FSQRT_S:{ :[f32] } FGR32Opnd:{ :[f32] }:$fs)
25776	/ 67866 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_S),
25777	/ 67871 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25778	/ 67875 / GIR_RootConstrainSelectedInstOperands,
25779	/ 67876 / // GIR_Coverage, 132,
25780	/ 67876 / GIR_Done,
25781	/ 67877 / // Label 1990: @67877
25782	/ 67877 / GIM_Reject,
25783	/ 67878 / // Label 1988: @67878
25784	/ 67878 / GIM_Try, /On fail goto//Label 1991/ GIMT_Encode4(`67939`),
25785	/ 67883 / GIM_RootCheckType, /Op/`1`, /Type/GILLT_s64,
25786	/ 67886 / GIM_Try_CheckFeatures, /On fail goto//Label 1992/ GIMT_Encode4(`67912`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 134 //
25787	/ 67893 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25788	/ 67897 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::AFGR64RegClassID),
25789	/ 67901 / // (strict_fsqrt:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D32:{ :[f64] } AFGR64Opnd:{ :[f64] }:$fs)
25790	/ 67901 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D32),
25791	/ 67906 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25792	/ 67910 / GIR_RootConstrainSelectedInstOperands,
25793	/ 67911 / // GIR_Coverage, 134,
25794	/ 67911 / GIR_Done,
25795	/ 67912 / // Label 1992: @67912
25796	/ 67912 / GIM_Try_CheckFeatures, /On fail goto//Label 1993/ GIMT_Encode4(`67938`), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 136 //
25797	/ 67919 / GIM_RootCheckRegBankForClass, /Op/`0`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25798	/ 67923 / GIM_RootCheckRegBankForClass, /Op/`1`, /RC/GIMT_Encode2(Mips::FGR64RegClassID),
25799	/ 67927 / // (strict_fsqrt:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs) => (FSQRT_D64:{ :[f64] } FGR64Opnd:{ :[f64] }:$fs)
25800	/ 67927 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::FSQRT_D64),
25801	/ 67932 / GIR_AddImplicitUse, /InsnID/`0`, GIMT_Encode2(Mips::FCR31),
25802	/ 67936 / GIR_RootConstrainSelectedInstOperands,
25803	/ 67937 / // GIR_Coverage, 136,
25804	/ 67937 / GIR_Done,
25805	/ 67938 / // Label 1993: @67938
25806	/ 67938 / GIM_Reject,
25807	/ 67939 / // Label 1991: @67939
25808	/ 67939 / GIM_Reject,
25809	/ 67940 / // Label 1989: @67940
25810	/ 67940 / GIM_Reject,
25811	/ 67941 / // Label 83: @67941
25812	/ 67941 / GIM_Try_CheckFeatures, /On fail goto//Label 1994/ GIMT_Encode4(`67955`), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 90 //
25813	/ 67948 / // (trap) => (TRAP)
25814	/ 67948 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::TRAP),
25815	/ 67953 / GIR_RootConstrainSelectedInstOperands,
25816	/ 67954 / // GIR_Coverage, 90,
25817	/ 67954 / GIR_Done,
25818	/ 67955 / // Label 1994: @67955
25819	/ 67955 / GIM_Try_CheckFeatures, /On fail goto//Label 1995/ GIMT_Encode4(`67969`), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1136 //
25820	/ 67962 / // (trap) => (TRAP_MM)
25821	/ 67962 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::TRAP_MM),
25822	/ 67967 / GIR_RootConstrainSelectedInstOperands,
25823	/ 67968 / // GIR_Coverage, 1136,
25824	/ 67968 / GIR_Done,
25825	/ 67969 / // Label 1995: @67969
25826	/ 67969 / GIM_Try_CheckFeatures, /On fail goto//Label 1996/ GIMT_Encode4(`67983`), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2037 //
25827	/ 67976 / // (trap) => (Break16)
25828	/ 67976 / GIR_MutateOpcode, /InsnID/`0`, /RecycleInsnID/`0`, /Opcode/GIMT_Encode2(Mips::Break16),
25829	/ 67981 / GIR_RootConstrainSelectedInstOperands,
25830	/ 67982 / // GIR_Coverage, 2037,
25831	/ 67982 / GIR_Done,
25832	/ 67983 / // Label 1996: @67983
25833	/ 67983 / GIM_Reject,
25834	/ 67984 / // Label 84: @67984
25835	/ 67984 / GIM_Reject,
25836	/ 67985 / }; // Size: 67985 bytes
25837	return MatchTable0;
25838	}
25839	#undef GIMT_Encode2
25840	#undef GIMT_Encode4
25841	#undef GIMT_Encode8
25842
25843
25844	#endif // GET_GLOBALISEL_IMPL
25845
25846	#ifdef GET_GLOBALISEL_PREDICATES_DECL
25847
25848	PredicateBitset AvailableModuleFeatures;
25849	mutable PredicateBitset AvailableFunctionFeatures;
25850	PredicateBitset getAvailableFeatures() const {
25851	return AvailableModuleFeatures \| AvailableFunctionFeatures;
25852	}
25853	PredicateBitset
25854	computeAvailableModuleFeatures(const MipsSubtarget Subtarget) const*;
25855	PredicateBitset
25856	computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
25857	const MachineFunction MF) const*;
25858	void setupGeneratedPerFunctionState(MachineFunction &MF) override;
25859
25860	#endif // GET_GLOBALISEL_PREDICATES_DECL
25861
25862	#ifdef GET_GLOBALISEL_PREDICATES_INIT
25863
25864	AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
25865	AvailableFunctionFeatures()
25866
25867	#endif // GET_GLOBALISEL_PREDICATES_INIT
25868
25869

Browse the source code of llvm_projects/build/lib/Target/Mips/MipsGenGlobalISel.inc