1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 43;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s16,
47 GILLT_s32,
48 GILLT_s64,
49 GILLT_v2s16,
50 GILLT_v2s64,
51 GILLT_v4s8,
52 GILLT_v4s32,
53 GILLT_v8s16,
54 GILLT_v16s8,
55};
56const static size_t NumTypeObjects = 9;
57const static LLT TypeObjects[] = {
58 LLT::scalar(16),
59 LLT::scalar(32),
60 LLT::scalar(64),
61 LLT::vector(ElementCount::getFixed(2), 16),
62 LLT::vector(ElementCount::getFixed(2), 64),
63 LLT::vector(ElementCount::getFixed(4), 8),
64 LLT::vector(ElementCount::getFixed(4), 32),
65 LLT::vector(ElementCount::getFixed(8), 16),
66 LLT::vector(ElementCount::getFixed(16), 8),
67};
68
69// Bits for subtarget features that participate in instruction matching.
70enum SubtargetFeatureBits : uint8_t {
71 Feature_IsPTR64bitBit = 22,
72 Feature_UseCompactBranchesBit = 39,
73 Feature_HasMips2Bit = 7,
74 Feature_HasMips3Bit = 17,
75 Feature_HasMips4_32Bit = 25,
76 Feature_NotMips4_32Bit = 26,
77 Feature_HasMips4_32r2Bit = 18,
78 Feature_HasMips32Bit = 3,
79 Feature_HasMips32r2Bit = 6,
80 Feature_HasMips32r6Bit = 27,
81 Feature_NotMips32r6Bit = 4,
82 Feature_IsGP64bitBit = 20,
83 Feature_HasMips64Bit = 23,
84 Feature_HasMips64r2Bit = 21,
85 Feature_HasMips64r6Bit = 28,
86 Feature_NotMips64r6Bit = 5,
87 Feature_InMips16ModeBit = 29,
88 Feature_NotInMips16ModeBit = 0,
89 Feature_HasCnMipsBit = 24,
90 Feature_NotCnMipsBit = 8,
91 Feature_IsSym32Bit = 36,
92 Feature_IsSym64Bit = 37,
93 Feature_IsN64Bit = 38,
94 Feature_RelocNotPICBit = 10,
95 Feature_RelocPICBit = 35,
96 Feature_HasStdEncBit = 1,
97 Feature_NotDSPBit = 12,
98 Feature_InMicroMipsBit = 33,
99 Feature_NotInMicroMipsBit = 2,
100 Feature_IsLEBit = 41,
101 Feature_IsBEBit = 42,
102 Feature_HasEVABit = 34,
103 Feature_HasMSABit = 32,
104 Feature_HasMadd4Bit = 19,
105 Feature_UseIndirectJumpsHazardBit = 13,
106 Feature_NoIndirectJumpGuardsBit = 11,
107 Feature_NotR5900Bit = 9,
108 Feature_AllowFPOpFusionBit = 40,
109 Feature_IsFP64bitBit = 16,
110 Feature_NotFP64bitBit = 15,
111 Feature_IsNotSoftFloatBit = 14,
112 Feature_HasDSPBit = 30,
113 Feature_HasDSPR2Bit = 31,
114};
115
116PredicateBitset MipsInstructionSelector::
117computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
118 PredicateBitset Features{};
119 if (Subtarget->isABI_N64())
120 Features.set(Feature_IsPTR64bitBit);
121 if (Subtarget->useCompactBranches())
122 Features.set(Feature_UseCompactBranchesBit);
123 if (Subtarget->hasMips2())
124 Features.set(Feature_HasMips2Bit);
125 if (Subtarget->hasMips3())
126 Features.set(Feature_HasMips3Bit);
127 if (Subtarget->hasMips4_32())
128 Features.set(Feature_HasMips4_32Bit);
129 if (!Subtarget->hasMips4_32())
130 Features.set(Feature_NotMips4_32Bit);
131 if (Subtarget->hasMips4_32r2())
132 Features.set(Feature_HasMips4_32r2Bit);
133 if (Subtarget->hasMips32())
134 Features.set(Feature_HasMips32Bit);
135 if (Subtarget->hasMips32r2())
136 Features.set(Feature_HasMips32r2Bit);
137 if (Subtarget->hasMips32r6())
138 Features.set(Feature_HasMips32r6Bit);
139 if (!Subtarget->hasMips32r6())
140 Features.set(Feature_NotMips32r6Bit);
141 if (Subtarget->isGP64bit())
142 Features.set(Feature_IsGP64bitBit);
143 if (Subtarget->hasMips64())
144 Features.set(Feature_HasMips64Bit);
145 if (Subtarget->hasMips64r2())
146 Features.set(Feature_HasMips64r2Bit);
147 if (Subtarget->hasMips64r6())
148 Features.set(Feature_HasMips64r6Bit);
149 if (!Subtarget->hasMips64r6())
150 Features.set(Feature_NotMips64r6Bit);
151 if (Subtarget->inMips16Mode())
152 Features.set(Feature_InMips16ModeBit);
153 if (!Subtarget->inMips16Mode())
154 Features.set(Feature_NotInMips16ModeBit);
155 if (Subtarget->hasCnMips())
156 Features.set(Feature_HasCnMipsBit);
157 if (!Subtarget->hasCnMips())
158 Features.set(Feature_NotCnMipsBit);
159 if (Subtarget->hasSym32())
160 Features.set(Feature_IsSym32Bit);
161 if (!Subtarget->hasSym32())
162 Features.set(Feature_IsSym64Bit);
163 if (Subtarget->isABI_N64())
164 Features.set(Feature_IsN64Bit);
165 if (!TM.isPositionIndependent())
166 Features.set(Feature_RelocNotPICBit);
167 if (TM.isPositionIndependent())
168 Features.set(Feature_RelocPICBit);
169 if (Subtarget->hasStandardEncoding())
170 Features.set(Feature_HasStdEncBit);
171 if (!Subtarget->hasDSP())
172 Features.set(Feature_NotDSPBit);
173 if (Subtarget->inMicroMipsMode())
174 Features.set(Feature_InMicroMipsBit);
175 if (!Subtarget->inMicroMipsMode())
176 Features.set(Feature_NotInMicroMipsBit);
177 if (Subtarget->isLittle())
178 Features.set(Feature_IsLEBit);
179 if (!Subtarget->isLittle())
180 Features.set(Feature_IsBEBit);
181 if (Subtarget->hasEVA())
182 Features.set(Feature_HasEVABit);
183 if (Subtarget->hasMSA())
184 Features.set(Feature_HasMSABit);
185 if (!Subtarget->disableMadd4())
186 Features.set(Feature_HasMadd4Bit);
187 if (Subtarget->useIndirectJumpsHazard())
188 Features.set(Feature_UseIndirectJumpsHazardBit);
189 if (!Subtarget->useIndirectJumpsHazard())
190 Features.set(Feature_NoIndirectJumpGuardsBit);
191 if (!Subtarget->isR5900())
192 Features.set(Feature_NotR5900Bit);
193 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
194 Features.set(Feature_AllowFPOpFusionBit);
195 if (Subtarget->isFP64bit())
196 Features.set(Feature_IsFP64bitBit);
197 if (!Subtarget->isFP64bit())
198 Features.set(Feature_NotFP64bitBit);
199 if (!Subtarget->useSoftFloat())
200 Features.set(Feature_IsNotSoftFloatBit);
201 if (Subtarget->hasDSP())
202 Features.set(Feature_HasDSPBit);
203 if (Subtarget->hasDSPR2())
204 Features.set(Feature_HasDSPR2Bit);
205 return Features;
206}
207
208void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
209 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
210}
211PredicateBitset MipsInstructionSelector::
212computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
213 PredicateBitset Features{};
214 return Features;
215}
216
217// Feature bitsets.
218enum {
219 GIFBS_Invalid,
220 GIFBS_HasCnMips,
221 GIFBS_HasDSP,
222 GIFBS_HasDSPR2,
223 GIFBS_HasMSA,
224 GIFBS_InMicroMips,
225 GIFBS_InMips16Mode,
226 GIFBS_IsFP64bit,
227 GIFBS_NotFP64bit,
228 GIFBS_NotInMips16Mode,
229 GIFBS_HasDSP_InMicroMips,
230 GIFBS_HasDSP_NotInMicroMips,
231 GIFBS_HasDSPR2_InMicroMips,
232 GIFBS_HasMSA_HasStdEnc,
233 GIFBS_HasMSA_IsBE,
234 GIFBS_HasMSA_IsLE,
235 GIFBS_HasMips32r6_HasStdEnc,
236 GIFBS_HasMips32r6_InMicroMips,
237 GIFBS_HasMips64r2_HasStdEnc,
238 GIFBS_HasMips64r6_HasStdEnc,
239 GIFBS_HasStdEnc_IsNotSoftFloat,
240 GIFBS_HasStdEnc_NotInMicroMips,
241 GIFBS_HasStdEnc_NotMips4_32,
242 GIFBS_InMicroMips_IsFP64bit,
243 GIFBS_InMicroMips_IsNotSoftFloat,
244 GIFBS_InMicroMips_NotFP64bit,
245 GIFBS_InMicroMips_NotMips32r6,
246 GIFBS_IsGP64bit_NotInMips16Mode,
247 GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
248 GIFBS_HasMSA_HasMips64_HasStdEnc,
249 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
250 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
251 GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
252 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
253 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
254 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
255 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
256 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
257 GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
258 GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
259 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
260 GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
261 GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
262 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
263 GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
264 GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
265 GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
266 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
267 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
268 GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
269 GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
270 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
271 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
272 GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
273 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
274 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
275 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
276 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
277 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
278 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
279 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
280 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
281 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
282 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
283 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
284 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
285 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
286 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
287 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
288 GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
289 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
290 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
291 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
292};
293constexpr static PredicateBitset FeatureBitsets[] {
294 {}, // GIFBS_Invalid
295 {Feature_HasCnMipsBit, },
296 {Feature_HasDSPBit, },
297 {Feature_HasDSPR2Bit, },
298 {Feature_HasMSABit, },
299 {Feature_InMicroMipsBit, },
300 {Feature_InMips16ModeBit, },
301 {Feature_IsFP64bitBit, },
302 {Feature_NotFP64bitBit, },
303 {Feature_NotInMips16ModeBit, },
304 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
305 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
306 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
307 {Feature_HasMSABit, Feature_HasStdEncBit, },
308 {Feature_HasMSABit, Feature_IsBEBit, },
309 {Feature_HasMSABit, Feature_IsLEBit, },
310 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
311 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
312 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
313 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
314 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
315 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
316 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
317 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
318 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
319 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
320 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
321 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
322 {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
323 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
324 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
325 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
326 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
327 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
328 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
329 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
330 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
331 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
332 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
333 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
334 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
335 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
336 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
337 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
338 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
339 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
340 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
341 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
342 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
343 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
344 {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
345 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
346 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
347 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
348 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
349 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
350 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
351 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
352 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
353 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
354 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
355 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
356 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
357 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
358 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
359 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
360 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
361 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
362 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
363 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
364 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
365 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
366 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
367};
368
369// ComplexPattern predicates.
370enum {
371 GICP_Invalid,
372};
373// See constructor for table contents
374
375MipsInstructionSelector::ComplexMatcherMemFn
376MipsInstructionSelector::ComplexPredicateFns[] = {
377 nullptr, // GICP_Invalid
378};
379
380// PatFrag predicates.
381enum {
382 GICXXPred_MI_Predicate_ffloor_nnan = GICXXPred_Invalid + 1,
383 GICXXPred_MI_Predicate_or_disjoint,
384};
385bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
386 const MachineFunction &MF = *MI.getParent()->getParent();
387 const MachineRegisterInfo &MRI = MF.getRegInfo();
388 const auto &Operands = State.RecordedOperands;
389 (void)Operands;
390 (void)MRI;
391 switch (PredicateID) {
392 case GICXXPred_MI_Predicate_ffloor_nnan: {
393
394 return MI.getFlag(MachineInstr::FmNoNans);
395
396 }
397 case GICXXPred_MI_Predicate_or_disjoint: {
398
399 return MI.getFlag(MachineInstr::Disjoint);
400
401 }
402 }
403 llvm_unreachable("Unknown predicate");
404 return false;
405}
406// PatFrag predicates.
407bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
408 const auto &Operands = State.RecordedOperands;
409 Register Reg = MO.getReg();
410 (void)Operands;
411 (void)Reg;
412 llvm_unreachable("Unknown predicate");
413 return false;
414}
415// PatFrag predicates.
416enum {
417 GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
418 GICXXPred_I64_Predicate_immSExt6,
419 GICXXPred_I64_Predicate_immSExt10,
420 GICXXPred_I64_Predicate_immSExtAddiur2,
421 GICXXPred_I64_Predicate_immSExtAddius5,
422 GICXXPred_I64_Predicate_immZExt1,
423 GICXXPred_I64_Predicate_immZExt1Ptr,
424 GICXXPred_I64_Predicate_immZExt2,
425 GICXXPred_I64_Predicate_immZExt2Lsa,
426 GICXXPred_I64_Predicate_immZExt2Ptr,
427 GICXXPred_I64_Predicate_immZExt2Shift,
428 GICXXPred_I64_Predicate_immZExt3,
429 GICXXPred_I64_Predicate_immZExt3Ptr,
430 GICXXPred_I64_Predicate_immZExt4,
431 GICXXPred_I64_Predicate_immZExt4Ptr,
432 GICXXPred_I64_Predicate_immZExt5,
433 GICXXPred_I64_Predicate_immZExt5_64,
434 GICXXPred_I64_Predicate_immZExt6,
435 GICXXPred_I64_Predicate_immZExt8,
436 GICXXPred_I64_Predicate_immZExt10,
437 GICXXPred_I64_Predicate_immZExtAndi16,
438 GICXXPred_I64_Predicate_immi32Cst7,
439 GICXXPred_I64_Predicate_immi32Cst15,
440 GICXXPred_I64_Predicate_immi32Cst31,
441 GICXXPred_I64_Predicate_timmSExt6,
442 GICXXPred_I64_Predicate_timmZExt1,
443 GICXXPred_I64_Predicate_timmZExt1Ptr,
444 GICXXPred_I64_Predicate_timmZExt2,
445 GICXXPred_I64_Predicate_timmZExt2Ptr,
446 GICXXPred_I64_Predicate_timmZExt3,
447 GICXXPred_I64_Predicate_timmZExt3Ptr,
448 GICXXPred_I64_Predicate_timmZExt4,
449 GICXXPred_I64_Predicate_timmZExt4Ptr,
450 GICXXPred_I64_Predicate_timmZExt5,
451 GICXXPred_I64_Predicate_timmZExt6,
452 GICXXPred_I64_Predicate_timmZExt8,
453 GICXXPred_I64_Predicate_timmZExt10,
454};
455bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
456 switch (PredicateID) {
457 case GICXXPred_I64_Predicate_immLi16: {
458 return Imm >= -1 && Imm <= 126;
459 }
460 case GICXXPred_I64_Predicate_immSExt6: {
461 return isInt<6>(Imm);
462 }
463 case GICXXPred_I64_Predicate_immSExt10: {
464 return isInt<10>(Imm);
465 }
466 case GICXXPred_I64_Predicate_immSExtAddiur2: {
467 return Imm == 1 || Imm == -1 ||
468 ((Imm % 4 == 0) &&
469 Imm < 28 && Imm > 0);
470 }
471 case GICXXPred_I64_Predicate_immSExtAddius5: {
472 return Imm >= -8 && Imm <= 7;
473 }
474 case GICXXPred_I64_Predicate_immZExt1: {
475 return isUInt<1>(Imm);
476 }
477 case GICXXPred_I64_Predicate_immZExt1Ptr: {
478 return isUInt<1>(Imm);
479 }
480 case GICXXPred_I64_Predicate_immZExt2: {
481 return isUInt<2>(Imm);
482 }
483 case GICXXPred_I64_Predicate_immZExt2Lsa: {
484 return isUInt<2>(Imm - 1);
485 }
486 case GICXXPred_I64_Predicate_immZExt2Ptr: {
487 return isUInt<2>(Imm);
488 }
489 case GICXXPred_I64_Predicate_immZExt2Shift: {
490 return Imm >= 1 && Imm <= 8;
491 }
492 case GICXXPred_I64_Predicate_immZExt3: {
493 return isUInt<3>(Imm);
494 }
495 case GICXXPred_I64_Predicate_immZExt3Ptr: {
496 return isUInt<3>(Imm);
497 }
498 case GICXXPred_I64_Predicate_immZExt4: {
499 return isUInt<4>(Imm);
500 }
501 case GICXXPred_I64_Predicate_immZExt4Ptr: {
502 return isUInt<4>(Imm);
503 }
504 case GICXXPred_I64_Predicate_immZExt5: {
505 return Imm == (Imm & 0x1f);
506 }
507 case GICXXPred_I64_Predicate_immZExt5_64: {
508 return Imm == (Imm & 0x1f);
509 }
510 case GICXXPred_I64_Predicate_immZExt6: {
511 return Imm == (Imm & 0x3f);
512 }
513 case GICXXPred_I64_Predicate_immZExt8: {
514 return isUInt<8>(Imm);
515 }
516 case GICXXPred_I64_Predicate_immZExt10: {
517 return isUInt<10>(Imm);
518 }
519 case GICXXPred_I64_Predicate_immZExtAndi16: {
520 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
521 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
522 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
523 }
524 case GICXXPred_I64_Predicate_immi32Cst7: {
525 return isUInt<32>(Imm) && Imm == 7;
526 }
527 case GICXXPred_I64_Predicate_immi32Cst15: {
528 return isUInt<32>(Imm) && Imm == 15;
529 }
530 case GICXXPred_I64_Predicate_immi32Cst31: {
531 return isUInt<32>(Imm) && Imm == 31;
532 }
533 case GICXXPred_I64_Predicate_timmSExt6: {
534 return isInt<6>(Imm);
535 }
536 case GICXXPred_I64_Predicate_timmZExt1: {
537 return isUInt<1>(Imm);
538 }
539 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
540 return isUInt<1>(Imm);
541 }
542 case GICXXPred_I64_Predicate_timmZExt2: {
543 return isUInt<2>(Imm);
544 }
545 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
546 return isUInt<2>(Imm);
547 }
548 case GICXXPred_I64_Predicate_timmZExt3: {
549 return isUInt<3>(Imm);
550 }
551 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
552 return isUInt<3>(Imm);
553 }
554 case GICXXPred_I64_Predicate_timmZExt4: {
555 return isUInt<4>(Imm);
556 }
557 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
558 return isUInt<4>(Imm);
559 }
560 case GICXXPred_I64_Predicate_timmZExt5: {
561 return Imm == (Imm & 0x1f);
562 }
563 case GICXXPred_I64_Predicate_timmZExt6: {
564 return Imm == (Imm & 0x3f);
565 }
566 case GICXXPred_I64_Predicate_timmZExt8: {
567 return isUInt<8>(Imm);
568 }
569 case GICXXPred_I64_Predicate_timmZExt10: {
570 return isUInt<10>(Imm);
571 }
572 }
573 llvm_unreachable("Unknown predicate");
574 return false;
575}
576// PatFrag predicates.
577bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
578 llvm_unreachable("Unknown predicate");
579 return false;
580}
581// PatFrag predicates.
582enum {
583 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
584 GICXXPred_APInt_Predicate_imm32ZExt16,
585};
586bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
587 switch (PredicateID) {
588 case GICXXPred_APInt_Predicate_imm32SExt16: {
589 return isInt<16>(Imm.getSExtValue());
590 }
591 case GICXXPred_APInt_Predicate_imm32ZExt16: {
592
593 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
594
595 }
596 }
597 llvm_unreachable("Unknown predicate");
598 return false;
599}
600bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
601 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
602 return false;
603}
604// Custom renderers.
605enum {
606 GICR_Invalid,
607};
608MipsInstructionSelector::CustomRendererFn
609MipsInstructionSelector::CustomRenderers[] = {
610 nullptr, // GICR_Invalid
611};
612
613bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
614 const PredicateBitset AvailableFeatures = getAvailableFeatures();
615 MachineIRBuilder B(I);
616 State.MIs.clear();
617 State.MIs.push_back(&I);
618
619 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
620 return true;
621 }
622
623 return false;
624}
625
626bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
627 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
628}
629#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
630#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
631#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
632#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
633#else
634#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
635#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
636#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
637#endif
638const uint8_t *MipsInstructionSelector::getMatchTable() const {
639 constexpr static uint8_t MatchTable0[] = {
640 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(302), /*)*//*default:*//*Label 84*/ GIMT_Encode4(72179),
641 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(998),
642 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2296),
643 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2987),
644 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3468),
645 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3737),
646 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(4006),
647 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4275), GIMT_Encode4(0), GIMT_Encode4(0),
648 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4544),
649 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5100),
650 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5504), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
651 /* 118 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6396),
652 /* 122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6469), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
653 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6810), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
654 /* 186 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(11121),
655 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(11186),
656 /* 194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11254), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
657 /* 222 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(11322),
658 /* 226 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11514),
659 /* 230 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11684),
660 /* 234 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11854),
661 /* 238 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(12024),
662 /* 242 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(12194),
663 /* 246 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(12364),
664 /* 250 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12534),
665 /* 254 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12704),
666 /* 258 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12874),
667 /* 262 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(13044),
668 /* 266 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(13214), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
669 /* 318 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(13384), GIMT_Encode4(0), GIMT_Encode4(0),
670 /* 330 */ /*TargetOpcode::G_INTRINSIC*//*Label 29*/ GIMT_Encode4(19929),
671 /* 334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ GIMT_Encode4(34194), GIMT_Encode4(0), GIMT_Encode4(0),
672 /* 346 */ /*TargetOpcode::G_ANYEXT*//*Label 31*/ GIMT_Encode4(39288),
673 /* 350 */ /*TargetOpcode::G_TRUNC*//*Label 32*/ GIMT_Encode4(39354), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
674 /* 366 */ /*TargetOpcode::G_CONSTANT*//*Label 33*/ GIMT_Encode4(39418), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
675 /* 382 */ /*TargetOpcode::G_SEXT*//*Label 34*/ GIMT_Encode4(39479),
676 /* 386 */ /*TargetOpcode::G_SEXT_INREG*//*Label 35*/ GIMT_Encode4(40943),
677 /* 390 */ /*TargetOpcode::G_ZEXT*//*Label 36*/ GIMT_Encode4(41291),
678 /* 394 */ /*TargetOpcode::G_SHL*//*Label 37*/ GIMT_Encode4(41492),
679 /* 398 */ /*TargetOpcode::G_LSHR*//*Label 38*/ GIMT_Encode4(43289),
680 /* 402 */ /*TargetOpcode::G_ASHR*//*Label 39*/ GIMT_Encode4(45086), GIMT_Encode4(0), GIMT_Encode4(0),
681 /* 414 */ /*TargetOpcode::G_ROTR*//*Label 40*/ GIMT_Encode4(46841), GIMT_Encode4(0),
682 /* 422 */ /*TargetOpcode::G_ICMP*//*Label 41*/ GIMT_Encode4(47129),
683 /* 426 */ /*TargetOpcode::G_FCMP*//*Label 42*/ GIMT_Encode4(49660), GIMT_Encode4(0), GIMT_Encode4(0),
684 /* 438 */ /*TargetOpcode::G_SELECT*//*Label 43*/ GIMT_Encode4(50660), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
685 /* 482 */ /*TargetOpcode::G_UMULH*//*Label 44*/ GIMT_Encode4(62790),
686 /* 486 */ /*TargetOpcode::G_SMULH*//*Label 45*/ GIMT_Encode4(62899), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
687 /* 546 */ /*TargetOpcode::G_FADD*//*Label 46*/ GIMT_Encode4(63008),
688 /* 550 */ /*TargetOpcode::G_FSUB*//*Label 47*/ GIMT_Encode4(64303),
689 /* 554 */ /*TargetOpcode::G_FMUL*//*Label 48*/ GIMT_Encode4(65118),
690 /* 558 */ /*TargetOpcode::G_FMA*//*Label 49*/ GIMT_Encode4(65629), GIMT_Encode4(0),
691 /* 566 */ /*TargetOpcode::G_FDIV*//*Label 50*/ GIMT_Encode4(65735), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
692 /* 590 */ /*TargetOpcode::G_FEXP2*//*Label 51*/ GIMT_Encode4(66058), GIMT_Encode4(0), GIMT_Encode4(0),
693 /* 602 */ /*TargetOpcode::G_FLOG2*//*Label 52*/ GIMT_Encode4(66136), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
694 /* 618 */ /*TargetOpcode::G_FNEG*//*Label 53*/ GIMT_Encode4(66214),
695 /* 622 */ /*TargetOpcode::G_FPEXT*//*Label 54*/ GIMT_Encode4(66407),
696 /* 626 */ /*TargetOpcode::G_FPTRUNC*//*Label 55*/ GIMT_Encode4(66601),
697 /* 630 */ /*TargetOpcode::G_FPTOSI*//*Label 56*/ GIMT_Encode4(66780),
698 /* 634 */ /*TargetOpcode::G_FPTOUI*//*Label 57*/ GIMT_Encode4(66858),
699 /* 638 */ /*TargetOpcode::G_SITOFP*//*Label 58*/ GIMT_Encode4(66936),
700 /* 642 */ /*TargetOpcode::G_UITOFP*//*Label 59*/ GIMT_Encode4(67189), GIMT_Encode4(0), GIMT_Encode4(0),
701 /* 654 */ /*TargetOpcode::G_FABS*//*Label 60*/ GIMT_Encode4(67267), GIMT_Encode4(0), GIMT_Encode4(0),
702 /* 666 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 61*/ GIMT_Encode4(67409),
703 /* 670 */ /*TargetOpcode::G_FMINNUM*//*Label 62*/ GIMT_Encode4(67483),
704 /* 674 */ /*TargetOpcode::G_FMAXNUM*//*Label 63*/ GIMT_Encode4(67555),
705 /* 678 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 64*/ GIMT_Encode4(67627),
706 /* 682 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 65*/ GIMT_Encode4(67699), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
707 /* 742 */ /*TargetOpcode::G_SMIN*//*Label 66*/ GIMT_Encode4(67771),
708 /* 746 */ /*TargetOpcode::G_SMAX*//*Label 67*/ GIMT_Encode4(67939),
709 /* 750 */ /*TargetOpcode::G_UMIN*//*Label 68*/ GIMT_Encode4(68107),
710 /* 754 */ /*TargetOpcode::G_UMAX*//*Label 69*/ GIMT_Encode4(68275), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
711 /* 770 */ /*TargetOpcode::G_BR*//*Label 70*/ GIMT_Encode4(68443), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
712 /* 790 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(68567),
713 /* 794 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(69131), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
714 /* 822 */ /*TargetOpcode::G_CTLZ*//*Label 73*/ GIMT_Encode4(69183), GIMT_Encode4(0), GIMT_Encode4(0),
715 /* 834 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(69688),
716 /* 838 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(69894), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
717 /* 894 */ /*TargetOpcode::G_FSQRT*//*Label 76*/ GIMT_Encode4(70058), GIMT_Encode4(0),
718 /* 902 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(70322), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
719 /* 934 */ /*TargetOpcode::G_STRICT_FADD*//*Label 78*/ GIMT_Encode4(70400),
720 /* 938 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 79*/ GIMT_Encode4(71255),
721 /* 942 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 80*/ GIMT_Encode4(71752),
722 /* 946 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 81*/ GIMT_Encode4(71885), GIMT_Encode4(0), GIMT_Encode4(0),
723 /* 958 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 82*/ GIMT_Encode4(72018), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
724 /* 994 */ /*TargetOpcode::G_TRAP*//*Label 83*/ GIMT_Encode4(72133),
725 /* 998 */ // Label 0: @998
726 /* 998 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 93*/ GIMT_Encode4(2295),
727 /* 1009 */ /*GILLT_s32*//*Label 85*/ GIMT_Encode4(1041),
728 /* 1013 */ /*GILLT_s64*//*Label 86*/ GIMT_Encode4(1449),
729 /* 1017 */ /*GILLT_v2s16*//*Label 87*/ GIMT_Encode4(1615),
730 /* 1021 */ /*GILLT_v2s64*//*Label 88*/ GIMT_Encode4(1647),
731 /* 1025 */ /*GILLT_v4s8*//*Label 89*/ GIMT_Encode4(1801),
732 /* 1029 */ /*GILLT_v4s32*//*Label 90*/ GIMT_Encode4(1833),
733 /* 1033 */ /*GILLT_v8s16*//*Label 91*/ GIMT_Encode4(1987),
734 /* 1037 */ /*GILLT_v16s8*//*Label 92*/ GIMT_Encode4(2141),
735 /* 1041 */ // Label 85: @1041
736 /* 1041 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1448),
737 /* 1046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
738 /* 1049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
739 /* 1052 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1119), // Rule ID 2537 //
740 /* 1057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
741 /* 1060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
742 /* 1064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
743 /* 1068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
744 /* 1072 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
745 /* 1076 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
746 /* 1080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
747 /* 1085 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
748 /* 1089 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
749 /* 1093 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
750 /* 1097 */ // MIs[2] Operand 1
751 /* 1097 */ // No operand predicates
752 /* 1097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
753 /* 1101 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
754 /* 1103 */ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
755 /* 1103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
756 /* 1106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
757 /* 1108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
758 /* 1112 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
759 /* 1114 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
760 /* 1117 */ GIR_RootConstrainSelectedInstOperands,
761 /* 1118 */ // GIR_Coverage, 2537,
762 /* 1118 */ GIR_EraseRootFromParent_Done,
763 /* 1119 */ // Label 95: @1119
764 /* 1119 */ GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1186), // Rule ID 858 //
765 /* 1124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
766 /* 1127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
767 /* 1131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
768 /* 1135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
769 /* 1139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
770 /* 1143 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
771 /* 1147 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
772 /* 1151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
773 /* 1156 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
774 /* 1160 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
775 /* 1164 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
776 /* 1168 */ // MIs[2] Operand 1
777 /* 1168 */ // No operand predicates
778 /* 1168 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
779 /* 1170 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
780 /* 1170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
781 /* 1173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
782 /* 1175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
783 /* 1179 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
784 /* 1181 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
785 /* 1184 */ GIR_RootConstrainSelectedInstOperands,
786 /* 1185 */ // GIR_Coverage, 858,
787 /* 1185 */ GIR_EraseRootFromParent_Done,
788 /* 1186 */ // Label 96: @1186
789 /* 1186 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1228), // Rule ID 40 //
790 /* 1191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
791 /* 1194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
792 /* 1198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
793 /* 1202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
794 /* 1206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
795 /* 1210 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
796 /* 1214 */ // MIs[1] Operand 1
797 /* 1214 */ // No operand predicates
798 /* 1214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
799 /* 1216 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
800 /* 1216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
801 /* 1219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
802 /* 1221 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
803 /* 1223 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
804 /* 1226 */ GIR_RootConstrainSelectedInstOperands,
805 /* 1227 */ // GIR_Coverage, 40,
806 /* 1227 */ GIR_EraseRootFromParent_Done,
807 /* 1228 */ // Label 97: @1228
808 /* 1228 */ GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1270), // Rule ID 2295 //
809 /* 1233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
810 /* 1236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
811 /* 1240 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
812 /* 1244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
813 /* 1248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
814 /* 1252 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
815 /* 1256 */ // MIs[1] Operand 1
816 /* 1256 */ // No operand predicates
817 /* 1256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
818 /* 1258 */ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
819 /* 1258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
820 /* 1261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
821 /* 1263 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
822 /* 1265 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
823 /* 1268 */ GIR_RootConstrainSelectedInstOperands,
824 /* 1269 */ // GIR_Coverage, 2295,
825 /* 1269 */ GIR_EraseRootFromParent_Done,
826 /* 1270 */ // Label 98: @1270
827 /* 1270 */ GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1312), // Rule ID 2296 //
828 /* 1275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
829 /* 1278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
830 /* 1282 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
831 /* 1286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
832 /* 1290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
833 /* 1294 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
834 /* 1298 */ // MIs[1] Operand 1
835 /* 1298 */ // No operand predicates
836 /* 1298 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
837 /* 1300 */ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
838 /* 1300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
839 /* 1303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
840 /* 1305 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
841 /* 1307 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
842 /* 1310 */ GIR_RootConstrainSelectedInstOperands,
843 /* 1311 */ // GIR_Coverage, 2296,
844 /* 1311 */ GIR_EraseRootFromParent_Done,
845 /* 1312 */ // Label 99: @1312
846 /* 1312 */ GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1339), // Rule ID 1231 //
847 /* 1317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
848 /* 1320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
849 /* 1324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
850 /* 1328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
851 /* 1332 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
852 /* 1332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
853 /* 1337 */ GIR_RootConstrainSelectedInstOperands,
854 /* 1338 */ // GIR_Coverage, 1231,
855 /* 1338 */ GIR_Done,
856 /* 1339 */ // Label 100: @1339
857 /* 1339 */ GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1366), // Rule ID 46 //
858 /* 1344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
859 /* 1347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
860 /* 1351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
861 /* 1355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
862 /* 1359 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
863 /* 1359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
864 /* 1364 */ GIR_RootConstrainSelectedInstOperands,
865 /* 1365 */ // GIR_Coverage, 46,
866 /* 1365 */ GIR_Done,
867 /* 1366 */ // Label 101: @1366
868 /* 1366 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1393), // Rule ID 1084 //
869 /* 1371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
870 /* 1374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
871 /* 1378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
872 /* 1382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
873 /* 1386 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
874 /* 1386 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
875 /* 1391 */ GIR_RootConstrainSelectedInstOperands,
876 /* 1392 */ // GIR_Coverage, 1084,
877 /* 1392 */ GIR_Done,
878 /* 1393 */ // Label 102: @1393
879 /* 1393 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1420), // Rule ID 1096 //
880 /* 1398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
881 /* 1401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
882 /* 1405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
883 /* 1409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
884 /* 1413 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
885 /* 1413 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
886 /* 1418 */ GIR_RootConstrainSelectedInstOperands,
887 /* 1419 */ // GIR_Coverage, 1096,
888 /* 1419 */ GIR_Done,
889 /* 1420 */ // Label 103: @1420
890 /* 1420 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1447), // Rule ID 1953 //
891 /* 1425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
892 /* 1428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
893 /* 1432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
894 /* 1436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
895 /* 1440 */ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
896 /* 1440 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
897 /* 1445 */ GIR_RootConstrainSelectedInstOperands,
898 /* 1446 */ // GIR_Coverage, 1953,
899 /* 1446 */ GIR_Done,
900 /* 1447 */ // Label 104: @1447
901 /* 1447 */ GIM_Reject,
902 /* 1448 */ // Label 94: @1448
903 /* 1448 */ GIM_Reject,
904 /* 1449 */ // Label 86: @1449
905 /* 1449 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1614),
906 /* 1454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
907 /* 1457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
908 /* 1460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
909 /* 1464 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1527), // Rule ID 2538 //
910 /* 1469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
911 /* 1472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
912 /* 1476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
913 /* 1480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
914 /* 1484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
915 /* 1488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
916 /* 1493 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
917 /* 1497 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
918 /* 1501 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
919 /* 1505 */ // MIs[2] Operand 1
920 /* 1505 */ // No operand predicates
921 /* 1505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
922 /* 1509 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
923 /* 1511 */ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
924 /* 1511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
925 /* 1514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
926 /* 1516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
927 /* 1520 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
928 /* 1522 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
929 /* 1525 */ GIR_RootConstrainSelectedInstOperands,
930 /* 1526 */ // GIR_Coverage, 2538,
931 /* 1526 */ GIR_EraseRootFromParent_Done,
932 /* 1527 */ // Label 106: @1527
933 /* 1527 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1590), // Rule ID 859 //
934 /* 1532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
935 /* 1535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
936 /* 1539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
937 /* 1543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
938 /* 1547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
939 /* 1551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
940 /* 1555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
941 /* 1560 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
942 /* 1564 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
943 /* 1568 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
944 /* 1572 */ // MIs[2] Operand 1
945 /* 1572 */ // No operand predicates
946 /* 1572 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
947 /* 1574 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
948 /* 1574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
949 /* 1577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
950 /* 1579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
951 /* 1583 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
952 /* 1585 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
953 /* 1588 */ GIR_RootConstrainSelectedInstOperands,
954 /* 1589 */ // GIR_Coverage, 859,
955 /* 1589 */ GIR_EraseRootFromParent_Done,
956 /* 1590 */ // Label 107: @1590
957 /* 1590 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1613), // Rule ID 226 //
958 /* 1595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
959 /* 1598 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
960 /* 1602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
961 /* 1606 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
962 /* 1606 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
963 /* 1611 */ GIR_RootConstrainSelectedInstOperands,
964 /* 1612 */ // GIR_Coverage, 226,
965 /* 1612 */ GIR_Done,
966 /* 1613 */ // Label 108: @1613
967 /* 1613 */ GIM_Reject,
968 /* 1614 */ // Label 105: @1614
969 /* 1614 */ GIM_Reject,
970 /* 1615 */ // Label 87: @1615
971 /* 1615 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1646), // Rule ID 2052 //
972 /* 1620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
973 /* 1623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
974 /* 1626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
975 /* 1629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
976 /* 1633 */ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
977 /* 1633 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
978 /* 1638 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
979 /* 1644 */ GIR_RootConstrainSelectedInstOperands,
980 /* 1645 */ // GIR_Coverage, 2052,
981 /* 1645 */ GIR_Done,
982 /* 1646 */ // Label 109: @1646
983 /* 1646 */ GIM_Reject,
984 /* 1647 */ // Label 88: @1647
985 /* 1647 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1800),
986 /* 1652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
987 /* 1655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
988 /* 1658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
989 /* 1662 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1719), // Rule ID 2542 //
990 /* 1667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
991 /* 1670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
992 /* 1674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
993 /* 1678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
994 /* 1682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
995 /* 1686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
996 /* 1691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
997 /* 1696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
998 /* 1700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
999 /* 1702 */ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1000 /* 1702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1001 /* 1705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1002 /* 1707 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1003 /* 1709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1004 /* 1713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1005 /* 1717 */ GIR_RootConstrainSelectedInstOperands,
1006 /* 1718 */ // GIR_Coverage, 2542,
1007 /* 1718 */ GIR_EraseRootFromParent_Done,
1008 /* 1719 */ // Label 111: @1719
1009 /* 1719 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1776), // Rule ID 867 //
1010 /* 1724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1011 /* 1727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1012 /* 1731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1013 /* 1735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1014 /* 1739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1015 /* 1743 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1016 /* 1747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1017 /* 1752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1018 /* 1757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1019 /* 1759 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1020 /* 1759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1021 /* 1762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1022 /* 1764 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1023 /* 1766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1024 /* 1770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1025 /* 1774 */ GIR_RootConstrainSelectedInstOperands,
1026 /* 1775 */ // GIR_Coverage, 867,
1027 /* 1775 */ GIR_EraseRootFromParent_Done,
1028 /* 1776 */ // Label 112: @1776
1029 /* 1776 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1799), // Rule ID 534 //
1030 /* 1781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1031 /* 1784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1032 /* 1788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1033 /* 1792 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1034 /* 1792 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
1035 /* 1797 */ GIR_RootConstrainSelectedInstOperands,
1036 /* 1798 */ // GIR_Coverage, 534,
1037 /* 1798 */ GIR_Done,
1038 /* 1799 */ // Label 113: @1799
1039 /* 1799 */ GIM_Reject,
1040 /* 1800 */ // Label 110: @1800
1041 /* 1800 */ GIM_Reject,
1042 /* 1801 */ // Label 89: @1801
1043 /* 1801 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1832), // Rule ID 2058 //
1044 /* 1806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1045 /* 1809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1046 /* 1812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1047 /* 1815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1048 /* 1819 */ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1049 /* 1819 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
1050 /* 1824 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1051 /* 1830 */ GIR_RootConstrainSelectedInstOperands,
1052 /* 1831 */ // GIR_Coverage, 2058,
1053 /* 1831 */ GIR_Done,
1054 /* 1832 */ // Label 114: @1832
1055 /* 1832 */ GIM_Reject,
1056 /* 1833 */ // Label 90: @1833
1057 /* 1833 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1986),
1058 /* 1838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1059 /* 1841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1060 /* 1844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1061 /* 1848 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1905), // Rule ID 2541 //
1062 /* 1853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1063 /* 1856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1064 /* 1860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1065 /* 1864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1066 /* 1868 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1067 /* 1872 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1068 /* 1877 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1069 /* 1882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1070 /* 1886 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1071 /* 1888 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1072 /* 1888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1073 /* 1891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1074 /* 1893 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1075 /* 1895 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1076 /* 1899 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1077 /* 1903 */ GIR_RootConstrainSelectedInstOperands,
1078 /* 1904 */ // GIR_Coverage, 2541,
1079 /* 1904 */ GIR_EraseRootFromParent_Done,
1080 /* 1905 */ // Label 116: @1905
1081 /* 1905 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1962), // Rule ID 866 //
1082 /* 1910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1083 /* 1913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1084 /* 1917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1085 /* 1921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1086 /* 1925 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1087 /* 1929 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1088 /* 1933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1089 /* 1938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1090 /* 1943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1091 /* 1945 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1092 /* 1945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1093 /* 1948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1094 /* 1950 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1095 /* 1952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1096 /* 1956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1097 /* 1960 */ GIR_RootConstrainSelectedInstOperands,
1098 /* 1961 */ // GIR_Coverage, 866,
1099 /* 1961 */ GIR_EraseRootFromParent_Done,
1100 /* 1962 */ // Label 117: @1962
1101 /* 1962 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1985), // Rule ID 533 //
1102 /* 1967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1103 /* 1970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1104 /* 1974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1105 /* 1978 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1106 /* 1978 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1107 /* 1983 */ GIR_RootConstrainSelectedInstOperands,
1108 /* 1984 */ // GIR_Coverage, 533,
1109 /* 1984 */ GIR_Done,
1110 /* 1985 */ // Label 118: @1985
1111 /* 1985 */ GIM_Reject,
1112 /* 1986 */ // Label 115: @1986
1113 /* 1986 */ GIM_Reject,
1114 /* 1987 */ // Label 91: @1987
1115 /* 1987 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2140),
1116 /* 1992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1117 /* 1995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1118 /* 1998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1119 /* 2002 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2059), // Rule ID 2540 //
1120 /* 2007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1121 /* 2010 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1122 /* 2014 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1123 /* 2018 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1124 /* 2022 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1125 /* 2026 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1126 /* 2031 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1127 /* 2036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1128 /* 2040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1129 /* 2042 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1130 /* 2042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1131 /* 2045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1132 /* 2047 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1133 /* 2049 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1134 /* 2053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1135 /* 2057 */ GIR_RootConstrainSelectedInstOperands,
1136 /* 2058 */ // GIR_Coverage, 2540,
1137 /* 2058 */ GIR_EraseRootFromParent_Done,
1138 /* 2059 */ // Label 120: @2059
1139 /* 2059 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2116), // Rule ID 865 //
1140 /* 2064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1141 /* 2067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1142 /* 2071 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1143 /* 2075 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1144 /* 2079 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1145 /* 2083 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1146 /* 2087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1147 /* 2092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1148 /* 2097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1149 /* 2099 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1150 /* 2099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1151 /* 2102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1152 /* 2104 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1153 /* 2106 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1154 /* 2110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1155 /* 2114 */ GIR_RootConstrainSelectedInstOperands,
1156 /* 2115 */ // GIR_Coverage, 865,
1157 /* 2115 */ GIR_EraseRootFromParent_Done,
1158 /* 2116 */ // Label 121: @2116
1159 /* 2116 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2139), // Rule ID 532 //
1160 /* 2121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1161 /* 2124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1162 /* 2128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1163 /* 2132 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1164 /* 2132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1165 /* 2137 */ GIR_RootConstrainSelectedInstOperands,
1166 /* 2138 */ // GIR_Coverage, 532,
1167 /* 2138 */ GIR_Done,
1168 /* 2139 */ // Label 122: @2139
1169 /* 2139 */ GIM_Reject,
1170 /* 2140 */ // Label 119: @2140
1171 /* 2140 */ GIM_Reject,
1172 /* 2141 */ // Label 92: @2141
1173 /* 2141 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2294),
1174 /* 2146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1175 /* 2149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1176 /* 2152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1177 /* 2156 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2213), // Rule ID 2539 //
1178 /* 2161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1179 /* 2164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1180 /* 2168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1181 /* 2172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1182 /* 2176 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1183 /* 2180 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1184 /* 2185 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1185 /* 2190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1186 /* 2194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1187 /* 2196 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1188 /* 2196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1189 /* 2199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1190 /* 2201 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1191 /* 2203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1192 /* 2207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1193 /* 2211 */ GIR_RootConstrainSelectedInstOperands,
1194 /* 2212 */ // GIR_Coverage, 2539,
1195 /* 2212 */ GIR_EraseRootFromParent_Done,
1196 /* 2213 */ // Label 124: @2213
1197 /* 2213 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2270), // Rule ID 864 //
1198 /* 2218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1199 /* 2221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1200 /* 2225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1201 /* 2229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1202 /* 2233 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1203 /* 2237 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1204 /* 2241 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1205 /* 2246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1206 /* 2251 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1207 /* 2253 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1208 /* 2253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1209 /* 2256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1210 /* 2258 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1211 /* 2260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1212 /* 2264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1213 /* 2268 */ GIR_RootConstrainSelectedInstOperands,
1214 /* 2269 */ // GIR_Coverage, 864,
1215 /* 2269 */ GIR_EraseRootFromParent_Done,
1216 /* 2270 */ // Label 125: @2270
1217 /* 2270 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2293), // Rule ID 531 //
1218 /* 2275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1219 /* 2278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1220 /* 2282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1221 /* 2286 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1222 /* 2286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1223 /* 2291 */ GIR_RootConstrainSelectedInstOperands,
1224 /* 2292 */ // GIR_Coverage, 531,
1225 /* 2292 */ GIR_Done,
1226 /* 2293 */ // Label 126: @2293
1227 /* 2293 */ GIM_Reject,
1228 /* 2294 */ // Label 123: @2294
1229 /* 2294 */ GIM_Reject,
1230 /* 2295 */ // Label 93: @2295
1231 /* 2295 */ GIM_Reject,
1232 /* 2296 */ // Label 1: @2296
1233 /* 2296 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 135*/ GIMT_Encode4(2986),
1234 /* 2307 */ /*GILLT_s32*//*Label 127*/ GIMT_Encode4(2339),
1235 /* 2311 */ /*GILLT_s64*//*Label 128*/ GIMT_Encode4(2516),
1236 /* 2315 */ /*GILLT_v2s16*//*Label 129*/ GIMT_Encode4(2550),
1237 /* 2319 */ /*GILLT_v2s64*//*Label 130*/ GIMT_Encode4(2582),
1238 /* 2323 */ /*GILLT_v4s8*//*Label 131*/ GIMT_Encode4(2675),
1239 /* 2327 */ /*GILLT_v4s32*//*Label 132*/ GIMT_Encode4(2707),
1240 /* 2331 */ /*GILLT_v8s16*//*Label 133*/ GIMT_Encode4(2800),
1241 /* 2335 */ /*GILLT_v16s8*//*Label 134*/ GIMT_Encode4(2893),
1242 /* 2339 */ // Label 127: @2339
1243 /* 2339 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2515),
1244 /* 2344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1245 /* 2347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1246 /* 2350 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2379), // Rule ID 1952 //
1247 /* 2355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1248 /* 2358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1249 /* 2362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1250 /* 2366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1251 /* 2370 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1252 /* 2370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1253 /* 2373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1254 /* 2375 */ GIR_RootToRootCopy, /*OpIdx*/2, // r
1255 /* 2377 */ GIR_RootConstrainSelectedInstOperands,
1256 /* 2378 */ // GIR_Coverage, 1952,
1257 /* 2378 */ GIR_EraseRootFromParent_Done,
1258 /* 2379 */ // Label 137: @2379
1259 /* 2379 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(2406), // Rule ID 1233 //
1260 /* 2384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1261 /* 2387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1262 /* 2391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1263 /* 2395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1264 /* 2399 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1265 /* 2399 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1266 /* 2404 */ GIR_RootConstrainSelectedInstOperands,
1267 /* 2405 */ // GIR_Coverage, 1233,
1268 /* 2405 */ GIR_Done,
1269 /* 2406 */ // Label 138: @2406
1270 /* 2406 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(2433), // Rule ID 47 //
1271 /* 2411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
1272 /* 2414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1273 /* 2418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1274 /* 2422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1275 /* 2426 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1276 /* 2426 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1277 /* 2431 */ GIR_RootConstrainSelectedInstOperands,
1278 /* 2432 */ // GIR_Coverage, 47,
1279 /* 2432 */ GIR_Done,
1280 /* 2433 */ // Label 139: @2433
1281 /* 2433 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(2460), // Rule ID 1088 //
1282 /* 2438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1283 /* 2441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1284 /* 2445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1285 /* 2449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1286 /* 2453 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1287 /* 2453 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1288 /* 2458 */ GIR_RootConstrainSelectedInstOperands,
1289 /* 2459 */ // GIR_Coverage, 1088,
1290 /* 2459 */ GIR_Done,
1291 /* 2460 */ // Label 140: @2460
1292 /* 2460 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2487), // Rule ID 1097 //
1293 /* 2465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1294 /* 2468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1295 /* 2472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1296 /* 2476 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1297 /* 2480 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1298 /* 2480 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1299 /* 2485 */ GIR_RootConstrainSelectedInstOperands,
1300 /* 2486 */ // GIR_Coverage, 1097,
1301 /* 2486 */ GIR_Done,
1302 /* 2487 */ // Label 141: @2487
1303 /* 2487 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2514), // Rule ID 1957 //
1304 /* 2492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1305 /* 2495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1306 /* 2499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1307 /* 2503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1308 /* 2507 */ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1309 /* 2507 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1310 /* 2512 */ GIR_RootConstrainSelectedInstOperands,
1311 /* 2513 */ // GIR_Coverage, 1957,
1312 /* 2513 */ GIR_Done,
1313 /* 2514 */ // Label 142: @2514
1314 /* 2514 */ GIM_Reject,
1315 /* 2515 */ // Label 136: @2515
1316 /* 2515 */ GIM_Reject,
1317 /* 2516 */ // Label 128: @2516
1318 /* 2516 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2549), // Rule ID 227 //
1319 /* 2521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
1320 /* 2524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1321 /* 2527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1322 /* 2530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1323 /* 2534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1324 /* 2538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1325 /* 2542 */ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1326 /* 2542 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1327 /* 2547 */ GIR_RootConstrainSelectedInstOperands,
1328 /* 2548 */ // GIR_Coverage, 227,
1329 /* 2548 */ GIR_Done,
1330 /* 2549 */ // Label 143: @2549
1331 /* 2549 */ GIM_Reject,
1332 /* 2550 */ // Label 129: @2550
1333 /* 2550 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2581), // Rule ID 2054 //
1334 /* 2555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1335 /* 2558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1336 /* 2561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1337 /* 2564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1338 /* 2568 */ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1339 /* 2568 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1340 /* 2573 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1341 /* 2579 */ GIR_RootConstrainSelectedInstOperands,
1342 /* 2580 */ // GIR_Coverage, 2054,
1343 /* 2580 */ GIR_Done,
1344 /* 2581 */ // Label 144: @2581
1345 /* 2581 */ GIM_Reject,
1346 /* 2582 */ // Label 130: @2582
1347 /* 2582 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2674),
1348 /* 2587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1349 /* 2590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1350 /* 2593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1351 /* 2597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1352 /* 2601 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2654), // Rule ID 923 //
1353 /* 2606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1354 /* 2609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1355 /* 2613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1356 /* 2617 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1357 /* 2621 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1358 /* 2625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1359 /* 2630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1360 /* 2635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1361 /* 2637 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1362 /* 2637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1363 /* 2640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1364 /* 2642 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1365 /* 2644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1366 /* 2648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1367 /* 2652 */ GIR_RootConstrainSelectedInstOperands,
1368 /* 2653 */ // GIR_Coverage, 923,
1369 /* 2653 */ GIR_EraseRootFromParent_Done,
1370 /* 2654 */ // Label 146: @2654
1371 /* 2654 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2673), // Rule ID 1052 //
1372 /* 2659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1373 /* 2662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1374 /* 2666 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1375 /* 2666 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1376 /* 2671 */ GIR_RootConstrainSelectedInstOperands,
1377 /* 2672 */ // GIR_Coverage, 1052,
1378 /* 2672 */ GIR_Done,
1379 /* 2673 */ // Label 147: @2673
1380 /* 2673 */ GIM_Reject,
1381 /* 2674 */ // Label 145: @2674
1382 /* 2674 */ GIM_Reject,
1383 /* 2675 */ // Label 131: @2675
1384 /* 2675 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2706), // Rule ID 2060 //
1385 /* 2680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1386 /* 2683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1387 /* 2686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1388 /* 2689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1389 /* 2693 */ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1390 /* 2693 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1391 /* 2698 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1392 /* 2704 */ GIR_RootConstrainSelectedInstOperands,
1393 /* 2705 */ // GIR_Coverage, 2060,
1394 /* 2705 */ GIR_Done,
1395 /* 2706 */ // Label 148: @2706
1396 /* 2706 */ GIM_Reject,
1397 /* 2707 */ // Label 132: @2707
1398 /* 2707 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2799),
1399 /* 2712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1400 /* 2715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1401 /* 2718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1402 /* 2722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1403 /* 2726 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2779), // Rule ID 922 //
1404 /* 2731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1405 /* 2734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1406 /* 2738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1407 /* 2742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1408 /* 2746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1409 /* 2750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1410 /* 2755 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1411 /* 2760 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1412 /* 2762 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1413 /* 2762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1414 /* 2765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1415 /* 2767 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1416 /* 2769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1417 /* 2773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1418 /* 2777 */ GIR_RootConstrainSelectedInstOperands,
1419 /* 2778 */ // GIR_Coverage, 922,
1420 /* 2778 */ GIR_EraseRootFromParent_Done,
1421 /* 2779 */ // Label 150: @2779
1422 /* 2779 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2798), // Rule ID 1051 //
1423 /* 2784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1424 /* 2787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1425 /* 2791 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1426 /* 2791 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1427 /* 2796 */ GIR_RootConstrainSelectedInstOperands,
1428 /* 2797 */ // GIR_Coverage, 1051,
1429 /* 2797 */ GIR_Done,
1430 /* 2798 */ // Label 151: @2798
1431 /* 2798 */ GIM_Reject,
1432 /* 2799 */ // Label 149: @2799
1433 /* 2799 */ GIM_Reject,
1434 /* 2800 */ // Label 133: @2800
1435 /* 2800 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2892),
1436 /* 2805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1437 /* 2808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1438 /* 2811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1439 /* 2815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1440 /* 2819 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2872), // Rule ID 921 //
1441 /* 2824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1442 /* 2827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1443 /* 2831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1444 /* 2835 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1445 /* 2839 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1446 /* 2843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1447 /* 2848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1448 /* 2853 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1449 /* 2855 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1450 /* 2855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1451 /* 2858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1452 /* 2860 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1453 /* 2862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1454 /* 2866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1455 /* 2870 */ GIR_RootConstrainSelectedInstOperands,
1456 /* 2871 */ // GIR_Coverage, 921,
1457 /* 2871 */ GIR_EraseRootFromParent_Done,
1458 /* 2872 */ // Label 153: @2872
1459 /* 2872 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2891), // Rule ID 1050 //
1460 /* 2877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1461 /* 2880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1462 /* 2884 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1463 /* 2884 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1464 /* 2889 */ GIR_RootConstrainSelectedInstOperands,
1465 /* 2890 */ // GIR_Coverage, 1050,
1466 /* 2890 */ GIR_Done,
1467 /* 2891 */ // Label 154: @2891
1468 /* 2891 */ GIM_Reject,
1469 /* 2892 */ // Label 152: @2892
1470 /* 2892 */ GIM_Reject,
1471 /* 2893 */ // Label 134: @2893
1472 /* 2893 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2985),
1473 /* 2898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1474 /* 2901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1475 /* 2904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1476 /* 2908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1477 /* 2912 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2965), // Rule ID 920 //
1478 /* 2917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1479 /* 2920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1480 /* 2924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1481 /* 2928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1482 /* 2932 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1483 /* 2936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1484 /* 2941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1485 /* 2946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1486 /* 2948 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1487 /* 2948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1488 /* 2951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1489 /* 2953 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1490 /* 2955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1491 /* 2959 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1492 /* 2963 */ GIR_RootConstrainSelectedInstOperands,
1493 /* 2964 */ // GIR_Coverage, 920,
1494 /* 2964 */ GIR_EraseRootFromParent_Done,
1495 /* 2965 */ // Label 156: @2965
1496 /* 2965 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2984), // Rule ID 1049 //
1497 /* 2970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1498 /* 2973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1499 /* 2977 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1500 /* 2977 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1501 /* 2982 */ GIR_RootConstrainSelectedInstOperands,
1502 /* 2983 */ // GIR_Coverage, 1049,
1503 /* 2983 */ GIR_Done,
1504 /* 2984 */ // Label 157: @2984
1505 /* 2984 */ GIM_Reject,
1506 /* 2985 */ // Label 155: @2985
1507 /* 2985 */ GIM_Reject,
1508 /* 2986 */ // Label 135: @2986
1509 /* 2986 */ GIM_Reject,
1510 /* 2987 */ // Label 2: @2987
1511 /* 2987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 165*/ GIMT_Encode4(3467),
1512 /* 2998 */ /*GILLT_s32*//*Label 158*/ GIMT_Encode4(3030),
1513 /* 3002 */ /*GILLT_s64*//*Label 159*/ GIMT_Encode4(3214),
1514 /* 3006 */ /*GILLT_v2s16*//*Label 160*/ GIMT_Encode4(3299),
1515 /* 3010 */ /*GILLT_v2s64*//*Label 161*/ GIMT_Encode4(3331), GIMT_Encode4(0),
1516 /* 3018 */ /*GILLT_v4s32*//*Label 162*/ GIMT_Encode4(3365),
1517 /* 3022 */ /*GILLT_v8s16*//*Label 163*/ GIMT_Encode4(3399),
1518 /* 3026 */ /*GILLT_v16s8*//*Label 164*/ GIMT_Encode4(3433),
1519 /* 3030 */ // Label 158: @3030
1520 /* 3030 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3213),
1521 /* 3035 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1522 /* 3038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1523 /* 3041 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3080), // Rule ID 48 //
1524 /* 3046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
1525 /* 3049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1526 /* 3053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1527 /* 3057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1528 /* 3061 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1529 /* 3061 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1530 /* 3066 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1531 /* 3072 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1532 /* 3078 */ GIR_RootConstrainSelectedInstOperands,
1533 /* 3079 */ // GIR_Coverage, 48,
1534 /* 3079 */ GIR_Done,
1535 /* 3080 */ // Label 167: @3080
1536 /* 3080 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3107), // Rule ID 356 //
1537 /* 3085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1538 /* 3088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1539 /* 3092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1540 /* 3096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1541 /* 3100 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1542 /* 3100 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1543 /* 3105 */ GIR_RootConstrainSelectedInstOperands,
1544 /* 3106 */ // GIR_Coverage, 356,
1545 /* 3106 */ GIR_Done,
1546 /* 3107 */ // Label 168: @3107
1547 /* 3107 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3146), // Rule ID 1098 //
1548 /* 3112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1549 /* 3115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1550 /* 3119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1551 /* 3123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1552 /* 3127 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1553 /* 3127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1554 /* 3132 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1555 /* 3138 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1556 /* 3144 */ GIR_RootConstrainSelectedInstOperands,
1557 /* 3145 */ // GIR_Coverage, 1098,
1558 /* 3145 */ GIR_Done,
1559 /* 3146 */ // Label 169: @3146
1560 /* 3146 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3173), // Rule ID 1202 //
1561 /* 3151 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1562 /* 3154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1563 /* 3158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1564 /* 3162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1565 /* 3166 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1566 /* 3166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1567 /* 3171 */ GIR_RootConstrainSelectedInstOperands,
1568 /* 3172 */ // GIR_Coverage, 1202,
1569 /* 3172 */ GIR_Done,
1570 /* 3173 */ // Label 170: @3173
1571 /* 3173 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3212), // Rule ID 1955 //
1572 /* 3178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1573 /* 3181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1574 /* 3185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1575 /* 3189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1576 /* 3193 */ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1577 /* 3193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1578 /* 3198 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1579 /* 3204 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1580 /* 3210 */ GIR_RootConstrainSelectedInstOperands,
1581 /* 3211 */ // GIR_Coverage, 1955,
1582 /* 3211 */ GIR_Done,
1583 /* 3212 */ // Label 171: @3212
1584 /* 3212 */ GIM_Reject,
1585 /* 3213 */ // Label 166: @3213
1586 /* 3213 */ GIM_Reject,
1587 /* 3214 */ // Label 159: @3214
1588 /* 3214 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3298),
1589 /* 3219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1590 /* 3222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1591 /* 3225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1592 /* 3229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1593 /* 3233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1594 /* 3237 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3282), // Rule ID 298 //
1595 /* 3242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
1596 /* 3245 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1597 /* 3245 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1598 /* 3250 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1599 /* 3256 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1600 /* 3262 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1601 /* 3268 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1602 /* 3274 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1603 /* 3280 */ GIR_RootConstrainSelectedInstOperands,
1604 /* 3281 */ // GIR_Coverage, 298,
1605 /* 3281 */ GIR_Done,
1606 /* 3282 */ // Label 173: @3282
1607 /* 3282 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3297), // Rule ID 371 //
1608 /* 3287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1609 /* 3290 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1610 /* 3290 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1611 /* 3295 */ GIR_RootConstrainSelectedInstOperands,
1612 /* 3296 */ // GIR_Coverage, 371,
1613 /* 3296 */ GIR_Done,
1614 /* 3297 */ // Label 174: @3297
1615 /* 3297 */ GIM_Reject,
1616 /* 3298 */ // Label 172: @3298
1617 /* 3298 */ GIM_Reject,
1618 /* 3299 */ // Label 160: @3299
1619 /* 3299 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(3330), // Rule ID 2056 //
1620 /* 3304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
1621 /* 3307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1622 /* 3310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1623 /* 3313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1624 /* 3317 */ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1625 /* 3317 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1626 /* 3322 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1627 /* 3328 */ GIR_RootConstrainSelectedInstOperands,
1628 /* 3329 */ // GIR_Coverage, 2056,
1629 /* 3329 */ GIR_Done,
1630 /* 3330 */ // Label 175: @3330
1631 /* 3330 */ GIM_Reject,
1632 /* 3331 */ // Label 161: @3331
1633 /* 3331 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(3364), // Rule ID 931 //
1634 /* 3336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1635 /* 3339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1636 /* 3342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1637 /* 3345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1638 /* 3349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1639 /* 3353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1640 /* 3357 */ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1641 /* 3357 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1642 /* 3362 */ GIR_RootConstrainSelectedInstOperands,
1643 /* 3363 */ // GIR_Coverage, 931,
1644 /* 3363 */ GIR_Done,
1645 /* 3364 */ // Label 176: @3364
1646 /* 3364 */ GIM_Reject,
1647 /* 3365 */ // Label 162: @3365
1648 /* 3365 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(3398), // Rule ID 930 //
1649 /* 3370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1650 /* 3373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1651 /* 3376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1652 /* 3379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1653 /* 3383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1654 /* 3387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1655 /* 3391 */ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1656 /* 3391 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1657 /* 3396 */ GIR_RootConstrainSelectedInstOperands,
1658 /* 3397 */ // GIR_Coverage, 930,
1659 /* 3397 */ GIR_Done,
1660 /* 3398 */ // Label 177: @3398
1661 /* 3398 */ GIM_Reject,
1662 /* 3399 */ // Label 163: @3399
1663 /* 3399 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(3432), // Rule ID 929 //
1664 /* 3404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1665 /* 3407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1666 /* 3410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1667 /* 3413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1668 /* 3417 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1669 /* 3421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1670 /* 3425 */ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1671 /* 3425 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1672 /* 3430 */ GIR_RootConstrainSelectedInstOperands,
1673 /* 3431 */ // GIR_Coverage, 929,
1674 /* 3431 */ GIR_Done,
1675 /* 3432 */ // Label 178: @3432
1676 /* 3432 */ GIM_Reject,
1677 /* 3433 */ // Label 164: @3433
1678 /* 3433 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(3466), // Rule ID 928 //
1679 /* 3438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1680 /* 3441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1681 /* 3444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1682 /* 3447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1683 /* 3451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1684 /* 3455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1685 /* 3459 */ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1686 /* 3459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1687 /* 3464 */ GIR_RootConstrainSelectedInstOperands,
1688 /* 3465 */ // GIR_Coverage, 928,
1689 /* 3465 */ GIR_Done,
1690 /* 3466 */ // Label 179: @3466
1691 /* 3466 */ GIM_Reject,
1692 /* 3467 */ // Label 165: @3467
1693 /* 3467 */ GIM_Reject,
1694 /* 3468 */ // Label 3: @3468
1695 /* 3468 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 186*/ GIMT_Encode4(3736),
1696 /* 3479 */ /*GILLT_s32*//*Label 180*/ GIMT_Encode4(3511),
1697 /* 3483 */ /*GILLT_s64*//*Label 181*/ GIMT_Encode4(3566), GIMT_Encode4(0),
1698 /* 3491 */ /*GILLT_v2s64*//*Label 182*/ GIMT_Encode4(3600), GIMT_Encode4(0),
1699 /* 3499 */ /*GILLT_v4s32*//*Label 183*/ GIMT_Encode4(3634),
1700 /* 3503 */ /*GILLT_v8s16*//*Label 184*/ GIMT_Encode4(3668),
1701 /* 3507 */ /*GILLT_v16s8*//*Label 185*/ GIMT_Encode4(3702),
1702 /* 3511 */ // Label 180: @3511
1703 /* 3511 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3565),
1704 /* 3516 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1705 /* 3519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1706 /* 3522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1707 /* 3526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1708 /* 3530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1709 /* 3534 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3549), // Rule ID 350 //
1710 /* 3539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1711 /* 3542 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1712 /* 3542 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1713 /* 3547 */ GIR_RootConstrainSelectedInstOperands,
1714 /* 3548 */ // GIR_Coverage, 350,
1715 /* 3548 */ GIR_Done,
1716 /* 3549 */ // Label 188: @3549
1717 /* 3549 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3564), // Rule ID 1195 //
1718 /* 3554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1719 /* 3557 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1720 /* 3557 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1721 /* 3562 */ GIR_RootConstrainSelectedInstOperands,
1722 /* 3563 */ // GIR_Coverage, 1195,
1723 /* 3563 */ GIR_Done,
1724 /* 3564 */ // Label 189: @3564
1725 /* 3564 */ GIM_Reject,
1726 /* 3565 */ // Label 187: @3565
1727 /* 3565 */ GIM_Reject,
1728 /* 3566 */ // Label 181: @3566
1729 /* 3566 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(3599), // Rule ID 365 //
1730 /* 3571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1731 /* 3574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1732 /* 3577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1733 /* 3580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1734 /* 3584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1735 /* 3588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1736 /* 3592 */ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1737 /* 3592 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1738 /* 3597 */ GIR_RootConstrainSelectedInstOperands,
1739 /* 3598 */ // GIR_Coverage, 365,
1740 /* 3598 */ GIR_Done,
1741 /* 3599 */ // Label 190: @3599
1742 /* 3599 */ GIM_Reject,
1743 /* 3600 */ // Label 182: @3600
1744 /* 3600 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(3633), // Rule ID 671 //
1745 /* 3605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1746 /* 3608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1747 /* 3611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1748 /* 3614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1749 /* 3618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1750 /* 3622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1751 /* 3626 */ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1752 /* 3626 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1753 /* 3631 */ GIR_RootConstrainSelectedInstOperands,
1754 /* 3632 */ // GIR_Coverage, 671,
1755 /* 3632 */ GIR_Done,
1756 /* 3633 */ // Label 191: @3633
1757 /* 3633 */ GIM_Reject,
1758 /* 3634 */ // Label 183: @3634
1759 /* 3634 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(3667), // Rule ID 670 //
1760 /* 3639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1761 /* 3642 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1762 /* 3645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1763 /* 3648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1764 /* 3652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1765 /* 3656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1766 /* 3660 */ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1767 /* 3660 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1768 /* 3665 */ GIR_RootConstrainSelectedInstOperands,
1769 /* 3666 */ // GIR_Coverage, 670,
1770 /* 3666 */ GIR_Done,
1771 /* 3667 */ // Label 192: @3667
1772 /* 3667 */ GIM_Reject,
1773 /* 3668 */ // Label 184: @3668
1774 /* 3668 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(3701), // Rule ID 669 //
1775 /* 3673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1776 /* 3676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1777 /* 3679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1778 /* 3682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1779 /* 3686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1780 /* 3690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1781 /* 3694 */ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1782 /* 3694 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1783 /* 3699 */ GIR_RootConstrainSelectedInstOperands,
1784 /* 3700 */ // GIR_Coverage, 669,
1785 /* 3700 */ GIR_Done,
1786 /* 3701 */ // Label 193: @3701
1787 /* 3701 */ GIM_Reject,
1788 /* 3702 */ // Label 185: @3702
1789 /* 3702 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(3735), // Rule ID 668 //
1790 /* 3707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1791 /* 3710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1792 /* 3713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1793 /* 3716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1794 /* 3720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1795 /* 3724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1796 /* 3728 */ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1797 /* 3728 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1798 /* 3733 */ GIR_RootConstrainSelectedInstOperands,
1799 /* 3734 */ // GIR_Coverage, 668,
1800 /* 3734 */ GIR_Done,
1801 /* 3735 */ // Label 194: @3735
1802 /* 3735 */ GIM_Reject,
1803 /* 3736 */ // Label 186: @3736
1804 /* 3736 */ GIM_Reject,
1805 /* 3737 */ // Label 4: @3737
1806 /* 3737 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 201*/ GIMT_Encode4(4005),
1807 /* 3748 */ /*GILLT_s32*//*Label 195*/ GIMT_Encode4(3780),
1808 /* 3752 */ /*GILLT_s64*//*Label 196*/ GIMT_Encode4(3835), GIMT_Encode4(0),
1809 /* 3760 */ /*GILLT_v2s64*//*Label 197*/ GIMT_Encode4(3869), GIMT_Encode4(0),
1810 /* 3768 */ /*GILLT_v4s32*//*Label 198*/ GIMT_Encode4(3903),
1811 /* 3772 */ /*GILLT_v8s16*//*Label 199*/ GIMT_Encode4(3937),
1812 /* 3776 */ /*GILLT_v16s8*//*Label 200*/ GIMT_Encode4(3971),
1813 /* 3780 */ // Label 195: @3780
1814 /* 3780 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(3834),
1815 /* 3785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1816 /* 3788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1817 /* 3791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1818 /* 3795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1819 /* 3799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1820 /* 3803 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(3818), // Rule ID 351 //
1821 /* 3808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1822 /* 3811 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1823 /* 3811 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1824 /* 3816 */ GIR_RootConstrainSelectedInstOperands,
1825 /* 3817 */ // GIR_Coverage, 351,
1826 /* 3817 */ GIR_Done,
1827 /* 3818 */ // Label 203: @3818
1828 /* 3818 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(3833), // Rule ID 1196 //
1829 /* 3823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1830 /* 3826 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1831 /* 3826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1832 /* 3831 */ GIR_RootConstrainSelectedInstOperands,
1833 /* 3832 */ // GIR_Coverage, 1196,
1834 /* 3832 */ GIR_Done,
1835 /* 3833 */ // Label 204: @3833
1836 /* 3833 */ GIM_Reject,
1837 /* 3834 */ // Label 202: @3834
1838 /* 3834 */ GIM_Reject,
1839 /* 3835 */ // Label 196: @3835
1840 /* 3835 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(3868), // Rule ID 366 //
1841 /* 3840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1842 /* 3843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1843 /* 3846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1844 /* 3849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1845 /* 3853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1846 /* 3857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1847 /* 3861 */ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1848 /* 3861 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1849 /* 3866 */ GIR_RootConstrainSelectedInstOperands,
1850 /* 3867 */ // GIR_Coverage, 366,
1851 /* 3867 */ GIR_Done,
1852 /* 3868 */ // Label 205: @3868
1853 /* 3868 */ GIM_Reject,
1854 /* 3869 */ // Label 197: @3869
1855 /* 3869 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(3902), // Rule ID 675 //
1856 /* 3874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1857 /* 3877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1858 /* 3880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1859 /* 3883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1860 /* 3887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1861 /* 3891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1862 /* 3895 */ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1863 /* 3895 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1864 /* 3900 */ GIR_RootConstrainSelectedInstOperands,
1865 /* 3901 */ // GIR_Coverage, 675,
1866 /* 3901 */ GIR_Done,
1867 /* 3902 */ // Label 206: @3902
1868 /* 3902 */ GIM_Reject,
1869 /* 3903 */ // Label 198: @3903
1870 /* 3903 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(3936), // Rule ID 674 //
1871 /* 3908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1872 /* 3911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1873 /* 3914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1874 /* 3917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1875 /* 3921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1876 /* 3925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1877 /* 3929 */ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1878 /* 3929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1879 /* 3934 */ GIR_RootConstrainSelectedInstOperands,
1880 /* 3935 */ // GIR_Coverage, 674,
1881 /* 3935 */ GIR_Done,
1882 /* 3936 */ // Label 207: @3936
1883 /* 3936 */ GIM_Reject,
1884 /* 3937 */ // Label 199: @3937
1885 /* 3937 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(3970), // Rule ID 673 //
1886 /* 3942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1887 /* 3945 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1888 /* 3948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1889 /* 3951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1890 /* 3955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1891 /* 3959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1892 /* 3963 */ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1893 /* 3963 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1894 /* 3968 */ GIR_RootConstrainSelectedInstOperands,
1895 /* 3969 */ // GIR_Coverage, 673,
1896 /* 3969 */ GIR_Done,
1897 /* 3970 */ // Label 208: @3970
1898 /* 3970 */ GIM_Reject,
1899 /* 3971 */ // Label 200: @3971
1900 /* 3971 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(4004), // Rule ID 672 //
1901 /* 3976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1902 /* 3979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1903 /* 3982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1904 /* 3985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1905 /* 3989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1906 /* 3993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1907 /* 3997 */ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1908 /* 3997 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1909 /* 4002 */ GIR_RootConstrainSelectedInstOperands,
1910 /* 4003 */ // GIR_Coverage, 672,
1911 /* 4003 */ GIR_Done,
1912 /* 4004 */ // Label 209: @4004
1913 /* 4004 */ GIM_Reject,
1914 /* 4005 */ // Label 201: @4005
1915 /* 4005 */ GIM_Reject,
1916 /* 4006 */ // Label 5: @4006
1917 /* 4006 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 216*/ GIMT_Encode4(4274),
1918 /* 4017 */ /*GILLT_s32*//*Label 210*/ GIMT_Encode4(4049),
1919 /* 4021 */ /*GILLT_s64*//*Label 211*/ GIMT_Encode4(4104), GIMT_Encode4(0),
1920 /* 4029 */ /*GILLT_v2s64*//*Label 212*/ GIMT_Encode4(4138), GIMT_Encode4(0),
1921 /* 4037 */ /*GILLT_v4s32*//*Label 213*/ GIMT_Encode4(4172),
1922 /* 4041 */ /*GILLT_v8s16*//*Label 214*/ GIMT_Encode4(4206),
1923 /* 4045 */ /*GILLT_v16s8*//*Label 215*/ GIMT_Encode4(4240),
1924 /* 4049 */ // Label 210: @4049
1925 /* 4049 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4103),
1926 /* 4054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1927 /* 4057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1928 /* 4060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1929 /* 4064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1930 /* 4068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1931 /* 4072 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4087), // Rule ID 352 //
1932 /* 4077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1933 /* 4080 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1934 /* 4080 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1935 /* 4085 */ GIR_RootConstrainSelectedInstOperands,
1936 /* 4086 */ // GIR_Coverage, 352,
1937 /* 4086 */ GIR_Done,
1938 /* 4087 */ // Label 218: @4087
1939 /* 4087 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4102), // Rule ID 1200 //
1940 /* 4092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1941 /* 4095 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1942 /* 4095 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1943 /* 4100 */ GIR_RootConstrainSelectedInstOperands,
1944 /* 4101 */ // GIR_Coverage, 1200,
1945 /* 4101 */ GIR_Done,
1946 /* 4102 */ // Label 219: @4102
1947 /* 4102 */ GIM_Reject,
1948 /* 4103 */ // Label 217: @4103
1949 /* 4103 */ GIM_Reject,
1950 /* 4104 */ // Label 211: @4104
1951 /* 4104 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(4137), // Rule ID 367 //
1952 /* 4109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1953 /* 4112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1954 /* 4115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1955 /* 4118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1956 /* 4122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1957 /* 4126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1958 /* 4130 */ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1959 /* 4130 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1960 /* 4135 */ GIR_RootConstrainSelectedInstOperands,
1961 /* 4136 */ // GIR_Coverage, 367,
1962 /* 4136 */ GIR_Done,
1963 /* 4137 */ // Label 220: @4137
1964 /* 4137 */ GIM_Reject,
1965 /* 4138 */ // Label 212: @4138
1966 /* 4138 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(4171), // Rule ID 911 //
1967 /* 4143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1968 /* 4146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1969 /* 4149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1970 /* 4152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1971 /* 4156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1972 /* 4160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1973 /* 4164 */ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1974 /* 4164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
1975 /* 4169 */ GIR_RootConstrainSelectedInstOperands,
1976 /* 4170 */ // GIR_Coverage, 911,
1977 /* 4170 */ GIR_Done,
1978 /* 4171 */ // Label 221: @4171
1979 /* 4171 */ GIM_Reject,
1980 /* 4172 */ // Label 213: @4172
1981 /* 4172 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(4205), // Rule ID 910 //
1982 /* 4177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1983 /* 4180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1984 /* 4183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1985 /* 4186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1986 /* 4190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1987 /* 4194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1988 /* 4198 */ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1989 /* 4198 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
1990 /* 4203 */ GIR_RootConstrainSelectedInstOperands,
1991 /* 4204 */ // GIR_Coverage, 910,
1992 /* 4204 */ GIR_Done,
1993 /* 4205 */ // Label 222: @4205
1994 /* 4205 */ GIM_Reject,
1995 /* 4206 */ // Label 214: @4206
1996 /* 4206 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(4239), // Rule ID 909 //
1997 /* 4211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1998 /* 4214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1999 /* 4217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2000 /* 4220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2001 /* 4224 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2002 /* 4228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2003 /* 4232 */ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2004 /* 4232 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
2005 /* 4237 */ GIR_RootConstrainSelectedInstOperands,
2006 /* 4238 */ // GIR_Coverage, 909,
2007 /* 4238 */ GIR_Done,
2008 /* 4239 */ // Label 223: @4239
2009 /* 4239 */ GIM_Reject,
2010 /* 4240 */ // Label 215: @4240
2011 /* 4240 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(4273), // Rule ID 908 //
2012 /* 4245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2013 /* 4248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2014 /* 4251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2015 /* 4254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2016 /* 4258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2017 /* 4262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2018 /* 4266 */ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2019 /* 4266 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
2020 /* 4271 */ GIR_RootConstrainSelectedInstOperands,
2021 /* 4272 */ // GIR_Coverage, 908,
2022 /* 4272 */ GIR_Done,
2023 /* 4273 */ // Label 224: @4273
2024 /* 4273 */ GIM_Reject,
2025 /* 4274 */ // Label 216: @4274
2026 /* 4274 */ GIM_Reject,
2027 /* 4275 */ // Label 6: @4275
2028 /* 4275 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 231*/ GIMT_Encode4(4543),
2029 /* 4286 */ /*GILLT_s32*//*Label 225*/ GIMT_Encode4(4318),
2030 /* 4290 */ /*GILLT_s64*//*Label 226*/ GIMT_Encode4(4373), GIMT_Encode4(0),
2031 /* 4298 */ /*GILLT_v2s64*//*Label 227*/ GIMT_Encode4(4407), GIMT_Encode4(0),
2032 /* 4306 */ /*GILLT_v4s32*//*Label 228*/ GIMT_Encode4(4441),
2033 /* 4310 */ /*GILLT_v8s16*//*Label 229*/ GIMT_Encode4(4475),
2034 /* 4314 */ /*GILLT_v16s8*//*Label 230*/ GIMT_Encode4(4509),
2035 /* 4318 */ // Label 225: @4318
2036 /* 4318 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4372),
2037 /* 4323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2038 /* 4326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2039 /* 4329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2040 /* 4333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2041 /* 4337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2042 /* 4341 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4356), // Rule ID 353 //
2043 /* 4346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
2044 /* 4349 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2045 /* 4349 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2046 /* 4354 */ GIR_RootConstrainSelectedInstOperands,
2047 /* 4355 */ // GIR_Coverage, 353,
2048 /* 4355 */ GIR_Done,
2049 /* 4356 */ // Label 233: @4356
2050 /* 4356 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4371), // Rule ID 1201 //
2051 /* 4361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2052 /* 4364 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2053 /* 4364 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2054 /* 4369 */ GIR_RootConstrainSelectedInstOperands,
2055 /* 4370 */ // GIR_Coverage, 1201,
2056 /* 4370 */ GIR_Done,
2057 /* 4371 */ // Label 234: @4371
2058 /* 4371 */ GIM_Reject,
2059 /* 4372 */ // Label 232: @4372
2060 /* 4372 */ GIM_Reject,
2061 /* 4373 */ // Label 226: @4373
2062 /* 4373 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4406), // Rule ID 368 //
2063 /* 4378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
2064 /* 4381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2065 /* 4384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2066 /* 4387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2067 /* 4391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2068 /* 4395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2069 /* 4399 */ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2070 /* 4399 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2071 /* 4404 */ GIR_RootConstrainSelectedInstOperands,
2072 /* 4405 */ // GIR_Coverage, 368,
2073 /* 4405 */ GIR_Done,
2074 /* 4406 */ // Label 235: @4406
2075 /* 4406 */ GIM_Reject,
2076 /* 4407 */ // Label 227: @4407
2077 /* 4407 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4440), // Rule ID 915 //
2078 /* 4412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2079 /* 4415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2080 /* 4418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2081 /* 4421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2082 /* 4425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2083 /* 4429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2084 /* 4433 */ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2085 /* 4433 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2086 /* 4438 */ GIR_RootConstrainSelectedInstOperands,
2087 /* 4439 */ // GIR_Coverage, 915,
2088 /* 4439 */ GIR_Done,
2089 /* 4440 */ // Label 236: @4440
2090 /* 4440 */ GIM_Reject,
2091 /* 4441 */ // Label 228: @4441
2092 /* 4441 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4474), // Rule ID 914 //
2093 /* 4446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2094 /* 4449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2095 /* 4452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2096 /* 4455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2097 /* 4459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2098 /* 4463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2099 /* 4467 */ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2100 /* 4467 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2101 /* 4472 */ GIR_RootConstrainSelectedInstOperands,
2102 /* 4473 */ // GIR_Coverage, 914,
2103 /* 4473 */ GIR_Done,
2104 /* 4474 */ // Label 237: @4474
2105 /* 4474 */ GIM_Reject,
2106 /* 4475 */ // Label 229: @4475
2107 /* 4475 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4508), // Rule ID 913 //
2108 /* 4480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2109 /* 4483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2110 /* 4486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2111 /* 4489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2112 /* 4493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2113 /* 4497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2114 /* 4501 */ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2115 /* 4501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2116 /* 4506 */ GIR_RootConstrainSelectedInstOperands,
2117 /* 4507 */ // GIR_Coverage, 913,
2118 /* 4507 */ GIR_Done,
2119 /* 4508 */ // Label 238: @4508
2120 /* 4508 */ GIM_Reject,
2121 /* 4509 */ // Label 230: @4509
2122 /* 4509 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4542), // Rule ID 912 //
2123 /* 4514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2124 /* 4517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2125 /* 4520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2126 /* 4523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2127 /* 4527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2128 /* 4531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2129 /* 4535 */ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2130 /* 4535 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2131 /* 4540 */ GIR_RootConstrainSelectedInstOperands,
2132 /* 4541 */ // GIR_Coverage, 912,
2133 /* 4541 */ GIR_Done,
2134 /* 4542 */ // Label 239: @4542
2135 /* 4542 */ GIM_Reject,
2136 /* 4543 */ // Label 231: @4543
2137 /* 4543 */ GIM_Reject,
2138 /* 4544 */ // Label 7: @4544
2139 /* 4544 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 246*/ GIMT_Encode4(5099),
2140 /* 4555 */ /*GILLT_s32*//*Label 240*/ GIMT_Encode4(4587),
2141 /* 4559 */ /*GILLT_s64*//*Label 241*/ GIMT_Encode4(4861), GIMT_Encode4(0),
2142 /* 4567 */ /*GILLT_v2s64*//*Label 242*/ GIMT_Encode4(4963), GIMT_Encode4(0),
2143 /* 4575 */ /*GILLT_v4s32*//*Label 243*/ GIMT_Encode4(4997),
2144 /* 4579 */ /*GILLT_v8s16*//*Label 244*/ GIMT_Encode4(5031),
2145 /* 4583 */ /*GILLT_v16s8*//*Label 245*/ GIMT_Encode4(5065),
2146 /* 4587 */ // Label 240: @4587
2147 /* 4587 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(4860),
2148 /* 4592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2149 /* 4595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2150 /* 4598 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4640), // Rule ID 41 //
2151 /* 4603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2152 /* 4606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2153 /* 4610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2154 /* 4614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2155 /* 4618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2156 /* 4622 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2157 /* 4626 */ // MIs[1] Operand 1
2158 /* 4626 */ // No operand predicates
2159 /* 4626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2160 /* 4628 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2161 /* 4628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2162 /* 4631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2163 /* 4633 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2164 /* 4635 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2165 /* 4638 */ GIR_RootConstrainSelectedInstOperands,
2166 /* 4639 */ // GIR_Coverage, 41,
2167 /* 4639 */ GIR_EraseRootFromParent_Done,
2168 /* 4640 */ // Label 248: @4640
2169 /* 4640 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4682), // Rule ID 2298 //
2170 /* 4645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2171 /* 4648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2172 /* 4652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2173 /* 4656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2174 /* 4660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2175 /* 4664 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2176 /* 4668 */ // MIs[1] Operand 1
2177 /* 4668 */ // No operand predicates
2178 /* 4668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2179 /* 4670 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2180 /* 4670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2181 /* 4673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2182 /* 4675 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2183 /* 4677 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2184 /* 4680 */ GIR_RootConstrainSelectedInstOperands,
2185 /* 4681 */ // GIR_Coverage, 2298,
2186 /* 4681 */ GIR_EraseRootFromParent_Done,
2187 /* 4682 */ // Label 249: @4682
2188 /* 4682 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4724), // Rule ID 2462 //
2189 /* 4687 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2190 /* 4690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2191 /* 4694 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2192 /* 4698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2193 /* 4702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2194 /* 4706 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2195 /* 4710 */ // MIs[1] Operand 1
2196 /* 4710 */ // No operand predicates
2197 /* 4710 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2198 /* 4712 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2199 /* 4712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2200 /* 4715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2201 /* 4717 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2202 /* 4719 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2203 /* 4722 */ GIR_RootConstrainSelectedInstOperands,
2204 /* 4723 */ // GIR_Coverage, 2462,
2205 /* 4723 */ GIR_EraseRootFromParent_Done,
2206 /* 4724 */ // Label 250: @4724
2207 /* 4724 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4751), // Rule ID 51 //
2208 /* 4729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2209 /* 4732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2210 /* 4736 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2211 /* 4740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2212 /* 4744 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2213 /* 4744 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2214 /* 4749 */ GIR_RootConstrainSelectedInstOperands,
2215 /* 4750 */ // GIR_Coverage, 51,
2216 /* 4750 */ GIR_Done,
2217 /* 4751 */ // Label 251: @4751
2218 /* 4751 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4778), // Rule ID 1085 //
2219 /* 4756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2220 /* 4759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2221 /* 4763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2222 /* 4767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2223 /* 4771 */ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2224 /* 4771 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2225 /* 4776 */ GIR_RootConstrainSelectedInstOperands,
2226 /* 4777 */ // GIR_Coverage, 1085,
2227 /* 4777 */ GIR_Done,
2228 /* 4778 */ // Label 252: @4778
2229 /* 4778 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4805), // Rule ID 1101 //
2230 /* 4783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2231 /* 4786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2232 /* 4790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2233 /* 4794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2234 /* 4798 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2235 /* 4798 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2236 /* 4803 */ GIR_RootConstrainSelectedInstOperands,
2237 /* 4804 */ // GIR_Coverage, 1101,
2238 /* 4804 */ GIR_Done,
2239 /* 4805 */ // Label 253: @4805
2240 /* 4805 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4832), // Rule ID 1193 //
2241 /* 4810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2242 /* 4813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2243 /* 4817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2244 /* 4821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2245 /* 4825 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2246 /* 4825 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2247 /* 4830 */ GIR_RootConstrainSelectedInstOperands,
2248 /* 4831 */ // GIR_Coverage, 1193,
2249 /* 4831 */ GIR_Done,
2250 /* 4832 */ // Label 254: @4832
2251 /* 4832 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4859), // Rule ID 1954 //
2252 /* 4837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2253 /* 4840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2254 /* 4844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2255 /* 4848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2256 /* 4852 */ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2257 /* 4852 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2258 /* 4857 */ GIR_RootConstrainSelectedInstOperands,
2259 /* 4858 */ // GIR_Coverage, 1954,
2260 /* 4858 */ GIR_Done,
2261 /* 4859 */ // Label 255: @4859
2262 /* 4859 */ GIM_Reject,
2263 /* 4860 */ // Label 247: @4860
2264 /* 4860 */ GIM_Reject,
2265 /* 4861 */ // Label 241: @4861
2266 /* 4861 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4962),
2267 /* 4866 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2268 /* 4869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2269 /* 4872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2270 /* 4876 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4938), // Rule ID 293 //
2271 /* 4881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
2272 /* 4884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2273 /* 4888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2274 /* 4892 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2275 /* 4896 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2276 /* 4900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2277 /* 4905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2278 /* 4910 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2279 /* 4921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2280 /* 4923 */ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2281 /* 4923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2282 /* 4926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2283 /* 4928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2284 /* 4932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2285 /* 4936 */ GIR_RootConstrainSelectedInstOperands,
2286 /* 4937 */ // GIR_Coverage, 293,
2287 /* 4937 */ GIR_EraseRootFromParent_Done,
2288 /* 4938 */ // Label 257: @4938
2289 /* 4938 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4961), // Rule ID 230 //
2290 /* 4943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2291 /* 4946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2292 /* 4950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2293 /* 4954 */ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2294 /* 4954 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2295 /* 4959 */ GIR_RootConstrainSelectedInstOperands,
2296 /* 4960 */ // GIR_Coverage, 230,
2297 /* 4960 */ GIR_Done,
2298 /* 4961 */ // Label 258: @4961
2299 /* 4961 */ GIM_Reject,
2300 /* 4962 */ // Label 256: @4962
2301 /* 4962 */ GIM_Reject,
2302 /* 4963 */ // Label 242: @4963
2303 /* 4963 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(4996), // Rule ID 542 //
2304 /* 4968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2305 /* 4971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2306 /* 4974 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2307 /* 4977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2308 /* 4981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2309 /* 4985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2310 /* 4989 */ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2311 /* 4989 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2312 /* 4994 */ GIR_RootConstrainSelectedInstOperands,
2313 /* 4995 */ // GIR_Coverage, 542,
2314 /* 4995 */ GIR_Done,
2315 /* 4996 */ // Label 259: @4996
2316 /* 4996 */ GIM_Reject,
2317 /* 4997 */ // Label 243: @4997
2318 /* 4997 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5030), // Rule ID 541 //
2319 /* 5002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2320 /* 5005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2321 /* 5008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2322 /* 5011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2323 /* 5015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2324 /* 5019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2325 /* 5023 */ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2326 /* 5023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2327 /* 5028 */ GIR_RootConstrainSelectedInstOperands,
2328 /* 5029 */ // GIR_Coverage, 541,
2329 /* 5029 */ GIR_Done,
2330 /* 5030 */ // Label 260: @5030
2331 /* 5030 */ GIM_Reject,
2332 /* 5031 */ // Label 244: @5031
2333 /* 5031 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5064), // Rule ID 540 //
2334 /* 5036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2335 /* 5039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2336 /* 5042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2337 /* 5045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2338 /* 5049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2339 /* 5053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2340 /* 5057 */ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2341 /* 5057 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2342 /* 5062 */ GIR_RootConstrainSelectedInstOperands,
2343 /* 5063 */ // GIR_Coverage, 540,
2344 /* 5063 */ GIR_Done,
2345 /* 5064 */ // Label 261: @5064
2346 /* 5064 */ GIM_Reject,
2347 /* 5065 */ // Label 245: @5065
2348 /* 5065 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(5098), // Rule ID 539 //
2349 /* 5070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2350 /* 5073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2351 /* 5076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2352 /* 5079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2353 /* 5083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2354 /* 5087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2355 /* 5091 */ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2356 /* 5091 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2357 /* 5096 */ GIR_RootConstrainSelectedInstOperands,
2358 /* 5097 */ // GIR_Coverage, 539,
2359 /* 5097 */ GIR_Done,
2360 /* 5098 */ // Label 262: @5098
2361 /* 5098 */ GIM_Reject,
2362 /* 5099 */ // Label 246: @5099
2363 /* 5099 */ GIM_Reject,
2364 /* 5100 */ // Label 8: @5100
2365 /* 5100 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 269*/ GIMT_Encode4(5503),
2366 /* 5111 */ /*GILLT_s32*//*Label 263*/ GIMT_Encode4(5143),
2367 /* 5115 */ /*GILLT_s64*//*Label 264*/ GIMT_Encode4(5333), GIMT_Encode4(0),
2368 /* 5123 */ /*GILLT_v2s64*//*Label 265*/ GIMT_Encode4(5367), GIMT_Encode4(0),
2369 /* 5131 */ /*GILLT_v4s32*//*Label 266*/ GIMT_Encode4(5401),
2370 /* 5135 */ /*GILLT_v8s16*//*Label 267*/ GIMT_Encode4(5435),
2371 /* 5139 */ /*GILLT_v16s8*//*Label 268*/ GIMT_Encode4(5469),
2372 /* 5143 */ // Label 263: @5143
2373 /* 5143 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5332),
2374 /* 5148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2375 /* 5151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2376 /* 5154 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5196), // Rule ID 42 //
2377 /* 5159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2378 /* 5162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2379 /* 5166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2380 /* 5170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2381 /* 5174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2382 /* 5178 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2383 /* 5182 */ // MIs[1] Operand 1
2384 /* 5182 */ // No operand predicates
2385 /* 5182 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2386 /* 5184 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2387 /* 5184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2388 /* 5187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2389 /* 5189 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2390 /* 5191 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2391 /* 5194 */ GIR_RootConstrainSelectedInstOperands,
2392 /* 5195 */ // GIR_Coverage, 42,
2393 /* 5195 */ GIR_EraseRootFromParent_Done,
2394 /* 5196 */ // Label 271: @5196
2395 /* 5196 */ GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5223), // Rule ID 52 //
2396 /* 5201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2397 /* 5204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2398 /* 5208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2399 /* 5212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2400 /* 5216 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2401 /* 5216 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2402 /* 5221 */ GIR_RootConstrainSelectedInstOperands,
2403 /* 5222 */ // GIR_Coverage, 52,
2404 /* 5222 */ GIR_Done,
2405 /* 5223 */ // Label 272: @5223
2406 /* 5223 */ GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5250), // Rule ID 1087 //
2407 /* 5228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2408 /* 5231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2409 /* 5235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2410 /* 5239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2411 /* 5243 */ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2412 /* 5243 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2413 /* 5248 */ GIR_RootConstrainSelectedInstOperands,
2414 /* 5249 */ // GIR_Coverage, 1087,
2415 /* 5249 */ GIR_Done,
2416 /* 5250 */ // Label 273: @5250
2417 /* 5250 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5277), // Rule ID 1102 //
2418 /* 5255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2419 /* 5258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2420 /* 5262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2421 /* 5266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2422 /* 5270 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2423 /* 5270 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2424 /* 5275 */ GIR_RootConstrainSelectedInstOperands,
2425 /* 5276 */ // GIR_Coverage, 1102,
2426 /* 5276 */ GIR_Done,
2427 /* 5277 */ // Label 274: @5277
2428 /* 5277 */ GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5304), // Rule ID 1206 //
2429 /* 5282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2430 /* 5285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2431 /* 5289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2432 /* 5293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2433 /* 5297 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2434 /* 5297 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2435 /* 5302 */ GIR_RootConstrainSelectedInstOperands,
2436 /* 5303 */ // GIR_Coverage, 1206,
2437 /* 5303 */ GIR_Done,
2438 /* 5304 */ // Label 275: @5304
2439 /* 5304 */ GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5331), // Rule ID 1956 //
2440 /* 5309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2441 /* 5312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2442 /* 5316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2443 /* 5320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2444 /* 5324 */ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2445 /* 5324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2446 /* 5329 */ GIR_RootConstrainSelectedInstOperands,
2447 /* 5330 */ // GIR_Coverage, 1956,
2448 /* 5330 */ GIR_Done,
2449 /* 5331 */ // Label 276: @5331
2450 /* 5331 */ GIM_Reject,
2451 /* 5332 */ // Label 270: @5332
2452 /* 5332 */ GIM_Reject,
2453 /* 5333 */ // Label 264: @5333
2454 /* 5333 */ GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5366), // Rule ID 231 //
2455 /* 5338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2456 /* 5341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2457 /* 5344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2458 /* 5347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2459 /* 5351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2460 /* 5355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2461 /* 5359 */ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2462 /* 5359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2463 /* 5364 */ GIR_RootConstrainSelectedInstOperands,
2464 /* 5365 */ // GIR_Coverage, 231,
2465 /* 5365 */ GIR_Done,
2466 /* 5366 */ // Label 277: @5366
2467 /* 5366 */ GIM_Reject,
2468 /* 5367 */ // Label 265: @5367
2469 /* 5367 */ GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5400), // Rule ID 948 //
2470 /* 5372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2471 /* 5375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2472 /* 5378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2473 /* 5381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2474 /* 5385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2475 /* 5389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2476 /* 5393 */ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2477 /* 5393 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2478 /* 5398 */ GIR_RootConstrainSelectedInstOperands,
2479 /* 5399 */ // GIR_Coverage, 948,
2480 /* 5399 */ GIR_Done,
2481 /* 5400 */ // Label 278: @5400
2482 /* 5400 */ GIM_Reject,
2483 /* 5401 */ // Label 266: @5401
2484 /* 5401 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5434), // Rule ID 947 //
2485 /* 5406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2486 /* 5409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2487 /* 5412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2488 /* 5415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2489 /* 5419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2490 /* 5423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2491 /* 5427 */ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2492 /* 5427 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2493 /* 5432 */ GIR_RootConstrainSelectedInstOperands,
2494 /* 5433 */ // GIR_Coverage, 947,
2495 /* 5433 */ GIR_Done,
2496 /* 5434 */ // Label 279: @5434
2497 /* 5434 */ GIM_Reject,
2498 /* 5435 */ // Label 267: @5435
2499 /* 5435 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5468), // Rule ID 946 //
2500 /* 5440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2501 /* 5443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2502 /* 5446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2503 /* 5449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2504 /* 5453 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2505 /* 5457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2506 /* 5461 */ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2507 /* 5461 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2508 /* 5466 */ GIR_RootConstrainSelectedInstOperands,
2509 /* 5467 */ // GIR_Coverage, 946,
2510 /* 5467 */ GIR_Done,
2511 /* 5468 */ // Label 280: @5468
2512 /* 5468 */ GIM_Reject,
2513 /* 5469 */ // Label 268: @5469
2514 /* 5469 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5502), // Rule ID 945 //
2515 /* 5474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2516 /* 5477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2517 /* 5480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2518 /* 5483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2519 /* 5487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2520 /* 5491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2521 /* 5495 */ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2522 /* 5495 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2523 /* 5500 */ GIR_RootConstrainSelectedInstOperands,
2524 /* 5501 */ // GIR_Coverage, 945,
2525 /* 5501 */ GIR_Done,
2526 /* 5502 */ // Label 281: @5502
2527 /* 5502 */ GIM_Reject,
2528 /* 5503 */ // Label 269: @5503
2529 /* 5503 */ GIM_Reject,
2530 /* 5504 */ // Label 9: @5504
2531 /* 5504 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 288*/ GIMT_Encode4(6395),
2532 /* 5515 */ /*GILLT_s32*//*Label 282*/ GIMT_Encode4(5547),
2533 /* 5519 */ /*GILLT_s64*//*Label 283*/ GIMT_Encode4(6164), GIMT_Encode4(0),
2534 /* 5527 */ /*GILLT_v2s64*//*Label 284*/ GIMT_Encode4(6259), GIMT_Encode4(0),
2535 /* 5535 */ /*GILLT_v4s32*//*Label 285*/ GIMT_Encode4(6293),
2536 /* 5539 */ /*GILLT_v8s16*//*Label 286*/ GIMT_Encode4(6327),
2537 /* 5543 */ /*GILLT_v16s8*//*Label 287*/ GIMT_Encode4(6361),
2538 /* 5547 */ // Label 282: @5547
2539 /* 5547 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(6163),
2540 /* 5552 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2541 /* 5555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2542 /* 5558 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(5617), // Rule ID 54 //
2543 /* 5563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2544 /* 5566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2545 /* 5570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2546 /* 5574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2547 /* 5578 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2548 /* 5582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2549 /* 5586 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2550 /* 5591 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2551 /* 5596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2552 /* 5600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2553 /* 5602 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2554 /* 5602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2555 /* 5605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2556 /* 5607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2557 /* 5611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2558 /* 5615 */ GIR_RootConstrainSelectedInstOperands,
2559 /* 5616 */ // GIR_Coverage, 54,
2560 /* 5616 */ GIR_EraseRootFromParent_Done,
2561 /* 5617 */ // Label 290: @5617
2562 /* 5617 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5676), // Rule ID 1104 //
2563 /* 5622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2564 /* 5625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2565 /* 5629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2566 /* 5633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2567 /* 5637 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2568 /* 5641 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2569 /* 5645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2570 /* 5650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2571 /* 5655 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2572 /* 5659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2573 /* 5661 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2574 /* 5661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2575 /* 5664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2576 /* 5666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2577 /* 5670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2578 /* 5674 */ GIR_RootConstrainSelectedInstOperands,
2579 /* 5675 */ // GIR_Coverage, 1104,
2580 /* 5675 */ GIR_EraseRootFromParent_Done,
2581 /* 5676 */ // Label 291: @5676
2582 /* 5676 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5735), // Rule ID 1205 //
2583 /* 5681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2584 /* 5684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2585 /* 5688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2586 /* 5692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2587 /* 5696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2588 /* 5700 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2589 /* 5704 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2590 /* 5709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2591 /* 5714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2592 /* 5718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2593 /* 5720 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2594 /* 5720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2595 /* 5723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2596 /* 5725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2597 /* 5729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2598 /* 5733 */ GIR_RootConstrainSelectedInstOperands,
2599 /* 5734 */ // GIR_Coverage, 1205,
2600 /* 5734 */ GIR_EraseRootFromParent_Done,
2601 /* 5735 */ // Label 292: @5735
2602 /* 5735 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5764), // Rule ID 1232 //
2603 /* 5740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2604 /* 5743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2605 /* 5747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2606 /* 5751 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2607 /* 5755 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2608 /* 5755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2609 /* 5758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2610 /* 5760 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2611 /* 5762 */ GIR_RootConstrainSelectedInstOperands,
2612 /* 5763 */ // GIR_Coverage, 1232,
2613 /* 5763 */ GIR_EraseRootFromParent_Done,
2614 /* 5764 */ // Label 293: @5764
2615 /* 5764 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5793), // Rule ID 1086 //
2616 /* 5769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2617 /* 5772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2618 /* 5776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2619 /* 5780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2620 /* 5784 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2621 /* 5784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2622 /* 5787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2623 /* 5789 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2624 /* 5791 */ GIR_RootConstrainSelectedInstOperands,
2625 /* 5792 */ // GIR_Coverage, 1086,
2626 /* 5792 */ GIR_EraseRootFromParent_Done,
2627 /* 5793 */ // Label 294: @5793
2628 /* 5793 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(5828), // Rule ID 1420 //
2629 /* 5798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2630 /* 5801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2631 /* 5805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2632 /* 5809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2633 /* 5813 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2634 /* 5813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2635 /* 5816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2636 /* 5818 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2637 /* 5820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2638 /* 5826 */ GIR_RootConstrainSelectedInstOperands,
2639 /* 5827 */ // GIR_Coverage, 1420,
2640 /* 5827 */ GIR_EraseRootFromParent_Done,
2641 /* 5828 */ // Label 295: @5828
2642 /* 5828 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(5857), // Rule ID 1951 //
2643 /* 5833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2644 /* 5836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2645 /* 5840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2646 /* 5844 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2647 /* 5848 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2648 /* 5848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2649 /* 5851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2650 /* 5853 */ GIR_RootToRootCopy, /*OpIdx*/1, // r
2651 /* 5855 */ GIR_RootConstrainSelectedInstOperands,
2652 /* 5856 */ // GIR_Coverage, 1951,
2653 /* 5856 */ GIR_EraseRootFromParent_Done,
2654 /* 5857 */ // Label 296: @5857
2655 /* 5857 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(5886), // Rule ID 2293 //
2656 /* 5862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2657 /* 5865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2658 /* 5869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2659 /* 5873 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2660 /* 5877 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2661 /* 5877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2662 /* 5880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2663 /* 5882 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2664 /* 5884 */ GIR_RootConstrainSelectedInstOperands,
2665 /* 5885 */ // GIR_Coverage, 2293,
2666 /* 5885 */ GIR_EraseRootFromParent_Done,
2667 /* 5886 */ // Label 297: @5886
2668 /* 5886 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(5921), // Rule ID 2294 //
2669 /* 5891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2670 /* 5894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2671 /* 5898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2672 /* 5902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2673 /* 5906 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2674 /* 5906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2675 /* 5909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2676 /* 5911 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2677 /* 5913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2678 /* 5919 */ GIR_RootConstrainSelectedInstOperands,
2679 /* 5920 */ // GIR_Coverage, 2294,
2680 /* 5920 */ GIR_EraseRootFromParent_Done,
2681 /* 5921 */ // Label 298: @5921
2682 /* 5921 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(5950), // Rule ID 2465 //
2683 /* 5926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2684 /* 5929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2685 /* 5933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2686 /* 5937 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2687 /* 5941 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2688 /* 5941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2689 /* 5944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2690 /* 5946 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2691 /* 5948 */ GIR_RootConstrainSelectedInstOperands,
2692 /* 5949 */ // GIR_Coverage, 2465,
2693 /* 5949 */ GIR_EraseRootFromParent_Done,
2694 /* 5950 */ // Label 299: @5950
2695 /* 5950 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(5985), // Rule ID 2466 //
2696 /* 5955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2697 /* 5958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2698 /* 5962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2699 /* 5966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2700 /* 5970 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2701 /* 5970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2702 /* 5973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2703 /* 5975 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2704 /* 5977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2705 /* 5983 */ GIR_RootConstrainSelectedInstOperands,
2706 /* 5984 */ // GIR_Coverage, 2466,
2707 /* 5984 */ GIR_EraseRootFromParent_Done,
2708 /* 5985 */ // Label 300: @5985
2709 /* 5985 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6027), // Rule ID 43 //
2710 /* 5990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2711 /* 5993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2712 /* 5997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2713 /* 6001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2714 /* 6005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2715 /* 6009 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2716 /* 6013 */ // MIs[1] Operand 1
2717 /* 6013 */ // No operand predicates
2718 /* 6013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2719 /* 6015 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2720 /* 6015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2721 /* 6018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2722 /* 6020 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2723 /* 6022 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2724 /* 6025 */ GIR_RootConstrainSelectedInstOperands,
2725 /* 6026 */ // GIR_Coverage, 43,
2726 /* 6026 */ GIR_EraseRootFromParent_Done,
2727 /* 6027 */ // Label 301: @6027
2728 /* 6027 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6054), // Rule ID 53 //
2729 /* 6032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2730 /* 6035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2731 /* 6039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2732 /* 6043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2733 /* 6047 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2734 /* 6047 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2735 /* 6052 */ GIR_RootConstrainSelectedInstOperands,
2736 /* 6053 */ // GIR_Coverage, 53,
2737 /* 6053 */ GIR_Done,
2738 /* 6054 */ // Label 302: @6054
2739 /* 6054 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6081), // Rule ID 1089 //
2740 /* 6059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2741 /* 6062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2742 /* 6066 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2743 /* 6070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2744 /* 6074 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2745 /* 6074 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2746 /* 6079 */ GIR_RootConstrainSelectedInstOperands,
2747 /* 6080 */ // GIR_Coverage, 1089,
2748 /* 6080 */ GIR_Done,
2749 /* 6081 */ // Label 303: @6081
2750 /* 6081 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6108), // Rule ID 1103 //
2751 /* 6086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2752 /* 6089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2753 /* 6093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2754 /* 6097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2755 /* 6101 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2756 /* 6101 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2757 /* 6106 */ GIR_RootConstrainSelectedInstOperands,
2758 /* 6107 */ // GIR_Coverage, 1103,
2759 /* 6107 */ GIR_Done,
2760 /* 6108 */ // Label 304: @6108
2761 /* 6108 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(6135), // Rule ID 1209 //
2762 /* 6113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2763 /* 6116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2764 /* 6120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2765 /* 6124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2766 /* 6128 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2767 /* 6128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2768 /* 6133 */ GIR_RootConstrainSelectedInstOperands,
2769 /* 6134 */ // GIR_Coverage, 1209,
2770 /* 6134 */ GIR_Done,
2771 /* 6135 */ // Label 305: @6135
2772 /* 6135 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(6162), // Rule ID 1958 //
2773 /* 6140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2774 /* 6143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2775 /* 6147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2776 /* 6151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2777 /* 6155 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2778 /* 6155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2779 /* 6160 */ GIR_RootConstrainSelectedInstOperands,
2780 /* 6161 */ // GIR_Coverage, 1958,
2781 /* 6161 */ GIR_Done,
2782 /* 6162 */ // Label 306: @6162
2783 /* 6162 */ GIM_Reject,
2784 /* 6163 */ // Label 289: @6163
2785 /* 6163 */ GIM_Reject,
2786 /* 6164 */ // Label 283: @6164
2787 /* 6164 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6258),
2788 /* 6169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2789 /* 6172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2790 /* 6175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2791 /* 6179 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6234), // Rule ID 233 //
2792 /* 6184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2793 /* 6187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2794 /* 6191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2795 /* 6195 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2796 /* 6199 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2797 /* 6203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2798 /* 6208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2799 /* 6213 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2800 /* 6217 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2801 /* 6219 */ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2802 /* 6219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2803 /* 6222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2804 /* 6224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2805 /* 6228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2806 /* 6232 */ GIR_RootConstrainSelectedInstOperands,
2807 /* 6233 */ // GIR_Coverage, 233,
2808 /* 6233 */ GIR_EraseRootFromParent_Done,
2809 /* 6234 */ // Label 308: @6234
2810 /* 6234 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6257), // Rule ID 232 //
2811 /* 6239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2812 /* 6242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2813 /* 6246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2814 /* 6250 */ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2815 /* 6250 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2816 /* 6255 */ GIR_RootConstrainSelectedInstOperands,
2817 /* 6256 */ // GIR_Coverage, 232,
2818 /* 6256 */ GIR_Done,
2819 /* 6257 */ // Label 309: @6257
2820 /* 6257 */ GIM_Reject,
2821 /* 6258 */ // Label 307: @6258
2822 /* 6258 */ GIM_Reject,
2823 /* 6259 */ // Label 284: @6259
2824 /* 6259 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6292), // Rule ID 1064 //
2825 /* 6264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2826 /* 6267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2827 /* 6270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2828 /* 6273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2829 /* 6277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2830 /* 6281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2831 /* 6285 */ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2832 /* 6285 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2833 /* 6290 */ GIR_RootConstrainSelectedInstOperands,
2834 /* 6291 */ // GIR_Coverage, 1064,
2835 /* 6291 */ GIR_Done,
2836 /* 6292 */ // Label 310: @6292
2837 /* 6292 */ GIM_Reject,
2838 /* 6293 */ // Label 285: @6293
2839 /* 6293 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6326), // Rule ID 1063 //
2840 /* 6298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2841 /* 6301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2842 /* 6304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2843 /* 6307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2844 /* 6311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2845 /* 6315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2846 /* 6319 */ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2847 /* 6319 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2848 /* 6324 */ GIR_RootConstrainSelectedInstOperands,
2849 /* 6325 */ // GIR_Coverage, 1063,
2850 /* 6325 */ GIR_Done,
2851 /* 6326 */ // Label 311: @6326
2852 /* 6326 */ GIM_Reject,
2853 /* 6327 */ // Label 286: @6327
2854 /* 6327 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6360), // Rule ID 1062 //
2855 /* 6332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2856 /* 6335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2857 /* 6338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2858 /* 6341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2859 /* 6345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2860 /* 6349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2861 /* 6353 */ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2862 /* 6353 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2863 /* 6358 */ GIR_RootConstrainSelectedInstOperands,
2864 /* 6359 */ // GIR_Coverage, 1062,
2865 /* 6359 */ GIR_Done,
2866 /* 6360 */ // Label 312: @6360
2867 /* 6360 */ GIM_Reject,
2868 /* 6361 */ // Label 287: @6361
2869 /* 6361 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6394), // Rule ID 1061 //
2870 /* 6366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2871 /* 6369 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2872 /* 6372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2873 /* 6375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2874 /* 6379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2875 /* 6383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2876 /* 6387 */ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2877 /* 6387 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2878 /* 6392 */ GIR_RootConstrainSelectedInstOperands,
2879 /* 6393 */ // GIR_Coverage, 1061,
2880 /* 6393 */ GIR_Done,
2881 /* 6394 */ // Label 313: @6394
2882 /* 6394 */ GIM_Reject,
2883 /* 6395 */ // Label 288: @6395
2884 /* 6395 */ GIM_Reject,
2885 /* 6396 */ // Label 10: @6396
2886 /* 6396 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6468),
2887 /* 6401 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2888 /* 6404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2889 /* 6407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2890 /* 6410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2891 /* 6413 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6440), // Rule ID 204 //
2892 /* 6418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
2893 /* 6421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2894 /* 6425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2895 /* 6429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2896 /* 6433 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2897 /* 6433 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2898 /* 6438 */ GIR_RootConstrainSelectedInstOperands,
2899 /* 6439 */ // GIR_Coverage, 204,
2900 /* 6439 */ GIR_Done,
2901 /* 6440 */ // Label 315: @6440
2902 /* 6440 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6467), // Rule ID 205 //
2903 /* 6445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
2904 /* 6448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2905 /* 6452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2906 /* 6456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2907 /* 6460 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2908 /* 6460 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2909 /* 6465 */ GIR_RootConstrainSelectedInstOperands,
2910 /* 6466 */ // GIR_Coverage, 205,
2911 /* 6466 */ GIR_Done,
2912 /* 6467 */ // Label 316: @6467
2913 /* 6467 */ GIM_Reject,
2914 /* 6468 */ // Label 314: @6468
2915 /* 6468 */ GIM_Reject,
2916 /* 6469 */ // Label 11: @6469
2917 /* 6469 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6540),
2918 /* 6474 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2919 /* 6477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2920 /* 6480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2921 /* 6483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2922 /* 6487 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6513), // Rule ID 743 //
2923 /* 6492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
2924 /* 6495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2925 /* 6499 */ // MIs[0] rs
2926 /* 6499 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2927 /* 6504 */ // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2928 /* 6504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2929 /* 6507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2930 /* 6509 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2931 /* 6511 */ GIR_RootConstrainSelectedInstOperands,
2932 /* 6512 */ // GIR_Coverage, 743,
2933 /* 6512 */ GIR_EraseRootFromParent_Done,
2934 /* 6513 */ // Label 318: @6513
2935 /* 6513 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6539), // Rule ID 745 //
2936 /* 6518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2937 /* 6521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2938 /* 6525 */ // MIs[0] fs
2939 /* 6525 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2940 /* 6530 */ // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2941 /* 6530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2942 /* 6533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2943 /* 6535 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2944 /* 6537 */ GIR_RootConstrainSelectedInstOperands,
2945 /* 6538 */ // GIR_Coverage, 745,
2946 /* 6538 */ GIR_EraseRootFromParent_Done,
2947 /* 6539 */ // Label 319: @6539
2948 /* 6539 */ GIM_Reject,
2949 /* 6540 */ // Label 317: @6540
2950 /* 6540 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6631),
2951 /* 6545 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2952 /* 6548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2953 /* 6551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2954 /* 6554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2955 /* 6558 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6594), // Rule ID 742 //
2956 /* 6563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2957 /* 6566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2958 /* 6570 */ // MIs[0] rs
2959 /* 6570 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2960 /* 6575 */ // MIs[0] rs
2961 /* 6575 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2962 /* 6580 */ // MIs[0] rs
2963 /* 6580 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2964 /* 6585 */ // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2965 /* 6585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2966 /* 6588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2967 /* 6590 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2968 /* 6592 */ GIR_RootConstrainSelectedInstOperands,
2969 /* 6593 */ // GIR_Coverage, 742,
2970 /* 6593 */ GIR_EraseRootFromParent_Done,
2971 /* 6594 */ // Label 321: @6594
2972 /* 6594 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(6630), // Rule ID 744 //
2973 /* 6599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2974 /* 6602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2975 /* 6606 */ // MIs[0] fs
2976 /* 6606 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2977 /* 6611 */ // MIs[0] fs
2978 /* 6611 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2979 /* 6616 */ // MIs[0] fs
2980 /* 6616 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2981 /* 6621 */ // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2982 /* 6621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2983 /* 6624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2984 /* 6626 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2985 /* 6628 */ GIR_RootConstrainSelectedInstOperands,
2986 /* 6629 */ // GIR_Coverage, 744,
2987 /* 6629 */ GIR_EraseRootFromParent_Done,
2988 /* 6630 */ // Label 322: @6630
2989 /* 6630 */ GIM_Reject,
2990 /* 6631 */ // Label 320: @6631
2991 /* 6631 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6700), // Rule ID 741 //
2992 /* 6636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2993 /* 6639 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
2994 /* 6642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
2995 /* 6645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2996 /* 6648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2997 /* 6652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2998 /* 6656 */ // MIs[0] rs
2999 /* 6656 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3000 /* 6661 */ // MIs[0] rs
3001 /* 6661 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3002 /* 6666 */ // MIs[0] rs
3003 /* 6666 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3004 /* 6671 */ // MIs[0] rs
3005 /* 6671 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3006 /* 6676 */ // MIs[0] rs
3007 /* 6676 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3008 /* 6681 */ // MIs[0] rs
3009 /* 6681 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3010 /* 6686 */ // MIs[0] rs
3011 /* 6686 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3012 /* 6691 */ // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
3013 /* 6691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
3014 /* 6694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3015 /* 6696 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3016 /* 6698 */ GIR_RootConstrainSelectedInstOperands,
3017 /* 6699 */ // GIR_Coverage, 741,
3018 /* 6699 */ GIR_EraseRootFromParent_Done,
3019 /* 6700 */ // Label 323: @6700
3020 /* 6700 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6809), // Rule ID 740 //
3021 /* 6705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
3022 /* 6708 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
3023 /* 6711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
3024 /* 6714 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3025 /* 6717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3026 /* 6721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3027 /* 6725 */ // MIs[0] rs
3028 /* 6725 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
3029 /* 6730 */ // MIs[0] rs
3030 /* 6730 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
3031 /* 6735 */ // MIs[0] rs
3032 /* 6735 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
3033 /* 6740 */ // MIs[0] rs
3034 /* 6740 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
3035 /* 6745 */ // MIs[0] rs
3036 /* 6745 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
3037 /* 6750 */ // MIs[0] rs
3038 /* 6750 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
3039 /* 6755 */ // MIs[0] rs
3040 /* 6755 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3041 /* 6760 */ // MIs[0] rs
3042 /* 6760 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3043 /* 6765 */ // MIs[0] rs
3044 /* 6765 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3045 /* 6770 */ // MIs[0] rs
3046 /* 6770 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3047 /* 6775 */ // MIs[0] rs
3048 /* 6775 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3049 /* 6780 */ // MIs[0] rs
3050 /* 6780 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3051 /* 6785 */ // MIs[0] rs
3052 /* 6785 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3053 /* 6790 */ // MIs[0] rs
3054 /* 6790 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3055 /* 6795 */ // MIs[0] rs
3056 /* 6795 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3057 /* 6800 */ // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3058 /* 6800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
3059 /* 6803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3060 /* 6805 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
3061 /* 6807 */ GIR_RootConstrainSelectedInstOperands,
3062 /* 6808 */ // GIR_Coverage, 740,
3063 /* 6808 */ GIR_EraseRootFromParent_Done,
3064 /* 6809 */ // Label 324: @6809
3065 /* 6809 */ GIM_Reject,
3066 /* 6810 */ // Label 12: @6810
3067 /* 6810 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 333*/ GIMT_Encode4(11120),
3068 /* 6821 */ /*GILLT_s32*//*Label 325*/ GIMT_Encode4(6853),
3069 /* 6825 */ /*GILLT_s64*//*Label 326*/ GIMT_Encode4(7130),
3070 /* 6829 */ /*GILLT_v2s16*//*Label 327*/ GIMT_Encode4(7186),
3071 /* 6833 */ /*GILLT_v2s64*//*Label 328*/ GIMT_Encode4(7246),
3072 /* 6837 */ /*GILLT_v4s8*//*Label 329*/ GIMT_Encode4(8381),
3073 /* 6841 */ /*GILLT_v4s32*//*Label 330*/ GIMT_Encode4(8441),
3074 /* 6845 */ /*GILLT_v8s16*//*Label 331*/ GIMT_Encode4(9510),
3075 /* 6849 */ /*GILLT_v16s8*//*Label 332*/ GIMT_Encode4(10435),
3076 /* 6853 */ // Label 325: @6853
3077 /* 6853 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(6879), // Rule ID 135 //
3078 /* 6858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3079 /* 6861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3080 /* 6864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3081 /* 6868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3082 /* 6872 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3083 /* 6872 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3084 /* 6877 */ GIR_RootConstrainSelectedInstOperands,
3085 /* 6878 */ // GIR_Coverage, 135,
3086 /* 6878 */ GIR_Done,
3087 /* 6879 */ // Label 334: @6879
3088 /* 6879 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(6905), // Rule ID 136 //
3089 /* 6884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3090 /* 6887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3091 /* 6890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3092 /* 6894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3093 /* 6898 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3094 /* 6898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3095 /* 6903 */ GIR_RootConstrainSelectedInstOperands,
3096 /* 6904 */ // GIR_Coverage, 136,
3097 /* 6904 */ GIR_Done,
3098 /* 6905 */ // Label 335: @6905
3099 /* 6905 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(6931), // Rule ID 1183 //
3100 /* 6910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3101 /* 6913 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3102 /* 6916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3103 /* 6920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3104 /* 6924 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3105 /* 6924 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3106 /* 6929 */ GIR_RootConstrainSelectedInstOperands,
3107 /* 6930 */ // GIR_Coverage, 1183,
3108 /* 6930 */ GIR_Done,
3109 /* 6931 */ // Label 336: @6931
3110 /* 6931 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(6957), // Rule ID 1184 //
3111 /* 6936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3112 /* 6939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3113 /* 6942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3114 /* 6946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3115 /* 6950 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3116 /* 6950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3117 /* 6955 */ GIR_RootConstrainSelectedInstOperands,
3118 /* 6956 */ // GIR_Coverage, 1184,
3119 /* 6956 */ GIR_Done,
3120 /* 6957 */ // Label 337: @6957
3121 /* 6957 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(6983), // Rule ID 1198 //
3122 /* 6962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3123 /* 6965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3124 /* 6968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3125 /* 6972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3126 /* 6976 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3127 /* 6976 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3128 /* 6981 */ GIR_RootConstrainSelectedInstOperands,
3129 /* 6982 */ // GIR_Coverage, 1198,
3130 /* 6982 */ GIR_Done,
3131 /* 6983 */ // Label 338: @6983
3132 /* 6983 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7009), // Rule ID 1199 //
3133 /* 6988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3134 /* 6991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3135 /* 6994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3136 /* 6998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3137 /* 7002 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3138 /* 7002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3139 /* 7007 */ GIR_RootConstrainSelectedInstOperands,
3140 /* 7008 */ // GIR_Coverage, 1199,
3141 /* 7008 */ GIR_Done,
3142 /* 7009 */ // Label 339: @7009
3143 /* 7009 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7039), // Rule ID 2039 //
3144 /* 7014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3145 /* 7017 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3146 /* 7020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3147 /* 7024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3148 /* 7028 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3149 /* 7028 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3150 /* 7033 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3151 /* 7038 */ // GIR_Coverage, 2039,
3152 /* 7038 */ GIR_Done,
3153 /* 7039 */ // Label 340: @7039
3154 /* 7039 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7069), // Rule ID 2040 //
3155 /* 7044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3156 /* 7047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3157 /* 7050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3158 /* 7054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3159 /* 7058 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3160 /* 7058 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3161 /* 7063 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3162 /* 7068 */ // GIR_Coverage, 2040,
3163 /* 7068 */ GIR_Done,
3164 /* 7069 */ // Label 341: @7069
3165 /* 7069 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7099), // Rule ID 2043 //
3166 /* 7074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3167 /* 7077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3168 /* 7080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3169 /* 7084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3170 /* 7088 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3171 /* 7088 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3172 /* 7093 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3173 /* 7098 */ // GIR_Coverage, 2043,
3174 /* 7098 */ GIR_Done,
3175 /* 7099 */ // Label 342: @7099
3176 /* 7099 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7129), // Rule ID 2044 //
3177 /* 7104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3178 /* 7107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3179 /* 7110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3180 /* 7114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3181 /* 7118 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3182 /* 7118 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3183 /* 7123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3184 /* 7128 */ // GIR_Coverage, 2044,
3185 /* 7128 */ GIR_Done,
3186 /* 7129 */ // Label 343: @7129
3187 /* 7129 */ GIM_Reject,
3188 /* 7130 */ // Label 326: @7130
3189 /* 7130 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7185),
3190 /* 7135 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3191 /* 7138 */ GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7161), // Rule ID 137 //
3192 /* 7143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3193 /* 7146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3194 /* 7150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3195 /* 7154 */ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3196 /* 7154 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3197 /* 7159 */ GIR_RootConstrainSelectedInstOperands,
3198 /* 7160 */ // GIR_Coverage, 137,
3199 /* 7160 */ GIR_Done,
3200 /* 7161 */ // Label 345: @7161
3201 /* 7161 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7184), // Rule ID 138 //
3202 /* 7166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3203 /* 7169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3204 /* 7173 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3205 /* 7177 */ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3206 /* 7177 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3207 /* 7182 */ GIR_RootConstrainSelectedInstOperands,
3208 /* 7183 */ // GIR_Coverage, 138,
3209 /* 7183 */ GIR_Done,
3210 /* 7184 */ // Label 346: @7184
3211 /* 7184 */ GIM_Reject,
3212 /* 7185 */ // Label 344: @7185
3213 /* 7185 */ GIM_Reject,
3214 /* 7186 */ // Label 327: @7186
3215 /* 7186 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7245),
3216 /* 7191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3217 /* 7194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3218 /* 7198 */ GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7221), // Rule ID 2041 //
3219 /* 7203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3220 /* 7206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3221 /* 7210 */ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3222 /* 7210 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3223 /* 7215 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3224 /* 7220 */ // GIR_Coverage, 2041,
3225 /* 7220 */ GIR_Done,
3226 /* 7221 */ // Label 348: @7221
3227 /* 7221 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7244), // Rule ID 2045 //
3228 /* 7226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3229 /* 7229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3230 /* 7233 */ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3231 /* 7233 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3232 /* 7238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3233 /* 7243 */ // GIR_Coverage, 2045,
3234 /* 7243 */ GIR_Done,
3235 /* 7244 */ // Label 349: @7244
3236 /* 7244 */ GIM_Reject,
3237 /* 7245 */ // Label 347: @7245
3238 /* 7245 */ GIM_Reject,
3239 /* 7246 */ // Label 328: @7246
3240 /* 7246 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7272), // Rule ID 2126 //
3241 /* 7251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3242 /* 7254 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3243 /* 7257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3244 /* 7261 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
3245 /* 7261 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3246 /* 7266 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3247 /* 7271 */ // GIR_Coverage, 2126,
3248 /* 7271 */ GIR_Done,
3249 /* 7272 */ // Label 350: @7272
3250 /* 7272 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7298), // Rule ID 2129 //
3251 /* 7277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3252 /* 7280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3253 /* 7283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3254 /* 7287 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
3255 /* 7287 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3256 /* 7292 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3257 /* 7297 */ // GIR_Coverage, 2129,
3258 /* 7297 */ GIR_Done,
3259 /* 7298 */ // Label 351: @7298
3260 /* 7298 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7324), // Rule ID 2146 //
3261 /* 7303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3262 /* 7306 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3263 /* 7309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3264 /* 7313 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3265 /* 7313 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3266 /* 7318 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3267 /* 7323 */ // GIR_Coverage, 2146,
3268 /* 7323 */ GIR_Done,
3269 /* 7324 */ // Label 352: @7324
3270 /* 7324 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7350), // Rule ID 2147 //
3271 /* 7329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3272 /* 7332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3273 /* 7335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3274 /* 7339 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3275 /* 7339 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3276 /* 7344 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3277 /* 7349 */ // GIR_Coverage, 2147,
3278 /* 7349 */ GIR_Done,
3279 /* 7350 */ // Label 353: @7350
3280 /* 7350 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7376), // Rule ID 2148 //
3281 /* 7355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3282 /* 7358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3283 /* 7361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3284 /* 7365 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3285 /* 7365 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3286 /* 7370 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3287 /* 7375 */ // GIR_Coverage, 2148,
3288 /* 7375 */ GIR_Done,
3289 /* 7376 */ // Label 354: @7376
3290 /* 7376 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7402), // Rule ID 2149 //
3291 /* 7381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3292 /* 7384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3293 /* 7387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3294 /* 7391 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3295 /* 7391 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3296 /* 7396 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3297 /* 7401 */ // GIR_Coverage, 2149,
3298 /* 7401 */ GIR_Done,
3299 /* 7402 */ // Label 355: @7402
3300 /* 7402 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7428), // Rule ID 2150 //
3301 /* 7407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3302 /* 7410 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3303 /* 7413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3304 /* 7417 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3305 /* 7417 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3306 /* 7422 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3307 /* 7427 */ // GIR_Coverage, 2150,
3308 /* 7427 */ GIR_Done,
3309 /* 7428 */ // Label 356: @7428
3310 /* 7428 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7454), // Rule ID 2156 //
3311 /* 7433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3312 /* 7436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3313 /* 7439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3314 /* 7443 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3315 /* 7443 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3316 /* 7448 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3317 /* 7453 */ // GIR_Coverage, 2156,
3318 /* 7453 */ GIR_Done,
3319 /* 7454 */ // Label 357: @7454
3320 /* 7454 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7480), // Rule ID 2157 //
3321 /* 7459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3322 /* 7462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3323 /* 7465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3324 /* 7469 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3325 /* 7469 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3326 /* 7474 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3327 /* 7479 */ // GIR_Coverage, 2157,
3328 /* 7479 */ GIR_Done,
3329 /* 7480 */ // Label 358: @7480
3330 /* 7480 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(7506), // Rule ID 2158 //
3331 /* 7485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3332 /* 7488 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3333 /* 7491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3334 /* 7495 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3335 /* 7495 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3336 /* 7500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3337 /* 7505 */ // GIR_Coverage, 2158,
3338 /* 7505 */ GIR_Done,
3339 /* 7506 */ // Label 359: @7506
3340 /* 7506 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(7532), // Rule ID 2159 //
3341 /* 7511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3342 /* 7514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3343 /* 7517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3344 /* 7521 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3345 /* 7521 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3346 /* 7526 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3347 /* 7531 */ // GIR_Coverage, 2159,
3348 /* 7531 */ GIR_Done,
3349 /* 7532 */ // Label 360: @7532
3350 /* 7532 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(7558), // Rule ID 2160 //
3351 /* 7537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3352 /* 7540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3353 /* 7543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3354 /* 7547 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3355 /* 7547 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3356 /* 7552 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3357 /* 7557 */ // GIR_Coverage, 2160,
3358 /* 7557 */ GIR_Done,
3359 /* 7558 */ // Label 361: @7558
3360 /* 7558 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(7675), // Rule ID 2165 //
3361 /* 7563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3362 /* 7566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3363 /* 7569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3364 /* 7573 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3365 /* 7573 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3366 /* 7576 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3367 /* 7580 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3368 /* 7585 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3369 /* 7589 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3370 /* 7594 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3371 /* 7597 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3372 /* 7601 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3373 /* 7606 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3374 /* 7609 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3375 /* 7612 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3376 /* 7614 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3377 /* 7617 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3378 /* 7621 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3379 /* 7626 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3380 /* 7629 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3381 /* 7634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3382 /* 7637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3383 /* 7641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3384 /* 7646 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3385 /* 7649 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3386 /* 7659 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3387 /* 7661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3388 /* 7664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3389 /* 7666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3390 /* 7669 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3391 /* 7674 */ // GIR_Coverage, 2165,
3392 /* 7674 */ GIR_EraseRootFromParent_Done,
3393 /* 7675 */ // Label 362: @7675
3394 /* 7675 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(7792), // Rule ID 2166 //
3395 /* 7680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3396 /* 7683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3397 /* 7686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3398 /* 7690 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3399 /* 7690 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3400 /* 7693 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3401 /* 7697 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3402 /* 7702 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3403 /* 7706 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3404 /* 7711 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3405 /* 7714 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3406 /* 7718 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3407 /* 7723 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3408 /* 7726 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3409 /* 7729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3410 /* 7731 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3411 /* 7734 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3412 /* 7738 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3413 /* 7743 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3414 /* 7746 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3415 /* 7751 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3416 /* 7754 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3417 /* 7758 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3418 /* 7763 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3419 /* 7766 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3420 /* 7776 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3421 /* 7778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3422 /* 7781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3423 /* 7783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3424 /* 7786 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3425 /* 7791 */ // GIR_Coverage, 2166,
3426 /* 7791 */ GIR_EraseRootFromParent_Done,
3427 /* 7792 */ // Label 363: @7792
3428 /* 7792 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(7862), // Rule ID 2170 //
3429 /* 7797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3430 /* 7800 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3431 /* 7803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3432 /* 7807 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3433 /* 7807 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3434 /* 7810 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3435 /* 7814 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3436 /* 7819 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3437 /* 7823 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3438 /* 7828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3439 /* 7831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3440 /* 7835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3441 /* 7840 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3442 /* 7843 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3443 /* 7846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3444 /* 7848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3445 /* 7851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3446 /* 7853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3447 /* 7856 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3448 /* 7861 */ // GIR_Coverage, 2170,
3449 /* 7861 */ GIR_EraseRootFromParent_Done,
3450 /* 7862 */ // Label 364: @7862
3451 /* 7862 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(7932), // Rule ID 2171 //
3452 /* 7867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3453 /* 7870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3454 /* 7873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3455 /* 7877 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3456 /* 7877 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3457 /* 7880 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3458 /* 7884 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3459 /* 7889 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3460 /* 7893 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3461 /* 7898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3462 /* 7901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3463 /* 7905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3464 /* 7910 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3465 /* 7913 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3466 /* 7916 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3467 /* 7918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3468 /* 7921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3469 /* 7923 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3470 /* 7926 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3471 /* 7931 */ // GIR_Coverage, 2171,
3472 /* 7931 */ GIR_EraseRootFromParent_Done,
3473 /* 7932 */ // Label 365: @7932
3474 /* 7932 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8002), // Rule ID 2175 //
3475 /* 7937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3476 /* 7940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3477 /* 7943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3478 /* 7947 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3479 /* 7947 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3480 /* 7950 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3481 /* 7954 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3482 /* 7959 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3483 /* 7963 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3484 /* 7968 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3485 /* 7971 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3486 /* 7975 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3487 /* 7980 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3488 /* 7983 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3489 /* 7986 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3490 /* 7988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3491 /* 7991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3492 /* 7993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3493 /* 7996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3494 /* 8001 */ // GIR_Coverage, 2175,
3495 /* 8001 */ GIR_EraseRootFromParent_Done,
3496 /* 8002 */ // Label 366: @8002
3497 /* 8002 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8072), // Rule ID 2176 //
3498 /* 8007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3499 /* 8010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3500 /* 8013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3501 /* 8017 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3502 /* 8017 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3503 /* 8020 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3504 /* 8024 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3505 /* 8029 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3506 /* 8033 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3507 /* 8038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3508 /* 8041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3509 /* 8045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3510 /* 8050 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3511 /* 8053 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3512 /* 8056 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3513 /* 8058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3514 /* 8061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3515 /* 8063 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3516 /* 8066 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3517 /* 8071 */ // GIR_Coverage, 2176,
3518 /* 8071 */ GIR_EraseRootFromParent_Done,
3519 /* 8072 */ // Label 367: @8072
3520 /* 8072 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8149), // Rule ID 2180 //
3521 /* 8077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3522 /* 8080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3523 /* 8083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3524 /* 8087 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3525 /* 8087 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3526 /* 8090 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3527 /* 8094 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3528 /* 8099 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3529 /* 8103 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3530 /* 8108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3531 /* 8111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3532 /* 8115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3533 /* 8120 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3534 /* 8123 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3535 /* 8133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3536 /* 8135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3537 /* 8138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3538 /* 8140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3539 /* 8143 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3540 /* 8148 */ // GIR_Coverage, 2180,
3541 /* 8148 */ GIR_EraseRootFromParent_Done,
3542 /* 8149 */ // Label 368: @8149
3543 /* 8149 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8226), // Rule ID 2181 //
3544 /* 8154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3545 /* 8157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3546 /* 8160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3547 /* 8164 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3548 /* 8164 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3549 /* 8167 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3550 /* 8171 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3551 /* 8176 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3552 /* 8180 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3553 /* 8185 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3554 /* 8188 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3555 /* 8192 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3556 /* 8197 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3557 /* 8200 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3558 /* 8210 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3559 /* 8212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3560 /* 8215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3561 /* 8217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3562 /* 8220 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3563 /* 8225 */ // GIR_Coverage, 2181,
3564 /* 8225 */ GIR_EraseRootFromParent_Done,
3565 /* 8226 */ // Label 369: @8226
3566 /* 8226 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8303), // Rule ID 2185 //
3567 /* 8231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3568 /* 8234 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3569 /* 8237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3570 /* 8241 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3571 /* 8241 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3572 /* 8244 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3573 /* 8248 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3574 /* 8253 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3575 /* 8257 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3576 /* 8262 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3577 /* 8265 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3578 /* 8269 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3579 /* 8274 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3580 /* 8277 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3581 /* 8287 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3582 /* 8289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3583 /* 8292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3584 /* 8294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3585 /* 8297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3586 /* 8302 */ // GIR_Coverage, 2185,
3587 /* 8302 */ GIR_EraseRootFromParent_Done,
3588 /* 8303 */ // Label 370: @8303
3589 /* 8303 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8380), // Rule ID 2186 //
3590 /* 8308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3591 /* 8311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3592 /* 8314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3593 /* 8318 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3594 /* 8318 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3595 /* 8321 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3596 /* 8325 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3597 /* 8330 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3598 /* 8334 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3599 /* 8339 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3600 /* 8342 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3601 /* 8346 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3602 /* 8351 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3603 /* 8354 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3604 /* 8364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3605 /* 8366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3606 /* 8369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3607 /* 8371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3608 /* 8374 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3609 /* 8379 */ // GIR_Coverage, 2186,
3610 /* 8379 */ GIR_EraseRootFromParent_Done,
3611 /* 8380 */ // Label 371: @8380
3612 /* 8380 */ GIM_Reject,
3613 /* 8381 */ // Label 329: @8381
3614 /* 8381 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8440),
3615 /* 8386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3616 /* 8389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3617 /* 8393 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8416), // Rule ID 2042 //
3618 /* 8398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3619 /* 8401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3620 /* 8405 */ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3621 /* 8405 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3622 /* 8410 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3623 /* 8415 */ // GIR_Coverage, 2042,
3624 /* 8415 */ GIR_Done,
3625 /* 8416 */ // Label 373: @8416
3626 /* 8416 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8439), // Rule ID 2046 //
3627 /* 8421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3628 /* 8424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3629 /* 8428 */ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3630 /* 8428 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3631 /* 8433 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3632 /* 8438 */ // GIR_Coverage, 2046,
3633 /* 8438 */ GIR_Done,
3634 /* 8439 */ // Label 374: @8439
3635 /* 8439 */ GIM_Reject,
3636 /* 8440 */ // Label 372: @8440
3637 /* 8440 */ GIM_Reject,
3638 /* 8441 */ // Label 330: @8441
3639 /* 8441 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8467), // Rule ID 2125 //
3640 /* 8446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3641 /* 8449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3642 /* 8452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3643 /* 8456 */ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3644 /* 8456 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3645 /* 8461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3646 /* 8466 */ // GIR_Coverage, 2125,
3647 /* 8466 */ GIR_Done,
3648 /* 8467 */ // Label 375: @8467
3649 /* 8467 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8493), // Rule ID 2128 //
3650 /* 8472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3651 /* 8475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3652 /* 8478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3653 /* 8482 */ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3654 /* 8482 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3655 /* 8487 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3656 /* 8492 */ // GIR_Coverage, 2128,
3657 /* 8492 */ GIR_Done,
3658 /* 8493 */ // Label 376: @8493
3659 /* 8493 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8519), // Rule ID 2141 //
3660 /* 8498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3661 /* 8501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3662 /* 8504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3663 /* 8508 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3664 /* 8508 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3665 /* 8513 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3666 /* 8518 */ // GIR_Coverage, 2141,
3667 /* 8518 */ GIR_Done,
3668 /* 8519 */ // Label 377: @8519
3669 /* 8519 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8545), // Rule ID 2142 //
3670 /* 8524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3671 /* 8527 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3672 /* 8530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3673 /* 8534 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3674 /* 8534 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3675 /* 8539 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3676 /* 8544 */ // GIR_Coverage, 2142,
3677 /* 8544 */ GIR_Done,
3678 /* 8545 */ // Label 378: @8545
3679 /* 8545 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(8571), // Rule ID 2143 //
3680 /* 8550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3681 /* 8553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3682 /* 8556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3683 /* 8560 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3684 /* 8560 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3685 /* 8565 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3686 /* 8570 */ // GIR_Coverage, 2143,
3687 /* 8570 */ GIR_Done,
3688 /* 8571 */ // Label 379: @8571
3689 /* 8571 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(8597), // Rule ID 2144 //
3690 /* 8576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3691 /* 8579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3692 /* 8582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3693 /* 8586 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3694 /* 8586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3695 /* 8591 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3696 /* 8596 */ // GIR_Coverage, 2144,
3697 /* 8596 */ GIR_Done,
3698 /* 8597 */ // Label 380: @8597
3699 /* 8597 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(8623), // Rule ID 2145 //
3700 /* 8602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3701 /* 8605 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3702 /* 8608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3703 /* 8612 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3704 /* 8612 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3705 /* 8617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3706 /* 8622 */ // GIR_Coverage, 2145,
3707 /* 8622 */ GIR_Done,
3708 /* 8623 */ // Label 381: @8623
3709 /* 8623 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(8649), // Rule ID 2151 //
3710 /* 8628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3711 /* 8631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3712 /* 8634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3713 /* 8638 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3714 /* 8638 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3715 /* 8643 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3716 /* 8648 */ // GIR_Coverage, 2151,
3717 /* 8648 */ GIR_Done,
3718 /* 8649 */ // Label 382: @8649
3719 /* 8649 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(8675), // Rule ID 2152 //
3720 /* 8654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3721 /* 8657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3722 /* 8660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3723 /* 8664 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3724 /* 8664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3725 /* 8669 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3726 /* 8674 */ // GIR_Coverage, 2152,
3727 /* 8674 */ GIR_Done,
3728 /* 8675 */ // Label 383: @8675
3729 /* 8675 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(8701), // Rule ID 2153 //
3730 /* 8680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3731 /* 8683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3732 /* 8686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3733 /* 8690 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3734 /* 8690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3735 /* 8695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3736 /* 8700 */ // GIR_Coverage, 2153,
3737 /* 8700 */ GIR_Done,
3738 /* 8701 */ // Label 384: @8701
3739 /* 8701 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(8727), // Rule ID 2154 //
3740 /* 8706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3741 /* 8709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3742 /* 8712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3743 /* 8716 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3744 /* 8716 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3745 /* 8721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3746 /* 8726 */ // GIR_Coverage, 2154,
3747 /* 8726 */ GIR_Done,
3748 /* 8727 */ // Label 385: @8727
3749 /* 8727 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(8753), // Rule ID 2155 //
3750 /* 8732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3751 /* 8735 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3752 /* 8738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3753 /* 8742 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3754 /* 8742 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3755 /* 8747 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3756 /* 8752 */ // GIR_Coverage, 2155,
3757 /* 8752 */ GIR_Done,
3758 /* 8753 */ // Label 386: @8753
3759 /* 8753 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(8823), // Rule ID 2163 //
3760 /* 8758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3761 /* 8761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3762 /* 8764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3763 /* 8768 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3764 /* 8768 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3765 /* 8771 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3766 /* 8775 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3767 /* 8780 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3768 /* 8784 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3769 /* 8789 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3770 /* 8792 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3771 /* 8796 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3772 /* 8801 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3773 /* 8804 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3774 /* 8807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3775 /* 8809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3776 /* 8812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3777 /* 8814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3778 /* 8817 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3779 /* 8822 */ // GIR_Coverage, 2163,
3780 /* 8822 */ GIR_EraseRootFromParent_Done,
3781 /* 8823 */ // Label 387: @8823
3782 /* 8823 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(8893), // Rule ID 2164 //
3783 /* 8828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3784 /* 8831 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3785 /* 8834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3786 /* 8838 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3787 /* 8838 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3788 /* 8841 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3789 /* 8845 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3790 /* 8850 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3791 /* 8854 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3792 /* 8859 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3793 /* 8862 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3794 /* 8866 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3795 /* 8871 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3796 /* 8874 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3797 /* 8877 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3798 /* 8879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3799 /* 8882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3800 /* 8884 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3801 /* 8887 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3802 /* 8892 */ // GIR_Coverage, 2164,
3803 /* 8892 */ GIR_EraseRootFromParent_Done,
3804 /* 8893 */ // Label 388: @8893
3805 /* 8893 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(8970), // Rule ID 2168 //
3806 /* 8898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3807 /* 8901 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3808 /* 8904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3809 /* 8908 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3810 /* 8908 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3811 /* 8911 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3812 /* 8915 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3813 /* 8920 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3814 /* 8924 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3815 /* 8929 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3816 /* 8932 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3817 /* 8936 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3818 /* 8941 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3819 /* 8944 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3820 /* 8954 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3821 /* 8956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3822 /* 8959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3823 /* 8961 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3824 /* 8964 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3825 /* 8969 */ // GIR_Coverage, 2168,
3826 /* 8969 */ GIR_EraseRootFromParent_Done,
3827 /* 8970 */ // Label 389: @8970
3828 /* 8970 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(9047), // Rule ID 2169 //
3829 /* 8975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3830 /* 8978 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3831 /* 8981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3832 /* 8985 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3833 /* 8985 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3834 /* 8988 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3835 /* 8992 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3836 /* 8997 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3837 /* 9001 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3838 /* 9006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3839 /* 9009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3840 /* 9013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3841 /* 9018 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3842 /* 9021 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3843 /* 9031 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3844 /* 9033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3845 /* 9036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3846 /* 9038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3847 /* 9041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3848 /* 9046 */ // GIR_Coverage, 2169,
3849 /* 9046 */ GIR_EraseRootFromParent_Done,
3850 /* 9047 */ // Label 390: @9047
3851 /* 9047 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(9124), // Rule ID 2173 //
3852 /* 9052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3853 /* 9055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3854 /* 9058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3855 /* 9062 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3856 /* 9062 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3857 /* 9065 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3858 /* 9069 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3859 /* 9074 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3860 /* 9078 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3861 /* 9083 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3862 /* 9086 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3863 /* 9090 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3864 /* 9095 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3865 /* 9098 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3866 /* 9108 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3867 /* 9110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3868 /* 9113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3869 /* 9115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3870 /* 9118 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3871 /* 9123 */ // GIR_Coverage, 2173,
3872 /* 9123 */ GIR_EraseRootFromParent_Done,
3873 /* 9124 */ // Label 391: @9124
3874 /* 9124 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(9201), // Rule ID 2174 //
3875 /* 9129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3876 /* 9132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3877 /* 9135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3878 /* 9139 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3879 /* 9139 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3880 /* 9142 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3881 /* 9146 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3882 /* 9151 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3883 /* 9155 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3884 /* 9160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3885 /* 9163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3886 /* 9167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3887 /* 9172 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3888 /* 9175 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3889 /* 9185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3890 /* 9187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3891 /* 9190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3892 /* 9192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3893 /* 9195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3894 /* 9200 */ // GIR_Coverage, 2174,
3895 /* 9200 */ GIR_EraseRootFromParent_Done,
3896 /* 9201 */ // Label 392: @9201
3897 /* 9201 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(9278), // Rule ID 2190 //
3898 /* 9206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3899 /* 9209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3900 /* 9212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3901 /* 9216 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3902 /* 9216 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3903 /* 9219 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3904 /* 9223 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3905 /* 9228 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3906 /* 9232 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3907 /* 9237 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3908 /* 9240 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3909 /* 9244 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3910 /* 9249 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3911 /* 9252 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3912 /* 9262 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3913 /* 9264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3914 /* 9267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3915 /* 9269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3916 /* 9272 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3917 /* 9277 */ // GIR_Coverage, 2190,
3918 /* 9277 */ GIR_EraseRootFromParent_Done,
3919 /* 9278 */ // Label 393: @9278
3920 /* 9278 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(9355), // Rule ID 2191 //
3921 /* 9283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3922 /* 9286 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3923 /* 9289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3924 /* 9293 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3925 /* 9293 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3926 /* 9296 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3927 /* 9300 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3928 /* 9305 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3929 /* 9309 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3930 /* 9314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3931 /* 9317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3932 /* 9321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3933 /* 9326 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3934 /* 9329 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3935 /* 9339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3936 /* 9341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3937 /* 9344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3938 /* 9346 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3939 /* 9349 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3940 /* 9354 */ // GIR_Coverage, 2191,
3941 /* 9354 */ GIR_EraseRootFromParent_Done,
3942 /* 9355 */ // Label 394: @9355
3943 /* 9355 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(9432), // Rule ID 2195 //
3944 /* 9360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3945 /* 9363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3946 /* 9366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3947 /* 9370 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3948 /* 9370 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3949 /* 9373 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3950 /* 9377 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3951 /* 9382 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3952 /* 9386 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3953 /* 9391 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3954 /* 9394 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3955 /* 9398 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3956 /* 9403 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3957 /* 9406 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3958 /* 9416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3959 /* 9418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3960 /* 9421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3961 /* 9423 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3962 /* 9426 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3963 /* 9431 */ // GIR_Coverage, 2195,
3964 /* 9431 */ GIR_EraseRootFromParent_Done,
3965 /* 9432 */ // Label 395: @9432
3966 /* 9432 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(9509), // Rule ID 2196 //
3967 /* 9437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3968 /* 9440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3969 /* 9443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3970 /* 9447 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3971 /* 9447 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3972 /* 9450 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3973 /* 9454 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3974 /* 9459 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3975 /* 9463 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3976 /* 9468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3977 /* 9471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3978 /* 9475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3979 /* 9480 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3980 /* 9483 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3981 /* 9493 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3982 /* 9495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3983 /* 9498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3984 /* 9500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3985 /* 9503 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3986 /* 9508 */ // GIR_Coverage, 2196,
3987 /* 9508 */ GIR_EraseRootFromParent_Done,
3988 /* 9509 */ // Label 396: @9509
3989 /* 9509 */ GIM_Reject,
3990 /* 9510 */ // Label 331: @9510
3991 /* 9510 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(9536), // Rule ID 2124 //
3992 /* 9515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3993 /* 9518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3994 /* 9521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3995 /* 9525 */ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3996 /* 9525 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3997 /* 9530 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3998 /* 9535 */ // GIR_Coverage, 2124,
3999 /* 9535 */ GIR_Done,
4000 /* 9536 */ // Label 397: @9536
4001 /* 9536 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(9562), // Rule ID 2127 //
4002 /* 9541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
4003 /* 9544 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4004 /* 9547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4005 /* 9551 */ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
4006 /* 9551 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4007 /* 9556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4008 /* 9561 */ // GIR_Coverage, 2127,
4009 /* 9561 */ GIR_Done,
4010 /* 9562 */ // Label 398: @9562
4011 /* 9562 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(9588), // Rule ID 2136 //
4012 /* 9567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4013 /* 9570 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4014 /* 9573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4015 /* 9577 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
4016 /* 9577 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4017 /* 9582 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4018 /* 9587 */ // GIR_Coverage, 2136,
4019 /* 9587 */ GIR_Done,
4020 /* 9588 */ // Label 399: @9588
4021 /* 9588 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(9614), // Rule ID 2137 //
4022 /* 9593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4023 /* 9596 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4024 /* 9599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4025 /* 9603 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
4026 /* 9603 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4027 /* 9608 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4028 /* 9613 */ // GIR_Coverage, 2137,
4029 /* 9613 */ GIR_Done,
4030 /* 9614 */ // Label 400: @9614
4031 /* 9614 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(9640), // Rule ID 2138 //
4032 /* 9619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4033 /* 9622 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4034 /* 9625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4035 /* 9629 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
4036 /* 9629 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4037 /* 9634 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4038 /* 9639 */ // GIR_Coverage, 2138,
4039 /* 9639 */ GIR_Done,
4040 /* 9640 */ // Label 401: @9640
4041 /* 9640 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(9666), // Rule ID 2139 //
4042 /* 9645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4043 /* 9648 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4044 /* 9651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4045 /* 9655 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
4046 /* 9655 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4047 /* 9660 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4048 /* 9665 */ // GIR_Coverage, 2139,
4049 /* 9665 */ GIR_Done,
4050 /* 9666 */ // Label 402: @9666
4051 /* 9666 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(9692), // Rule ID 2140 //
4052 /* 9671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4053 /* 9674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4054 /* 9677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4055 /* 9681 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
4056 /* 9681 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4057 /* 9686 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4058 /* 9691 */ // GIR_Coverage, 2140,
4059 /* 9691 */ GIR_Done,
4060 /* 9692 */ // Label 403: @9692
4061 /* 9692 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(9769), // Rule ID 2161 //
4062 /* 9697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4063 /* 9700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4064 /* 9703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4065 /* 9707 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4066 /* 9707 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4067 /* 9710 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4068 /* 9714 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4069 /* 9719 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4070 /* 9723 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4071 /* 9728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4072 /* 9731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4073 /* 9735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4074 /* 9740 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4075 /* 9743 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4076 /* 9753 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4077 /* 9755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4078 /* 9758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4079 /* 9760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4080 /* 9763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4081 /* 9768 */ // GIR_Coverage, 2161,
4082 /* 9768 */ GIR_EraseRootFromParent_Done,
4083 /* 9769 */ // Label 404: @9769
4084 /* 9769 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(9846), // Rule ID 2162 //
4085 /* 9774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4086 /* 9777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4087 /* 9780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4088 /* 9784 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4089 /* 9784 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4090 /* 9787 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4091 /* 9791 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4092 /* 9796 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4093 /* 9800 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4094 /* 9805 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4095 /* 9808 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4096 /* 9812 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4097 /* 9817 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4098 /* 9820 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4099 /* 9830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4100 /* 9832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4101 /* 9835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4102 /* 9837 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4103 /* 9840 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4104 /* 9845 */ // GIR_Coverage, 2162,
4105 /* 9845 */ GIR_EraseRootFromParent_Done,
4106 /* 9846 */ // Label 405: @9846
4107 /* 9846 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(9923), // Rule ID 2178 //
4108 /* 9851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4109 /* 9854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4110 /* 9857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4111 /* 9861 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4112 /* 9861 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4113 /* 9864 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4114 /* 9868 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4115 /* 9873 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4116 /* 9877 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4117 /* 9882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4118 /* 9885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4119 /* 9889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4120 /* 9894 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4121 /* 9897 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4122 /* 9907 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4123 /* 9909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4124 /* 9912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4125 /* 9914 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4126 /* 9917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4127 /* 9922 */ // GIR_Coverage, 2178,
4128 /* 9922 */ GIR_EraseRootFromParent_Done,
4129 /* 9923 */ // Label 406: @9923
4130 /* 9923 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(10000), // Rule ID 2179 //
4131 /* 9928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4132 /* 9931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4133 /* 9934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4134 /* 9938 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4135 /* 9938 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4136 /* 9941 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4137 /* 9945 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4138 /* 9950 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4139 /* 9954 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4140 /* 9959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4141 /* 9962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4142 /* 9966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4143 /* 9971 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4144 /* 9974 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4145 /* 9984 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4146 /* 9986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4147 /* 9989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4148 /* 9991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4149 /* 9994 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4150 /* 9999 */ // GIR_Coverage, 2179,
4151 /* 9999 */ GIR_EraseRootFromParent_Done,
4152 /* 10000 */ // Label 407: @10000
4153 /* 10000 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(10077), // Rule ID 2183 //
4154 /* 10005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4155 /* 10008 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4156 /* 10011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4157 /* 10015 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4158 /* 10015 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4159 /* 10018 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4160 /* 10022 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4161 /* 10027 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4162 /* 10031 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4163 /* 10036 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4164 /* 10039 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4165 /* 10043 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4166 /* 10048 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4167 /* 10051 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4168 /* 10061 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4169 /* 10063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4170 /* 10066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4171 /* 10068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4172 /* 10071 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4173 /* 10076 */ // GIR_Coverage, 2183,
4174 /* 10076 */ GIR_EraseRootFromParent_Done,
4175 /* 10077 */ // Label 408: @10077
4176 /* 10077 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(10154), // Rule ID 2184 //
4177 /* 10082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4178 /* 10085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4179 /* 10088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4180 /* 10092 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4181 /* 10092 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4182 /* 10095 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4183 /* 10099 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4184 /* 10104 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4185 /* 10108 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4186 /* 10113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4187 /* 10116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4188 /* 10120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4189 /* 10125 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4190 /* 10128 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4191 /* 10138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4192 /* 10140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4193 /* 10143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4194 /* 10145 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4195 /* 10148 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4196 /* 10153 */ // GIR_Coverage, 2184,
4197 /* 10153 */ GIR_EraseRootFromParent_Done,
4198 /* 10154 */ // Label 409: @10154
4199 /* 10154 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(10224), // Rule ID 2188 //
4200 /* 10159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4201 /* 10162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4202 /* 10165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4203 /* 10169 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4204 /* 10169 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4205 /* 10172 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4206 /* 10176 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4207 /* 10181 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4208 /* 10185 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4209 /* 10190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4210 /* 10193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4211 /* 10197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4212 /* 10202 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4213 /* 10205 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4214 /* 10208 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4215 /* 10210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4216 /* 10213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4217 /* 10215 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4218 /* 10218 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4219 /* 10223 */ // GIR_Coverage, 2188,
4220 /* 10223 */ GIR_EraseRootFromParent_Done,
4221 /* 10224 */ // Label 410: @10224
4222 /* 10224 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(10294), // Rule ID 2189 //
4223 /* 10229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4224 /* 10232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4225 /* 10235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4226 /* 10239 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4227 /* 10239 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4228 /* 10242 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4229 /* 10246 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4230 /* 10251 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4231 /* 10255 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4232 /* 10260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4233 /* 10263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4234 /* 10267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4235 /* 10272 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4236 /* 10275 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4237 /* 10278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4238 /* 10280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4239 /* 10283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4240 /* 10285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4241 /* 10288 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4242 /* 10293 */ // GIR_Coverage, 2189,
4243 /* 10293 */ GIR_EraseRootFromParent_Done,
4244 /* 10294 */ // Label 411: @10294
4245 /* 10294 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(10364), // Rule ID 2193 //
4246 /* 10299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4247 /* 10302 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4248 /* 10305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4249 /* 10309 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4250 /* 10309 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4251 /* 10312 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4252 /* 10316 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4253 /* 10321 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4254 /* 10325 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4255 /* 10330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4256 /* 10333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4257 /* 10337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4258 /* 10342 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4259 /* 10345 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4260 /* 10348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4261 /* 10350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4262 /* 10353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4263 /* 10355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4264 /* 10358 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4265 /* 10363 */ // GIR_Coverage, 2193,
4266 /* 10363 */ GIR_EraseRootFromParent_Done,
4267 /* 10364 */ // Label 412: @10364
4268 /* 10364 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(10434), // Rule ID 2194 //
4269 /* 10369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4270 /* 10372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4271 /* 10375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4272 /* 10379 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4273 /* 10379 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4274 /* 10382 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4275 /* 10386 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4276 /* 10391 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4277 /* 10395 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4278 /* 10400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4279 /* 10403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4280 /* 10407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4281 /* 10412 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4282 /* 10415 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4283 /* 10418 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4284 /* 10420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4285 /* 10423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4286 /* 10425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4287 /* 10428 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4288 /* 10433 */ // GIR_Coverage, 2194,
4289 /* 10433 */ GIR_EraseRootFromParent_Done,
4290 /* 10434 */ // Label 413: @10434
4291 /* 10434 */ GIM_Reject,
4292 /* 10435 */ // Label 332: @10435
4293 /* 10435 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(10461), // Rule ID 2130 //
4294 /* 10440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4295 /* 10443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4296 /* 10446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4297 /* 10450 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
4298 /* 10450 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4299 /* 10455 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4300 /* 10460 */ // GIR_Coverage, 2130,
4301 /* 10460 */ GIR_Done,
4302 /* 10461 */ // Label 414: @10461
4303 /* 10461 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(10487), // Rule ID 2131 //
4304 /* 10466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4305 /* 10469 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4306 /* 10472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4307 /* 10476 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4308 /* 10476 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4309 /* 10481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4310 /* 10486 */ // GIR_Coverage, 2131,
4311 /* 10486 */ GIR_Done,
4312 /* 10487 */ // Label 415: @10487
4313 /* 10487 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(10513), // Rule ID 2132 //
4314 /* 10492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4315 /* 10495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4316 /* 10498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4317 /* 10502 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4318 /* 10502 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4319 /* 10507 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4320 /* 10512 */ // GIR_Coverage, 2132,
4321 /* 10512 */ GIR_Done,
4322 /* 10513 */ // Label 416: @10513
4323 /* 10513 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(10539), // Rule ID 2133 //
4324 /* 10518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4325 /* 10521 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4326 /* 10524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4327 /* 10528 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4328 /* 10528 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4329 /* 10533 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4330 /* 10538 */ // GIR_Coverage, 2133,
4331 /* 10538 */ GIR_Done,
4332 /* 10539 */ // Label 417: @10539
4333 /* 10539 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(10565), // Rule ID 2134 //
4334 /* 10544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4335 /* 10547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4336 /* 10550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4337 /* 10554 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4338 /* 10554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4339 /* 10559 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4340 /* 10564 */ // GIR_Coverage, 2134,
4341 /* 10564 */ GIR_Done,
4342 /* 10565 */ // Label 418: @10565
4343 /* 10565 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(10591), // Rule ID 2135 //
4344 /* 10570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4345 /* 10573 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4346 /* 10576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4347 /* 10580 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4348 /* 10580 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4349 /* 10585 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4350 /* 10590 */ // GIR_Coverage, 2135,
4351 /* 10590 */ GIR_Done,
4352 /* 10591 */ // Label 419: @10591
4353 /* 10591 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(10668), // Rule ID 2167 //
4354 /* 10596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4355 /* 10599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4356 /* 10602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4357 /* 10606 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4358 /* 10606 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4359 /* 10609 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4360 /* 10613 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4361 /* 10618 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4362 /* 10622 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4363 /* 10627 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4364 /* 10630 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4365 /* 10634 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4366 /* 10639 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4367 /* 10642 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4368 /* 10652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4369 /* 10654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4370 /* 10657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4371 /* 10659 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4372 /* 10662 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4373 /* 10667 */ // GIR_Coverage, 2167,
4374 /* 10667 */ GIR_EraseRootFromParent_Done,
4375 /* 10668 */ // Label 420: @10668
4376 /* 10668 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(10745), // Rule ID 2172 //
4377 /* 10673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4378 /* 10676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4379 /* 10679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4380 /* 10683 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4381 /* 10683 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4382 /* 10686 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4383 /* 10690 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4384 /* 10695 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4385 /* 10699 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4386 /* 10704 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4387 /* 10707 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4388 /* 10711 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4389 /* 10716 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4390 /* 10719 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4391 /* 10729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4392 /* 10731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4393 /* 10734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4394 /* 10736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4395 /* 10739 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4396 /* 10744 */ // GIR_Coverage, 2172,
4397 /* 10744 */ GIR_EraseRootFromParent_Done,
4398 /* 10745 */ // Label 421: @10745
4399 /* 10745 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(10815), // Rule ID 2177 //
4400 /* 10750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4401 /* 10753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4402 /* 10756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4403 /* 10760 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4404 /* 10760 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4405 /* 10763 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4406 /* 10767 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4407 /* 10772 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4408 /* 10776 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4409 /* 10781 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4410 /* 10784 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4411 /* 10788 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4412 /* 10793 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4413 /* 10796 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4414 /* 10799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4415 /* 10801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4416 /* 10804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4417 /* 10806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4418 /* 10809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4419 /* 10814 */ // GIR_Coverage, 2177,
4420 /* 10814 */ GIR_EraseRootFromParent_Done,
4421 /* 10815 */ // Label 422: @10815
4422 /* 10815 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(10885), // Rule ID 2182 //
4423 /* 10820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4424 /* 10823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4425 /* 10826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4426 /* 10830 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4427 /* 10830 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4428 /* 10833 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4429 /* 10837 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4430 /* 10842 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4431 /* 10846 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4432 /* 10851 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4433 /* 10854 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4434 /* 10858 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4435 /* 10863 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4436 /* 10866 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4437 /* 10869 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4438 /* 10871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4439 /* 10874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4440 /* 10876 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4441 /* 10879 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4442 /* 10884 */ // GIR_Coverage, 2182,
4443 /* 10884 */ GIR_EraseRootFromParent_Done,
4444 /* 10885 */ // Label 423: @10885
4445 /* 10885 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(11002), // Rule ID 2187 //
4446 /* 10890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4447 /* 10893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4448 /* 10896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4449 /* 10900 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4450 /* 10900 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4451 /* 10903 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4452 /* 10907 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4453 /* 10912 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4454 /* 10916 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4455 /* 10921 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4456 /* 10924 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4457 /* 10928 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4458 /* 10933 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4459 /* 10936 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4460 /* 10939 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4461 /* 10941 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4462 /* 10944 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4463 /* 10948 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4464 /* 10953 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4465 /* 10956 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4466 /* 10961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4467 /* 10964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4468 /* 10968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4469 /* 10973 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4470 /* 10976 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4471 /* 10986 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4472 /* 10988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4473 /* 10991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4474 /* 10993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4475 /* 10996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4476 /* 11001 */ // GIR_Coverage, 2187,
4477 /* 11001 */ GIR_EraseRootFromParent_Done,
4478 /* 11002 */ // Label 424: @11002
4479 /* 11002 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(11119), // Rule ID 2192 //
4480 /* 11007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4481 /* 11010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4482 /* 11013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4483 /* 11017 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4484 /* 11017 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4485 /* 11020 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4486 /* 11024 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4487 /* 11029 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4488 /* 11033 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4489 /* 11038 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4490 /* 11041 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4491 /* 11045 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4492 /* 11050 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4493 /* 11053 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4494 /* 11056 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4495 /* 11058 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4496 /* 11061 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4497 /* 11065 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4498 /* 11070 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4499 /* 11073 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4500 /* 11078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4501 /* 11081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4502 /* 11085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4503 /* 11090 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4504 /* 11093 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4505 /* 11103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4506 /* 11105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4507 /* 11108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4508 /* 11110 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4509 /* 11113 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4510 /* 11118 */ // GIR_Coverage, 2192,
4511 /* 11118 */ GIR_EraseRootFromParent_Done,
4512 /* 11119 */ // Label 425: @11119
4513 /* 11119 */ GIM_Reject,
4514 /* 11120 */ // Label 333: @11120
4515 /* 11120 */ GIM_Reject,
4516 /* 11121 */ // Label 13: @11121
4517 /* 11121 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(11185), // Rule ID 2115 //
4518 /* 11126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4519 /* 11129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4520 /* 11132 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4521 /* 11135 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4522 /* 11139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4523 /* 11143 */ // MIs[0] Operand 1
4524 /* 11143 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4525 /* 11147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4526 /* 11151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4527 /* 11155 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4528 /* 11159 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4529 /* 11163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4530 /* 11165 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4531 /* 11165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4532 /* 11168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4533 /* 11170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4534 /* 11174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4535 /* 11178 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4536 /* 11183 */ GIR_RootConstrainSelectedInstOperands,
4537 /* 11184 */ // GIR_Coverage, 2115,
4538 /* 11184 */ GIR_EraseRootFromParent_Done,
4539 /* 11185 */ // Label 426: @11185
4540 /* 11185 */ GIM_Reject,
4541 /* 11186 */ // Label 14: @11186
4542 /* 11186 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(11253), // Rule ID 2114 //
4543 /* 11191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4544 /* 11194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4545 /* 11197 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4546 /* 11200 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4547 /* 11207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4548 /* 11211 */ // MIs[0] Operand 1
4549 /* 11211 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4550 /* 11215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4551 /* 11219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4552 /* 11223 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4553 /* 11227 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4554 /* 11231 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4555 /* 11233 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4556 /* 11233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4557 /* 11236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4558 /* 11238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4559 /* 11242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4560 /* 11246 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4561 /* 11251 */ GIR_RootConstrainSelectedInstOperands,
4562 /* 11252 */ // GIR_Coverage, 2114,
4563 /* 11252 */ GIR_EraseRootFromParent_Done,
4564 /* 11253 */ // Label 427: @11253
4565 /* 11253 */ GIM_Reject,
4566 /* 11254 */ // Label 15: @11254
4567 /* 11254 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(11321), // Rule ID 2113 //
4568 /* 11259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4569 /* 11262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4570 /* 11265 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4571 /* 11268 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4572 /* 11275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4573 /* 11279 */ // MIs[0] Operand 1
4574 /* 11279 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4575 /* 11283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4576 /* 11287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4577 /* 11291 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4578 /* 11295 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4579 /* 11299 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4580 /* 11301 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4581 /* 11301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4582 /* 11304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4583 /* 11306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4584 /* 11310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4585 /* 11314 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4586 /* 11319 */ GIR_RootConstrainSelectedInstOperands,
4587 /* 11320 */ // GIR_Coverage, 2113,
4588 /* 11320 */ GIR_EraseRootFromParent_Done,
4589 /* 11321 */ // Label 428: @11321
4590 /* 11321 */ GIM_Reject,
4591 /* 11322 */ // Label 16: @11322
4592 /* 11322 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 431*/ GIMT_Encode4(11513),
4593 /* 11333 */ /*GILLT_s32*//*Label 429*/ GIMT_Encode4(11341),
4594 /* 11337 */ /*GILLT_s64*//*Label 430*/ GIMT_Encode4(11468),
4595 /* 11341 */ // Label 429: @11341
4596 /* 11341 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(11467),
4597 /* 11346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4598 /* 11349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
4599 /* 11352 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(11390), // Rule ID 25 //
4600 /* 11357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4601 /* 11360 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4602 /* 11367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4603 /* 11371 */ // MIs[0] ptr
4604 /* 11371 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4605 /* 11375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4606 /* 11379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4607 /* 11383 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4608 /* 11383 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4609 /* 11388 */ GIR_RootConstrainSelectedInstOperands,
4610 /* 11389 */ // GIR_Coverage, 25,
4611 /* 11389 */ GIR_Done,
4612 /* 11390 */ // Label 433: @11390
4613 /* 11390 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(11428), // Rule ID 26 //
4614 /* 11395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4615 /* 11398 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4616 /* 11405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4617 /* 11409 */ // MIs[0] ptr
4618 /* 11409 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4619 /* 11413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4620 /* 11417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4621 /* 11421 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4622 /* 11421 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4623 /* 11426 */ GIR_RootConstrainSelectedInstOperands,
4624 /* 11427 */ // GIR_Coverage, 26,
4625 /* 11427 */ GIR_Done,
4626 /* 11428 */ // Label 434: @11428
4627 /* 11428 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(11466), // Rule ID 27 //
4628 /* 11433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4629 /* 11436 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4630 /* 11443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4631 /* 11447 */ // MIs[0] ptr
4632 /* 11447 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4633 /* 11451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4634 /* 11455 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4635 /* 11459 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4636 /* 11459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4637 /* 11464 */ GIR_RootConstrainSelectedInstOperands,
4638 /* 11465 */ // GIR_Coverage, 27,
4639 /* 11465 */ GIR_Done,
4640 /* 11466 */ // Label 435: @11466
4641 /* 11466 */ GIM_Reject,
4642 /* 11467 */ // Label 432: @11467
4643 /* 11467 */ GIM_Reject,
4644 /* 11468 */ // Label 430: @11468
4645 /* 11468 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(11512), // Rule ID 215 //
4646 /* 11473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4647 /* 11476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4648 /* 11479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
4649 /* 11482 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4650 /* 11489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4651 /* 11493 */ // MIs[0] ptr
4652 /* 11493 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4653 /* 11497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4654 /* 11501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4655 /* 11505 */ // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4656 /* 11505 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4657 /* 11510 */ GIR_RootConstrainSelectedInstOperands,
4658 /* 11511 */ // GIR_Coverage, 215,
4659 /* 11511 */ GIR_Done,
4660 /* 11512 */ // Label 436: @11512
4661 /* 11512 */ GIM_Reject,
4662 /* 11513 */ // Label 431: @11513
4663 /* 11513 */ GIM_Reject,
4664 /* 11514 */ // Label 17: @11514
4665 /* 11514 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 439*/ GIMT_Encode4(11683),
4666 /* 11525 */ /*GILLT_s32*//*Label 437*/ GIMT_Encode4(11533),
4667 /* 11529 */ /*GILLT_s64*//*Label 438*/ GIMT_Encode4(11645),
4668 /* 11533 */ // Label 437: @11533
4669 /* 11533 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(11644),
4670 /* 11538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4671 /* 11541 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(11575), // Rule ID 22 //
4672 /* 11546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4673 /* 11549 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4674 /* 11556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4675 /* 11560 */ // MIs[0] ptr
4676 /* 11560 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4677 /* 11564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4678 /* 11568 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4679 /* 11568 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4680 /* 11573 */ GIR_RootConstrainSelectedInstOperands,
4681 /* 11574 */ // GIR_Coverage, 22,
4682 /* 11574 */ GIR_Done,
4683 /* 11575 */ // Label 441: @11575
4684 /* 11575 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(11609), // Rule ID 23 //
4685 /* 11580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4686 /* 11583 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4687 /* 11590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4688 /* 11594 */ // MIs[0] ptr
4689 /* 11594 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4690 /* 11598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4691 /* 11602 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4692 /* 11602 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4693 /* 11607 */ GIR_RootConstrainSelectedInstOperands,
4694 /* 11608 */ // GIR_Coverage, 23,
4695 /* 11608 */ GIR_Done,
4696 /* 11609 */ // Label 442: @11609
4697 /* 11609 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(11643), // Rule ID 24 //
4698 /* 11614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4699 /* 11617 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4700 /* 11624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4701 /* 11628 */ // MIs[0] ptr
4702 /* 11628 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4703 /* 11632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4704 /* 11636 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4705 /* 11636 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4706 /* 11641 */ GIR_RootConstrainSelectedInstOperands,
4707 /* 11642 */ // GIR_Coverage, 24,
4708 /* 11642 */ GIR_Done,
4709 /* 11643 */ // Label 443: @11643
4710 /* 11643 */ GIM_Reject,
4711 /* 11644 */ // Label 440: @11644
4712 /* 11644 */ GIM_Reject,
4713 /* 11645 */ // Label 438: @11645
4714 /* 11645 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(11682), // Rule ID 214 //
4715 /* 11650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4716 /* 11653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4717 /* 11656 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4718 /* 11663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4719 /* 11667 */ // MIs[0] ptr
4720 /* 11667 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4721 /* 11671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4722 /* 11675 */ // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4723 /* 11675 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4724 /* 11680 */ GIR_RootConstrainSelectedInstOperands,
4725 /* 11681 */ // GIR_Coverage, 214,
4726 /* 11681 */ GIR_Done,
4727 /* 11682 */ // Label 444: @11682
4728 /* 11682 */ GIM_Reject,
4729 /* 11683 */ // Label 439: @11683
4730 /* 11683 */ GIM_Reject,
4731 /* 11684 */ // Label 18: @11684
4732 /* 11684 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 447*/ GIMT_Encode4(11853),
4733 /* 11695 */ /*GILLT_s32*//*Label 445*/ GIMT_Encode4(11703),
4734 /* 11699 */ /*GILLT_s64*//*Label 446*/ GIMT_Encode4(11815),
4735 /* 11703 */ // Label 445: @11703
4736 /* 11703 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(11814),
4737 /* 11708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4738 /* 11711 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(11745), // Rule ID 4 //
4739 /* 11716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4740 /* 11719 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4741 /* 11726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4742 /* 11730 */ // MIs[0] ptr
4743 /* 11730 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4744 /* 11734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4745 /* 11738 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4746 /* 11738 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4747 /* 11743 */ GIR_RootConstrainSelectedInstOperands,
4748 /* 11744 */ // GIR_Coverage, 4,
4749 /* 11744 */ GIR_Done,
4750 /* 11745 */ // Label 449: @11745
4751 /* 11745 */ GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(11779), // Rule ID 5 //
4752 /* 11750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4753 /* 11753 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4754 /* 11760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4755 /* 11764 */ // MIs[0] ptr
4756 /* 11764 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4757 /* 11768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4758 /* 11772 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4759 /* 11772 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4760 /* 11777 */ GIR_RootConstrainSelectedInstOperands,
4761 /* 11778 */ // GIR_Coverage, 5,
4762 /* 11778 */ GIR_Done,
4763 /* 11779 */ // Label 450: @11779
4764 /* 11779 */ GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(11813), // Rule ID 6 //
4765 /* 11784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4766 /* 11787 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4767 /* 11794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4768 /* 11798 */ // MIs[0] ptr
4769 /* 11798 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4770 /* 11802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4771 /* 11806 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4772 /* 11806 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4773 /* 11811 */ GIR_RootConstrainSelectedInstOperands,
4774 /* 11812 */ // GIR_Coverage, 6,
4775 /* 11812 */ GIR_Done,
4776 /* 11813 */ // Label 451: @11813
4777 /* 11813 */ GIM_Reject,
4778 /* 11814 */ // Label 448: @11814
4779 /* 11814 */ GIM_Reject,
4780 /* 11815 */ // Label 446: @11815
4781 /* 11815 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(11852), // Rule ID 208 //
4782 /* 11820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4783 /* 11823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4784 /* 11826 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4785 /* 11833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4786 /* 11837 */ // MIs[0] ptr
4787 /* 11837 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4788 /* 11841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4789 /* 11845 */ // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4790 /* 11845 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4791 /* 11850 */ GIR_RootConstrainSelectedInstOperands,
4792 /* 11851 */ // GIR_Coverage, 208,
4793 /* 11851 */ GIR_Done,
4794 /* 11852 */ // Label 452: @11852
4795 /* 11852 */ GIM_Reject,
4796 /* 11853 */ // Label 447: @11853
4797 /* 11853 */ GIM_Reject,
4798 /* 11854 */ // Label 19: @11854
4799 /* 11854 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 455*/ GIMT_Encode4(12023),
4800 /* 11865 */ /*GILLT_s32*//*Label 453*/ GIMT_Encode4(11873),
4801 /* 11869 */ /*GILLT_s64*//*Label 454*/ GIMT_Encode4(11985),
4802 /* 11873 */ // Label 453: @11873
4803 /* 11873 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(11984),
4804 /* 11878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4805 /* 11881 */ GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(11915), // Rule ID 7 //
4806 /* 11886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4807 /* 11889 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4808 /* 11896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4809 /* 11900 */ // MIs[0] ptr
4810 /* 11900 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4811 /* 11904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4812 /* 11908 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4813 /* 11908 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4814 /* 11913 */ GIR_RootConstrainSelectedInstOperands,
4815 /* 11914 */ // GIR_Coverage, 7,
4816 /* 11914 */ GIR_Done,
4817 /* 11915 */ // Label 457: @11915
4818 /* 11915 */ GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(11949), // Rule ID 8 //
4819 /* 11920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4820 /* 11923 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4821 /* 11930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4822 /* 11934 */ // MIs[0] ptr
4823 /* 11934 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4824 /* 11938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4825 /* 11942 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4826 /* 11942 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4827 /* 11947 */ GIR_RootConstrainSelectedInstOperands,
4828 /* 11948 */ // GIR_Coverage, 8,
4829 /* 11948 */ GIR_Done,
4830 /* 11949 */ // Label 458: @11949
4831 /* 11949 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(11983), // Rule ID 9 //
4832 /* 11954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4833 /* 11957 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4834 /* 11964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4835 /* 11968 */ // MIs[0] ptr
4836 /* 11968 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4837 /* 11972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4838 /* 11976 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4839 /* 11976 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4840 /* 11981 */ GIR_RootConstrainSelectedInstOperands,
4841 /* 11982 */ // GIR_Coverage, 9,
4842 /* 11982 */ GIR_Done,
4843 /* 11983 */ // Label 459: @11983
4844 /* 11983 */ GIM_Reject,
4845 /* 11984 */ // Label 456: @11984
4846 /* 11984 */ GIM_Reject,
4847 /* 11985 */ // Label 454: @11985
4848 /* 11985 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(12022), // Rule ID 209 //
4849 /* 11990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4850 /* 11993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4851 /* 11996 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4852 /* 12003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4853 /* 12007 */ // MIs[0] ptr
4854 /* 12007 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4855 /* 12011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4856 /* 12015 */ // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4857 /* 12015 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4858 /* 12020 */ GIR_RootConstrainSelectedInstOperands,
4859 /* 12021 */ // GIR_Coverage, 209,
4860 /* 12021 */ GIR_Done,
4861 /* 12022 */ // Label 460: @12022
4862 /* 12022 */ GIM_Reject,
4863 /* 12023 */ // Label 455: @12023
4864 /* 12023 */ GIM_Reject,
4865 /* 12024 */ // Label 20: @12024
4866 /* 12024 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 463*/ GIMT_Encode4(12193),
4867 /* 12035 */ /*GILLT_s32*//*Label 461*/ GIMT_Encode4(12043),
4868 /* 12039 */ /*GILLT_s64*//*Label 462*/ GIMT_Encode4(12155),
4869 /* 12043 */ // Label 461: @12043
4870 /* 12043 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(12154),
4871 /* 12048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4872 /* 12051 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(12085), // Rule ID 10 //
4873 /* 12056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4874 /* 12059 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4875 /* 12066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4876 /* 12070 */ // MIs[0] ptr
4877 /* 12070 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4878 /* 12074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4879 /* 12078 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4880 /* 12078 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4881 /* 12083 */ GIR_RootConstrainSelectedInstOperands,
4882 /* 12084 */ // GIR_Coverage, 10,
4883 /* 12084 */ GIR_Done,
4884 /* 12085 */ // Label 465: @12085
4885 /* 12085 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(12119), // Rule ID 11 //
4886 /* 12090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4887 /* 12093 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4888 /* 12100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4889 /* 12104 */ // MIs[0] ptr
4890 /* 12104 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4891 /* 12108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4892 /* 12112 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4893 /* 12112 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4894 /* 12117 */ GIR_RootConstrainSelectedInstOperands,
4895 /* 12118 */ // GIR_Coverage, 11,
4896 /* 12118 */ GIR_Done,
4897 /* 12119 */ // Label 466: @12119
4898 /* 12119 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(12153), // Rule ID 12 //
4899 /* 12124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4900 /* 12127 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4901 /* 12134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4902 /* 12138 */ // MIs[0] ptr
4903 /* 12138 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4904 /* 12142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4905 /* 12146 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4906 /* 12146 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4907 /* 12151 */ GIR_RootConstrainSelectedInstOperands,
4908 /* 12152 */ // GIR_Coverage, 12,
4909 /* 12152 */ GIR_Done,
4910 /* 12153 */ // Label 467: @12153
4911 /* 12153 */ GIM_Reject,
4912 /* 12154 */ // Label 464: @12154
4913 /* 12154 */ GIM_Reject,
4914 /* 12155 */ // Label 462: @12155
4915 /* 12155 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(12192), // Rule ID 210 //
4916 /* 12160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4917 /* 12163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4918 /* 12166 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4919 /* 12173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4920 /* 12177 */ // MIs[0] ptr
4921 /* 12177 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4922 /* 12181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4923 /* 12185 */ // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4924 /* 12185 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4925 /* 12190 */ GIR_RootConstrainSelectedInstOperands,
4926 /* 12191 */ // GIR_Coverage, 210,
4927 /* 12191 */ GIR_Done,
4928 /* 12192 */ // Label 468: @12192
4929 /* 12192 */ GIM_Reject,
4930 /* 12193 */ // Label 463: @12193
4931 /* 12193 */ GIM_Reject,
4932 /* 12194 */ // Label 21: @12194
4933 /* 12194 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 471*/ GIMT_Encode4(12363),
4934 /* 12205 */ /*GILLT_s32*//*Label 469*/ GIMT_Encode4(12213),
4935 /* 12209 */ /*GILLT_s64*//*Label 470*/ GIMT_Encode4(12325),
4936 /* 12213 */ // Label 469: @12213
4937 /* 12213 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(12324),
4938 /* 12218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4939 /* 12221 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(12255), // Rule ID 19 //
4940 /* 12226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4941 /* 12229 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4942 /* 12236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4943 /* 12240 */ // MIs[0] ptr
4944 /* 12240 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4945 /* 12244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4946 /* 12248 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4947 /* 12248 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4948 /* 12253 */ GIR_RootConstrainSelectedInstOperands,
4949 /* 12254 */ // GIR_Coverage, 19,
4950 /* 12254 */ GIR_Done,
4951 /* 12255 */ // Label 473: @12255
4952 /* 12255 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(12289), // Rule ID 20 //
4953 /* 12260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4954 /* 12263 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4955 /* 12270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4956 /* 12274 */ // MIs[0] ptr
4957 /* 12274 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4958 /* 12278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4959 /* 12282 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4960 /* 12282 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4961 /* 12287 */ GIR_RootConstrainSelectedInstOperands,
4962 /* 12288 */ // GIR_Coverage, 20,
4963 /* 12288 */ GIR_Done,
4964 /* 12289 */ // Label 474: @12289
4965 /* 12289 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(12323), // Rule ID 21 //
4966 /* 12294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4967 /* 12297 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4968 /* 12304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4969 /* 12308 */ // MIs[0] ptr
4970 /* 12308 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4971 /* 12312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4972 /* 12316 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4973 /* 12316 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4974 /* 12321 */ GIR_RootConstrainSelectedInstOperands,
4975 /* 12322 */ // GIR_Coverage, 21,
4976 /* 12322 */ GIR_Done,
4977 /* 12323 */ // Label 475: @12323
4978 /* 12323 */ GIM_Reject,
4979 /* 12324 */ // Label 472: @12324
4980 /* 12324 */ GIM_Reject,
4981 /* 12325 */ // Label 470: @12325
4982 /* 12325 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(12362), // Rule ID 213 //
4983 /* 12330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
4984 /* 12333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4985 /* 12336 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4986 /* 12343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4987 /* 12347 */ // MIs[0] ptr
4988 /* 12347 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4989 /* 12351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4990 /* 12355 */ // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4991 /* 12355 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4992 /* 12360 */ GIR_RootConstrainSelectedInstOperands,
4993 /* 12361 */ // GIR_Coverage, 213,
4994 /* 12361 */ GIR_Done,
4995 /* 12362 */ // Label 476: @12362
4996 /* 12362 */ GIM_Reject,
4997 /* 12363 */ // Label 471: @12363
4998 /* 12363 */ GIM_Reject,
4999 /* 12364 */ // Label 22: @12364
5000 /* 12364 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 479*/ GIMT_Encode4(12533),
5001 /* 12375 */ /*GILLT_s32*//*Label 477*/ GIMT_Encode4(12383),
5002 /* 12379 */ /*GILLT_s64*//*Label 478*/ GIMT_Encode4(12495),
5003 /* 12383 */ // Label 477: @12383
5004 /* 12383 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(12494),
5005 /* 12388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5006 /* 12391 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(12425), // Rule ID 13 //
5007 /* 12396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5008 /* 12399 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5009 /* 12406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5010 /* 12410 */ // MIs[0] ptr
5011 /* 12410 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5012 /* 12414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5013 /* 12418 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5014 /* 12418 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
5015 /* 12423 */ GIR_RootConstrainSelectedInstOperands,
5016 /* 12424 */ // GIR_Coverage, 13,
5017 /* 12424 */ GIR_Done,
5018 /* 12425 */ // Label 481: @12425
5019 /* 12425 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(12459), // Rule ID 14 //
5020 /* 12430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5021 /* 12433 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5022 /* 12440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5023 /* 12444 */ // MIs[0] ptr
5024 /* 12444 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5025 /* 12448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5026 /* 12452 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5027 /* 12452 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
5028 /* 12457 */ GIR_RootConstrainSelectedInstOperands,
5029 /* 12458 */ // GIR_Coverage, 14,
5030 /* 12458 */ GIR_Done,
5031 /* 12459 */ // Label 482: @12459
5032 /* 12459 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(12493), // Rule ID 15 //
5033 /* 12464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5034 /* 12467 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5035 /* 12474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5036 /* 12478 */ // MIs[0] ptr
5037 /* 12478 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5038 /* 12482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5039 /* 12486 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5040 /* 12486 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
5041 /* 12491 */ GIR_RootConstrainSelectedInstOperands,
5042 /* 12492 */ // GIR_Coverage, 15,
5043 /* 12492 */ GIR_Done,
5044 /* 12493 */ // Label 483: @12493
5045 /* 12493 */ GIM_Reject,
5046 /* 12494 */ // Label 480: @12494
5047 /* 12494 */ GIM_Reject,
5048 /* 12495 */ // Label 478: @12495
5049 /* 12495 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(12532), // Rule ID 211 //
5050 /* 12500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5051 /* 12503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5052 /* 12506 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5053 /* 12513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5054 /* 12517 */ // MIs[0] ptr
5055 /* 12517 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5056 /* 12521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5057 /* 12525 */ // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5058 /* 12525 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
5059 /* 12530 */ GIR_RootConstrainSelectedInstOperands,
5060 /* 12531 */ // GIR_Coverage, 211,
5061 /* 12531 */ GIR_Done,
5062 /* 12532 */ // Label 484: @12532
5063 /* 12532 */ GIM_Reject,
5064 /* 12533 */ // Label 479: @12533
5065 /* 12533 */ GIM_Reject,
5066 /* 12534 */ // Label 23: @12534
5067 /* 12534 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 487*/ GIMT_Encode4(12703),
5068 /* 12545 */ /*GILLT_s32*//*Label 485*/ GIMT_Encode4(12553),
5069 /* 12549 */ /*GILLT_s64*//*Label 486*/ GIMT_Encode4(12665),
5070 /* 12553 */ // Label 485: @12553
5071 /* 12553 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(12664),
5072 /* 12558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5073 /* 12561 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(12595), // Rule ID 16 //
5074 /* 12566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5075 /* 12569 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5076 /* 12576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5077 /* 12580 */ // MIs[0] ptr
5078 /* 12580 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5079 /* 12584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5080 /* 12588 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5081 /* 12588 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
5082 /* 12593 */ GIR_RootConstrainSelectedInstOperands,
5083 /* 12594 */ // GIR_Coverage, 16,
5084 /* 12594 */ GIR_Done,
5085 /* 12595 */ // Label 489: @12595
5086 /* 12595 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(12629), // Rule ID 17 //
5087 /* 12600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5088 /* 12603 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5089 /* 12610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5090 /* 12614 */ // MIs[0] ptr
5091 /* 12614 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5092 /* 12618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5093 /* 12622 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5094 /* 12622 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
5095 /* 12627 */ GIR_RootConstrainSelectedInstOperands,
5096 /* 12628 */ // GIR_Coverage, 17,
5097 /* 12628 */ GIR_Done,
5098 /* 12629 */ // Label 490: @12629
5099 /* 12629 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(12663), // Rule ID 18 //
5100 /* 12634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5101 /* 12637 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5102 /* 12644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5103 /* 12648 */ // MIs[0] ptr
5104 /* 12648 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5105 /* 12652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5106 /* 12656 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5107 /* 12656 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
5108 /* 12661 */ GIR_RootConstrainSelectedInstOperands,
5109 /* 12662 */ // GIR_Coverage, 18,
5110 /* 12662 */ GIR_Done,
5111 /* 12663 */ // Label 491: @12663
5112 /* 12663 */ GIM_Reject,
5113 /* 12664 */ // Label 488: @12664
5114 /* 12664 */ GIM_Reject,
5115 /* 12665 */ // Label 486: @12665
5116 /* 12665 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(12702), // Rule ID 212 //
5117 /* 12670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5118 /* 12673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5119 /* 12676 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5120 /* 12683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5121 /* 12687 */ // MIs[0] ptr
5122 /* 12687 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5123 /* 12691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5124 /* 12695 */ // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5125 /* 12695 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
5126 /* 12700 */ GIR_RootConstrainSelectedInstOperands,
5127 /* 12701 */ // GIR_Coverage, 212,
5128 /* 12701 */ GIR_Done,
5129 /* 12702 */ // Label 492: @12702
5130 /* 12702 */ GIM_Reject,
5131 /* 12703 */ // Label 487: @12703
5132 /* 12703 */ GIM_Reject,
5133 /* 12704 */ // Label 24: @12704
5134 /* 12704 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 495*/ GIMT_Encode4(12873),
5135 /* 12715 */ /*GILLT_s32*//*Label 493*/ GIMT_Encode4(12723),
5136 /* 12719 */ /*GILLT_s64*//*Label 494*/ GIMT_Encode4(12835),
5137 /* 12723 */ // Label 493: @12723
5138 /* 12723 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(12834),
5139 /* 12728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5140 /* 12731 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(12765), // Rule ID 31 //
5141 /* 12736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5142 /* 12739 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5143 /* 12746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5144 /* 12750 */ // MIs[0] ptr
5145 /* 12750 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5146 /* 12754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5147 /* 12758 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5148 /* 12758 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
5149 /* 12763 */ GIR_RootConstrainSelectedInstOperands,
5150 /* 12764 */ // GIR_Coverage, 31,
5151 /* 12764 */ GIR_Done,
5152 /* 12765 */ // Label 497: @12765
5153 /* 12765 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(12799), // Rule ID 32 //
5154 /* 12770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5155 /* 12773 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5156 /* 12780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5157 /* 12784 */ // MIs[0] ptr
5158 /* 12784 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5159 /* 12788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5160 /* 12792 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5161 /* 12792 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
5162 /* 12797 */ GIR_RootConstrainSelectedInstOperands,
5163 /* 12798 */ // GIR_Coverage, 32,
5164 /* 12798 */ GIR_Done,
5165 /* 12799 */ // Label 498: @12799
5166 /* 12799 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(12833), // Rule ID 33 //
5167 /* 12804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5168 /* 12807 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5169 /* 12814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5170 /* 12818 */ // MIs[0] ptr
5171 /* 12818 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5172 /* 12822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5173 /* 12826 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5174 /* 12826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
5175 /* 12831 */ GIR_RootConstrainSelectedInstOperands,
5176 /* 12832 */ // GIR_Coverage, 33,
5177 /* 12832 */ GIR_Done,
5178 /* 12833 */ // Label 499: @12833
5179 /* 12833 */ GIM_Reject,
5180 /* 12834 */ // Label 496: @12834
5181 /* 12834 */ GIM_Reject,
5182 /* 12835 */ // Label 494: @12835
5183 /* 12835 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(12872), // Rule ID 217 //
5184 /* 12840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5185 /* 12843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5186 /* 12846 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5187 /* 12853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5188 /* 12857 */ // MIs[0] ptr
5189 /* 12857 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5190 /* 12861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5191 /* 12865 */ // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5192 /* 12865 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
5193 /* 12870 */ GIR_RootConstrainSelectedInstOperands,
5194 /* 12871 */ // GIR_Coverage, 217,
5195 /* 12871 */ GIR_Done,
5196 /* 12872 */ // Label 500: @12872
5197 /* 12872 */ GIM_Reject,
5198 /* 12873 */ // Label 495: @12873
5199 /* 12873 */ GIM_Reject,
5200 /* 12874 */ // Label 25: @12874
5201 /* 12874 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 503*/ GIMT_Encode4(13043),
5202 /* 12885 */ /*GILLT_s32*//*Label 501*/ GIMT_Encode4(12893),
5203 /* 12889 */ /*GILLT_s64*//*Label 502*/ GIMT_Encode4(13005),
5204 /* 12893 */ // Label 501: @12893
5205 /* 12893 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(13004),
5206 /* 12898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5207 /* 12901 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(12935), // Rule ID 28 //
5208 /* 12906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5209 /* 12909 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5210 /* 12916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5211 /* 12920 */ // MIs[0] ptr
5212 /* 12920 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5213 /* 12924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5214 /* 12928 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5215 /* 12928 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
5216 /* 12933 */ GIR_RootConstrainSelectedInstOperands,
5217 /* 12934 */ // GIR_Coverage, 28,
5218 /* 12934 */ GIR_Done,
5219 /* 12935 */ // Label 505: @12935
5220 /* 12935 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(12969), // Rule ID 29 //
5221 /* 12940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5222 /* 12943 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5223 /* 12950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5224 /* 12954 */ // MIs[0] ptr
5225 /* 12954 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5226 /* 12958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5227 /* 12962 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5228 /* 12962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
5229 /* 12967 */ GIR_RootConstrainSelectedInstOperands,
5230 /* 12968 */ // GIR_Coverage, 29,
5231 /* 12968 */ GIR_Done,
5232 /* 12969 */ // Label 506: @12969
5233 /* 12969 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(13003), // Rule ID 30 //
5234 /* 12974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5235 /* 12977 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5236 /* 12984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5237 /* 12988 */ // MIs[0] ptr
5238 /* 12988 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5239 /* 12992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5240 /* 12996 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5241 /* 12996 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
5242 /* 13001 */ GIR_RootConstrainSelectedInstOperands,
5243 /* 13002 */ // GIR_Coverage, 30,
5244 /* 13002 */ GIR_Done,
5245 /* 13003 */ // Label 507: @13003
5246 /* 13003 */ GIM_Reject,
5247 /* 13004 */ // Label 504: @13004
5248 /* 13004 */ GIM_Reject,
5249 /* 13005 */ // Label 502: @13005
5250 /* 13005 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(13042), // Rule ID 216 //
5251 /* 13010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5252 /* 13013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5253 /* 13016 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5254 /* 13023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5255 /* 13027 */ // MIs[0] ptr
5256 /* 13027 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5257 /* 13031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5258 /* 13035 */ // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5259 /* 13035 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
5260 /* 13040 */ GIR_RootConstrainSelectedInstOperands,
5261 /* 13041 */ // GIR_Coverage, 216,
5262 /* 13041 */ GIR_Done,
5263 /* 13042 */ // Label 508: @13042
5264 /* 13042 */ GIM_Reject,
5265 /* 13043 */ // Label 503: @13043
5266 /* 13043 */ GIM_Reject,
5267 /* 13044 */ // Label 26: @13044
5268 /* 13044 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 511*/ GIMT_Encode4(13213),
5269 /* 13055 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(13063),
5270 /* 13059 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(13175),
5271 /* 13063 */ // Label 509: @13063
5272 /* 13063 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(13174),
5273 /* 13068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5274 /* 13071 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(13105), // Rule ID 37 //
5275 /* 13076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5276 /* 13079 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5277 /* 13086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5278 /* 13090 */ // MIs[0] ptr
5279 /* 13090 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5280 /* 13094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5281 /* 13098 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5282 /* 13098 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
5283 /* 13103 */ GIR_RootConstrainSelectedInstOperands,
5284 /* 13104 */ // GIR_Coverage, 37,
5285 /* 13104 */ GIR_Done,
5286 /* 13105 */ // Label 513: @13105
5287 /* 13105 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(13139), // Rule ID 38 //
5288 /* 13110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5289 /* 13113 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5290 /* 13120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5291 /* 13124 */ // MIs[0] ptr
5292 /* 13124 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5293 /* 13128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5294 /* 13132 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5295 /* 13132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5296 /* 13137 */ GIR_RootConstrainSelectedInstOperands,
5297 /* 13138 */ // GIR_Coverage, 38,
5298 /* 13138 */ GIR_Done,
5299 /* 13139 */ // Label 514: @13139
5300 /* 13139 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(13173), // Rule ID 39 //
5301 /* 13144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5302 /* 13147 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5303 /* 13154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5304 /* 13158 */ // MIs[0] ptr
5305 /* 13158 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5306 /* 13162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5307 /* 13166 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5308 /* 13166 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5309 /* 13171 */ GIR_RootConstrainSelectedInstOperands,
5310 /* 13172 */ // GIR_Coverage, 39,
5311 /* 13172 */ GIR_Done,
5312 /* 13173 */ // Label 515: @13173
5313 /* 13173 */ GIM_Reject,
5314 /* 13174 */ // Label 512: @13174
5315 /* 13174 */ GIM_Reject,
5316 /* 13175 */ // Label 510: @13175
5317 /* 13175 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(13212), // Rule ID 219 //
5318 /* 13180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5319 /* 13183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5320 /* 13186 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5321 /* 13193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5322 /* 13197 */ // MIs[0] ptr
5323 /* 13197 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5324 /* 13201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5325 /* 13205 */ // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5326 /* 13205 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5327 /* 13210 */ GIR_RootConstrainSelectedInstOperands,
5328 /* 13211 */ // GIR_Coverage, 219,
5329 /* 13211 */ GIR_Done,
5330 /* 13212 */ // Label 516: @13212
5331 /* 13212 */ GIM_Reject,
5332 /* 13213 */ // Label 511: @13213
5333 /* 13213 */ GIM_Reject,
5334 /* 13214 */ // Label 27: @13214
5335 /* 13214 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 519*/ GIMT_Encode4(13383),
5336 /* 13225 */ /*GILLT_s32*//*Label 517*/ GIMT_Encode4(13233),
5337 /* 13229 */ /*GILLT_s64*//*Label 518*/ GIMT_Encode4(13345),
5338 /* 13233 */ // Label 517: @13233
5339 /* 13233 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(13344),
5340 /* 13238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5341 /* 13241 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(13275), // Rule ID 34 //
5342 /* 13246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5343 /* 13249 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5344 /* 13256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5345 /* 13260 */ // MIs[0] ptr
5346 /* 13260 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5347 /* 13264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5348 /* 13268 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5349 /* 13268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5350 /* 13273 */ GIR_RootConstrainSelectedInstOperands,
5351 /* 13274 */ // GIR_Coverage, 34,
5352 /* 13274 */ GIR_Done,
5353 /* 13275 */ // Label 521: @13275
5354 /* 13275 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(13309), // Rule ID 35 //
5355 /* 13280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5356 /* 13283 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5357 /* 13290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5358 /* 13294 */ // MIs[0] ptr
5359 /* 13294 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5360 /* 13298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5361 /* 13302 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5362 /* 13302 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5363 /* 13307 */ GIR_RootConstrainSelectedInstOperands,
5364 /* 13308 */ // GIR_Coverage, 35,
5365 /* 13308 */ GIR_Done,
5366 /* 13309 */ // Label 522: @13309
5367 /* 13309 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(13343), // Rule ID 36 //
5368 /* 13314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5369 /* 13317 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5370 /* 13324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5371 /* 13328 */ // MIs[0] ptr
5372 /* 13328 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5373 /* 13332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5374 /* 13336 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5375 /* 13336 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5376 /* 13341 */ GIR_RootConstrainSelectedInstOperands,
5377 /* 13342 */ // GIR_Coverage, 36,
5378 /* 13342 */ GIR_Done,
5379 /* 13343 */ // Label 523: @13343
5380 /* 13343 */ GIM_Reject,
5381 /* 13344 */ // Label 520: @13344
5382 /* 13344 */ GIM_Reject,
5383 /* 13345 */ // Label 518: @13345
5384 /* 13345 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(13382), // Rule ID 218 //
5385 /* 13350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
5386 /* 13353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5387 /* 13356 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5388 /* 13363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5389 /* 13367 */ // MIs[0] ptr
5390 /* 13367 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5391 /* 13371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5392 /* 13375 */ // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5393 /* 13375 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5394 /* 13380 */ GIR_RootConstrainSelectedInstOperands,
5395 /* 13381 */ // GIR_Coverage, 218,
5396 /* 13381 */ GIR_Done,
5397 /* 13382 */ // Label 524: @13382
5398 /* 13382 */ GIM_Reject,
5399 /* 13383 */ // Label 519: @13383
5400 /* 13383 */ GIM_Reject,
5401 /* 13384 */ // Label 28: @13384
5402 /* 13384 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 527*/ GIMT_Encode4(19928),
5403 /* 13395 */ /*GILLT_s32*//*Label 525*/ GIMT_Encode4(13403),
5404 /* 13399 */ /*GILLT_s64*//*Label 526*/ GIMT_Encode4(19894),
5405 /* 13403 */ // Label 525: @13403
5406 /* 13403 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(13511), // Rule ID 2502 //
5407 /* 13408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5408 /* 13411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5409 /* 13415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5410 /* 13419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5411 /* 13423 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5412 /* 13427 */ // MIs[1] Operand 1
5413 /* 13427 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5414 /* 13432 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5415 /* 13436 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5416 /* 13440 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5417 /* 13444 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5418 /* 13448 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5419 /* 13452 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5420 /* 13456 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5421 /* 13460 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5422 /* 13464 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5423 /* 13468 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5424 /* 13472 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5425 /* 13476 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5426 /* 13480 */ // MIs[4] Operand 1
5427 /* 13480 */ // No operand predicates
5428 /* 13480 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5429 /* 13485 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5430 /* 13489 */ // MIs[0] offset
5431 /* 13489 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5432 /* 13492 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5433 /* 13494 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5434 /* 13494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5435 /* 13497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5436 /* 13501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5437 /* 13504 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5438 /* 13506 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5439 /* 13509 */ GIR_RootConstrainSelectedInstOperands,
5440 /* 13510 */ // GIR_Coverage, 2502,
5441 /* 13510 */ GIR_EraseRootFromParent_Done,
5442 /* 13511 */ // Label 528: @13511
5443 /* 13511 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(13626), // Rule ID 2503 //
5444 /* 13516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5445 /* 13519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5446 /* 13523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5447 /* 13527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5448 /* 13531 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5449 /* 13535 */ // MIs[1] Operand 1
5450 /* 13535 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5451 /* 13540 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5452 /* 13544 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5453 /* 13548 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5454 /* 13552 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5455 /* 13556 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5456 /* 13560 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5457 /* 13564 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5458 /* 13568 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5459 /* 13572 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5460 /* 13583 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5461 /* 13587 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5462 /* 13591 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5463 /* 13595 */ // MIs[4] Operand 1
5464 /* 13595 */ // No operand predicates
5465 /* 13595 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5466 /* 13600 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5467 /* 13604 */ // MIs[0] offset
5468 /* 13604 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5469 /* 13607 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5470 /* 13609 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5471 /* 13609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5472 /* 13612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5473 /* 13616 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5474 /* 13619 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5475 /* 13621 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5476 /* 13624 */ GIR_RootConstrainSelectedInstOperands,
5477 /* 13625 */ // GIR_Coverage, 2503,
5478 /* 13625 */ GIR_EraseRootFromParent_Done,
5479 /* 13626 */ // Label 529: @13626
5480 /* 13626 */ GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(13734), // Rule ID 2504 //
5481 /* 13631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5482 /* 13634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5483 /* 13638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5484 /* 13642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5485 /* 13646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5486 /* 13650 */ // MIs[1] Operand 1
5487 /* 13650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5488 /* 13655 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5489 /* 13659 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5490 /* 13663 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5491 /* 13667 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5492 /* 13671 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5493 /* 13675 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5494 /* 13679 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5495 /* 13683 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5496 /* 13687 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5497 /* 13691 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5498 /* 13695 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5499 /* 13699 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5500 /* 13703 */ // MIs[4] Operand 1
5501 /* 13703 */ // No operand predicates
5502 /* 13703 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5503 /* 13708 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5504 /* 13712 */ // MIs[0] offset
5505 /* 13712 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5506 /* 13715 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5507 /* 13717 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5508 /* 13717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5509 /* 13720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5510 /* 13724 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5511 /* 13727 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5512 /* 13729 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5513 /* 13732 */ GIR_RootConstrainSelectedInstOperands,
5514 /* 13733 */ // GIR_Coverage, 2504,
5515 /* 13733 */ GIR_EraseRootFromParent_Done,
5516 /* 13734 */ // Label 530: @13734
5517 /* 13734 */ GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(13849), // Rule ID 2505 //
5518 /* 13739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5519 /* 13742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5520 /* 13746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5521 /* 13750 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5522 /* 13754 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5523 /* 13758 */ // MIs[1] Operand 1
5524 /* 13758 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5525 /* 13763 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5526 /* 13767 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5527 /* 13771 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5528 /* 13775 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5529 /* 13779 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5530 /* 13783 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5531 /* 13787 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5532 /* 13791 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5533 /* 13795 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5534 /* 13806 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5535 /* 13810 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5536 /* 13814 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5537 /* 13818 */ // MIs[4] Operand 1
5538 /* 13818 */ // No operand predicates
5539 /* 13818 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5540 /* 13823 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5541 /* 13827 */ // MIs[0] offset
5542 /* 13827 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5543 /* 13830 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5544 /* 13832 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5545 /* 13832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5546 /* 13835 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5547 /* 13839 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5548 /* 13842 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5549 /* 13844 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5550 /* 13847 */ GIR_RootConstrainSelectedInstOperands,
5551 /* 13848 */ // GIR_Coverage, 2505,
5552 /* 13848 */ GIR_EraseRootFromParent_Done,
5553 /* 13849 */ // Label 531: @13849
5554 /* 13849 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(13957), // Rule ID 294 //
5555 /* 13854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5556 /* 13857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5557 /* 13861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5558 /* 13865 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5559 /* 13869 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5560 /* 13873 */ // MIs[1] Operand 1
5561 /* 13873 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5562 /* 13878 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5563 /* 13882 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5564 /* 13886 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5565 /* 13890 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5566 /* 13894 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5567 /* 13899 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5568 /* 13903 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5569 /* 13907 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5570 /* 13911 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5571 /* 13915 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5572 /* 13919 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5573 /* 13923 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5574 /* 13927 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5575 /* 13931 */ // MIs[4] Operand 1
5576 /* 13931 */ // No operand predicates
5577 /* 13931 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5578 /* 13935 */ // MIs[0] offset
5579 /* 13935 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5580 /* 13938 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5581 /* 13940 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5582 /* 13940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5583 /* 13943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5584 /* 13947 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5585 /* 13950 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5586 /* 13952 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5587 /* 13955 */ GIR_RootConstrainSelectedInstOperands,
5588 /* 13956 */ // GIR_Coverage, 294,
5589 /* 13956 */ GIR_EraseRootFromParent_Done,
5590 /* 13957 */ // Label 532: @13957
5591 /* 13957 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(14072), // Rule ID 295 //
5592 /* 13962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5593 /* 13965 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5594 /* 13969 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5595 /* 13973 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5596 /* 13977 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5597 /* 13981 */ // MIs[1] Operand 1
5598 /* 13981 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5599 /* 13986 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5600 /* 13990 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5601 /* 13994 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5602 /* 13998 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5603 /* 14002 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5604 /* 14007 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5605 /* 14011 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5606 /* 14015 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5607 /* 14019 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5608 /* 14023 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5609 /* 14034 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5610 /* 14038 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5611 /* 14042 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5612 /* 14046 */ // MIs[4] Operand 1
5613 /* 14046 */ // No operand predicates
5614 /* 14046 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5615 /* 14050 */ // MIs[0] offset
5616 /* 14050 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5617 /* 14053 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5618 /* 14055 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5619 /* 14055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5620 /* 14058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5621 /* 14062 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5622 /* 14065 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5623 /* 14067 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5624 /* 14070 */ GIR_RootConstrainSelectedInstOperands,
5625 /* 14071 */ // GIR_Coverage, 295,
5626 /* 14071 */ GIR_EraseRootFromParent_Done,
5627 /* 14072 */ // Label 533: @14072
5628 /* 14072 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(14180), // Rule ID 296 //
5629 /* 14077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5630 /* 14080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5631 /* 14084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5632 /* 14088 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5633 /* 14092 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5634 /* 14096 */ // MIs[1] Operand 1
5635 /* 14096 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5636 /* 14101 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5637 /* 14105 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5638 /* 14109 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5639 /* 14113 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5640 /* 14117 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5641 /* 14122 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5642 /* 14126 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5643 /* 14130 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5644 /* 14134 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5645 /* 14138 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5646 /* 14142 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5647 /* 14146 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5648 /* 14150 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5649 /* 14154 */ // MIs[4] Operand 1
5650 /* 14154 */ // No operand predicates
5651 /* 14154 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5652 /* 14158 */ // MIs[0] offset
5653 /* 14158 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5654 /* 14161 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5655 /* 14163 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5656 /* 14163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5657 /* 14166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5658 /* 14170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5659 /* 14173 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5660 /* 14175 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5661 /* 14178 */ GIR_RootConstrainSelectedInstOperands,
5662 /* 14179 */ // GIR_Coverage, 296,
5663 /* 14179 */ GIR_EraseRootFromParent_Done,
5664 /* 14180 */ // Label 534: @14180
5665 /* 14180 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(14295), // Rule ID 297 //
5666 /* 14185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
5667 /* 14188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5668 /* 14192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5669 /* 14196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5670 /* 14200 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5671 /* 14204 */ // MIs[1] Operand 1
5672 /* 14204 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5673 /* 14209 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5674 /* 14213 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5675 /* 14217 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5676 /* 14221 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5677 /* 14225 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5678 /* 14230 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5679 /* 14234 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5680 /* 14238 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5681 /* 14242 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5682 /* 14246 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5683 /* 14257 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5684 /* 14261 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5685 /* 14265 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5686 /* 14269 */ // MIs[4] Operand 1
5687 /* 14269 */ // No operand predicates
5688 /* 14269 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5689 /* 14273 */ // MIs[0] offset
5690 /* 14273 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5691 /* 14276 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5692 /* 14278 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5693 /* 14278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5694 /* 14281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5695 /* 14285 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5696 /* 14288 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5697 /* 14290 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5698 /* 14293 */ GIR_RootConstrainSelectedInstOperands,
5699 /* 14294 */ // GIR_Coverage, 297,
5700 /* 14294 */ GIR_EraseRootFromParent_Done,
5701 /* 14295 */ // Label 535: @14295
5702 /* 14295 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(14352), // Rule ID 94 //
5703 /* 14300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5704 /* 14303 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5705 /* 14307 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5706 /* 14311 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5707 /* 14315 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5708 /* 14319 */ // MIs[1] Operand 1
5709 /* 14319 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5710 /* 14324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5711 /* 14329 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5712 /* 14333 */ // MIs[0] offset
5713 /* 14333 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5714 /* 14336 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5715 /* 14338 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5716 /* 14338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5717 /* 14341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5718 /* 14345 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5719 /* 14347 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5720 /* 14350 */ GIR_RootConstrainSelectedInstOperands,
5721 /* 14351 */ // GIR_Coverage, 94,
5722 /* 14351 */ GIR_EraseRootFromParent_Done,
5723 /* 14352 */ // Label 536: @14352
5724 /* 14352 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(14409), // Rule ID 95 //
5725 /* 14357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5726 /* 14360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5727 /* 14364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5728 /* 14368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5729 /* 14372 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5730 /* 14376 */ // MIs[1] Operand 1
5731 /* 14376 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5732 /* 14381 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5733 /* 14386 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5734 /* 14390 */ // MIs[0] offset
5735 /* 14390 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5736 /* 14393 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5737 /* 14395 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5738 /* 14395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
5739 /* 14398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5740 /* 14402 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5741 /* 14404 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5742 /* 14407 */ GIR_RootConstrainSelectedInstOperands,
5743 /* 14408 */ // GIR_Coverage, 95,
5744 /* 14408 */ GIR_EraseRootFromParent_Done,
5745 /* 14409 */ // Label 537: @14409
5746 /* 14409 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(14466), // Rule ID 96 //
5747 /* 14414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5748 /* 14417 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5749 /* 14421 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5750 /* 14425 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5751 /* 14429 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5752 /* 14433 */ // MIs[1] Operand 1
5753 /* 14433 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5754 /* 14438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5755 /* 14443 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5756 /* 14447 */ // MIs[0] offset
5757 /* 14447 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5758 /* 14450 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5759 /* 14452 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5760 /* 14452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5761 /* 14455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5762 /* 14459 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5763 /* 14461 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5764 /* 14464 */ GIR_RootConstrainSelectedInstOperands,
5765 /* 14465 */ // GIR_Coverage, 96,
5766 /* 14465 */ GIR_EraseRootFromParent_Done,
5767 /* 14466 */ // Label 538: @14466
5768 /* 14466 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(14523), // Rule ID 97 //
5769 /* 14471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5770 /* 14474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5771 /* 14478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5772 /* 14482 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5773 /* 14486 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5774 /* 14490 */ // MIs[1] Operand 1
5775 /* 14490 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5776 /* 14495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5777 /* 14500 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5778 /* 14504 */ // MIs[0] offset
5779 /* 14504 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5780 /* 14507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5781 /* 14509 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5782 /* 14509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
5783 /* 14512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5784 /* 14516 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5785 /* 14518 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5786 /* 14521 */ GIR_RootConstrainSelectedInstOperands,
5787 /* 14522 */ // GIR_Coverage, 97,
5788 /* 14522 */ GIR_EraseRootFromParent_Done,
5789 /* 14523 */ // Label 539: @14523
5790 /* 14523 */ GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(14580), // Rule ID 269 //
5791 /* 14528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5792 /* 14531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5793 /* 14535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5794 /* 14539 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5795 /* 14543 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5796 /* 14547 */ // MIs[1] Operand 1
5797 /* 14547 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5798 /* 14552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5799 /* 14557 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5800 /* 14561 */ // MIs[0] offset
5801 /* 14561 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5802 /* 14564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5803 /* 14566 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5804 /* 14566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5805 /* 14569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5806 /* 14573 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5807 /* 14575 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5808 /* 14578 */ GIR_RootConstrainSelectedInstOperands,
5809 /* 14579 */ // GIR_Coverage, 269,
5810 /* 14579 */ GIR_EraseRootFromParent_Done,
5811 /* 14580 */ // Label 540: @14580
5812 /* 14580 */ GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(14637), // Rule ID 270 //
5813 /* 14585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5814 /* 14588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5815 /* 14592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5816 /* 14596 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5817 /* 14600 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5818 /* 14604 */ // MIs[1] Operand 1
5819 /* 14604 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5820 /* 14609 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5821 /* 14614 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5822 /* 14618 */ // MIs[0] offset
5823 /* 14618 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5824 /* 14621 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5825 /* 14623 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5826 /* 14623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
5827 /* 14626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5828 /* 14630 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5829 /* 14632 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5830 /* 14635 */ GIR_RootConstrainSelectedInstOperands,
5831 /* 14636 */ // GIR_Coverage, 270,
5832 /* 14636 */ GIR_EraseRootFromParent_Done,
5833 /* 14637 */ // Label 541: @14637
5834 /* 14637 */ GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(14694), // Rule ID 271 //
5835 /* 14642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5836 /* 14645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5837 /* 14649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5838 /* 14653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5839 /* 14657 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5840 /* 14661 */ // MIs[1] Operand 1
5841 /* 14661 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5842 /* 14666 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5843 /* 14671 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5844 /* 14675 */ // MIs[0] offset
5845 /* 14675 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5846 /* 14678 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5847 /* 14680 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5848 /* 14680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5849 /* 14683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5850 /* 14687 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5851 /* 14689 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5852 /* 14692 */ GIR_RootConstrainSelectedInstOperands,
5853 /* 14693 */ // GIR_Coverage, 271,
5854 /* 14693 */ GIR_EraseRootFromParent_Done,
5855 /* 14694 */ // Label 542: @14694
5856 /* 14694 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(14751), // Rule ID 272 //
5857 /* 14699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5858 /* 14702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5859 /* 14706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5860 /* 14710 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5861 /* 14714 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5862 /* 14718 */ // MIs[1] Operand 1
5863 /* 14718 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5864 /* 14723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5865 /* 14728 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5866 /* 14732 */ // MIs[0] offset
5867 /* 14732 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5868 /* 14735 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5869 /* 14737 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5870 /* 14737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5871 /* 14740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5872 /* 14744 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5873 /* 14746 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5874 /* 14749 */ GIR_RootConstrainSelectedInstOperands,
5875 /* 14750 */ // GIR_Coverage, 272,
5876 /* 14750 */ GIR_EraseRootFromParent_Done,
5877 /* 14751 */ // Label 543: @14751
5878 /* 14751 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(14808), // Rule ID 1133 //
5879 /* 14756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5880 /* 14759 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5881 /* 14763 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5882 /* 14767 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5883 /* 14771 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5884 /* 14775 */ // MIs[1] Operand 1
5885 /* 14775 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5886 /* 14780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5887 /* 14785 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5888 /* 14789 */ // MIs[0] offset
5889 /* 14789 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5890 /* 14792 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5891 /* 14794 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5892 /* 14794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5893 /* 14797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5894 /* 14801 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5895 /* 14803 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5896 /* 14806 */ GIR_RootConstrainSelectedInstOperands,
5897 /* 14807 */ // GIR_Coverage, 1133,
5898 /* 14807 */ GIR_EraseRootFromParent_Done,
5899 /* 14808 */ // Label 544: @14808
5900 /* 14808 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(14865), // Rule ID 1134 //
5901 /* 14813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5902 /* 14816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5903 /* 14820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5904 /* 14824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5905 /* 14828 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5906 /* 14832 */ // MIs[1] Operand 1
5907 /* 14832 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5908 /* 14837 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5909 /* 14842 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5910 /* 14846 */ // MIs[0] offset
5911 /* 14846 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5912 /* 14849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5913 /* 14851 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5914 /* 14851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5915 /* 14854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5916 /* 14858 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5917 /* 14860 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5918 /* 14863 */ GIR_RootConstrainSelectedInstOperands,
5919 /* 14864 */ // GIR_Coverage, 1134,
5920 /* 14864 */ GIR_EraseRootFromParent_Done,
5921 /* 14865 */ // Label 545: @14865
5922 /* 14865 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(14922), // Rule ID 1135 //
5923 /* 14870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5924 /* 14873 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5925 /* 14877 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5926 /* 14881 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5927 /* 14885 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5928 /* 14889 */ // MIs[1] Operand 1
5929 /* 14889 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5930 /* 14894 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5931 /* 14899 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5932 /* 14903 */ // MIs[0] offset
5933 /* 14903 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5934 /* 14906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5935 /* 14908 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5936 /* 14908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5937 /* 14911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5938 /* 14915 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5939 /* 14917 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5940 /* 14920 */ GIR_RootConstrainSelectedInstOperands,
5941 /* 14921 */ // GIR_Coverage, 1135,
5942 /* 14921 */ GIR_EraseRootFromParent_Done,
5943 /* 14922 */ // Label 546: @14922
5944 /* 14922 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(14979), // Rule ID 1136 //
5945 /* 14927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5946 /* 14930 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5947 /* 14934 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5948 /* 14938 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5949 /* 14942 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5950 /* 14946 */ // MIs[1] Operand 1
5951 /* 14946 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5952 /* 14951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5953 /* 14956 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5954 /* 14960 */ // MIs[0] offset
5955 /* 14960 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5956 /* 14963 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5957 /* 14965 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5958 /* 14965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5959 /* 14968 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5960 /* 14972 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5961 /* 14974 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5962 /* 14977 */ GIR_RootConstrainSelectedInstOperands,
5963 /* 14978 */ // GIR_Coverage, 1136,
5964 /* 14978 */ GIR_EraseRootFromParent_Done,
5965 /* 14979 */ // Label 547: @14979
5966 /* 14979 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(15042), // Rule ID 1425 //
5967 /* 14984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5968 /* 14987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5969 /* 14991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5970 /* 14995 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5971 /* 14999 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5972 /* 15003 */ // MIs[1] Operand 1
5973 /* 15003 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5974 /* 15008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5975 /* 15013 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5976 /* 15017 */ // MIs[0] dst
5977 /* 15017 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5978 /* 15020 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5979 /* 15022 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5980 /* 15022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5981 /* 15025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5982 /* 15029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5983 /* 15035 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5984 /* 15037 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5985 /* 15040 */ GIR_RootConstrainSelectedInstOperands,
5986 /* 15041 */ // GIR_Coverage, 1425,
5987 /* 15041 */ GIR_EraseRootFromParent_Done,
5988 /* 15042 */ // Label 548: @15042
5989 /* 15042 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(15105), // Rule ID 1426 //
5990 /* 15047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5991 /* 15050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5992 /* 15054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5993 /* 15058 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5994 /* 15062 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5995 /* 15066 */ // MIs[1] Operand 1
5996 /* 15066 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5997 /* 15071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5998 /* 15076 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5999 /* 15080 */ // MIs[0] dst
6000 /* 15080 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6001 /* 15083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6002 /* 15085 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6003 /* 15085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6004 /* 15088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6005 /* 15092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6006 /* 15098 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6007 /* 15100 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6008 /* 15103 */ GIR_RootConstrainSelectedInstOperands,
6009 /* 15104 */ // GIR_Coverage, 1426,
6010 /* 15104 */ GIR_EraseRootFromParent_Done,
6011 /* 15105 */ // Label 549: @15105
6012 /* 15105 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(15168), // Rule ID 1650 //
6013 /* 15110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6014 /* 15113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6015 /* 15117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6016 /* 15121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6017 /* 15125 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6018 /* 15129 */ // MIs[1] Operand 1
6019 /* 15129 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6020 /* 15134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6021 /* 15139 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6022 /* 15143 */ // MIs[0] dst
6023 /* 15143 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6024 /* 15146 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6025 /* 15148 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6026 /* 15148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6027 /* 15151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6028 /* 15155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6029 /* 15161 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6030 /* 15163 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6031 /* 15166 */ GIR_RootConstrainSelectedInstOperands,
6032 /* 15167 */ // GIR_Coverage, 1650,
6033 /* 15167 */ GIR_EraseRootFromParent_Done,
6034 /* 15168 */ // Label 550: @15168
6035 /* 15168 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(15231), // Rule ID 1651 //
6036 /* 15173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6037 /* 15176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6038 /* 15180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6039 /* 15184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6040 /* 15188 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6041 /* 15192 */ // MIs[1] Operand 1
6042 /* 15192 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6043 /* 15197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6044 /* 15202 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6045 /* 15206 */ // MIs[0] dst
6046 /* 15206 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6047 /* 15209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6048 /* 15211 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6049 /* 15211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6050 /* 15214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6051 /* 15218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6052 /* 15224 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6053 /* 15226 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6054 /* 15229 */ GIR_RootConstrainSelectedInstOperands,
6055 /* 15230 */ // GIR_Coverage, 1651,
6056 /* 15230 */ GIR_EraseRootFromParent_Done,
6057 /* 15231 */ // Label 551: @15231
6058 /* 15231 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(15285), // Rule ID 1982 //
6059 /* 15236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6060 /* 15239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6061 /* 15243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6062 /* 15247 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6063 /* 15251 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6064 /* 15255 */ // MIs[1] Operand 1
6065 /* 15255 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6066 /* 15260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6067 /* 15265 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6068 /* 15269 */ // MIs[0] targ16
6069 /* 15269 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6070 /* 15272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6071 /* 15274 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6072 /* 15274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
6073 /* 15277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6074 /* 15281 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6075 /* 15283 */ GIR_RootConstrainSelectedInstOperands,
6076 /* 15284 */ // GIR_Coverage, 1982,
6077 /* 15284 */ GIR_EraseRootFromParent_Done,
6078 /* 15285 */ // Label 552: @15285
6079 /* 15285 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(15339), // Rule ID 1991 //
6080 /* 15290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6081 /* 15293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6082 /* 15297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6083 /* 15301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6084 /* 15305 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6085 /* 15309 */ // MIs[1] Operand 1
6086 /* 15309 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6087 /* 15314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6088 /* 15319 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6089 /* 15323 */ // MIs[0] targ16
6090 /* 15323 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6091 /* 15326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6092 /* 15328 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6093 /* 15328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
6094 /* 15331 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6095 /* 15335 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
6096 /* 15337 */ GIR_RootConstrainSelectedInstOperands,
6097 /* 15338 */ // GIR_Coverage, 1991,
6098 /* 15338 */ GIR_EraseRootFromParent_Done,
6099 /* 15339 */ // Label 553: @15339
6100 /* 15339 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(15402), // Rule ID 2321 //
6101 /* 15344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6102 /* 15347 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6103 /* 15351 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6104 /* 15355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6105 /* 15359 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6106 /* 15363 */ // MIs[1] Operand 1
6107 /* 15363 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6108 /* 15368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6109 /* 15373 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6110 /* 15377 */ // MIs[0] dst
6111 /* 15377 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6112 /* 15380 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6113 /* 15382 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6114 /* 15382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6115 /* 15385 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6116 /* 15389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6117 /* 15395 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6118 /* 15397 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6119 /* 15400 */ GIR_RootConstrainSelectedInstOperands,
6120 /* 15401 */ // GIR_Coverage, 2321,
6121 /* 15401 */ GIR_EraseRootFromParent_Done,
6122 /* 15402 */ // Label 554: @15402
6123 /* 15402 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(15465), // Rule ID 2322 //
6124 /* 15407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6125 /* 15410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6126 /* 15414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6127 /* 15418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6128 /* 15422 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6129 /* 15426 */ // MIs[1] Operand 1
6130 /* 15426 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6131 /* 15431 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6132 /* 15436 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6133 /* 15440 */ // MIs[0] dst
6134 /* 15440 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6135 /* 15443 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6136 /* 15445 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6137 /* 15445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6138 /* 15448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6139 /* 15452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6140 /* 15458 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6141 /* 15460 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6142 /* 15463 */ GIR_RootConstrainSelectedInstOperands,
6143 /* 15464 */ // GIR_Coverage, 2322,
6144 /* 15464 */ GIR_EraseRootFromParent_Done,
6145 /* 15465 */ // Label 555: @15465
6146 /* 15465 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(15522), // Rule ID 2473 //
6147 /* 15470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6148 /* 15473 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6149 /* 15477 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6150 /* 15481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6151 /* 15485 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6152 /* 15489 */ // MIs[1] Operand 1
6153 /* 15489 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6154 /* 15494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6155 /* 15499 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6156 /* 15503 */ // MIs[0] dst
6157 /* 15503 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6158 /* 15506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6159 /* 15508 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6160 /* 15508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
6161 /* 15511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6162 /* 15515 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6163 /* 15517 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6164 /* 15520 */ GIR_RootConstrainSelectedInstOperands,
6165 /* 15521 */ // GIR_Coverage, 2473,
6166 /* 15521 */ GIR_EraseRootFromParent_Done,
6167 /* 15522 */ // Label 556: @15522
6168 /* 15522 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(15579), // Rule ID 2474 //
6169 /* 15527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6170 /* 15530 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6171 /* 15534 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6172 /* 15538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6173 /* 15542 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6174 /* 15546 */ // MIs[1] Operand 1
6175 /* 15546 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6176 /* 15551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6177 /* 15556 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6178 /* 15560 */ // MIs[0] dst
6179 /* 15560 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6180 /* 15563 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6181 /* 15565 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6182 /* 15565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6183 /* 15568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6184 /* 15572 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6185 /* 15574 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6186 /* 15577 */ GIR_RootConstrainSelectedInstOperands,
6187 /* 15578 */ // GIR_Coverage, 2474,
6188 /* 15578 */ GIR_EraseRootFromParent_Done,
6189 /* 15579 */ // Label 557: @15579
6190 /* 15579 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(15631), // Rule ID 1436 //
6191 /* 15584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6192 /* 15587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6193 /* 15591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6194 /* 15595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6195 /* 15599 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6196 /* 15603 */ // MIs[1] Operand 1
6197 /* 15603 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6198 /* 15608 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6199 /* 15612 */ // MIs[0] dst
6200 /* 15612 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6201 /* 15615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6202 /* 15617 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6203 /* 15617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
6204 /* 15620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6205 /* 15624 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6206 /* 15626 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6207 /* 15629 */ GIR_RootConstrainSelectedInstOperands,
6208 /* 15630 */ // GIR_Coverage, 1436,
6209 /* 15630 */ GIR_EraseRootFromParent_Done,
6210 /* 15631 */ // Label 558: @15631
6211 /* 15631 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(15683), // Rule ID 1437 //
6212 /* 15636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6213 /* 15639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6214 /* 15643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6215 /* 15647 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6216 /* 15651 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6217 /* 15655 */ // MIs[1] Operand 1
6218 /* 15655 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6219 /* 15660 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6220 /* 15664 */ // MIs[0] dst
6221 /* 15664 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6222 /* 15667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6223 /* 15669 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6224 /* 15669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
6225 /* 15672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6226 /* 15676 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6227 /* 15678 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6228 /* 15681 */ GIR_RootConstrainSelectedInstOperands,
6229 /* 15682 */ // GIR_Coverage, 1437,
6230 /* 15682 */ GIR_EraseRootFromParent_Done,
6231 /* 15683 */ // Label 559: @15683
6232 /* 15683 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(15735), // Rule ID 1661 //
6233 /* 15688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6234 /* 15691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6235 /* 15695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6236 /* 15699 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6237 /* 15703 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6238 /* 15707 */ // MIs[1] Operand 1
6239 /* 15707 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6240 /* 15712 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6241 /* 15716 */ // MIs[0] dst
6242 /* 15716 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6243 /* 15719 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6244 /* 15721 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6245 /* 15721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
6246 /* 15724 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6247 /* 15728 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6248 /* 15730 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6249 /* 15733 */ GIR_RootConstrainSelectedInstOperands,
6250 /* 15734 */ // GIR_Coverage, 1661,
6251 /* 15734 */ GIR_EraseRootFromParent_Done,
6252 /* 15735 */ // Label 560: @15735
6253 /* 15735 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(15787), // Rule ID 1662 //
6254 /* 15740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6255 /* 15743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6256 /* 15747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6257 /* 15751 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6258 /* 15755 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6259 /* 15759 */ // MIs[1] Operand 1
6260 /* 15759 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6261 /* 15764 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6262 /* 15768 */ // MIs[0] dst
6263 /* 15768 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6264 /* 15771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6265 /* 15773 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
6266 /* 15773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
6267 /* 15776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6268 /* 15780 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6269 /* 15782 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6270 /* 15785 */ GIR_RootConstrainSelectedInstOperands,
6271 /* 15786 */ // GIR_Coverage, 1662,
6272 /* 15786 */ GIR_EraseRootFromParent_Done,
6273 /* 15787 */ // Label 561: @15787
6274 /* 15787 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(15839), // Rule ID 1892 //
6275 /* 15792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6276 /* 15795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6277 /* 15799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6278 /* 15803 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6279 /* 15807 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6280 /* 15811 */ // MIs[1] Operand 1
6281 /* 15811 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6282 /* 15816 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6283 /* 15820 */ // MIs[0] offset
6284 /* 15820 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6285 /* 15823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6286 /* 15825 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6287 /* 15825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6288 /* 15828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6289 /* 15832 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6290 /* 15834 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6291 /* 15837 */ GIR_RootConstrainSelectedInstOperands,
6292 /* 15838 */ // GIR_Coverage, 1892,
6293 /* 15838 */ GIR_EraseRootFromParent_Done,
6294 /* 15839 */ // Label 562: @15839
6295 /* 15839 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(15891), // Rule ID 1893 //
6296 /* 15844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6297 /* 15847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6298 /* 15851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6299 /* 15855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6300 /* 15859 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6301 /* 15863 */ // MIs[1] Operand 1
6302 /* 15863 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6303 /* 15868 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6304 /* 15872 */ // MIs[0] offset
6305 /* 15872 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6306 /* 15875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6307 /* 15877 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6308 /* 15877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6309 /* 15880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6310 /* 15884 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6311 /* 15886 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6312 /* 15889 */ GIR_RootConstrainSelectedInstOperands,
6313 /* 15890 */ // GIR_Coverage, 1893,
6314 /* 15890 */ GIR_EraseRootFromParent_Done,
6315 /* 15891 */ // Label 563: @15891
6316 /* 15891 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(15943), // Rule ID 1894 //
6317 /* 15896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6318 /* 15899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6319 /* 15903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6320 /* 15907 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6321 /* 15911 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6322 /* 15915 */ // MIs[1] Operand 1
6323 /* 15915 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6324 /* 15920 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6325 /* 15924 */ // MIs[0] offset
6326 /* 15924 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6327 /* 15927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6328 /* 15929 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6329 /* 15929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6330 /* 15932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6331 /* 15936 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6332 /* 15938 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6333 /* 15941 */ GIR_RootConstrainSelectedInstOperands,
6334 /* 15942 */ // GIR_Coverage, 1894,
6335 /* 15942 */ GIR_EraseRootFromParent_Done,
6336 /* 15943 */ // Label 564: @15943
6337 /* 15943 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(15995), // Rule ID 1895 //
6338 /* 15948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6339 /* 15951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6340 /* 15955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6341 /* 15959 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6342 /* 15963 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6343 /* 15967 */ // MIs[1] Operand 1
6344 /* 15967 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6345 /* 15972 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6346 /* 15976 */ // MIs[0] offset
6347 /* 15976 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6348 /* 15979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6349 /* 15981 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6350 /* 15981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6351 /* 15984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6352 /* 15988 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6353 /* 15990 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6354 /* 15993 */ GIR_RootConstrainSelectedInstOperands,
6355 /* 15994 */ // GIR_Coverage, 1895,
6356 /* 15994 */ GIR_EraseRootFromParent_Done,
6357 /* 15995 */ // Label 565: @15995
6358 /* 15995 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(16047), // Rule ID 1896 //
6359 /* 16000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6360 /* 16003 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6361 /* 16007 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6362 /* 16011 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6363 /* 16015 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6364 /* 16019 */ // MIs[1] Operand 1
6365 /* 16019 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6366 /* 16024 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6367 /* 16028 */ // MIs[0] offset
6368 /* 16028 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6369 /* 16031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6370 /* 16033 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6371 /* 16033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6372 /* 16036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6373 /* 16040 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6374 /* 16042 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6375 /* 16045 */ GIR_RootConstrainSelectedInstOperands,
6376 /* 16046 */ // GIR_Coverage, 1896,
6377 /* 16046 */ GIR_EraseRootFromParent_Done,
6378 /* 16047 */ // Label 566: @16047
6379 /* 16047 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(16099), // Rule ID 1897 //
6380 /* 16052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6381 /* 16055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6382 /* 16059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6383 /* 16063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6384 /* 16067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6385 /* 16071 */ // MIs[1] Operand 1
6386 /* 16071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6387 /* 16076 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6388 /* 16080 */ // MIs[0] offset
6389 /* 16080 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6390 /* 16083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6391 /* 16085 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6392 /* 16085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6393 /* 16088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6394 /* 16092 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6395 /* 16094 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6396 /* 16097 */ GIR_RootConstrainSelectedInstOperands,
6397 /* 16098 */ // GIR_Coverage, 1897,
6398 /* 16098 */ GIR_EraseRootFromParent_Done,
6399 /* 16099 */ // Label 567: @16099
6400 /* 16099 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(16151), // Rule ID 1898 //
6401 /* 16104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6402 /* 16107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6403 /* 16111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6404 /* 16115 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6405 /* 16119 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6406 /* 16123 */ // MIs[1] Operand 1
6407 /* 16123 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6408 /* 16128 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6409 /* 16132 */ // MIs[0] offset
6410 /* 16132 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6411 /* 16135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6412 /* 16137 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6413 /* 16137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6414 /* 16140 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6415 /* 16144 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6416 /* 16146 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6417 /* 16149 */ GIR_RootConstrainSelectedInstOperands,
6418 /* 16150 */ // GIR_Coverage, 1898,
6419 /* 16150 */ GIR_EraseRootFromParent_Done,
6420 /* 16151 */ // Label 568: @16151
6421 /* 16151 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(16203), // Rule ID 1899 //
6422 /* 16156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6423 /* 16159 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6424 /* 16163 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6425 /* 16167 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6426 /* 16171 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6427 /* 16175 */ // MIs[1] Operand 1
6428 /* 16175 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6429 /* 16180 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6430 /* 16184 */ // MIs[0] offset
6431 /* 16184 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6432 /* 16187 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6433 /* 16189 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6434 /* 16189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6435 /* 16192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6436 /* 16196 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6437 /* 16198 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6438 /* 16201 */ GIR_RootConstrainSelectedInstOperands,
6439 /* 16202 */ // GIR_Coverage, 1899,
6440 /* 16202 */ GIR_EraseRootFromParent_Done,
6441 /* 16203 */ // Label 569: @16203
6442 /* 16203 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(16255), // Rule ID 1935 //
6443 /* 16208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6444 /* 16211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6445 /* 16215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6446 /* 16219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6447 /* 16223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6448 /* 16227 */ // MIs[1] Operand 1
6449 /* 16227 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6450 /* 16232 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6451 /* 16236 */ // MIs[0] offset
6452 /* 16236 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6453 /* 16239 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6454 /* 16241 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6455 /* 16241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6456 /* 16244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6457 /* 16248 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6458 /* 16250 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6459 /* 16253 */ GIR_RootConstrainSelectedInstOperands,
6460 /* 16254 */ // GIR_Coverage, 1935,
6461 /* 16254 */ GIR_EraseRootFromParent_Done,
6462 /* 16255 */ // Label 570: @16255
6463 /* 16255 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(16307), // Rule ID 1936 //
6464 /* 16260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6465 /* 16263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6466 /* 16267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6467 /* 16271 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6468 /* 16275 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6469 /* 16279 */ // MIs[1] Operand 1
6470 /* 16279 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6471 /* 16284 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6472 /* 16288 */ // MIs[0] offset
6473 /* 16288 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6474 /* 16291 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6475 /* 16293 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6476 /* 16293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6477 /* 16296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6478 /* 16300 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6479 /* 16302 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6480 /* 16305 */ GIR_RootConstrainSelectedInstOperands,
6481 /* 16306 */ // GIR_Coverage, 1936,
6482 /* 16306 */ GIR_EraseRootFromParent_Done,
6483 /* 16307 */ // Label 571: @16307
6484 /* 16307 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(16359), // Rule ID 1937 //
6485 /* 16312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6486 /* 16315 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6487 /* 16319 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6488 /* 16323 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6489 /* 16327 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6490 /* 16331 */ // MIs[1] Operand 1
6491 /* 16331 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6492 /* 16336 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6493 /* 16340 */ // MIs[0] offset
6494 /* 16340 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6495 /* 16343 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6496 /* 16345 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6497 /* 16345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6498 /* 16348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6499 /* 16352 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6500 /* 16354 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6501 /* 16357 */ GIR_RootConstrainSelectedInstOperands,
6502 /* 16358 */ // GIR_Coverage, 1937,
6503 /* 16358 */ GIR_EraseRootFromParent_Done,
6504 /* 16359 */ // Label 572: @16359
6505 /* 16359 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(16411), // Rule ID 1938 //
6506 /* 16364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6507 /* 16367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6508 /* 16371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6509 /* 16375 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6510 /* 16379 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6511 /* 16383 */ // MIs[1] Operand 1
6512 /* 16383 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6513 /* 16388 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6514 /* 16392 */ // MIs[0] offset
6515 /* 16392 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6516 /* 16395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6517 /* 16397 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6518 /* 16397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6519 /* 16400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6520 /* 16404 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6521 /* 16406 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6522 /* 16409 */ GIR_RootConstrainSelectedInstOperands,
6523 /* 16410 */ // GIR_Coverage, 1938,
6524 /* 16410 */ GIR_EraseRootFromParent_Done,
6525 /* 16411 */ // Label 573: @16411
6526 /* 16411 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(16463), // Rule ID 1939 //
6527 /* 16416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6528 /* 16419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6529 /* 16423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6530 /* 16427 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6531 /* 16431 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6532 /* 16435 */ // MIs[1] Operand 1
6533 /* 16435 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6534 /* 16440 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6535 /* 16444 */ // MIs[0] offset
6536 /* 16444 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6537 /* 16447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6538 /* 16449 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6539 /* 16449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6540 /* 16452 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6541 /* 16456 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6542 /* 16458 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6543 /* 16461 */ GIR_RootConstrainSelectedInstOperands,
6544 /* 16462 */ // GIR_Coverage, 1939,
6545 /* 16462 */ GIR_EraseRootFromParent_Done,
6546 /* 16463 */ // Label 574: @16463
6547 /* 16463 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(16515), // Rule ID 1940 //
6548 /* 16468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6549 /* 16471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6550 /* 16475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6551 /* 16479 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6552 /* 16483 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6553 /* 16487 */ // MIs[1] Operand 1
6554 /* 16487 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6555 /* 16492 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6556 /* 16496 */ // MIs[0] offset
6557 /* 16496 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6558 /* 16499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6559 /* 16501 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6560 /* 16501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6561 /* 16504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6562 /* 16508 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6563 /* 16510 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6564 /* 16513 */ GIR_RootConstrainSelectedInstOperands,
6565 /* 16514 */ // GIR_Coverage, 1940,
6566 /* 16514 */ GIR_EraseRootFromParent_Done,
6567 /* 16515 */ // Label 575: @16515
6568 /* 16515 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(16567), // Rule ID 1941 //
6569 /* 16520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6570 /* 16523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6571 /* 16527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6572 /* 16531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6573 /* 16535 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6574 /* 16539 */ // MIs[1] Operand 1
6575 /* 16539 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6576 /* 16544 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6577 /* 16548 */ // MIs[0] offset
6578 /* 16548 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6579 /* 16551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6580 /* 16553 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6581 /* 16553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6582 /* 16556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6583 /* 16560 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6584 /* 16562 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6585 /* 16565 */ GIR_RootConstrainSelectedInstOperands,
6586 /* 16566 */ // GIR_Coverage, 1941,
6587 /* 16566 */ GIR_EraseRootFromParent_Done,
6588 /* 16567 */ // Label 576: @16567
6589 /* 16567 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(16619), // Rule ID 1942 //
6590 /* 16572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
6591 /* 16575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6592 /* 16579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6593 /* 16583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6594 /* 16587 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6595 /* 16591 */ // MIs[1] Operand 1
6596 /* 16591 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6597 /* 16596 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6598 /* 16600 */ // MIs[0] offset
6599 /* 16600 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6600 /* 16603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6601 /* 16605 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6602 /* 16605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6603 /* 16608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6604 /* 16612 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6605 /* 16614 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6606 /* 16617 */ GIR_RootConstrainSelectedInstOperands,
6607 /* 16618 */ // GIR_Coverage, 1942,
6608 /* 16618 */ GIR_EraseRootFromParent_Done,
6609 /* 16619 */ // Label 577: @16619
6610 /* 16619 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(16671), // Rule ID 2332 //
6611 /* 16624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6612 /* 16627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6613 /* 16631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6614 /* 16635 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6615 /* 16639 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6616 /* 16643 */ // MIs[1] Operand 1
6617 /* 16643 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6618 /* 16648 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6619 /* 16652 */ // MIs[0] dst
6620 /* 16652 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6621 /* 16655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6622 /* 16657 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6623 /* 16657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
6624 /* 16660 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6625 /* 16664 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6626 /* 16666 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6627 /* 16669 */ GIR_RootConstrainSelectedInstOperands,
6628 /* 16670 */ // GIR_Coverage, 2332,
6629 /* 16670 */ GIR_EraseRootFromParent_Done,
6630 /* 16671 */ // Label 578: @16671
6631 /* 16671 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(16723), // Rule ID 2333 //
6632 /* 16676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6633 /* 16679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6634 /* 16683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6635 /* 16687 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6636 /* 16691 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6637 /* 16695 */ // MIs[1] Operand 1
6638 /* 16695 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6639 /* 16700 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6640 /* 16704 */ // MIs[0] dst
6641 /* 16704 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6642 /* 16707 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6643 /* 16709 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6644 /* 16709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
6645 /* 16712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6646 /* 16716 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6647 /* 16718 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6648 /* 16721 */ GIR_RootConstrainSelectedInstOperands,
6649 /* 16722 */ // GIR_Coverage, 2333,
6650 /* 16722 */ GIR_EraseRootFromParent_Done,
6651 /* 16723 */ // Label 579: @16723
6652 /* 16723 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(16785), // Rule ID 92 //
6653 /* 16728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6654 /* 16731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6655 /* 16735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6656 /* 16739 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6657 /* 16743 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6658 /* 16747 */ // MIs[1] Operand 1
6659 /* 16747 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6660 /* 16752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6661 /* 16757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6662 /* 16762 */ // MIs[0] offset
6663 /* 16762 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6664 /* 16765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6665 /* 16767 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6666 /* 16767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6667 /* 16770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6668 /* 16774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6669 /* 16778 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6670 /* 16780 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6671 /* 16783 */ GIR_RootConstrainSelectedInstOperands,
6672 /* 16784 */ // GIR_Coverage, 92,
6673 /* 16784 */ GIR_EraseRootFromParent_Done,
6674 /* 16785 */ // Label 580: @16785
6675 /* 16785 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(16847), // Rule ID 93 //
6676 /* 16790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6677 /* 16793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6678 /* 16797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6679 /* 16801 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6680 /* 16805 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6681 /* 16809 */ // MIs[1] Operand 1
6682 /* 16809 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6683 /* 16814 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6684 /* 16819 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6685 /* 16824 */ // MIs[0] offset
6686 /* 16824 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6687 /* 16827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6688 /* 16829 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6689 /* 16829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6690 /* 16832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6691 /* 16836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6692 /* 16840 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6693 /* 16842 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6694 /* 16845 */ GIR_RootConstrainSelectedInstOperands,
6695 /* 16846 */ // GIR_Coverage, 93,
6696 /* 16846 */ GIR_EraseRootFromParent_Done,
6697 /* 16847 */ // Label 581: @16847
6698 /* 16847 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(16909), // Rule ID 267 //
6699 /* 16852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6700 /* 16855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6701 /* 16859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6702 /* 16863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6703 /* 16867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6704 /* 16871 */ // MIs[1] Operand 1
6705 /* 16871 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6706 /* 16876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6707 /* 16881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6708 /* 16886 */ // MIs[0] offset
6709 /* 16886 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6710 /* 16889 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6711 /* 16891 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6712 /* 16891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6713 /* 16894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6714 /* 16898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6715 /* 16902 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6716 /* 16904 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6717 /* 16907 */ GIR_RootConstrainSelectedInstOperands,
6718 /* 16908 */ // GIR_Coverage, 267,
6719 /* 16908 */ GIR_EraseRootFromParent_Done,
6720 /* 16909 */ // Label 582: @16909
6721 /* 16909 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(16971), // Rule ID 268 //
6722 /* 16914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
6723 /* 16917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6724 /* 16921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6725 /* 16925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6726 /* 16929 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6727 /* 16933 */ // MIs[1] Operand 1
6728 /* 16933 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6729 /* 16938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6730 /* 16943 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6731 /* 16948 */ // MIs[0] offset
6732 /* 16948 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6733 /* 16951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6734 /* 16953 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6735 /* 16953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6736 /* 16956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6737 /* 16960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6738 /* 16964 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6739 /* 16966 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6740 /* 16969 */ GIR_RootConstrainSelectedInstOperands,
6741 /* 16970 */ // GIR_Coverage, 268,
6742 /* 16970 */ GIR_EraseRootFromParent_Done,
6743 /* 16971 */ // Label 583: @16971
6744 /* 16971 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(17033), // Rule ID 1131 //
6745 /* 16976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6746 /* 16979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6747 /* 16983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6748 /* 16987 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6749 /* 16991 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6750 /* 16995 */ // MIs[1] Operand 1
6751 /* 16995 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6752 /* 17000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6753 /* 17005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6754 /* 17010 */ // MIs[0] offset
6755 /* 17010 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6756 /* 17013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6757 /* 17015 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6758 /* 17015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6759 /* 17018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6760 /* 17022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6761 /* 17026 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6762 /* 17028 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6763 /* 17031 */ GIR_RootConstrainSelectedInstOperands,
6764 /* 17032 */ // GIR_Coverage, 1131,
6765 /* 17032 */ GIR_EraseRootFromParent_Done,
6766 /* 17033 */ // Label 584: @17033
6767 /* 17033 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(17095), // Rule ID 1132 //
6768 /* 17038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6769 /* 17041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6770 /* 17045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6771 /* 17049 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6772 /* 17053 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6773 /* 17057 */ // MIs[1] Operand 1
6774 /* 17057 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6775 /* 17062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6776 /* 17067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6777 /* 17072 */ // MIs[0] offset
6778 /* 17072 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6779 /* 17075 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6780 /* 17077 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6781 /* 17077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6782 /* 17080 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6783 /* 17084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6784 /* 17088 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6785 /* 17090 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6786 /* 17093 */ GIR_RootConstrainSelectedInstOperands,
6787 /* 17094 */ // GIR_Coverage, 1132,
6788 /* 17094 */ GIR_EraseRootFromParent_Done,
6789 /* 17095 */ // Label 585: @17095
6790 /* 17095 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(17180), // Rule ID 1427 //
6791 /* 17100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6792 /* 17103 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6793 /* 17107 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6794 /* 17111 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6795 /* 17115 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6796 /* 17119 */ // MIs[1] Operand 1
6797 /* 17119 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6798 /* 17124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6799 /* 17129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6800 /* 17134 */ // MIs[0] dst
6801 /* 17134 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6802 /* 17137 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6803 /* 17139 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6804 /* 17139 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6805 /* 17142 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6806 /* 17146 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6807 /* 17151 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6808 /* 17155 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6809 /* 17159 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6810 /* 17161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6811 /* 17164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6812 /* 17167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6813 /* 17173 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6814 /* 17175 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6815 /* 17178 */ GIR_RootConstrainSelectedInstOperands,
6816 /* 17179 */ // GIR_Coverage, 1427,
6817 /* 17179 */ GIR_EraseRootFromParent_Done,
6818 /* 17180 */ // Label 586: @17180
6819 /* 17180 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(17265), // Rule ID 1428 //
6820 /* 17185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6821 /* 17188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6822 /* 17192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6823 /* 17196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6824 /* 17200 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6825 /* 17204 */ // MIs[1] Operand 1
6826 /* 17204 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6827 /* 17209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6828 /* 17214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6829 /* 17219 */ // MIs[0] dst
6830 /* 17219 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6831 /* 17222 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6832 /* 17224 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6833 /* 17224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6834 /* 17227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6835 /* 17231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6836 /* 17236 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6837 /* 17240 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6838 /* 17244 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6839 /* 17246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6840 /* 17249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6841 /* 17252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6842 /* 17258 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6843 /* 17260 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6844 /* 17263 */ GIR_RootConstrainSelectedInstOperands,
6845 /* 17264 */ // GIR_Coverage, 1428,
6846 /* 17264 */ GIR_EraseRootFromParent_Done,
6847 /* 17265 */ // Label 587: @17265
6848 /* 17265 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(17350), // Rule ID 1433 //
6849 /* 17270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6850 /* 17273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6851 /* 17277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6852 /* 17281 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6853 /* 17285 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6854 /* 17289 */ // MIs[1] Operand 1
6855 /* 17289 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6856 /* 17294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6857 /* 17299 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6858 /* 17304 */ // MIs[0] dst
6859 /* 17304 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6860 /* 17307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6861 /* 17309 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6862 /* 17309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6863 /* 17312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6864 /* 17316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6865 /* 17321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6866 /* 17325 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6867 /* 17329 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6868 /* 17331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6869 /* 17334 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6870 /* 17337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6871 /* 17343 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6872 /* 17345 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6873 /* 17348 */ GIR_RootConstrainSelectedInstOperands,
6874 /* 17349 */ // GIR_Coverage, 1433,
6875 /* 17349 */ GIR_EraseRootFromParent_Done,
6876 /* 17350 */ // Label 588: @17350
6877 /* 17350 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(17435), // Rule ID 1434 //
6878 /* 17355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6879 /* 17358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6880 /* 17362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6881 /* 17366 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6882 /* 17370 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6883 /* 17374 */ // MIs[1] Operand 1
6884 /* 17374 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6885 /* 17379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6886 /* 17384 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6887 /* 17389 */ // MIs[0] dst
6888 /* 17389 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6889 /* 17392 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6890 /* 17394 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6891 /* 17394 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6892 /* 17397 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6893 /* 17401 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6894 /* 17406 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6895 /* 17410 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6896 /* 17414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6897 /* 17416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6898 /* 17419 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6899 /* 17422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6900 /* 17428 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6901 /* 17430 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6902 /* 17433 */ GIR_RootConstrainSelectedInstOperands,
6903 /* 17434 */ // GIR_Coverage, 1434,
6904 /* 17434 */ GIR_EraseRootFromParent_Done,
6905 /* 17435 */ // Label 589: @17435
6906 /* 17435 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(17520), // Rule ID 1652 //
6907 /* 17440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6908 /* 17443 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6909 /* 17447 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6910 /* 17451 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6911 /* 17455 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6912 /* 17459 */ // MIs[1] Operand 1
6913 /* 17459 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6914 /* 17464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6915 /* 17469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6916 /* 17474 */ // MIs[0] dst
6917 /* 17474 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6918 /* 17477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6919 /* 17479 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6920 /* 17479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6921 /* 17482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6922 /* 17486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6923 /* 17491 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6924 /* 17495 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6925 /* 17499 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6926 /* 17501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6927 /* 17504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6928 /* 17507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6929 /* 17513 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6930 /* 17515 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6931 /* 17518 */ GIR_RootConstrainSelectedInstOperands,
6932 /* 17519 */ // GIR_Coverage, 1652,
6933 /* 17519 */ GIR_EraseRootFromParent_Done,
6934 /* 17520 */ // Label 590: @17520
6935 /* 17520 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(17605), // Rule ID 1653 //
6936 /* 17525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6937 /* 17528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6938 /* 17532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6939 /* 17536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6940 /* 17540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6941 /* 17544 */ // MIs[1] Operand 1
6942 /* 17544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6943 /* 17549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6944 /* 17554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6945 /* 17559 */ // MIs[0] dst
6946 /* 17559 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6947 /* 17562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6948 /* 17564 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6949 /* 17564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6950 /* 17567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6951 /* 17571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6952 /* 17576 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6953 /* 17580 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6954 /* 17584 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6955 /* 17586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6956 /* 17589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6957 /* 17592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6958 /* 17598 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6959 /* 17600 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6960 /* 17603 */ GIR_RootConstrainSelectedInstOperands,
6961 /* 17604 */ // GIR_Coverage, 1653,
6962 /* 17604 */ GIR_EraseRootFromParent_Done,
6963 /* 17605 */ // Label 591: @17605
6964 /* 17605 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(17690), // Rule ID 1658 //
6965 /* 17610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6966 /* 17613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6967 /* 17617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6968 /* 17621 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6969 /* 17625 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6970 /* 17629 */ // MIs[1] Operand 1
6971 /* 17629 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6972 /* 17634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6973 /* 17639 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6974 /* 17644 */ // MIs[0] dst
6975 /* 17644 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6976 /* 17647 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6977 /* 17649 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6978 /* 17649 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6979 /* 17652 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6980 /* 17656 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6981 /* 17661 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6982 /* 17665 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6983 /* 17669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6984 /* 17671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6985 /* 17674 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6986 /* 17677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6987 /* 17683 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6988 /* 17685 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6989 /* 17688 */ GIR_RootConstrainSelectedInstOperands,
6990 /* 17689 */ // GIR_Coverage, 1658,
6991 /* 17689 */ GIR_EraseRootFromParent_Done,
6992 /* 17690 */ // Label 592: @17690
6993 /* 17690 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(17775), // Rule ID 1659 //
6994 /* 17695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6995 /* 17698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6996 /* 17702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6997 /* 17706 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6998 /* 17710 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6999 /* 17714 */ // MIs[1] Operand 1
7000 /* 17714 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7001 /* 17719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7002 /* 17724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7003 /* 17729 */ // MIs[0] dst
7004 /* 17729 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7005 /* 17732 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7006 /* 17734 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7007 /* 17734 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7008 /* 17737 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
7009 /* 17741 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7010 /* 17746 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7011 /* 17750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7012 /* 17754 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7013 /* 17756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
7014 /* 17759 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7015 /* 17762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7016 /* 17768 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7017 /* 17770 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7018 /* 17773 */ GIR_RootConstrainSelectedInstOperands,
7019 /* 17774 */ // GIR_Coverage, 1659,
7020 /* 17774 */ GIR_EraseRootFromParent_Done,
7021 /* 17775 */ // Label 593: @17775
7022 /* 17775 */ GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(17837), // Rule ID 1900 //
7023 /* 17780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7024 /* 17783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7025 /* 17787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7026 /* 17791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7027 /* 17795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7028 /* 17799 */ // MIs[1] Operand 1
7029 /* 17799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7030 /* 17804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7031 /* 17809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7032 /* 17814 */ // MIs[0] offset
7033 /* 17814 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7034 /* 17817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7035 /* 17819 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7036 /* 17819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
7037 /* 17822 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7038 /* 17826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7039 /* 17830 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7040 /* 17832 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7041 /* 17835 */ GIR_RootConstrainSelectedInstOperands,
7042 /* 17836 */ // GIR_Coverage, 1900,
7043 /* 17836 */ GIR_EraseRootFromParent_Done,
7044 /* 17837 */ // Label 594: @17837
7045 /* 17837 */ GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(17899), // Rule ID 1901 //
7046 /* 17842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7047 /* 17845 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7048 /* 17849 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7049 /* 17853 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7050 /* 17857 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7051 /* 17861 */ // MIs[1] Operand 1
7052 /* 17861 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7053 /* 17866 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7054 /* 17871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7055 /* 17876 */ // MIs[0] offset
7056 /* 17876 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7057 /* 17879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7058 /* 17881 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7059 /* 17881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
7060 /* 17884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7061 /* 17888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7062 /* 17892 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7063 /* 17894 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7064 /* 17897 */ GIR_RootConstrainSelectedInstOperands,
7065 /* 17898 */ // GIR_Coverage, 1901,
7066 /* 17898 */ GIR_EraseRootFromParent_Done,
7067 /* 17899 */ // Label 595: @17899
7068 /* 17899 */ GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(17961), // Rule ID 1902 //
7069 /* 17904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7070 /* 17907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7071 /* 17911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7072 /* 17915 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7073 /* 17919 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7074 /* 17923 */ // MIs[1] Operand 1
7075 /* 17923 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7076 /* 17928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7077 /* 17933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7078 /* 17938 */ // MIs[0] offset
7079 /* 17938 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7080 /* 17941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7081 /* 17943 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7082 /* 17943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
7083 /* 17946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7084 /* 17950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7085 /* 17954 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7086 /* 17956 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7087 /* 17959 */ GIR_RootConstrainSelectedInstOperands,
7088 /* 17960 */ // GIR_Coverage, 1902,
7089 /* 17960 */ GIR_EraseRootFromParent_Done,
7090 /* 17961 */ // Label 596: @17961
7091 /* 17961 */ GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(18023), // Rule ID 1903 //
7092 /* 17966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7093 /* 17969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7094 /* 17973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7095 /* 17977 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7096 /* 17981 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7097 /* 17985 */ // MIs[1] Operand 1
7098 /* 17985 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7099 /* 17990 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7100 /* 17995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7101 /* 18000 */ // MIs[0] offset
7102 /* 18000 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7103 /* 18003 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7104 /* 18005 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7105 /* 18005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
7106 /* 18008 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7107 /* 18012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7108 /* 18016 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7109 /* 18018 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7110 /* 18021 */ GIR_RootConstrainSelectedInstOperands,
7111 /* 18022 */ // GIR_Coverage, 1903,
7112 /* 18022 */ GIR_EraseRootFromParent_Done,
7113 /* 18023 */ // Label 597: @18023
7114 /* 18023 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(18085), // Rule ID 1904 //
7115 /* 18028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7116 /* 18031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7117 /* 18035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7118 /* 18039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7119 /* 18043 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7120 /* 18047 */ // MIs[1] Operand 1
7121 /* 18047 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
7122 /* 18052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7123 /* 18057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7124 /* 18062 */ // MIs[0] offset
7125 /* 18062 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7126 /* 18065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7127 /* 18067 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7128 /* 18067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
7129 /* 18070 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7130 /* 18074 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7131 /* 18078 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7132 /* 18080 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7133 /* 18083 */ GIR_RootConstrainSelectedInstOperands,
7134 /* 18084 */ // GIR_Coverage, 1904,
7135 /* 18084 */ GIR_EraseRootFromParent_Done,
7136 /* 18085 */ // Label 598: @18085
7137 /* 18085 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(18147), // Rule ID 1905 //
7138 /* 18090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7139 /* 18093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7140 /* 18097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7141 /* 18101 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7142 /* 18105 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7143 /* 18109 */ // MIs[1] Operand 1
7144 /* 18109 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7145 /* 18114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7146 /* 18119 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7147 /* 18124 */ // MIs[0] offset
7148 /* 18124 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7149 /* 18127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7150 /* 18129 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
7151 /* 18129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
7152 /* 18132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7153 /* 18136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7154 /* 18140 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7155 /* 18142 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7156 /* 18145 */ GIR_RootConstrainSelectedInstOperands,
7157 /* 18146 */ // GIR_Coverage, 1905,
7158 /* 18146 */ GIR_EraseRootFromParent_Done,
7159 /* 18147 */ // Label 599: @18147
7160 /* 18147 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(18209), // Rule ID 1906 //
7161 /* 18152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7162 /* 18155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7163 /* 18159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7164 /* 18163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7165 /* 18167 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7166 /* 18171 */ // MIs[1] Operand 1
7167 /* 18171 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
7168 /* 18176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7169 /* 18181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7170 /* 18186 */ // MIs[0] offset
7171 /* 18186 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7172 /* 18189 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7173 /* 18191 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7174 /* 18191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
7175 /* 18194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7176 /* 18198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7177 /* 18202 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7178 /* 18204 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7179 /* 18207 */ GIR_RootConstrainSelectedInstOperands,
7180 /* 18208 */ // GIR_Coverage, 1906,
7181 /* 18208 */ GIR_EraseRootFromParent_Done,
7182 /* 18209 */ // Label 600: @18209
7183 /* 18209 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(18271), // Rule ID 1907 //
7184 /* 18214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7185 /* 18217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7186 /* 18221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7187 /* 18225 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7188 /* 18229 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7189 /* 18233 */ // MIs[1] Operand 1
7190 /* 18233 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7191 /* 18238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7192 /* 18243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7193 /* 18248 */ // MIs[0] offset
7194 /* 18248 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7195 /* 18251 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7196 /* 18253 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
7197 /* 18253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
7198 /* 18256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7199 /* 18260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7200 /* 18264 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7201 /* 18266 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7202 /* 18269 */ GIR_RootConstrainSelectedInstOperands,
7203 /* 18270 */ // GIR_Coverage, 1907,
7204 /* 18270 */ GIR_EraseRootFromParent_Done,
7205 /* 18271 */ // Label 601: @18271
7206 /* 18271 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(18333), // Rule ID 1943 //
7207 /* 18276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7208 /* 18279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7209 /* 18283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7210 /* 18287 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7211 /* 18291 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7212 /* 18295 */ // MIs[1] Operand 1
7213 /* 18295 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7214 /* 18300 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7215 /* 18305 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7216 /* 18310 */ // MIs[0] offset
7217 /* 18310 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7218 /* 18313 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7219 /* 18315 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7220 /* 18315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
7221 /* 18318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7222 /* 18322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7223 /* 18326 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7224 /* 18328 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7225 /* 18331 */ GIR_RootConstrainSelectedInstOperands,
7226 /* 18332 */ // GIR_Coverage, 1943,
7227 /* 18332 */ GIR_EraseRootFromParent_Done,
7228 /* 18333 */ // Label 602: @18333
7229 /* 18333 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(18395), // Rule ID 1944 //
7230 /* 18338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7231 /* 18341 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7232 /* 18345 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7233 /* 18349 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7234 /* 18353 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7235 /* 18357 */ // MIs[1] Operand 1
7236 /* 18357 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7237 /* 18362 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7238 /* 18367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7239 /* 18372 */ // MIs[0] offset
7240 /* 18372 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7241 /* 18375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7242 /* 18377 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7243 /* 18377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
7244 /* 18380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7245 /* 18384 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7246 /* 18388 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7247 /* 18390 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7248 /* 18393 */ GIR_RootConstrainSelectedInstOperands,
7249 /* 18394 */ // GIR_Coverage, 1944,
7250 /* 18394 */ GIR_EraseRootFromParent_Done,
7251 /* 18395 */ // Label 603: @18395
7252 /* 18395 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(18457), // Rule ID 1945 //
7253 /* 18400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7254 /* 18403 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7255 /* 18407 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7256 /* 18411 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7257 /* 18415 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7258 /* 18419 */ // MIs[1] Operand 1
7259 /* 18419 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7260 /* 18424 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7261 /* 18429 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7262 /* 18434 */ // MIs[0] offset
7263 /* 18434 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7264 /* 18437 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7265 /* 18439 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7266 /* 18439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
7267 /* 18442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7268 /* 18446 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7269 /* 18450 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7270 /* 18452 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7271 /* 18455 */ GIR_RootConstrainSelectedInstOperands,
7272 /* 18456 */ // GIR_Coverage, 1945,
7273 /* 18456 */ GIR_EraseRootFromParent_Done,
7274 /* 18457 */ // Label 604: @18457
7275 /* 18457 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(18519), // Rule ID 1946 //
7276 /* 18462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7277 /* 18465 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7278 /* 18469 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7279 /* 18473 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7280 /* 18477 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7281 /* 18481 */ // MIs[1] Operand 1
7282 /* 18481 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7283 /* 18486 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7284 /* 18491 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7285 /* 18496 */ // MIs[0] offset
7286 /* 18496 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7287 /* 18499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7288 /* 18501 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7289 /* 18501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
7290 /* 18504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7291 /* 18508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7292 /* 18512 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7293 /* 18514 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7294 /* 18517 */ GIR_RootConstrainSelectedInstOperands,
7295 /* 18518 */ // GIR_Coverage, 1946,
7296 /* 18518 */ GIR_EraseRootFromParent_Done,
7297 /* 18519 */ // Label 605: @18519
7298 /* 18519 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(18581), // Rule ID 1947 //
7299 /* 18524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7300 /* 18527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7301 /* 18531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7302 /* 18535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7303 /* 18539 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7304 /* 18543 */ // MIs[1] Operand 1
7305 /* 18543 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
7306 /* 18548 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7307 /* 18553 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7308 /* 18558 */ // MIs[0] offset
7309 /* 18558 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7310 /* 18561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7311 /* 18563 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7312 /* 18563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
7313 /* 18566 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7314 /* 18570 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7315 /* 18574 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7316 /* 18576 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7317 /* 18579 */ GIR_RootConstrainSelectedInstOperands,
7318 /* 18580 */ // GIR_Coverage, 1947,
7319 /* 18580 */ GIR_EraseRootFromParent_Done,
7320 /* 18581 */ // Label 606: @18581
7321 /* 18581 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(18643), // Rule ID 1948 //
7322 /* 18586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7323 /* 18589 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7324 /* 18593 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7325 /* 18597 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7326 /* 18601 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7327 /* 18605 */ // MIs[1] Operand 1
7328 /* 18605 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7329 /* 18610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7330 /* 18615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7331 /* 18620 */ // MIs[0] offset
7332 /* 18620 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7333 /* 18623 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7334 /* 18625 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
7335 /* 18625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
7336 /* 18628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7337 /* 18632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7338 /* 18636 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7339 /* 18638 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7340 /* 18641 */ GIR_RootConstrainSelectedInstOperands,
7341 /* 18642 */ // GIR_Coverage, 1948,
7342 /* 18642 */ GIR_EraseRootFromParent_Done,
7343 /* 18643 */ // Label 607: @18643
7344 /* 18643 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(18705), // Rule ID 1949 //
7345 /* 18648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7346 /* 18651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7347 /* 18655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7348 /* 18659 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7349 /* 18663 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7350 /* 18667 */ // MIs[1] Operand 1
7351 /* 18667 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
7352 /* 18672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7353 /* 18677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7354 /* 18682 */ // MIs[0] offset
7355 /* 18682 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7356 /* 18685 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7357 /* 18687 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7358 /* 18687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
7359 /* 18690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7360 /* 18694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7361 /* 18698 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7362 /* 18700 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7363 /* 18703 */ GIR_RootConstrainSelectedInstOperands,
7364 /* 18704 */ // GIR_Coverage, 1949,
7365 /* 18704 */ GIR_EraseRootFromParent_Done,
7366 /* 18705 */ // Label 608: @18705
7367 /* 18705 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(18767), // Rule ID 1950 //
7368 /* 18710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
7369 /* 18713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7370 /* 18717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7371 /* 18721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
7372 /* 18725 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
7373 /* 18729 */ // MIs[1] Operand 1
7374 /* 18729 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7375 /* 18734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7376 /* 18739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7377 /* 18744 */ // MIs[0] offset
7378 /* 18744 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7379 /* 18747 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7380 /* 18749 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
7381 /* 18749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
7382 /* 18752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
7383 /* 18756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
7384 /* 18760 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
7385 /* 18762 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7386 /* 18765 */ GIR_RootConstrainSelectedInstOperands,
7387 /* 18766 */ // GIR_Coverage, 1950,
7388 /* 18766 */ GIR_EraseRootFromParent_Done,
7389 /* 18767 */ // Label 609: @18767
7390 /* 18767 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(18826), // Rule ID 1980 //
7391 /* 18772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7392 /* 18775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7393 /* 18779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7394 /* 18783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7395 /* 18787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7396 /* 18791 */ // MIs[1] Operand 1
7397 /* 18791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
7398 /* 18796 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7399 /* 18801 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7400 /* 18806 */ // MIs[0] imm16
7401 /* 18806 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7402 /* 18809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7403 /* 18811 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7404 /* 18811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
7405 /* 18814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7406 /* 18818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7407 /* 18822 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7408 /* 18824 */ GIR_RootConstrainSelectedInstOperands,
7409 /* 18825 */ // GIR_Coverage, 1980,
7410 /* 18825 */ GIR_EraseRootFromParent_Done,
7411 /* 18826 */ // Label 610: @18826
7412 /* 18826 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(18885), // Rule ID 1983 //
7413 /* 18831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7414 /* 18834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7415 /* 18838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7416 /* 18842 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7417 /* 18846 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7418 /* 18850 */ // MIs[1] Operand 1
7419 /* 18850 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
7420 /* 18855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7421 /* 18860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7422 /* 18865 */ // MIs[0] imm16
7423 /* 18865 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7424 /* 18868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7425 /* 18870 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
7426 /* 18870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
7427 /* 18873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7428 /* 18877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7429 /* 18881 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7430 /* 18883 */ GIR_RootConstrainSelectedInstOperands,
7431 /* 18884 */ // GIR_Coverage, 1983,
7432 /* 18884 */ GIR_EraseRootFromParent_Done,
7433 /* 18885 */ // Label 611: @18885
7434 /* 18885 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(18944), // Rule ID 1984 //
7435 /* 18890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7436 /* 18893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7437 /* 18897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7438 /* 18901 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7439 /* 18905 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7440 /* 18909 */ // MIs[1] Operand 1
7441 /* 18909 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7442 /* 18914 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7443 /* 18919 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7444 /* 18924 */ // MIs[0] imm16
7445 /* 18924 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7446 /* 18927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7447 /* 18929 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7448 /* 18929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7449 /* 18932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7450 /* 18936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7451 /* 18940 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7452 /* 18942 */ GIR_RootConstrainSelectedInstOperands,
7453 /* 18943 */ // GIR_Coverage, 1984,
7454 /* 18943 */ GIR_EraseRootFromParent_Done,
7455 /* 18944 */ // Label 612: @18944
7456 /* 18944 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(19003), // Rule ID 1986 //
7457 /* 18949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7458 /* 18952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7459 /* 18956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7460 /* 18960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7461 /* 18964 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7462 /* 18968 */ // MIs[1] Operand 1
7463 /* 18968 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
7464 /* 18973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7465 /* 18978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7466 /* 18983 */ // MIs[0] imm16
7467 /* 18983 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7468 /* 18986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7469 /* 18988 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7470 /* 18988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
7471 /* 18991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7472 /* 18995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7473 /* 18999 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7474 /* 19001 */ GIR_RootConstrainSelectedInstOperands,
7475 /* 19002 */ // GIR_Coverage, 1986,
7476 /* 19002 */ GIR_EraseRootFromParent_Done,
7477 /* 19003 */ // Label 613: @19003
7478 /* 19003 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(19062), // Rule ID 1988 //
7479 /* 19008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7480 /* 19011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7481 /* 19015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7482 /* 19019 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7483 /* 19023 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7484 /* 19027 */ // MIs[1] Operand 1
7485 /* 19027 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7486 /* 19032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7487 /* 19037 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7488 /* 19042 */ // MIs[0] imm16
7489 /* 19042 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7490 /* 19045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7491 /* 19047 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
7492 /* 19047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
7493 /* 19050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7494 /* 19054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7495 /* 19058 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7496 /* 19060 */ GIR_RootConstrainSelectedInstOperands,
7497 /* 19061 */ // GIR_Coverage, 1988,
7498 /* 19061 */ GIR_EraseRootFromParent_Done,
7499 /* 19062 */ // Label 614: @19062
7500 /* 19062 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(19121), // Rule ID 1989 //
7501 /* 19067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7502 /* 19070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7503 /* 19074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7504 /* 19078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7505 /* 19082 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7506 /* 19086 */ // MIs[1] Operand 1
7507 /* 19086 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
7508 /* 19091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7509 /* 19096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7510 /* 19101 */ // MIs[0] imm16
7511 /* 19101 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7512 /* 19104 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7513 /* 19106 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
7514 /* 19106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
7515 /* 19109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7516 /* 19113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7517 /* 19117 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7518 /* 19119 */ GIR_RootConstrainSelectedInstOperands,
7519 /* 19120 */ // GIR_Coverage, 1989,
7520 /* 19120 */ GIR_EraseRootFromParent_Done,
7521 /* 19121 */ // Label 615: @19121
7522 /* 19121 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(19206), // Rule ID 2323 //
7523 /* 19126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7524 /* 19129 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7525 /* 19133 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7526 /* 19137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7527 /* 19141 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7528 /* 19145 */ // MIs[1] Operand 1
7529 /* 19145 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7530 /* 19150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7531 /* 19155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7532 /* 19160 */ // MIs[0] dst
7533 /* 19160 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7534 /* 19163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7535 /* 19165 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7536 /* 19165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7537 /* 19168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7538 /* 19172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7539 /* 19177 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7540 /* 19181 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7541 /* 19185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7542 /* 19187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7543 /* 19190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7544 /* 19193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7545 /* 19199 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7546 /* 19201 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7547 /* 19204 */ GIR_RootConstrainSelectedInstOperands,
7548 /* 19205 */ // GIR_Coverage, 2323,
7549 /* 19205 */ GIR_EraseRootFromParent_Done,
7550 /* 19206 */ // Label 616: @19206
7551 /* 19206 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19291), // Rule ID 2324 //
7552 /* 19211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7553 /* 19214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7554 /* 19218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7555 /* 19222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7556 /* 19226 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7557 /* 19230 */ // MIs[1] Operand 1
7558 /* 19230 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7559 /* 19235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7560 /* 19240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7561 /* 19245 */ // MIs[0] dst
7562 /* 19245 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7563 /* 19248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7564 /* 19250 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7565 /* 19250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7566 /* 19253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7567 /* 19257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7568 /* 19262 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7569 /* 19266 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7570 /* 19270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7571 /* 19272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7572 /* 19275 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7573 /* 19278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7574 /* 19284 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7575 /* 19286 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7576 /* 19289 */ GIR_RootConstrainSelectedInstOperands,
7577 /* 19290 */ // GIR_Coverage, 2324,
7578 /* 19290 */ GIR_EraseRootFromParent_Done,
7579 /* 19291 */ // Label 617: @19291
7580 /* 19291 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19376), // Rule ID 2329 //
7581 /* 19296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7582 /* 19299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7583 /* 19303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7584 /* 19307 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7585 /* 19311 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7586 /* 19315 */ // MIs[1] Operand 1
7587 /* 19315 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7588 /* 19320 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7589 /* 19325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7590 /* 19330 */ // MIs[0] dst
7591 /* 19330 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7592 /* 19333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7593 /* 19335 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7594 /* 19335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7595 /* 19338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7596 /* 19342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7597 /* 19347 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7598 /* 19351 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7599 /* 19355 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7600 /* 19357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7601 /* 19360 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7602 /* 19363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7603 /* 19369 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7604 /* 19371 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7605 /* 19374 */ GIR_RootConstrainSelectedInstOperands,
7606 /* 19375 */ // GIR_Coverage, 2329,
7607 /* 19375 */ GIR_EraseRootFromParent_Done,
7608 /* 19376 */ // Label 618: @19376
7609 /* 19376 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19461), // Rule ID 2330 //
7610 /* 19381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7611 /* 19384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7612 /* 19388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7613 /* 19392 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7614 /* 19396 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7615 /* 19400 */ // MIs[1] Operand 1
7616 /* 19400 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7617 /* 19405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7618 /* 19410 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7619 /* 19415 */ // MIs[0] dst
7620 /* 19415 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7621 /* 19418 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7622 /* 19420 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7623 /* 19420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7624 /* 19423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7625 /* 19427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7626 /* 19432 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7627 /* 19436 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7628 /* 19440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7629 /* 19442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7630 /* 19445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7631 /* 19448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7632 /* 19454 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7633 /* 19456 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7634 /* 19459 */ GIR_RootConstrainSelectedInstOperands,
7635 /* 19460 */ // GIR_Coverage, 2330,
7636 /* 19460 */ GIR_EraseRootFromParent_Done,
7637 /* 19461 */ // Label 619: @19461
7638 /* 19461 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19540), // Rule ID 2475 //
7639 /* 19466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7640 /* 19469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7641 /* 19473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7642 /* 19477 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7643 /* 19481 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7644 /* 19485 */ // MIs[1] Operand 1
7645 /* 19485 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7646 /* 19490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7647 /* 19495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7648 /* 19500 */ // MIs[0] dst
7649 /* 19500 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7650 /* 19503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7651 /* 19505 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7652 /* 19505 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7653 /* 19508 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7654 /* 19512 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7655 /* 19517 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7656 /* 19521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7657 /* 19525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7658 /* 19527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7659 /* 19530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7660 /* 19533 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7661 /* 19535 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7662 /* 19538 */ GIR_RootConstrainSelectedInstOperands,
7663 /* 19539 */ // GIR_Coverage, 2475,
7664 /* 19539 */ GIR_EraseRootFromParent_Done,
7665 /* 19540 */ // Label 620: @19540
7666 /* 19540 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19619), // Rule ID 2476 //
7667 /* 19545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7668 /* 19548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7669 /* 19552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7670 /* 19556 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7671 /* 19560 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7672 /* 19564 */ // MIs[1] Operand 1
7673 /* 19564 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7674 /* 19569 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7675 /* 19574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7676 /* 19579 */ // MIs[0] dst
7677 /* 19579 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7678 /* 19582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7679 /* 19584 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7680 /* 19584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7681 /* 19587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7682 /* 19591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7683 /* 19596 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7684 /* 19600 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7685 /* 19604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7686 /* 19606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7687 /* 19609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7688 /* 19612 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7689 /* 19614 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7690 /* 19617 */ GIR_RootConstrainSelectedInstOperands,
7691 /* 19618 */ // GIR_Coverage, 2476,
7692 /* 19618 */ GIR_EraseRootFromParent_Done,
7693 /* 19619 */ // Label 621: @19619
7694 /* 19619 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19698), // Rule ID 2481 //
7695 /* 19624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7696 /* 19627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7697 /* 19631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7698 /* 19635 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7699 /* 19639 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7700 /* 19643 */ // MIs[1] Operand 1
7701 /* 19643 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7702 /* 19648 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7703 /* 19653 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7704 /* 19658 */ // MIs[0] dst
7705 /* 19658 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7706 /* 19661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7707 /* 19663 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7708 /* 19663 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7709 /* 19666 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7710 /* 19670 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7711 /* 19675 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7712 /* 19679 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7713 /* 19683 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7714 /* 19685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7715 /* 19688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7716 /* 19691 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7717 /* 19693 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7718 /* 19696 */ GIR_RootConstrainSelectedInstOperands,
7719 /* 19697 */ // GIR_Coverage, 2481,
7720 /* 19697 */ GIR_EraseRootFromParent_Done,
7721 /* 19698 */ // Label 622: @19698
7722 /* 19698 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19777), // Rule ID 2482 //
7723 /* 19703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7724 /* 19706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7725 /* 19710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7726 /* 19714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7727 /* 19718 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7728 /* 19722 */ // MIs[1] Operand 1
7729 /* 19722 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7730 /* 19727 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7731 /* 19732 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7732 /* 19737 */ // MIs[0] dst
7733 /* 19737 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7734 /* 19740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7735 /* 19742 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7736 /* 19742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7737 /* 19745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7738 /* 19749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7739 /* 19754 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7740 /* 19758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7741 /* 19762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7742 /* 19764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7743 /* 19767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7744 /* 19770 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7745 /* 19772 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7746 /* 19775 */ GIR_RootConstrainSelectedInstOperands,
7747 /* 19776 */ // GIR_Coverage, 2482,
7748 /* 19776 */ GIR_EraseRootFromParent_Done,
7749 /* 19777 */ // Label 623: @19777
7750 /* 19777 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19810), // Rule ID 1435 //
7751 /* 19782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
7752 /* 19785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7753 /* 19789 */ // MIs[0] dst
7754 /* 19789 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7755 /* 19792 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7756 /* 19792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
7757 /* 19795 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7758 /* 19797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7759 /* 19803 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7760 /* 19805 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7761 /* 19808 */ GIR_RootConstrainSelectedInstOperands,
7762 /* 19809 */ // GIR_Coverage, 1435,
7763 /* 19809 */ GIR_EraseRootFromParent_Done,
7764 /* 19810 */ // Label 624: @19810
7765 /* 19810 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19832), // Rule ID 1992 //
7766 /* 19815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
7767 /* 19818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7768 /* 19822 */ // MIs[0] targ16
7769 /* 19822 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7770 /* 19825 */ // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
7771 /* 19825 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
7772 /* 19830 */ GIR_RootConstrainSelectedInstOperands,
7773 /* 19831 */ // GIR_Coverage, 1992,
7774 /* 19831 */ GIR_Done,
7775 /* 19832 */ // Label 625: @19832
7776 /* 19832 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19865), // Rule ID 2331 //
7777 /* 19837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
7778 /* 19840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7779 /* 19844 */ // MIs[0] dst
7780 /* 19844 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7781 /* 19847 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7782 /* 19847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
7783 /* 19850 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7784 /* 19852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7785 /* 19858 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7786 /* 19860 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7787 /* 19863 */ GIR_RootConstrainSelectedInstOperands,
7788 /* 19864 */ // GIR_Coverage, 2331,
7789 /* 19864 */ GIR_EraseRootFromParent_Done,
7790 /* 19865 */ // Label 626: @19865
7791 /* 19865 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19893), // Rule ID 2483 //
7792 /* 19870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
7793 /* 19873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7794 /* 19877 */ // MIs[0] dst
7795 /* 19877 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7796 /* 19880 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
7797 /* 19880 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
7798 /* 19885 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
7799 /* 19891 */ GIR_RootConstrainSelectedInstOperands,
7800 /* 19892 */ // GIR_Coverage, 2483,
7801 /* 19892 */ GIR_Done,
7802 /* 19893 */ // Label 627: @19893
7803 /* 19893 */ GIM_Reject,
7804 /* 19894 */ // Label 526: @19894
7805 /* 19894 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19927), // Rule ID 1660 //
7806 /* 19899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
7807 /* 19902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7808 /* 19906 */ // MIs[0] dst
7809 /* 19906 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7810 /* 19909 */ // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
7811 /* 19909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
7812 /* 19912 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7813 /* 19914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7814 /* 19920 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7815 /* 19922 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7816 /* 19925 */ GIR_RootConstrainSelectedInstOperands,
7817 /* 19926 */ // GIR_Coverage, 1660,
7818 /* 19926 */ GIR_EraseRootFromParent_Done,
7819 /* 19927 */ // Label 628: @19927
7820 /* 19927 */ GIM_Reject,
7821 /* 19928 */ // Label 527: @19928
7822 /* 19928 */ GIM_Reject,
7823 /* 19929 */ // Label 29: @19929
7824 /* 19929 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(21926),
7825 /* 19934 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7826 /* 19937 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19984), // Rule ID 452 //
7827 /* 19942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7828 /* 19945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7829 /* 19950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7830 /* 19953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7831 /* 19956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7832 /* 19960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7833 /* 19964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7834 /* 19968 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7835 /* 19972 */ // MIs[1] Operand 1
7836 /* 19972 */ // No operand predicates
7837 /* 19972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7838 /* 19974 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7839 /* 19974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
7840 /* 19977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7841 /* 19979 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7842 /* 19982 */ GIR_RootConstrainSelectedInstOperands,
7843 /* 19983 */ // GIR_Coverage, 452,
7844 /* 19983 */ GIR_EraseRootFromParent_Done,
7845 /* 19984 */ // Label 630: @19984
7846 /* 19984 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(20031), // Rule ID 453 //
7847 /* 19989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7848 /* 19992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7849 /* 19997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7850 /* 20000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7851 /* 20003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7852 /* 20007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7853 /* 20011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7854 /* 20015 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7855 /* 20019 */ // MIs[1] Operand 1
7856 /* 20019 */ // No operand predicates
7857 /* 20019 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7858 /* 20021 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7859 /* 20021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
7860 /* 20024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7861 /* 20026 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7862 /* 20029 */ GIR_RootConstrainSelectedInstOperands,
7863 /* 20030 */ // GIR_Coverage, 453,
7864 /* 20030 */ GIR_EraseRootFromParent_Done,
7865 /* 20031 */ // Label 631: @20031
7866 /* 20031 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(20078), // Rule ID 1311 //
7867 /* 20036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7868 /* 20039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7869 /* 20044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7870 /* 20047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7871 /* 20050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7872 /* 20054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7873 /* 20058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7874 /* 20062 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7875 /* 20066 */ // MIs[1] Operand 1
7876 /* 20066 */ // No operand predicates
7877 /* 20066 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7878 /* 20068 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7879 /* 20068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
7880 /* 20071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7881 /* 20073 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7882 /* 20076 */ GIR_RootConstrainSelectedInstOperands,
7883 /* 20077 */ // GIR_Coverage, 1311,
7884 /* 20077 */ GIR_EraseRootFromParent_Done,
7885 /* 20078 */ // Label 632: @20078
7886 /* 20078 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(20125), // Rule ID 1312 //
7887 /* 20083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7888 /* 20086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7889 /* 20091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7890 /* 20094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7891 /* 20097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7892 /* 20101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7893 /* 20105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7894 /* 20109 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7895 /* 20113 */ // MIs[1] Operand 1
7896 /* 20113 */ // No operand predicates
7897 /* 20113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7898 /* 20115 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7899 /* 20115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
7900 /* 20118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7901 /* 20120 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7902 /* 20123 */ GIR_RootConstrainSelectedInstOperands,
7903 /* 20124 */ // GIR_Coverage, 1312,
7904 /* 20124 */ GIR_EraseRootFromParent_Done,
7905 /* 20125 */ // Label 633: @20125
7906 /* 20125 */ GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(20161), // Rule ID 386 //
7907 /* 20130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7908 /* 20133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7909 /* 20138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7910 /* 20141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7911 /* 20144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7912 /* 20148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7913 /* 20152 */ // (intrinsic_wo_chain:{ *:[i32] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7914 /* 20152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
7915 /* 20155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7916 /* 20157 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7917 /* 20159 */ GIR_RootConstrainSelectedInstOperands,
7918 /* 20160 */ // GIR_Coverage, 386,
7919 /* 20160 */ GIR_EraseRootFromParent_Done,
7920 /* 20161 */ // Label 634: @20161
7921 /* 20161 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(20197), // Rule ID 393 //
7922 /* 20166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7923 /* 20169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7924 /* 20174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7925 /* 20177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7926 /* 20180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7927 /* 20184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7928 /* 20188 */ // (intrinsic_wo_chain:{ *:[i32] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7929 /* 20188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7930 /* 20191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7931 /* 20193 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7932 /* 20195 */ GIR_RootConstrainSelectedInstOperands,
7933 /* 20196 */ // GIR_Coverage, 393,
7934 /* 20196 */ GIR_EraseRootFromParent_Done,
7935 /* 20197 */ // Label 635: @20197
7936 /* 20197 */ GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(20233), // Rule ID 394 //
7937 /* 20202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7938 /* 20205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7939 /* 20210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7940 /* 20213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7941 /* 20216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7942 /* 20220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7943 /* 20224 */ // (intrinsic_wo_chain:{ *:[i32] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7944 /* 20224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7945 /* 20227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7946 /* 20229 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7947 /* 20231 */ GIR_RootConstrainSelectedInstOperands,
7948 /* 20232 */ // GIR_Coverage, 394,
7949 /* 20232 */ GIR_EraseRootFromParent_Done,
7950 /* 20233 */ // Label 636: @20233
7951 /* 20233 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(20269), // Rule ID 395 //
7952 /* 20238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7953 /* 20241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7954 /* 20246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7955 /* 20249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7956 /* 20252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7957 /* 20256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7958 /* 20260 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7959 /* 20260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7960 /* 20263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7961 /* 20265 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7962 /* 20267 */ GIR_RootConstrainSelectedInstOperands,
7963 /* 20268 */ // GIR_Coverage, 395,
7964 /* 20268 */ GIR_EraseRootFromParent_Done,
7965 /* 20269 */ // Label 637: @20269
7966 /* 20269 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(20305), // Rule ID 396 //
7967 /* 20274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7968 /* 20277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7969 /* 20282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7970 /* 20285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7971 /* 20288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7972 /* 20292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7973 /* 20296 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7974 /* 20296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7975 /* 20299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7976 /* 20301 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7977 /* 20303 */ GIR_RootConstrainSelectedInstOperands,
7978 /* 20304 */ // GIR_Coverage, 396,
7979 /* 20304 */ GIR_EraseRootFromParent_Done,
7980 /* 20305 */ // Label 638: @20305
7981 /* 20305 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(20341), // Rule ID 397 //
7982 /* 20310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7983 /* 20313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7984 /* 20318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7985 /* 20321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7986 /* 20324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7987 /* 20328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7988 /* 20332 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7989 /* 20332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7990 /* 20335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7991 /* 20337 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7992 /* 20339 */ GIR_RootConstrainSelectedInstOperands,
7993 /* 20340 */ // GIR_Coverage, 397,
7994 /* 20340 */ GIR_EraseRootFromParent_Done,
7995 /* 20341 */ // Label 639: @20341
7996 /* 20341 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(20377), // Rule ID 398 //
7997 /* 20346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7998 /* 20349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7999 /* 20354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8000 /* 20357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8001 /* 20360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8002 /* 20364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8003 /* 20368 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8004 /* 20368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
8005 /* 20371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8006 /* 20373 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8007 /* 20375 */ GIR_RootConstrainSelectedInstOperands,
8008 /* 20376 */ // GIR_Coverage, 398,
8009 /* 20376 */ GIR_EraseRootFromParent_Done,
8010 /* 20377 */ // Label 640: @20377
8011 /* 20377 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(20413), // Rule ID 399 //
8012 /* 20382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8013 /* 20385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
8014 /* 20390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8015 /* 20393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8016 /* 20396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8017 /* 20400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8018 /* 20404 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8019 /* 20404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
8020 /* 20407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8021 /* 20409 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8022 /* 20411 */ GIR_RootConstrainSelectedInstOperands,
8023 /* 20412 */ // GIR_Coverage, 399,
8024 /* 20412 */ GIR_EraseRootFromParent_Done,
8025 /* 20413 */ // Label 641: @20413
8026 /* 20413 */ GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(20449), // Rule ID 400 //
8027 /* 20418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8028 /* 20421 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
8029 /* 20426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8030 /* 20429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8031 /* 20432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8032 /* 20436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8033 /* 20440 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8034 /* 20440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
8035 /* 20443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8036 /* 20445 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8037 /* 20447 */ GIR_RootConstrainSelectedInstOperands,
8038 /* 20448 */ // GIR_Coverage, 400,
8039 /* 20448 */ GIR_EraseRootFromParent_Done,
8040 /* 20449 */ // Label 642: @20449
8041 /* 20449 */ GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(20485), // Rule ID 401 //
8042 /* 20454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8043 /* 20457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
8044 /* 20462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8045 /* 20465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8046 /* 20468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8047 /* 20472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8048 /* 20476 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8049 /* 20476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
8050 /* 20479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8051 /* 20481 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8052 /* 20483 */ GIR_RootConstrainSelectedInstOperands,
8053 /* 20484 */ // GIR_Coverage, 401,
8054 /* 20484 */ GIR_EraseRootFromParent_Done,
8055 /* 20485 */ // Label 643: @20485
8056 /* 20485 */ GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(20521), // Rule ID 402 //
8057 /* 20490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8058 /* 20493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
8059 /* 20498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8060 /* 20501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8061 /* 20504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8062 /* 20508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8063 /* 20512 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
8064 /* 20512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
8065 /* 20515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8066 /* 20517 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8067 /* 20519 */ GIR_RootConstrainSelectedInstOperands,
8068 /* 20520 */ // GIR_Coverage, 402,
8069 /* 20520 */ GIR_EraseRootFromParent_Done,
8070 /* 20521 */ // Label 644: @20521
8071 /* 20521 */ GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20557), // Rule ID 450 //
8072 /* 20526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8073 /* 20529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8074 /* 20534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8075 /* 20537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8076 /* 20540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8077 /* 20544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8078 /* 20548 */ // (intrinsic_wo_chain:{ *:[i32] } 8055:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
8079 /* 20548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
8080 /* 20551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8081 /* 20553 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8082 /* 20555 */ GIR_RootConstrainSelectedInstOperands,
8083 /* 20556 */ // GIR_Coverage, 450,
8084 /* 20556 */ GIR_EraseRootFromParent_Done,
8085 /* 20557 */ // Label 645: @20557
8086 /* 20557 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20593), // Rule ID 454 //
8087 /* 20562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8088 /* 20565 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8089 /* 20570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8090 /* 20573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8091 /* 20576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8092 /* 20580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8093 /* 20584 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
8094 /* 20584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
8095 /* 20587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8096 /* 20589 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8097 /* 20591 */ GIR_RootConstrainSelectedInstOperands,
8098 /* 20592 */ // GIR_Coverage, 454,
8099 /* 20592 */ GIR_EraseRootFromParent_Done,
8100 /* 20593 */ // Label 646: @20593
8101 /* 20593 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(20629), // Rule ID 455 //
8102 /* 20598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8103 /* 20601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8104 /* 20606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8105 /* 20609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8106 /* 20612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8107 /* 20616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8108 /* 20620 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
8109 /* 20620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
8110 /* 20623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8111 /* 20625 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8112 /* 20627 */ GIR_RootConstrainSelectedInstOperands,
8113 /* 20628 */ // GIR_Coverage, 455,
8114 /* 20628 */ GIR_EraseRootFromParent_Done,
8115 /* 20629 */ // Label 647: @20629
8116 /* 20629 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20665), // Rule ID 704 //
8117 /* 20634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8118 /* 20637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
8119 /* 20642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8120 /* 20645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8121 /* 20648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8122 /* 20652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8123 /* 20656 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8207:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8124 /* 20656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
8125 /* 20659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8126 /* 20661 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8127 /* 20663 */ GIR_RootConstrainSelectedInstOperands,
8128 /* 20664 */ // GIR_Coverage, 704,
8129 /* 20664 */ GIR_EraseRootFromParent_Done,
8130 /* 20665 */ // Label 648: @20665
8131 /* 20665 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20701), // Rule ID 705 //
8132 /* 20670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8133 /* 20673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
8134 /* 20678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8135 /* 20681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8136 /* 20684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8137 /* 20688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8138 /* 20692 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8206:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8139 /* 20692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
8140 /* 20695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8141 /* 20697 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8142 /* 20699 */ GIR_RootConstrainSelectedInstOperands,
8143 /* 20700 */ // GIR_Coverage, 705,
8144 /* 20700 */ GIR_EraseRootFromParent_Done,
8145 /* 20701 */ // Label 649: @20701
8146 /* 20701 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20737), // Rule ID 728 //
8147 /* 20706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8148 /* 20709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
8149 /* 20714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8150 /* 20717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8151 /* 20720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8152 /* 20724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8153 /* 20728 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8233:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
8154 /* 20728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
8155 /* 20731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8156 /* 20733 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8157 /* 20735 */ GIR_RootConstrainSelectedInstOperands,
8158 /* 20736 */ // GIR_Coverage, 728,
8159 /* 20736 */ GIR_EraseRootFromParent_Done,
8160 /* 20737 */ // Label 650: @20737
8161 /* 20737 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20773), // Rule ID 729 //
8162 /* 20742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8163 /* 20745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
8164 /* 20750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8165 /* 20753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8166 /* 20756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8167 /* 20760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8168 /* 20764 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8232:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8169 /* 20764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
8170 /* 20767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8171 /* 20769 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8172 /* 20771 */ GIR_RootConstrainSelectedInstOperands,
8173 /* 20772 */ // GIR_Coverage, 729,
8174 /* 20772 */ GIR_EraseRootFromParent_Done,
8175 /* 20773 */ // Label 651: @20773
8176 /* 20773 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20809), // Rule ID 730 //
8177 /* 20778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8178 /* 20781 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
8179 /* 20786 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8180 /* 20789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8181 /* 20792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8182 /* 20796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8183 /* 20800 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8235:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
8184 /* 20800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
8185 /* 20803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8186 /* 20805 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8187 /* 20807 */ GIR_RootConstrainSelectedInstOperands,
8188 /* 20808 */ // GIR_Coverage, 730,
8189 /* 20808 */ GIR_EraseRootFromParent_Done,
8190 /* 20809 */ // Label 652: @20809
8191 /* 20809 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20845), // Rule ID 731 //
8192 /* 20814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8193 /* 20817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
8194 /* 20822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8195 /* 20825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8196 /* 20828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8197 /* 20832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8198 /* 20836 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8234:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8199 /* 20836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
8200 /* 20839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8201 /* 20841 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8202 /* 20843 */ GIR_RootConstrainSelectedInstOperands,
8203 /* 20844 */ // GIR_Coverage, 731,
8204 /* 20844 */ GIR_EraseRootFromParent_Done,
8205 /* 20845 */ // Label 653: @20845
8206 /* 20845 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20881), // Rule ID 736 //
8207 /* 20850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8208 /* 20853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
8209 /* 20858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8210 /* 20861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8211 /* 20864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8212 /* 20868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8213 /* 20872 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8241:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8214 /* 20872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
8215 /* 20875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8216 /* 20877 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8217 /* 20879 */ GIR_RootConstrainSelectedInstOperands,
8218 /* 20880 */ // GIR_Coverage, 736,
8219 /* 20880 */ GIR_EraseRootFromParent_Done,
8220 /* 20881 */ // Label 654: @20881
8221 /* 20881 */ GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20917), // Rule ID 737 //
8222 /* 20886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8223 /* 20889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
8224 /* 20894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8225 /* 20897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8226 /* 20900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8227 /* 20904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8228 /* 20908 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8229 /* 20908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
8230 /* 20911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8231 /* 20913 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8232 /* 20915 */ GIR_RootConstrainSelectedInstOperands,
8233 /* 20916 */ // GIR_Coverage, 737,
8234 /* 20916 */ GIR_EraseRootFromParent_Done,
8235 /* 20917 */ // Label 655: @20917
8236 /* 20917 */ GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20953), // Rule ID 738 //
8237 /* 20922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8238 /* 20925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
8239 /* 20930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8240 /* 20933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8241 /* 20936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8242 /* 20940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8243 /* 20944 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8243:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8244 /* 20944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
8245 /* 20947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8246 /* 20949 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8247 /* 20951 */ GIR_RootConstrainSelectedInstOperands,
8248 /* 20952 */ // GIR_Coverage, 738,
8249 /* 20952 */ GIR_EraseRootFromParent_Done,
8250 /* 20953 */ // Label 656: @20953
8251 /* 20953 */ GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20989), // Rule ID 739 //
8252 /* 20958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8253 /* 20961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
8254 /* 20966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8255 /* 20969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8256 /* 20972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8257 /* 20976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8258 /* 20980 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8242:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8259 /* 20980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
8260 /* 20983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8261 /* 20985 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8262 /* 20987 */ GIR_RootConstrainSelectedInstOperands,
8263 /* 20988 */ // GIR_Coverage, 739,
8264 /* 20988 */ GIR_EraseRootFromParent_Done,
8265 /* 20989 */ // Label 657: @20989
8266 /* 20989 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(21025), // Rule ID 764 //
8267 /* 20994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8268 /* 20997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
8269 /* 21002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8270 /* 21005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8271 /* 21008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8272 /* 21012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8273 /* 21016 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8265:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8274 /* 21016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
8275 /* 21019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8276 /* 21021 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8277 /* 21023 */ GIR_RootConstrainSelectedInstOperands,
8278 /* 21024 */ // GIR_Coverage, 764,
8279 /* 21024 */ GIR_EraseRootFromParent_Done,
8280 /* 21025 */ // Label 658: @21025
8281 /* 21025 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(21061), // Rule ID 765 //
8282 /* 21030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8283 /* 21033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
8284 /* 21038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8285 /* 21041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8286 /* 21044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8287 /* 21048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8288 /* 21052 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8264:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8289 /* 21052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
8290 /* 21055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8291 /* 21057 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8292 /* 21059 */ GIR_RootConstrainSelectedInstOperands,
8293 /* 21060 */ // GIR_Coverage, 765,
8294 /* 21060 */ GIR_EraseRootFromParent_Done,
8295 /* 21061 */ // Label 659: @21061
8296 /* 21061 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(21097), // Rule ID 766 //
8297 /* 21066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8298 /* 21069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
8299 /* 21074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8300 /* 21077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8301 /* 21080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8302 /* 21084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8303 /* 21088 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8269:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8304 /* 21088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
8305 /* 21091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8306 /* 21093 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8307 /* 21095 */ GIR_RootConstrainSelectedInstOperands,
8308 /* 21096 */ // GIR_Coverage, 766,
8309 /* 21096 */ GIR_EraseRootFromParent_Done,
8310 /* 21097 */ // Label 660: @21097
8311 /* 21097 */ GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(21133), // Rule ID 767 //
8312 /* 21102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8313 /* 21105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
8314 /* 21110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8315 /* 21113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8316 /* 21116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8317 /* 21120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8318 /* 21124 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8268:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8319 /* 21124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
8320 /* 21127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8321 /* 21129 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8322 /* 21131 */ GIR_RootConstrainSelectedInstOperands,
8323 /* 21132 */ // GIR_Coverage, 767,
8324 /* 21132 */ GIR_EraseRootFromParent_Done,
8325 /* 21133 */ // Label 661: @21133
8326 /* 21133 */ GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(21169), // Rule ID 794 //
8327 /* 21138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8328 /* 21141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
8329 /* 21146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8330 /* 21149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8331 /* 21152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8332 /* 21156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8333 /* 21160 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8297:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8334 /* 21160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
8335 /* 21163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8336 /* 21165 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8337 /* 21167 */ GIR_RootConstrainSelectedInstOperands,
8338 /* 21168 */ // GIR_Coverage, 794,
8339 /* 21168 */ GIR_EraseRootFromParent_Done,
8340 /* 21169 */ // Label 662: @21169
8341 /* 21169 */ GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(21205), // Rule ID 795 //
8342 /* 21174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8343 /* 21177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
8344 /* 21182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8345 /* 21185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8346 /* 21188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8347 /* 21192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8348 /* 21196 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8296:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8349 /* 21196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
8350 /* 21199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8351 /* 21201 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8352 /* 21203 */ GIR_RootConstrainSelectedInstOperands,
8353 /* 21204 */ // GIR_Coverage, 795,
8354 /* 21204 */ GIR_EraseRootFromParent_Done,
8355 /* 21205 */ // Label 663: @21205
8356 /* 21205 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(21241), // Rule ID 796 //
8357 /* 21210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8358 /* 21213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
8359 /* 21218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8360 /* 21221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8361 /* 21224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8362 /* 21228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8363 /* 21232 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8299:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
8364 /* 21232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
8365 /* 21235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8366 /* 21237 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8367 /* 21239 */ GIR_RootConstrainSelectedInstOperands,
8368 /* 21240 */ // GIR_Coverage, 796,
8369 /* 21240 */ GIR_EraseRootFromParent_Done,
8370 /* 21241 */ // Label 664: @21241
8371 /* 21241 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(21277), // Rule ID 797 //
8372 /* 21246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8373 /* 21249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
8374 /* 21254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8375 /* 21257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8376 /* 21260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8377 /* 21264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8378 /* 21268 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8298:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
8379 /* 21268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
8380 /* 21271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8381 /* 21273 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8382 /* 21275 */ GIR_RootConstrainSelectedInstOperands,
8383 /* 21276 */ // GIR_Coverage, 797,
8384 /* 21276 */ GIR_EraseRootFromParent_Done,
8385 /* 21277 */ // Label 665: @21277
8386 /* 21277 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(21313), // Rule ID 932 //
8387 /* 21282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8388 /* 21285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
8389 /* 21290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8390 /* 21293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8391 /* 21296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8392 /* 21300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8393 /* 21304 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8454:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
8394 /* 21304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
8395 /* 21307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8396 /* 21309 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8397 /* 21311 */ GIR_RootConstrainSelectedInstOperands,
8398 /* 21312 */ // GIR_Coverage, 932,
8399 /* 21312 */ GIR_EraseRootFromParent_Done,
8400 /* 21313 */ // Label 666: @21313
8401 /* 21313 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21349), // Rule ID 933 //
8402 /* 21318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8403 /* 21321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
8404 /* 21326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8405 /* 21329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8406 /* 21332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8407 /* 21336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8408 /* 21340 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8456:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
8409 /* 21340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
8410 /* 21343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8411 /* 21345 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8412 /* 21347 */ GIR_RootConstrainSelectedInstOperands,
8413 /* 21348 */ // GIR_Coverage, 933,
8414 /* 21348 */ GIR_EraseRootFromParent_Done,
8415 /* 21349 */ // Label 667: @21349
8416 /* 21349 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21385), // Rule ID 934 //
8417 /* 21354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8418 /* 21357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
8419 /* 21362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8420 /* 21365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8421 /* 21368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8422 /* 21372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8423 /* 21376 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8457:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
8424 /* 21376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
8425 /* 21379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8426 /* 21381 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8427 /* 21383 */ GIR_RootConstrainSelectedInstOperands,
8428 /* 21384 */ // GIR_Coverage, 934,
8429 /* 21384 */ GIR_EraseRootFromParent_Done,
8430 /* 21385 */ // Label 668: @21385
8431 /* 21385 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21421), // Rule ID 935 //
8432 /* 21390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8433 /* 21393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
8434 /* 21398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8435 /* 21401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8436 /* 21404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8437 /* 21408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8438 /* 21412 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8455:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
8439 /* 21412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
8440 /* 21415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8441 /* 21417 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8442 /* 21419 */ GIR_RootConstrainSelectedInstOperands,
8443 /* 21420 */ // GIR_Coverage, 935,
8444 /* 21420 */ GIR_EraseRootFromParent_Done,
8445 /* 21421 */ // Label 669: @21421
8446 /* 21421 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21457), // Rule ID 1274 //
8447 /* 21426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8448 /* 21429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
8449 /* 21434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8450 /* 21437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8451 /* 21440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8452 /* 21444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8453 /* 21448 */ // (intrinsic_wo_chain:{ *:[i32] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8454 /* 21448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
8455 /* 21451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8456 /* 21453 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8457 /* 21455 */ GIR_RootConstrainSelectedInstOperands,
8458 /* 21456 */ // GIR_Coverage, 1274,
8459 /* 21456 */ GIR_EraseRootFromParent_Done,
8460 /* 21457 */ // Label 670: @21457
8461 /* 21457 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21493), // Rule ID 1275 //
8462 /* 21462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8463 /* 21465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
8464 /* 21470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8465 /* 21473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8466 /* 21476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8467 /* 21480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8468 /* 21484 */ // (intrinsic_wo_chain:{ *:[i32] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
8469 /* 21484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
8470 /* 21487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8471 /* 21489 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8472 /* 21491 */ GIR_RootConstrainSelectedInstOperands,
8473 /* 21492 */ // GIR_Coverage, 1275,
8474 /* 21492 */ GIR_EraseRootFromParent_Done,
8475 /* 21493 */ // Label 671: @21493
8476 /* 21493 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21529), // Rule ID 1276 //
8477 /* 21498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8478 /* 21501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
8479 /* 21506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8480 /* 21509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8481 /* 21512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8482 /* 21516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8483 /* 21520 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8484 /* 21520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
8485 /* 21523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8486 /* 21525 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8487 /* 21527 */ GIR_RootConstrainSelectedInstOperands,
8488 /* 21528 */ // GIR_Coverage, 1276,
8489 /* 21528 */ GIR_EraseRootFromParent_Done,
8490 /* 21529 */ // Label 672: @21529
8491 /* 21529 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21565), // Rule ID 1277 //
8492 /* 21534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8493 /* 21537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
8494 /* 21542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8495 /* 21545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8496 /* 21548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8497 /* 21552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8498 /* 21556 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8499 /* 21556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
8500 /* 21559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8501 /* 21561 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8502 /* 21563 */ GIR_RootConstrainSelectedInstOperands,
8503 /* 21564 */ // GIR_Coverage, 1277,
8504 /* 21564 */ GIR_EraseRootFromParent_Done,
8505 /* 21565 */ // Label 673: @21565
8506 /* 21565 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21601), // Rule ID 1278 //
8507 /* 21570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8508 /* 21573 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
8509 /* 21578 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8510 /* 21581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8511 /* 21584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8512 /* 21588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8513 /* 21592 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8514 /* 21592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
8515 /* 21595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8516 /* 21597 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8517 /* 21599 */ GIR_RootConstrainSelectedInstOperands,
8518 /* 21600 */ // GIR_Coverage, 1278,
8519 /* 21600 */ GIR_EraseRootFromParent_Done,
8520 /* 21601 */ // Label 674: @21601
8521 /* 21601 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21637), // Rule ID 1279 //
8522 /* 21606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8523 /* 21609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
8524 /* 21614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8525 /* 21617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8526 /* 21620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8527 /* 21624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8528 /* 21628 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8529 /* 21628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
8530 /* 21631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8531 /* 21633 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8532 /* 21635 */ GIR_RootConstrainSelectedInstOperands,
8533 /* 21636 */ // GIR_Coverage, 1279,
8534 /* 21636 */ GIR_EraseRootFromParent_Done,
8535 /* 21637 */ // Label 675: @21637
8536 /* 21637 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21673), // Rule ID 1280 //
8537 /* 21642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8538 /* 21645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
8539 /* 21650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8540 /* 21653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8541 /* 21656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8542 /* 21660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8543 /* 21664 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8544 /* 21664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
8545 /* 21667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8546 /* 21669 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8547 /* 21671 */ GIR_RootConstrainSelectedInstOperands,
8548 /* 21672 */ // GIR_Coverage, 1280,
8549 /* 21672 */ GIR_EraseRootFromParent_Done,
8550 /* 21673 */ // Label 676: @21673
8551 /* 21673 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21709), // Rule ID 1281 //
8552 /* 21678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8553 /* 21681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
8554 /* 21686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8555 /* 21689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8556 /* 21692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8557 /* 21696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8558 /* 21700 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8559 /* 21700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
8560 /* 21703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8561 /* 21705 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8562 /* 21707 */ GIR_RootConstrainSelectedInstOperands,
8563 /* 21708 */ // GIR_Coverage, 1281,
8564 /* 21708 */ GIR_EraseRootFromParent_Done,
8565 /* 21709 */ // Label 677: @21709
8566 /* 21709 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21745), // Rule ID 1282 //
8567 /* 21714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8568 /* 21717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
8569 /* 21722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8570 /* 21725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8571 /* 21728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8572 /* 21732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8573 /* 21736 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8574 /* 21736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
8575 /* 21739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8576 /* 21741 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8577 /* 21743 */ GIR_RootConstrainSelectedInstOperands,
8578 /* 21744 */ // GIR_Coverage, 1282,
8579 /* 21744 */ GIR_EraseRootFromParent_Done,
8580 /* 21745 */ // Label 678: @21745
8581 /* 21745 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21781), // Rule ID 1283 //
8582 /* 21750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8583 /* 21753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
8584 /* 21758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8585 /* 21761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8586 /* 21764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8587 /* 21768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8588 /* 21772 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
8589 /* 21772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
8590 /* 21775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8591 /* 21777 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8592 /* 21779 */ GIR_RootConstrainSelectedInstOperands,
8593 /* 21780 */ // GIR_Coverage, 1283,
8594 /* 21780 */ GIR_EraseRootFromParent_Done,
8595 /* 21781 */ // Label 679: @21781
8596 /* 21781 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21817), // Rule ID 1309 //
8597 /* 21786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8598 /* 21789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
8599 /* 21794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8600 /* 21797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8601 /* 21800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8602 /* 21804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8603 /* 21808 */ // (intrinsic_wo_chain:{ *:[i32] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
8604 /* 21808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
8605 /* 21811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8606 /* 21813 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8607 /* 21815 */ GIR_RootConstrainSelectedInstOperands,
8608 /* 21816 */ // GIR_Coverage, 1309,
8609 /* 21816 */ GIR_EraseRootFromParent_Done,
8610 /* 21817 */ // Label 680: @21817
8611 /* 21817 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21853), // Rule ID 1313 //
8612 /* 21822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8613 /* 21825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8614 /* 21830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8615 /* 21833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8616 /* 21836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8617 /* 21840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8618 /* 21844 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
8619 /* 21844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
8620 /* 21847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8621 /* 21849 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8622 /* 21851 */ GIR_RootConstrainSelectedInstOperands,
8623 /* 21852 */ // GIR_Coverage, 1313,
8624 /* 21852 */ GIR_EraseRootFromParent_Done,
8625 /* 21853 */ // Label 681: @21853
8626 /* 21853 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21889), // Rule ID 1314 //
8627 /* 21858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8628 /* 21861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8629 /* 21866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8630 /* 21869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8631 /* 21872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8632 /* 21876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8633 /* 21880 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
8634 /* 21880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
8635 /* 21883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8636 /* 21885 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8637 /* 21887 */ GIR_RootConstrainSelectedInstOperands,
8638 /* 21888 */ // GIR_Coverage, 1314,
8639 /* 21888 */ GIR_EraseRootFromParent_Done,
8640 /* 21889 */ // Label 682: @21889
8641 /* 21889 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21925), // Rule ID 1324 //
8642 /* 21894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
8643 /* 21897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8644 /* 21902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8645 /* 21905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8646 /* 21908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8647 /* 21912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8648 /* 21916 */ // (intrinsic_wo_chain:{ *:[i32] } 8055:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
8649 /* 21916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
8650 /* 21919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8651 /* 21921 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8652 /* 21923 */ GIR_RootConstrainSelectedInstOperands,
8653 /* 21924 */ // GIR_Coverage, 1324,
8654 /* 21924 */ GIR_EraseRootFromParent_Done,
8655 /* 21925 */ // Label 683: @21925
8656 /* 21925 */ GIM_Reject,
8657 /* 21926 */ // Label 629: @21926
8658 /* 21926 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31679),
8659 /* 21931 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
8660 /* 21934 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21980), // Rule ID 962 //
8661 /* 21939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8662 /* 21942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
8663 /* 21947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8664 /* 21950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8665 /* 21953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8666 /* 21957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8667 /* 21961 */ // MIs[0] m
8668 /* 21961 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8669 /* 21964 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8670 /* 21969 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8503:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8671 /* 21969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
8672 /* 21972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8673 /* 21974 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8674 /* 21976 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8675 /* 21978 */ GIR_RootConstrainSelectedInstOperands,
8676 /* 21979 */ // GIR_Coverage, 962,
8677 /* 21979 */ GIR_EraseRootFromParent_Done,
8678 /* 21980 */ // Label 685: @21980
8679 /* 21980 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(22026), // Rule ID 963 //
8680 /* 21985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8681 /* 21988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
8682 /* 21993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8683 /* 21996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8684 /* 21999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8685 /* 22003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8686 /* 22007 */ // MIs[0] m
8687 /* 22007 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8688 /* 22010 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8689 /* 22015 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8505:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8690 /* 22015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
8691 /* 22018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8692 /* 22020 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8693 /* 22022 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8694 /* 22024 */ GIR_RootConstrainSelectedInstOperands,
8695 /* 22025 */ // GIR_Coverage, 963,
8696 /* 22025 */ GIR_EraseRootFromParent_Done,
8697 /* 22026 */ // Label 686: @22026
8698 /* 22026 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(22072), // Rule ID 964 //
8699 /* 22031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8700 /* 22034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
8701 /* 22039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8702 /* 22042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8703 /* 22045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8704 /* 22049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8705 /* 22053 */ // MIs[0] m
8706 /* 22053 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8707 /* 22056 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8708 /* 22061 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8506:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8709 /* 22061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
8710 /* 22064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8711 /* 22066 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8712 /* 22068 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8713 /* 22070 */ GIR_RootConstrainSelectedInstOperands,
8714 /* 22071 */ // GIR_Coverage, 964,
8715 /* 22071 */ GIR_EraseRootFromParent_Done,
8716 /* 22072 */ // Label 687: @22072
8717 /* 22072 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(22118), // Rule ID 965 //
8718 /* 22077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8719 /* 22080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8720 /* 22085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8721 /* 22088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8722 /* 22091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8723 /* 22095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8724 /* 22099 */ // MIs[0] m
8725 /* 22099 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8726 /* 22102 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8727 /* 22107 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8504:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8728 /* 22107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
8729 /* 22110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8730 /* 22112 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8731 /* 22114 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8732 /* 22116 */ GIR_RootConstrainSelectedInstOperands,
8733 /* 22117 */ // GIR_Coverage, 965,
8734 /* 22117 */ GIR_EraseRootFromParent_Done,
8735 /* 22118 */ // Label 688: @22118
8736 /* 22118 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(22164), // Rule ID 966 //
8737 /* 22123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8738 /* 22126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8739 /* 22131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8740 /* 22134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8741 /* 22137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8742 /* 22141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8743 /* 22145 */ // MIs[0] m
8744 /* 22145 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8745 /* 22148 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8746 /* 22153 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8507:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8747 /* 22153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
8748 /* 22156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8749 /* 22158 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8750 /* 22160 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8751 /* 22162 */ GIR_RootConstrainSelectedInstOperands,
8752 /* 22163 */ // GIR_Coverage, 966,
8753 /* 22163 */ GIR_EraseRootFromParent_Done,
8754 /* 22164 */ // Label 689: @22164
8755 /* 22164 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(22210), // Rule ID 967 //
8756 /* 22169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8757 /* 22172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8758 /* 22177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8759 /* 22180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8760 /* 22183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8761 /* 22187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8762 /* 22191 */ // MIs[0] m
8763 /* 22191 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8764 /* 22194 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8765 /* 22199 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8509:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8766 /* 22199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
8767 /* 22202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8768 /* 22204 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8769 /* 22206 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8770 /* 22208 */ GIR_RootConstrainSelectedInstOperands,
8771 /* 22209 */ // GIR_Coverage, 967,
8772 /* 22209 */ GIR_EraseRootFromParent_Done,
8773 /* 22210 */ // Label 690: @22210
8774 /* 22210 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(22256), // Rule ID 968 //
8775 /* 22215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8776 /* 22218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8777 /* 22223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8778 /* 22226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8779 /* 22229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8780 /* 22233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8781 /* 22237 */ // MIs[0] m
8782 /* 22237 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8783 /* 22240 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8784 /* 22245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8510:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8785 /* 22245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
8786 /* 22248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8787 /* 22250 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8788 /* 22252 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8789 /* 22254 */ GIR_RootConstrainSelectedInstOperands,
8790 /* 22255 */ // GIR_Coverage, 968,
8791 /* 22255 */ GIR_EraseRootFromParent_Done,
8792 /* 22256 */ // Label 691: @22256
8793 /* 22256 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(22302), // Rule ID 969 //
8794 /* 22261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8795 /* 22264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8796 /* 22269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8797 /* 22272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8798 /* 22275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8799 /* 22279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8800 /* 22283 */ // MIs[0] m
8801 /* 22283 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8802 /* 22286 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8803 /* 22291 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8508:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8804 /* 22291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
8805 /* 22294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8806 /* 22296 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8807 /* 22298 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8808 /* 22300 */ GIR_RootConstrainSelectedInstOperands,
8809 /* 22301 */ // GIR_Coverage, 969,
8810 /* 22301 */ GIR_EraseRootFromParent_Done,
8811 /* 22302 */ // Label 692: @22302
8812 /* 22302 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(22348), // Rule ID 1009 //
8813 /* 22307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8814 /* 22310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
8815 /* 22315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8816 /* 22318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8817 /* 22321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8818 /* 22325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8819 /* 22329 */ // MIs[0] m
8820 /* 22329 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8821 /* 22332 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8822 /* 22337 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8823 /* 22337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
8824 /* 22340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8825 /* 22342 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8826 /* 22344 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8827 /* 22346 */ GIR_RootConstrainSelectedInstOperands,
8828 /* 22347 */ // GIR_Coverage, 1009,
8829 /* 22347 */ GIR_EraseRootFromParent_Done,
8830 /* 22348 */ // Label 693: @22348
8831 /* 22348 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(22394), // Rule ID 1010 //
8832 /* 22353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8833 /* 22356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
8834 /* 22361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8835 /* 22364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8836 /* 22367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8837 /* 22371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8838 /* 22375 */ // MIs[0] m
8839 /* 22375 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8840 /* 22378 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8841 /* 22383 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8564:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8842 /* 22383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
8843 /* 22386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8844 /* 22388 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8845 /* 22390 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8846 /* 22392 */ GIR_RootConstrainSelectedInstOperands,
8847 /* 22393 */ // GIR_Coverage, 1010,
8848 /* 22393 */ GIR_EraseRootFromParent_Done,
8849 /* 22394 */ // Label 694: @22394
8850 /* 22394 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(22440), // Rule ID 1011 //
8851 /* 22399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8852 /* 22402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
8853 /* 22407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8854 /* 22410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8855 /* 22413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8856 /* 22417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8857 /* 22421 */ // MIs[0] m
8858 /* 22421 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8859 /* 22424 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8860 /* 22429 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8565:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8861 /* 22429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
8862 /* 22432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8863 /* 22434 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8864 /* 22436 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8865 /* 22438 */ GIR_RootConstrainSelectedInstOperands,
8866 /* 22439 */ // GIR_Coverage, 1011,
8867 /* 22439 */ GIR_EraseRootFromParent_Done,
8868 /* 22440 */ // Label 695: @22440
8869 /* 22440 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(22486), // Rule ID 1012 //
8870 /* 22445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8871 /* 22448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
8872 /* 22453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8873 /* 22456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8874 /* 22459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8875 /* 22463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8876 /* 22467 */ // MIs[0] m
8877 /* 22467 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8878 /* 22470 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8879 /* 22475 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8880 /* 22475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
8881 /* 22478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8882 /* 22480 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8883 /* 22482 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8884 /* 22484 */ GIR_RootConstrainSelectedInstOperands,
8885 /* 22485 */ // GIR_Coverage, 1012,
8886 /* 22485 */ GIR_EraseRootFromParent_Done,
8887 /* 22486 */ // Label 696: @22486
8888 /* 22486 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(22532), // Rule ID 1025 //
8889 /* 22491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8890 /* 22494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
8891 /* 22499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8892 /* 22502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8893 /* 22505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8894 /* 22509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8895 /* 22513 */ // MIs[0] m
8896 /* 22513 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8897 /* 22516 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8898 /* 22521 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8578:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8899 /* 22521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
8900 /* 22524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8901 /* 22526 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8902 /* 22528 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8903 /* 22530 */ GIR_RootConstrainSelectedInstOperands,
8904 /* 22531 */ // GIR_Coverage, 1025,
8905 /* 22531 */ GIR_EraseRootFromParent_Done,
8906 /* 22532 */ // Label 697: @22532
8907 /* 22532 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(22578), // Rule ID 1026 //
8908 /* 22537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8909 /* 22540 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
8910 /* 22545 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8911 /* 22548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8912 /* 22551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8913 /* 22555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8914 /* 22559 */ // MIs[0] m
8915 /* 22559 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8916 /* 22562 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8917 /* 22567 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8580:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8918 /* 22567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
8919 /* 22570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8920 /* 22572 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8921 /* 22574 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8922 /* 22576 */ GIR_RootConstrainSelectedInstOperands,
8923 /* 22577 */ // GIR_Coverage, 1026,
8924 /* 22577 */ GIR_EraseRootFromParent_Done,
8925 /* 22578 */ // Label 698: @22578
8926 /* 22578 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(22624), // Rule ID 1027 //
8927 /* 22583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8928 /* 22586 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
8929 /* 22591 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8930 /* 22594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8931 /* 22597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8932 /* 22601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8933 /* 22605 */ // MIs[0] m
8934 /* 22605 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8935 /* 22608 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8936 /* 22613 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8581:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8937 /* 22613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
8938 /* 22616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8939 /* 22618 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8940 /* 22620 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8941 /* 22622 */ GIR_RootConstrainSelectedInstOperands,
8942 /* 22623 */ // GIR_Coverage, 1027,
8943 /* 22623 */ GIR_EraseRootFromParent_Done,
8944 /* 22624 */ // Label 699: @22624
8945 /* 22624 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(22670), // Rule ID 1028 //
8946 /* 22629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8947 /* 22632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
8948 /* 22637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8949 /* 22640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8950 /* 22643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8951 /* 22647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8952 /* 22651 */ // MIs[0] m
8953 /* 22651 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8954 /* 22654 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8955 /* 22659 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8579:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8956 /* 22659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
8957 /* 22662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8958 /* 22664 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8959 /* 22666 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8960 /* 22668 */ GIR_RootConstrainSelectedInstOperands,
8961 /* 22669 */ // GIR_Coverage, 1028,
8962 /* 22669 */ GIR_EraseRootFromParent_Done,
8963 /* 22670 */ // Label 700: @22670
8964 /* 22670 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(22726), // Rule ID 409 //
8965 /* 22675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8966 /* 22678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8967 /* 22683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8968 /* 22686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8969 /* 22689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8970 /* 22692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8971 /* 22696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8972 /* 22700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8973 /* 22704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8974 /* 22708 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8975 /* 22712 */ // MIs[1] Operand 1
8976 /* 22712 */ // No operand predicates
8977 /* 22712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8978 /* 22714 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8979 /* 22714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
8980 /* 22717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8981 /* 22719 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8982 /* 22721 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8983 /* 22724 */ GIR_RootConstrainSelectedInstOperands,
8984 /* 22725 */ // GIR_Coverage, 409,
8985 /* 22725 */ GIR_EraseRootFromParent_Done,
8986 /* 22726 */ // Label 701: @22726
8987 /* 22726 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(22782), // Rule ID 413 //
8988 /* 22731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
8989 /* 22734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8990 /* 22739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8991 /* 22742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8992 /* 22745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8993 /* 22748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8994 /* 22752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8995 /* 22756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8996 /* 22760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8997 /* 22764 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8998 /* 22768 */ // MIs[1] Operand 1
8999 /* 22768 */ // No operand predicates
9000 /* 22768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9001 /* 22770 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
9002 /* 22770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
9003 /* 22773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9004 /* 22775 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9005 /* 22777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
9006 /* 22780 */ GIR_RootConstrainSelectedInstOperands,
9007 /* 22781 */ // GIR_Coverage, 413,
9008 /* 22781 */ GIR_EraseRootFromParent_Done,
9009 /* 22782 */ // Label 702: @22782
9010 /* 22782 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(22838), // Rule ID 504 //
9011 /* 22787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9012 /* 22790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9013 /* 22795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9014 /* 22798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9015 /* 22801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9016 /* 22804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9017 /* 22808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9018 /* 22812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9019 /* 22816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9020 /* 22820 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9021 /* 22824 */ // MIs[1] Operand 1
9022 /* 22824 */ // No operand predicates
9023 /* 22824 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9024 /* 22826 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
9025 /* 22826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
9026 /* 22829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9027 /* 22831 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9028 /* 22833 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
9029 /* 22836 */ GIR_RootConstrainSelectedInstOperands,
9030 /* 22837 */ // GIR_Coverage, 504,
9031 /* 22837 */ GIR_EraseRootFromParent_Done,
9032 /* 22838 */ // Label 703: @22838
9033 /* 22838 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(22894), // Rule ID 1268 //
9034 /* 22843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
9035 /* 22846 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
9036 /* 22851 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9037 /* 22854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9038 /* 22857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9039 /* 22860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9040 /* 22864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9041 /* 22868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9042 /* 22872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9043 /* 22876 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9044 /* 22880 */ // MIs[1] Operand 1
9045 /* 22880 */ // No operand predicates
9046 /* 22880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9047 /* 22882 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
9048 /* 22882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
9049 /* 22885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9050 /* 22887 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9051 /* 22889 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9052 /* 22892 */ GIR_RootConstrainSelectedInstOperands,
9053 /* 22893 */ // GIR_Coverage, 1268,
9054 /* 22893 */ GIR_EraseRootFromParent_Done,
9055 /* 22894 */ // Label 704: @22894
9056 /* 22894 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(22950), // Rule ID 1272 //
9057 /* 22899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
9058 /* 22902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
9059 /* 22907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9060 /* 22910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9061 /* 22913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9062 /* 22916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9063 /* 22920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9064 /* 22924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9065 /* 22928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9066 /* 22932 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
9067 /* 22936 */ // MIs[1] Operand 1
9068 /* 22936 */ // No operand predicates
9069 /* 22936 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9070 /* 22938 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
9071 /* 22938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
9072 /* 22941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9073 /* 22943 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9074 /* 22945 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9075 /* 22948 */ GIR_RootConstrainSelectedInstOperands,
9076 /* 22949 */ // GIR_Coverage, 1272,
9077 /* 22949 */ GIR_EraseRootFromParent_Done,
9078 /* 22950 */ // Label 705: @22950
9079 /* 22950 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(23006), // Rule ID 1347 //
9080 /* 22955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
9081 /* 22958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9082 /* 22963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9083 /* 22966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9084 /* 22969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9085 /* 22972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9086 /* 22976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9087 /* 22980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9088 /* 22984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9089 /* 22988 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9090 /* 22992 */ // MIs[1] Operand 1
9091 /* 22992 */ // No operand predicates
9092 /* 22992 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9093 /* 22994 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
9094 /* 22994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
9095 /* 22997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
9096 /* 22999 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9097 /* 23001 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
9098 /* 23004 */ GIR_RootConstrainSelectedInstOperands,
9099 /* 23005 */ // GIR_Coverage, 1347,
9100 /* 23005 */ GIR_EraseRootFromParent_Done,
9101 /* 23006 */ // Label 706: @23006
9102 /* 23006 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(23058), // Rule ID 2069 //
9103 /* 23011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9104 /* 23014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
9105 /* 23019 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9106 /* 23022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9107 /* 23025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9108 /* 23028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9109 /* 23032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9110 /* 23036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9111 /* 23040 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9112 /* 23044 */ // MIs[1] Operand 1
9113 /* 23044 */ // No operand predicates
9114 /* 23044 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9115 /* 23046 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
9116 /* 23046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
9117 /* 23049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9118 /* 23051 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9119 /* 23053 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9120 /* 23056 */ GIR_RootConstrainSelectedInstOperands,
9121 /* 23057 */ // GIR_Coverage, 2069,
9122 /* 23057 */ GIR_EraseRootFromParent_Done,
9123 /* 23058 */ // Label 707: @23058
9124 /* 23058 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(23110), // Rule ID 2070 //
9125 /* 23063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9126 /* 23066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9127 /* 23071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9128 /* 23074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9129 /* 23077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9130 /* 23080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9131 /* 23084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9132 /* 23088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9133 /* 23092 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
9134 /* 23096 */ // MIs[1] Operand 1
9135 /* 23096 */ // No operand predicates
9136 /* 23096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9137 /* 23098 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
9138 /* 23098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
9139 /* 23101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9140 /* 23103 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9141 /* 23105 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9142 /* 23108 */ GIR_RootConstrainSelectedInstOperands,
9143 /* 23109 */ // GIR_Coverage, 2070,
9144 /* 23109 */ GIR_EraseRootFromParent_Done,
9145 /* 23110 */ // Label 708: @23110
9146 /* 23110 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(23162), // Rule ID 2075 //
9147 /* 23115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9148 /* 23118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
9149 /* 23123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9150 /* 23126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9151 /* 23129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9152 /* 23132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9153 /* 23136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9154 /* 23140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9155 /* 23144 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9156 /* 23148 */ // MIs[1] Operand 1
9157 /* 23148 */ // No operand predicates
9158 /* 23148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9159 /* 23150 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
9160 /* 23150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
9161 /* 23153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9162 /* 23155 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9163 /* 23157 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9164 /* 23160 */ GIR_RootConstrainSelectedInstOperands,
9165 /* 23161 */ // GIR_Coverage, 2075,
9166 /* 23161 */ GIR_EraseRootFromParent_Done,
9167 /* 23162 */ // Label 709: @23162
9168 /* 23162 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(23214), // Rule ID 2076 //
9169 /* 23167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9170 /* 23170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
9171 /* 23175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9172 /* 23178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9173 /* 23181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9174 /* 23184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9175 /* 23188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
9176 /* 23192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9177 /* 23196 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
9178 /* 23200 */ // MIs[1] Operand 1
9179 /* 23200 */ // No operand predicates
9180 /* 23200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9181 /* 23202 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
9182 /* 23202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
9183 /* 23205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9184 /* 23207 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
9185 /* 23209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
9186 /* 23212 */ GIR_RootConstrainSelectedInstOperands,
9187 /* 23213 */ // GIR_Coverage, 2076,
9188 /* 23213 */ GIR_EraseRootFromParent_Done,
9189 /* 23214 */ // Label 710: @23214
9190 /* 23214 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(23262), // Rule ID 379 //
9191 /* 23219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9192 /* 23222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
9193 /* 23227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9194 /* 23230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9195 /* 23233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9196 /* 23236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9197 /* 23240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9198 /* 23244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9199 /* 23248 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9200 /* 23248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
9201 /* 23251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9202 /* 23253 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9203 /* 23255 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9204 /* 23257 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9205 /* 23260 */ GIR_RootConstrainSelectedInstOperands,
9206 /* 23261 */ // GIR_Coverage, 379,
9207 /* 23261 */ GIR_EraseRootFromParent_Done,
9208 /* 23262 */ // Label 711: @23262
9209 /* 23262 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(23310), // Rule ID 380 //
9210 /* 23267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9211 /* 23270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
9212 /* 23275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9213 /* 23278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9214 /* 23281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9215 /* 23284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9216 /* 23288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9217 /* 23292 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9218 /* 23296 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9219 /* 23296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
9220 /* 23299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9221 /* 23301 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9222 /* 23303 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9223 /* 23305 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9224 /* 23308 */ GIR_RootConstrainSelectedInstOperands,
9225 /* 23309 */ // GIR_Coverage, 380,
9226 /* 23309 */ GIR_EraseRootFromParent_Done,
9227 /* 23310 */ // Label 712: @23310
9228 /* 23310 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(23358), // Rule ID 381 //
9229 /* 23315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9230 /* 23318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
9231 /* 23323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9232 /* 23326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9233 /* 23329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9234 /* 23332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9235 /* 23336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9236 /* 23340 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9237 /* 23344 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7969:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9238 /* 23344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
9239 /* 23347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9240 /* 23349 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9241 /* 23351 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9242 /* 23353 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9243 /* 23356 */ GIR_RootConstrainSelectedInstOperands,
9244 /* 23357 */ // GIR_Coverage, 381,
9245 /* 23357 */ GIR_EraseRootFromParent_Done,
9246 /* 23358 */ // Label 713: @23358
9247 /* 23358 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(23406), // Rule ID 382 //
9248 /* 23363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9249 /* 23366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
9250 /* 23371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9251 /* 23374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9252 /* 23377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9253 /* 23380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9254 /* 23384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9255 /* 23388 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9256 /* 23392 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8589:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9257 /* 23392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
9258 /* 23395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9259 /* 23397 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9260 /* 23399 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9261 /* 23401 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
9262 /* 23404 */ GIR_RootConstrainSelectedInstOperands,
9263 /* 23405 */ // GIR_Coverage, 382,
9264 /* 23405 */ GIR_EraseRootFromParent_Done,
9265 /* 23406 */ // Label 714: @23406
9266 /* 23406 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(23451), // Rule ID 385 //
9267 /* 23411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9268 /* 23414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
9269 /* 23419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9270 /* 23422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9271 /* 23425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9272 /* 23428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9273 /* 23432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9274 /* 23436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9275 /* 23440 */ // (intrinsic_wo_chain:{ *:[i32] } 8419:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9276 /* 23440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
9277 /* 23443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9278 /* 23445 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9279 /* 23447 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9280 /* 23449 */ GIR_RootConstrainSelectedInstOperands,
9281 /* 23450 */ // GIR_Coverage, 385,
9282 /* 23450 */ GIR_EraseRootFromParent_Done,
9283 /* 23451 */ // Label 715: @23451
9284 /* 23451 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(23496), // Rule ID 389 //
9285 /* 23456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9286 /* 23459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
9287 /* 23464 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9288 /* 23467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9289 /* 23470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9290 /* 23473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9291 /* 23477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9292 /* 23481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9293 /* 23485 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9294 /* 23485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
9295 /* 23488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9296 /* 23490 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9297 /* 23492 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9298 /* 23494 */ GIR_RootConstrainSelectedInstOperands,
9299 /* 23495 */ // GIR_Coverage, 389,
9300 /* 23495 */ GIR_EraseRootFromParent_Done,
9301 /* 23496 */ // Label 716: @23496
9302 /* 23496 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(23541), // Rule ID 390 //
9303 /* 23501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9304 /* 23504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
9305 /* 23509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9306 /* 23512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9307 /* 23515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9308 /* 23518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9309 /* 23522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9310 /* 23526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9311 /* 23530 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9312 /* 23530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
9313 /* 23533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9314 /* 23535 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9315 /* 23537 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9316 /* 23539 */ GIR_RootConstrainSelectedInstOperands,
9317 /* 23540 */ // GIR_Coverage, 390,
9318 /* 23540 */ GIR_EraseRootFromParent_Done,
9319 /* 23541 */ // Label 717: @23541
9320 /* 23541 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(23586), // Rule ID 404 //
9321 /* 23546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9322 /* 23549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
9323 /* 23554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9324 /* 23557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9325 /* 23560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9326 /* 23563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9327 /* 23567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9328 /* 23571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9329 /* 23575 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9330 /* 23575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
9331 /* 23578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9332 /* 23580 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9333 /* 23582 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9334 /* 23584 */ GIR_RootConstrainSelectedInstOperands,
9335 /* 23585 */ // GIR_Coverage, 404,
9336 /* 23585 */ GIR_EraseRootFromParent_Done,
9337 /* 23586 */ // Label 718: @23586
9338 /* 23586 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(23631), // Rule ID 408 //
9339 /* 23591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9340 /* 23594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
9341 /* 23599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9342 /* 23602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9343 /* 23605 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9344 /* 23608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9345 /* 23612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9346 /* 23616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9347 /* 23620 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9348 /* 23620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
9349 /* 23623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9350 /* 23625 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9351 /* 23627 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9352 /* 23629 */ GIR_RootConstrainSelectedInstOperands,
9353 /* 23630 */ // GIR_Coverage, 408,
9354 /* 23630 */ GIR_EraseRootFromParent_Done,
9355 /* 23631 */ // Label 719: @23631
9356 /* 23631 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(23676), // Rule ID 410 //
9357 /* 23636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9358 /* 23639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
9359 /* 23644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9360 /* 23647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9361 /* 23650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9362 /* 23653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9363 /* 23657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9364 /* 23661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9365 /* 23665 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9366 /* 23665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
9367 /* 23668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9368 /* 23670 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9369 /* 23672 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9370 /* 23674 */ GIR_RootConstrainSelectedInstOperands,
9371 /* 23675 */ // GIR_Coverage, 410,
9372 /* 23675 */ GIR_EraseRootFromParent_Done,
9373 /* 23676 */ // Label 720: @23676
9374 /* 23676 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(23721), // Rule ID 414 //
9375 /* 23681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9376 /* 23684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
9377 /* 23689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9378 /* 23692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9379 /* 23695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9380 /* 23698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9381 /* 23702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9382 /* 23706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9383 /* 23710 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9384 /* 23710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
9385 /* 23713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9386 /* 23715 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9387 /* 23717 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9388 /* 23719 */ GIR_RootConstrainSelectedInstOperands,
9389 /* 23720 */ // GIR_Coverage, 414,
9390 /* 23720 */ GIR_EraseRootFromParent_Done,
9391 /* 23721 */ // Label 721: @23721
9392 /* 23721 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(23766), // Rule ID 451 //
9393 /* 23726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
9394 /* 23729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
9395 /* 23734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9396 /* 23737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9397 /* 23740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9398 /* 23743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9399 /* 23747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9400 /* 23751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9401 /* 23755 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9402 /* 23755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
9403 /* 23758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9404 /* 23760 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9405 /* 23762 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9406 /* 23764 */ GIR_RootConstrainSelectedInstOperands,
9407 /* 23765 */ // GIR_Coverage, 451,
9408 /* 23765 */ GIR_EraseRootFromParent_Done,
9409 /* 23766 */ // Label 722: @23766
9410 /* 23766 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(23811), // Rule ID 475 //
9411 /* 23771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9412 /* 23774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
9413 /* 23779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9414 /* 23782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9415 /* 23785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9416 /* 23788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9417 /* 23792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9418 /* 23796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9419 /* 23800 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7992:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9420 /* 23800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
9421 /* 23803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9422 /* 23805 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9423 /* 23807 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9424 /* 23809 */ GIR_RootConstrainSelectedInstOperands,
9425 /* 23810 */ // GIR_Coverage, 475,
9426 /* 23810 */ GIR_EraseRootFromParent_Done,
9427 /* 23811 */ // Label 723: @23811
9428 /* 23811 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(23856), // Rule ID 476 //
9429 /* 23816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9430 /* 23819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
9431 /* 23824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9432 /* 23827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9433 /* 23830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9434 /* 23833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9435 /* 23837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9436 /* 23841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9437 /* 23845 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9438 /* 23845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
9439 /* 23848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9440 /* 23850 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9441 /* 23852 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9442 /* 23854 */ GIR_RootConstrainSelectedInstOperands,
9443 /* 23855 */ // GIR_Coverage, 476,
9444 /* 23855 */ GIR_EraseRootFromParent_Done,
9445 /* 23856 */ // Label 724: @23856
9446 /* 23856 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(23901), // Rule ID 477 //
9447 /* 23861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9448 /* 23864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
9449 /* 23869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9450 /* 23872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9451 /* 23875 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9452 /* 23878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9453 /* 23882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9454 /* 23886 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9455 /* 23890 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8615:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9456 /* 23890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
9457 /* 23893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9458 /* 23895 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9459 /* 23897 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9460 /* 23899 */ GIR_RootConstrainSelectedInstOperands,
9461 /* 23900 */ // GIR_Coverage, 477,
9462 /* 23900 */ GIR_EraseRootFromParent_Done,
9463 /* 23901 */ // Label 725: @23901
9464 /* 23901 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(23946), // Rule ID 478 //
9465 /* 23906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9466 /* 23909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
9467 /* 23914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9468 /* 23917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9469 /* 23920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
9470 /* 23923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9471 /* 23927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9472 /* 23931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9473 /* 23935 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8616:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
9474 /* 23935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
9475 /* 23938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9476 /* 23940 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9477 /* 23942 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9478 /* 23944 */ GIR_RootConstrainSelectedInstOperands,
9479 /* 23945 */ // GIR_Coverage, 478,
9480 /* 23945 */ GIR_EraseRootFromParent_Done,
9481 /* 23946 */ // Label 726: @23946
9482 /* 23946 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(23991), // Rule ID 479 //
9483 /* 23951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9484 /* 23954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
9485 /* 23959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9486 /* 23962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9487 /* 23965 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9488 /* 23968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9489 /* 23972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9490 /* 23976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9491 /* 23980 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7971:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9492 /* 23980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
9493 /* 23983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9494 /* 23985 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9495 /* 23987 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9496 /* 23989 */ GIR_RootConstrainSelectedInstOperands,
9497 /* 23990 */ // GIR_Coverage, 479,
9498 /* 23990 */ GIR_EraseRootFromParent_Done,
9499 /* 23991 */ // Label 727: @23991
9500 /* 23991 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(24036), // Rule ID 480 //
9501 /* 23996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9502 /* 23999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
9503 /* 24004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9504 /* 24007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9505 /* 24010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9506 /* 24013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9507 /* 24017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9508 /* 24021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9509 /* 24025 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9510 /* 24025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
9511 /* 24028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9512 /* 24030 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9513 /* 24032 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9514 /* 24034 */ GIR_RootConstrainSelectedInstOperands,
9515 /* 24035 */ // GIR_Coverage, 480,
9516 /* 24035 */ GIR_EraseRootFromParent_Done,
9517 /* 24036 */ // Label 728: @24036
9518 /* 24036 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(24081), // Rule ID 481 //
9519 /* 24041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9520 /* 24044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
9521 /* 24049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9522 /* 24052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9523 /* 24055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9524 /* 24058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9525 /* 24062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9526 /* 24066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9527 /* 24070 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8591:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9528 /* 24070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
9529 /* 24073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9530 /* 24075 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9531 /* 24077 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9532 /* 24079 */ GIR_RootConstrainSelectedInstOperands,
9533 /* 24080 */ // GIR_Coverage, 481,
9534 /* 24080 */ GIR_EraseRootFromParent_Done,
9535 /* 24081 */ // Label 729: @24081
9536 /* 24081 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(24126), // Rule ID 482 //
9537 /* 24086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9538 /* 24089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
9539 /* 24094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9540 /* 24097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9541 /* 24100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
9542 /* 24103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9543 /* 24107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9544 /* 24111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9545 /* 24115 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
9546 /* 24115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
9547 /* 24118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9548 /* 24120 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9549 /* 24122 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9550 /* 24124 */ GIR_RootConstrainSelectedInstOperands,
9551 /* 24125 */ // GIR_Coverage, 482,
9552 /* 24125 */ GIR_EraseRootFromParent_Done,
9553 /* 24126 */ // Label 730: @24126
9554 /* 24126 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(24171), // Rule ID 483 //
9555 /* 24131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9556 /* 24134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
9557 /* 24139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9558 /* 24142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9559 /* 24145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9560 /* 24148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9561 /* 24152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9562 /* 24156 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9563 /* 24160 */ // (intrinsic_wo_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9564 /* 24160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
9565 /* 24163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9566 /* 24165 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9567 /* 24167 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9568 /* 24169 */ GIR_RootConstrainSelectedInstOperands,
9569 /* 24170 */ // GIR_Coverage, 483,
9570 /* 24170 */ GIR_EraseRootFromParent_Done,
9571 /* 24171 */ // Label 731: @24171
9572 /* 24171 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(24216), // Rule ID 484 //
9573 /* 24176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9574 /* 24179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
9575 /* 24184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9576 /* 24187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9577 /* 24190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9578 /* 24193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9579 /* 24197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9580 /* 24201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9581 /* 24205 */ // (intrinsic_wo_chain:{ *:[i32] } 7973:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9582 /* 24205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
9583 /* 24208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9584 /* 24210 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9585 /* 24212 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9586 /* 24214 */ GIR_RootConstrainSelectedInstOperands,
9587 /* 24215 */ // GIR_Coverage, 484,
9588 /* 24215 */ GIR_EraseRootFromParent_Done,
9589 /* 24216 */ // Label 732: @24216
9590 /* 24216 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(24261), // Rule ID 485 //
9591 /* 24221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9592 /* 24224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
9593 /* 24229 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9594 /* 24232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9595 /* 24235 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9596 /* 24238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9597 /* 24242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9598 /* 24246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9599 /* 24250 */ // (intrinsic_wo_chain:{ *:[i32] } 8594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9600 /* 24250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
9601 /* 24253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9602 /* 24255 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9603 /* 24257 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9604 /* 24259 */ GIR_RootConstrainSelectedInstOperands,
9605 /* 24260 */ // GIR_Coverage, 485,
9606 /* 24260 */ GIR_EraseRootFromParent_Done,
9607 /* 24261 */ // Label 733: @24261
9608 /* 24261 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(24306), // Rule ID 486 //
9609 /* 24266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9610 /* 24269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
9611 /* 24274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
9612 /* 24277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9613 /* 24280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9614 /* 24283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9615 /* 24287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9616 /* 24291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9617 /* 24295 */ // (intrinsic_wo_chain:{ *:[i32] } 8593:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
9618 /* 24295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
9619 /* 24298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9620 /* 24300 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
9621 /* 24302 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
9622 /* 24304 */ GIR_RootConstrainSelectedInstOperands,
9623 /* 24305 */ // GIR_Coverage, 486,
9624 /* 24305 */ GIR_EraseRootFromParent_Done,
9625 /* 24306 */ // Label 734: @24306
9626 /* 24306 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(24351), // Rule ID 503 //
9627 /* 24311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9628 /* 24314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
9629 /* 24319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9630 /* 24322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9631 /* 24325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9632 /* 24328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9633 /* 24332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9634 /* 24336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9635 /* 24340 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9636 /* 24340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
9637 /* 24343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9638 /* 24345 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9639 /* 24347 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9640 /* 24349 */ GIR_RootConstrainSelectedInstOperands,
9641 /* 24350 */ // GIR_Coverage, 503,
9642 /* 24350 */ GIR_EraseRootFromParent_Done,
9643 /* 24351 */ // Label 735: @24351
9644 /* 24351 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(24396), // Rule ID 505 //
9645 /* 24356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9646 /* 24359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
9647 /* 24364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
9648 /* 24367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
9649 /* 24370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9650 /* 24373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9651 /* 24377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9652 /* 24381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9653 /* 24385 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9654 /* 24385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
9655 /* 24388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9656 /* 24390 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9657 /* 24392 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9658 /* 24394 */ GIR_RootConstrainSelectedInstOperands,
9659 /* 24395 */ // GIR_Coverage, 505,
9660 /* 24395 */ GIR_EraseRootFromParent_Done,
9661 /* 24396 */ // Label 736: @24396
9662 /* 24396 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(24441), // Rule ID 506 //
9663 /* 24401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
9664 /* 24404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9665 /* 24409 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9666 /* 24412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9667 /* 24415 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9668 /* 24418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9669 /* 24422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9670 /* 24426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9671 /* 24430 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9672 /* 24430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
9673 /* 24433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9674 /* 24435 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9675 /* 24437 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9676 /* 24439 */ GIR_RootConstrainSelectedInstOperands,
9677 /* 24440 */ // GIR_Coverage, 506,
9678 /* 24440 */ GIR_EraseRootFromParent_Done,
9679 /* 24441 */ // Label 737: @24441
9680 /* 24441 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(24486), // Rule ID 515 //
9681 /* 24446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9682 /* 24449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
9683 /* 24454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9684 /* 24457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9685 /* 24460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9686 /* 24463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9687 /* 24467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9688 /* 24471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9689 /* 24475 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7964:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9690 /* 24475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
9691 /* 24478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9692 /* 24480 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9693 /* 24482 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9694 /* 24484 */ GIR_RootConstrainSelectedInstOperands,
9695 /* 24485 */ // GIR_Coverage, 515,
9696 /* 24485 */ GIR_EraseRootFromParent_Done,
9697 /* 24486 */ // Label 738: @24486
9698 /* 24486 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(24531), // Rule ID 516 //
9699 /* 24491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9700 /* 24494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
9701 /* 24499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9702 /* 24502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9703 /* 24505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9704 /* 24508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9705 /* 24512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9706 /* 24516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9707 /* 24520 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7966:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9708 /* 24520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
9709 /* 24523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9710 /* 24525 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9711 /* 24527 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9712 /* 24529 */ GIR_RootConstrainSelectedInstOperands,
9713 /* 24530 */ // GIR_Coverage, 516,
9714 /* 24530 */ GIR_EraseRootFromParent_Done,
9715 /* 24531 */ // Label 739: @24531
9716 /* 24531 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(24576), // Rule ID 517 //
9717 /* 24536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9718 /* 24539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
9719 /* 24544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9720 /* 24547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9721 /* 24550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9722 /* 24553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9723 /* 24557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9724 /* 24561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9725 /* 24565 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7967:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9726 /* 24565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
9727 /* 24568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9728 /* 24570 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9729 /* 24572 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9730 /* 24574 */ GIR_RootConstrainSelectedInstOperands,
9731 /* 24575 */ // GIR_Coverage, 517,
9732 /* 24575 */ GIR_EraseRootFromParent_Done,
9733 /* 24576 */ // Label 740: @24576
9734 /* 24576 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(24621), // Rule ID 518 //
9735 /* 24581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9736 /* 24584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
9737 /* 24589 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9738 /* 24592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9739 /* 24595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9740 /* 24598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9741 /* 24602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9742 /* 24606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9743 /* 24610 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7965:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9744 /* 24610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
9745 /* 24613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9746 /* 24615 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9747 /* 24617 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9748 /* 24619 */ GIR_RootConstrainSelectedInstOperands,
9749 /* 24620 */ // GIR_Coverage, 518,
9750 /* 24620 */ GIR_EraseRootFromParent_Done,
9751 /* 24621 */ // Label 741: @24621
9752 /* 24621 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(24666), // Rule ID 519 //
9753 /* 24626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9754 /* 24629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9755 /* 24634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9756 /* 24637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9757 /* 24640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9758 /* 24643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9759 /* 24647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9760 /* 24651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9761 /* 24655 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7975:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9762 /* 24655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
9763 /* 24658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9764 /* 24660 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9765 /* 24662 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9766 /* 24664 */ GIR_RootConstrainSelectedInstOperands,
9767 /* 24665 */ // GIR_Coverage, 519,
9768 /* 24665 */ GIR_EraseRootFromParent_Done,
9769 /* 24666 */ // Label 742: @24666
9770 /* 24666 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(24711), // Rule ID 520 //
9771 /* 24671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9772 /* 24674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9773 /* 24679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9774 /* 24682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9775 /* 24685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9776 /* 24688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9777 /* 24692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9778 /* 24696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9779 /* 24700 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7977:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9780 /* 24700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
9781 /* 24703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9782 /* 24705 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9783 /* 24707 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9784 /* 24709 */ GIR_RootConstrainSelectedInstOperands,
9785 /* 24710 */ // GIR_Coverage, 520,
9786 /* 24710 */ GIR_EraseRootFromParent_Done,
9787 /* 24711 */ // Label 743: @24711
9788 /* 24711 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(24756), // Rule ID 521 //
9789 /* 24716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9790 /* 24719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9791 /* 24724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9792 /* 24727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9793 /* 24730 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9794 /* 24733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9795 /* 24737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9796 /* 24741 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9797 /* 24745 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7978:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9798 /* 24745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
9799 /* 24748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9800 /* 24750 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9801 /* 24752 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9802 /* 24754 */ GIR_RootConstrainSelectedInstOperands,
9803 /* 24755 */ // GIR_Coverage, 521,
9804 /* 24755 */ GIR_EraseRootFromParent_Done,
9805 /* 24756 */ // Label 744: @24756
9806 /* 24756 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(24801), // Rule ID 522 //
9807 /* 24761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9808 /* 24764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9809 /* 24769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9810 /* 24772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9811 /* 24775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9812 /* 24778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9813 /* 24782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9814 /* 24786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9815 /* 24790 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7976:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9816 /* 24790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
9817 /* 24793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9818 /* 24795 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9819 /* 24797 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9820 /* 24799 */ GIR_RootConstrainSelectedInstOperands,
9821 /* 24800 */ // GIR_Coverage, 522,
9822 /* 24800 */ GIR_EraseRootFromParent_Done,
9823 /* 24801 */ // Label 745: @24801
9824 /* 24801 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(24846), // Rule ID 523 //
9825 /* 24806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9826 /* 24809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9827 /* 24814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9828 /* 24817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9829 /* 24820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9830 /* 24823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9831 /* 24827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9832 /* 24831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9833 /* 24835 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7979:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9834 /* 24835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
9835 /* 24838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9836 /* 24840 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9837 /* 24842 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9838 /* 24844 */ GIR_RootConstrainSelectedInstOperands,
9839 /* 24845 */ // GIR_Coverage, 523,
9840 /* 24845 */ GIR_EraseRootFromParent_Done,
9841 /* 24846 */ // Label 746: @24846
9842 /* 24846 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(24891), // Rule ID 524 //
9843 /* 24851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9844 /* 24854 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9845 /* 24859 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9846 /* 24862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9847 /* 24865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9848 /* 24868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9849 /* 24872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9850 /* 24876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9851 /* 24880 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7981:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9852 /* 24880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
9853 /* 24883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9854 /* 24885 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9855 /* 24887 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9856 /* 24889 */ GIR_RootConstrainSelectedInstOperands,
9857 /* 24890 */ // GIR_Coverage, 524,
9858 /* 24890 */ GIR_EraseRootFromParent_Done,
9859 /* 24891 */ // Label 747: @24891
9860 /* 24891 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(24936), // Rule ID 525 //
9861 /* 24896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9862 /* 24899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9863 /* 24904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9864 /* 24907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9865 /* 24910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9866 /* 24913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9867 /* 24917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9868 /* 24921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9869 /* 24925 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7982:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9870 /* 24925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
9871 /* 24928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9872 /* 24930 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9873 /* 24932 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9874 /* 24934 */ GIR_RootConstrainSelectedInstOperands,
9875 /* 24935 */ // GIR_Coverage, 525,
9876 /* 24935 */ GIR_EraseRootFromParent_Done,
9877 /* 24936 */ // Label 748: @24936
9878 /* 24936 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(24981), // Rule ID 526 //
9879 /* 24941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9880 /* 24944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9881 /* 24949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9882 /* 24952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9883 /* 24955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9884 /* 24958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9885 /* 24962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9886 /* 24966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9887 /* 24970 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7980:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9888 /* 24970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
9889 /* 24973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9890 /* 24975 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9891 /* 24977 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9892 /* 24979 */ GIR_RootConstrainSelectedInstOperands,
9893 /* 24980 */ // GIR_Coverage, 526,
9894 /* 24980 */ GIR_EraseRootFromParent_Done,
9895 /* 24981 */ // Label 749: @24981
9896 /* 24981 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(25026), // Rule ID 527 //
9897 /* 24986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9898 /* 24989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9899 /* 24994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9900 /* 24997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9901 /* 25000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9902 /* 25003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9903 /* 25007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9904 /* 25011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9905 /* 25015 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7983:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9906 /* 25015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
9907 /* 25018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9908 /* 25020 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9909 /* 25022 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9910 /* 25024 */ GIR_RootConstrainSelectedInstOperands,
9911 /* 25025 */ // GIR_Coverage, 527,
9912 /* 25025 */ GIR_EraseRootFromParent_Done,
9913 /* 25026 */ // Label 750: @25026
9914 /* 25026 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(25071), // Rule ID 528 //
9915 /* 25031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9916 /* 25034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9917 /* 25039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9918 /* 25042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9919 /* 25045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9920 /* 25048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9921 /* 25052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9922 /* 25056 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9923 /* 25060 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7985:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9924 /* 25060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
9925 /* 25063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9926 /* 25065 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9927 /* 25067 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9928 /* 25069 */ GIR_RootConstrainSelectedInstOperands,
9929 /* 25070 */ // GIR_Coverage, 528,
9930 /* 25070 */ GIR_EraseRootFromParent_Done,
9931 /* 25071 */ // Label 751: @25071
9932 /* 25071 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(25116), // Rule ID 529 //
9933 /* 25076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9934 /* 25079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9935 /* 25084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9936 /* 25087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9937 /* 25090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9938 /* 25093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9939 /* 25097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9940 /* 25101 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9941 /* 25105 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7986:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9942 /* 25105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
9943 /* 25108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9944 /* 25110 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9945 /* 25112 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9946 /* 25114 */ GIR_RootConstrainSelectedInstOperands,
9947 /* 25115 */ // GIR_Coverage, 529,
9948 /* 25115 */ GIR_EraseRootFromParent_Done,
9949 /* 25116 */ // Label 752: @25116
9950 /* 25116 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(25161), // Rule ID 530 //
9951 /* 25121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9952 /* 25124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9953 /* 25129 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9954 /* 25132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9955 /* 25135 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9956 /* 25138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9957 /* 25142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9958 /* 25146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9959 /* 25150 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7984:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9960 /* 25150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
9961 /* 25153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9962 /* 25155 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9963 /* 25157 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9964 /* 25159 */ GIR_RootConstrainSelectedInstOperands,
9965 /* 25160 */ // GIR_Coverage, 530,
9966 /* 25160 */ GIR_EraseRootFromParent_Done,
9967 /* 25161 */ // Label 753: @25161
9968 /* 25161 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(25206), // Rule ID 544 //
9969 /* 25166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9970 /* 25169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9971 /* 25174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9972 /* 25177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9973 /* 25180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9974 /* 25183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9975 /* 25187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9976 /* 25191 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9977 /* 25195 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8006:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9978 /* 25195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
9979 /* 25198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9980 /* 25200 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9981 /* 25202 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9982 /* 25204 */ GIR_RootConstrainSelectedInstOperands,
9983 /* 25205 */ // GIR_Coverage, 544,
9984 /* 25205 */ GIR_EraseRootFromParent_Done,
9985 /* 25206 */ // Label 754: @25206
9986 /* 25206 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(25251), // Rule ID 545 //
9987 /* 25211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9988 /* 25214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9989 /* 25219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9990 /* 25222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9991 /* 25225 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9992 /* 25228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9993 /* 25232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9994 /* 25236 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9995 /* 25240 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8008:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9996 /* 25240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
9997 /* 25243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9998 /* 25245 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9999 /* 25247 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10000 /* 25249 */ GIR_RootConstrainSelectedInstOperands,
10001 /* 25250 */ // GIR_Coverage, 545,
10002 /* 25250 */ GIR_EraseRootFromParent_Done,
10003 /* 25251 */ // Label 755: @25251
10004 /* 25251 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(25296), // Rule ID 546 //
10005 /* 25256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10006 /* 25259 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
10007 /* 25264 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10008 /* 25267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10009 /* 25270 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10010 /* 25273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10011 /* 25277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10012 /* 25281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10013 /* 25285 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8009:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10014 /* 25285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
10015 /* 25288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10016 /* 25290 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10017 /* 25292 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10018 /* 25294 */ GIR_RootConstrainSelectedInstOperands,
10019 /* 25295 */ // GIR_Coverage, 546,
10020 /* 25295 */ GIR_EraseRootFromParent_Done,
10021 /* 25296 */ // Label 756: @25296
10022 /* 25296 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(25341), // Rule ID 547 //
10023 /* 25301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10024 /* 25304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
10025 /* 25309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10026 /* 25312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10027 /* 25315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10028 /* 25318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10029 /* 25322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10030 /* 25326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10031 /* 25330 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8007:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10032 /* 25330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
10033 /* 25333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10034 /* 25335 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10035 /* 25337 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10036 /* 25339 */ GIR_RootConstrainSelectedInstOperands,
10037 /* 25340 */ // GIR_Coverage, 547,
10038 /* 25340 */ GIR_EraseRootFromParent_Done,
10039 /* 25341 */ // Label 757: @25341
10040 /* 25341 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(25386), // Rule ID 548 //
10041 /* 25346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10042 /* 25349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
10043 /* 25354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10044 /* 25357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10045 /* 25360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10046 /* 25363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10047 /* 25367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10048 /* 25371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10049 /* 25375 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8010:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10050 /* 25375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
10051 /* 25378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10052 /* 25380 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10053 /* 25382 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10054 /* 25384 */ GIR_RootConstrainSelectedInstOperands,
10055 /* 25385 */ // GIR_Coverage, 548,
10056 /* 25385 */ GIR_EraseRootFromParent_Done,
10057 /* 25386 */ // Label 758: @25386
10058 /* 25386 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(25431), // Rule ID 549 //
10059 /* 25391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10060 /* 25394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
10061 /* 25399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10062 /* 25402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10063 /* 25405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10064 /* 25408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10065 /* 25412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10066 /* 25416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10067 /* 25420 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8012:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10068 /* 25420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
10069 /* 25423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10070 /* 25425 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10071 /* 25427 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10072 /* 25429 */ GIR_RootConstrainSelectedInstOperands,
10073 /* 25430 */ // GIR_Coverage, 549,
10074 /* 25430 */ GIR_EraseRootFromParent_Done,
10075 /* 25431 */ // Label 759: @25431
10076 /* 25431 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(25476), // Rule ID 550 //
10077 /* 25436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10078 /* 25439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
10079 /* 25444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10080 /* 25447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10081 /* 25450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10082 /* 25453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10083 /* 25457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10084 /* 25461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10085 /* 25465 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8013:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10086 /* 25465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
10087 /* 25468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10088 /* 25470 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10089 /* 25472 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10090 /* 25474 */ GIR_RootConstrainSelectedInstOperands,
10091 /* 25475 */ // GIR_Coverage, 550,
10092 /* 25475 */ GIR_EraseRootFromParent_Done,
10093 /* 25476 */ // Label 760: @25476
10094 /* 25476 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(25521), // Rule ID 551 //
10095 /* 25481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10096 /* 25484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
10097 /* 25489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10098 /* 25492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10099 /* 25495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10100 /* 25498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10101 /* 25502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10102 /* 25506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10103 /* 25510 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8011:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10104 /* 25510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
10105 /* 25513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10106 /* 25515 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10107 /* 25517 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10108 /* 25519 */ GIR_RootConstrainSelectedInstOperands,
10109 /* 25520 */ // GIR_Coverage, 551,
10110 /* 25520 */ GIR_EraseRootFromParent_Done,
10111 /* 25521 */ // Label 761: @25521
10112 /* 25521 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(25566), // Rule ID 552 //
10113 /* 25526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10114 /* 25529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
10115 /* 25534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10116 /* 25537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10117 /* 25540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10118 /* 25543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10119 /* 25547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10120 /* 25551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10121 /* 25555 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8014:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10122 /* 25555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
10123 /* 25558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10124 /* 25560 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10125 /* 25562 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10126 /* 25564 */ GIR_RootConstrainSelectedInstOperands,
10127 /* 25565 */ // GIR_Coverage, 552,
10128 /* 25565 */ GIR_EraseRootFromParent_Done,
10129 /* 25566 */ // Label 762: @25566
10130 /* 25566 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(25611), // Rule ID 553 //
10131 /* 25571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10132 /* 25574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
10133 /* 25579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10134 /* 25582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10135 /* 25585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10136 /* 25588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10137 /* 25592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10138 /* 25596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10139 /* 25600 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8016:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10140 /* 25600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
10141 /* 25603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10142 /* 25605 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10143 /* 25607 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10144 /* 25609 */ GIR_RootConstrainSelectedInstOperands,
10145 /* 25610 */ // GIR_Coverage, 553,
10146 /* 25610 */ GIR_EraseRootFromParent_Done,
10147 /* 25611 */ // Label 763: @25611
10148 /* 25611 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(25656), // Rule ID 554 //
10149 /* 25616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10150 /* 25619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
10151 /* 25624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10152 /* 25627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10153 /* 25630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10154 /* 25633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10155 /* 25637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10156 /* 25641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10157 /* 25645 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8017:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10158 /* 25645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
10159 /* 25648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10160 /* 25650 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10161 /* 25652 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10162 /* 25654 */ GIR_RootConstrainSelectedInstOperands,
10163 /* 25655 */ // GIR_Coverage, 554,
10164 /* 25655 */ GIR_EraseRootFromParent_Done,
10165 /* 25656 */ // Label 764: @25656
10166 /* 25656 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(25701), // Rule ID 555 //
10167 /* 25661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10168 /* 25664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
10169 /* 25669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10170 /* 25672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10171 /* 25675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10172 /* 25678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10173 /* 25682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10174 /* 25686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10175 /* 25690 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8015:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10176 /* 25690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
10177 /* 25693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10178 /* 25695 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10179 /* 25697 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10180 /* 25699 */ GIR_RootConstrainSelectedInstOperands,
10181 /* 25700 */ // GIR_Coverage, 555,
10182 /* 25700 */ GIR_EraseRootFromParent_Done,
10183 /* 25701 */ // Label 765: @25701
10184 /* 25701 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(25746), // Rule ID 556 //
10185 /* 25706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10186 /* 25709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
10187 /* 25714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10188 /* 25717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10189 /* 25720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10190 /* 25723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10191 /* 25727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10192 /* 25731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10193 /* 25735 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8018:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10194 /* 25735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
10195 /* 25738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10196 /* 25740 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10197 /* 25742 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10198 /* 25744 */ GIR_RootConstrainSelectedInstOperands,
10199 /* 25745 */ // GIR_Coverage, 556,
10200 /* 25745 */ GIR_EraseRootFromParent_Done,
10201 /* 25746 */ // Label 766: @25746
10202 /* 25746 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(25791), // Rule ID 557 //
10203 /* 25751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10204 /* 25754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
10205 /* 25759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10206 /* 25762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10207 /* 25765 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10208 /* 25768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10209 /* 25772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10210 /* 25776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10211 /* 25780 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8020:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10212 /* 25780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
10213 /* 25783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10214 /* 25785 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10215 /* 25787 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10216 /* 25789 */ GIR_RootConstrainSelectedInstOperands,
10217 /* 25790 */ // GIR_Coverage, 557,
10218 /* 25790 */ GIR_EraseRootFromParent_Done,
10219 /* 25791 */ // Label 767: @25791
10220 /* 25791 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(25836), // Rule ID 558 //
10221 /* 25796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10222 /* 25799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
10223 /* 25804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10224 /* 25807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10225 /* 25810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10226 /* 25813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10227 /* 25817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10228 /* 25821 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10229 /* 25825 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8021:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10230 /* 25825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
10231 /* 25828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10232 /* 25830 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10233 /* 25832 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10234 /* 25834 */ GIR_RootConstrainSelectedInstOperands,
10235 /* 25835 */ // GIR_Coverage, 558,
10236 /* 25835 */ GIR_EraseRootFromParent_Done,
10237 /* 25836 */ // Label 768: @25836
10238 /* 25836 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(25881), // Rule ID 559 //
10239 /* 25841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10240 /* 25844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
10241 /* 25849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10242 /* 25852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10243 /* 25855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10244 /* 25858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10245 /* 25862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10246 /* 25866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10247 /* 25870 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8019:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10248 /* 25870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
10249 /* 25873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10250 /* 25875 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10251 /* 25877 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10252 /* 25879 */ GIR_RootConstrainSelectedInstOperands,
10253 /* 25880 */ // GIR_Coverage, 559,
10254 /* 25880 */ GIR_EraseRootFromParent_Done,
10255 /* 25881 */ // Label 769: @25881
10256 /* 25881 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(25926), // Rule ID 560 //
10257 /* 25886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10258 /* 25889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
10259 /* 25894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10260 /* 25897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10261 /* 25900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10262 /* 25903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10263 /* 25907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10264 /* 25911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10265 /* 25915 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8022:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10266 /* 25915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
10267 /* 25918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10268 /* 25920 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10269 /* 25922 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10270 /* 25924 */ GIR_RootConstrainSelectedInstOperands,
10271 /* 25925 */ // GIR_Coverage, 560,
10272 /* 25925 */ GIR_EraseRootFromParent_Done,
10273 /* 25926 */ // Label 770: @25926
10274 /* 25926 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(25971), // Rule ID 561 //
10275 /* 25931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10276 /* 25934 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
10277 /* 25939 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10278 /* 25942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10279 /* 25945 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10280 /* 25948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10281 /* 25952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10282 /* 25956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10283 /* 25960 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8024:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10284 /* 25960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
10285 /* 25963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10286 /* 25965 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10287 /* 25967 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10288 /* 25969 */ GIR_RootConstrainSelectedInstOperands,
10289 /* 25970 */ // GIR_Coverage, 561,
10290 /* 25970 */ GIR_EraseRootFromParent_Done,
10291 /* 25971 */ // Label 771: @25971
10292 /* 25971 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(26016), // Rule ID 562 //
10293 /* 25976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10294 /* 25979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
10295 /* 25984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10296 /* 25987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10297 /* 25990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10298 /* 25993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10299 /* 25997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10300 /* 26001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10301 /* 26005 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8025:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10302 /* 26005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
10303 /* 26008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10304 /* 26010 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10305 /* 26012 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10306 /* 26014 */ GIR_RootConstrainSelectedInstOperands,
10307 /* 26015 */ // GIR_Coverage, 562,
10308 /* 26015 */ GIR_EraseRootFromParent_Done,
10309 /* 26016 */ // Label 772: @26016
10310 /* 26016 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(26061), // Rule ID 563 //
10311 /* 26021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10312 /* 26024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
10313 /* 26029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10314 /* 26032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10315 /* 26035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10316 /* 26038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10317 /* 26042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10318 /* 26046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10319 /* 26050 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8023:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10320 /* 26050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
10321 /* 26053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10322 /* 26055 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10323 /* 26057 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10324 /* 26059 */ GIR_RootConstrainSelectedInstOperands,
10325 /* 26060 */ // GIR_Coverage, 563,
10326 /* 26060 */ GIR_EraseRootFromParent_Done,
10327 /* 26061 */ // Label 773: @26061
10328 /* 26061 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(26106), // Rule ID 564 //
10329 /* 26066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10330 /* 26069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
10331 /* 26074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10332 /* 26077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10333 /* 26080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10334 /* 26083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10335 /* 26087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10336 /* 26091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10337 /* 26095 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8026:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10338 /* 26095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
10339 /* 26098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10340 /* 26100 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10341 /* 26102 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10342 /* 26104 */ GIR_RootConstrainSelectedInstOperands,
10343 /* 26105 */ // GIR_Coverage, 564,
10344 /* 26105 */ GIR_EraseRootFromParent_Done,
10345 /* 26106 */ // Label 774: @26106
10346 /* 26106 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(26151), // Rule ID 565 //
10347 /* 26111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10348 /* 26114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
10349 /* 26119 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10350 /* 26122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10351 /* 26125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10352 /* 26128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10353 /* 26132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10354 /* 26136 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10355 /* 26140 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8028:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10356 /* 26140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
10357 /* 26143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10358 /* 26145 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10359 /* 26147 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10360 /* 26149 */ GIR_RootConstrainSelectedInstOperands,
10361 /* 26150 */ // GIR_Coverage, 565,
10362 /* 26150 */ GIR_EraseRootFromParent_Done,
10363 /* 26151 */ // Label 775: @26151
10364 /* 26151 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(26196), // Rule ID 566 //
10365 /* 26156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10366 /* 26159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
10367 /* 26164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10368 /* 26167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10369 /* 26170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10370 /* 26173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10371 /* 26177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10372 /* 26181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10373 /* 26185 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8029:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10374 /* 26185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
10375 /* 26188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10376 /* 26190 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10377 /* 26192 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10378 /* 26194 */ GIR_RootConstrainSelectedInstOperands,
10379 /* 26195 */ // GIR_Coverage, 566,
10380 /* 26195 */ GIR_EraseRootFromParent_Done,
10381 /* 26196 */ // Label 776: @26196
10382 /* 26196 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(26241), // Rule ID 567 //
10383 /* 26201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10384 /* 26204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
10385 /* 26209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10386 /* 26212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10387 /* 26215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10388 /* 26218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10389 /* 26222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10390 /* 26226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10391 /* 26230 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8027:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10392 /* 26230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
10393 /* 26233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10394 /* 26235 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10395 /* 26237 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10396 /* 26239 */ GIR_RootConstrainSelectedInstOperands,
10397 /* 26240 */ // GIR_Coverage, 567,
10398 /* 26240 */ GIR_EraseRootFromParent_Done,
10399 /* 26241 */ // Label 777: @26241
10400 /* 26241 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(26286), // Rule ID 676 //
10401 /* 26246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10402 /* 26249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
10403 /* 26254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10404 /* 26257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10405 /* 26260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10406 /* 26263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10407 /* 26267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10408 /* 26271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10409 /* 26275 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8161:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10410 /* 26275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
10411 /* 26278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10412 /* 26280 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10413 /* 26282 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10414 /* 26284 */ GIR_RootConstrainSelectedInstOperands,
10415 /* 26285 */ // GIR_Coverage, 676,
10416 /* 26285 */ GIR_EraseRootFromParent_Done,
10417 /* 26286 */ // Label 778: @26286
10418 /* 26286 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(26331), // Rule ID 677 //
10419 /* 26291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10420 /* 26294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
10421 /* 26299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10422 /* 26302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10423 /* 26305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10424 /* 26308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10425 /* 26312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10426 /* 26316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10427 /* 26320 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8162:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10428 /* 26320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
10429 /* 26323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10430 /* 26325 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10431 /* 26327 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10432 /* 26329 */ GIR_RootConstrainSelectedInstOperands,
10433 /* 26330 */ // GIR_Coverage, 677,
10434 /* 26330 */ GIR_EraseRootFromParent_Done,
10435 /* 26331 */ // Label 779: @26331
10436 /* 26331 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(26376), // Rule ID 678 //
10437 /* 26336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10438 /* 26339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
10439 /* 26344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10440 /* 26347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10441 /* 26350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10442 /* 26353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10443 /* 26357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10444 /* 26361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10445 /* 26365 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10446 /* 26365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
10447 /* 26368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10448 /* 26370 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10449 /* 26372 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10450 /* 26374 */ GIR_RootConstrainSelectedInstOperands,
10451 /* 26375 */ // GIR_Coverage, 678,
10452 /* 26375 */ GIR_EraseRootFromParent_Done,
10453 /* 26376 */ // Label 780: @26376
10454 /* 26376 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(26421), // Rule ID 679 //
10455 /* 26381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10456 /* 26384 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
10457 /* 26389 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10458 /* 26392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10459 /* 26395 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10460 /* 26398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10461 /* 26402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10462 /* 26406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10463 /* 26410 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8164:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10464 /* 26410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
10465 /* 26413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10466 /* 26415 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10467 /* 26417 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10468 /* 26419 */ GIR_RootConstrainSelectedInstOperands,
10469 /* 26420 */ // GIR_Coverage, 679,
10470 /* 26420 */ GIR_EraseRootFromParent_Done,
10471 /* 26421 */ // Label 781: @26421
10472 /* 26421 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(26466), // Rule ID 680 //
10473 /* 26426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10474 /* 26429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
10475 /* 26434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10476 /* 26437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10477 /* 26440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10478 /* 26443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10479 /* 26447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10480 /* 26451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10481 /* 26455 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8165:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10482 /* 26455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
10483 /* 26458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10484 /* 26460 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10485 /* 26462 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10486 /* 26464 */ GIR_RootConstrainSelectedInstOperands,
10487 /* 26465 */ // GIR_Coverage, 680,
10488 /* 26465 */ GIR_EraseRootFromParent_Done,
10489 /* 26466 */ // Label 782: @26466
10490 /* 26466 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(26511), // Rule ID 681 //
10491 /* 26471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10492 /* 26474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
10493 /* 26479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10494 /* 26482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10495 /* 26485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10496 /* 26488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10497 /* 26492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10498 /* 26496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10499 /* 26500 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8163:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10500 /* 26500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
10501 /* 26503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10502 /* 26505 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10503 /* 26507 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10504 /* 26509 */ GIR_RootConstrainSelectedInstOperands,
10505 /* 26510 */ // GIR_Coverage, 681,
10506 /* 26510 */ GIR_EraseRootFromParent_Done,
10507 /* 26511 */ // Label 783: @26511
10508 /* 26511 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(26556), // Rule ID 696 //
10509 /* 26516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10510 /* 26519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
10511 /* 26524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10512 /* 26527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10513 /* 26530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10514 /* 26533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10515 /* 26537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10516 /* 26541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10517 /* 26545 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10518 /* 26545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
10519 /* 26548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10520 /* 26550 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10521 /* 26552 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10522 /* 26554 */ GIR_RootConstrainSelectedInstOperands,
10523 /* 26555 */ // GIR_Coverage, 696,
10524 /* 26555 */ GIR_EraseRootFromParent_Done,
10525 /* 26556 */ // Label 784: @26556
10526 /* 26556 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(26601), // Rule ID 697 //
10527 /* 26561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10528 /* 26564 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
10529 /* 26569 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10530 /* 26572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10531 /* 26575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10532 /* 26578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10533 /* 26582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10534 /* 26586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10535 /* 26590 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8202:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10536 /* 26590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
10537 /* 26593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10538 /* 26595 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10539 /* 26597 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10540 /* 26599 */ GIR_RootConstrainSelectedInstOperands,
10541 /* 26600 */ // GIR_Coverage, 697,
10542 /* 26600 */ GIR_EraseRootFromParent_Done,
10543 /* 26601 */ // Label 785: @26601
10544 /* 26601 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(26646), // Rule ID 722 //
10545 /* 26606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10546 /* 26609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
10547 /* 26614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10548 /* 26617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10549 /* 26620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10550 /* 26623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10551 /* 26627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10552 /* 26631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10553 /* 26635 */ // (intrinsic_wo_chain:{ *:[v8f16] } 8228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10554 /* 26635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
10555 /* 26638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10556 /* 26640 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10557 /* 26642 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10558 /* 26644 */ GIR_RootConstrainSelectedInstOperands,
10559 /* 26645 */ // GIR_Coverage, 722,
10560 /* 26645 */ GIR_EraseRootFromParent_Done,
10561 /* 26646 */ // Label 786: @26646
10562 /* 26646 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(26691), // Rule ID 723 //
10563 /* 26651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10564 /* 26654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
10565 /* 26659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10566 /* 26662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10567 /* 26665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10568 /* 26668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10569 /* 26672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10570 /* 26676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10571 /* 26680 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10572 /* 26680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
10573 /* 26683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10574 /* 26685 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10575 /* 26687 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10576 /* 26689 */ GIR_RootConstrainSelectedInstOperands,
10577 /* 26690 */ // GIR_Coverage, 723,
10578 /* 26690 */ GIR_EraseRootFromParent_Done,
10579 /* 26691 */ // Label 787: @26691
10580 /* 26691 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(26736), // Rule ID 750 //
10581 /* 26696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10582 /* 26699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
10583 /* 26704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10584 /* 26707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10585 /* 26710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10586 /* 26713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10587 /* 26717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10588 /* 26721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10589 /* 26725 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8255:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10590 /* 26725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
10591 /* 26728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10592 /* 26730 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10593 /* 26732 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10594 /* 26734 */ GIR_RootConstrainSelectedInstOperands,
10595 /* 26735 */ // GIR_Coverage, 750,
10596 /* 26735 */ GIR_EraseRootFromParent_Done,
10597 /* 26736 */ // Label 788: @26736
10598 /* 26736 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(26781), // Rule ID 751 //
10599 /* 26741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10600 /* 26744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
10601 /* 26749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10602 /* 26752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10603 /* 26755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10604 /* 26758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10605 /* 26762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10606 /* 26766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10607 /* 26770 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8254:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10608 /* 26770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
10609 /* 26773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10610 /* 26775 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10611 /* 26777 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10612 /* 26779 */ GIR_RootConstrainSelectedInstOperands,
10613 /* 26780 */ // GIR_Coverage, 751,
10614 /* 26780 */ GIR_EraseRootFromParent_Done,
10615 /* 26781 */ // Label 789: @26781
10616 /* 26781 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(26826), // Rule ID 752 //
10617 /* 26786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10618 /* 26789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
10619 /* 26794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10620 /* 26797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10621 /* 26800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10622 /* 26803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10623 /* 26807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10624 /* 26811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10625 /* 26815 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10626 /* 26815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
10627 /* 26818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10628 /* 26820 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10629 /* 26822 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10630 /* 26824 */ GIR_RootConstrainSelectedInstOperands,
10631 /* 26825 */ // GIR_Coverage, 752,
10632 /* 26825 */ GIR_EraseRootFromParent_Done,
10633 /* 26826 */ // Label 790: @26826
10634 /* 26826 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(26871), // Rule ID 753 //
10635 /* 26831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10636 /* 26834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
10637 /* 26839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10638 /* 26842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10639 /* 26845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10640 /* 26848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10641 /* 26852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10642 /* 26856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10643 /* 26860 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8252:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10644 /* 26860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
10645 /* 26863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10646 /* 26865 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10647 /* 26867 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10648 /* 26869 */ GIR_RootConstrainSelectedInstOperands,
10649 /* 26870 */ // GIR_Coverage, 753,
10650 /* 26870 */ GIR_EraseRootFromParent_Done,
10651 /* 26871 */ // Label 791: @26871
10652 /* 26871 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(26916), // Rule ID 754 //
10653 /* 26876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10654 /* 26879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
10655 /* 26884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10656 /* 26887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10657 /* 26890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10658 /* 26893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10659 /* 26897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10660 /* 26901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10661 /* 26905 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8259:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10662 /* 26905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
10663 /* 26908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10664 /* 26910 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10665 /* 26912 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10666 /* 26914 */ GIR_RootConstrainSelectedInstOperands,
10667 /* 26915 */ // GIR_Coverage, 754,
10668 /* 26915 */ GIR_EraseRootFromParent_Done,
10669 /* 26916 */ // Label 792: @26916
10670 /* 26916 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(26961), // Rule ID 755 //
10671 /* 26921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10672 /* 26924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
10673 /* 26929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10674 /* 26932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10675 /* 26935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10676 /* 26938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10677 /* 26942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10678 /* 26946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10679 /* 26950 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8258:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10680 /* 26950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
10681 /* 26953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10682 /* 26955 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10683 /* 26957 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10684 /* 26959 */ GIR_RootConstrainSelectedInstOperands,
10685 /* 26960 */ // GIR_Coverage, 755,
10686 /* 26960 */ GIR_EraseRootFromParent_Done,
10687 /* 26961 */ // Label 793: @26961
10688 /* 26961 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(27006), // Rule ID 756 //
10689 /* 26966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10690 /* 26969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
10691 /* 26974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10692 /* 26977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10693 /* 26980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10694 /* 26983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10695 /* 26987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10696 /* 26991 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10697 /* 26995 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8257:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10698 /* 26995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
10699 /* 26998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10700 /* 27000 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10701 /* 27002 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10702 /* 27004 */ GIR_RootConstrainSelectedInstOperands,
10703 /* 27005 */ // GIR_Coverage, 756,
10704 /* 27005 */ GIR_EraseRootFromParent_Done,
10705 /* 27006 */ // Label 794: @27006
10706 /* 27006 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(27051), // Rule ID 757 //
10707 /* 27011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10708 /* 27014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
10709 /* 27019 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10710 /* 27022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10711 /* 27025 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10712 /* 27028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10713 /* 27032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10714 /* 27036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10715 /* 27040 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8256:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10716 /* 27040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
10717 /* 27043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10718 /* 27045 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10719 /* 27047 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10720 /* 27049 */ GIR_RootConstrainSelectedInstOperands,
10721 /* 27050 */ // GIR_Coverage, 757,
10722 /* 27050 */ GIR_EraseRootFromParent_Done,
10723 /* 27051 */ // Label 795: @27051
10724 /* 27051 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(27096), // Rule ID 768 //
10725 /* 27056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10726 /* 27059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
10727 /* 27064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10728 /* 27067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10729 /* 27070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10730 /* 27073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10731 /* 27077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10732 /* 27081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10733 /* 27085 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10734 /* 27085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
10735 /* 27088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10736 /* 27090 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10737 /* 27092 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10738 /* 27094 */ GIR_RootConstrainSelectedInstOperands,
10739 /* 27095 */ // GIR_Coverage, 768,
10740 /* 27095 */ GIR_EraseRootFromParent_Done,
10741 /* 27096 */ // Label 796: @27096
10742 /* 27096 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(27141), // Rule ID 769 //
10743 /* 27101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10744 /* 27104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
10745 /* 27109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10746 /* 27112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10747 /* 27115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10748 /* 27118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10749 /* 27122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10750 /* 27126 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10751 /* 27130 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8270:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10752 /* 27130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
10753 /* 27133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10754 /* 27135 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10755 /* 27137 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10756 /* 27139 */ GIR_RootConstrainSelectedInstOperands,
10757 /* 27140 */ // GIR_Coverage, 769,
10758 /* 27140 */ GIR_EraseRootFromParent_Done,
10759 /* 27141 */ // Label 797: @27141
10760 /* 27141 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(27186), // Rule ID 770 //
10761 /* 27146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10762 /* 27149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
10763 /* 27154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10764 /* 27157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10765 /* 27160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10766 /* 27163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10767 /* 27167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10768 /* 27171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10769 /* 27175 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8273:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10770 /* 27175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
10771 /* 27178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10772 /* 27180 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10773 /* 27182 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10774 /* 27184 */ GIR_RootConstrainSelectedInstOperands,
10775 /* 27185 */ // GIR_Coverage, 770,
10776 /* 27185 */ GIR_EraseRootFromParent_Done,
10777 /* 27186 */ // Label 798: @27186
10778 /* 27186 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(27231), // Rule ID 771 //
10779 /* 27191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10780 /* 27194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
10781 /* 27199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10782 /* 27202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10783 /* 27205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10784 /* 27208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10785 /* 27212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10786 /* 27216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10787 /* 27220 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8272:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10788 /* 27220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
10789 /* 27223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10790 /* 27225 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10791 /* 27227 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10792 /* 27229 */ GIR_RootConstrainSelectedInstOperands,
10793 /* 27230 */ // GIR_Coverage, 771,
10794 /* 27230 */ GIR_EraseRootFromParent_Done,
10795 /* 27231 */ // Label 799: @27231
10796 /* 27231 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(27276), // Rule ID 772 //
10797 /* 27236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10798 /* 27239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
10799 /* 27244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10800 /* 27247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10801 /* 27250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10802 /* 27253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10803 /* 27257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10804 /* 27261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10805 /* 27265 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8275:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10806 /* 27265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
10807 /* 27268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10808 /* 27270 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10809 /* 27272 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10810 /* 27274 */ GIR_RootConstrainSelectedInstOperands,
10811 /* 27275 */ // GIR_Coverage, 772,
10812 /* 27275 */ GIR_EraseRootFromParent_Done,
10813 /* 27276 */ // Label 800: @27276
10814 /* 27276 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(27321), // Rule ID 773 //
10815 /* 27281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10816 /* 27284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
10817 /* 27289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10818 /* 27292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10819 /* 27295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10820 /* 27298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10821 /* 27302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10822 /* 27306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10823 /* 27310 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10824 /* 27310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
10825 /* 27313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10826 /* 27315 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10827 /* 27317 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10828 /* 27319 */ GIR_RootConstrainSelectedInstOperands,
10829 /* 27320 */ // GIR_Coverage, 773,
10830 /* 27320 */ GIR_EraseRootFromParent_Done,
10831 /* 27321 */ // Label 801: @27321
10832 /* 27321 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(27366), // Rule ID 774 //
10833 /* 27326 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10834 /* 27329 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
10835 /* 27334 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10836 /* 27337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10837 /* 27340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10838 /* 27343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10839 /* 27347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10840 /* 27351 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10841 /* 27355 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10842 /* 27355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
10843 /* 27358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10844 /* 27360 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10845 /* 27362 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10846 /* 27364 */ GIR_RootConstrainSelectedInstOperands,
10847 /* 27365 */ // GIR_Coverage, 774,
10848 /* 27365 */ GIR_EraseRootFromParent_Done,
10849 /* 27366 */ // Label 802: @27366
10850 /* 27366 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(27411), // Rule ID 775 //
10851 /* 27371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10852 /* 27374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
10853 /* 27379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10854 /* 27382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10855 /* 27385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10856 /* 27388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10857 /* 27392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10858 /* 27396 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10859 /* 27400 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8276:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10860 /* 27400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
10861 /* 27403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10862 /* 27405 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10863 /* 27407 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10864 /* 27409 */ GIR_RootConstrainSelectedInstOperands,
10865 /* 27410 */ // GIR_Coverage, 775,
10866 /* 27410 */ GIR_EraseRootFromParent_Done,
10867 /* 27411 */ // Label 803: @27411
10868 /* 27411 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(27456), // Rule ID 776 //
10869 /* 27416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10870 /* 27419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
10871 /* 27424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10872 /* 27427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10873 /* 27430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10874 /* 27433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10875 /* 27437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10876 /* 27441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10877 /* 27445 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8279:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10878 /* 27445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
10879 /* 27448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10880 /* 27450 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10881 /* 27452 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10882 /* 27454 */ GIR_RootConstrainSelectedInstOperands,
10883 /* 27455 */ // GIR_Coverage, 776,
10884 /* 27455 */ GIR_EraseRootFromParent_Done,
10885 /* 27456 */ // Label 804: @27456
10886 /* 27456 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(27501), // Rule ID 777 //
10887 /* 27461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10888 /* 27464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
10889 /* 27469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10890 /* 27472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10891 /* 27475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10892 /* 27478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10893 /* 27482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10894 /* 27486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10895 /* 27490 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10896 /* 27490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
10897 /* 27493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10898 /* 27495 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10899 /* 27497 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10900 /* 27499 */ GIR_RootConstrainSelectedInstOperands,
10901 /* 27500 */ // GIR_Coverage, 777,
10902 /* 27500 */ GIR_EraseRootFromParent_Done,
10903 /* 27501 */ // Label 805: @27501
10904 /* 27501 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(27546), // Rule ID 778 //
10905 /* 27506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10906 /* 27509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
10907 /* 27514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10908 /* 27517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10909 /* 27520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10910 /* 27523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10911 /* 27527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10912 /* 27531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10913 /* 27535 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8281:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10914 /* 27535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
10915 /* 27538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10916 /* 27540 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10917 /* 27542 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10918 /* 27544 */ GIR_RootConstrainSelectedInstOperands,
10919 /* 27545 */ // GIR_Coverage, 778,
10920 /* 27545 */ GIR_EraseRootFromParent_Done,
10921 /* 27546 */ // Label 806: @27546
10922 /* 27546 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(27591), // Rule ID 779 //
10923 /* 27551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10924 /* 27554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
10925 /* 27559 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10926 /* 27562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10927 /* 27565 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10928 /* 27568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10929 /* 27572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10930 /* 27576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10931 /* 27580 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8280:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10932 /* 27580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
10933 /* 27583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10934 /* 27585 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10935 /* 27587 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10936 /* 27589 */ GIR_RootConstrainSelectedInstOperands,
10937 /* 27590 */ // GIR_Coverage, 779,
10938 /* 27590 */ GIR_EraseRootFromParent_Done,
10939 /* 27591 */ // Label 807: @27591
10940 /* 27591 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(27636), // Rule ID 784 //
10941 /* 27596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10942 /* 27599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10943 /* 27604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10944 /* 27607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10945 /* 27610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10946 /* 27613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10947 /* 27617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10948 /* 27621 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10949 /* 27625 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8287:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10950 /* 27625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
10951 /* 27628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10952 /* 27630 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10953 /* 27632 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10954 /* 27634 */ GIR_RootConstrainSelectedInstOperands,
10955 /* 27635 */ // GIR_Coverage, 784,
10956 /* 27635 */ GIR_EraseRootFromParent_Done,
10957 /* 27636 */ // Label 808: @27636
10958 /* 27636 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(27681), // Rule ID 785 //
10959 /* 27641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10960 /* 27644 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10961 /* 27649 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10962 /* 27652 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10963 /* 27655 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10964 /* 27658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10965 /* 27662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10966 /* 27666 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10967 /* 27670 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10968 /* 27670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
10969 /* 27673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10970 /* 27675 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10971 /* 27677 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10972 /* 27679 */ GIR_RootConstrainSelectedInstOperands,
10973 /* 27680 */ // GIR_Coverage, 785,
10974 /* 27680 */ GIR_EraseRootFromParent_Done,
10975 /* 27681 */ // Label 809: @27681
10976 /* 27681 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(27726), // Rule ID 786 //
10977 /* 27686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10978 /* 27689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
10979 /* 27694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10980 /* 27697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10981 /* 27700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10982 /* 27703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10983 /* 27707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10984 /* 27711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10985 /* 27715 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8289:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10986 /* 27715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
10987 /* 27718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10988 /* 27720 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10989 /* 27722 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10990 /* 27724 */ GIR_RootConstrainSelectedInstOperands,
10991 /* 27725 */ // GIR_Coverage, 786,
10992 /* 27725 */ GIR_EraseRootFromParent_Done,
10993 /* 27726 */ // Label 810: @27726
10994 /* 27726 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(27771), // Rule ID 787 //
10995 /* 27731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10996 /* 27734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
10997 /* 27739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10998 /* 27742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10999 /* 27745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11000 /* 27748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11001 /* 27752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11002 /* 27756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11003 /* 27760 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8288:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11004 /* 27760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
11005 /* 27763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11006 /* 27765 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11007 /* 27767 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11008 /* 27769 */ GIR_RootConstrainSelectedInstOperands,
11009 /* 27770 */ // GIR_Coverage, 787,
11010 /* 27770 */ GIR_EraseRootFromParent_Done,
11011 /* 27771 */ // Label 811: @27771
11012 /* 27771 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(27816), // Rule ID 788 //
11013 /* 27776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11014 /* 27779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
11015 /* 27784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11016 /* 27787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11017 /* 27790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11018 /* 27793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11019 /* 27797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11020 /* 27801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11021 /* 27805 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8291:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11022 /* 27805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
11023 /* 27808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11024 /* 27810 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11025 /* 27812 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11026 /* 27814 */ GIR_RootConstrainSelectedInstOperands,
11027 /* 27815 */ // GIR_Coverage, 788,
11028 /* 27815 */ GIR_EraseRootFromParent_Done,
11029 /* 27816 */ // Label 812: @27816
11030 /* 27816 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(27861), // Rule ID 789 //
11031 /* 27821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11032 /* 27824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
11033 /* 27829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11034 /* 27832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11035 /* 27835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11036 /* 27838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11037 /* 27842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11038 /* 27846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11039 /* 27850 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8290:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11040 /* 27850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
11041 /* 27853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11042 /* 27855 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11043 /* 27857 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11044 /* 27859 */ GIR_RootConstrainSelectedInstOperands,
11045 /* 27860 */ // GIR_Coverage, 789,
11046 /* 27860 */ GIR_EraseRootFromParent_Done,
11047 /* 27861 */ // Label 813: @27861
11048 /* 27861 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(27906), // Rule ID 790 //
11049 /* 27866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11050 /* 27869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
11051 /* 27874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11052 /* 27877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11053 /* 27880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11054 /* 27883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11055 /* 27887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11056 /* 27891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11057 /* 27895 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8293:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11058 /* 27895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
11059 /* 27898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11060 /* 27900 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11061 /* 27902 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11062 /* 27904 */ GIR_RootConstrainSelectedInstOperands,
11063 /* 27905 */ // GIR_Coverage, 790,
11064 /* 27905 */ GIR_EraseRootFromParent_Done,
11065 /* 27906 */ // Label 814: @27906
11066 /* 27906 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(27951), // Rule ID 791 //
11067 /* 27911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11068 /* 27914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
11069 /* 27919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11070 /* 27922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11071 /* 27925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11072 /* 27928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11073 /* 27932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11074 /* 27936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11075 /* 27940 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8292:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11076 /* 27940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
11077 /* 27943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11078 /* 27945 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11079 /* 27947 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11080 /* 27949 */ GIR_RootConstrainSelectedInstOperands,
11081 /* 27950 */ // GIR_Coverage, 791,
11082 /* 27950 */ GIR_EraseRootFromParent_Done,
11083 /* 27951 */ // Label 815: @27951
11084 /* 27951 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(27996), // Rule ID 792 //
11085 /* 27956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11086 /* 27959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
11087 /* 27964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11088 /* 27967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11089 /* 27970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11090 /* 27973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11091 /* 27977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11092 /* 27981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11093 /* 27985 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8295:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11094 /* 27985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
11095 /* 27988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11096 /* 27990 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11097 /* 27992 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11098 /* 27994 */ GIR_RootConstrainSelectedInstOperands,
11099 /* 27995 */ // GIR_Coverage, 792,
11100 /* 27995 */ GIR_EraseRootFromParent_Done,
11101 /* 27996 */ // Label 816: @27996
11102 /* 27996 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(28041), // Rule ID 793 //
11103 /* 28001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11104 /* 28004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
11105 /* 28009 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11106 /* 28012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11107 /* 28015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11108 /* 28018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11109 /* 28022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11110 /* 28026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11111 /* 28030 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11112 /* 28030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
11113 /* 28033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11114 /* 28035 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11115 /* 28037 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11116 /* 28039 */ GIR_RootConstrainSelectedInstOperands,
11117 /* 28040 */ // GIR_Coverage, 793,
11118 /* 28040 */ GIR_EraseRootFromParent_Done,
11119 /* 28041 */ // Label 817: @28041
11120 /* 28041 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(28086), // Rule ID 798 //
11121 /* 28046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11122 /* 28049 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
11123 /* 28054 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11124 /* 28057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11125 /* 28060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11126 /* 28063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11127 /* 28067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11128 /* 28071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11129 /* 28075 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8300:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
11130 /* 28075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
11131 /* 28078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11132 /* 28080 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11133 /* 28082 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11134 /* 28084 */ GIR_RootConstrainSelectedInstOperands,
11135 /* 28085 */ // GIR_Coverage, 798,
11136 /* 28085 */ GIR_EraseRootFromParent_Done,
11137 /* 28086 */ // Label 818: @28086
11138 /* 28086 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(28131), // Rule ID 799 //
11139 /* 28091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11140 /* 28094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
11141 /* 28099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11142 /* 28102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11143 /* 28105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11144 /* 28108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11145 /* 28112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11146 /* 28116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11147 /* 28120 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8301:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
11148 /* 28120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
11149 /* 28123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11150 /* 28125 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11151 /* 28127 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11152 /* 28129 */ GIR_RootConstrainSelectedInstOperands,
11153 /* 28130 */ // GIR_Coverage, 799,
11154 /* 28130 */ GIR_EraseRootFromParent_Done,
11155 /* 28131 */ // Label 819: @28131
11156 /* 28131 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(28176), // Rule ID 804 //
11157 /* 28136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11158 /* 28139 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
11159 /* 28144 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11160 /* 28147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11161 /* 28150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11162 /* 28153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11163 /* 28157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11164 /* 28161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11165 /* 28165 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8307:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11166 /* 28165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
11167 /* 28168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11168 /* 28170 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11169 /* 28172 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11170 /* 28174 */ GIR_RootConstrainSelectedInstOperands,
11171 /* 28175 */ // GIR_Coverage, 804,
11172 /* 28175 */ GIR_EraseRootFromParent_Done,
11173 /* 28176 */ // Label 820: @28176
11174 /* 28176 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(28221), // Rule ID 805 //
11175 /* 28181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11176 /* 28184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
11177 /* 28189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11178 /* 28192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11179 /* 28195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11180 /* 28198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11181 /* 28202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11182 /* 28206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11183 /* 28210 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8308:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11184 /* 28210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
11185 /* 28213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11186 /* 28215 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11187 /* 28217 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11188 /* 28219 */ GIR_RootConstrainSelectedInstOperands,
11189 /* 28220 */ // GIR_Coverage, 805,
11190 /* 28220 */ GIR_EraseRootFromParent_Done,
11191 /* 28221 */ // Label 821: @28221
11192 /* 28221 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(28266), // Rule ID 806 //
11193 /* 28226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11194 /* 28229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
11195 /* 28234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11196 /* 28237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11197 /* 28240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11198 /* 28243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11199 /* 28247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11200 /* 28251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11201 /* 28255 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8306:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11202 /* 28255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
11203 /* 28258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11204 /* 28260 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11205 /* 28262 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11206 /* 28264 */ GIR_RootConstrainSelectedInstOperands,
11207 /* 28265 */ // GIR_Coverage, 806,
11208 /* 28265 */ GIR_EraseRootFromParent_Done,
11209 /* 28266 */ // Label 822: @28266
11210 /* 28266 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(28311), // Rule ID 807 //
11211 /* 28271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11212 /* 28274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
11213 /* 28279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11214 /* 28282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11215 /* 28285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11216 /* 28288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11217 /* 28292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11218 /* 28296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11219 /* 28300 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8310:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11220 /* 28300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
11221 /* 28303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11222 /* 28305 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11223 /* 28307 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11224 /* 28309 */ GIR_RootConstrainSelectedInstOperands,
11225 /* 28310 */ // GIR_Coverage, 807,
11226 /* 28310 */ GIR_EraseRootFromParent_Done,
11227 /* 28311 */ // Label 823: @28311
11228 /* 28311 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(28356), // Rule ID 808 //
11229 /* 28316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11230 /* 28319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
11231 /* 28324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11232 /* 28327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11233 /* 28330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11234 /* 28333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11235 /* 28337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11236 /* 28341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11237 /* 28345 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8311:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11238 /* 28345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
11239 /* 28348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11240 /* 28350 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11241 /* 28352 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11242 /* 28354 */ GIR_RootConstrainSelectedInstOperands,
11243 /* 28355 */ // GIR_Coverage, 808,
11244 /* 28355 */ GIR_EraseRootFromParent_Done,
11245 /* 28356 */ // Label 824: @28356
11246 /* 28356 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(28401), // Rule ID 809 //
11247 /* 28361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11248 /* 28364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
11249 /* 28369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11250 /* 28372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11251 /* 28375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11252 /* 28378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11253 /* 28382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11254 /* 28386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11255 /* 28390 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11256 /* 28390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
11257 /* 28393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11258 /* 28395 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11259 /* 28397 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11260 /* 28399 */ GIR_RootConstrainSelectedInstOperands,
11261 /* 28400 */ // GIR_Coverage, 809,
11262 /* 28400 */ GIR_EraseRootFromParent_Done,
11263 /* 28401 */ // Label 825: @28401
11264 /* 28401 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(28446), // Rule ID 810 //
11265 /* 28406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11266 /* 28409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
11267 /* 28414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11268 /* 28417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11269 /* 28420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11270 /* 28423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11271 /* 28427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11272 /* 28431 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11273 /* 28435 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8313:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11274 /* 28435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
11275 /* 28438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11276 /* 28440 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11277 /* 28442 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11278 /* 28444 */ GIR_RootConstrainSelectedInstOperands,
11279 /* 28445 */ // GIR_Coverage, 810,
11280 /* 28445 */ GIR_EraseRootFromParent_Done,
11281 /* 28446 */ // Label 826: @28446
11282 /* 28446 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(28491), // Rule ID 811 //
11283 /* 28451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11284 /* 28454 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
11285 /* 28459 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11286 /* 28462 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11287 /* 28465 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11288 /* 28468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11289 /* 28472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11290 /* 28476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11291 /* 28480 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8314:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11292 /* 28480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
11293 /* 28483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11294 /* 28485 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11295 /* 28487 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11296 /* 28489 */ GIR_RootConstrainSelectedInstOperands,
11297 /* 28490 */ // GIR_Coverage, 811,
11298 /* 28490 */ GIR_EraseRootFromParent_Done,
11299 /* 28491 */ // Label 827: @28491
11300 /* 28491 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(28536), // Rule ID 812 //
11301 /* 28496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11302 /* 28499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
11303 /* 28504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11304 /* 28507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11305 /* 28510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11306 /* 28513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11307 /* 28517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11308 /* 28521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11309 /* 28525 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8312:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11310 /* 28525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
11311 /* 28528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11312 /* 28530 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11313 /* 28532 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11314 /* 28534 */ GIR_RootConstrainSelectedInstOperands,
11315 /* 28535 */ // GIR_Coverage, 812,
11316 /* 28535 */ GIR_EraseRootFromParent_Done,
11317 /* 28536 */ // Label 828: @28536
11318 /* 28536 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(28581), // Rule ID 813 //
11319 /* 28541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11320 /* 28544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
11321 /* 28549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11322 /* 28552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11323 /* 28555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11324 /* 28558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11325 /* 28562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11326 /* 28566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11327 /* 28570 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8316:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11328 /* 28570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
11329 /* 28573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11330 /* 28575 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11331 /* 28577 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11332 /* 28579 */ GIR_RootConstrainSelectedInstOperands,
11333 /* 28580 */ // GIR_Coverage, 813,
11334 /* 28580 */ GIR_EraseRootFromParent_Done,
11335 /* 28581 */ // Label 829: @28581
11336 /* 28581 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(28626), // Rule ID 814 //
11337 /* 28586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11338 /* 28589 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
11339 /* 28594 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11340 /* 28597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11341 /* 28600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11342 /* 28603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11343 /* 28607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11344 /* 28611 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11345 /* 28615 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8317:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11346 /* 28615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
11347 /* 28618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11348 /* 28620 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11349 /* 28622 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11350 /* 28624 */ GIR_RootConstrainSelectedInstOperands,
11351 /* 28625 */ // GIR_Coverage, 814,
11352 /* 28625 */ GIR_EraseRootFromParent_Done,
11353 /* 28626 */ // Label 830: @28626
11354 /* 28626 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(28671), // Rule ID 815 //
11355 /* 28631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11356 /* 28634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
11357 /* 28639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11358 /* 28642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11359 /* 28645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11360 /* 28648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11361 /* 28652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11362 /* 28656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11363 /* 28660 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8315:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11364 /* 28660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
11365 /* 28663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11366 /* 28665 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11367 /* 28667 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11368 /* 28669 */ GIR_RootConstrainSelectedInstOperands,
11369 /* 28670 */ // GIR_Coverage, 815,
11370 /* 28670 */ GIR_EraseRootFromParent_Done,
11371 /* 28671 */ // Label 831: @28671
11372 /* 28671 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(28716), // Rule ID 868 //
11373 /* 28676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11374 /* 28679 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
11375 /* 28684 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11376 /* 28687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11377 /* 28690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11378 /* 28693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11379 /* 28697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11380 /* 28701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11381 /* 28705 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8371:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11382 /* 28705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
11383 /* 28708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11384 /* 28710 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11385 /* 28712 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11386 /* 28714 */ GIR_RootConstrainSelectedInstOperands,
11387 /* 28715 */ // GIR_Coverage, 868,
11388 /* 28715 */ GIR_EraseRootFromParent_Done,
11389 /* 28716 */ // Label 832: @28716
11390 /* 28716 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(28761), // Rule ID 869 //
11391 /* 28721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11392 /* 28724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
11393 /* 28729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11394 /* 28732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11395 /* 28735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11396 /* 28738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11397 /* 28742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11398 /* 28746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11399 /* 28750 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8373:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11400 /* 28750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
11401 /* 28753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11402 /* 28755 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11403 /* 28757 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11404 /* 28759 */ GIR_RootConstrainSelectedInstOperands,
11405 /* 28760 */ // GIR_Coverage, 869,
11406 /* 28760 */ GIR_EraseRootFromParent_Done,
11407 /* 28761 */ // Label 833: @28761
11408 /* 28761 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(28806), // Rule ID 870 //
11409 /* 28766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11410 /* 28769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
11411 /* 28774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11412 /* 28777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11413 /* 28780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11414 /* 28783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11415 /* 28787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11416 /* 28791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11417 /* 28795 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8374:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11418 /* 28795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
11419 /* 28798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11420 /* 28800 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11421 /* 28802 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11422 /* 28804 */ GIR_RootConstrainSelectedInstOperands,
11423 /* 28805 */ // GIR_Coverage, 870,
11424 /* 28805 */ GIR_EraseRootFromParent_Done,
11425 /* 28806 */ // Label 834: @28806
11426 /* 28806 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(28851), // Rule ID 871 //
11427 /* 28811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11428 /* 28814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
11429 /* 28819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11430 /* 28822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11431 /* 28825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11432 /* 28828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11433 /* 28832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11434 /* 28836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11435 /* 28840 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8372:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11436 /* 28840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
11437 /* 28843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11438 /* 28845 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11439 /* 28847 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11440 /* 28849 */ GIR_RootConstrainSelectedInstOperands,
11441 /* 28850 */ // GIR_Coverage, 871,
11442 /* 28850 */ GIR_EraseRootFromParent_Done,
11443 /* 28851 */ // Label 835: @28851
11444 /* 28851 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(28896), // Rule ID 888 //
11445 /* 28856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11446 /* 28859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
11447 /* 28864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11448 /* 28867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11449 /* 28870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11450 /* 28873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11451 /* 28877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11452 /* 28881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11453 /* 28885 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8391:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11454 /* 28885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
11455 /* 28888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11456 /* 28890 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11457 /* 28892 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11458 /* 28894 */ GIR_RootConstrainSelectedInstOperands,
11459 /* 28895 */ // GIR_Coverage, 888,
11460 /* 28895 */ GIR_EraseRootFromParent_Done,
11461 /* 28896 */ // Label 836: @28896
11462 /* 28896 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(28941), // Rule ID 889 //
11463 /* 28901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11464 /* 28904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
11465 /* 28909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11466 /* 28912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11467 /* 28915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11468 /* 28918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11469 /* 28922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11470 /* 28926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11471 /* 28930 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8393:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11472 /* 28930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
11473 /* 28933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11474 /* 28935 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11475 /* 28937 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11476 /* 28939 */ GIR_RootConstrainSelectedInstOperands,
11477 /* 28940 */ // GIR_Coverage, 889,
11478 /* 28940 */ GIR_EraseRootFromParent_Done,
11479 /* 28941 */ // Label 837: @28941
11480 /* 28941 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(28986), // Rule ID 890 //
11481 /* 28946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11482 /* 28949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
11483 /* 28954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11484 /* 28957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11485 /* 28960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11486 /* 28963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11487 /* 28967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11488 /* 28971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11489 /* 28975 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8394:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11490 /* 28975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
11491 /* 28978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11492 /* 28980 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11493 /* 28982 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11494 /* 28984 */ GIR_RootConstrainSelectedInstOperands,
11495 /* 28985 */ // GIR_Coverage, 890,
11496 /* 28985 */ GIR_EraseRootFromParent_Done,
11497 /* 28986 */ // Label 838: @28986
11498 /* 28986 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(29031), // Rule ID 891 //
11499 /* 28991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11500 /* 28994 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
11501 /* 28999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11502 /* 29002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11503 /* 29005 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11504 /* 29008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11505 /* 29012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11506 /* 29016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11507 /* 29020 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8392:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11508 /* 29020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
11509 /* 29023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11510 /* 29025 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11511 /* 29027 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11512 /* 29029 */ GIR_RootConstrainSelectedInstOperands,
11513 /* 29030 */ // GIR_Coverage, 891,
11514 /* 29030 */ GIR_EraseRootFromParent_Done,
11515 /* 29031 */ // Label 839: @29031
11516 /* 29031 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(29076), // Rule ID 924 //
11517 /* 29036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11518 /* 29039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
11519 /* 29044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11520 /* 29047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11521 /* 29050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11522 /* 29053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11523 /* 29057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11524 /* 29061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11525 /* 29065 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8433:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11526 /* 29065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
11527 /* 29068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11528 /* 29070 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11529 /* 29072 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11530 /* 29074 */ GIR_RootConstrainSelectedInstOperands,
11531 /* 29075 */ // GIR_Coverage, 924,
11532 /* 29075 */ GIR_EraseRootFromParent_Done,
11533 /* 29076 */ // Label 840: @29076
11534 /* 29076 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(29121), // Rule ID 925 //
11535 /* 29081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11536 /* 29084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
11537 /* 29089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11538 /* 29092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11539 /* 29095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11540 /* 29098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11541 /* 29102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11542 /* 29106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11543 /* 29110 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8434:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11544 /* 29110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
11545 /* 29113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11546 /* 29115 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11547 /* 29117 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11548 /* 29119 */ GIR_RootConstrainSelectedInstOperands,
11549 /* 29120 */ // GIR_Coverage, 925,
11550 /* 29120 */ GIR_EraseRootFromParent_Done,
11551 /* 29121 */ // Label 841: @29121
11552 /* 29121 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(29166), // Rule ID 926 //
11553 /* 29126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11554 /* 29129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
11555 /* 29134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11556 /* 29137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11557 /* 29140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11558 /* 29143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11559 /* 29147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11560 /* 29151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11561 /* 29155 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8444:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11562 /* 29155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
11563 /* 29158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11564 /* 29160 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11565 /* 29162 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11566 /* 29164 */ GIR_RootConstrainSelectedInstOperands,
11567 /* 29165 */ // GIR_Coverage, 926,
11568 /* 29165 */ GIR_EraseRootFromParent_Done,
11569 /* 29166 */ // Label 842: @29166
11570 /* 29166 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(29211), // Rule ID 927 //
11571 /* 29171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11572 /* 29174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
11573 /* 29179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11574 /* 29182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11575 /* 29185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11576 /* 29188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11577 /* 29192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11578 /* 29196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11579 /* 29200 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8445:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11580 /* 29200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
11581 /* 29203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11582 /* 29205 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11583 /* 29207 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11584 /* 29209 */ GIR_RootConstrainSelectedInstOperands,
11585 /* 29210 */ // GIR_Coverage, 927,
11586 /* 29210 */ GIR_EraseRootFromParent_Done,
11587 /* 29211 */ // Label 843: @29211
11588 /* 29211 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(29256), // Rule ID 1005 //
11589 /* 29216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11590 /* 29219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
11591 /* 29224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11592 /* 29227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11593 /* 29230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11594 /* 29233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11595 /* 29237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11596 /* 29241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11597 /* 29245 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8558:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11598 /* 29245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
11599 /* 29248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11600 /* 29250 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11601 /* 29252 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11602 /* 29254 */ GIR_RootConstrainSelectedInstOperands,
11603 /* 29255 */ // GIR_Coverage, 1005,
11604 /* 29255 */ GIR_EraseRootFromParent_Done,
11605 /* 29256 */ // Label 844: @29256
11606 /* 29256 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(29301), // Rule ID 1006 //
11607 /* 29261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11608 /* 29264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
11609 /* 29269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11610 /* 29272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11611 /* 29275 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11612 /* 29278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11613 /* 29282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11614 /* 29286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11615 /* 29290 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8560:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11616 /* 29290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
11617 /* 29293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11618 /* 29295 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11619 /* 29297 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11620 /* 29299 */ GIR_RootConstrainSelectedInstOperands,
11621 /* 29300 */ // GIR_Coverage, 1006,
11622 /* 29300 */ GIR_EraseRootFromParent_Done,
11623 /* 29301 */ // Label 845: @29301
11624 /* 29301 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(29346), // Rule ID 1007 //
11625 /* 29306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11626 /* 29309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
11627 /* 29314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11628 /* 29317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11629 /* 29320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11630 /* 29323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11631 /* 29327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11632 /* 29331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11633 /* 29335 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8561:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11634 /* 29335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
11635 /* 29338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11636 /* 29340 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11637 /* 29342 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11638 /* 29344 */ GIR_RootConstrainSelectedInstOperands,
11639 /* 29345 */ // GIR_Coverage, 1007,
11640 /* 29345 */ GIR_EraseRootFromParent_Done,
11641 /* 29346 */ // Label 846: @29346
11642 /* 29346 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(29391), // Rule ID 1008 //
11643 /* 29351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11644 /* 29354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
11645 /* 29359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11646 /* 29362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11647 /* 29365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11648 /* 29368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11649 /* 29372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11650 /* 29376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11651 /* 29380 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8559:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11652 /* 29380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
11653 /* 29383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11654 /* 29385 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11655 /* 29387 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11656 /* 29389 */ GIR_RootConstrainSelectedInstOperands,
11657 /* 29390 */ // GIR_Coverage, 1008,
11658 /* 29390 */ GIR_EraseRootFromParent_Done,
11659 /* 29391 */ // Label 847: @29391
11660 /* 29391 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(29436), // Rule ID 1021 //
11661 /* 29396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11662 /* 29399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
11663 /* 29404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11664 /* 29407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11665 /* 29410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11666 /* 29413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11667 /* 29417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11668 /* 29421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11669 /* 29425 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11670 /* 29425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
11671 /* 29428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11672 /* 29430 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11673 /* 29432 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11674 /* 29434 */ GIR_RootConstrainSelectedInstOperands,
11675 /* 29435 */ // GIR_Coverage, 1021,
11676 /* 29435 */ GIR_EraseRootFromParent_Done,
11677 /* 29436 */ // Label 848: @29436
11678 /* 29436 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(29481), // Rule ID 1022 //
11679 /* 29441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11680 /* 29444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
11681 /* 29449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11682 /* 29452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11683 /* 29455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11684 /* 29458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11685 /* 29462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11686 /* 29466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11687 /* 29470 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8576:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11688 /* 29470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
11689 /* 29473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11690 /* 29475 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11691 /* 29477 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11692 /* 29479 */ GIR_RootConstrainSelectedInstOperands,
11693 /* 29480 */ // GIR_Coverage, 1022,
11694 /* 29480 */ GIR_EraseRootFromParent_Done,
11695 /* 29481 */ // Label 849: @29481
11696 /* 29481 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(29526), // Rule ID 1023 //
11697 /* 29486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11698 /* 29489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
11699 /* 29494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11700 /* 29497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11701 /* 29500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11702 /* 29503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11703 /* 29507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11704 /* 29511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11705 /* 29515 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8577:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11706 /* 29515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
11707 /* 29518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11708 /* 29520 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11709 /* 29522 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11710 /* 29524 */ GIR_RootConstrainSelectedInstOperands,
11711 /* 29525 */ // GIR_Coverage, 1023,
11712 /* 29525 */ GIR_EraseRootFromParent_Done,
11713 /* 29526 */ // Label 850: @29526
11714 /* 29526 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(29571), // Rule ID 1024 //
11715 /* 29531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11716 /* 29534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
11717 /* 29539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11718 /* 29542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11719 /* 29545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11720 /* 29548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11721 /* 29552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11722 /* 29556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11723 /* 29560 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8575:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11724 /* 29560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
11725 /* 29563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11726 /* 29565 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11727 /* 29567 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11728 /* 29569 */ GIR_RootConstrainSelectedInstOperands,
11729 /* 29570 */ // GIR_Coverage, 1024,
11730 /* 29570 */ GIR_EraseRootFromParent_Done,
11731 /* 29571 */ // Label 851: @29571
11732 /* 29571 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(29616), // Rule ID 1033 //
11733 /* 29576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11734 /* 29579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
11735 /* 29584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11736 /* 29587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11737 /* 29590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11738 /* 29593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11739 /* 29597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11740 /* 29601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11741 /* 29605 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8595:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11742 /* 29605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
11743 /* 29608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11744 /* 29610 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11745 /* 29612 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11746 /* 29614 */ GIR_RootConstrainSelectedInstOperands,
11747 /* 29615 */ // GIR_Coverage, 1033,
11748 /* 29615 */ GIR_EraseRootFromParent_Done,
11749 /* 29616 */ // Label 852: @29616
11750 /* 29616 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(29661), // Rule ID 1034 //
11751 /* 29621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11752 /* 29624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
11753 /* 29629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11754 /* 29632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11755 /* 29635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11756 /* 29638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11757 /* 29642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11758 /* 29646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11759 /* 29650 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8597:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11760 /* 29650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
11761 /* 29653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11762 /* 29655 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11763 /* 29657 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11764 /* 29659 */ GIR_RootConstrainSelectedInstOperands,
11765 /* 29660 */ // GIR_Coverage, 1034,
11766 /* 29660 */ GIR_EraseRootFromParent_Done,
11767 /* 29661 */ // Label 853: @29661
11768 /* 29661 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(29706), // Rule ID 1035 //
11769 /* 29666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11770 /* 29669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
11771 /* 29674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11772 /* 29677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11773 /* 29680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11774 /* 29683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11775 /* 29687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11776 /* 29691 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11777 /* 29695 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8598:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11778 /* 29695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
11779 /* 29698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11780 /* 29700 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11781 /* 29702 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11782 /* 29704 */ GIR_RootConstrainSelectedInstOperands,
11783 /* 29705 */ // GIR_Coverage, 1035,
11784 /* 29705 */ GIR_EraseRootFromParent_Done,
11785 /* 29706 */ // Label 854: @29706
11786 /* 29706 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(29751), // Rule ID 1036 //
11787 /* 29711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11788 /* 29714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
11789 /* 29719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11790 /* 29722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11791 /* 29725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11792 /* 29728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11793 /* 29732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11794 /* 29736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11795 /* 29740 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8596:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11796 /* 29740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
11797 /* 29743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11798 /* 29745 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11799 /* 29747 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11800 /* 29749 */ GIR_RootConstrainSelectedInstOperands,
11801 /* 29750 */ // GIR_Coverage, 1036,
11802 /* 29750 */ GIR_EraseRootFromParent_Done,
11803 /* 29751 */ // Label 855: @29751
11804 /* 29751 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(29796), // Rule ID 1037 //
11805 /* 29756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11806 /* 29759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
11807 /* 29764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11808 /* 29767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11809 /* 29770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11810 /* 29773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11811 /* 29777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11812 /* 29781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11813 /* 29785 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8599:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11814 /* 29785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
11815 /* 29788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11816 /* 29790 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11817 /* 29792 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11818 /* 29794 */ GIR_RootConstrainSelectedInstOperands,
11819 /* 29795 */ // GIR_Coverage, 1037,
11820 /* 29795 */ GIR_EraseRootFromParent_Done,
11821 /* 29796 */ // Label 856: @29796
11822 /* 29796 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(29841), // Rule ID 1038 //
11823 /* 29801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11824 /* 29804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11825 /* 29809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11826 /* 29812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11827 /* 29815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11828 /* 29818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11829 /* 29822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11830 /* 29826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11831 /* 29830 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8601:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11832 /* 29830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
11833 /* 29833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11834 /* 29835 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11835 /* 29837 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11836 /* 29839 */ GIR_RootConstrainSelectedInstOperands,
11837 /* 29840 */ // GIR_Coverage, 1038,
11838 /* 29840 */ GIR_EraseRootFromParent_Done,
11839 /* 29841 */ // Label 857: @29841
11840 /* 29841 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(29886), // Rule ID 1039 //
11841 /* 29846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11842 /* 29849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11843 /* 29854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11844 /* 29857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11845 /* 29860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11846 /* 29863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11847 /* 29867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11848 /* 29871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11849 /* 29875 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8602:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11850 /* 29875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
11851 /* 29878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11852 /* 29880 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11853 /* 29882 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11854 /* 29884 */ GIR_RootConstrainSelectedInstOperands,
11855 /* 29885 */ // GIR_Coverage, 1039,
11856 /* 29885 */ GIR_EraseRootFromParent_Done,
11857 /* 29886 */ // Label 858: @29886
11858 /* 29886 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(29931), // Rule ID 1040 //
11859 /* 29891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11860 /* 29894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11861 /* 29899 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11862 /* 29902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11863 /* 29905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11864 /* 29908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11865 /* 29912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11866 /* 29916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11867 /* 29920 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8600:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11868 /* 29920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
11869 /* 29923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11870 /* 29925 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11871 /* 29927 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11872 /* 29929 */ GIR_RootConstrainSelectedInstOperands,
11873 /* 29930 */ // GIR_Coverage, 1040,
11874 /* 29930 */ GIR_EraseRootFromParent_Done,
11875 /* 29931 */ // Label 859: @29931
11876 /* 29931 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(29976), // Rule ID 1041 //
11877 /* 29936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11878 /* 29939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11879 /* 29944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11880 /* 29947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11881 /* 29950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11882 /* 29953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11883 /* 29957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11884 /* 29961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11885 /* 29965 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8603:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11886 /* 29965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
11887 /* 29968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11888 /* 29970 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11889 /* 29972 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11890 /* 29974 */ GIR_RootConstrainSelectedInstOperands,
11891 /* 29975 */ // GIR_Coverage, 1041,
11892 /* 29975 */ GIR_EraseRootFromParent_Done,
11893 /* 29976 */ // Label 860: @29976
11894 /* 29976 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(30021), // Rule ID 1042 //
11895 /* 29981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11896 /* 29984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11897 /* 29989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11898 /* 29992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11899 /* 29995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11900 /* 29998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11901 /* 30002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11902 /* 30006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11903 /* 30010 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8605:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11904 /* 30010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
11905 /* 30013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11906 /* 30015 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11907 /* 30017 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11908 /* 30019 */ GIR_RootConstrainSelectedInstOperands,
11909 /* 30020 */ // GIR_Coverage, 1042,
11910 /* 30020 */ GIR_EraseRootFromParent_Done,
11911 /* 30021 */ // Label 861: @30021
11912 /* 30021 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(30066), // Rule ID 1043 //
11913 /* 30026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11914 /* 30029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11915 /* 30034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11916 /* 30037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11917 /* 30040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11918 /* 30043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11919 /* 30047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11920 /* 30051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11921 /* 30055 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8606:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11922 /* 30055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
11923 /* 30058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11924 /* 30060 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11925 /* 30062 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11926 /* 30064 */ GIR_RootConstrainSelectedInstOperands,
11927 /* 30065 */ // GIR_Coverage, 1043,
11928 /* 30065 */ GIR_EraseRootFromParent_Done,
11929 /* 30066 */ // Label 862: @30066
11930 /* 30066 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(30111), // Rule ID 1044 //
11931 /* 30071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11932 /* 30074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11933 /* 30079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11934 /* 30082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11935 /* 30085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11936 /* 30088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11937 /* 30092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11938 /* 30096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11939 /* 30100 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8604:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11940 /* 30100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
11941 /* 30103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11942 /* 30105 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11943 /* 30107 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11944 /* 30109 */ GIR_RootConstrainSelectedInstOperands,
11945 /* 30110 */ // GIR_Coverage, 1044,
11946 /* 30110 */ GIR_EraseRootFromParent_Done,
11947 /* 30111 */ // Label 863: @30111
11948 /* 30111 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(30156), // Rule ID 1045 //
11949 /* 30116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11950 /* 30119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11951 /* 30124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11952 /* 30127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11953 /* 30130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11954 /* 30133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11955 /* 30137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11956 /* 30141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11957 /* 30145 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8607:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11958 /* 30145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
11959 /* 30148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11960 /* 30150 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11961 /* 30152 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11962 /* 30154 */ GIR_RootConstrainSelectedInstOperands,
11963 /* 30155 */ // GIR_Coverage, 1045,
11964 /* 30155 */ GIR_EraseRootFromParent_Done,
11965 /* 30156 */ // Label 864: @30156
11966 /* 30156 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(30201), // Rule ID 1046 //
11967 /* 30161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11968 /* 30164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11969 /* 30169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11970 /* 30172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11971 /* 30175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11972 /* 30178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11973 /* 30182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11974 /* 30186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11975 /* 30190 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8609:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11976 /* 30190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
11977 /* 30193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11978 /* 30195 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11979 /* 30197 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11980 /* 30199 */ GIR_RootConstrainSelectedInstOperands,
11981 /* 30200 */ // GIR_Coverage, 1046,
11982 /* 30200 */ GIR_EraseRootFromParent_Done,
11983 /* 30201 */ // Label 865: @30201
11984 /* 30201 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(30246), // Rule ID 1047 //
11985 /* 30206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11986 /* 30209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11987 /* 30214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11988 /* 30217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11989 /* 30220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11990 /* 30223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11991 /* 30227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11992 /* 30231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11993 /* 30235 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8610:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11994 /* 30235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
11995 /* 30238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11996 /* 30240 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11997 /* 30242 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11998 /* 30244 */ GIR_RootConstrainSelectedInstOperands,
11999 /* 30245 */ // GIR_Coverage, 1047,
12000 /* 30245 */ GIR_EraseRootFromParent_Done,
12001 /* 30246 */ // Label 866: @30246
12002 /* 30246 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(30291), // Rule ID 1048 //
12003 /* 30251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12004 /* 30254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
12005 /* 30259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12006 /* 30262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12007 /* 30265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12008 /* 30268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12009 /* 30272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12010 /* 30276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12011 /* 30280 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8608:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12012 /* 30280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
12013 /* 30283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12014 /* 30285 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
12015 /* 30287 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
12016 /* 30289 */ GIR_RootConstrainSelectedInstOperands,
12017 /* 30290 */ // GIR_Coverage, 1048,
12018 /* 30290 */ GIR_EraseRootFromParent_Done,
12019 /* 30291 */ // Label 867: @30291
12020 /* 30291 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(30339), // Rule ID 1246 //
12021 /* 30296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12022 /* 30299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
12023 /* 30304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12024 /* 30307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12025 /* 30310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12026 /* 30313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12027 /* 30317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12028 /* 30321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12029 /* 30325 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7969:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12030 /* 30325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
12031 /* 30328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12032 /* 30330 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12033 /* 30332 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12034 /* 30334 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12035 /* 30337 */ GIR_RootConstrainSelectedInstOperands,
12036 /* 30338 */ // GIR_Coverage, 1246,
12037 /* 30338 */ GIR_EraseRootFromParent_Done,
12038 /* 30339 */ // Label 868: @30339
12039 /* 30339 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(30387), // Rule ID 1248 //
12040 /* 30344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12041 /* 30347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
12042 /* 30352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12043 /* 30355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12044 /* 30358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12045 /* 30361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12046 /* 30365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12047 /* 30369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12048 /* 30373 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12049 /* 30373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
12050 /* 30376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12051 /* 30378 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12052 /* 30380 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12053 /* 30382 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12054 /* 30385 */ GIR_RootConstrainSelectedInstOperands,
12055 /* 30386 */ // GIR_Coverage, 1248,
12056 /* 30386 */ GIR_EraseRootFromParent_Done,
12057 /* 30387 */ // Label 869: @30387
12058 /* 30387 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(30432), // Rule ID 1269 //
12059 /* 30392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12060 /* 30395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
12061 /* 30400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12062 /* 30403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12063 /* 30406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12064 /* 30409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12065 /* 30413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12066 /* 30417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12067 /* 30421 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12068 /* 30421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
12069 /* 30424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12070 /* 30426 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12071 /* 30428 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12072 /* 30430 */ GIR_RootConstrainSelectedInstOperands,
12073 /* 30431 */ // GIR_Coverage, 1269,
12074 /* 30431 */ GIR_EraseRootFromParent_Done,
12075 /* 30432 */ // Label 870: @30432
12076 /* 30432 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30477), // Rule ID 1270 //
12077 /* 30437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12078 /* 30440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
12079 /* 30445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12080 /* 30448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12081 /* 30451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12082 /* 30454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12083 /* 30458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12084 /* 30462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12085 /* 30466 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12086 /* 30466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
12087 /* 30469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12088 /* 30471 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12089 /* 30473 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12090 /* 30475 */ GIR_RootConstrainSelectedInstOperands,
12091 /* 30476 */ // GIR_Coverage, 1270,
12092 /* 30476 */ GIR_EraseRootFromParent_Done,
12093 /* 30477 */ // Label 871: @30477
12094 /* 30477 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30522), // Rule ID 1271 //
12095 /* 30482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12096 /* 30485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
12097 /* 30490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12098 /* 30493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12099 /* 30496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12100 /* 30499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12101 /* 30503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12102 /* 30507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12103 /* 30511 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12104 /* 30511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
12105 /* 30514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12106 /* 30516 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12107 /* 30518 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12108 /* 30520 */ GIR_RootConstrainSelectedInstOperands,
12109 /* 30521 */ // GIR_Coverage, 1271,
12110 /* 30521 */ GIR_EraseRootFromParent_Done,
12111 /* 30522 */ // Label 872: @30522
12112 /* 30522 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30567), // Rule ID 1273 //
12113 /* 30527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12114 /* 30530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
12115 /* 30535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12116 /* 30538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12117 /* 30541 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12118 /* 30544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12119 /* 30548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12120 /* 30552 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12121 /* 30556 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12122 /* 30556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
12123 /* 30559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12124 /* 30561 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12125 /* 30563 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12126 /* 30565 */ GIR_RootConstrainSelectedInstOperands,
12127 /* 30566 */ // GIR_Coverage, 1273,
12128 /* 30566 */ GIR_EraseRootFromParent_Done,
12129 /* 30567 */ // Label 873: @30567
12130 /* 30567 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30615), // Rule ID 1284 //
12131 /* 30572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12132 /* 30575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
12133 /* 30580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12134 /* 30583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12135 /* 30586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12136 /* 30589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12137 /* 30593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12138 /* 30597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12139 /* 30601 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8589:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12140 /* 30601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
12141 /* 30604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12142 /* 30606 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12143 /* 30608 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12144 /* 30610 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12145 /* 30613 */ GIR_RootConstrainSelectedInstOperands,
12146 /* 30614 */ // GIR_Coverage, 1284,
12147 /* 30614 */ GIR_EraseRootFromParent_Done,
12148 /* 30615 */ // Label 874: @30615
12149 /* 30615 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(30663), // Rule ID 1286 //
12150 /* 30620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12151 /* 30623 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
12152 /* 30628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12153 /* 30631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12154 /* 30634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12155 /* 30637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12156 /* 30641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12157 /* 30645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12158 /* 30649 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12159 /* 30649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
12160 /* 30652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12161 /* 30654 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12162 /* 30656 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12163 /* 30658 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12164 /* 30661 */ GIR_RootConstrainSelectedInstOperands,
12165 /* 30662 */ // GIR_Coverage, 1286,
12166 /* 30662 */ GIR_EraseRootFromParent_Done,
12167 /* 30663 */ // Label 875: @30663
12168 /* 30663 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(30708), // Rule ID 1296 //
12169 /* 30668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12170 /* 30671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
12171 /* 30676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12172 /* 30679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12173 /* 30682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12174 /* 30685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12175 /* 30689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12176 /* 30693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12177 /* 30697 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12178 /* 30697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
12179 /* 30700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12180 /* 30702 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12181 /* 30704 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12182 /* 30706 */ GIR_RootConstrainSelectedInstOperands,
12183 /* 30707 */ // GIR_Coverage, 1296,
12184 /* 30707 */ GIR_EraseRootFromParent_Done,
12185 /* 30708 */ // Label 876: @30708
12186 /* 30708 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(30753), // Rule ID 1297 //
12187 /* 30713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12188 /* 30716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
12189 /* 30721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12190 /* 30724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12191 /* 30727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12192 /* 30730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12193 /* 30734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12194 /* 30738 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12195 /* 30742 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12196 /* 30742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
12197 /* 30745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12198 /* 30747 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12199 /* 30749 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12200 /* 30751 */ GIR_RootConstrainSelectedInstOperands,
12201 /* 30752 */ // GIR_Coverage, 1297,
12202 /* 30752 */ GIR_EraseRootFromParent_Done,
12203 /* 30753 */ // Label 877: @30753
12204 /* 30753 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(30798), // Rule ID 1316 //
12205 /* 30758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12206 /* 30761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
12207 /* 30766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12208 /* 30769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12209 /* 30772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12210 /* 30775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12211 /* 30779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12212 /* 30783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12213 /* 30787 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12214 /* 30787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
12215 /* 30790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12216 /* 30792 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12217 /* 30794 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12218 /* 30796 */ GIR_RootConstrainSelectedInstOperands,
12219 /* 30797 */ // GIR_Coverage, 1316,
12220 /* 30797 */ GIR_EraseRootFromParent_Done,
12221 /* 30798 */ // Label 878: @30798
12222 /* 30798 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(30843), // Rule ID 1322 //
12223 /* 30803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12224 /* 30806 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
12225 /* 30811 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12226 /* 30814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12227 /* 30817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12228 /* 30820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12229 /* 30824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12230 /* 30828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12231 /* 30832 */ // (intrinsic_wo_chain:{ *:[i32] } 8419:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12232 /* 30832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
12233 /* 30835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12234 /* 30837 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12235 /* 30839 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12236 /* 30841 */ GIR_RootConstrainSelectedInstOperands,
12237 /* 30842 */ // GIR_Coverage, 1322,
12238 /* 30842 */ GIR_EraseRootFromParent_Done,
12239 /* 30843 */ // Label 879: @30843
12240 /* 30843 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(30888), // Rule ID 1335 //
12241 /* 30848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12242 /* 30851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
12243 /* 30856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12244 /* 30859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12245 /* 30862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12246 /* 30865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12247 /* 30869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12248 /* 30873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12249 /* 30877 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7971:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12250 /* 30877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
12251 /* 30880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12252 /* 30882 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12253 /* 30884 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12254 /* 30886 */ GIR_RootConstrainSelectedInstOperands,
12255 /* 30887 */ // GIR_Coverage, 1335,
12256 /* 30887 */ GIR_EraseRootFromParent_Done,
12257 /* 30888 */ // Label 880: @30888
12258 /* 30888 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(30933), // Rule ID 1336 //
12259 /* 30893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12260 /* 30896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
12261 /* 30901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12262 /* 30904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12263 /* 30907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12264 /* 30910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12265 /* 30914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12266 /* 30918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12267 /* 30922 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12268 /* 30922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
12269 /* 30925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12270 /* 30927 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12271 /* 30929 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12272 /* 30931 */ GIR_RootConstrainSelectedInstOperands,
12273 /* 30932 */ // GIR_Coverage, 1336,
12274 /* 30932 */ GIR_EraseRootFromParent_Done,
12275 /* 30933 */ // Label 881: @30933
12276 /* 30933 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(30978), // Rule ID 1337 //
12277 /* 30938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12278 /* 30941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
12279 /* 30946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12280 /* 30949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12281 /* 30952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12282 /* 30955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12283 /* 30959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12284 /* 30963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12285 /* 30967 */ // (intrinsic_wo_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12286 /* 30967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
12287 /* 30970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12288 /* 30972 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12289 /* 30974 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12290 /* 30976 */ GIR_RootConstrainSelectedInstOperands,
12291 /* 30977 */ // GIR_Coverage, 1337,
12292 /* 30977 */ GIR_EraseRootFromParent_Done,
12293 /* 30978 */ // Label 882: @30978
12294 /* 30978 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(31023), // Rule ID 1338 //
12295 /* 30983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12296 /* 30986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
12297 /* 30991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12298 /* 30994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12299 /* 30997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12300 /* 31000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12301 /* 31004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12302 /* 31008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12303 /* 31012 */ // (intrinsic_wo_chain:{ *:[i32] } 7973:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12304 /* 31012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
12305 /* 31015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12306 /* 31017 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12307 /* 31019 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12308 /* 31021 */ GIR_RootConstrainSelectedInstOperands,
12309 /* 31022 */ // GIR_Coverage, 1338,
12310 /* 31022 */ GIR_EraseRootFromParent_Done,
12311 /* 31023 */ // Label 883: @31023
12312 /* 31023 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31068), // Rule ID 1341 //
12313 /* 31028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12314 /* 31031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
12315 /* 31036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12316 /* 31039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12317 /* 31042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12318 /* 31045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12319 /* 31049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12320 /* 31053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12321 /* 31057 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7992:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12322 /* 31057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
12323 /* 31060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12324 /* 31062 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12325 /* 31064 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12326 /* 31066 */ GIR_RootConstrainSelectedInstOperands,
12327 /* 31067 */ // GIR_Coverage, 1341,
12328 /* 31067 */ GIR_EraseRootFromParent_Done,
12329 /* 31068 */ // Label 884: @31068
12330 /* 31068 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(31113), // Rule ID 1342 //
12331 /* 31073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12332 /* 31076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
12333 /* 31081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12334 /* 31084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12335 /* 31087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12336 /* 31090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12337 /* 31094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12338 /* 31098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12339 /* 31102 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12340 /* 31102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
12341 /* 31105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12342 /* 31107 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12343 /* 31109 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12344 /* 31111 */ GIR_RootConstrainSelectedInstOperands,
12345 /* 31112 */ // GIR_Coverage, 1342,
12346 /* 31112 */ GIR_EraseRootFromParent_Done,
12347 /* 31113 */ // Label 885: @31113
12348 /* 31113 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(31158), // Rule ID 1348 //
12349 /* 31118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12350 /* 31121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
12351 /* 31126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12352 /* 31129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12353 /* 31132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12354 /* 31135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12355 /* 31139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12356 /* 31143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12357 /* 31147 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12358 /* 31147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
12359 /* 31150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12360 /* 31152 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12361 /* 31154 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12362 /* 31156 */ GIR_RootConstrainSelectedInstOperands,
12363 /* 31157 */ // GIR_Coverage, 1348,
12364 /* 31157 */ GIR_EraseRootFromParent_Done,
12365 /* 31158 */ // Label 886: @31158
12366 /* 31158 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(31203), // Rule ID 1349 //
12367 /* 31163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12368 /* 31166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
12369 /* 31171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12370 /* 31174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12371 /* 31177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12372 /* 31180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12373 /* 31184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12374 /* 31188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12375 /* 31192 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12376 /* 31192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
12377 /* 31195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12378 /* 31197 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12379 /* 31199 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12380 /* 31201 */ GIR_RootConstrainSelectedInstOperands,
12381 /* 31202 */ // GIR_Coverage, 1349,
12382 /* 31202 */ GIR_EraseRootFromParent_Done,
12383 /* 31203 */ // Label 887: @31203
12384 /* 31203 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(31248), // Rule ID 1354 //
12385 /* 31208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12386 /* 31211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
12387 /* 31216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12388 /* 31219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12389 /* 31222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12390 /* 31225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12391 /* 31229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12392 /* 31233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12393 /* 31237 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
12394 /* 31237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
12395 /* 31240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12396 /* 31242 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12397 /* 31244 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12398 /* 31246 */ GIR_RootConstrainSelectedInstOperands,
12399 /* 31247 */ // GIR_Coverage, 1354,
12400 /* 31247 */ GIR_EraseRootFromParent_Done,
12401 /* 31248 */ // Label 888: @31248
12402 /* 31248 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(31293), // Rule ID 1355 //
12403 /* 31253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12404 /* 31256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
12405 /* 31261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12406 /* 31264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12407 /* 31267 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12408 /* 31270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12409 /* 31274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12410 /* 31278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12411 /* 31282 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8591:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12412 /* 31282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
12413 /* 31285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12414 /* 31287 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12415 /* 31289 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12416 /* 31291 */ GIR_RootConstrainSelectedInstOperands,
12417 /* 31292 */ // GIR_Coverage, 1355,
12418 /* 31292 */ GIR_EraseRootFromParent_Done,
12419 /* 31293 */ // Label 889: @31293
12420 /* 31293 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(31338), // Rule ID 1356 //
12421 /* 31298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12422 /* 31301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
12423 /* 31306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12424 /* 31309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12425 /* 31312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12426 /* 31315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12427 /* 31319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12428 /* 31323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12429 /* 31327 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12430 /* 31327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
12431 /* 31330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12432 /* 31332 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12433 /* 31334 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12434 /* 31336 */ GIR_RootConstrainSelectedInstOperands,
12435 /* 31337 */ // GIR_Coverage, 1356,
12436 /* 31337 */ GIR_EraseRootFromParent_Done,
12437 /* 31338 */ // Label 890: @31338
12438 /* 31338 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(31383), // Rule ID 1357 //
12439 /* 31343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12440 /* 31346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
12441 /* 31351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12442 /* 31354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12443 /* 31357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12444 /* 31360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12445 /* 31364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12446 /* 31368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12447 /* 31372 */ // (intrinsic_wo_chain:{ *:[i32] } 8594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12448 /* 31372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
12449 /* 31375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12450 /* 31377 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12451 /* 31379 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12452 /* 31381 */ GIR_RootConstrainSelectedInstOperands,
12453 /* 31382 */ // GIR_Coverage, 1357,
12454 /* 31382 */ GIR_EraseRootFromParent_Done,
12455 /* 31383 */ // Label 891: @31383
12456 /* 31383 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(31428), // Rule ID 1358 //
12457 /* 31388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12458 /* 31391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
12459 /* 31396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12460 /* 31399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12461 /* 31402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12462 /* 31405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12463 /* 31409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12464 /* 31413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12465 /* 31417 */ // (intrinsic_wo_chain:{ *:[i32] } 8593:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12466 /* 31417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
12467 /* 31420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12468 /* 31422 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12469 /* 31424 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12470 /* 31426 */ GIR_RootConstrainSelectedInstOperands,
12471 /* 31427 */ // GIR_Coverage, 1358,
12472 /* 31427 */ GIR_EraseRootFromParent_Done,
12473 /* 31428 */ // Label 892: @31428
12474 /* 31428 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(31473), // Rule ID 1361 //
12475 /* 31433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12476 /* 31436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
12477 /* 31441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12478 /* 31444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12479 /* 31447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12480 /* 31450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12481 /* 31454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12482 /* 31458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12483 /* 31462 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8615:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12484 /* 31462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
12485 /* 31465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12486 /* 31467 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12487 /* 31469 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12488 /* 31471 */ GIR_RootConstrainSelectedInstOperands,
12489 /* 31472 */ // GIR_Coverage, 1361,
12490 /* 31472 */ GIR_EraseRootFromParent_Done,
12491 /* 31473 */ // Label 893: @31473
12492 /* 31473 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(31518), // Rule ID 1362 //
12493 /* 31478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12494 /* 31481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
12495 /* 31486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12496 /* 31489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12497 /* 31492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12498 /* 31495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12499 /* 31499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12500 /* 31503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12501 /* 31507 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8616:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12502 /* 31507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
12503 /* 31510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12504 /* 31512 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12505 /* 31514 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
12506 /* 31516 */ GIR_RootConstrainSelectedInstOperands,
12507 /* 31517 */ // GIR_Coverage, 1362,
12508 /* 31517 */ GIR_EraseRootFromParent_Done,
12509 /* 31518 */ // Label 894: @31518
12510 /* 31518 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(31558), // Rule ID 2051 //
12511 /* 31523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12512 /* 31526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
12513 /* 31531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12514 /* 31534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12515 /* 31537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12516 /* 31540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12517 /* 31544 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7968:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12518 /* 31544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
12519 /* 31547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12520 /* 31549 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12521 /* 31551 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12522 /* 31553 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12523 /* 31556 */ GIR_RootConstrainSelectedInstOperands,
12524 /* 31557 */ // GIR_Coverage, 2051,
12525 /* 31557 */ GIR_EraseRootFromParent_Done,
12526 /* 31558 */ // Label 895: @31558
12527 /* 31558 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(31598), // Rule ID 2053 //
12528 /* 31563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12529 /* 31566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
12530 /* 31571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12531 /* 31574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12532 /* 31577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12533 /* 31580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12534 /* 31584 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8588:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
12535 /* 31584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
12536 /* 31587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12537 /* 31589 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12538 /* 31591 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12539 /* 31593 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12540 /* 31596 */ GIR_RootConstrainSelectedInstOperands,
12541 /* 31597 */ // GIR_Coverage, 2053,
12542 /* 31597 */ GIR_EraseRootFromParent_Done,
12543 /* 31598 */ // Label 896: @31598
12544 /* 31598 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(31638), // Rule ID 2057 //
12545 /* 31603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12546 /* 31606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
12547 /* 31611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12548 /* 31614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12549 /* 31617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12550 /* 31620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12551 /* 31624 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7989:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
12552 /* 31624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
12553 /* 31627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12554 /* 31629 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12555 /* 31631 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12556 /* 31633 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12557 /* 31636 */ GIR_RootConstrainSelectedInstOperands,
12558 /* 31637 */ // GIR_Coverage, 2057,
12559 /* 31637 */ GIR_EraseRootFromParent_Done,
12560 /* 31638 */ // Label 897: @31638
12561 /* 31638 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(31678), // Rule ID 2059 //
12562 /* 31643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12563 /* 31646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
12564 /* 31651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12565 /* 31654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12566 /* 31657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12567 /* 31660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12568 /* 31664 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8612:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
12569 /* 31664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
12570 /* 31667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12571 /* 31669 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
12572 /* 31671 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
12573 /* 31673 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12574 /* 31676 */ GIR_RootConstrainSelectedInstOperands,
12575 /* 31677 */ // GIR_Coverage, 2059,
12576 /* 31677 */ GIR_EraseRootFromParent_Done,
12577 /* 31678 */ // Label 898: @31678
12578 /* 31678 */ GIM_Reject,
12579 /* 31679 */ // Label 684: @31679
12580 /* 31679 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(34193),
12581 /* 31684 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
12582 /* 31687 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(31742), // Rule ID 501 //
12583 /* 31692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12584 /* 31695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12585 /* 31700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12586 /* 31703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12587 /* 31706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12588 /* 31709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12589 /* 31713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12590 /* 31717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12591 /* 31721 */ // MIs[0] sa
12592 /* 31721 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12593 /* 31724 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12594 /* 31729 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12595 /* 31729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
12596 /* 31732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12597 /* 31734 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12598 /* 31736 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12599 /* 31738 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12600 /* 31740 */ GIR_RootConstrainSelectedInstOperands,
12601 /* 31741 */ // GIR_Coverage, 501,
12602 /* 31741 */ GIR_EraseRootFromParent_Done,
12603 /* 31742 */ // Label 900: @31742
12604 /* 31742 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(31797), // Rule ID 502 //
12605 /* 31747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12606 /* 31750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12607 /* 31755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12608 /* 31758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12609 /* 31761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12610 /* 31764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12611 /* 31768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12612 /* 31772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12613 /* 31776 */ // MIs[0] sa
12614 /* 31776 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12615 /* 31779 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12616 /* 31784 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8493:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12617 /* 31784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
12618 /* 31787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12619 /* 31789 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12620 /* 31791 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12621 /* 31793 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12622 /* 31795 */ GIR_RootConstrainSelectedInstOperands,
12623 /* 31796 */ // GIR_Coverage, 502,
12624 /* 31796 */ GIR_EraseRootFromParent_Done,
12625 /* 31797 */ // Label 901: @31797
12626 /* 31797 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(31852), // Rule ID 507 //
12627 /* 31802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12628 /* 31805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12629 /* 31810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12630 /* 31813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12631 /* 31816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12632 /* 31819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12633 /* 31823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12634 /* 31827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12635 /* 31831 */ // MIs[0] sa
12636 /* 31831 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12637 /* 31834 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12638 /* 31839 */ // (intrinsic_wo_chain:{ *:[i32] } 8005:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12639 /* 31839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
12640 /* 31842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12641 /* 31844 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12642 /* 31846 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12643 /* 31848 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12644 /* 31850 */ GIR_RootConstrainSelectedInstOperands,
12645 /* 31851 */ // GIR_Coverage, 507,
12646 /* 31851 */ GIR_EraseRootFromParent_Done,
12647 /* 31852 */ // Label 902: @31852
12648 /* 31852 */ GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(31907), // Rule ID 508 //
12649 /* 31857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12650 /* 31860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12651 /* 31865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12652 /* 31868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12653 /* 31871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12654 /* 31874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12655 /* 31878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12656 /* 31882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12657 /* 31886 */ // MIs[0] sa
12658 /* 31886 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12659 /* 31889 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12660 /* 31894 */ // (intrinsic_wo_chain:{ *:[i32] } 8030:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12661 /* 31894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
12662 /* 31897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12663 /* 31899 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12664 /* 31901 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12665 /* 31903 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12666 /* 31905 */ GIR_RootConstrainSelectedInstOperands,
12667 /* 31906 */ // GIR_Coverage, 508,
12668 /* 31906 */ GIR_EraseRootFromParent_Done,
12669 /* 31907 */ // Label 903: @31907
12670 /* 31907 */ GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(31962), // Rule ID 509 //
12671 /* 31912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12672 /* 31915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12673 /* 31920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12674 /* 31923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12675 /* 31926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12676 /* 31929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12677 /* 31933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12678 /* 31937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12679 /* 31941 */ // MIs[0] sa
12680 /* 31941 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12681 /* 31944 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12682 /* 31949 */ // (intrinsic_wo_chain:{ *:[i32] } 8498:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12683 /* 31949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
12684 /* 31952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12685 /* 31954 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12686 /* 31956 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12687 /* 31958 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12688 /* 31960 */ GIR_RootConstrainSelectedInstOperands,
12689 /* 31961 */ // GIR_Coverage, 509,
12690 /* 31961 */ GIR_EraseRootFromParent_Done,
12691 /* 31962 */ // Label 904: @31962
12692 /* 31962 */ GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(32017), // Rule ID 977 //
12693 /* 31967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12694 /* 31970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
12695 /* 31975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12696 /* 31978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12697 /* 31981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12698 /* 31984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12699 /* 31988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12700 /* 31992 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12701 /* 31996 */ // MIs[0] n
12702 /* 31996 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12703 /* 31999 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
12704 /* 32004 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8530:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
12705 /* 32004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
12706 /* 32007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12707 /* 32009 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12708 /* 32011 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12709 /* 32013 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12710 /* 32015 */ GIR_RootConstrainSelectedInstOperands,
12711 /* 32016 */ // GIR_Coverage, 977,
12712 /* 32016 */ GIR_EraseRootFromParent_Done,
12713 /* 32017 */ // Label 905: @32017
12714 /* 32017 */ GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(32072), // Rule ID 978 //
12715 /* 32022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12716 /* 32025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
12717 /* 32030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12718 /* 32033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12719 /* 32036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12720 /* 32039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12721 /* 32043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12722 /* 32047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12723 /* 32051 */ // MIs[0] n
12724 /* 32051 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12725 /* 32054 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
12726 /* 32059 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8532:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
12727 /* 32059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
12728 /* 32062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12729 /* 32064 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12730 /* 32066 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12731 /* 32068 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12732 /* 32070 */ GIR_RootConstrainSelectedInstOperands,
12733 /* 32071 */ // GIR_Coverage, 978,
12734 /* 32071 */ GIR_EraseRootFromParent_Done,
12735 /* 32072 */ // Label 906: @32072
12736 /* 32072 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(32127), // Rule ID 979 //
12737 /* 32077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12738 /* 32080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
12739 /* 32085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12740 /* 32088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12741 /* 32091 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12742 /* 32094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12743 /* 32098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12744 /* 32102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12745 /* 32106 */ // MIs[0] n
12746 /* 32106 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12747 /* 32109 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
12748 /* 32114 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8533:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
12749 /* 32114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
12750 /* 32117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12751 /* 32119 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12752 /* 32121 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12753 /* 32123 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12754 /* 32125 */ GIR_RootConstrainSelectedInstOperands,
12755 /* 32126 */ // GIR_Coverage, 979,
12756 /* 32126 */ GIR_EraseRootFromParent_Done,
12757 /* 32127 */ // Label 907: @32127
12758 /* 32127 */ GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(32182), // Rule ID 980 //
12759 /* 32132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12760 /* 32135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
12761 /* 32140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12762 /* 32143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12763 /* 32146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12764 /* 32149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12765 /* 32153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12766 /* 32157 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12767 /* 32161 */ // MIs[0] n
12768 /* 32161 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12769 /* 32164 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
12770 /* 32169 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8531:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
12771 /* 32169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
12772 /* 32172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12773 /* 32174 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12774 /* 32176 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12775 /* 32178 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
12776 /* 32180 */ GIR_RootConstrainSelectedInstOperands,
12777 /* 32181 */ // GIR_Coverage, 980,
12778 /* 32181 */ GIR_EraseRootFromParent_Done,
12779 /* 32182 */ // Label 908: @32182
12780 /* 32182 */ GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(32237), // Rule ID 1372 //
12781 /* 32187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12782 /* 32190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
12783 /* 32195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12784 /* 32198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12785 /* 32201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12786 /* 32204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12787 /* 32208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12788 /* 32212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12789 /* 32216 */ // MIs[0] sa
12790 /* 32216 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12791 /* 32219 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12792 /* 32224 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12793 /* 32224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
12794 /* 32227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12795 /* 32229 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12796 /* 32231 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12797 /* 32233 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12798 /* 32235 */ GIR_RootConstrainSelectedInstOperands,
12799 /* 32236 */ // GIR_Coverage, 1372,
12800 /* 32236 */ GIR_EraseRootFromParent_Done,
12801 /* 32237 */ // Label 909: @32237
12802 /* 32237 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(32292), // Rule ID 1373 //
12803 /* 32242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12804 /* 32245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
12805 /* 32250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12806 /* 32253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12807 /* 32256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12808 /* 32259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12809 /* 32263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12810 /* 32267 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12811 /* 32271 */ // MIs[0] sa
12812 /* 32271 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12813 /* 32274 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12814 /* 32279 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8493:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12815 /* 32279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
12816 /* 32282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12817 /* 32284 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12818 /* 32286 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12819 /* 32288 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12820 /* 32290 */ GIR_RootConstrainSelectedInstOperands,
12821 /* 32291 */ // GIR_Coverage, 1373,
12822 /* 32291 */ GIR_EraseRootFromParent_Done,
12823 /* 32292 */ // Label 910: @32292
12824 /* 32292 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(32347), // Rule ID 1374 //
12825 /* 32297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12826 /* 32300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12827 /* 32305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12828 /* 32308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12829 /* 32311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12830 /* 32314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12831 /* 32318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12832 /* 32322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12833 /* 32326 */ // MIs[0] sa
12834 /* 32326 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12835 /* 32329 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12836 /* 32334 */ // (intrinsic_wo_chain:{ *:[i32] } 8498:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12837 /* 32334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
12838 /* 32337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12839 /* 32339 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12840 /* 32341 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12841 /* 32343 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12842 /* 32345 */ GIR_RootConstrainSelectedInstOperands,
12843 /* 32346 */ // GIR_Coverage, 1374,
12844 /* 32346 */ GIR_EraseRootFromParent_Done,
12845 /* 32347 */ // Label 911: @32347
12846 /* 32347 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(32402), // Rule ID 1375 //
12847 /* 32352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12848 /* 32355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12849 /* 32360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12850 /* 32363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12851 /* 32366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12852 /* 32369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12853 /* 32373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12854 /* 32377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12855 /* 32381 */ // MIs[0] sa
12856 /* 32381 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12857 /* 32384 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12858 /* 32389 */ // (intrinsic_wo_chain:{ *:[i32] } 8005:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12859 /* 32389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
12860 /* 32392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12861 /* 32394 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12862 /* 32396 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12863 /* 32398 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12864 /* 32400 */ GIR_RootConstrainSelectedInstOperands,
12865 /* 32401 */ // GIR_Coverage, 1375,
12866 /* 32401 */ GIR_EraseRootFromParent_Done,
12867 /* 32402 */ // Label 912: @32402
12868 /* 32402 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(32464), // Rule ID 1350 //
12869 /* 32407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12870 /* 32410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12871 /* 32415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12872 /* 32418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12873 /* 32421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12874 /* 32424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12875 /* 32428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12876 /* 32432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12877 /* 32436 */ // MIs[0] bp
12878 /* 32436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
12879 /* 32440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12880 /* 32444 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12881 /* 32448 */ // MIs[1] Operand 1
12882 /* 32448 */ // No operand predicates
12883 /* 32448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
12884 /* 32450 */ // (intrinsic_wo_chain:{ *:[i32] } 8030:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
12885 /* 32450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
12886 /* 32453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12887 /* 32455 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12888 /* 32457 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
12889 /* 32460 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12890 /* 32462 */ GIR_RootConstrainSelectedInstOperands,
12891 /* 32463 */ // GIR_Coverage, 1350,
12892 /* 32463 */ GIR_EraseRootFromParent_Done,
12893 /* 32464 */ // Label 913: @32464
12894 /* 32464 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(32518), // Rule ID 576 //
12895 /* 32469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12896 /* 32472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
12897 /* 32477 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12898 /* 32480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12899 /* 32483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12900 /* 32486 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12901 /* 32489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12902 /* 32493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12903 /* 32497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12904 /* 32501 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12905 /* 32505 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8039:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12906 /* 32505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
12907 /* 32508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12908 /* 32510 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12909 /* 32512 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12910 /* 32514 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12911 /* 32516 */ GIR_RootConstrainSelectedInstOperands,
12912 /* 32517 */ // GIR_Coverage, 576,
12913 /* 32517 */ GIR_EraseRootFromParent_Done,
12914 /* 32518 */ // Label 914: @32518
12915 /* 32518 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(32572), // Rule ID 577 //
12916 /* 32523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12917 /* 32526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
12918 /* 32531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12919 /* 32534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12920 /* 32537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12921 /* 32540 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12922 /* 32543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12923 /* 32547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12924 /* 32551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12925 /* 32555 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12926 /* 32559 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8041:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12927 /* 32559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
12928 /* 32562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12929 /* 32564 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12930 /* 32566 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12931 /* 32568 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12932 /* 32570 */ GIR_RootConstrainSelectedInstOperands,
12933 /* 32571 */ // GIR_Coverage, 577,
12934 /* 32571 */ GIR_EraseRootFromParent_Done,
12935 /* 32572 */ // Label 915: @32572
12936 /* 32572 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(32626), // Rule ID 578 //
12937 /* 32577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12938 /* 32580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
12939 /* 32585 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12940 /* 32588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12941 /* 32591 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12942 /* 32594 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12943 /* 32597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12944 /* 32601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12945 /* 32605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12946 /* 32609 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12947 /* 32613 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8042:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12948 /* 32613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
12949 /* 32616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12950 /* 32618 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12951 /* 32620 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12952 /* 32622 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12953 /* 32624 */ GIR_RootConstrainSelectedInstOperands,
12954 /* 32625 */ // GIR_Coverage, 578,
12955 /* 32625 */ GIR_EraseRootFromParent_Done,
12956 /* 32626 */ // Label 916: @32626
12957 /* 32626 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(32680), // Rule ID 579 //
12958 /* 32631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12959 /* 32634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
12960 /* 32639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12961 /* 32642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12962 /* 32645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12963 /* 32648 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12964 /* 32651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12965 /* 32655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12966 /* 32659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12967 /* 32663 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12968 /* 32667 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8040:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12969 /* 32667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
12970 /* 32670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12971 /* 32672 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12972 /* 32674 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12973 /* 32676 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12974 /* 32678 */ GIR_RootConstrainSelectedInstOperands,
12975 /* 32679 */ // GIR_Coverage, 579,
12976 /* 32679 */ GIR_EraseRootFromParent_Done,
12977 /* 32680 */ // Label 917: @32680
12978 /* 32680 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(32734), // Rule ID 584 //
12979 /* 32685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
12980 /* 32688 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
12981 /* 32693 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12982 /* 32696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12983 /* 32699 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12984 /* 32702 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12985 /* 32705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12986 /* 32709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12987 /* 32713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12988 /* 32717 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12989 /* 32721 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8047:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12990 /* 32721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
12991 /* 32724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12992 /* 32726 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12993 /* 32728 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12994 /* 32730 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12995 /* 32732 */ GIR_RootConstrainSelectedInstOperands,
12996 /* 32733 */ // GIR_Coverage, 584,
12997 /* 32733 */ GIR_EraseRootFromParent_Done,
12998 /* 32734 */ // Label 918: @32734
12999 /* 32734 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(32788), // Rule ID 585 //
13000 /* 32739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13001 /* 32742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
13002 /* 32747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13003 /* 32750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13004 /* 32753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13005 /* 32756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13006 /* 32759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13007 /* 32763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13008 /* 32767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13009 /* 32771 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13010 /* 32775 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8049:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13011 /* 32775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
13012 /* 32778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13013 /* 32780 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13014 /* 32782 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13015 /* 32784 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13016 /* 32786 */ GIR_RootConstrainSelectedInstOperands,
13017 /* 32787 */ // GIR_Coverage, 585,
13018 /* 32787 */ GIR_EraseRootFromParent_Done,
13019 /* 32788 */ // Label 919: @32788
13020 /* 32788 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(32842), // Rule ID 586 //
13021 /* 32793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13022 /* 32796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
13023 /* 32801 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13024 /* 32804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13025 /* 32807 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13026 /* 32810 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13027 /* 32813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13028 /* 32817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13029 /* 32821 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13030 /* 32825 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13031 /* 32829 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8050:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13032 /* 32829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
13033 /* 32832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13034 /* 32834 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13035 /* 32836 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13036 /* 32838 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13037 /* 32840 */ GIR_RootConstrainSelectedInstOperands,
13038 /* 32841 */ // GIR_Coverage, 586,
13039 /* 32841 */ GIR_EraseRootFromParent_Done,
13040 /* 32842 */ // Label 920: @32842
13041 /* 32842 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(32896), // Rule ID 587 //
13042 /* 32847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13043 /* 32850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
13044 /* 32855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13045 /* 32858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13046 /* 32861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
13047 /* 32864 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
13048 /* 32867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13049 /* 32871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13050 /* 32875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13051 /* 32879 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13052 /* 32883 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8048:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
13053 /* 32883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
13054 /* 32886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13055 /* 32888 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13056 /* 32890 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13057 /* 32892 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13058 /* 32894 */ GIR_RootConstrainSelectedInstOperands,
13059 /* 32895 */ // GIR_Coverage, 587,
13060 /* 32895 */ GIR_EraseRootFromParent_Done,
13061 /* 32896 */ // Label 921: @32896
13062 /* 32896 */ GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(32950), // Rule ID 682 //
13063 /* 32901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13064 /* 32904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
13065 /* 32909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13066 /* 32912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13067 /* 32915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13068 /* 32918 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13069 /* 32921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13070 /* 32925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13071 /* 32929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13072 /* 32933 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13073 /* 32937 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8168:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13074 /* 32937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
13075 /* 32940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13076 /* 32942 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13077 /* 32944 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13078 /* 32946 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13079 /* 32948 */ GIR_RootConstrainSelectedInstOperands,
13080 /* 32949 */ // GIR_Coverage, 682,
13081 /* 32949 */ GIR_EraseRootFromParent_Done,
13082 /* 32950 */ // Label 922: @32950
13083 /* 32950 */ GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(33004), // Rule ID 683 //
13084 /* 32955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13085 /* 32958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
13086 /* 32963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13087 /* 32966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13088 /* 32969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13089 /* 32972 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13090 /* 32975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13091 /* 32979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13092 /* 32983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13093 /* 32987 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13094 /* 32991 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8169:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13095 /* 32991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
13096 /* 32994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13097 /* 32996 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13098 /* 32998 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13099 /* 33000 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13100 /* 33002 */ GIR_RootConstrainSelectedInstOperands,
13101 /* 33003 */ // GIR_Coverage, 683,
13102 /* 33003 */ GIR_EraseRootFromParent_Done,
13103 /* 33004 */ // Label 923: @33004
13104 /* 33004 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(33058), // Rule ID 684 //
13105 /* 33009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13106 /* 33012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
13107 /* 33017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13108 /* 33020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13109 /* 33023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13110 /* 33026 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13111 /* 33029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13112 /* 33033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13113 /* 33037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13114 /* 33041 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13115 /* 33045 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8167:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13116 /* 33045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
13117 /* 33048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13118 /* 33050 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13119 /* 33052 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13120 /* 33054 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13121 /* 33056 */ GIR_RootConstrainSelectedInstOperands,
13122 /* 33057 */ // GIR_Coverage, 684,
13123 /* 33057 */ GIR_EraseRootFromParent_Done,
13124 /* 33058 */ // Label 924: @33058
13125 /* 33058 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(33112), // Rule ID 685 //
13126 /* 33063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13127 /* 33066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
13128 /* 33071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13129 /* 33074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13130 /* 33077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13131 /* 33080 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13132 /* 33083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13133 /* 33087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13134 /* 33091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13135 /* 33095 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13136 /* 33099 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8171:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13137 /* 33099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
13138 /* 33102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13139 /* 33104 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13140 /* 33106 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13141 /* 33108 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13142 /* 33110 */ GIR_RootConstrainSelectedInstOperands,
13143 /* 33111 */ // GIR_Coverage, 685,
13144 /* 33111 */ GIR_EraseRootFromParent_Done,
13145 /* 33112 */ // Label 925: @33112
13146 /* 33112 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(33166), // Rule ID 686 //
13147 /* 33117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13148 /* 33120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
13149 /* 33125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13150 /* 33128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13151 /* 33131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13152 /* 33134 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13153 /* 33137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13154 /* 33141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13155 /* 33145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13156 /* 33149 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13157 /* 33153 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8172:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13158 /* 33153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
13159 /* 33156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13160 /* 33158 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13161 /* 33160 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13162 /* 33162 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13163 /* 33164 */ GIR_RootConstrainSelectedInstOperands,
13164 /* 33165 */ // GIR_Coverage, 686,
13165 /* 33165 */ GIR_EraseRootFromParent_Done,
13166 /* 33166 */ // Label 926: @33166
13167 /* 33166 */ GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(33220), // Rule ID 687 //
13168 /* 33171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13169 /* 33174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
13170 /* 33179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13171 /* 33182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13172 /* 33185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13173 /* 33188 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13174 /* 33191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13175 /* 33195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13176 /* 33199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13177 /* 33203 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13178 /* 33207 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8170:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13179 /* 33207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
13180 /* 33210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13181 /* 33212 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13182 /* 33214 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13183 /* 33216 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13184 /* 33218 */ GIR_RootConstrainSelectedInstOperands,
13185 /* 33219 */ // GIR_Coverage, 687,
13186 /* 33219 */ GIR_EraseRootFromParent_Done,
13187 /* 33220 */ // Label 927: @33220
13188 /* 33220 */ GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(33274), // Rule ID 688 //
13189 /* 33225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13190 /* 33228 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
13191 /* 33233 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13192 /* 33236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13193 /* 33239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13194 /* 33242 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13195 /* 33245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13196 /* 33249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13197 /* 33253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13198 /* 33257 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13199 /* 33261 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8188:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13200 /* 33261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
13201 /* 33264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13202 /* 33266 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13203 /* 33268 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13204 /* 33270 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13205 /* 33272 */ GIR_RootConstrainSelectedInstOperands,
13206 /* 33273 */ // GIR_Coverage, 688,
13207 /* 33273 */ GIR_EraseRootFromParent_Done,
13208 /* 33274 */ // Label 928: @33274
13209 /* 33274 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(33328), // Rule ID 689 //
13210 /* 33279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13211 /* 33282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
13212 /* 33287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13213 /* 33290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13214 /* 33293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13215 /* 33296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13216 /* 33299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13217 /* 33303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13218 /* 33307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13219 /* 33311 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13220 /* 33315 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8189:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13221 /* 33315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
13222 /* 33318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13223 /* 33320 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13224 /* 33322 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13225 /* 33324 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13226 /* 33326 */ GIR_RootConstrainSelectedInstOperands,
13227 /* 33327 */ // GIR_Coverage, 689,
13228 /* 33327 */ GIR_EraseRootFromParent_Done,
13229 /* 33328 */ // Label 929: @33328
13230 /* 33328 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(33382), // Rule ID 690 //
13231 /* 33333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13232 /* 33336 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
13233 /* 33341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13234 /* 33344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13235 /* 33347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13236 /* 33350 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13237 /* 33353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13238 /* 33357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13239 /* 33361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13240 /* 33365 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13241 /* 33369 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8187:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13242 /* 33369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
13243 /* 33372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13244 /* 33374 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13245 /* 33376 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13246 /* 33378 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13247 /* 33380 */ GIR_RootConstrainSelectedInstOperands,
13248 /* 33381 */ // GIR_Coverage, 690,
13249 /* 33381 */ GIR_EraseRootFromParent_Done,
13250 /* 33382 */ // Label 930: @33382
13251 /* 33382 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(33436), // Rule ID 691 //
13252 /* 33387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13253 /* 33390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
13254 /* 33395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13255 /* 33398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13256 /* 33401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13257 /* 33404 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
13258 /* 33407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13259 /* 33411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13260 /* 33415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13261 /* 33419 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13262 /* 33423 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8191:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
13263 /* 33423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
13264 /* 33426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13265 /* 33428 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13266 /* 33430 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13267 /* 33432 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13268 /* 33434 */ GIR_RootConstrainSelectedInstOperands,
13269 /* 33435 */ // GIR_Coverage, 691,
13270 /* 33435 */ GIR_EraseRootFromParent_Done,
13271 /* 33436 */ // Label 931: @33436
13272 /* 33436 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(33490), // Rule ID 692 //
13273 /* 33441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13274 /* 33444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
13275 /* 33449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13276 /* 33452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13277 /* 33455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13278 /* 33458 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13279 /* 33461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13280 /* 33465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13281 /* 33469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13282 /* 33473 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13283 /* 33477 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8192:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13284 /* 33477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
13285 /* 33480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13286 /* 33482 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13287 /* 33484 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13288 /* 33486 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13289 /* 33488 */ GIR_RootConstrainSelectedInstOperands,
13290 /* 33489 */ // GIR_Coverage, 692,
13291 /* 33489 */ GIR_EraseRootFromParent_Done,
13292 /* 33490 */ // Label 932: @33490
13293 /* 33490 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(33544), // Rule ID 693 //
13294 /* 33495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13295 /* 33498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
13296 /* 33503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13297 /* 33506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13298 /* 33509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13299 /* 33512 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13300 /* 33515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13301 /* 33519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13302 /* 33523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13303 /* 33527 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13304 /* 33531 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8190:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13305 /* 33531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
13306 /* 33534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13307 /* 33536 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13308 /* 33538 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13309 /* 33540 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13310 /* 33542 */ GIR_RootConstrainSelectedInstOperands,
13311 /* 33543 */ // GIR_Coverage, 693,
13312 /* 33543 */ GIR_EraseRootFromParent_Done,
13313 /* 33544 */ // Label 933: @33544
13314 /* 33544 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(33598), // Rule ID 860 //
13315 /* 33549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13316 /* 33552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
13317 /* 33557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13318 /* 33560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13319 /* 33563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13320 /* 33566 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13321 /* 33569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13322 /* 33573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13323 /* 33577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13324 /* 33581 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13325 /* 33585 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8358:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13326 /* 33585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
13327 /* 33588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13328 /* 33590 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13329 /* 33592 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13330 /* 33594 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13331 /* 33596 */ GIR_RootConstrainSelectedInstOperands,
13332 /* 33597 */ // GIR_Coverage, 860,
13333 /* 33597 */ GIR_EraseRootFromParent_Done,
13334 /* 33598 */ // Label 934: @33598
13335 /* 33598 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(33652), // Rule ID 861 //
13336 /* 33603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13337 /* 33606 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
13338 /* 33611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13339 /* 33614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13340 /* 33617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13341 /* 33620 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13342 /* 33623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13343 /* 33627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13344 /* 33631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13345 /* 33635 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13346 /* 33639 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8359:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13347 /* 33639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
13348 /* 33642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13349 /* 33644 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13350 /* 33646 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13351 /* 33648 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13352 /* 33650 */ GIR_RootConstrainSelectedInstOperands,
13353 /* 33651 */ // GIR_Coverage, 861,
13354 /* 33651 */ GIR_EraseRootFromParent_Done,
13355 /* 33652 */ // Label 935: @33652
13356 /* 33652 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(33706), // Rule ID 862 //
13357 /* 33657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13358 /* 33660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
13359 /* 33665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13360 /* 33668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13361 /* 33671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13362 /* 33674 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13363 /* 33677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13364 /* 33681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13365 /* 33685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13366 /* 33689 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13367 /* 33693 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8360:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13368 /* 33693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
13369 /* 33696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13370 /* 33698 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13371 /* 33700 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13372 /* 33702 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13373 /* 33704 */ GIR_RootConstrainSelectedInstOperands,
13374 /* 33705 */ // GIR_Coverage, 862,
13375 /* 33705 */ GIR_EraseRootFromParent_Done,
13376 /* 33706 */ // Label 936: @33706
13377 /* 33706 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(33760), // Rule ID 863 //
13378 /* 33711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13379 /* 33714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
13380 /* 33719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13381 /* 33722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13382 /* 33725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13383 /* 33728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13384 /* 33731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13385 /* 33735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13386 /* 33739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13387 /* 33743 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13388 /* 33747 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8361:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13389 /* 33747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
13390 /* 33750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13391 /* 33752 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13392 /* 33754 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13393 /* 33756 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13394 /* 33758 */ GIR_RootConstrainSelectedInstOperands,
13395 /* 33759 */ // GIR_Coverage, 863,
13396 /* 33759 */ GIR_EraseRootFromParent_Done,
13397 /* 33760 */ // Label 937: @33760
13398 /* 33760 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(33814), // Rule ID 916 //
13399 /* 33765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13400 /* 33768 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
13401 /* 33773 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13402 /* 33776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13403 /* 33779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13404 /* 33782 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13405 /* 33785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13406 /* 33789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13407 /* 33793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13408 /* 33797 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13409 /* 33801 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8422:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13410 /* 33801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
13411 /* 33804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13412 /* 33806 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13413 /* 33808 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13414 /* 33810 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13415 /* 33812 */ GIR_RootConstrainSelectedInstOperands,
13416 /* 33813 */ // GIR_Coverage, 916,
13417 /* 33813 */ GIR_EraseRootFromParent_Done,
13418 /* 33814 */ // Label 938: @33814
13419 /* 33814 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(33868), // Rule ID 917 //
13420 /* 33819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13421 /* 33822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
13422 /* 33827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13423 /* 33830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13424 /* 33833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13425 /* 33836 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13426 /* 33839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13427 /* 33843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13428 /* 33847 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13429 /* 33851 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13430 /* 33855 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8423:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13431 /* 33855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
13432 /* 33858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13433 /* 33860 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13434 /* 33862 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13435 /* 33864 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13436 /* 33866 */ GIR_RootConstrainSelectedInstOperands,
13437 /* 33867 */ // GIR_Coverage, 917,
13438 /* 33867 */ GIR_EraseRootFromParent_Done,
13439 /* 33868 */ // Label 939: @33868
13440 /* 33868 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(33922), // Rule ID 918 //
13441 /* 33873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13442 /* 33876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
13443 /* 33881 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13444 /* 33884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13445 /* 33887 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13446 /* 33890 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
13447 /* 33893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13448 /* 33897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13449 /* 33901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13450 /* 33905 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13451 /* 33909 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8424:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
13452 /* 33909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
13453 /* 33912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13454 /* 33914 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13455 /* 33916 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13456 /* 33918 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13457 /* 33920 */ GIR_RootConstrainSelectedInstOperands,
13458 /* 33921 */ // GIR_Coverage, 918,
13459 /* 33921 */ GIR_EraseRootFromParent_Done,
13460 /* 33922 */ // Label 940: @33922
13461 /* 33922 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(33976), // Rule ID 919 //
13462 /* 33927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13463 /* 33930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
13464 /* 33935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13465 /* 33938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13466 /* 33941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13467 /* 33944 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
13468 /* 33947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13469 /* 33951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13470 /* 33955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13471 /* 33959 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13472 /* 33963 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8425:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
13473 /* 33963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
13474 /* 33966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13475 /* 33968 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13476 /* 33970 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13477 /* 33972 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
13478 /* 33974 */ GIR_RootConstrainSelectedInstOperands,
13479 /* 33975 */ // GIR_Coverage, 919,
13480 /* 33975 */ GIR_EraseRootFromParent_Done,
13481 /* 33976 */ // Label 941: @33976
13482 /* 33976 */ GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(34030), // Rule ID 973 //
13483 /* 33981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13484 /* 33984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
13485 /* 33989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
13486 /* 33992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
13487 /* 33995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
13488 /* 33998 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13489 /* 34001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13490 /* 34005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13491 /* 34009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
13492 /* 34013 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13493 /* 34017 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8526:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13494 /* 34017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
13495 /* 34020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13496 /* 34022 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13497 /* 34024 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13498 /* 34026 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13499 /* 34028 */ GIR_RootConstrainSelectedInstOperands,
13500 /* 34029 */ // GIR_Coverage, 973,
13501 /* 34029 */ GIR_EraseRootFromParent_Done,
13502 /* 34030 */ // Label 942: @34030
13503 /* 34030 */ GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(34084), // Rule ID 974 //
13504 /* 34035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13505 /* 34038 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
13506 /* 34043 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
13507 /* 34046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
13508 /* 34049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
13509 /* 34052 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13510 /* 34055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13511 /* 34059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13512 /* 34063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
13513 /* 34067 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13514 /* 34071 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8528:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13515 /* 34071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
13516 /* 34074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13517 /* 34076 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13518 /* 34078 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13519 /* 34080 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13520 /* 34082 */ GIR_RootConstrainSelectedInstOperands,
13521 /* 34083 */ // GIR_Coverage, 974,
13522 /* 34083 */ GIR_EraseRootFromParent_Done,
13523 /* 34084 */ // Label 943: @34084
13524 /* 34084 */ GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(34138), // Rule ID 975 //
13525 /* 34089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13526 /* 34092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
13527 /* 34097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
13528 /* 34100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
13529 /* 34103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
13530 /* 34106 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13531 /* 34109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13532 /* 34113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13533 /* 34117 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
13534 /* 34121 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13535 /* 34125 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8529:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13536 /* 34125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
13537 /* 34128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13538 /* 34130 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13539 /* 34132 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13540 /* 34134 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13541 /* 34136 */ GIR_RootConstrainSelectedInstOperands,
13542 /* 34137 */ // GIR_Coverage, 975,
13543 /* 34137 */ GIR_EraseRootFromParent_Done,
13544 /* 34138 */ // Label 944: @34138
13545 /* 34138 */ GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(34192), // Rule ID 976 //
13546 /* 34143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
13547 /* 34146 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
13548 /* 34151 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
13549 /* 34154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
13550 /* 34157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
13551 /* 34160 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
13552 /* 34163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13553 /* 34167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13554 /* 34171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
13555 /* 34175 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13556 /* 34179 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8527:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
13557 /* 34179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
13558 /* 34182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
13559 /* 34184 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
13560 /* 34186 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
13561 /* 34188 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
13562 /* 34190 */ GIR_RootConstrainSelectedInstOperands,
13563 /* 34191 */ // GIR_Coverage, 976,
13564 /* 34191 */ GIR_EraseRootFromParent_Done,
13565 /* 34192 */ // Label 945: @34192
13566 /* 34192 */ GIM_Reject,
13567 /* 34193 */ // Label 899: @34193
13568 /* 34193 */ GIM_Reject,
13569 /* 34194 */ // Label 30: @34194
13570 /* 34194 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(34225), // Rule ID 378 //
13571 /* 34199 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
13572 /* 34202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
13573 /* 34207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13574 /* 34210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13575 /* 34214 */ // (intrinsic_w_chain:{ *:[i32] } 8073:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
13576 /* 34214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
13577 /* 34217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13578 /* 34219 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13579 /* 34223 */ GIR_RootConstrainSelectedInstOperands,
13580 /* 34224 */ // GIR_Coverage, 378,
13581 /* 34224 */ GIR_EraseRootFromParent_Done,
13582 /* 34225 */ // Label 946: @34225
13583 /* 34225 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(35162),
13584 /* 34230 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
13585 /* 34233 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(34274), // Rule ID 465 //
13586 /* 34238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13587 /* 34241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
13588 /* 34246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13589 /* 34249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13590 /* 34253 */ // MIs[0] mask
13591 /* 34253 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13592 /* 34256 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
13593 /* 34261 */ // (intrinsic_w_chain:{ *:[i32] } 8500:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
13594 /* 34261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
13595 /* 34264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13596 /* 34266 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13597 /* 34268 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13598 /* 34272 */ GIR_RootConstrainSelectedInstOperands,
13599 /* 34273 */ // GIR_Coverage, 465,
13600 /* 34273 */ GIR_EraseRootFromParent_Done,
13601 /* 34274 */ // Label 948: @34274
13602 /* 34274 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(34310), // Rule ID 1310 //
13603 /* 34279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13604 /* 34282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
13605 /* 34287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13606 /* 34290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13607 /* 34294 */ // MIs[0] mask
13608 /* 34294 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13609 /* 34297 */ // (intrinsic_w_chain:{ *:[i32] } 8500:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
13610 /* 34297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
13611 /* 34300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13612 /* 34302 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13613 /* 34304 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13614 /* 34308 */ GIR_RootConstrainSelectedInstOperands,
13615 /* 34309 */ // GIR_Coverage, 1310,
13616 /* 34309 */ GIR_EraseRootFromParent_Done,
13617 /* 34310 */ // Label 949: @34310
13618 /* 34310 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(34351), // Rule ID 466 //
13619 /* 34315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
13620 /* 34318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
13621 /* 34323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13622 /* 34326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13623 /* 34330 */ // MIs[0] mask
13624 /* 34330 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13625 /* 34333 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
13626 /* 34338 */ // (intrinsic_void 8629:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
13627 /* 34338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
13628 /* 34341 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13629 /* 34343 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13630 /* 34345 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13631 /* 34349 */ GIR_RootConstrainSelectedInstOperands,
13632 /* 34350 */ // GIR_Coverage, 466,
13633 /* 34350 */ GIR_EraseRootFromParent_Done,
13634 /* 34351 */ // Label 950: @34351
13635 /* 34351 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(34387), // Rule ID 1321 //
13636 /* 34356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13637 /* 34359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
13638 /* 34364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13639 /* 34367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13640 /* 34371 */ // MIs[0] mask
13641 /* 34371 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
13642 /* 34374 */ // (intrinsic_void 8629:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
13643 /* 34374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
13644 /* 34377 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
13645 /* 34379 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
13646 /* 34381 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13647 /* 34385 */ GIR_RootConstrainSelectedInstOperands,
13648 /* 34386 */ // GIR_Coverage, 1321,
13649 /* 34386 */ GIR_EraseRootFromParent_Done,
13650 /* 34387 */ // Label 951: @34387
13651 /* 34387 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(34430), // Rule ID 387 //
13652 /* 34392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13653 /* 34395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
13654 /* 34400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13655 /* 34403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13656 /* 34406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13657 /* 34410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13658 /* 34414 */ // (intrinsic_w_chain:{ *:[v2i16] } 7961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
13659 /* 34414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
13660 /* 34417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13661 /* 34419 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13662 /* 34421 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13663 /* 34424 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13664 /* 34428 */ GIR_RootConstrainSelectedInstOperands,
13665 /* 34429 */ // GIR_Coverage, 387,
13666 /* 34429 */ GIR_EraseRootFromParent_Done,
13667 /* 34430 */ // Label 952: @34430
13668 /* 34430 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(34473), // Rule ID 388 //
13669 /* 34435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13670 /* 34438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13671 /* 34443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13672 /* 34446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13673 /* 34449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13674 /* 34453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13675 /* 34457 */ // (intrinsic_w_chain:{ *:[i32] } 7963:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
13676 /* 34457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
13677 /* 34460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13678 /* 34462 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13679 /* 34464 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13680 /* 34467 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13681 /* 34471 */ GIR_RootConstrainSelectedInstOperands,
13682 /* 34472 */ // GIR_Coverage, 388,
13683 /* 34472 */ GIR_EraseRootFromParent_Done,
13684 /* 34473 */ // Label 953: @34473
13685 /* 34473 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(34516), // Rule ID 474 //
13686 /* 34478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13687 /* 34481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13688 /* 34486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13689 /* 34489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13690 /* 34492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13691 /* 34496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13692 /* 34500 */ // (intrinsic_w_chain:{ *:[v4i8] } 7962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
13693 /* 34500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
13694 /* 34503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13695 /* 34505 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13696 /* 34507 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13697 /* 34510 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13698 /* 34514 */ GIR_RootConstrainSelectedInstOperands,
13699 /* 34515 */ // GIR_Coverage, 474,
13700 /* 34515 */ GIR_EraseRootFromParent_Done,
13701 /* 34516 */ // Label 954: @34516
13702 /* 34516 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(34559), // Rule ID 1253 //
13703 /* 34521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13704 /* 34524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
13705 /* 34529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13706 /* 34532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13707 /* 34535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13708 /* 34539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13709 /* 34543 */ // (intrinsic_w_chain:{ *:[v2i16] } 7961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
13710 /* 34543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
13711 /* 34546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13712 /* 34548 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13713 /* 34550 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13714 /* 34553 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13715 /* 34557 */ GIR_RootConstrainSelectedInstOperands,
13716 /* 34558 */ // GIR_Coverage, 1253,
13717 /* 34558 */ GIR_EraseRootFromParent_Done,
13718 /* 34559 */ // Label 955: @34559
13719 /* 34559 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(34602), // Rule ID 1254 //
13720 /* 34564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13721 /* 34567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
13722 /* 34572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13723 /* 34575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13724 /* 34578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13725 /* 34582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13726 /* 34586 */ // (intrinsic_w_chain:{ *:[i32] } 7963:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
13727 /* 34586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
13728 /* 34589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13729 /* 34591 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13730 /* 34593 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13731 /* 34596 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13732 /* 34600 */ GIR_RootConstrainSelectedInstOperands,
13733 /* 34601 */ // GIR_Coverage, 1254,
13734 /* 34601 */ GIR_EraseRootFromParent_Done,
13735 /* 34602 */ // Label 956: @34602
13736 /* 34602 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(34645), // Rule ID 1334 //
13737 /* 34607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13738 /* 34610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
13739 /* 34615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13740 /* 34618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13741 /* 34621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13742 /* 34625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13743 /* 34629 */ // (intrinsic_w_chain:{ *:[v4i8] } 7962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
13744 /* 34629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
13745 /* 34632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13746 /* 34634 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13747 /* 34636 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13748 /* 34639 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13749 /* 34643 */ GIR_RootConstrainSelectedInstOperands,
13750 /* 34644 */ // GIR_Coverage, 1334,
13751 /* 34644 */ GIR_EraseRootFromParent_Done,
13752 /* 34645 */ // Label 957: @34645
13753 /* 34645 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(34688), // Rule ID 441 //
13754 /* 34650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13755 /* 34653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13756 /* 34658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13757 /* 34661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13758 /* 34664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13759 /* 34668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13760 /* 34672 */ // (intrinsic_void 8139:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13761 /* 34672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
13762 /* 34675 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13763 /* 34677 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13764 /* 34679 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13765 /* 34682 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13766 /* 34686 */ GIR_RootConstrainSelectedInstOperands,
13767 /* 34687 */ // GIR_Coverage, 441,
13768 /* 34687 */ GIR_EraseRootFromParent_Done,
13769 /* 34688 */ // Label 958: @34688
13770 /* 34688 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(34731), // Rule ID 442 //
13771 /* 34693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13772 /* 34696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13773 /* 34701 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13774 /* 34704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13775 /* 34707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13776 /* 34711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13777 /* 34715 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13778 /* 34715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
13779 /* 34718 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13780 /* 34720 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13781 /* 34722 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13782 /* 34725 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13783 /* 34729 */ GIR_RootConstrainSelectedInstOperands,
13784 /* 34730 */ // GIR_Coverage, 442,
13785 /* 34730 */ GIR_EraseRootFromParent_Done,
13786 /* 34731 */ // Label 959: @34731
13787 /* 34731 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(34774), // Rule ID 443 //
13788 /* 34736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13789 /* 34739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13790 /* 34744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13791 /* 34747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13792 /* 34750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13793 /* 34754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13794 /* 34758 */ // (intrinsic_void 8140:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13795 /* 34758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
13796 /* 34761 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13797 /* 34763 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13798 /* 34765 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13799 /* 34768 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13800 /* 34772 */ GIR_RootConstrainSelectedInstOperands,
13801 /* 34773 */ // GIR_Coverage, 443,
13802 /* 34773 */ GIR_EraseRootFromParent_Done,
13803 /* 34774 */ // Label 960: @34774
13804 /* 34774 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(34817), // Rule ID 447 //
13805 /* 34779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13806 /* 34782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13807 /* 34787 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13808 /* 34790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13809 /* 34793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13810 /* 34797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13811 /* 34801 */ // (intrinsic_void 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13812 /* 34801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
13813 /* 34804 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13814 /* 34806 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13815 /* 34808 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13816 /* 34811 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13817 /* 34815 */ GIR_RootConstrainSelectedInstOperands,
13818 /* 34816 */ // GIR_Coverage, 447,
13819 /* 34816 */ GIR_EraseRootFromParent_Done,
13820 /* 34817 */ // Label 961: @34817
13821 /* 34817 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(34860), // Rule ID 448 //
13822 /* 34822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13823 /* 34825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13824 /* 34830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13825 /* 34833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13826 /* 34836 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13827 /* 34840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13828 /* 34844 */ // (intrinsic_void 8132:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13829 /* 34844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
13830 /* 34847 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13831 /* 34849 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13832 /* 34851 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13833 /* 34854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13834 /* 34858 */ GIR_RootConstrainSelectedInstOperands,
13835 /* 34859 */ // GIR_Coverage, 448,
13836 /* 34859 */ GIR_EraseRootFromParent_Done,
13837 /* 34860 */ // Label 962: @34860
13838 /* 34860 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(34903), // Rule ID 449 //
13839 /* 34865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13840 /* 34868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13841 /* 34873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13842 /* 34876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13843 /* 34879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13844 /* 34883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13845 /* 34887 */ // (intrinsic_void 8131:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13846 /* 34887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
13847 /* 34890 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13848 /* 34892 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13849 /* 34894 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13850 /* 34897 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13851 /* 34901 */ GIR_RootConstrainSelectedInstOperands,
13852 /* 34902 */ // GIR_Coverage, 449,
13853 /* 34902 */ GIR_EraseRootFromParent_Done,
13854 /* 34903 */ // Label 963: @34903
13855 /* 34903 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(34946), // Rule ID 1325 //
13856 /* 34908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13857 /* 34911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
13858 /* 34916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13859 /* 34919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13860 /* 34922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13861 /* 34926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13862 /* 34930 */ // (intrinsic_void 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13863 /* 34930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
13864 /* 34933 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13865 /* 34935 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13866 /* 34937 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13867 /* 34940 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13868 /* 34944 */ GIR_RootConstrainSelectedInstOperands,
13869 /* 34945 */ // GIR_Coverage, 1325,
13870 /* 34945 */ GIR_EraseRootFromParent_Done,
13871 /* 34946 */ // Label 964: @34946
13872 /* 34946 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(34989), // Rule ID 1326 //
13873 /* 34951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13874 /* 34954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
13875 /* 34959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13876 /* 34962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13877 /* 34965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13878 /* 34969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13879 /* 34973 */ // (intrinsic_void 8132:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13880 /* 34973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
13881 /* 34976 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13882 /* 34978 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13883 /* 34980 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13884 /* 34983 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13885 /* 34987 */ GIR_RootConstrainSelectedInstOperands,
13886 /* 34988 */ // GIR_Coverage, 1326,
13887 /* 34988 */ GIR_EraseRootFromParent_Done,
13888 /* 34989 */ // Label 965: @34989
13889 /* 34989 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(35032), // Rule ID 1327 //
13890 /* 34994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13891 /* 34997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13892 /* 35002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13893 /* 35005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13894 /* 35008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13895 /* 35012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13896 /* 35016 */ // (intrinsic_void 8131:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13897 /* 35016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
13898 /* 35019 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13899 /* 35021 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13900 /* 35023 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13901 /* 35026 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13902 /* 35030 */ GIR_RootConstrainSelectedInstOperands,
13903 /* 35031 */ // GIR_Coverage, 1327,
13904 /* 35031 */ GIR_EraseRootFromParent_Done,
13905 /* 35032 */ // Label 966: @35032
13906 /* 35032 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(35075), // Rule ID 1331 //
13907 /* 35037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13908 /* 35040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13909 /* 35045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13910 /* 35048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13911 /* 35051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13912 /* 35055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13913 /* 35059 */ // (intrinsic_void 8139:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13914 /* 35059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
13915 /* 35062 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13916 /* 35064 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13917 /* 35066 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13918 /* 35069 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13919 /* 35073 */ GIR_RootConstrainSelectedInstOperands,
13920 /* 35074 */ // GIR_Coverage, 1331,
13921 /* 35074 */ GIR_EraseRootFromParent_Done,
13922 /* 35075 */ // Label 967: @35075
13923 /* 35075 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(35118), // Rule ID 1332 //
13924 /* 35080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13925 /* 35083 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13926 /* 35088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13927 /* 35091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13928 /* 35094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13929 /* 35098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13930 /* 35102 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13931 /* 35102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13932 /* 35105 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13933 /* 35107 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13934 /* 35109 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13935 /* 35112 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13936 /* 35116 */ GIR_RootConstrainSelectedInstOperands,
13937 /* 35117 */ // GIR_Coverage, 1332,
13938 /* 35117 */ GIR_EraseRootFromParent_Done,
13939 /* 35118 */ // Label 968: @35118
13940 /* 35118 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35161), // Rule ID 1333 //
13941 /* 35123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13942 /* 35126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13943 /* 35131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13944 /* 35134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13945 /* 35137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13946 /* 35141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13947 /* 35145 */ // (intrinsic_void 8140:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13948 /* 35145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13949 /* 35148 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13950 /* 35150 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13951 /* 35152 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13952 /* 35155 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13953 /* 35159 */ GIR_RootConstrainSelectedInstOperands,
13954 /* 35160 */ // GIR_Coverage, 1333,
13955 /* 35160 */ GIR_EraseRootFromParent_Done,
13956 /* 35161 */ // Label 969: @35161
13957 /* 35161 */ GIM_Reject,
13958 /* 35162 */ // Label 947: @35162
13959 /* 35162 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(39287),
13960 /* 35167 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
13961 /* 35170 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(35234), // Rule ID 406 //
13962 /* 35175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13963 /* 35178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13964 /* 35183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13965 /* 35186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13966 /* 35189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13967 /* 35192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13968 /* 35196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13969 /* 35200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13970 /* 35204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13971 /* 35208 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13972 /* 35212 */ // MIs[1] Operand 1
13973 /* 35212 */ // No operand predicates
13974 /* 35212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13975 /* 35214 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13976 /* 35214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
13977 /* 35217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13978 /* 35219 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13979 /* 35221 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13980 /* 35224 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13981 /* 35227 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13982 /* 35232 */ GIR_RootConstrainSelectedInstOperands,
13983 /* 35233 */ // GIR_Coverage, 406,
13984 /* 35233 */ GIR_EraseRootFromParent_Done,
13985 /* 35234 */ // Label 971: @35234
13986 /* 35234 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35298), // Rule ID 411 //
13987 /* 35239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13988 /* 35242 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13989 /* 35247 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13990 /* 35250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13991 /* 35253 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13992 /* 35256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13993 /* 35260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13994 /* 35264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13995 /* 35268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13996 /* 35272 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13997 /* 35276 */ // MIs[1] Operand 1
13998 /* 35276 */ // No operand predicates
13999 /* 35276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14000 /* 35278 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
14001 /* 35278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
14002 /* 35281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14003 /* 35283 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14004 /* 35285 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
14005 /* 35288 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14006 /* 35291 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14007 /* 35296 */ GIR_RootConstrainSelectedInstOperands,
14008 /* 35297 */ // GIR_Coverage, 411,
14009 /* 35297 */ GIR_EraseRootFromParent_Done,
14010 /* 35298 */ // Label 972: @35298
14011 /* 35298 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(35362), // Rule ID 1262 //
14012 /* 35303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14013 /* 35306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14014 /* 35311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14015 /* 35314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14016 /* 35317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14017 /* 35320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14018 /* 35324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14019 /* 35328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14020 /* 35332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14021 /* 35336 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
14022 /* 35340 */ // MIs[1] Operand 1
14023 /* 35340 */ // No operand predicates
14024 /* 35340 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14025 /* 35342 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
14026 /* 35342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
14027 /* 35345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14028 /* 35347 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14029 /* 35349 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
14030 /* 35352 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14031 /* 35355 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14032 /* 35360 */ GIR_RootConstrainSelectedInstOperands,
14033 /* 35361 */ // GIR_Coverage, 1262,
14034 /* 35361 */ GIR_EraseRootFromParent_Done,
14035 /* 35362 */ // Label 973: @35362
14036 /* 35362 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(35426), // Rule ID 1267 //
14037 /* 35367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14038 /* 35370 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14039 /* 35375 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14040 /* 35378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14041 /* 35381 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14042 /* 35384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14043 /* 35388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14044 /* 35392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14045 /* 35396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14046 /* 35400 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14047 /* 35404 */ // MIs[1] Operand 1
14048 /* 35404 */ // No operand predicates
14049 /* 35404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14050 /* 35406 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
14051 /* 35406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
14052 /* 35409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14053 /* 35411 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14054 /* 35413 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
14055 /* 35416 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14056 /* 35419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
14057 /* 35424 */ GIR_RootConstrainSelectedInstOperands,
14058 /* 35425 */ // GIR_Coverage, 1267,
14059 /* 35425 */ GIR_EraseRootFromParent_Done,
14060 /* 35426 */ // Label 974: @35426
14061 /* 35426 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(35481), // Rule ID 2068 //
14062 /* 35431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14063 /* 35434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14064 /* 35439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14065 /* 35442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14066 /* 35445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14067 /* 35448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14068 /* 35452 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14069 /* 35456 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14070 /* 35460 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
14071 /* 35464 */ // MIs[1] Operand 1
14072 /* 35464 */ // No operand predicates
14073 /* 35464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14074 /* 35466 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
14075 /* 35466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
14076 /* 35469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14077 /* 35471 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14078 /* 35473 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14079 /* 35476 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14080 /* 35479 */ GIR_RootConstrainSelectedInstOperands,
14081 /* 35480 */ // GIR_Coverage, 2068,
14082 /* 35480 */ GIR_EraseRootFromParent_Done,
14083 /* 35481 */ // Label 975: @35481
14084 /* 35481 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(35536), // Rule ID 2074 //
14085 /* 35486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14086 /* 35489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14087 /* 35494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14088 /* 35497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14089 /* 35500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14090 /* 35503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14091 /* 35507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
14092 /* 35511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14093 /* 35515 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
14094 /* 35519 */ // MIs[1] Operand 1
14095 /* 35519 */ // No operand predicates
14096 /* 35519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14097 /* 35521 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
14098 /* 35521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
14099 /* 35524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14100 /* 35526 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14101 /* 35528 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14102 /* 35531 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14103 /* 35534 */ GIR_RootConstrainSelectedInstOperands,
14104 /* 35535 */ // GIR_Coverage, 2074,
14105 /* 35535 */ GIR_EraseRootFromParent_Done,
14106 /* 35536 */ // Label 976: @35536
14107 /* 35536 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(35588), // Rule ID 383 //
14108 /* 35541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14109 /* 35544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
14110 /* 35549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14111 /* 35552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14112 /* 35555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14113 /* 35558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14114 /* 35562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14115 /* 35566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14116 /* 35570 */ // (intrinsic_w_chain:{ *:[i32] } 7970:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14117 /* 35570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
14118 /* 35573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14119 /* 35575 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14120 /* 35577 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14121 /* 35579 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14122 /* 35582 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14123 /* 35586 */ GIR_RootConstrainSelectedInstOperands,
14124 /* 35587 */ // GIR_Coverage, 383,
14125 /* 35587 */ GIR_EraseRootFromParent_Done,
14126 /* 35588 */ // Label 977: @35588
14127 /* 35588 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(35640), // Rule ID 384 //
14128 /* 35593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14129 /* 35596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14130 /* 35601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14131 /* 35604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14132 /* 35607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14133 /* 35610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14134 /* 35614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14135 /* 35618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14136 /* 35622 */ // (intrinsic_w_chain:{ *:[i32] } 8590:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14137 /* 35622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
14138 /* 35625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14139 /* 35627 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14140 /* 35629 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14141 /* 35631 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14142 /* 35634 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14143 /* 35638 */ GIR_RootConstrainSelectedInstOperands,
14144 /* 35639 */ // GIR_Coverage, 384,
14145 /* 35639 */ GIR_EraseRootFromParent_Done,
14146 /* 35640 */ // Label 978: @35640
14147 /* 35640 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(35692), // Rule ID 391 //
14148 /* 35645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14149 /* 35648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14150 /* 35653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14151 /* 35656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14152 /* 35659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14153 /* 35662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14154 /* 35666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14155 /* 35670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14156 /* 35674 */ // (intrinsic_w_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14157 /* 35674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
14158 /* 35677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14159 /* 35679 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14160 /* 35681 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14161 /* 35683 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14162 /* 35686 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14163 /* 35690 */ GIR_RootConstrainSelectedInstOperands,
14164 /* 35691 */ // GIR_Coverage, 391,
14165 /* 35691 */ GIR_EraseRootFromParent_Done,
14166 /* 35692 */ // Label 979: @35692
14167 /* 35692 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(35744), // Rule ID 392 //
14168 /* 35697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14169 /* 35700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14170 /* 35705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14171 /* 35708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14172 /* 35711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14173 /* 35714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14174 /* 35718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14175 /* 35722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14176 /* 35726 */ // (intrinsic_w_chain:{ *:[v4i8] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14177 /* 35726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
14178 /* 35729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14179 /* 35731 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14180 /* 35733 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14181 /* 35735 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14182 /* 35738 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14183 /* 35742 */ GIR_RootConstrainSelectedInstOperands,
14184 /* 35743 */ // GIR_Coverage, 392,
14185 /* 35743 */ GIR_EraseRootFromParent_Done,
14186 /* 35744 */ // Label 980: @35744
14187 /* 35744 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(35796), // Rule ID 403 //
14188 /* 35749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14189 /* 35752 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14190 /* 35757 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14191 /* 35760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14192 /* 35763 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14193 /* 35766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14194 /* 35770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14195 /* 35774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14196 /* 35778 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14197 /* 35778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
14198 /* 35781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14199 /* 35783 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14200 /* 35785 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14201 /* 35787 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14202 /* 35790 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14203 /* 35794 */ GIR_RootConstrainSelectedInstOperands,
14204 /* 35795 */ // GIR_Coverage, 403,
14205 /* 35795 */ GIR_EraseRootFromParent_Done,
14206 /* 35796 */ // Label 981: @35796
14207 /* 35796 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(35848), // Rule ID 405 //
14208 /* 35801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14209 /* 35804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14210 /* 35809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14211 /* 35812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14212 /* 35815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14213 /* 35818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14214 /* 35822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14215 /* 35826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14216 /* 35830 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14217 /* 35830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
14218 /* 35833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14219 /* 35835 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14220 /* 35837 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14221 /* 35839 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14222 /* 35842 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14223 /* 35846 */ GIR_RootConstrainSelectedInstOperands,
14224 /* 35847 */ // GIR_Coverage, 405,
14225 /* 35847 */ GIR_EraseRootFromParent_Done,
14226 /* 35848 */ // Label 982: @35848
14227 /* 35848 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(35900), // Rule ID 407 //
14228 /* 35853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14229 /* 35856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14230 /* 35861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14231 /* 35864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14232 /* 35867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14233 /* 35870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14234 /* 35874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14235 /* 35878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14236 /* 35882 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14237 /* 35882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
14238 /* 35885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14239 /* 35887 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14240 /* 35889 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14241 /* 35891 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14242 /* 35894 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14243 /* 35898 */ GIR_RootConstrainSelectedInstOperands,
14244 /* 35899 */ // GIR_Coverage, 407,
14245 /* 35899 */ GIR_EraseRootFromParent_Done,
14246 /* 35900 */ // Label 983: @35900
14247 /* 35900 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(35952), // Rule ID 412 //
14248 /* 35905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14249 /* 35908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14250 /* 35913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14251 /* 35916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14252 /* 35919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14253 /* 35922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14254 /* 35926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14255 /* 35930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14256 /* 35934 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
14257 /* 35934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
14258 /* 35937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14259 /* 35939 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14260 /* 35941 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
14261 /* 35943 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14262 /* 35946 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14263 /* 35950 */ GIR_RootConstrainSelectedInstOperands,
14264 /* 35951 */ // GIR_Coverage, 412,
14265 /* 35951 */ GIR_EraseRootFromParent_Done,
14266 /* 35952 */ // Label 984: @35952
14267 /* 35952 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(36004), // Rule ID 415 //
14268 /* 35957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14269 /* 35960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14270 /* 35965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14271 /* 35968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14272 /* 35971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14273 /* 35974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14274 /* 35978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14275 /* 35982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14276 /* 35986 */ // (intrinsic_w_chain:{ *:[v2i16] } 8438:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14277 /* 35986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
14278 /* 35989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14279 /* 35991 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14280 /* 35993 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14281 /* 35995 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14282 /* 35998 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14283 /* 36002 */ GIR_RootConstrainSelectedInstOperands,
14284 /* 36003 */ // GIR_Coverage, 415,
14285 /* 36003 */ GIR_EraseRootFromParent_Done,
14286 /* 36004 */ // Label 985: @36004
14287 /* 36004 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(36056), // Rule ID 416 //
14288 /* 36009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14289 /* 36012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14290 /* 36017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14291 /* 36020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14292 /* 36023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14293 /* 36026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14294 /* 36030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14295 /* 36034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14296 /* 36038 */ // (intrinsic_w_chain:{ *:[v2i16] } 8439:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14297 /* 36038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
14298 /* 36041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14299 /* 36043 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14300 /* 36045 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14301 /* 36047 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14302 /* 36050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14303 /* 36054 */ GIR_RootConstrainSelectedInstOperands,
14304 /* 36055 */ // GIR_Coverage, 416,
14305 /* 36055 */ GIR_EraseRootFromParent_Done,
14306 /* 36056 */ // Label 986: @36056
14307 /* 36056 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(36108), // Rule ID 417 //
14308 /* 36061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14309 /* 36064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14310 /* 36069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14311 /* 36072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14312 /* 36075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14313 /* 36078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14314 /* 36082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14315 /* 36086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14316 /* 36090 */ // (intrinsic_w_chain:{ *:[i32] } 8436:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14317 /* 36090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
14318 /* 36093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14319 /* 36095 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14320 /* 36097 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14321 /* 36099 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14322 /* 36102 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14323 /* 36106 */ GIR_RootConstrainSelectedInstOperands,
14324 /* 36107 */ // GIR_Coverage, 417,
14325 /* 36107 */ GIR_EraseRootFromParent_Done,
14326 /* 36108 */ // Label 987: @36108
14327 /* 36108 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(36160), // Rule ID 418 //
14328 /* 36113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14329 /* 36116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14330 /* 36121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14331 /* 36124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14332 /* 36127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14333 /* 36130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14334 /* 36134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14335 /* 36138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14336 /* 36142 */ // (intrinsic_w_chain:{ *:[i32] } 8437:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14337 /* 36142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
14338 /* 36145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14339 /* 36147 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14340 /* 36149 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14341 /* 36151 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14342 /* 36154 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14343 /* 36158 */ GIR_RootConstrainSelectedInstOperands,
14344 /* 36159 */ // GIR_Coverage, 418,
14345 /* 36159 */ GIR_EraseRootFromParent_Done,
14346 /* 36160 */ // Label 988: @36160
14347 /* 36160 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(36212), // Rule ID 419 //
14348 /* 36165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14349 /* 36168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14350 /* 36173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14351 /* 36176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14352 /* 36179 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14353 /* 36182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14354 /* 36186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14355 /* 36190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14356 /* 36194 */ // (intrinsic_w_chain:{ *:[v2i16] } 8440:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14357 /* 36194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
14358 /* 36197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14359 /* 36199 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14360 /* 36201 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14361 /* 36203 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14362 /* 36206 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14363 /* 36210 */ GIR_RootConstrainSelectedInstOperands,
14364 /* 36211 */ // GIR_Coverage, 419,
14365 /* 36211 */ GIR_EraseRootFromParent_Done,
14366 /* 36212 */ // Label 989: @36212
14367 /* 36212 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(36261), // Rule ID 444 //
14368 /* 36217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14369 /* 36220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14370 /* 36225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14371 /* 36228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14372 /* 36231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14373 /* 36234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14374 /* 36238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14375 /* 36242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14376 /* 36246 */ // (intrinsic_w_chain:{ *:[i32] } 8136:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14377 /* 36246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
14378 /* 36249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14379 /* 36251 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14380 /* 36253 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14381 /* 36255 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14382 /* 36259 */ GIR_RootConstrainSelectedInstOperands,
14383 /* 36260 */ // GIR_Coverage, 444,
14384 /* 36260 */ GIR_EraseRootFromParent_Done,
14385 /* 36261 */ // Label 990: @36261
14386 /* 36261 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(36310), // Rule ID 445 //
14387 /* 36266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14388 /* 36269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14389 /* 36274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14390 /* 36277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14391 /* 36280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14392 /* 36283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14393 /* 36287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14394 /* 36291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14395 /* 36295 */ // (intrinsic_w_chain:{ *:[i32] } 8138:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14396 /* 36295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
14397 /* 36298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14398 /* 36300 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14399 /* 36302 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14400 /* 36304 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14401 /* 36308 */ GIR_RootConstrainSelectedInstOperands,
14402 /* 36309 */ // GIR_Coverage, 445,
14403 /* 36309 */ GIR_EraseRootFromParent_Done,
14404 /* 36310 */ // Label 991: @36310
14405 /* 36310 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(36359), // Rule ID 446 //
14406 /* 36315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14407 /* 36318 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14408 /* 36323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14409 /* 36326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14410 /* 36329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14411 /* 36332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14412 /* 36336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14413 /* 36340 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14414 /* 36344 */ // (intrinsic_w_chain:{ *:[i32] } 8137:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14415 /* 36344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
14416 /* 36347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14417 /* 36349 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14418 /* 36351 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14419 /* 36353 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14420 /* 36357 */ GIR_RootConstrainSelectedInstOperands,
14421 /* 36358 */ // GIR_Coverage, 446,
14422 /* 36358 */ GIR_EraseRootFromParent_Done,
14423 /* 36359 */ // Label 992: @36359
14424 /* 36359 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(36408), // Rule ID 456 //
14425 /* 36364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14426 /* 36367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
14427 /* 36372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14428 /* 36375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14429 /* 36378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14430 /* 36381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14431 /* 36385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14432 /* 36389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14433 /* 36393 */ // (intrinsic_w_chain:{ *:[v4i8] } 8480:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14434 /* 36393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
14435 /* 36396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14436 /* 36398 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14437 /* 36400 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14438 /* 36402 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14439 /* 36406 */ GIR_RootConstrainSelectedInstOperands,
14440 /* 36407 */ // GIR_Coverage, 456,
14441 /* 36407 */ GIR_EraseRootFromParent_Done,
14442 /* 36408 */ // Label 993: @36408
14443 /* 36408 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(36457), // Rule ID 457 //
14444 /* 36413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14445 /* 36416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
14446 /* 36421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14447 /* 36424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14448 /* 36427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14449 /* 36430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14450 /* 36434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14451 /* 36438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14452 /* 36442 */ // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14453 /* 36442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
14454 /* 36445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14455 /* 36447 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14456 /* 36449 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14457 /* 36451 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14458 /* 36455 */ GIR_RootConstrainSelectedInstOperands,
14459 /* 36456 */ // GIR_Coverage, 457,
14460 /* 36456 */ GIR_EraseRootFromParent_Done,
14461 /* 36457 */ // Label 994: @36457
14462 /* 36457 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(36506), // Rule ID 461 //
14463 /* 36462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
14464 /* 36465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
14465 /* 36470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14466 /* 36473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14467 /* 36476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14468 /* 36479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14469 /* 36483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14470 /* 36487 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14471 /* 36491 */ // (intrinsic_w_chain:{ *:[i32] } 8338:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
14472 /* 36491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
14473 /* 36494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14474 /* 36496 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
14475 /* 36498 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14476 /* 36500 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14477 /* 36504 */ GIR_RootConstrainSelectedInstOperands,
14478 /* 36505 */ // GIR_Coverage, 461,
14479 /* 36505 */ GIR_EraseRootFromParent_Done,
14480 /* 36506 */ // Label 995: @36506
14481 /* 36506 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(36558), // Rule ID 467 //
14482 /* 36511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14483 /* 36514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
14484 /* 36519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14485 /* 36522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14486 /* 36525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14487 /* 36528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14488 /* 36532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14489 /* 36536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14490 /* 36540 */ // (intrinsic_w_chain:{ *:[v2i16] } 7988:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14491 /* 36540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
14492 /* 36543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14493 /* 36545 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14494 /* 36547 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14495 /* 36549 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14496 /* 36552 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14497 /* 36556 */ GIR_RootConstrainSelectedInstOperands,
14498 /* 36557 */ // GIR_Coverage, 467,
14499 /* 36557 */ GIR_EraseRootFromParent_Done,
14500 /* 36558 */ // Label 996: @36558
14501 /* 36558 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(36610), // Rule ID 468 //
14502 /* 36563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14503 /* 36566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14504 /* 36571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14505 /* 36574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14506 /* 36577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14507 /* 36580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14508 /* 36584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14509 /* 36588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14510 /* 36592 */ // (intrinsic_w_chain:{ *:[v2i16] } 7990:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14511 /* 36592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
14512 /* 36595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14513 /* 36597 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14514 /* 36599 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14515 /* 36601 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14516 /* 36604 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14517 /* 36608 */ GIR_RootConstrainSelectedInstOperands,
14518 /* 36609 */ // GIR_Coverage, 468,
14519 /* 36609 */ GIR_EraseRootFromParent_Done,
14520 /* 36610 */ // Label 997: @36610
14521 /* 36610 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36662), // Rule ID 469 //
14522 /* 36615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14523 /* 36618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
14524 /* 36623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14525 /* 36626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14526 /* 36629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14527 /* 36632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14528 /* 36636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14529 /* 36640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14530 /* 36644 */ // (intrinsic_w_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14531 /* 36644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
14532 /* 36647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14533 /* 36649 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14534 /* 36651 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14535 /* 36653 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14536 /* 36656 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14537 /* 36660 */ GIR_RootConstrainSelectedInstOperands,
14538 /* 36661 */ // GIR_Coverage, 469,
14539 /* 36661 */ GIR_EraseRootFromParent_Done,
14540 /* 36662 */ // Label 998: @36662
14541 /* 36662 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(36714), // Rule ID 470 //
14542 /* 36667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14543 /* 36670 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14544 /* 36675 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14545 /* 36678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14546 /* 36681 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14547 /* 36684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14548 /* 36688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14549 /* 36692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14550 /* 36696 */ // (intrinsic_w_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14551 /* 36696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
14552 /* 36699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14553 /* 36701 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14554 /* 36703 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14555 /* 36705 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14556 /* 36708 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14557 /* 36712 */ GIR_RootConstrainSelectedInstOperands,
14558 /* 36713 */ // GIR_Coverage, 470,
14559 /* 36713 */ GIR_EraseRootFromParent_Done,
14560 /* 36714 */ // Label 999: @36714
14561 /* 36714 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36766), // Rule ID 471 //
14562 /* 36719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14563 /* 36722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14564 /* 36727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14565 /* 36730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14566 /* 36733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14567 /* 36736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14568 /* 36740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14569 /* 36744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14570 /* 36748 */ // (intrinsic_w_chain:{ *:[i32] } 8133:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14571 /* 36748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
14572 /* 36751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14573 /* 36753 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14574 /* 36755 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14575 /* 36757 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14576 /* 36760 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14577 /* 36764 */ GIR_RootConstrainSelectedInstOperands,
14578 /* 36765 */ // GIR_Coverage, 471,
14579 /* 36765 */ GIR_EraseRootFromParent_Done,
14580 /* 36766 */ // Label 1000: @36766
14581 /* 36766 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36818), // Rule ID 472 //
14582 /* 36771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14583 /* 36774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14584 /* 36779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14585 /* 36782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14586 /* 36785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14587 /* 36788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14588 /* 36792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14589 /* 36796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14590 /* 36800 */ // (intrinsic_w_chain:{ *:[i32] } 8135:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14591 /* 36800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
14592 /* 36803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14593 /* 36805 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14594 /* 36807 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14595 /* 36809 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14596 /* 36812 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14597 /* 36816 */ GIR_RootConstrainSelectedInstOperands,
14598 /* 36817 */ // GIR_Coverage, 472,
14599 /* 36817 */ GIR_EraseRootFromParent_Done,
14600 /* 36818 */ // Label 1001: @36818
14601 /* 36818 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36870), // Rule ID 473 //
14602 /* 36823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14603 /* 36826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14604 /* 36831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14605 /* 36834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14606 /* 36837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14607 /* 36840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14608 /* 36844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14609 /* 36848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14610 /* 36852 */ // (intrinsic_w_chain:{ *:[i32] } 8134:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14611 /* 36852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
14612 /* 36855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14613 /* 36857 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14614 /* 36859 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14615 /* 36861 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14616 /* 36864 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14617 /* 36868 */ GIR_RootConstrainSelectedInstOperands,
14618 /* 36869 */ // GIR_Coverage, 473,
14619 /* 36869 */ GIR_EraseRootFromParent_Done,
14620 /* 36870 */ // Label 1002: @36870
14621 /* 36870 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36922), // Rule ID 487 //
14622 /* 36875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14623 /* 36878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14624 /* 36883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14625 /* 36886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14626 /* 36889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14627 /* 36892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14628 /* 36896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14629 /* 36900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14630 /* 36904 */ // (intrinsic_w_chain:{ *:[v2i16] } 8435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14631 /* 36904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
14632 /* 36907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14633 /* 36909 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14634 /* 36911 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14635 /* 36913 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14636 /* 36916 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14637 /* 36920 */ GIR_RootConstrainSelectedInstOperands,
14638 /* 36921 */ // GIR_Coverage, 487,
14639 /* 36921 */ GIR_EraseRootFromParent_Done,
14640 /* 36922 */ // Label 1003: @36922
14641 /* 36922 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36974), // Rule ID 488 //
14642 /* 36927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14643 /* 36930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14644 /* 36935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14645 /* 36938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14646 /* 36941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14647 /* 36944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14648 /* 36948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14649 /* 36952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14650 /* 36956 */ // (intrinsic_w_chain:{ *:[i32] } 8443:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14651 /* 36956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
14652 /* 36959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14653 /* 36961 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14654 /* 36963 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14655 /* 36965 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14656 /* 36968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14657 /* 36972 */ GIR_RootConstrainSelectedInstOperands,
14658 /* 36973 */ // GIR_Coverage, 488,
14659 /* 36973 */ GIR_EraseRootFromParent_Done,
14660 /* 36974 */ // Label 1004: @36974
14661 /* 36974 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(37026), // Rule ID 489 //
14662 /* 36979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14663 /* 36982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14664 /* 36987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14665 /* 36990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14666 /* 36993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14667 /* 36996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14668 /* 37000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14669 /* 37004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14670 /* 37008 */ // (intrinsic_w_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14671 /* 37008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
14672 /* 37011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14673 /* 37013 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14674 /* 37015 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14675 /* 37017 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14676 /* 37020 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14677 /* 37024 */ GIR_RootConstrainSelectedInstOperands,
14678 /* 37025 */ // GIR_Coverage, 489,
14679 /* 37025 */ GIR_EraseRootFromParent_Done,
14680 /* 37026 */ // Label 1005: @37026
14681 /* 37026 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(37078), // Rule ID 490 //
14682 /* 37031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14683 /* 37034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14684 /* 37039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14685 /* 37042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14686 /* 37045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14687 /* 37048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14688 /* 37052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14689 /* 37056 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14690 /* 37060 */ // (intrinsic_w_chain:{ *:[v2i16] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14691 /* 37060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
14692 /* 37063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14693 /* 37065 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14694 /* 37067 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14695 /* 37069 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14696 /* 37072 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14697 /* 37076 */ GIR_RootConstrainSelectedInstOperands,
14698 /* 37077 */ // GIR_Coverage, 490,
14699 /* 37077 */ GIR_EraseRootFromParent_Done,
14700 /* 37078 */ // Label 1006: @37078
14701 /* 37078 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(37127), // Rule ID 500 //
14702 /* 37083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
14703 /* 37086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14704 /* 37091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14705 /* 37094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14706 /* 37097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14707 /* 37100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14708 /* 37104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14709 /* 37108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14710 /* 37112 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14711 /* 37112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
14712 /* 37115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14713 /* 37117 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14714 /* 37119 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14715 /* 37121 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14716 /* 37125 */ GIR_RootConstrainSelectedInstOperands,
14717 /* 37126 */ // GIR_Coverage, 500,
14718 /* 37126 */ GIR_EraseRootFromParent_Done,
14719 /* 37127 */ // Label 1007: @37127
14720 /* 37127 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(37179), // Rule ID 1247 //
14721 /* 37132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14722 /* 37135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
14723 /* 37140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14724 /* 37143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14725 /* 37146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14726 /* 37149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14727 /* 37153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14728 /* 37157 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14729 /* 37161 */ // (intrinsic_w_chain:{ *:[i32] } 7970:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14730 /* 37161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
14731 /* 37164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14732 /* 37166 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14733 /* 37168 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14734 /* 37170 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14735 /* 37173 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14736 /* 37177 */ GIR_RootConstrainSelectedInstOperands,
14737 /* 37178 */ // GIR_Coverage, 1247,
14738 /* 37178 */ GIR_EraseRootFromParent_Done,
14739 /* 37179 */ // Label 1008: @37179
14740 /* 37179 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(37228), // Rule ID 1255 //
14741 /* 37184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14742 /* 37187 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
14743 /* 37192 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14744 /* 37195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14745 /* 37198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14746 /* 37201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14747 /* 37205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14748 /* 37209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14749 /* 37213 */ // (intrinsic_w_chain:{ *:[i32] } 8338:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
14750 /* 37213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
14751 /* 37216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14752 /* 37218 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
14753 /* 37220 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14754 /* 37222 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14755 /* 37226 */ GIR_RootConstrainSelectedInstOperands,
14756 /* 37227 */ // GIR_Coverage, 1255,
14757 /* 37227 */ GIR_EraseRootFromParent_Done,
14758 /* 37228 */ // Label 1009: @37228
14759 /* 37228 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(37280), // Rule ID 1263 //
14760 /* 37233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14761 /* 37236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
14762 /* 37241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14763 /* 37244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14764 /* 37247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14765 /* 37250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14766 /* 37254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14767 /* 37258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14768 /* 37262 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14769 /* 37262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
14770 /* 37265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14771 /* 37267 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14772 /* 37269 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14773 /* 37271 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14774 /* 37274 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14775 /* 37278 */ GIR_RootConstrainSelectedInstOperands,
14776 /* 37279 */ // GIR_Coverage, 1263,
14777 /* 37279 */ GIR_EraseRootFromParent_Done,
14778 /* 37280 */ // Label 1010: @37280
14779 /* 37280 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(37332), // Rule ID 1264 //
14780 /* 37285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14781 /* 37288 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
14782 /* 37293 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14783 /* 37296 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14784 /* 37299 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14785 /* 37302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14786 /* 37306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14787 /* 37310 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14788 /* 37314 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14789 /* 37314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
14790 /* 37317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14791 /* 37319 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14792 /* 37321 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14793 /* 37323 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14794 /* 37326 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14795 /* 37330 */ GIR_RootConstrainSelectedInstOperands,
14796 /* 37331 */ // GIR_Coverage, 1264,
14797 /* 37331 */ GIR_EraseRootFromParent_Done,
14798 /* 37332 */ // Label 1011: @37332
14799 /* 37332 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(37384), // Rule ID 1265 //
14800 /* 37337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14801 /* 37340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
14802 /* 37345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14803 /* 37348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14804 /* 37351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14805 /* 37354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14806 /* 37358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14807 /* 37362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14808 /* 37366 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14809 /* 37366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
14810 /* 37369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14811 /* 37371 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14812 /* 37373 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14813 /* 37375 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14814 /* 37378 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14815 /* 37382 */ GIR_RootConstrainSelectedInstOperands,
14816 /* 37383 */ // GIR_Coverage, 1265,
14817 /* 37383 */ GIR_EraseRootFromParent_Done,
14818 /* 37384 */ // Label 1012: @37384
14819 /* 37384 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(37436), // Rule ID 1266 //
14820 /* 37389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14821 /* 37392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
14822 /* 37397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14823 /* 37400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14824 /* 37403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14825 /* 37406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14826 /* 37410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14827 /* 37414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14828 /* 37418 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14829 /* 37418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
14830 /* 37421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14831 /* 37423 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
14832 /* 37425 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
14833 /* 37427 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14834 /* 37430 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14835 /* 37434 */ GIR_RootConstrainSelectedInstOperands,
14836 /* 37435 */ // GIR_Coverage, 1266,
14837 /* 37435 */ GIR_EraseRootFromParent_Done,
14838 /* 37436 */ // Label 1013: @37436
14839 /* 37436 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(37488), // Rule ID 1285 //
14840 /* 37441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14841 /* 37444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
14842 /* 37449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14843 /* 37452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14844 /* 37455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14845 /* 37458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14846 /* 37462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14847 /* 37466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14848 /* 37470 */ // (intrinsic_w_chain:{ *:[i32] } 8590:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14849 /* 37470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
14850 /* 37473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14851 /* 37475 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14852 /* 37477 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14853 /* 37479 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14854 /* 37482 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14855 /* 37486 */ GIR_RootConstrainSelectedInstOperands,
14856 /* 37487 */ // GIR_Coverage, 1285,
14857 /* 37487 */ GIR_EraseRootFromParent_Done,
14858 /* 37488 */ // Label 1014: @37488
14859 /* 37488 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(37540), // Rule ID 1291 //
14860 /* 37493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14861 /* 37496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
14862 /* 37501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14863 /* 37504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14864 /* 37507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14865 /* 37510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14866 /* 37514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14867 /* 37518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14868 /* 37522 */ // (intrinsic_w_chain:{ *:[i32] } 8436:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14869 /* 37522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
14870 /* 37525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14871 /* 37527 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14872 /* 37529 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14873 /* 37531 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14874 /* 37534 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14875 /* 37538 */ GIR_RootConstrainSelectedInstOperands,
14876 /* 37539 */ // GIR_Coverage, 1291,
14877 /* 37539 */ GIR_EraseRootFromParent_Done,
14878 /* 37540 */ // Label 1015: @37540
14879 /* 37540 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(37592), // Rule ID 1292 //
14880 /* 37545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14881 /* 37548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
14882 /* 37553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14883 /* 37556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14884 /* 37559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14885 /* 37562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14886 /* 37566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14887 /* 37570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14888 /* 37574 */ // (intrinsic_w_chain:{ *:[i32] } 8437:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14889 /* 37574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
14890 /* 37577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14891 /* 37579 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14892 /* 37581 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14893 /* 37583 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14894 /* 37586 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14895 /* 37590 */ GIR_RootConstrainSelectedInstOperands,
14896 /* 37591 */ // GIR_Coverage, 1292,
14897 /* 37591 */ GIR_EraseRootFromParent_Done,
14898 /* 37592 */ // Label 1016: @37592
14899 /* 37592 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37644), // Rule ID 1293 //
14900 /* 37597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14901 /* 37600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
14902 /* 37605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14903 /* 37608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14904 /* 37611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14905 /* 37614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14906 /* 37618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14907 /* 37622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14908 /* 37626 */ // (intrinsic_w_chain:{ *:[v2i16] } 8438:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14909 /* 37626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
14910 /* 37629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14911 /* 37631 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14912 /* 37633 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14913 /* 37635 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14914 /* 37638 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14915 /* 37642 */ GIR_RootConstrainSelectedInstOperands,
14916 /* 37643 */ // GIR_Coverage, 1293,
14917 /* 37643 */ GIR_EraseRootFromParent_Done,
14918 /* 37644 */ // Label 1017: @37644
14919 /* 37644 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(37696), // Rule ID 1294 //
14920 /* 37649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14921 /* 37652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
14922 /* 37657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14923 /* 37660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14924 /* 37663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14925 /* 37666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14926 /* 37670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14927 /* 37674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14928 /* 37678 */ // (intrinsic_w_chain:{ *:[v2i16] } 8439:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14929 /* 37678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
14930 /* 37681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14931 /* 37683 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14932 /* 37685 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14933 /* 37687 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14934 /* 37690 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14935 /* 37694 */ GIR_RootConstrainSelectedInstOperands,
14936 /* 37695 */ // GIR_Coverage, 1294,
14937 /* 37695 */ GIR_EraseRootFromParent_Done,
14938 /* 37696 */ // Label 1018: @37696
14939 /* 37696 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(37748), // Rule ID 1295 //
14940 /* 37701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14941 /* 37704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14942 /* 37709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14943 /* 37712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14944 /* 37715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14945 /* 37718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14946 /* 37722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14947 /* 37726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14948 /* 37730 */ // (intrinsic_w_chain:{ *:[v2i16] } 8440:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14949 /* 37730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
14950 /* 37733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14951 /* 37735 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14952 /* 37737 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14953 /* 37739 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14954 /* 37742 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14955 /* 37746 */ GIR_RootConstrainSelectedInstOperands,
14956 /* 37747 */ // GIR_Coverage, 1295,
14957 /* 37747 */ GIR_EraseRootFromParent_Done,
14958 /* 37748 */ // Label 1019: @37748
14959 /* 37748 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(37800), // Rule ID 1298 //
14960 /* 37753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14961 /* 37756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14962 /* 37761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14963 /* 37764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14964 /* 37767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14965 /* 37770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14966 /* 37774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14967 /* 37778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14968 /* 37782 */ // (intrinsic_w_chain:{ *:[v4i8] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14969 /* 37782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
14970 /* 37785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14971 /* 37787 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14972 /* 37789 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14973 /* 37791 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14974 /* 37794 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14975 /* 37798 */ GIR_RootConstrainSelectedInstOperands,
14976 /* 37799 */ // GIR_Coverage, 1298,
14977 /* 37799 */ GIR_EraseRootFromParent_Done,
14978 /* 37800 */ // Label 1020: @37800
14979 /* 37800 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(37852), // Rule ID 1299 //
14980 /* 37805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
14981 /* 37808 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14982 /* 37813 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14983 /* 37816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14984 /* 37819 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14985 /* 37822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14986 /* 37826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14987 /* 37830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14988 /* 37834 */ // (intrinsic_w_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14989 /* 37834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14990 /* 37837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14991 /* 37839 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14992 /* 37841 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14993 /* 37843 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14994 /* 37846 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14995 /* 37850 */ GIR_RootConstrainSelectedInstOperands,
14996 /* 37851 */ // GIR_Coverage, 1299,
14997 /* 37851 */ GIR_EraseRootFromParent_Done,
14998 /* 37852 */ // Label 1021: @37852
14999 /* 37852 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37901), // Rule ID 1317 //
15000 /* 37857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15001 /* 37860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
15002 /* 37865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15003 /* 37868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15004 /* 37871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15005 /* 37874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15006 /* 37878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15007 /* 37882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15008 /* 37886 */ // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15009 /* 37886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
15010 /* 37889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15011 /* 37891 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15012 /* 37893 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15013 /* 37895 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15014 /* 37899 */ GIR_RootConstrainSelectedInstOperands,
15015 /* 37900 */ // GIR_Coverage, 1317,
15016 /* 37900 */ GIR_EraseRootFromParent_Done,
15017 /* 37901 */ // Label 1022: @37901
15018 /* 37901 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37950), // Rule ID 1318 //
15019 /* 37906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15020 /* 37909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
15021 /* 37914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
15022 /* 37917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15023 /* 37920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15024 /* 37923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15025 /* 37927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15026 /* 37931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15027 /* 37935 */ // (intrinsic_w_chain:{ *:[v4i8] } 8480:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15028 /* 37935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
15029 /* 37938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15030 /* 37940 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15031 /* 37942 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15032 /* 37944 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15033 /* 37948 */ GIR_RootConstrainSelectedInstOperands,
15034 /* 37949 */ // GIR_Coverage, 1318,
15035 /* 37949 */ GIR_EraseRootFromParent_Done,
15036 /* 37950 */ // Label 1023: @37950
15037 /* 37950 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37999), // Rule ID 1328 //
15038 /* 37955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15039 /* 37958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
15040 /* 37963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15041 /* 37966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15042 /* 37969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15043 /* 37972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15044 /* 37976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15045 /* 37980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15046 /* 37984 */ // (intrinsic_w_chain:{ *:[i32] } 8136:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15047 /* 37984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
15048 /* 37987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15049 /* 37989 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15050 /* 37991 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15051 /* 37993 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15052 /* 37997 */ GIR_RootConstrainSelectedInstOperands,
15053 /* 37998 */ // GIR_Coverage, 1328,
15054 /* 37998 */ GIR_EraseRootFromParent_Done,
15055 /* 37999 */ // Label 1024: @37999
15056 /* 37999 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(38048), // Rule ID 1329 //
15057 /* 38004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15058 /* 38007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
15059 /* 38012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15060 /* 38015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15061 /* 38018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15062 /* 38021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15063 /* 38025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15064 /* 38029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15065 /* 38033 */ // (intrinsic_w_chain:{ *:[i32] } 8138:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15066 /* 38033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
15067 /* 38036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15068 /* 38038 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15069 /* 38040 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15070 /* 38042 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15071 /* 38046 */ GIR_RootConstrainSelectedInstOperands,
15072 /* 38047 */ // GIR_Coverage, 1329,
15073 /* 38047 */ GIR_EraseRootFromParent_Done,
15074 /* 38048 */ // Label 1025: @38048
15075 /* 38048 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(38097), // Rule ID 1330 //
15076 /* 38053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15077 /* 38056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
15078 /* 38061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15079 /* 38064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15080 /* 38067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15081 /* 38070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15082 /* 38074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15083 /* 38078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15084 /* 38082 */ // (intrinsic_w_chain:{ *:[i32] } 8137:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15085 /* 38082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
15086 /* 38085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15087 /* 38087 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15088 /* 38089 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15089 /* 38091 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15090 /* 38095 */ GIR_RootConstrainSelectedInstOperands,
15091 /* 38096 */ // GIR_Coverage, 1330,
15092 /* 38096 */ GIR_EraseRootFromParent_Done,
15093 /* 38097 */ // Label 1026: @38097
15094 /* 38097 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(38149), // Rule ID 1339 //
15095 /* 38102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15096 /* 38105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
15097 /* 38110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15098 /* 38113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15099 /* 38116 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15100 /* 38119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15101 /* 38123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15102 /* 38127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15103 /* 38131 */ // (intrinsic_w_chain:{ *:[v2i16] } 7988:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15104 /* 38131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
15105 /* 38134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15106 /* 38136 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15107 /* 38138 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15108 /* 38140 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15109 /* 38143 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15110 /* 38147 */ GIR_RootConstrainSelectedInstOperands,
15111 /* 38148 */ // GIR_Coverage, 1339,
15112 /* 38148 */ GIR_EraseRootFromParent_Done,
15113 /* 38149 */ // Label 1027: @38149
15114 /* 38149 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(38201), // Rule ID 1340 //
15115 /* 38154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15116 /* 38157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
15117 /* 38162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15118 /* 38165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15119 /* 38168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15120 /* 38171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15121 /* 38175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15122 /* 38179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15123 /* 38183 */ // (intrinsic_w_chain:{ *:[v2i16] } 7990:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15124 /* 38183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
15125 /* 38186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15126 /* 38188 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15127 /* 38190 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15128 /* 38192 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15129 /* 38195 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15130 /* 38199 */ GIR_RootConstrainSelectedInstOperands,
15131 /* 38200 */ // GIR_Coverage, 1340,
15132 /* 38200 */ GIR_EraseRootFromParent_Done,
15133 /* 38201 */ // Label 1028: @38201
15134 /* 38201 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(38253), // Rule ID 1351 //
15135 /* 38206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15136 /* 38209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
15137 /* 38214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15138 /* 38217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15139 /* 38220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15140 /* 38223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15141 /* 38227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15142 /* 38231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15143 /* 38235 */ // (intrinsic_w_chain:{ *:[i32] } 8133:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15144 /* 38235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
15145 /* 38238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15146 /* 38240 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15147 /* 38242 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15148 /* 38244 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15149 /* 38247 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15150 /* 38251 */ GIR_RootConstrainSelectedInstOperands,
15151 /* 38252 */ // GIR_Coverage, 1351,
15152 /* 38252 */ GIR_EraseRootFromParent_Done,
15153 /* 38253 */ // Label 1029: @38253
15154 /* 38253 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(38305), // Rule ID 1352 //
15155 /* 38258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15156 /* 38261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
15157 /* 38266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15158 /* 38269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15159 /* 38272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15160 /* 38275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15161 /* 38279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15162 /* 38283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15163 /* 38287 */ // (intrinsic_w_chain:{ *:[i32] } 8135:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15164 /* 38287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
15165 /* 38290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15166 /* 38292 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15167 /* 38294 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15168 /* 38296 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15169 /* 38299 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15170 /* 38303 */ GIR_RootConstrainSelectedInstOperands,
15171 /* 38304 */ // GIR_Coverage, 1352,
15172 /* 38304 */ GIR_EraseRootFromParent_Done,
15173 /* 38305 */ // Label 1030: @38305
15174 /* 38305 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(38357), // Rule ID 1353 //
15175 /* 38310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15176 /* 38313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
15177 /* 38318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15178 /* 38321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
15179 /* 38324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
15180 /* 38327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15181 /* 38331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15182 /* 38335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15183 /* 38339 */ // (intrinsic_w_chain:{ *:[i32] } 8134:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
15184 /* 38339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
15185 /* 38342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15186 /* 38344 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15187 /* 38346 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15188 /* 38348 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
15189 /* 38351 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15190 /* 38355 */ GIR_RootConstrainSelectedInstOperands,
15191 /* 38356 */ // GIR_Coverage, 1353,
15192 /* 38356 */ GIR_EraseRootFromParent_Done,
15193 /* 38357 */ // Label 1031: @38357
15194 /* 38357 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(38409), // Rule ID 1359 //
15195 /* 38362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15196 /* 38365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
15197 /* 38370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15198 /* 38373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15199 /* 38376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15200 /* 38379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15201 /* 38383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15202 /* 38387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15203 /* 38391 */ // (intrinsic_w_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15204 /* 38391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
15205 /* 38394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15206 /* 38396 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15207 /* 38398 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15208 /* 38400 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15209 /* 38403 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15210 /* 38407 */ GIR_RootConstrainSelectedInstOperands,
15211 /* 38408 */ // GIR_Coverage, 1359,
15212 /* 38408 */ GIR_EraseRootFromParent_Done,
15213 /* 38409 */ // Label 1032: @38409
15214 /* 38409 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(38461), // Rule ID 1360 //
15215 /* 38414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15216 /* 38417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
15217 /* 38422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15218 /* 38425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15219 /* 38428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15220 /* 38431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15221 /* 38435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15222 /* 38439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15223 /* 38443 */ // (intrinsic_w_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15224 /* 38443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
15225 /* 38446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15226 /* 38448 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15227 /* 38450 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15228 /* 38452 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15229 /* 38455 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15230 /* 38459 */ GIR_RootConstrainSelectedInstOperands,
15231 /* 38460 */ // GIR_Coverage, 1360,
15232 /* 38460 */ GIR_EraseRootFromParent_Done,
15233 /* 38461 */ // Label 1033: @38461
15234 /* 38461 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(38513), // Rule ID 1367 //
15235 /* 38466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15236 /* 38469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
15237 /* 38474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15238 /* 38477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15239 /* 38480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15240 /* 38483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15241 /* 38487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15242 /* 38491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15243 /* 38495 */ // (intrinsic_w_chain:{ *:[v2i16] } 8435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15244 /* 38495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
15245 /* 38498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15246 /* 38500 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15247 /* 38502 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15248 /* 38504 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15249 /* 38507 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15250 /* 38511 */ GIR_RootConstrainSelectedInstOperands,
15251 /* 38512 */ // GIR_Coverage, 1367,
15252 /* 38512 */ GIR_EraseRootFromParent_Done,
15253 /* 38513 */ // Label 1034: @38513
15254 /* 38513 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(38565), // Rule ID 1368 //
15255 /* 38518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15256 /* 38521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
15257 /* 38526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15258 /* 38529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15259 /* 38532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15260 /* 38535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15261 /* 38539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15262 /* 38543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15263 /* 38547 */ // (intrinsic_w_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15264 /* 38547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
15265 /* 38550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15266 /* 38552 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15267 /* 38554 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15268 /* 38556 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15269 /* 38559 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15270 /* 38563 */ GIR_RootConstrainSelectedInstOperands,
15271 /* 38564 */ // GIR_Coverage, 1368,
15272 /* 38564 */ GIR_EraseRootFromParent_Done,
15273 /* 38565 */ // Label 1035: @38565
15274 /* 38565 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(38617), // Rule ID 1369 //
15275 /* 38570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15276 /* 38573 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
15277 /* 38578 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15278 /* 38581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15279 /* 38584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15280 /* 38587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15281 /* 38591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15282 /* 38595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15283 /* 38599 */ // (intrinsic_w_chain:{ *:[v2i16] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15284 /* 38599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
15285 /* 38602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15286 /* 38604 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15287 /* 38606 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15288 /* 38608 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15289 /* 38611 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15290 /* 38615 */ GIR_RootConstrainSelectedInstOperands,
15291 /* 38616 */ // GIR_Coverage, 1369,
15292 /* 38616 */ GIR_EraseRootFromParent_Done,
15293 /* 38617 */ // Label 1036: @38617
15294 /* 38617 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(38669), // Rule ID 1370 //
15295 /* 38622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15296 /* 38625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
15297 /* 38630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15298 /* 38633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15299 /* 38636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15300 /* 38639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15301 /* 38643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15302 /* 38647 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15303 /* 38651 */ // (intrinsic_w_chain:{ *:[i32] } 8443:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
15304 /* 38651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
15305 /* 38654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15306 /* 38656 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15307 /* 38658 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15308 /* 38660 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15309 /* 38663 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15310 /* 38667 */ GIR_RootConstrainSelectedInstOperands,
15311 /* 38668 */ // GIR_Coverage, 1370,
15312 /* 38668 */ GIR_EraseRootFromParent_Done,
15313 /* 38669 */ // Label 1037: @38669
15314 /* 38669 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(38718), // Rule ID 1371 //
15315 /* 38674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
15316 /* 38677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
15317 /* 38682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
15318 /* 38685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15319 /* 38688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15320 /* 38691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15321 /* 38695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15322 /* 38699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15323 /* 38703 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
15324 /* 38703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
15325 /* 38706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15326 /* 38708 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
15327 /* 38710 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
15328 /* 38712 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15329 /* 38716 */ GIR_RootConstrainSelectedInstOperands,
15330 /* 38717 */ // GIR_Coverage, 1371,
15331 /* 38717 */ GIR_EraseRootFromParent_Done,
15332 /* 38718 */ // Label 1038: @38718
15333 /* 38718 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(38762), // Rule ID 2055 //
15334 /* 38723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
15335 /* 38726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
15336 /* 38731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
15337 /* 38734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
15338 /* 38737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
15339 /* 38740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
15340 /* 38744 */ // (intrinsic_w_chain:{ *:[v2i16] } 8432:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
15341 /* 38744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
15342 /* 38747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15343 /* 38749 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15344 /* 38751 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15345 /* 38753 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
15346 /* 38756 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15347 /* 38760 */ GIR_RootConstrainSelectedInstOperands,
15348 /* 38761 */ // GIR_Coverage, 2055,
15349 /* 38761 */ GIR_EraseRootFromParent_Done,
15350 /* 38762 */ // Label 1039: @38762
15351 /* 38762 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(38806), // Rule ID 2061 //
15352 /* 38767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15353 /* 38770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
15354 /* 38775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15355 /* 38778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15356 /* 38781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15357 /* 38784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15358 /* 38788 */ // (intrinsic_w_chain:{ *:[i32] } 7987:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
15359 /* 38788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
15360 /* 38791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15361 /* 38793 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15362 /* 38795 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15363 /* 38797 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
15364 /* 38800 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15365 /* 38804 */ GIR_RootConstrainSelectedInstOperands,
15366 /* 38805 */ // GIR_Coverage, 2061,
15367 /* 38805 */ GIR_EraseRootFromParent_Done,
15368 /* 38806 */ // Label 1040: @38806
15369 /* 38806 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(38850), // Rule ID 2063 //
15370 /* 38811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15371 /* 38814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
15372 /* 38819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15373 /* 38822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15374 /* 38825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15375 /* 38828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15376 /* 38832 */ // (intrinsic_w_chain:{ *:[i32] } 8002:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
15377 /* 38832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
15378 /* 38835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15379 /* 38837 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
15380 /* 38839 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
15381 /* 38841 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
15382 /* 38844 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15383 /* 38848 */ GIR_RootConstrainSelectedInstOperands,
15384 /* 38849 */ // GIR_Coverage, 2063,
15385 /* 38849 */ GIR_EraseRootFromParent_Done,
15386 /* 38850 */ // Label 1041: @38850
15387 /* 38850 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(38896), // Rule ID 511 //
15388 /* 38855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15389 /* 38858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
15390 /* 38863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15391 /* 38866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15392 /* 38869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15393 /* 38873 */ // MIs[0] ptr
15394 /* 38873 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15395 /* 38877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15396 /* 38881 */ // (intrinsic_w_chain:{ *:[v2i64] } 8352:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15397 /* 38881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
15398 /* 38884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15399 /* 38886 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15400 /* 38888 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15401 /* 38890 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15402 /* 38894 */ GIR_RootConstrainSelectedInstOperands,
15403 /* 38895 */ // GIR_Coverage, 511,
15404 /* 38895 */ GIR_EraseRootFromParent_Done,
15405 /* 38896 */ // Label 1042: @38896
15406 /* 38896 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(38942), // Rule ID 512 //
15407 /* 38901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15408 /* 38904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
15409 /* 38909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15410 /* 38912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15411 /* 38915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15412 /* 38919 */ // MIs[0] ptr
15413 /* 38919 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15414 /* 38923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15415 /* 38927 */ // (intrinsic_w_chain:{ *:[v4i32] } 8353:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15416 /* 38927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
15417 /* 38930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15418 /* 38932 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15419 /* 38934 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15420 /* 38936 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15421 /* 38940 */ GIR_RootConstrainSelectedInstOperands,
15422 /* 38941 */ // GIR_Coverage, 512,
15423 /* 38941 */ GIR_EraseRootFromParent_Done,
15424 /* 38942 */ // Label 1043: @38942
15425 /* 38942 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(38984), // Rule ID 458 //
15426 /* 38947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15427 /* 38950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
15428 /* 38955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15429 /* 38958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15430 /* 38961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15431 /* 38965 */ // MIs[0] base
15432 /* 38965 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15433 /* 38969 */ // (intrinsic_w_chain:{ *:[i32] } 8356:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15434 /* 38969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
15435 /* 38972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15436 /* 38974 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15437 /* 38976 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15438 /* 38978 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15439 /* 38982 */ GIR_RootConstrainSelectedInstOperands,
15440 /* 38983 */ // GIR_Coverage, 458,
15441 /* 38983 */ GIR_EraseRootFromParent_Done,
15442 /* 38984 */ // Label 1044: @38984
15443 /* 38984 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(39026), // Rule ID 459 //
15444 /* 38989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15445 /* 38992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
15446 /* 38997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15447 /* 39000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15448 /* 39003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15449 /* 39007 */ // MIs[0] base
15450 /* 39007 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15451 /* 39011 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15452 /* 39011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
15453 /* 39014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15454 /* 39016 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15455 /* 39018 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15456 /* 39020 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15457 /* 39024 */ GIR_RootConstrainSelectedInstOperands,
15458 /* 39025 */ // GIR_Coverage, 459,
15459 /* 39025 */ GIR_EraseRootFromParent_Done,
15460 /* 39026 */ // Label 1045: @39026
15461 /* 39026 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(39068), // Rule ID 460 //
15462 /* 39031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
15463 /* 39034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
15464 /* 39039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15465 /* 39042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15466 /* 39045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15467 /* 39049 */ // MIs[0] base
15468 /* 39049 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15469 /* 39053 */ // (intrinsic_w_chain:{ *:[i32] } 8343:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15470 /* 39053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
15471 /* 39056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15472 /* 39058 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15473 /* 39060 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15474 /* 39062 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15475 /* 39066 */ GIR_RootConstrainSelectedInstOperands,
15476 /* 39067 */ // GIR_Coverage, 460,
15477 /* 39067 */ GIR_EraseRootFromParent_Done,
15478 /* 39068 */ // Label 1046: @39068
15479 /* 39068 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(39110), // Rule ID 1300 //
15480 /* 39073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15481 /* 39076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
15482 /* 39081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15483 /* 39084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15484 /* 39087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15485 /* 39091 */ // MIs[0] base
15486 /* 39091 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15487 /* 39095 */ // (intrinsic_w_chain:{ *:[i32] } 8343:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15488 /* 39095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
15489 /* 39098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15490 /* 39100 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15491 /* 39102 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15492 /* 39104 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15493 /* 39108 */ GIR_RootConstrainSelectedInstOperands,
15494 /* 39109 */ // GIR_Coverage, 1300,
15495 /* 39109 */ GIR_EraseRootFromParent_Done,
15496 /* 39110 */ // Label 1047: @39110
15497 /* 39110 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(39152), // Rule ID 1301 //
15498 /* 39115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15499 /* 39118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
15500 /* 39123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15501 /* 39126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15502 /* 39129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15503 /* 39133 */ // MIs[0] base
15504 /* 39133 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15505 /* 39137 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15506 /* 39137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
15507 /* 39140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15508 /* 39142 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15509 /* 39144 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15510 /* 39146 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15511 /* 39150 */ GIR_RootConstrainSelectedInstOperands,
15512 /* 39151 */ // GIR_Coverage, 1301,
15513 /* 39151 */ GIR_EraseRootFromParent_Done,
15514 /* 39152 */ // Label 1048: @39152
15515 /* 39152 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(39194), // Rule ID 1302 //
15516 /* 39157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
15517 /* 39160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
15518 /* 39165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15519 /* 39168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15520 /* 39171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15521 /* 39175 */ // MIs[0] base
15522 /* 39175 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15523 /* 39179 */ // (intrinsic_w_chain:{ *:[i32] } 8356:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
15524 /* 39179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
15525 /* 39182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15526 /* 39184 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
15527 /* 39186 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
15528 /* 39188 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15529 /* 39192 */ GIR_RootConstrainSelectedInstOperands,
15530 /* 39193 */ // GIR_Coverage, 1302,
15531 /* 39193 */ GIR_EraseRootFromParent_Done,
15532 /* 39194 */ // Label 1049: @39194
15533 /* 39194 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(39240), // Rule ID 513 //
15534 /* 39199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15535 /* 39202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
15536 /* 39207 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
15537 /* 39210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15538 /* 39213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15539 /* 39217 */ // MIs[0] ptr
15540 /* 39217 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15541 /* 39221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15542 /* 39225 */ // (intrinsic_void 8586:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15543 /* 39225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
15544 /* 39228 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
15545 /* 39230 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15546 /* 39232 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15547 /* 39234 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15548 /* 39238 */ GIR_RootConstrainSelectedInstOperands,
15549 /* 39239 */ // GIR_Coverage, 513,
15550 /* 39239 */ GIR_EraseRootFromParent_Done,
15551 /* 39240 */ // Label 1050: @39240
15552 /* 39240 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(39286), // Rule ID 514 //
15553 /* 39245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
15554 /* 39248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
15555 /* 39253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
15556 /* 39256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
15557 /* 39259 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15558 /* 39263 */ // MIs[0] ptr
15559 /* 39263 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
15560 /* 39267 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15561 /* 39271 */ // (intrinsic_void 8587:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
15562 /* 39271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
15563 /* 39274 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
15564 /* 39276 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
15565 /* 39278 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
15566 /* 39280 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15567 /* 39284 */ GIR_RootConstrainSelectedInstOperands,
15568 /* 39285 */ // GIR_Coverage, 514,
15569 /* 39285 */ GIR_EraseRootFromParent_Done,
15570 /* 39286 */ // Label 1051: @39286
15571 /* 39286 */ GIM_Reject,
15572 /* 39287 */ // Label 970: @39287
15573 /* 39287 */ GIM_Reject,
15574 /* 39288 */ // Label 31: @39288
15575 /* 39288 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(39353), // Rule ID 1684 //
15576 /* 39293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15577 /* 39296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15578 /* 39299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15579 /* 39302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15580 /* 39306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15581 /* 39310 */ // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
15582 /* 39310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15583 /* 39313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15584 /* 39317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15585 /* 39322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15586 /* 39324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15587 /* 39327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15588 /* 39329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15589 /* 39332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15590 /* 39334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15591 /* 39337 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15592 /* 39342 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15593 /* 39347 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15594 /* 39352 */ // GIR_Coverage, 1684,
15595 /* 39352 */ GIR_EraseRootFromParent_Done,
15596 /* 39353 */ // Label 1052: @39353
15597 /* 39353 */ GIM_Reject,
15598 /* 39354 */ // Label 32: @39354
15599 /* 39354 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(39417), // Rule ID 1677 //
15600 /* 39359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15601 /* 39362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15602 /* 39365 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15603 /* 39368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15604 /* 39372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15605 /* 39376 */ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
15606 /* 39376 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15607 /* 39379 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15608 /* 39383 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15609 /* 39388 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
15610 /* 39394 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15611 /* 39399 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15612 /* 39404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
15613 /* 39407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15614 /* 39409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15615 /* 39412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15616 /* 39415 */ GIR_RootConstrainSelectedInstOperands,
15617 /* 39416 */ // GIR_Coverage, 1677,
15618 /* 39416 */ GIR_EraseRootFromParent_Done,
15619 /* 39417 */ // Label 1053: @39417
15620 /* 39417 */ GIM_Reject,
15621 /* 39418 */ // Label 33: @39418
15622 /* 39418 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(39478),
15623 /* 39423 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15624 /* 39426 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(39452), // Rule ID 2288 //
15625 /* 39431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15626 /* 39434 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
15627 /* 39438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15628 /* 39442 */ // MIs[0] Operand 1
15629 /* 39442 */ // No operand predicates
15630 /* 39442 */ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
15631 /* 39442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
15632 /* 39445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15633 /* 39447 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
15634 /* 39450 */ GIR_RootConstrainSelectedInstOperands,
15635 /* 39451 */ // GIR_Coverage, 2288,
15636 /* 39451 */ GIR_EraseRootFromParent_Done,
15637 /* 39452 */ // Label 1055: @39452
15638 /* 39452 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(39477), // Rule ID 1979 //
15639 /* 39457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15640 /* 39460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15641 /* 39464 */ // MIs[0] Operand 1
15642 /* 39464 */ // No operand predicates
15643 /* 39464 */ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
15644 /* 39464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
15645 /* 39467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15646 /* 39469 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
15647 /* 39472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
15648 /* 39475 */ GIR_RootConstrainSelectedInstOperands,
15649 /* 39476 */ // GIR_Coverage, 1979,
15650 /* 39476 */ GIR_EraseRootFromParent_Done,
15651 /* 39477 */ // Label 1056: @39477
15652 /* 39477 */ GIM_Reject,
15653 /* 39478 */ // Label 1054: @39478
15654 /* 39478 */ GIM_Reject,
15655 /* 39479 */ // Label 34: @39479
15656 /* 39479 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(40942),
15657 /* 39484 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15658 /* 39487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15659 /* 39490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15660 /* 39494 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(39599), // Rule ID 1733 //
15661 /* 39499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15662 /* 39503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
15663 /* 39507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15664 /* 39511 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15665 /* 39515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15666 /* 39520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15667 /* 39524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15668 /* 39528 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15669 /* 39532 */ // MIs[2] Operand 1
15670 /* 39532 */ // No operand predicates
15671 /* 39532 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15672 /* 39534 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15673 /* 39534 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15674 /* 39537 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
15675 /* 39541 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15676 /* 39546 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15677 /* 39550 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15678 /* 39553 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15679 /* 39555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15680 /* 39558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15681 /* 39562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15682 /* 39567 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15683 /* 39569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15684 /* 39572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15685 /* 39574 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15686 /* 39577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15687 /* 39580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15688 /* 39583 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15689 /* 39588 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15690 /* 39593 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15691 /* 39598 */ // GIR_Coverage, 1733,
15692 /* 39598 */ GIR_EraseRootFromParent_Done,
15693 /* 39599 */ // Label 1058: @39599
15694 /* 39599 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(39704), // Rule ID 1729 //
15695 /* 39604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15696 /* 39608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15697 /* 39612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15698 /* 39616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15699 /* 39620 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15700 /* 39625 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15701 /* 39629 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15702 /* 39633 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15703 /* 39637 */ // MIs[2] Operand 1
15704 /* 39637 */ // No operand predicates
15705 /* 39637 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15706 /* 39639 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15707 /* 39639 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15708 /* 39642 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
15709 /* 39646 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15710 /* 39651 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15711 /* 39655 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15712 /* 39658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15713 /* 39660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15714 /* 39663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15715 /* 39667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15716 /* 39672 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15717 /* 39674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15718 /* 39677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15719 /* 39679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15720 /* 39682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15721 /* 39685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15722 /* 39688 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15723 /* 39693 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15724 /* 39698 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15725 /* 39703 */ // GIR_Coverage, 1729,
15726 /* 39703 */ GIR_EraseRootFromParent_Done,
15727 /* 39704 */ // Label 1059: @39704
15728 /* 39704 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(39809), // Rule ID 1725 //
15729 /* 39709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15730 /* 39713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15731 /* 39717 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15732 /* 39721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15733 /* 39725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15734 /* 39730 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15735 /* 39734 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15736 /* 39738 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15737 /* 39742 */ // MIs[2] Operand 1
15738 /* 39742 */ // No operand predicates
15739 /* 39742 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
15740 /* 39744 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
15741 /* 39744 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15742 /* 39747 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
15743 /* 39751 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15744 /* 39756 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15745 /* 39760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
15746 /* 39763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15747 /* 39765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15748 /* 39768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15749 /* 39772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15750 /* 39777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15751 /* 39779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15752 /* 39782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15753 /* 39784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15754 /* 39787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15755 /* 39790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15756 /* 39793 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15757 /* 39798 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15758 /* 39803 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15759 /* 39808 */ // GIR_Coverage, 1725,
15760 /* 39808 */ GIR_EraseRootFromParent_Done,
15761 /* 39809 */ // Label 1060: @39809
15762 /* 39809 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(39908), // Rule ID 1715 //
15763 /* 39814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15764 /* 39818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
15765 /* 39822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15766 /* 39826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15767 /* 39830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15768 /* 39835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15769 /* 39840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15770 /* 39842 */ // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15771 /* 39842 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15772 /* 39845 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
15773 /* 39849 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15774 /* 39854 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15775 /* 39858 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15776 /* 39862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15777 /* 39864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15778 /* 39867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15779 /* 39871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15780 /* 39876 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15781 /* 39878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15782 /* 39881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15783 /* 39883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15784 /* 39886 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15785 /* 39889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15786 /* 39892 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15787 /* 39897 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15788 /* 39902 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15789 /* 39907 */ // GIR_Coverage, 1715,
15790 /* 39907 */ GIR_EraseRootFromParent_Done,
15791 /* 39908 */ // Label 1061: @39908
15792 /* 39908 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(40007), // Rule ID 1735 //
15793 /* 39913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15794 /* 39917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
15795 /* 39921 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15796 /* 39925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15797 /* 39929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15798 /* 39934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15799 /* 39939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15800 /* 39941 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15801 /* 39941 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15802 /* 39944 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
15803 /* 39948 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15804 /* 39953 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15805 /* 39957 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15806 /* 39961 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15807 /* 39963 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15808 /* 39966 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15809 /* 39970 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15810 /* 39975 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15811 /* 39977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15812 /* 39980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15813 /* 39982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15814 /* 39985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15815 /* 39988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15816 /* 39991 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15817 /* 39996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15818 /* 40001 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15819 /* 40006 */ // GIR_Coverage, 1735,
15820 /* 40006 */ GIR_EraseRootFromParent_Done,
15821 /* 40007 */ // Label 1062: @40007
15822 /* 40007 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(40106), // Rule ID 1731 //
15823 /* 40012 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15824 /* 40016 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
15825 /* 40020 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15826 /* 40024 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15827 /* 40028 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15828 /* 40033 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15829 /* 40038 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15830 /* 40040 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15831 /* 40040 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15832 /* 40043 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
15833 /* 40047 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15834 /* 40052 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15835 /* 40056 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15836 /* 40060 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15837 /* 40062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15838 /* 40065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15839 /* 40069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15840 /* 40074 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15841 /* 40076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15842 /* 40079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15843 /* 40081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15844 /* 40084 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15845 /* 40087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15846 /* 40090 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15847 /* 40095 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15848 /* 40100 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15849 /* 40105 */ // GIR_Coverage, 1731,
15850 /* 40105 */ GIR_EraseRootFromParent_Done,
15851 /* 40106 */ // Label 1063: @40106
15852 /* 40106 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(40214), // Rule ID 1719 //
15853 /* 40111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6),
15854 /* 40114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15855 /* 40118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15856 /* 40122 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15857 /* 40126 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15858 /* 40130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15859 /* 40135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15860 /* 40140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15861 /* 40142 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15862 /* 40142 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15863 /* 40145 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
15864 /* 40149 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15865 /* 40154 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15866 /* 40158 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15867 /* 40162 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
15868 /* 40165 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
15869 /* 40168 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15870 /* 40170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15871 /* 40173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15872 /* 40177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15873 /* 40182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15874 /* 40184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15875 /* 40187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15876 /* 40189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15877 /* 40192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15878 /* 40195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15879 /* 40198 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15880 /* 40203 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15881 /* 40208 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15882 /* 40213 */ // GIR_Coverage, 1719,
15883 /* 40213 */ GIR_EraseRootFromParent_Done,
15884 /* 40214 */ // Label 1064: @40214
15885 /* 40214 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(40316), // Rule ID 1930 //
15886 /* 40219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15887 /* 40222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15888 /* 40226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
15889 /* 40230 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15890 /* 40234 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15891 /* 40238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15892 /* 40243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15893 /* 40248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15894 /* 40250 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15895 /* 40250 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15896 /* 40253 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
15897 /* 40257 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15898 /* 40262 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15899 /* 40266 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15900 /* 40270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15901 /* 40272 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15902 /* 40275 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15903 /* 40279 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15904 /* 40284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15905 /* 40286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15906 /* 40289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15907 /* 40291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15908 /* 40294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15909 /* 40297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15910 /* 40300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15911 /* 40305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15912 /* 40310 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15913 /* 40315 */ // GIR_Coverage, 1930,
15914 /* 40315 */ GIR_EraseRootFromParent_Done,
15915 /* 40316 */ // Label 1065: @40316
15916 /* 40316 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(40418), // Rule ID 1931 //
15917 /* 40321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15918 /* 40324 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15919 /* 40328 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
15920 /* 40332 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15921 /* 40336 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15922 /* 40340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15923 /* 40345 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15924 /* 40350 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15925 /* 40352 */ // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15926 /* 40352 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15927 /* 40355 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
15928 /* 40359 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15929 /* 40364 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15930 /* 40368 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15931 /* 40372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15932 /* 40374 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15933 /* 40377 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15934 /* 40381 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15935 /* 40386 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15936 /* 40388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15937 /* 40391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15938 /* 40393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15939 /* 40396 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15940 /* 40399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15941 /* 40402 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15942 /* 40407 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15943 /* 40412 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15944 /* 40417 */ // GIR_Coverage, 1931,
15945 /* 40417 */ GIR_EraseRootFromParent_Done,
15946 /* 40418 */ // Label 1066: @40418
15947 /* 40418 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(40517), // Rule ID 1727 //
15948 /* 40423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15949 /* 40427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
15950 /* 40431 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15951 /* 40435 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15952 /* 40439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15953 /* 40444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15954 /* 40449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15955 /* 40451 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15956 /* 40451 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15957 /* 40454 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15958 /* 40458 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15959 /* 40463 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15960 /* 40467 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15961 /* 40471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15962 /* 40473 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15963 /* 40476 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15964 /* 40480 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15965 /* 40485 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15966 /* 40487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15967 /* 40490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15968 /* 40492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15969 /* 40495 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15970 /* 40498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15971 /* 40501 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15972 /* 40506 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15973 /* 40511 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15974 /* 40516 */ // GIR_Coverage, 1727,
15975 /* 40516 */ GIR_EraseRootFromParent_Done,
15976 /* 40517 */ // Label 1067: @40517
15977 /* 40517 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(40619), // Rule ID 1933 //
15978 /* 40522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
15979 /* 40525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15980 /* 40529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
15981 /* 40533 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15982 /* 40537 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15983 /* 40541 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15984 /* 40546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15985 /* 40551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15986 /* 40553 */ // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15987 /* 40553 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15988 /* 40556 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
15989 /* 40560 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15990 /* 40565 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15991 /* 40569 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15992 /* 40573 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15993 /* 40575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15994 /* 40578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15995 /* 40582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15996 /* 40587 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15997 /* 40589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15998 /* 40592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15999 /* 40594 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16000 /* 40597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16001 /* 40600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16002 /* 40603 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16003 /* 40608 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16004 /* 40613 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16005 /* 40618 */ // GIR_Coverage, 1933,
16006 /* 40618 */ GIR_EraseRootFromParent_Done,
16007 /* 40619 */ // Label 1068: @40619
16008 /* 40619 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(40718), // Rule ID 1717 //
16009 /* 40624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16010 /* 40628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
16011 /* 40632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16012 /* 40636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16013 /* 40640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16014 /* 40645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16015 /* 40650 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16016 /* 40652 */ // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16017 /* 40652 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16018 /* 40655 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
16019 /* 40659 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16020 /* 40664 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16021 /* 40668 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16022 /* 40672 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16023 /* 40674 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16024 /* 40677 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16025 /* 40681 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16026 /* 40686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16027 /* 40688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16028 /* 40691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16029 /* 40693 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16030 /* 40696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16031 /* 40699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16032 /* 40702 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16033 /* 40707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16034 /* 40712 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16035 /* 40717 */ // GIR_Coverage, 1717,
16036 /* 40717 */ GIR_EraseRootFromParent_Done,
16037 /* 40718 */ // Label 1069: @40718
16038 /* 40718 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(40820), // Rule ID 1932 //
16039 /* 40723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
16040 /* 40726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16041 /* 40730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
16042 /* 40734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16043 /* 40738 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16044 /* 40742 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16045 /* 40747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16046 /* 40752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16047 /* 40754 */ // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16048 /* 40754 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16049 /* 40757 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
16050 /* 40761 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16051 /* 40766 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16052 /* 40770 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16053 /* 40774 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16054 /* 40776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16055 /* 40779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16056 /* 40783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16057 /* 40788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16058 /* 40790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16059 /* 40793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16060 /* 40795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16061 /* 40798 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16062 /* 40801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16063 /* 40804 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16064 /* 40809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16065 /* 40814 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16066 /* 40819 */ // GIR_Coverage, 1932,
16067 /* 40819 */ GIR_EraseRootFromParent_Done,
16068 /* 40820 */ // Label 1070: @40820
16069 /* 40820 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(40922), // Rule ID 1934 //
16070 /* 40825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
16071 /* 40828 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16072 /* 40832 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
16073 /* 40836 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16074 /* 40840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16075 /* 40844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16076 /* 40849 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16077 /* 40854 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16078 /* 40856 */ // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
16079 /* 40856 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16080 /* 40859 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
16081 /* 40863 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16082 /* 40868 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
16083 /* 40872 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
16084 /* 40876 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16085 /* 40878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16086 /* 40881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16087 /* 40885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16088 /* 40890 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16089 /* 40892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16090 /* 40895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16091 /* 40897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16092 /* 40900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16093 /* 40903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16094 /* 40906 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
16095 /* 40911 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16096 /* 40916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
16097 /* 40921 */ // GIR_Coverage, 1934,
16098 /* 40921 */ GIR_EraseRootFromParent_Done,
16099 /* 40922 */ // Label 1071: @40922
16100 /* 40922 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(40941), // Rule ID 1687 //
16101 /* 40927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16102 /* 40930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16103 /* 40934 */ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
16104 /* 40934 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
16105 /* 40939 */ GIR_RootConstrainSelectedInstOperands,
16106 /* 40940 */ // GIR_Coverage, 1687,
16107 /* 40940 */ GIR_Done,
16108 /* 40941 */ // Label 1072: @40941
16109 /* 40941 */ GIM_Reject,
16110 /* 40942 */ // Label 1057: @40942
16111 /* 40942 */ GIM_Reject,
16112 /* 40943 */ // Label 35: @40943
16113 /* 40943 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1075*/ GIMT_Encode4(41290),
16114 /* 40954 */ /*GILLT_s32*//*Label 1073*/ GIMT_Encode4(40962),
16115 /* 40958 */ /*GILLT_s64*//*Label 1074*/ GIMT_Encode4(41188),
16116 /* 40962 */ // Label 1073: @40962
16117 /* 40962 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(41187),
16118 /* 40967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16119 /* 40970 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(41006), // Rule ID 106 //
16120 /* 40975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16121 /* 40978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16122 /* 40982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16123 /* 40986 */ // MIs[0] Operand 2
16124 /* 40986 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16125 /* 40997 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16126 /* 40997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
16127 /* 41000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16128 /* 41002 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16129 /* 41004 */ GIR_RootConstrainSelectedInstOperands,
16130 /* 41005 */ // GIR_Coverage, 106,
16131 /* 41005 */ GIR_EraseRootFromParent_Done,
16132 /* 41006 */ // Label 1077: @41006
16133 /* 41006 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(41042), // Rule ID 107 //
16134 /* 41011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16135 /* 41014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16136 /* 41018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16137 /* 41022 */ // MIs[0] Operand 2
16138 /* 41022 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16139 /* 41033 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16140 /* 41033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
16141 /* 41036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16142 /* 41038 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16143 /* 41040 */ GIR_RootConstrainSelectedInstOperands,
16144 /* 41041 */ // GIR_Coverage, 107,
16145 /* 41041 */ GIR_EraseRootFromParent_Done,
16146 /* 41042 */ // Label 1078: @41042
16147 /* 41042 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(41078), // Rule ID 1125 //
16148 /* 41047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16149 /* 41050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16150 /* 41054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16151 /* 41058 */ // MIs[0] Operand 2
16152 /* 41058 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16153 /* 41069 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16154 /* 41069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
16155 /* 41072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16156 /* 41074 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16157 /* 41076 */ GIR_RootConstrainSelectedInstOperands,
16158 /* 41077 */ // GIR_Coverage, 1125,
16159 /* 41077 */ GIR_EraseRootFromParent_Done,
16160 /* 41078 */ // Label 1079: @41078
16161 /* 41078 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(41114), // Rule ID 1126 //
16162 /* 41083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16163 /* 41086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16164 /* 41090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16165 /* 41094 */ // MIs[0] Operand 2
16166 /* 41094 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16167 /* 41105 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
16168 /* 41105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
16169 /* 41108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16170 /* 41110 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16171 /* 41112 */ GIR_RootConstrainSelectedInstOperands,
16172 /* 41113 */ // GIR_Coverage, 1126,
16173 /* 41113 */ GIR_EraseRootFromParent_Done,
16174 /* 41114 */ // Label 1080: @41114
16175 /* 41114 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(41150), // Rule ID 2037 //
16176 /* 41119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16177 /* 41122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16178 /* 41126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16179 /* 41130 */ // MIs[0] Operand 2
16180 /* 41130 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16181 /* 41141 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) => (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
16182 /* 41141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
16183 /* 41144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16184 /* 41146 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
16185 /* 41148 */ GIR_RootConstrainSelectedInstOperands,
16186 /* 41149 */ // GIR_Coverage, 2037,
16187 /* 41149 */ GIR_EraseRootFromParent_Done,
16188 /* 41150 */ // Label 1081: @41150
16189 /* 41150 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(41186), // Rule ID 2038 //
16190 /* 41155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16191 /* 41158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16192 /* 41162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16193 /* 41166 */ // MIs[0] Operand 2
16194 /* 41166 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16195 /* 41177 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) => (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
16196 /* 41177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
16197 /* 41180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16198 /* 41182 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
16199 /* 41184 */ GIR_RootConstrainSelectedInstOperands,
16200 /* 41185 */ // GIR_Coverage, 2038,
16201 /* 41185 */ GIR_EraseRootFromParent_Done,
16202 /* 41186 */ // Label 1082: @41186
16203 /* 41186 */ GIM_Reject,
16204 /* 41187 */ // Label 1076: @41187
16205 /* 41187 */ GIM_Reject,
16206 /* 41188 */ // Label 1074: @41188
16207 /* 41188 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(41289),
16208 /* 41193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16209 /* 41196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16210 /* 41200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16211 /* 41204 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(41232), // Rule ID 285 //
16212 /* 41209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
16213 /* 41212 */ // MIs[0] Operand 2
16214 /* 41212 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
16215 /* 41223 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) => (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
16216 /* 41223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
16217 /* 41226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16218 /* 41228 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16219 /* 41230 */ GIR_RootConstrainSelectedInstOperands,
16220 /* 41231 */ // GIR_Coverage, 285,
16221 /* 41231 */ GIR_EraseRootFromParent_Done,
16222 /* 41232 */ // Label 1084: @41232
16223 /* 41232 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(41260), // Rule ID 286 //
16224 /* 41237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
16225 /* 41240 */ // MIs[0] Operand 2
16226 /* 41240 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
16227 /* 41251 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) => (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
16228 /* 41251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
16229 /* 41254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16230 /* 41256 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16231 /* 41258 */ GIR_RootConstrainSelectedInstOperands,
16232 /* 41259 */ // GIR_Coverage, 286,
16233 /* 41259 */ GIR_EraseRootFromParent_Done,
16234 /* 41260 */ // Label 1085: @41260
16235 /* 41260 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(41288), // Rule ID 1690 //
16236 /* 41265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16237 /* 41268 */ // MIs[0] Operand 2
16238 /* 41268 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
16239 /* 41279 */ // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) => (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
16240 /* 41279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
16241 /* 41282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16242 /* 41284 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16243 /* 41286 */ GIR_RootConstrainSelectedInstOperands,
16244 /* 41287 */ // GIR_Coverage, 1690,
16245 /* 41287 */ GIR_EraseRootFromParent_Done,
16246 /* 41288 */ // Label 1086: @41288
16247 /* 41288 */ GIM_Reject,
16248 /* 41289 */ // Label 1083: @41289
16249 /* 41289 */ GIM_Reject,
16250 /* 41290 */ // Label 1075: @41290
16251 /* 41290 */ GIM_Reject,
16252 /* 41291 */ // Label 36: @41291
16253 /* 41291 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(41491),
16254 /* 41296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
16255 /* 41299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16256 /* 41302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16257 /* 41306 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(41362), // Rule ID 304 //
16258 /* 41311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
16259 /* 41314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16260 /* 41318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16261 /* 41322 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16262 /* 41326 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16263 /* 41330 */ // MIs[1] Operand 1
16264 /* 41330 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16265 /* 41335 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16266 /* 41340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16267 /* 41345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16268 /* 41347 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16269 /* 41347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
16270 /* 41350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16271 /* 41352 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
16272 /* 41356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
16273 /* 41360 */ GIR_RootConstrainSelectedInstOperands,
16274 /* 41361 */ // GIR_Coverage, 304,
16275 /* 41361 */ GIR_EraseRootFromParent_Done,
16276 /* 41362 */ // Label 1088: @41362
16277 /* 41362 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(41418), // Rule ID 306 //
16278 /* 41367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
16279 /* 41370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
16280 /* 41374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
16281 /* 41378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
16282 /* 41382 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
16283 /* 41386 */ // MIs[1] Operand 1
16284 /* 41386 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16285 /* 41391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16286 /* 41396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16287 /* 41401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16288 /* 41403 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16289 /* 41403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
16290 /* 41406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16291 /* 41408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
16292 /* 41412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
16293 /* 41416 */ GIR_RootConstrainSelectedInstOperands,
16294 /* 41417 */ // GIR_Coverage, 306,
16295 /* 41417 */ GIR_EraseRootFromParent_Done,
16296 /* 41418 */ // Label 1089: @41418
16297 /* 41418 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(41490),
16298 /* 41423 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16299 /* 41427 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(41466), // Rule ID 1685 //
16300 /* 41432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16301 /* 41435 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
16302 /* 41435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
16303 /* 41438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
16304 /* 41442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16305 /* 41447 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
16306 /* 41451 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16307 /* 41453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
16308 /* 41456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16309 /* 41458 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16310 /* 41461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
16311 /* 41464 */ GIR_RootConstrainSelectedInstOperands,
16312 /* 41465 */ // GIR_Coverage, 1685,
16313 /* 41465 */ GIR_EraseRootFromParent_Done,
16314 /* 41466 */ // Label 1091: @41466
16315 /* 41466 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(41489), // Rule ID 1688 //
16316 /* 41471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips),
16317 /* 41474 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
16318 /* 41474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
16319 /* 41477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16320 /* 41479 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16321 /* 41481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16322 /* 41484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
16323 /* 41487 */ GIR_RootConstrainSelectedInstOperands,
16324 /* 41488 */ // GIR_Coverage, 1688,
16325 /* 41488 */ GIR_EraseRootFromParent_Done,
16326 /* 41489 */ // Label 1092: @41489
16327 /* 41489 */ GIM_Reject,
16328 /* 41490 */ // Label 1090: @41490
16329 /* 41490 */ GIM_Reject,
16330 /* 41491 */ // Label 1087: @41491
16331 /* 41491 */ GIM_Reject,
16332 /* 41492 */ // Label 37: @41492
16333 /* 41492 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1099*/ GIMT_Encode4(43288),
16334 /* 41503 */ /*GILLT_s32*//*Label 1093*/ GIMT_Encode4(41535),
16335 /* 41507 */ /*GILLT_s64*//*Label 1094*/ GIMT_Encode4(41797), GIMT_Encode4(0),
16336 /* 41515 */ /*GILLT_v2s64*//*Label 1095*/ GIMT_Encode4(41938), GIMT_Encode4(0),
16337 /* 41523 */ /*GILLT_v4s32*//*Label 1096*/ GIMT_Encode4(41972),
16338 /* 41527 */ /*GILLT_v8s16*//*Label 1097*/ GIMT_Encode4(42240),
16339 /* 41531 */ /*GILLT_v16s8*//*Label 1098*/ GIMT_Encode4(42636),
16340 /* 41535 */ // Label 1093: @41535
16341 /* 41535 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(41796),
16342 /* 41540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16343 /* 41543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16344 /* 41546 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(41588), // Rule ID 55 //
16345 /* 41551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16346 /* 41554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16347 /* 41558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16348 /* 41562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16349 /* 41566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16350 /* 41570 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16351 /* 41574 */ // MIs[1] Operand 1
16352 /* 41574 */ // No operand predicates
16353 /* 41574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16354 /* 41576 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16355 /* 41576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
16356 /* 41579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16357 /* 41581 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16358 /* 41583 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16359 /* 41586 */ GIR_RootConstrainSelectedInstOperands,
16360 /* 41587 */ // GIR_Coverage, 55,
16361 /* 41587 */ GIR_EraseRootFromParent_Done,
16362 /* 41588 */ // Label 1101: @41588
16363 /* 41588 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(41630), // Rule ID 1961 //
16364 /* 41593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16365 /* 41596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16366 /* 41600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16367 /* 41604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16368 /* 41608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16369 /* 41612 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16370 /* 41616 */ // MIs[1] Operand 1
16371 /* 41616 */ // No operand predicates
16372 /* 41616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16373 /* 41618 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16374 /* 41618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
16375 /* 41621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16376 /* 41623 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16377 /* 41625 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16378 /* 41628 */ GIR_RootConstrainSelectedInstOperands,
16379 /* 41629 */ // GIR_Coverage, 1961,
16380 /* 41629 */ GIR_EraseRootFromParent_Done,
16381 /* 41630 */ // Label 1102: @41630
16382 /* 41630 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(41672), // Rule ID 2300 //
16383 /* 41635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16384 /* 41638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16385 /* 41642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16386 /* 41646 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16387 /* 41650 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16388 /* 41654 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16389 /* 41658 */ // MIs[1] Operand 1
16390 /* 41658 */ // No operand predicates
16391 /* 41658 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16392 /* 41660 */ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16393 /* 41660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
16394 /* 41663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16395 /* 41665 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16396 /* 41667 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16397 /* 41670 */ GIR_RootConstrainSelectedInstOperands,
16398 /* 41671 */ // GIR_Coverage, 2300,
16399 /* 41671 */ GIR_EraseRootFromParent_Done,
16400 /* 41672 */ // Label 1103: @41672
16401 /* 41672 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(41714), // Rule ID 2301 //
16402 /* 41677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16403 /* 41680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16404 /* 41684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16405 /* 41688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16406 /* 41692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16407 /* 41696 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16408 /* 41700 */ // MIs[1] Operand 1
16409 /* 41700 */ // No operand predicates
16410 /* 41700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16411 /* 41702 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16412 /* 41702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
16413 /* 41705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16414 /* 41707 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16415 /* 41709 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16416 /* 41712 */ GIR_RootConstrainSelectedInstOperands,
16417 /* 41713 */ // GIR_Coverage, 2301,
16418 /* 41713 */ GIR_EraseRootFromParent_Done,
16419 /* 41714 */ // Label 1104: @41714
16420 /* 41714 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(41741), // Rule ID 61 //
16421 /* 41719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16422 /* 41722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16423 /* 41726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16424 /* 41730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16425 /* 41734 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16426 /* 41734 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
16427 /* 41739 */ GIR_RootConstrainSelectedInstOperands,
16428 /* 41740 */ // GIR_Coverage, 61,
16429 /* 41740 */ GIR_Done,
16430 /* 41741 */ // Label 1105: @41741
16431 /* 41741 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(41768), // Rule ID 1964 //
16432 /* 41746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16433 /* 41749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16434 /* 41753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16435 /* 41757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16436 /* 41761 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16437 /* 41761 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
16438 /* 41766 */ GIR_RootConstrainSelectedInstOperands,
16439 /* 41767 */ // GIR_Coverage, 1964,
16440 /* 41767 */ GIR_Done,
16441 /* 41768 */ // Label 1106: @41768
16442 /* 41768 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(41795), // Rule ID 2302 //
16443 /* 41773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16444 /* 41776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16445 /* 41780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16446 /* 41784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16447 /* 41788 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16448 /* 41788 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
16449 /* 41793 */ GIR_RootConstrainSelectedInstOperands,
16450 /* 41794 */ // GIR_Coverage, 2302,
16451 /* 41794 */ GIR_Done,
16452 /* 41795 */ // Label 1107: @41795
16453 /* 41795 */ GIM_Reject,
16454 /* 41796 */ // Label 1100: @41796
16455 /* 41796 */ GIM_Reject,
16456 /* 41797 */ // Label 1094: @41797
16457 /* 41797 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(41937),
16458 /* 41802 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16459 /* 41805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16460 /* 41808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16461 /* 41812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16462 /* 41816 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(41850), // Rule ID 234 //
16463 /* 41821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16464 /* 41824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16465 /* 41828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16466 /* 41832 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16467 /* 41836 */ // MIs[1] Operand 1
16468 /* 41836 */ // No operand predicates
16469 /* 41836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16470 /* 41838 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16471 /* 41838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
16472 /* 41841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16473 /* 41843 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16474 /* 41845 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16475 /* 41848 */ GIR_RootConstrainSelectedInstOperands,
16476 /* 41849 */ // GIR_Coverage, 234,
16477 /* 41849 */ GIR_EraseRootFromParent_Done,
16478 /* 41850 */ // Label 1109: @41850
16479 /* 41850 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(41917), // Rule ID 1678 //
16480 /* 41855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16481 /* 41858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16482 /* 41862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16483 /* 41866 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16484 /* 41870 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16485 /* 41875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16486 /* 41877 */ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16487 /* 41877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16488 /* 41880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16489 /* 41884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16490 /* 41889 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16491 /* 41895 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16492 /* 41900 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16493 /* 41905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
16494 /* 41908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16495 /* 41910 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16496 /* 41912 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16497 /* 41915 */ GIR_RootConstrainSelectedInstOperands,
16498 /* 41916 */ // GIR_Coverage, 1678,
16499 /* 41916 */ GIR_EraseRootFromParent_Done,
16500 /* 41917 */ // Label 1110: @41917
16501 /* 41917 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(41936), // Rule ID 240 //
16502 /* 41922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16503 /* 41925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16504 /* 41929 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16505 /* 41929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
16506 /* 41934 */ GIR_RootConstrainSelectedInstOperands,
16507 /* 41935 */ // GIR_Coverage, 240,
16508 /* 41935 */ GIR_Done,
16509 /* 41936 */ // Label 1111: @41936
16510 /* 41936 */ GIM_Reject,
16511 /* 41937 */ // Label 1108: @41937
16512 /* 41937 */ GIM_Reject,
16513 /* 41938 */ // Label 1095: @41938
16514 /* 41938 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(41971), // Rule ID 984 //
16515 /* 41943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16516 /* 41946 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16517 /* 41949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16518 /* 41952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16519 /* 41956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16520 /* 41960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16521 /* 41964 */ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16522 /* 41964 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
16523 /* 41969 */ GIR_RootConstrainSelectedInstOperands,
16524 /* 41970 */ // GIR_Coverage, 984,
16525 /* 41970 */ GIR_Done,
16526 /* 41971 */ // Label 1112: @41971
16527 /* 41971 */ GIM_Reject,
16528 /* 41972 */ // Label 1096: @41972
16529 /* 41972 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(42239),
16530 /* 41977 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16531 /* 41980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16532 /* 41983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16533 /* 41987 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(42101), // Rule ID 2636 //
16534 /* 41992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16535 /* 41995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16536 /* 41999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16537 /* 42003 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16538 /* 42007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16539 /* 42011 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16540 /* 42015 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16541 /* 42019 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16542 /* 42022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16543 /* 42026 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16544 /* 42030 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16545 /* 42034 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16546 /* 42038 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16547 /* 42042 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16548 /* 42046 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16549 /* 42050 */ // MIs[3] Operand 1
16550 /* 42050 */ // No operand predicates
16551 /* 42050 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16552 /* 42054 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16553 /* 42058 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16554 /* 42062 */ // MIs[4] Operand 1
16555 /* 42062 */ // No operand predicates
16556 /* 42062 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16557 /* 42066 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16558 /* 42070 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16559 /* 42074 */ // MIs[5] Operand 1
16560 /* 42074 */ // No operand predicates
16561 /* 42074 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16562 /* 42078 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16563 /* 42082 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16564 /* 42086 */ // MIs[6] Operand 1
16565 /* 42086 */ // No operand predicates
16566 /* 42086 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16567 /* 42088 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16568 /* 42088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16569 /* 42091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16570 /* 42093 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16571 /* 42095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16572 /* 42099 */ GIR_RootConstrainSelectedInstOperands,
16573 /* 42100 */ // GIR_Coverage, 2636,
16574 /* 42100 */ GIR_EraseRootFromParent_Done,
16575 /* 42101 */ // Label 1114: @42101
16576 /* 42101 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(42215), // Rule ID 2201 //
16577 /* 42106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16578 /* 42109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16579 /* 42113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16580 /* 42117 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16581 /* 42121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16582 /* 42125 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16583 /* 42129 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16584 /* 42133 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16585 /* 42136 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16586 /* 42140 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16587 /* 42144 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16588 /* 42148 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16589 /* 42152 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16590 /* 42156 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16591 /* 42160 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16592 /* 42164 */ // MIs[3] Operand 1
16593 /* 42164 */ // No operand predicates
16594 /* 42164 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16595 /* 42168 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16596 /* 42172 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16597 /* 42176 */ // MIs[4] Operand 1
16598 /* 42176 */ // No operand predicates
16599 /* 42176 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16600 /* 42180 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16601 /* 42184 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16602 /* 42188 */ // MIs[5] Operand 1
16603 /* 42188 */ // No operand predicates
16604 /* 42188 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16605 /* 42192 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16606 /* 42196 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16607 /* 42200 */ // MIs[6] Operand 1
16608 /* 42200 */ // No operand predicates
16609 /* 42200 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16610 /* 42202 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16611 /* 42202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16612 /* 42205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16613 /* 42207 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16614 /* 42209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16615 /* 42213 */ GIR_RootConstrainSelectedInstOperands,
16616 /* 42214 */ // GIR_Coverage, 2201,
16617 /* 42214 */ GIR_EraseRootFromParent_Done,
16618 /* 42215 */ // Label 1115: @42215
16619 /* 42215 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(42238), // Rule ID 983 //
16620 /* 42220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16621 /* 42223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16622 /* 42227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16623 /* 42231 */ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16624 /* 42231 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
16625 /* 42236 */ GIR_RootConstrainSelectedInstOperands,
16626 /* 42237 */ // GIR_Coverage, 983,
16627 /* 42237 */ GIR_Done,
16628 /* 42238 */ // Label 1116: @42238
16629 /* 42238 */ GIM_Reject,
16630 /* 42239 */ // Label 1113: @42239
16631 /* 42239 */ GIM_Reject,
16632 /* 42240 */ // Label 1097: @42240
16633 /* 42240 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(42635),
16634 /* 42245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16635 /* 42248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16636 /* 42251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16637 /* 42255 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(42433), // Rule ID 2635 //
16638 /* 42260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16639 /* 42263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16640 /* 42267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16641 /* 42271 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16642 /* 42275 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16643 /* 42279 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16644 /* 42283 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16645 /* 42287 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16646 /* 42290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16647 /* 42294 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16648 /* 42298 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16649 /* 42302 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16650 /* 42306 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16651 /* 42310 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16652 /* 42314 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16653 /* 42318 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16654 /* 42322 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16655 /* 42326 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16656 /* 42330 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16657 /* 42334 */ // MIs[3] Operand 1
16658 /* 42334 */ // No operand predicates
16659 /* 42334 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16660 /* 42338 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16661 /* 42342 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16662 /* 42346 */ // MIs[4] Operand 1
16663 /* 42346 */ // No operand predicates
16664 /* 42346 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16665 /* 42350 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16666 /* 42354 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16667 /* 42358 */ // MIs[5] Operand 1
16668 /* 42358 */ // No operand predicates
16669 /* 42358 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16670 /* 42362 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16671 /* 42366 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16672 /* 42370 */ // MIs[6] Operand 1
16673 /* 42370 */ // No operand predicates
16674 /* 42370 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16675 /* 42374 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16676 /* 42378 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16677 /* 42382 */ // MIs[7] Operand 1
16678 /* 42382 */ // No operand predicates
16679 /* 42382 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16680 /* 42386 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16681 /* 42390 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16682 /* 42394 */ // MIs[8] Operand 1
16683 /* 42394 */ // No operand predicates
16684 /* 42394 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16685 /* 42398 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16686 /* 42402 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16687 /* 42406 */ // MIs[9] Operand 1
16688 /* 42406 */ // No operand predicates
16689 /* 42406 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16690 /* 42410 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16691 /* 42414 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16692 /* 42418 */ // MIs[10] Operand 1
16693 /* 42418 */ // No operand predicates
16694 /* 42418 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16695 /* 42420 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16696 /* 42420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16697 /* 42423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16698 /* 42425 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16699 /* 42427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16700 /* 42431 */ GIR_RootConstrainSelectedInstOperands,
16701 /* 42432 */ // GIR_Coverage, 2635,
16702 /* 42432 */ GIR_EraseRootFromParent_Done,
16703 /* 42433 */ // Label 1118: @42433
16704 /* 42433 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(42611), // Rule ID 2200 //
16705 /* 42438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16706 /* 42441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16707 /* 42445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16708 /* 42449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16709 /* 42453 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16710 /* 42457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16711 /* 42461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16712 /* 42465 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16713 /* 42468 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16714 /* 42472 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16715 /* 42476 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16716 /* 42480 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16717 /* 42484 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16718 /* 42488 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16719 /* 42492 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16720 /* 42496 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16721 /* 42500 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16722 /* 42504 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16723 /* 42508 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16724 /* 42512 */ // MIs[3] Operand 1
16725 /* 42512 */ // No operand predicates
16726 /* 42512 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16727 /* 42516 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16728 /* 42520 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16729 /* 42524 */ // MIs[4] Operand 1
16730 /* 42524 */ // No operand predicates
16731 /* 42524 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16732 /* 42528 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16733 /* 42532 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16734 /* 42536 */ // MIs[5] Operand 1
16735 /* 42536 */ // No operand predicates
16736 /* 42536 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16737 /* 42540 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16738 /* 42544 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16739 /* 42548 */ // MIs[6] Operand 1
16740 /* 42548 */ // No operand predicates
16741 /* 42548 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16742 /* 42552 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16743 /* 42556 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16744 /* 42560 */ // MIs[7] Operand 1
16745 /* 42560 */ // No operand predicates
16746 /* 42560 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16747 /* 42564 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16748 /* 42568 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16749 /* 42572 */ // MIs[8] Operand 1
16750 /* 42572 */ // No operand predicates
16751 /* 42572 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16752 /* 42576 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16753 /* 42580 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16754 /* 42584 */ // MIs[9] Operand 1
16755 /* 42584 */ // No operand predicates
16756 /* 42584 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16757 /* 42588 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16758 /* 42592 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16759 /* 42596 */ // MIs[10] Operand 1
16760 /* 42596 */ // No operand predicates
16761 /* 42596 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16762 /* 42598 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16763 /* 42598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16764 /* 42601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16765 /* 42603 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16766 /* 42605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16767 /* 42609 */ GIR_RootConstrainSelectedInstOperands,
16768 /* 42610 */ // GIR_Coverage, 2200,
16769 /* 42610 */ GIR_EraseRootFromParent_Done,
16770 /* 42611 */ // Label 1119: @42611
16771 /* 42611 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(42634), // Rule ID 982 //
16772 /* 42616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16773 /* 42619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16774 /* 42623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16775 /* 42627 */ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16776 /* 42627 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
16777 /* 42632 */ GIR_RootConstrainSelectedInstOperands,
16778 /* 42633 */ // GIR_Coverage, 982,
16779 /* 42633 */ GIR_Done,
16780 /* 42634 */ // Label 1120: @42634
16781 /* 42634 */ GIM_Reject,
16782 /* 42635 */ // Label 1117: @42635
16783 /* 42635 */ GIM_Reject,
16784 /* 42636 */ // Label 1098: @42636
16785 /* 42636 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(43287),
16786 /* 42641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16787 /* 42644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16788 /* 42647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16789 /* 42651 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(42957), // Rule ID 2634 //
16790 /* 42656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16791 /* 42659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16792 /* 42663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16793 /* 42667 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16794 /* 42671 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16795 /* 42675 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16796 /* 42679 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16797 /* 42683 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16798 /* 42686 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16799 /* 42690 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16800 /* 42694 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16801 /* 42698 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16802 /* 42702 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16803 /* 42706 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16804 /* 42710 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16805 /* 42714 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16806 /* 42718 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16807 /* 42722 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16808 /* 42726 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16809 /* 42730 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16810 /* 42734 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16811 /* 42738 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16812 /* 42742 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16813 /* 42746 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16814 /* 42750 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16815 /* 42754 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16816 /* 42758 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16817 /* 42762 */ // MIs[3] Operand 1
16818 /* 42762 */ // No operand predicates
16819 /* 42762 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16820 /* 42766 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16821 /* 42770 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16822 /* 42774 */ // MIs[4] Operand 1
16823 /* 42774 */ // No operand predicates
16824 /* 42774 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16825 /* 42778 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16826 /* 42782 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16827 /* 42786 */ // MIs[5] Operand 1
16828 /* 42786 */ // No operand predicates
16829 /* 42786 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16830 /* 42790 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16831 /* 42794 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16832 /* 42798 */ // MIs[6] Operand 1
16833 /* 42798 */ // No operand predicates
16834 /* 42798 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16835 /* 42802 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16836 /* 42806 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16837 /* 42810 */ // MIs[7] Operand 1
16838 /* 42810 */ // No operand predicates
16839 /* 42810 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16840 /* 42814 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16841 /* 42818 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16842 /* 42822 */ // MIs[8] Operand 1
16843 /* 42822 */ // No operand predicates
16844 /* 42822 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16845 /* 42826 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16846 /* 42830 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16847 /* 42834 */ // MIs[9] Operand 1
16848 /* 42834 */ // No operand predicates
16849 /* 42834 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16850 /* 42838 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16851 /* 42842 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16852 /* 42846 */ // MIs[10] Operand 1
16853 /* 42846 */ // No operand predicates
16854 /* 42846 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16855 /* 42850 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16856 /* 42854 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16857 /* 42858 */ // MIs[11] Operand 1
16858 /* 42858 */ // No operand predicates
16859 /* 42858 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16860 /* 42862 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16861 /* 42866 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16862 /* 42870 */ // MIs[12] Operand 1
16863 /* 42870 */ // No operand predicates
16864 /* 42870 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16865 /* 42874 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16866 /* 42878 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16867 /* 42882 */ // MIs[13] Operand 1
16868 /* 42882 */ // No operand predicates
16869 /* 42882 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16870 /* 42886 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16871 /* 42890 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16872 /* 42894 */ // MIs[14] Operand 1
16873 /* 42894 */ // No operand predicates
16874 /* 42894 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16875 /* 42898 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16876 /* 42902 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16877 /* 42906 */ // MIs[15] Operand 1
16878 /* 42906 */ // No operand predicates
16879 /* 42906 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16880 /* 42910 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16881 /* 42914 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16882 /* 42918 */ // MIs[16] Operand 1
16883 /* 42918 */ // No operand predicates
16884 /* 42918 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16885 /* 42922 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16886 /* 42926 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16887 /* 42930 */ // MIs[17] Operand 1
16888 /* 42930 */ // No operand predicates
16889 /* 42930 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16890 /* 42934 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16891 /* 42938 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16892 /* 42942 */ // MIs[18] Operand 1
16893 /* 42942 */ // No operand predicates
16894 /* 42942 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16895 /* 42944 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16896 /* 42944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
16897 /* 42947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16898 /* 42949 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16899 /* 42951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16900 /* 42955 */ GIR_RootConstrainSelectedInstOperands,
16901 /* 42956 */ // GIR_Coverage, 2634,
16902 /* 42956 */ GIR_EraseRootFromParent_Done,
16903 /* 42957 */ // Label 1122: @42957
16904 /* 42957 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(43263), // Rule ID 2199 //
16905 /* 42962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16906 /* 42965 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16907 /* 42969 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16908 /* 42973 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16909 /* 42977 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16910 /* 42981 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16911 /* 42985 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16912 /* 42989 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16913 /* 42992 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16914 /* 42996 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16915 /* 43000 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16916 /* 43004 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16917 /* 43008 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16918 /* 43012 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16919 /* 43016 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16920 /* 43020 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16921 /* 43024 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16922 /* 43028 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16923 /* 43032 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16924 /* 43036 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16925 /* 43040 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16926 /* 43044 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16927 /* 43048 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16928 /* 43052 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16929 /* 43056 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16930 /* 43060 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16931 /* 43064 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16932 /* 43068 */ // MIs[3] Operand 1
16933 /* 43068 */ // No operand predicates
16934 /* 43068 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16935 /* 43072 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16936 /* 43076 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16937 /* 43080 */ // MIs[4] Operand 1
16938 /* 43080 */ // No operand predicates
16939 /* 43080 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16940 /* 43084 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16941 /* 43088 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16942 /* 43092 */ // MIs[5] Operand 1
16943 /* 43092 */ // No operand predicates
16944 /* 43092 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16945 /* 43096 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16946 /* 43100 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16947 /* 43104 */ // MIs[6] Operand 1
16948 /* 43104 */ // No operand predicates
16949 /* 43104 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16950 /* 43108 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16951 /* 43112 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16952 /* 43116 */ // MIs[7] Operand 1
16953 /* 43116 */ // No operand predicates
16954 /* 43116 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16955 /* 43120 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16956 /* 43124 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16957 /* 43128 */ // MIs[8] Operand 1
16958 /* 43128 */ // No operand predicates
16959 /* 43128 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16960 /* 43132 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16961 /* 43136 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16962 /* 43140 */ // MIs[9] Operand 1
16963 /* 43140 */ // No operand predicates
16964 /* 43140 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16965 /* 43144 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16966 /* 43148 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16967 /* 43152 */ // MIs[10] Operand 1
16968 /* 43152 */ // No operand predicates
16969 /* 43152 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16970 /* 43156 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16971 /* 43160 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16972 /* 43164 */ // MIs[11] Operand 1
16973 /* 43164 */ // No operand predicates
16974 /* 43164 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16975 /* 43168 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16976 /* 43172 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16977 /* 43176 */ // MIs[12] Operand 1
16978 /* 43176 */ // No operand predicates
16979 /* 43176 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16980 /* 43180 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16981 /* 43184 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16982 /* 43188 */ // MIs[13] Operand 1
16983 /* 43188 */ // No operand predicates
16984 /* 43188 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16985 /* 43192 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16986 /* 43196 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16987 /* 43200 */ // MIs[14] Operand 1
16988 /* 43200 */ // No operand predicates
16989 /* 43200 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16990 /* 43204 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16991 /* 43208 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16992 /* 43212 */ // MIs[15] Operand 1
16993 /* 43212 */ // No operand predicates
16994 /* 43212 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16995 /* 43216 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16996 /* 43220 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16997 /* 43224 */ // MIs[16] Operand 1
16998 /* 43224 */ // No operand predicates
16999 /* 43224 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17000 /* 43228 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17001 /* 43232 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17002 /* 43236 */ // MIs[17] Operand 1
17003 /* 43236 */ // No operand predicates
17004 /* 43236 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17005 /* 43240 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17006 /* 43244 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17007 /* 43248 */ // MIs[18] Operand 1
17008 /* 43248 */ // No operand predicates
17009 /* 43248 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17010 /* 43250 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17011 /* 43250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
17012 /* 43253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17013 /* 43255 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17014 /* 43257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17015 /* 43261 */ GIR_RootConstrainSelectedInstOperands,
17016 /* 43262 */ // GIR_Coverage, 2199,
17017 /* 43262 */ GIR_EraseRootFromParent_Done,
17018 /* 43263 */ // Label 1123: @43263
17019 /* 43263 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(43286), // Rule ID 981 //
17020 /* 43268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17021 /* 43271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17022 /* 43275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17023 /* 43279 */ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17024 /* 43279 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
17025 /* 43284 */ GIR_RootConstrainSelectedInstOperands,
17026 /* 43285 */ // GIR_Coverage, 981,
17027 /* 43285 */ GIR_Done,
17028 /* 43286 */ // Label 1124: @43286
17029 /* 43286 */ GIM_Reject,
17030 /* 43287 */ // Label 1121: @43287
17031 /* 43287 */ GIM_Reject,
17032 /* 43288 */ // Label 1099: @43288
17033 /* 43288 */ GIM_Reject,
17034 /* 43289 */ // Label 38: @43289
17035 /* 43289 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1131*/ GIMT_Encode4(45085),
17036 /* 43300 */ /*GILLT_s32*//*Label 1125*/ GIMT_Encode4(43332),
17037 /* 43304 */ /*GILLT_s64*//*Label 1126*/ GIMT_Encode4(43594), GIMT_Encode4(0),
17038 /* 43312 */ /*GILLT_v2s64*//*Label 1127*/ GIMT_Encode4(43735), GIMT_Encode4(0),
17039 /* 43320 */ /*GILLT_v4s32*//*Label 1128*/ GIMT_Encode4(43769),
17040 /* 43324 */ /*GILLT_v8s16*//*Label 1129*/ GIMT_Encode4(44037),
17041 /* 43328 */ /*GILLT_v16s8*//*Label 1130*/ GIMT_Encode4(44433),
17042 /* 43332 */ // Label 1125: @43332
17043 /* 43332 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(43593),
17044 /* 43337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17045 /* 43340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17046 /* 43343 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(43385), // Rule ID 57 //
17047 /* 43348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17048 /* 43351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17049 /* 43355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17050 /* 43359 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17051 /* 43363 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17052 /* 43367 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17053 /* 43371 */ // MIs[1] Operand 1
17054 /* 43371 */ // No operand predicates
17055 /* 43371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17056 /* 43373 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17057 /* 43373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
17058 /* 43376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17059 /* 43378 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17060 /* 43380 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17061 /* 43383 */ GIR_RootConstrainSelectedInstOperands,
17062 /* 43384 */ // GIR_Coverage, 57,
17063 /* 43384 */ GIR_EraseRootFromParent_Done,
17064 /* 43385 */ // Label 1133: @43385
17065 /* 43385 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(43427), // Rule ID 1962 //
17066 /* 43390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17067 /* 43393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17068 /* 43397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17069 /* 43401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17070 /* 43405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17071 /* 43409 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17072 /* 43413 */ // MIs[1] Operand 1
17073 /* 43413 */ // No operand predicates
17074 /* 43413 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17075 /* 43415 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17076 /* 43415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
17077 /* 43418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
17078 /* 43420 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17079 /* 43422 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17080 /* 43425 */ GIR_RootConstrainSelectedInstOperands,
17081 /* 43426 */ // GIR_Coverage, 1962,
17082 /* 43426 */ GIR_EraseRootFromParent_Done,
17083 /* 43427 */ // Label 1134: @43427
17084 /* 43427 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(43469), // Rule ID 2303 //
17085 /* 43432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17086 /* 43435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
17087 /* 43439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
17088 /* 43443 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17089 /* 43447 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17090 /* 43451 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
17091 /* 43455 */ // MIs[1] Operand 1
17092 /* 43455 */ // No operand predicates
17093 /* 43455 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17094 /* 43457 */ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
17095 /* 43457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
17096 /* 43460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17097 /* 43462 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17098 /* 43464 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17099 /* 43467 */ GIR_RootConstrainSelectedInstOperands,
17100 /* 43468 */ // GIR_Coverage, 2303,
17101 /* 43468 */ GIR_EraseRootFromParent_Done,
17102 /* 43469 */ // Label 1135: @43469
17103 /* 43469 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(43511), // Rule ID 2304 //
17104 /* 43474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17105 /* 43477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17106 /* 43481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17107 /* 43485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17108 /* 43489 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17109 /* 43493 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17110 /* 43497 */ // MIs[1] Operand 1
17111 /* 43497 */ // No operand predicates
17112 /* 43497 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17113 /* 43499 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17114 /* 43499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
17115 /* 43502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17116 /* 43504 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17117 /* 43506 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17118 /* 43509 */ GIR_RootConstrainSelectedInstOperands,
17119 /* 43510 */ // GIR_Coverage, 2304,
17120 /* 43510 */ GIR_EraseRootFromParent_Done,
17121 /* 43511 */ // Label 1136: @43511
17122 /* 43511 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(43538), // Rule ID 63 //
17123 /* 43516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17124 /* 43519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17125 /* 43523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17126 /* 43527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17127 /* 43531 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17128 /* 43531 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
17129 /* 43536 */ GIR_RootConstrainSelectedInstOperands,
17130 /* 43537 */ // GIR_Coverage, 63,
17131 /* 43537 */ GIR_Done,
17132 /* 43538 */ // Label 1137: @43538
17133 /* 43538 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(43565), // Rule ID 1966 //
17134 /* 43543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17135 /* 43546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17136 /* 43550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17137 /* 43554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17138 /* 43558 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
17139 /* 43558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
17140 /* 43563 */ GIR_RootConstrainSelectedInstOperands,
17141 /* 43564 */ // GIR_Coverage, 1966,
17142 /* 43564 */ GIR_Done,
17143 /* 43565 */ // Label 1138: @43565
17144 /* 43565 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(43592), // Rule ID 2305 //
17145 /* 43570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17146 /* 43573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17147 /* 43577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17148 /* 43581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17149 /* 43585 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
17150 /* 43585 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
17151 /* 43590 */ GIR_RootConstrainSelectedInstOperands,
17152 /* 43591 */ // GIR_Coverage, 2305,
17153 /* 43591 */ GIR_Done,
17154 /* 43592 */ // Label 1139: @43592
17155 /* 43592 */ GIM_Reject,
17156 /* 43593 */ // Label 1132: @43593
17157 /* 43593 */ GIM_Reject,
17158 /* 43594 */ // Label 1126: @43594
17159 /* 43594 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(43734),
17160 /* 43599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17161 /* 43602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17162 /* 43605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17163 /* 43609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17164 /* 43613 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(43647), // Rule ID 236 //
17165 /* 43618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17166 /* 43621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17167 /* 43625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17168 /* 43629 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17169 /* 43633 */ // MIs[1] Operand 1
17170 /* 43633 */ // No operand predicates
17171 /* 43633 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17172 /* 43635 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17173 /* 43635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
17174 /* 43638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17175 /* 43640 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17176 /* 43642 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17177 /* 43645 */ GIR_RootConstrainSelectedInstOperands,
17178 /* 43646 */ // GIR_Coverage, 236,
17179 /* 43646 */ GIR_EraseRootFromParent_Done,
17180 /* 43647 */ // Label 1141: @43647
17181 /* 43647 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(43714), // Rule ID 1679 //
17182 /* 43652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17183 /* 43655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17184 /* 43659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17185 /* 43663 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17186 /* 43667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17187 /* 43672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17188 /* 43674 */ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17189 /* 43674 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17190 /* 43677 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17191 /* 43681 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17192 /* 43686 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17193 /* 43692 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17194 /* 43697 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17195 /* 43702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
17196 /* 43705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17197 /* 43707 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17198 /* 43709 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17199 /* 43712 */ GIR_RootConstrainSelectedInstOperands,
17200 /* 43713 */ // GIR_Coverage, 1679,
17201 /* 43713 */ GIR_EraseRootFromParent_Done,
17202 /* 43714 */ // Label 1142: @43714
17203 /* 43714 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(43733), // Rule ID 244 //
17204 /* 43719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17205 /* 43722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17206 /* 43726 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17207 /* 43726 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
17208 /* 43731 */ GIR_RootConstrainSelectedInstOperands,
17209 /* 43732 */ // GIR_Coverage, 244,
17210 /* 43732 */ GIR_Done,
17211 /* 43733 */ // Label 1143: @43733
17212 /* 43733 */ GIM_Reject,
17213 /* 43734 */ // Label 1140: @43734
17214 /* 43734 */ GIM_Reject,
17215 /* 43735 */ // Label 1127: @43735
17216 /* 43735 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(43768), // Rule ID 1016 //
17217 /* 43740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17218 /* 43743 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17219 /* 43746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17220 /* 43749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17221 /* 43753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17222 /* 43757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17223 /* 43761 */ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17224 /* 43761 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
17225 /* 43766 */ GIR_RootConstrainSelectedInstOperands,
17226 /* 43767 */ // GIR_Coverage, 1016,
17227 /* 43767 */ GIR_Done,
17228 /* 43768 */ // Label 1144: @43768
17229 /* 43768 */ GIM_Reject,
17230 /* 43769 */ // Label 1128: @43769
17231 /* 43769 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(44036),
17232 /* 43774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17233 /* 43777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17234 /* 43780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17235 /* 43784 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(43898), // Rule ID 2652 //
17236 /* 43789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17237 /* 43792 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17238 /* 43796 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17239 /* 43800 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17240 /* 43804 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17241 /* 43808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17242 /* 43812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17243 /* 43816 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17244 /* 43819 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17245 /* 43823 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17246 /* 43827 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17247 /* 43831 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17248 /* 43835 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17249 /* 43839 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17250 /* 43843 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17251 /* 43847 */ // MIs[3] Operand 1
17252 /* 43847 */ // No operand predicates
17253 /* 43847 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17254 /* 43851 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17255 /* 43855 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17256 /* 43859 */ // MIs[4] Operand 1
17257 /* 43859 */ // No operand predicates
17258 /* 43859 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17259 /* 43863 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17260 /* 43867 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17261 /* 43871 */ // MIs[5] Operand 1
17262 /* 43871 */ // No operand predicates
17263 /* 43871 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17264 /* 43875 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17265 /* 43879 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17266 /* 43883 */ // MIs[6] Operand 1
17267 /* 43883 */ // No operand predicates
17268 /* 43883 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17269 /* 43885 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17270 /* 43885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17271 /* 43888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17272 /* 43890 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17273 /* 43892 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17274 /* 43896 */ GIR_RootConstrainSelectedInstOperands,
17275 /* 43897 */ // GIR_Coverage, 2652,
17276 /* 43897 */ GIR_EraseRootFromParent_Done,
17277 /* 43898 */ // Label 1146: @43898
17278 /* 43898 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(44012), // Rule ID 2209 //
17279 /* 43903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17280 /* 43906 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17281 /* 43910 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17282 /* 43914 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17283 /* 43918 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17284 /* 43922 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17285 /* 43926 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17286 /* 43930 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17287 /* 43933 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17288 /* 43937 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17289 /* 43941 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17290 /* 43945 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17291 /* 43949 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17292 /* 43953 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17293 /* 43957 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17294 /* 43961 */ // MIs[3] Operand 1
17295 /* 43961 */ // No operand predicates
17296 /* 43961 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17297 /* 43965 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17298 /* 43969 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17299 /* 43973 */ // MIs[4] Operand 1
17300 /* 43973 */ // No operand predicates
17301 /* 43973 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17302 /* 43977 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17303 /* 43981 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17304 /* 43985 */ // MIs[5] Operand 1
17305 /* 43985 */ // No operand predicates
17306 /* 43985 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17307 /* 43989 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17308 /* 43993 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17309 /* 43997 */ // MIs[6] Operand 1
17310 /* 43997 */ // No operand predicates
17311 /* 43997 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17312 /* 43999 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17313 /* 43999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17314 /* 44002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17315 /* 44004 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17316 /* 44006 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17317 /* 44010 */ GIR_RootConstrainSelectedInstOperands,
17318 /* 44011 */ // GIR_Coverage, 2209,
17319 /* 44011 */ GIR_EraseRootFromParent_Done,
17320 /* 44012 */ // Label 1147: @44012
17321 /* 44012 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(44035), // Rule ID 1015 //
17322 /* 44017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17323 /* 44020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17324 /* 44024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17325 /* 44028 */ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17326 /* 44028 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
17327 /* 44033 */ GIR_RootConstrainSelectedInstOperands,
17328 /* 44034 */ // GIR_Coverage, 1015,
17329 /* 44034 */ GIR_Done,
17330 /* 44035 */ // Label 1148: @44035
17331 /* 44035 */ GIM_Reject,
17332 /* 44036 */ // Label 1145: @44036
17333 /* 44036 */ GIM_Reject,
17334 /* 44037 */ // Label 1129: @44037
17335 /* 44037 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(44432),
17336 /* 44042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17337 /* 44045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17338 /* 44048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17339 /* 44052 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(44230), // Rule ID 2651 //
17340 /* 44057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17341 /* 44060 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17342 /* 44064 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17343 /* 44068 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17344 /* 44072 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17345 /* 44076 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17346 /* 44080 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17347 /* 44084 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17348 /* 44087 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17349 /* 44091 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17350 /* 44095 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17351 /* 44099 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17352 /* 44103 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17353 /* 44107 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17354 /* 44111 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17355 /* 44115 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17356 /* 44119 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17357 /* 44123 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17358 /* 44127 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17359 /* 44131 */ // MIs[3] Operand 1
17360 /* 44131 */ // No operand predicates
17361 /* 44131 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17362 /* 44135 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17363 /* 44139 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17364 /* 44143 */ // MIs[4] Operand 1
17365 /* 44143 */ // No operand predicates
17366 /* 44143 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17367 /* 44147 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17368 /* 44151 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17369 /* 44155 */ // MIs[5] Operand 1
17370 /* 44155 */ // No operand predicates
17371 /* 44155 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17372 /* 44159 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17373 /* 44163 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17374 /* 44167 */ // MIs[6] Operand 1
17375 /* 44167 */ // No operand predicates
17376 /* 44167 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17377 /* 44171 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17378 /* 44175 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17379 /* 44179 */ // MIs[7] Operand 1
17380 /* 44179 */ // No operand predicates
17381 /* 44179 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17382 /* 44183 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17383 /* 44187 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17384 /* 44191 */ // MIs[8] Operand 1
17385 /* 44191 */ // No operand predicates
17386 /* 44191 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17387 /* 44195 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17388 /* 44199 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17389 /* 44203 */ // MIs[9] Operand 1
17390 /* 44203 */ // No operand predicates
17391 /* 44203 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17392 /* 44207 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17393 /* 44211 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17394 /* 44215 */ // MIs[10] Operand 1
17395 /* 44215 */ // No operand predicates
17396 /* 44215 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17397 /* 44217 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17398 /* 44217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17399 /* 44220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17400 /* 44222 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17401 /* 44224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17402 /* 44228 */ GIR_RootConstrainSelectedInstOperands,
17403 /* 44229 */ // GIR_Coverage, 2651,
17404 /* 44229 */ GIR_EraseRootFromParent_Done,
17405 /* 44230 */ // Label 1150: @44230
17406 /* 44230 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(44408), // Rule ID 2208 //
17407 /* 44235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17408 /* 44238 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17409 /* 44242 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17410 /* 44246 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17411 /* 44250 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17412 /* 44254 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17413 /* 44258 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17414 /* 44262 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17415 /* 44265 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17416 /* 44269 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17417 /* 44273 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17418 /* 44277 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17419 /* 44281 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17420 /* 44285 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17421 /* 44289 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17422 /* 44293 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17423 /* 44297 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17424 /* 44301 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17425 /* 44305 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17426 /* 44309 */ // MIs[3] Operand 1
17427 /* 44309 */ // No operand predicates
17428 /* 44309 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17429 /* 44313 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17430 /* 44317 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17431 /* 44321 */ // MIs[4] Operand 1
17432 /* 44321 */ // No operand predicates
17433 /* 44321 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17434 /* 44325 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17435 /* 44329 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17436 /* 44333 */ // MIs[5] Operand 1
17437 /* 44333 */ // No operand predicates
17438 /* 44333 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17439 /* 44337 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17440 /* 44341 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17441 /* 44345 */ // MIs[6] Operand 1
17442 /* 44345 */ // No operand predicates
17443 /* 44345 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17444 /* 44349 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17445 /* 44353 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17446 /* 44357 */ // MIs[7] Operand 1
17447 /* 44357 */ // No operand predicates
17448 /* 44357 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17449 /* 44361 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17450 /* 44365 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17451 /* 44369 */ // MIs[8] Operand 1
17452 /* 44369 */ // No operand predicates
17453 /* 44369 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17454 /* 44373 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17455 /* 44377 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17456 /* 44381 */ // MIs[9] Operand 1
17457 /* 44381 */ // No operand predicates
17458 /* 44381 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17459 /* 44385 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17460 /* 44389 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17461 /* 44393 */ // MIs[10] Operand 1
17462 /* 44393 */ // No operand predicates
17463 /* 44393 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17464 /* 44395 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17465 /* 44395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17466 /* 44398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17467 /* 44400 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17468 /* 44402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17469 /* 44406 */ GIR_RootConstrainSelectedInstOperands,
17470 /* 44407 */ // GIR_Coverage, 2208,
17471 /* 44407 */ GIR_EraseRootFromParent_Done,
17472 /* 44408 */ // Label 1151: @44408
17473 /* 44408 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(44431), // Rule ID 1014 //
17474 /* 44413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17475 /* 44416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17476 /* 44420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17477 /* 44424 */ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
17478 /* 44424 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
17479 /* 44429 */ GIR_RootConstrainSelectedInstOperands,
17480 /* 44430 */ // GIR_Coverage, 1014,
17481 /* 44430 */ GIR_Done,
17482 /* 44431 */ // Label 1152: @44431
17483 /* 44431 */ GIM_Reject,
17484 /* 44432 */ // Label 1149: @44432
17485 /* 44432 */ GIM_Reject,
17486 /* 44433 */ // Label 1130: @44433
17487 /* 44433 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(45084),
17488 /* 44438 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
17489 /* 44441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17490 /* 44444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17491 /* 44448 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(44754), // Rule ID 2650 //
17492 /* 44453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17493 /* 44456 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17494 /* 44460 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17495 /* 44464 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17496 /* 44468 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17497 /* 44472 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17498 /* 44476 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17499 /* 44480 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17500 /* 44483 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17501 /* 44487 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17502 /* 44491 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17503 /* 44495 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17504 /* 44499 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17505 /* 44503 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17506 /* 44507 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17507 /* 44511 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17508 /* 44515 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17509 /* 44519 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17510 /* 44523 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17511 /* 44527 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17512 /* 44531 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17513 /* 44535 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17514 /* 44539 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17515 /* 44543 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17516 /* 44547 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17517 /* 44551 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17518 /* 44555 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17519 /* 44559 */ // MIs[3] Operand 1
17520 /* 44559 */ // No operand predicates
17521 /* 44559 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17522 /* 44563 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17523 /* 44567 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17524 /* 44571 */ // MIs[4] Operand 1
17525 /* 44571 */ // No operand predicates
17526 /* 44571 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17527 /* 44575 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17528 /* 44579 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17529 /* 44583 */ // MIs[5] Operand 1
17530 /* 44583 */ // No operand predicates
17531 /* 44583 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17532 /* 44587 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17533 /* 44591 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17534 /* 44595 */ // MIs[6] Operand 1
17535 /* 44595 */ // No operand predicates
17536 /* 44595 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17537 /* 44599 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17538 /* 44603 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17539 /* 44607 */ // MIs[7] Operand 1
17540 /* 44607 */ // No operand predicates
17541 /* 44607 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17542 /* 44611 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17543 /* 44615 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17544 /* 44619 */ // MIs[8] Operand 1
17545 /* 44619 */ // No operand predicates
17546 /* 44619 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17547 /* 44623 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17548 /* 44627 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17549 /* 44631 */ // MIs[9] Operand 1
17550 /* 44631 */ // No operand predicates
17551 /* 44631 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17552 /* 44635 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17553 /* 44639 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17554 /* 44643 */ // MIs[10] Operand 1
17555 /* 44643 */ // No operand predicates
17556 /* 44643 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17557 /* 44647 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17558 /* 44651 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17559 /* 44655 */ // MIs[11] Operand 1
17560 /* 44655 */ // No operand predicates
17561 /* 44655 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17562 /* 44659 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17563 /* 44663 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17564 /* 44667 */ // MIs[12] Operand 1
17565 /* 44667 */ // No operand predicates
17566 /* 44667 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17567 /* 44671 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17568 /* 44675 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17569 /* 44679 */ // MIs[13] Operand 1
17570 /* 44679 */ // No operand predicates
17571 /* 44679 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17572 /* 44683 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17573 /* 44687 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17574 /* 44691 */ // MIs[14] Operand 1
17575 /* 44691 */ // No operand predicates
17576 /* 44691 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17577 /* 44695 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17578 /* 44699 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17579 /* 44703 */ // MIs[15] Operand 1
17580 /* 44703 */ // No operand predicates
17581 /* 44703 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17582 /* 44707 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17583 /* 44711 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17584 /* 44715 */ // MIs[16] Operand 1
17585 /* 44715 */ // No operand predicates
17586 /* 44715 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17587 /* 44719 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17588 /* 44723 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17589 /* 44727 */ // MIs[17] Operand 1
17590 /* 44727 */ // No operand predicates
17591 /* 44727 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17592 /* 44731 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17593 /* 44735 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17594 /* 44739 */ // MIs[18] Operand 1
17595 /* 44739 */ // No operand predicates
17596 /* 44739 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17597 /* 44741 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17598 /* 44741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17599 /* 44744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17600 /* 44746 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17601 /* 44748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17602 /* 44752 */ GIR_RootConstrainSelectedInstOperands,
17603 /* 44753 */ // GIR_Coverage, 2650,
17604 /* 44753 */ GIR_EraseRootFromParent_Done,
17605 /* 44754 */ // Label 1154: @44754
17606 /* 44754 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(45060), // Rule ID 2207 //
17607 /* 44759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17608 /* 44762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17609 /* 44766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17610 /* 44770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
17611 /* 44774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
17612 /* 44778 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17613 /* 44782 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17614 /* 44786 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
17615 /* 44789 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17616 /* 44793 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17617 /* 44797 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17618 /* 44801 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17619 /* 44805 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17620 /* 44809 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17621 /* 44813 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17622 /* 44817 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17623 /* 44821 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
17624 /* 44825 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
17625 /* 44829 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
17626 /* 44833 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
17627 /* 44837 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
17628 /* 44841 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
17629 /* 44845 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
17630 /* 44849 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
17631 /* 44853 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17632 /* 44857 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17633 /* 44861 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17634 /* 44865 */ // MIs[3] Operand 1
17635 /* 44865 */ // No operand predicates
17636 /* 44865 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17637 /* 44869 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17638 /* 44873 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17639 /* 44877 */ // MIs[4] Operand 1
17640 /* 44877 */ // No operand predicates
17641 /* 44877 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17642 /* 44881 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17643 /* 44885 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17644 /* 44889 */ // MIs[5] Operand 1
17645 /* 44889 */ // No operand predicates
17646 /* 44889 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17647 /* 44893 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17648 /* 44897 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17649 /* 44901 */ // MIs[6] Operand 1
17650 /* 44901 */ // No operand predicates
17651 /* 44901 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17652 /* 44905 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17653 /* 44909 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17654 /* 44913 */ // MIs[7] Operand 1
17655 /* 44913 */ // No operand predicates
17656 /* 44913 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17657 /* 44917 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17658 /* 44921 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17659 /* 44925 */ // MIs[8] Operand 1
17660 /* 44925 */ // No operand predicates
17661 /* 44925 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17662 /* 44929 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17663 /* 44933 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17664 /* 44937 */ // MIs[9] Operand 1
17665 /* 44937 */ // No operand predicates
17666 /* 44937 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17667 /* 44941 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17668 /* 44945 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17669 /* 44949 */ // MIs[10] Operand 1
17670 /* 44949 */ // No operand predicates
17671 /* 44949 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17672 /* 44953 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17673 /* 44957 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17674 /* 44961 */ // MIs[11] Operand 1
17675 /* 44961 */ // No operand predicates
17676 /* 44961 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17677 /* 44965 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17678 /* 44969 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17679 /* 44973 */ // MIs[12] Operand 1
17680 /* 44973 */ // No operand predicates
17681 /* 44973 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17682 /* 44977 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17683 /* 44981 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17684 /* 44985 */ // MIs[13] Operand 1
17685 /* 44985 */ // No operand predicates
17686 /* 44985 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17687 /* 44989 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17688 /* 44993 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17689 /* 44997 */ // MIs[14] Operand 1
17690 /* 44997 */ // No operand predicates
17691 /* 44997 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17692 /* 45001 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17693 /* 45005 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17694 /* 45009 */ // MIs[15] Operand 1
17695 /* 45009 */ // No operand predicates
17696 /* 45009 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17697 /* 45013 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17698 /* 45017 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17699 /* 45021 */ // MIs[16] Operand 1
17700 /* 45021 */ // No operand predicates
17701 /* 45021 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17702 /* 45025 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17703 /* 45029 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17704 /* 45033 */ // MIs[17] Operand 1
17705 /* 45033 */ // No operand predicates
17706 /* 45033 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17707 /* 45037 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17708 /* 45041 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17709 /* 45045 */ // MIs[18] Operand 1
17710 /* 45045 */ // No operand predicates
17711 /* 45045 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17712 /* 45047 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17713 /* 45047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17714 /* 45050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17715 /* 45052 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17716 /* 45054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17717 /* 45058 */ GIR_RootConstrainSelectedInstOperands,
17718 /* 45059 */ // GIR_Coverage, 2207,
17719 /* 45059 */ GIR_EraseRootFromParent_Done,
17720 /* 45060 */ // Label 1155: @45060
17721 /* 45060 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(45083), // Rule ID 1013 //
17722 /* 45065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17723 /* 45068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17724 /* 45072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17725 /* 45076 */ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17726 /* 45076 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
17727 /* 45081 */ GIR_RootConstrainSelectedInstOperands,
17728 /* 45082 */ // GIR_Coverage, 1013,
17729 /* 45082 */ GIR_Done,
17730 /* 45083 */ // Label 1156: @45083
17731 /* 45083 */ GIM_Reject,
17732 /* 45084 */ // Label 1153: @45084
17733 /* 45084 */ GIM_Reject,
17734 /* 45085 */ // Label 1131: @45085
17735 /* 45085 */ GIM_Reject,
17736 /* 45086 */ // Label 39: @45086
17737 /* 45086 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1163*/ GIMT_Encode4(46840),
17738 /* 45097 */ /*GILLT_s32*//*Label 1157*/ GIMT_Encode4(45129),
17739 /* 45101 */ /*GILLT_s64*//*Label 1158*/ GIMT_Encode4(45349), GIMT_Encode4(0),
17740 /* 45109 */ /*GILLT_v2s64*//*Label 1159*/ GIMT_Encode4(45490), GIMT_Encode4(0),
17741 /* 45117 */ /*GILLT_v4s32*//*Label 1160*/ GIMT_Encode4(45524),
17742 /* 45121 */ /*GILLT_v8s16*//*Label 1161*/ GIMT_Encode4(45792),
17743 /* 45125 */ /*GILLT_v16s8*//*Label 1162*/ GIMT_Encode4(46188),
17744 /* 45129 */ // Label 1157: @45129
17745 /* 45129 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(45348),
17746 /* 45134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17747 /* 45137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17748 /* 45140 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(45182), // Rule ID 59 //
17749 /* 45145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17750 /* 45148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17751 /* 45152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17752 /* 45156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17753 /* 45160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17754 /* 45164 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17755 /* 45168 */ // MIs[1] Operand 1
17756 /* 45168 */ // No operand predicates
17757 /* 45168 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17758 /* 45170 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17759 /* 45170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
17760 /* 45173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17761 /* 45175 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17762 /* 45177 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17763 /* 45180 */ GIR_RootConstrainSelectedInstOperands,
17764 /* 45181 */ // GIR_Coverage, 59,
17765 /* 45181 */ GIR_EraseRootFromParent_Done,
17766 /* 45182 */ // Label 1165: @45182
17767 /* 45182 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(45224), // Rule ID 1963 //
17768 /* 45187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17769 /* 45190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17770 /* 45194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17771 /* 45198 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17772 /* 45202 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17773 /* 45206 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17774 /* 45210 */ // MIs[1] Operand 1
17775 /* 45210 */ // No operand predicates
17776 /* 45210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17777 /* 45212 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17778 /* 45212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
17779 /* 45215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
17780 /* 45217 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
17781 /* 45219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17782 /* 45222 */ GIR_RootConstrainSelectedInstOperands,
17783 /* 45223 */ // GIR_Coverage, 1963,
17784 /* 45223 */ GIR_EraseRootFromParent_Done,
17785 /* 45224 */ // Label 1166: @45224
17786 /* 45224 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(45266), // Rule ID 2306 //
17787 /* 45229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17788 /* 45232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17789 /* 45236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17790 /* 45240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17791 /* 45244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17792 /* 45248 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17793 /* 45252 */ // MIs[1] Operand 1
17794 /* 45252 */ // No operand predicates
17795 /* 45252 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17796 /* 45254 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
17797 /* 45254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
17798 /* 45257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17799 /* 45259 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
17800 /* 45261 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17801 /* 45264 */ GIR_RootConstrainSelectedInstOperands,
17802 /* 45265 */ // GIR_Coverage, 2306,
17803 /* 45265 */ GIR_EraseRootFromParent_Done,
17804 /* 45266 */ // Label 1167: @45266
17805 /* 45266 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(45293), // Rule ID 65 //
17806 /* 45271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17807 /* 45274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17808 /* 45278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17809 /* 45282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17810 /* 45286 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17811 /* 45286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
17812 /* 45291 */ GIR_RootConstrainSelectedInstOperands,
17813 /* 45292 */ // GIR_Coverage, 65,
17814 /* 45292 */ GIR_Done,
17815 /* 45293 */ // Label 1168: @45293
17816 /* 45293 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(45320), // Rule ID 1965 //
17817 /* 45298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17818 /* 45301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17819 /* 45305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17820 /* 45309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17821 /* 45313 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
17822 /* 45313 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
17823 /* 45318 */ GIR_RootConstrainSelectedInstOperands,
17824 /* 45319 */ // GIR_Coverage, 1965,
17825 /* 45319 */ GIR_Done,
17826 /* 45320 */ // Label 1169: @45320
17827 /* 45320 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(45347), // Rule ID 2307 //
17828 /* 45325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17829 /* 45328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17830 /* 45332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17831 /* 45336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17832 /* 45340 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
17833 /* 45340 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
17834 /* 45345 */ GIR_RootConstrainSelectedInstOperands,
17835 /* 45346 */ // GIR_Coverage, 2307,
17836 /* 45346 */ GIR_Done,
17837 /* 45347 */ // Label 1170: @45347
17838 /* 45347 */ GIM_Reject,
17839 /* 45348 */ // Label 1164: @45348
17840 /* 45348 */ GIM_Reject,
17841 /* 45349 */ // Label 1158: @45349
17842 /* 45349 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(45489),
17843 /* 45354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17844 /* 45357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17845 /* 45360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17846 /* 45364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17847 /* 45368 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(45402), // Rule ID 238 //
17848 /* 45373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17849 /* 45376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17850 /* 45380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17851 /* 45384 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17852 /* 45388 */ // MIs[1] Operand 1
17853 /* 45388 */ // No operand predicates
17854 /* 45388 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17855 /* 45390 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17856 /* 45390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
17857 /* 45393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17858 /* 45395 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17859 /* 45397 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17860 /* 45400 */ GIR_RootConstrainSelectedInstOperands,
17861 /* 45401 */ // GIR_Coverage, 238,
17862 /* 45401 */ GIR_EraseRootFromParent_Done,
17863 /* 45402 */ // Label 1172: @45402
17864 /* 45402 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(45469), // Rule ID 1680 //
17865 /* 45407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
17866 /* 45410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17867 /* 45414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17868 /* 45418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17869 /* 45422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17870 /* 45427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17871 /* 45429 */ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17872 /* 45429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17873 /* 45432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17874 /* 45436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17875 /* 45441 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17876 /* 45447 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17877 /* 45452 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17878 /* 45457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17879 /* 45460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17880 /* 45462 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17881 /* 45464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17882 /* 45467 */ GIR_RootConstrainSelectedInstOperands,
17883 /* 45468 */ // GIR_Coverage, 1680,
17884 /* 45468 */ GIR_EraseRootFromParent_Done,
17885 /* 45469 */ // Label 1173: @45469
17886 /* 45469 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(45488), // Rule ID 242 //
17887 /* 45474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
17888 /* 45477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17889 /* 45481 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17890 /* 45481 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
17891 /* 45486 */ GIR_RootConstrainSelectedInstOperands,
17892 /* 45487 */ // GIR_Coverage, 242,
17893 /* 45487 */ GIR_Done,
17894 /* 45488 */ // Label 1174: @45488
17895 /* 45488 */ GIM_Reject,
17896 /* 45489 */ // Label 1171: @45489
17897 /* 45489 */ GIM_Reject,
17898 /* 45490 */ // Label 1159: @45490
17899 /* 45490 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(45523), // Rule ID 1000 //
17900 /* 45495 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
17901 /* 45498 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17902 /* 45501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17903 /* 45504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17904 /* 45508 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17905 /* 45512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17906 /* 45516 */ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17907 /* 45516 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
17908 /* 45521 */ GIR_RootConstrainSelectedInstOperands,
17909 /* 45522 */ // GIR_Coverage, 1000,
17910 /* 45522 */ GIR_Done,
17911 /* 45523 */ // Label 1175: @45523
17912 /* 45523 */ GIM_Reject,
17913 /* 45524 */ // Label 1160: @45524
17914 /* 45524 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(45791),
17915 /* 45529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17916 /* 45532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17917 /* 45535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17918 /* 45539 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(45653), // Rule ID 2656 //
17919 /* 45544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17920 /* 45547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17921 /* 45551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17922 /* 45555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17923 /* 45559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17924 /* 45563 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17925 /* 45567 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17926 /* 45571 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17927 /* 45574 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17928 /* 45578 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17929 /* 45582 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17930 /* 45586 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17931 /* 45590 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17932 /* 45594 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17933 /* 45598 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17934 /* 45602 */ // MIs[3] Operand 1
17935 /* 45602 */ // No operand predicates
17936 /* 45602 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17937 /* 45606 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17938 /* 45610 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17939 /* 45614 */ // MIs[4] Operand 1
17940 /* 45614 */ // No operand predicates
17941 /* 45614 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17942 /* 45618 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17943 /* 45622 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17944 /* 45626 */ // MIs[5] Operand 1
17945 /* 45626 */ // No operand predicates
17946 /* 45626 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17947 /* 45630 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17948 /* 45634 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17949 /* 45638 */ // MIs[6] Operand 1
17950 /* 45638 */ // No operand predicates
17951 /* 45638 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17952 /* 45640 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17953 /* 45640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17954 /* 45643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17955 /* 45645 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17956 /* 45647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17957 /* 45651 */ GIR_RootConstrainSelectedInstOperands,
17958 /* 45652 */ // GIR_Coverage, 2656,
17959 /* 45652 */ GIR_EraseRootFromParent_Done,
17960 /* 45653 */ // Label 1177: @45653
17961 /* 45653 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(45767), // Rule ID 2213 //
17962 /* 45658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
17963 /* 45661 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17964 /* 45665 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17965 /* 45669 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17966 /* 45673 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17967 /* 45677 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17968 /* 45681 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17969 /* 45685 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17970 /* 45688 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17971 /* 45692 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17972 /* 45696 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17973 /* 45700 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17974 /* 45704 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17975 /* 45708 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17976 /* 45712 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17977 /* 45716 */ // MIs[3] Operand 1
17978 /* 45716 */ // No operand predicates
17979 /* 45716 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17980 /* 45720 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17981 /* 45724 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17982 /* 45728 */ // MIs[4] Operand 1
17983 /* 45728 */ // No operand predicates
17984 /* 45728 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17985 /* 45732 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17986 /* 45736 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17987 /* 45740 */ // MIs[5] Operand 1
17988 /* 45740 */ // No operand predicates
17989 /* 45740 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17990 /* 45744 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17991 /* 45748 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17992 /* 45752 */ // MIs[6] Operand 1
17993 /* 45752 */ // No operand predicates
17994 /* 45752 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17995 /* 45754 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17996 /* 45754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17997 /* 45757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17998 /* 45759 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17999 /* 45761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18000 /* 45765 */ GIR_RootConstrainSelectedInstOperands,
18001 /* 45766 */ // GIR_Coverage, 2213,
18002 /* 45766 */ GIR_EraseRootFromParent_Done,
18003 /* 45767 */ // Label 1178: @45767
18004 /* 45767 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(45790), // Rule ID 999 //
18005 /* 45772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18006 /* 45775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
18007 /* 45779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
18008 /* 45783 */ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
18009 /* 45783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
18010 /* 45788 */ GIR_RootConstrainSelectedInstOperands,
18011 /* 45789 */ // GIR_Coverage, 999,
18012 /* 45789 */ GIR_Done,
18013 /* 45790 */ // Label 1179: @45790
18014 /* 45790 */ GIM_Reject,
18015 /* 45791 */ // Label 1176: @45791
18016 /* 45791 */ GIM_Reject,
18017 /* 45792 */ // Label 1161: @45792
18018 /* 45792 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(46187),
18019 /* 45797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
18020 /* 45800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18021 /* 45803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18022 /* 45807 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(45985), // Rule ID 2655 //
18023 /* 45812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18024 /* 45815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18025 /* 45819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18026 /* 45823 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
18027 /* 45827 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
18028 /* 45831 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18029 /* 45835 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18030 /* 45839 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
18031 /* 45842 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18032 /* 45846 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18033 /* 45850 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18034 /* 45854 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18035 /* 45858 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18036 /* 45862 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18037 /* 45866 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18038 /* 45870 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18039 /* 45874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18040 /* 45878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18041 /* 45882 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18042 /* 45886 */ // MIs[3] Operand 1
18043 /* 45886 */ // No operand predicates
18044 /* 45886 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18045 /* 45890 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18046 /* 45894 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18047 /* 45898 */ // MIs[4] Operand 1
18048 /* 45898 */ // No operand predicates
18049 /* 45898 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18050 /* 45902 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18051 /* 45906 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18052 /* 45910 */ // MIs[5] Operand 1
18053 /* 45910 */ // No operand predicates
18054 /* 45910 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18055 /* 45914 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18056 /* 45918 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18057 /* 45922 */ // MIs[6] Operand 1
18058 /* 45922 */ // No operand predicates
18059 /* 45922 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18060 /* 45926 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18061 /* 45930 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18062 /* 45934 */ // MIs[7] Operand 1
18063 /* 45934 */ // No operand predicates
18064 /* 45934 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18065 /* 45938 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18066 /* 45942 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18067 /* 45946 */ // MIs[8] Operand 1
18068 /* 45946 */ // No operand predicates
18069 /* 45946 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18070 /* 45950 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18071 /* 45954 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18072 /* 45958 */ // MIs[9] Operand 1
18073 /* 45958 */ // No operand predicates
18074 /* 45958 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18075 /* 45962 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18076 /* 45966 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18077 /* 45970 */ // MIs[10] Operand 1
18078 /* 45970 */ // No operand predicates
18079 /* 45970 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
18080 /* 45972 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
18081 /* 45972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18082 /* 45975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18083 /* 45977 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18084 /* 45979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
18085 /* 45983 */ GIR_RootConstrainSelectedInstOperands,
18086 /* 45984 */ // GIR_Coverage, 2655,
18087 /* 45984 */ GIR_EraseRootFromParent_Done,
18088 /* 45985 */ // Label 1181: @45985
18089 /* 45985 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(46163), // Rule ID 2212 //
18090 /* 45990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18091 /* 45993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18092 /* 45997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18093 /* 46001 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
18094 /* 46005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
18095 /* 46009 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18096 /* 46013 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18097 /* 46017 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
18098 /* 46020 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18099 /* 46024 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18100 /* 46028 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18101 /* 46032 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18102 /* 46036 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18103 /* 46040 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18104 /* 46044 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18105 /* 46048 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18106 /* 46052 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18107 /* 46056 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18108 /* 46060 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18109 /* 46064 */ // MIs[3] Operand 1
18110 /* 46064 */ // No operand predicates
18111 /* 46064 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18112 /* 46068 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18113 /* 46072 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18114 /* 46076 */ // MIs[4] Operand 1
18115 /* 46076 */ // No operand predicates
18116 /* 46076 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18117 /* 46080 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18118 /* 46084 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18119 /* 46088 */ // MIs[5] Operand 1
18120 /* 46088 */ // No operand predicates
18121 /* 46088 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18122 /* 46092 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18123 /* 46096 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18124 /* 46100 */ // MIs[6] Operand 1
18125 /* 46100 */ // No operand predicates
18126 /* 46100 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18127 /* 46104 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18128 /* 46108 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18129 /* 46112 */ // MIs[7] Operand 1
18130 /* 46112 */ // No operand predicates
18131 /* 46112 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18132 /* 46116 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18133 /* 46120 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18134 /* 46124 */ // MIs[8] Operand 1
18135 /* 46124 */ // No operand predicates
18136 /* 46124 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18137 /* 46128 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18138 /* 46132 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18139 /* 46136 */ // MIs[9] Operand 1
18140 /* 46136 */ // No operand predicates
18141 /* 46136 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18142 /* 46140 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18143 /* 46144 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
18144 /* 46148 */ // MIs[10] Operand 1
18145 /* 46148 */ // No operand predicates
18146 /* 46148 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
18147 /* 46150 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
18148 /* 46150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18149 /* 46153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18150 /* 46155 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18151 /* 46157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18152 /* 46161 */ GIR_RootConstrainSelectedInstOperands,
18153 /* 46162 */ // GIR_Coverage, 2212,
18154 /* 46162 */ GIR_EraseRootFromParent_Done,
18155 /* 46163 */ // Label 1182: @46163
18156 /* 46163 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(46186), // Rule ID 998 //
18157 /* 46168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18158 /* 46171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18159 /* 46175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
18160 /* 46179 */ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
18161 /* 46179 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
18162 /* 46184 */ GIR_RootConstrainSelectedInstOperands,
18163 /* 46185 */ // GIR_Coverage, 998,
18164 /* 46185 */ GIR_Done,
18165 /* 46186 */ // Label 1183: @46186
18166 /* 46186 */ GIM_Reject,
18167 /* 46187 */ // Label 1180: @46187
18168 /* 46187 */ GIM_Reject,
18169 /* 46188 */ // Label 1162: @46188
18170 /* 46188 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(46839),
18171 /* 46193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
18172 /* 46196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
18173 /* 46199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
18174 /* 46203 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(46509), // Rule ID 2654 //
18175 /* 46208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18176 /* 46211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18177 /* 46215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18178 /* 46219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
18179 /* 46223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
18180 /* 46227 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
18181 /* 46231 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18182 /* 46235 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
18183 /* 46238 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18184 /* 46242 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18185 /* 46246 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18186 /* 46250 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18187 /* 46254 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18188 /* 46258 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18189 /* 46262 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18190 /* 46266 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18191 /* 46270 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
18192 /* 46274 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
18193 /* 46278 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
18194 /* 46282 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
18195 /* 46286 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
18196 /* 46290 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
18197 /* 46294 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
18198 /* 46298 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
18199 /* 46302 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18200 /* 46306 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18201 /* 46310 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18202 /* 46314 */ // MIs[3] Operand 1
18203 /* 46314 */ // No operand predicates
18204 /* 46314 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18205 /* 46318 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18206 /* 46322 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18207 /* 46326 */ // MIs[4] Operand 1
18208 /* 46326 */ // No operand predicates
18209 /* 46326 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18210 /* 46330 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18211 /* 46334 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18212 /* 46338 */ // MIs[5] Operand 1
18213 /* 46338 */ // No operand predicates
18214 /* 46338 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18215 /* 46342 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18216 /* 46346 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18217 /* 46350 */ // MIs[6] Operand 1
18218 /* 46350 */ // No operand predicates
18219 /* 46350 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18220 /* 46354 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18221 /* 46358 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18222 /* 46362 */ // MIs[7] Operand 1
18223 /* 46362 */ // No operand predicates
18224 /* 46362 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18225 /* 46366 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18226 /* 46370 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18227 /* 46374 */ // MIs[8] Operand 1
18228 /* 46374 */ // No operand predicates
18229 /* 46374 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18230 /* 46378 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18231 /* 46382 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18232 /* 46386 */ // MIs[9] Operand 1
18233 /* 46386 */ // No operand predicates
18234 /* 46386 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18235 /* 46390 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18236 /* 46394 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18237 /* 46398 */ // MIs[10] Operand 1
18238 /* 46398 */ // No operand predicates
18239 /* 46398 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
18240 /* 46402 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18241 /* 46406 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18242 /* 46410 */ // MIs[11] Operand 1
18243 /* 46410 */ // No operand predicates
18244 /* 46410 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
18245 /* 46414 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18246 /* 46418 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18247 /* 46422 */ // MIs[12] Operand 1
18248 /* 46422 */ // No operand predicates
18249 /* 46422 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
18250 /* 46426 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18251 /* 46430 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18252 /* 46434 */ // MIs[13] Operand 1
18253 /* 46434 */ // No operand predicates
18254 /* 46434 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
18255 /* 46438 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18256 /* 46442 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18257 /* 46446 */ // MIs[14] Operand 1
18258 /* 46446 */ // No operand predicates
18259 /* 46446 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
18260 /* 46450 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18261 /* 46454 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18262 /* 46458 */ // MIs[15] Operand 1
18263 /* 46458 */ // No operand predicates
18264 /* 46458 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
18265 /* 46462 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18266 /* 46466 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18267 /* 46470 */ // MIs[16] Operand 1
18268 /* 46470 */ // No operand predicates
18269 /* 46470 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
18270 /* 46474 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18271 /* 46478 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18272 /* 46482 */ // MIs[17] Operand 1
18273 /* 46482 */ // No operand predicates
18274 /* 46482 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
18275 /* 46486 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18276 /* 46490 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18277 /* 46494 */ // MIs[18] Operand 1
18278 /* 46494 */ // No operand predicates
18279 /* 46494 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
18280 /* 46496 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
18281 /* 46496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18282 /* 46499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18283 /* 46501 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18284 /* 46503 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
18285 /* 46507 */ GIR_RootConstrainSelectedInstOperands,
18286 /* 46508 */ // GIR_Coverage, 2654,
18287 /* 46508 */ GIR_EraseRootFromParent_Done,
18288 /* 46509 */ // Label 1185: @46509
18289 /* 46509 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(46815), // Rule ID 2211 //
18290 /* 46514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
18291 /* 46517 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18292 /* 46521 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
18293 /* 46525 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
18294 /* 46529 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
18295 /* 46533 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
18296 /* 46537 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
18297 /* 46541 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
18298 /* 46544 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
18299 /* 46548 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
18300 /* 46552 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
18301 /* 46556 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
18302 /* 46560 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
18303 /* 46564 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
18304 /* 46568 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
18305 /* 46572 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
18306 /* 46576 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
18307 /* 46580 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
18308 /* 46584 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
18309 /* 46588 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
18310 /* 46592 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
18311 /* 46596 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
18312 /* 46600 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
18313 /* 46604 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
18314 /* 46608 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
18315 /* 46612 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18316 /* 46616 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18317 /* 46620 */ // MIs[3] Operand 1
18318 /* 46620 */ // No operand predicates
18319 /* 46620 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
18320 /* 46624 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18321 /* 46628 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18322 /* 46632 */ // MIs[4] Operand 1
18323 /* 46632 */ // No operand predicates
18324 /* 46632 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
18325 /* 46636 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18326 /* 46640 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18327 /* 46644 */ // MIs[5] Operand 1
18328 /* 46644 */ // No operand predicates
18329 /* 46644 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
18330 /* 46648 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18331 /* 46652 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18332 /* 46656 */ // MIs[6] Operand 1
18333 /* 46656 */ // No operand predicates
18334 /* 46656 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
18335 /* 46660 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18336 /* 46664 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18337 /* 46668 */ // MIs[7] Operand 1
18338 /* 46668 */ // No operand predicates
18339 /* 46668 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
18340 /* 46672 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18341 /* 46676 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18342 /* 46680 */ // MIs[8] Operand 1
18343 /* 46680 */ // No operand predicates
18344 /* 46680 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
18345 /* 46684 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18346 /* 46688 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18347 /* 46692 */ // MIs[9] Operand 1
18348 /* 46692 */ // No operand predicates
18349 /* 46692 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
18350 /* 46696 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18351 /* 46700 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18352 /* 46704 */ // MIs[10] Operand 1
18353 /* 46704 */ // No operand predicates
18354 /* 46704 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
18355 /* 46708 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18356 /* 46712 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18357 /* 46716 */ // MIs[11] Operand 1
18358 /* 46716 */ // No operand predicates
18359 /* 46716 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
18360 /* 46720 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18361 /* 46724 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18362 /* 46728 */ // MIs[12] Operand 1
18363 /* 46728 */ // No operand predicates
18364 /* 46728 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
18365 /* 46732 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18366 /* 46736 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18367 /* 46740 */ // MIs[13] Operand 1
18368 /* 46740 */ // No operand predicates
18369 /* 46740 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
18370 /* 46744 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18371 /* 46748 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18372 /* 46752 */ // MIs[14] Operand 1
18373 /* 46752 */ // No operand predicates
18374 /* 46752 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
18375 /* 46756 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18376 /* 46760 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18377 /* 46764 */ // MIs[15] Operand 1
18378 /* 46764 */ // No operand predicates
18379 /* 46764 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
18380 /* 46768 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18381 /* 46772 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18382 /* 46776 */ // MIs[16] Operand 1
18383 /* 46776 */ // No operand predicates
18384 /* 46776 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
18385 /* 46780 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18386 /* 46784 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18387 /* 46788 */ // MIs[17] Operand 1
18388 /* 46788 */ // No operand predicates
18389 /* 46788 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
18390 /* 46792 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18391 /* 46796 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
18392 /* 46800 */ // MIs[18] Operand 1
18393 /* 46800 */ // No operand predicates
18394 /* 46800 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
18395 /* 46802 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
18396 /* 46802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18397 /* 46805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
18398 /* 46807 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
18399 /* 46809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
18400 /* 46813 */ GIR_RootConstrainSelectedInstOperands,
18401 /* 46814 */ // GIR_Coverage, 2211,
18402 /* 46814 */ GIR_EraseRootFromParent_Done,
18403 /* 46815 */ // Label 1186: @46815
18404 /* 46815 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(46838), // Rule ID 997 //
18405 /* 46820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
18406 /* 46823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
18407 /* 46827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
18408 /* 46831 */ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
18409 /* 46831 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
18410 /* 46836 */ GIR_RootConstrainSelectedInstOperands,
18411 /* 46837 */ // GIR_Coverage, 997,
18412 /* 46837 */ GIR_Done,
18413 /* 46838 */ // Label 1187: @46838
18414 /* 46838 */ GIM_Reject,
18415 /* 46839 */ // Label 1184: @46839
18416 /* 46839 */ GIM_Reject,
18417 /* 46840 */ // Label 1163: @46840
18418 /* 46840 */ GIM_Reject,
18419 /* 46841 */ // Label 40: @46841
18420 /* 46841 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(47128),
18421 /* 46852 */ /*GILLT_s32*//*Label 1188*/ GIMT_Encode4(46860),
18422 /* 46856 */ /*GILLT_s64*//*Label 1189*/ GIMT_Encode4(46987),
18423 /* 46860 */ // Label 1188: @46860
18424 /* 46860 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(46986),
18425 /* 46865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18426 /* 46868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18427 /* 46871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18428 /* 46875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18429 /* 46879 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(46913), // Rule ID 67 //
18430 /* 46884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
18431 /* 46887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18432 /* 46891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18433 /* 46895 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
18434 /* 46899 */ // MIs[1] Operand 1
18435 /* 46899 */ // No operand predicates
18436 /* 46899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18437 /* 46901 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
18438 /* 46901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
18439 /* 46904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18440 /* 46906 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18441 /* 46908 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18442 /* 46911 */ GIR_RootConstrainSelectedInstOperands,
18443 /* 46912 */ // GIR_Coverage, 67,
18444 /* 46912 */ GIR_EraseRootFromParent_Done,
18445 /* 46913 */ // Label 1192: @46913
18446 /* 46913 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(46947), // Rule ID 1105 //
18447 /* 46918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18448 /* 46921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18449 /* 46925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18450 /* 46929 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
18451 /* 46933 */ // MIs[1] Operand 1
18452 /* 46933 */ // No operand predicates
18453 /* 46933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18454 /* 46935 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
18455 /* 46935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
18456 /* 46938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18457 /* 46940 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18458 /* 46942 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18459 /* 46945 */ GIR_RootConstrainSelectedInstOperands,
18460 /* 46946 */ // GIR_Coverage, 1105,
18461 /* 46946 */ GIR_EraseRootFromParent_Done,
18462 /* 46947 */ // Label 1193: @46947
18463 /* 46947 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(46966), // Rule ID 68 //
18464 /* 46952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
18465 /* 46955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18466 /* 46959 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18467 /* 46959 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
18468 /* 46964 */ GIR_RootConstrainSelectedInstOperands,
18469 /* 46965 */ // GIR_Coverage, 68,
18470 /* 46965 */ GIR_Done,
18471 /* 46966 */ // Label 1194: @46966
18472 /* 46966 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(46985), // Rule ID 1106 //
18473 /* 46971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18474 /* 46974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18475 /* 46978 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18476 /* 46978 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
18477 /* 46983 */ GIR_RootConstrainSelectedInstOperands,
18478 /* 46984 */ // GIR_Coverage, 1106,
18479 /* 46984 */ GIR_Done,
18480 /* 46985 */ // Label 1195: @46985
18481 /* 46985 */ GIM_Reject,
18482 /* 46986 */ // Label 1191: @46986
18483 /* 46986 */ GIM_Reject,
18484 /* 46987 */ // Label 1189: @46987
18485 /* 46987 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(47127),
18486 /* 46992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
18487 /* 46995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18488 /* 46998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18489 /* 47002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18490 /* 47006 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(47040), // Rule ID 246 //
18491 /* 47011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
18492 /* 47014 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18493 /* 47018 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18494 /* 47022 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
18495 /* 47026 */ // MIs[1] Operand 1
18496 /* 47026 */ // No operand predicates
18497 /* 47026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18498 /* 47028 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
18499 /* 47028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
18500 /* 47031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18501 /* 47033 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18502 /* 47035 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
18503 /* 47038 */ GIR_RootConstrainSelectedInstOperands,
18504 /* 47039 */ // GIR_Coverage, 246,
18505 /* 47039 */ GIR_EraseRootFromParent_Done,
18506 /* 47040 */ // Label 1197: @47040
18507 /* 47040 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(47107), // Rule ID 1681 //
18508 /* 47045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
18509 /* 47048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
18510 /* 47052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
18511 /* 47056 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
18512 /* 47060 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18513 /* 47065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18514 /* 47067 */ // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
18515 /* 47067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18516 /* 47070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
18517 /* 47074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18518 /* 47079 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
18519 /* 47085 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
18520 /* 47090 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
18521 /* 47095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
18522 /* 47098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18523 /* 47100 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
18524 /* 47102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18525 /* 47105 */ GIR_RootConstrainSelectedInstOperands,
18526 /* 47106 */ // GIR_Coverage, 1681,
18527 /* 47106 */ GIR_EraseRootFromParent_Done,
18528 /* 47107 */ // Label 1198: @47107
18529 /* 47107 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(47126), // Rule ID 247 //
18530 /* 47112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
18531 /* 47115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18532 /* 47119 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
18533 /* 47119 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
18534 /* 47124 */ GIR_RootConstrainSelectedInstOperands,
18535 /* 47125 */ // GIR_Coverage, 247,
18536 /* 47125 */ GIR_Done,
18537 /* 47126 */ // Label 1199: @47126
18538 /* 47126 */ GIM_Reject,
18539 /* 47127 */ // Label 1196: @47127
18540 /* 47127 */ GIM_Reject,
18541 /* 47128 */ // Label 1190: @47128
18542 /* 47128 */ GIM_Reject,
18543 /* 47129 */ // Label 41: @47129
18544 /* 47129 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(49659),
18545 /* 47134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18546 /* 47137 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1203*/ GIMT_Encode4(47322),
18547 /* 47148 */ /*GILLT_s32*//*Label 1201*/ GIMT_Encode4(47156),
18548 /* 47152 */ /*GILLT_s64*//*Label 1202*/ GIMT_Encode4(47239),
18549 /* 47156 */ // Label 1201: @47156
18550 /* 47156 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(47238),
18551 /* 47161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18552 /* 47164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18553 /* 47168 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(47201), // Rule ID 1438 //
18554 /* 47173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18555 /* 47176 */ // MIs[0] Operand 1
18556 /* 47176 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18557 /* 47181 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18558 /* 47185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18559 /* 47189 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18560 /* 47189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
18561 /* 47192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18562 /* 47194 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18563 /* 47196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18564 /* 47199 */ GIR_RootConstrainSelectedInstOperands,
18565 /* 47200 */ // GIR_Coverage, 1438,
18566 /* 47200 */ GIR_EraseRootFromParent_Done,
18567 /* 47201 */ // Label 1205: @47201
18568 /* 47201 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(47237), // Rule ID 1439 //
18569 /* 47206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18570 /* 47209 */ // MIs[0] Operand 1
18571 /* 47209 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18572 /* 47214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18573 /* 47218 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18574 /* 47222 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
18575 /* 47222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18576 /* 47225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18577 /* 47227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18578 /* 47233 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18579 /* 47235 */ GIR_RootConstrainSelectedInstOperands,
18580 /* 47236 */ // GIR_Coverage, 1439,
18581 /* 47236 */ GIR_EraseRootFromParent_Done,
18582 /* 47237 */ // Label 1206: @47237
18583 /* 47237 */ GIM_Reject,
18584 /* 47238 */ // Label 1204: @47238
18585 /* 47238 */ GIM_Reject,
18586 /* 47239 */ // Label 1202: @47239
18587 /* 47239 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(47321),
18588 /* 47244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18589 /* 47247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18590 /* 47251 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(47284), // Rule ID 1663 //
18591 /* 47256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18592 /* 47259 */ // MIs[0] Operand 1
18593 /* 47259 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18594 /* 47264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18595 /* 47268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18596 /* 47272 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
18597 /* 47272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18598 /* 47275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18599 /* 47277 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18600 /* 47279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18601 /* 47282 */ GIR_RootConstrainSelectedInstOperands,
18602 /* 47283 */ // GIR_Coverage, 1663,
18603 /* 47283 */ GIR_EraseRootFromParent_Done,
18604 /* 47284 */ // Label 1208: @47284
18605 /* 47284 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(47320), // Rule ID 1664 //
18606 /* 47289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18607 /* 47292 */ // MIs[0] Operand 1
18608 /* 47292 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18609 /* 47297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18610 /* 47301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18611 /* 47305 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
18612 /* 47305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18613 /* 47308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18614 /* 47310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18615 /* 47316 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18616 /* 47318 */ GIR_RootConstrainSelectedInstOperands,
18617 /* 47319 */ // GIR_Coverage, 1664,
18618 /* 47319 */ GIR_EraseRootFromParent_Done,
18619 /* 47320 */ // Label 1209: @47320
18620 /* 47320 */ GIM_Reject,
18621 /* 47321 */ // Label 1207: @47321
18622 /* 47321 */ GIM_Reject,
18623 /* 47322 */ // Label 1203: @47322
18624 /* 47322 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1212*/ GIMT_Encode4(47705),
18625 /* 47333 */ /*GILLT_s32*//*Label 1210*/ GIMT_Encode4(47341),
18626 /* 47337 */ /*GILLT_s64*//*Label 1211*/ GIMT_Encode4(47627),
18627 /* 47341 */ // Label 1210: @47341
18628 /* 47341 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(47626),
18629 /* 47346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18630 /* 47349 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(47386), // Rule ID 2013 //
18631 /* 47354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18632 /* 47357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18633 /* 47361 */ // MIs[0] Operand 1
18634 /* 47361 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18635 /* 47366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18636 /* 47370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18637 /* 47374 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18638 /* 47374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
18639 /* 47377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18640 /* 47379 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18641 /* 47381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18642 /* 47384 */ GIR_RootConstrainSelectedInstOperands,
18643 /* 47385 */ // GIR_Coverage, 2013,
18644 /* 47385 */ GIR_EraseRootFromParent_Done,
18645 /* 47386 */ // Label 1214: @47386
18646 /* 47386 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(47476), // Rule ID 2015 //
18647 /* 47391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18648 /* 47394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18649 /* 47398 */ // MIs[0] Operand 1
18650 /* 47398 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18651 /* 47403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18652 /* 47407 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709518847u),
18653 /* 47418 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18654 /* 47418 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18655 /* 47421 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18656 /* 47425 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18657 /* 47430 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18658 /* 47433 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18659 /* 47435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18660 /* 47438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
18661 /* 47442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18662 /* 47447 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18663 /* 47451 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
18664 /* 47461 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18665 /* 47463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18666 /* 47466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18667 /* 47468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18668 /* 47471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18669 /* 47474 */ GIR_RootConstrainSelectedInstOperands,
18670 /* 47475 */ // GIR_Coverage, 2015,
18671 /* 47475 */ GIR_EraseRootFromParent_Done,
18672 /* 47476 */ // Label 1215: @47476
18673 /* 47476 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(47513), // Rule ID 2334 //
18674 /* 47481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18675 /* 47484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18676 /* 47488 */ // MIs[0] Operand 1
18677 /* 47488 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18678 /* 47493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18679 /* 47497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18680 /* 47501 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
18681 /* 47501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
18682 /* 47504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18683 /* 47506 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18684 /* 47508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18685 /* 47511 */ GIR_RootConstrainSelectedInstOperands,
18686 /* 47512 */ // GIR_Coverage, 2334,
18687 /* 47512 */ GIR_EraseRootFromParent_Done,
18688 /* 47513 */ // Label 1216: @47513
18689 /* 47513 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(47553), // Rule ID 2335 //
18690 /* 47518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18691 /* 47521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18692 /* 47525 */ // MIs[0] Operand 1
18693 /* 47525 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18694 /* 47530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18695 /* 47534 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18696 /* 47538 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
18697 /* 47538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18698 /* 47541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18699 /* 47543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18700 /* 47549 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18701 /* 47551 */ GIR_RootConstrainSelectedInstOperands,
18702 /* 47552 */ // GIR_Coverage, 2335,
18703 /* 47552 */ GIR_EraseRootFromParent_Done,
18704 /* 47553 */ // Label 1217: @47553
18705 /* 47553 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(47589), // Rule ID 49 //
18706 /* 47558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18707 /* 47561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18708 /* 47565 */ // MIs[0] Operand 1
18709 /* 47565 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18710 /* 47570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18711 /* 47574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18712 /* 47578 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18713 /* 47578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
18714 /* 47581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18715 /* 47583 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18716 /* 47585 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18717 /* 47587 */ GIR_RootConstrainSelectedInstOperands,
18718 /* 47588 */ // GIR_Coverage, 49,
18719 /* 47588 */ GIR_EraseRootFromParent_Done,
18720 /* 47589 */ // Label 1218: @47589
18721 /* 47589 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(47625), // Rule ID 50 //
18722 /* 47594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18723 /* 47597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18724 /* 47601 */ // MIs[0] Operand 1
18725 /* 47601 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18726 /* 47606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18727 /* 47610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18728 /* 47614 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18729 /* 47614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18730 /* 47617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18731 /* 47619 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18732 /* 47621 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18733 /* 47623 */ GIR_RootConstrainSelectedInstOperands,
18734 /* 47624 */ // GIR_Coverage, 50,
18735 /* 47624 */ GIR_EraseRootFromParent_Done,
18736 /* 47625 */ // Label 1219: @47625
18737 /* 47625 */ GIM_Reject,
18738 /* 47626 */ // Label 1213: @47626
18739 /* 47626 */ GIM_Reject,
18740 /* 47627 */ // Label 1211: @47627
18741 /* 47627 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(47704),
18742 /* 47632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18743 /* 47635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18744 /* 47639 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(47671), // Rule ID 228 //
18745 /* 47644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18746 /* 47647 */ // MIs[0] Operand 1
18747 /* 47647 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18748 /* 47652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18749 /* 47656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18750 /* 47660 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18751 /* 47660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18752 /* 47663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18753 /* 47665 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18754 /* 47667 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18755 /* 47669 */ GIR_RootConstrainSelectedInstOperands,
18756 /* 47670 */ // GIR_Coverage, 228,
18757 /* 47670 */ GIR_EraseRootFromParent_Done,
18758 /* 47671 */ // Label 1221: @47671
18759 /* 47671 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(47703), // Rule ID 229 //
18760 /* 47676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
18761 /* 47679 */ // MIs[0] Operand 1
18762 /* 47679 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18763 /* 47684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18764 /* 47688 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18765 /* 47692 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18766 /* 47692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18767 /* 47695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18768 /* 47697 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18769 /* 47699 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18770 /* 47701 */ GIR_RootConstrainSelectedInstOperands,
18771 /* 47702 */ // GIR_Coverage, 229,
18772 /* 47702 */ GIR_EraseRootFromParent_Done,
18773 /* 47703 */ // Label 1222: @47703
18774 /* 47703 */ GIM_Reject,
18775 /* 47704 */ // Label 1220: @47704
18776 /* 47704 */ GIM_Reject,
18777 /* 47705 */ // Label 1212: @47705
18778 /* 47705 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1225*/ GIMT_Encode4(48622),
18779 /* 47716 */ /*GILLT_s32*//*Label 1223*/ GIMT_Encode4(47724),
18780 /* 47720 */ /*GILLT_s64*//*Label 1224*/ GIMT_Encode4(48205),
18781 /* 47724 */ // Label 1223: @47724
18782 /* 47724 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(48204),
18783 /* 47729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18784 /* 47732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18785 /* 47736 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(47768), // Rule ID 1099 //
18786 /* 47741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18787 /* 47744 */ // MIs[0] Operand 1
18788 /* 47744 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18789 /* 47749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18790 /* 47753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18791 /* 47757 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18792 /* 47757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18793 /* 47760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18794 /* 47762 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18795 /* 47764 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18796 /* 47766 */ GIR_RootConstrainSelectedInstOperands,
18797 /* 47767 */ // GIR_Coverage, 1099,
18798 /* 47767 */ GIR_EraseRootFromParent_Done,
18799 /* 47768 */ // Label 1227: @47768
18800 /* 47768 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(47800), // Rule ID 1100 //
18801 /* 47773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
18802 /* 47776 */ // MIs[0] Operand 1
18803 /* 47776 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18804 /* 47781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18805 /* 47785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18806 /* 47789 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
18807 /* 47789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18808 /* 47792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18809 /* 47794 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18810 /* 47796 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18811 /* 47798 */ GIR_RootConstrainSelectedInstOperands,
18812 /* 47799 */ // GIR_Coverage, 1100,
18813 /* 47799 */ GIR_EraseRootFromParent_Done,
18814 /* 47800 */ // Label 1228: @47800
18815 /* 47800 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(47856), // Rule ID 1440 //
18816 /* 47805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18817 /* 47808 */ // MIs[0] Operand 1
18818 /* 47808 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18819 /* 47813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18820 /* 47817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18821 /* 47821 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18822 /* 47821 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18823 /* 47824 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18824 /* 47828 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18825 /* 47833 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18826 /* 47837 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18827 /* 47841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18828 /* 47843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
18829 /* 47846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18830 /* 47848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18831 /* 47851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18832 /* 47854 */ GIR_RootConstrainSelectedInstOperands,
18833 /* 47855 */ // GIR_Coverage, 1440,
18834 /* 47855 */ GIR_EraseRootFromParent_Done,
18835 /* 47856 */ // Label 1229: @47856
18836 /* 47856 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(47915), // Rule ID 1441 //
18837 /* 47861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18838 /* 47864 */ // MIs[0] Operand 1
18839 /* 47864 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18840 /* 47869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18841 /* 47873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18842 /* 47877 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18843 /* 47877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18844 /* 47880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18845 /* 47884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18846 /* 47889 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18847 /* 47893 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18848 /* 47897 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18849 /* 47899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18850 /* 47902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18851 /* 47904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18852 /* 47910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18853 /* 47913 */ GIR_RootConstrainSelectedInstOperands,
18854 /* 47914 */ // GIR_Coverage, 1441,
18855 /* 47914 */ GIR_EraseRootFromParent_Done,
18856 /* 47915 */ // Label 1230: @47915
18857 /* 47915 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(47971), // Rule ID 1442 //
18858 /* 47920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18859 /* 47923 */ // MIs[0] Operand 1
18860 /* 47923 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18861 /* 47928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18862 /* 47932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18863 /* 47936 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18864 /* 47936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18865 /* 47939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18866 /* 47943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18867 /* 47948 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18868 /* 47952 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18869 /* 47956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18870 /* 47958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18871 /* 47961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18872 /* 47963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18873 /* 47966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18874 /* 47969 */ GIR_RootConstrainSelectedInstOperands,
18875 /* 47970 */ // GIR_Coverage, 1442,
18876 /* 47970 */ GIR_EraseRootFromParent_Done,
18877 /* 47971 */ // Label 1231: @47971
18878 /* 47971 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(48027), // Rule ID 1443 //
18879 /* 47976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18880 /* 47979 */ // MIs[0] Operand 1
18881 /* 47979 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18882 /* 47984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18883 /* 47988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18884 /* 47992 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18885 /* 47992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18886 /* 47995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18887 /* 47999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18888 /* 48004 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18889 /* 48008 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18890 /* 48012 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18891 /* 48014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18892 /* 48017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18893 /* 48019 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18894 /* 48022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18895 /* 48025 */ GIR_RootConstrainSelectedInstOperands,
18896 /* 48026 */ // GIR_Coverage, 1443,
18897 /* 48026 */ GIR_EraseRootFromParent_Done,
18898 /* 48027 */ // Label 1232: @48027
18899 /* 48027 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(48059), // Rule ID 1444 //
18900 /* 48032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18901 /* 48035 */ // MIs[0] Operand 1
18902 /* 48035 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18903 /* 48040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18904 /* 48044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18905 /* 48048 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18906 /* 48048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
18907 /* 48051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18908 /* 48053 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18909 /* 48055 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18910 /* 48057 */ GIR_RootConstrainSelectedInstOperands,
18911 /* 48058 */ // GIR_Coverage, 1444,
18912 /* 48058 */ GIR_EraseRootFromParent_Done,
18913 /* 48059 */ // Label 1233: @48059
18914 /* 48059 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(48091), // Rule ID 1445 //
18915 /* 48064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18916 /* 48067 */ // MIs[0] Operand 1
18917 /* 48067 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18918 /* 48072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18919 /* 48076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18920 /* 48080 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18921 /* 48080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18922 /* 48083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18923 /* 48085 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18924 /* 48087 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18925 /* 48089 */ GIR_RootConstrainSelectedInstOperands,
18926 /* 48090 */ // GIR_Coverage, 1445,
18927 /* 48090 */ GIR_EraseRootFromParent_Done,
18928 /* 48091 */ // Label 1234: @48091
18929 /* 48091 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(48147), // Rule ID 1446 //
18930 /* 48096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18931 /* 48099 */ // MIs[0] Operand 1
18932 /* 48099 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18933 /* 48104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18934 /* 48108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18935 /* 48112 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18936 /* 48112 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18937 /* 48115 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18938 /* 48119 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18939 /* 48124 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18940 /* 48128 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18941 /* 48132 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18942 /* 48134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18943 /* 48137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18944 /* 48139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18945 /* 48142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18946 /* 48145 */ GIR_RootConstrainSelectedInstOperands,
18947 /* 48146 */ // GIR_Coverage, 1446,
18948 /* 48146 */ GIR_EraseRootFromParent_Done,
18949 /* 48147 */ // Label 1235: @48147
18950 /* 48147 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(48203), // Rule ID 1447 //
18951 /* 48152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
18952 /* 48155 */ // MIs[0] Operand 1
18953 /* 48155 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18954 /* 48160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18955 /* 48164 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18956 /* 48168 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18957 /* 48168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18958 /* 48171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18959 /* 48175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18960 /* 48180 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18961 /* 48184 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18962 /* 48188 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18963 /* 48190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18964 /* 48193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18965 /* 48195 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18966 /* 48198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18967 /* 48201 */ GIR_RootConstrainSelectedInstOperands,
18968 /* 48202 */ // GIR_Coverage, 1447,
18969 /* 48202 */ GIR_EraseRootFromParent_Done,
18970 /* 48203 */ // Label 1236: @48203
18971 /* 48203 */ GIM_Reject,
18972 /* 48204 */ // Label 1226: @48204
18973 /* 48204 */ GIM_Reject,
18974 /* 48205 */ // Label 1224: @48205
18975 /* 48205 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(48621),
18976 /* 48210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18977 /* 48213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18978 /* 48217 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(48273), // Rule ID 1665 //
18979 /* 48222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
18980 /* 48225 */ // MIs[0] Operand 1
18981 /* 48225 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18982 /* 48230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18983 /* 48234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18984 /* 48238 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
18985 /* 48238 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18986 /* 48241 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18987 /* 48245 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18988 /* 48250 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18989 /* 48254 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18990 /* 48258 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18991 /* 48260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18992 /* 48263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18993 /* 48265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18994 /* 48268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18995 /* 48271 */ GIR_RootConstrainSelectedInstOperands,
18996 /* 48272 */ // GIR_Coverage, 1665,
18997 /* 48272 */ GIR_EraseRootFromParent_Done,
18998 /* 48273 */ // Label 1238: @48273
18999 /* 48273 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(48332), // Rule ID 1666 //
19000 /* 48278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19001 /* 48281 */ // MIs[0] Operand 1
19002 /* 48281 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19003 /* 48286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19004 /* 48290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19005 /* 48294 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
19006 /* 48294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19007 /* 48297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19008 /* 48301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19009 /* 48306 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19010 /* 48310 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19011 /* 48314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19012 /* 48316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19013 /* 48319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19014 /* 48321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19015 /* 48327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19016 /* 48330 */ GIR_RootConstrainSelectedInstOperands,
19017 /* 48331 */ // GIR_Coverage, 1666,
19018 /* 48331 */ GIR_EraseRootFromParent_Done,
19019 /* 48332 */ // Label 1239: @48332
19020 /* 48332 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(48388), // Rule ID 1667 //
19021 /* 48337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19022 /* 48340 */ // MIs[0] Operand 1
19023 /* 48340 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19024 /* 48345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19025 /* 48349 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19026 /* 48353 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
19027 /* 48353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19028 /* 48356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19029 /* 48360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19030 /* 48365 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19031 /* 48369 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19032 /* 48373 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19033 /* 48375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19034 /* 48378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19035 /* 48380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19036 /* 48383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19037 /* 48386 */ GIR_RootConstrainSelectedInstOperands,
19038 /* 48387 */ // GIR_Coverage, 1667,
19039 /* 48387 */ GIR_EraseRootFromParent_Done,
19040 /* 48388 */ // Label 1240: @48388
19041 /* 48388 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(48444), // Rule ID 1668 //
19042 /* 48393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19043 /* 48396 */ // MIs[0] Operand 1
19044 /* 48396 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19045 /* 48401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19046 /* 48405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19047 /* 48409 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
19048 /* 48409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19049 /* 48412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19050 /* 48416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19051 /* 48421 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19052 /* 48425 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19053 /* 48429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19054 /* 48431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19055 /* 48434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19056 /* 48436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19057 /* 48439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19058 /* 48442 */ GIR_RootConstrainSelectedInstOperands,
19059 /* 48443 */ // GIR_Coverage, 1668,
19060 /* 48443 */ GIR_EraseRootFromParent_Done,
19061 /* 48444 */ // Label 1241: @48444
19062 /* 48444 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(48476), // Rule ID 1669 //
19063 /* 48449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19064 /* 48452 */ // MIs[0] Operand 1
19065 /* 48452 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19066 /* 48457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19067 /* 48461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19068 /* 48465 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
19069 /* 48465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19070 /* 48468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19071 /* 48470 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19072 /* 48472 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19073 /* 48474 */ GIR_RootConstrainSelectedInstOperands,
19074 /* 48475 */ // GIR_Coverage, 1669,
19075 /* 48475 */ GIR_EraseRootFromParent_Done,
19076 /* 48476 */ // Label 1242: @48476
19077 /* 48476 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(48508), // Rule ID 1670 //
19078 /* 48481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19079 /* 48484 */ // MIs[0] Operand 1
19080 /* 48484 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19081 /* 48489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19082 /* 48493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19083 /* 48497 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
19084 /* 48497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19085 /* 48500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19086 /* 48502 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19087 /* 48504 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19088 /* 48506 */ GIR_RootConstrainSelectedInstOperands,
19089 /* 48507 */ // GIR_Coverage, 1670,
19090 /* 48507 */ GIR_EraseRootFromParent_Done,
19091 /* 48508 */ // Label 1243: @48508
19092 /* 48508 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(48564), // Rule ID 1671 //
19093 /* 48513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19094 /* 48516 */ // MIs[0] Operand 1
19095 /* 48516 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19096 /* 48521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19097 /* 48525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19098 /* 48529 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
19099 /* 48529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19100 /* 48532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19101 /* 48536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19102 /* 48541 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19103 /* 48545 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19104 /* 48549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19105 /* 48551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19106 /* 48554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19107 /* 48556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19108 /* 48559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19109 /* 48562 */ GIR_RootConstrainSelectedInstOperands,
19110 /* 48563 */ // GIR_Coverage, 1671,
19111 /* 48563 */ GIR_EraseRootFromParent_Done,
19112 /* 48564 */ // Label 1244: @48564
19113 /* 48564 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(48620), // Rule ID 1672 //
19114 /* 48569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
19115 /* 48572 */ // MIs[0] Operand 1
19116 /* 48572 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19117 /* 48577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19118 /* 48581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19119 /* 48585 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
19120 /* 48585 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19121 /* 48588 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19122 /* 48592 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19123 /* 48597 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19124 /* 48601 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19125 /* 48605 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19126 /* 48607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
19127 /* 48610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19128 /* 48612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19129 /* 48615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19130 /* 48618 */ GIR_RootConstrainSelectedInstOperands,
19131 /* 48619 */ // GIR_Coverage, 1672,
19132 /* 48619 */ GIR_EraseRootFromParent_Done,
19133 /* 48620 */ // Label 1245: @48620
19134 /* 48620 */ GIM_Reject,
19135 /* 48621 */ // Label 1237: @48621
19136 /* 48621 */ GIM_Reject,
19137 /* 48622 */ // Label 1225: @48622
19138 /* 48622 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(49658),
19139 /* 48627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19140 /* 48630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19141 /* 48633 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(48693), // Rule ID 2012 //
19142 /* 48638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19143 /* 48641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19144 /* 48645 */ // MIs[0] Operand 1
19145 /* 48645 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19146 /* 48650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19147 /* 48654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19148 /* 48658 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19149 /* 48658 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19150 /* 48661 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19151 /* 48665 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19152 /* 48670 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19153 /* 48674 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19154 /* 48678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19155 /* 48680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
19156 /* 48683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19157 /* 48685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19158 /* 48688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19159 /* 48691 */ GIR_RootConstrainSelectedInstOperands,
19160 /* 48692 */ // GIR_Coverage, 2012,
19161 /* 48692 */ GIR_EraseRootFromParent_Done,
19162 /* 48693 */ // Label 1247: @48693
19163 /* 48693 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(48770), // Rule ID 2014 //
19164 /* 48698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19165 /* 48701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19166 /* 48705 */ // MIs[0] Operand 1
19167 /* 48705 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19168 /* 48710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19169 /* 48714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19170 /* 48718 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19171 /* 48718 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19172 /* 48721 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19173 /* 48725 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19174 /* 48730 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19175 /* 48733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19176 /* 48735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19177 /* 48738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19178 /* 48742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19179 /* 48747 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19180 /* 48751 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19181 /* 48755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19182 /* 48757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19183 /* 48760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19184 /* 48762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19185 /* 48765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19186 /* 48768 */ GIR_RootConstrainSelectedInstOperands,
19187 /* 48769 */ // GIR_Coverage, 2014,
19188 /* 48769 */ GIR_EraseRootFromParent_Done,
19189 /* 48770 */ // Label 1248: @48770
19190 /* 48770 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(48806), // Rule ID 2016 //
19191 /* 48775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19192 /* 48778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19193 /* 48782 */ // MIs[0] Operand 1
19194 /* 48782 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19195 /* 48787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19196 /* 48791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19197 /* 48795 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
19198 /* 48795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19199 /* 48798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19200 /* 48800 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19201 /* 48802 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19202 /* 48804 */ GIR_RootConstrainSelectedInstOperands,
19203 /* 48805 */ // GIR_Coverage, 2016,
19204 /* 48805 */ GIR_EraseRootFromParent_Done,
19205 /* 48806 */ // Label 1249: @48806
19206 /* 48806 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(48883), // Rule ID 2017 //
19207 /* 48811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19208 /* 48814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19209 /* 48818 */ // MIs[0] Operand 1
19210 /* 48818 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19211 /* 48823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19212 /* 48827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19213 /* 48831 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
19214 /* 48831 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19215 /* 48834 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
19216 /* 48838 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19217 /* 48843 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19218 /* 48846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19219 /* 48848 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19220 /* 48851 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19221 /* 48855 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19222 /* 48860 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19223 /* 48864 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19224 /* 48868 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19225 /* 48870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19226 /* 48873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19227 /* 48875 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19228 /* 48878 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19229 /* 48881 */ GIR_RootConstrainSelectedInstOperands,
19230 /* 48882 */ // GIR_Coverage, 2017,
19231 /* 48882 */ GIR_EraseRootFromParent_Done,
19232 /* 48883 */ // Label 1250: @48883
19233 /* 48883 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(48919), // Rule ID 2018 //
19234 /* 48888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19235 /* 48891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19236 /* 48895 */ // MIs[0] Operand 1
19237 /* 48895 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
19238 /* 48900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19239 /* 48904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19240 /* 48908 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
19241 /* 48908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
19242 /* 48911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19243 /* 48913 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
19244 /* 48915 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
19245 /* 48917 */ GIR_RootConstrainSelectedInstOperands,
19246 /* 48918 */ // GIR_Coverage, 2018,
19247 /* 48918 */ GIR_EraseRootFromParent_Done,
19248 /* 48919 */ // Label 1251: @48919
19249 /* 48919 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(48996), // Rule ID 2020 //
19250 /* 48924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19251 /* 48927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19252 /* 48931 */ // MIs[0] Operand 1
19253 /* 48931 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19254 /* 48936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19255 /* 48940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19256 /* 48944 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
19257 /* 48944 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19258 /* 48947 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19259 /* 48951 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19260 /* 48956 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19261 /* 48960 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19262 /* 48964 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19263 /* 48966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19264 /* 48969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19265 /* 48973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19266 /* 48978 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
19267 /* 48981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19268 /* 48983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19269 /* 48986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19270 /* 48988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19271 /* 48991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19272 /* 48994 */ GIR_RootConstrainSelectedInstOperands,
19273 /* 48995 */ // GIR_Coverage, 2020,
19274 /* 48995 */ GIR_EraseRootFromParent_Done,
19275 /* 48996 */ // Label 1252: @48996
19276 /* 48996 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(49073), // Rule ID 2021 //
19277 /* 49001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19278 /* 49004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19279 /* 49008 */ // MIs[0] Operand 1
19280 /* 49008 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19281 /* 49013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19282 /* 49017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19283 /* 49021 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19284 /* 49021 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19285 /* 49024 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19286 /* 49028 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19287 /* 49033 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19288 /* 49036 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19289 /* 49038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19290 /* 49041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19291 /* 49045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19292 /* 49050 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19293 /* 49054 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19294 /* 49058 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19295 /* 49060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19296 /* 49063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19297 /* 49065 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19298 /* 49068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19299 /* 49071 */ GIR_RootConstrainSelectedInstOperands,
19300 /* 49072 */ // GIR_Coverage, 2021,
19301 /* 49072 */ GIR_EraseRootFromParent_Done,
19302 /* 49073 */ // Label 1253: @49073
19303 /* 49073 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(49109), // Rule ID 2022 //
19304 /* 49078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19305 /* 49081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19306 /* 49085 */ // MIs[0] Operand 1
19307 /* 49085 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19308 /* 49090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19309 /* 49094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19310 /* 49098 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
19311 /* 49098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19312 /* 49101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19313 /* 49103 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19314 /* 49105 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19315 /* 49107 */ GIR_RootConstrainSelectedInstOperands,
19316 /* 49108 */ // GIR_Coverage, 2022,
19317 /* 49108 */ GIR_EraseRootFromParent_Done,
19318 /* 49109 */ // Label 1254: @49109
19319 /* 49109 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(49186), // Rule ID 2023 //
19320 /* 49114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19321 /* 49117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19322 /* 49121 */ // MIs[0] Operand 1
19323 /* 49121 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19324 /* 49126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19325 /* 49130 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19326 /* 49134 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
19327 /* 49134 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
19328 /* 49137 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
19329 /* 49141 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19330 /* 49146 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
19331 /* 49149 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
19332 /* 49151 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19333 /* 49154 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19334 /* 49158 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19335 /* 49163 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19336 /* 49167 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19337 /* 49171 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19338 /* 49173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
19339 /* 49176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
19340 /* 49178 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19341 /* 49181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
19342 /* 49184 */ GIR_RootConstrainSelectedInstOperands,
19343 /* 49185 */ // GIR_Coverage, 2023,
19344 /* 49185 */ GIR_EraseRootFromParent_Done,
19345 /* 49186 */ // Label 1255: @49186
19346 /* 49186 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(49222), // Rule ID 2024 //
19347 /* 49191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19348 /* 49194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19349 /* 49198 */ // MIs[0] Operand 1
19350 /* 49198 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
19351 /* 49203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19352 /* 49207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19353 /* 49211 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
19354 /* 49211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
19355 /* 49214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
19356 /* 49216 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
19357 /* 49218 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
19358 /* 49220 */ GIR_RootConstrainSelectedInstOperands,
19359 /* 49221 */ // GIR_Coverage, 2024,
19360 /* 49221 */ GIR_EraseRootFromParent_Done,
19361 /* 49222 */ // Label 1256: @49222
19362 /* 49222 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(49282), // Rule ID 2336 //
19363 /* 49227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19364 /* 49230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19365 /* 49234 */ // MIs[0] Operand 1
19366 /* 49234 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19367 /* 49239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19368 /* 49243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19369 /* 49247 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19370 /* 49247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19371 /* 49250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
19372 /* 49254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19373 /* 49259 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19374 /* 49263 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19375 /* 49267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19376 /* 49269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
19377 /* 49272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19378 /* 49274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19379 /* 49277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19380 /* 49280 */ GIR_RootConstrainSelectedInstOperands,
19381 /* 49281 */ // GIR_Coverage, 2336,
19382 /* 49281 */ GIR_EraseRootFromParent_Done,
19383 /* 49282 */ // Label 1257: @49282
19384 /* 49282 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(49345), // Rule ID 2337 //
19385 /* 49287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19386 /* 49290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19387 /* 49294 */ // MIs[0] Operand 1
19388 /* 49294 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19389 /* 49299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19390 /* 49303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19391 /* 49307 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
19392 /* 49307 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19393 /* 49310 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
19394 /* 49314 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19395 /* 49319 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19396 /* 49323 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19397 /* 49327 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19398 /* 49329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19399 /* 49332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19400 /* 49334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19401 /* 49340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19402 /* 49343 */ GIR_RootConstrainSelectedInstOperands,
19403 /* 49344 */ // GIR_Coverage, 2337,
19404 /* 49344 */ GIR_EraseRootFromParent_Done,
19405 /* 49345 */ // Label 1258: @49345
19406 /* 49345 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(49405), // Rule ID 2338 //
19407 /* 49350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19408 /* 49353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19409 /* 49357 */ // MIs[0] Operand 1
19410 /* 49357 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19411 /* 49362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19412 /* 49366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19413 /* 49370 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
19414 /* 49370 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19415 /* 49373 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19416 /* 49377 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19417 /* 49382 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19418 /* 49386 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19419 /* 49390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19420 /* 49392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19421 /* 49395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19422 /* 49397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19423 /* 49400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19424 /* 49403 */ GIR_RootConstrainSelectedInstOperands,
19425 /* 49404 */ // GIR_Coverage, 2338,
19426 /* 49404 */ GIR_EraseRootFromParent_Done,
19427 /* 49405 */ // Label 1259: @49405
19428 /* 49405 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(49465), // Rule ID 2339 //
19429 /* 49410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19430 /* 49413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19431 /* 49417 */ // MIs[0] Operand 1
19432 /* 49417 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19433 /* 49422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19434 /* 49426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19435 /* 49430 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
19436 /* 49430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19437 /* 49433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19438 /* 49437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19439 /* 49442 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19440 /* 49446 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19441 /* 49450 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19442 /* 49452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19443 /* 49455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19444 /* 49457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19445 /* 49460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19446 /* 49463 */ GIR_RootConstrainSelectedInstOperands,
19447 /* 49464 */ // GIR_Coverage, 2339,
19448 /* 49464 */ GIR_EraseRootFromParent_Done,
19449 /* 49465 */ // Label 1260: @49465
19450 /* 49465 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(49501), // Rule ID 2340 //
19451 /* 49470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19452 /* 49473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19453 /* 49477 */ // MIs[0] Operand 1
19454 /* 49477 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19455 /* 49482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19456 /* 49486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19457 /* 49490 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
19458 /* 49490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19459 /* 49493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19460 /* 49495 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19461 /* 49497 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19462 /* 49499 */ GIR_RootConstrainSelectedInstOperands,
19463 /* 49500 */ // GIR_Coverage, 2340,
19464 /* 49500 */ GIR_EraseRootFromParent_Done,
19465 /* 49501 */ // Label 1261: @49501
19466 /* 49501 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(49537), // Rule ID 2341 //
19467 /* 49506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19468 /* 49509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19469 /* 49513 */ // MIs[0] Operand 1
19470 /* 49513 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19471 /* 49518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19472 /* 49522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19473 /* 49526 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
19474 /* 49526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19475 /* 49529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19476 /* 49531 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
19477 /* 49533 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
19478 /* 49535 */ GIR_RootConstrainSelectedInstOperands,
19479 /* 49536 */ // GIR_Coverage, 2341,
19480 /* 49536 */ GIR_EraseRootFromParent_Done,
19481 /* 49537 */ // Label 1262: @49537
19482 /* 49537 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(49597), // Rule ID 2342 //
19483 /* 49542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19484 /* 49545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19485 /* 49549 */ // MIs[0] Operand 1
19486 /* 49549 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19487 /* 49554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19488 /* 49558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19489 /* 49562 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19490 /* 49562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19491 /* 49565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19492 /* 49569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19493 /* 49574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19494 /* 49578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19495 /* 49582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19496 /* 49584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19497 /* 49587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19498 /* 49589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19499 /* 49592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19500 /* 49595 */ GIR_RootConstrainSelectedInstOperands,
19501 /* 49596 */ // GIR_Coverage, 2342,
19502 /* 49596 */ GIR_EraseRootFromParent_Done,
19503 /* 49597 */ // Label 1263: @49597
19504 /* 49597 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(49657), // Rule ID 2343 //
19505 /* 49602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
19506 /* 49605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19507 /* 49609 */ // MIs[0] Operand 1
19508 /* 49609 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19509 /* 49614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19510 /* 49618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19511 /* 49622 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
19512 /* 49622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19513 /* 49625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19514 /* 49629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19515 /* 49634 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
19516 /* 49638 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
19517 /* 49642 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19518 /* 49644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
19519 /* 49647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
19520 /* 49649 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19521 /* 49652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
19522 /* 49655 */ GIR_RootConstrainSelectedInstOperands,
19523 /* 49656 */ // GIR_Coverage, 2343,
19524 /* 49656 */ GIR_EraseRootFromParent_Done,
19525 /* 49657 */ // Label 1264: @49657
19526 /* 49657 */ GIM_Reject,
19527 /* 49658 */ // Label 1246: @49658
19528 /* 49658 */ GIM_Reject,
19529 /* 49659 */ // Label 1200: @49659
19530 /* 49659 */ GIM_Reject,
19531 /* 49660 */ // Label 42: @49660
19532 /* 49660 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(50659),
19533 /* 49665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19534 /* 49668 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(50163),
19535 /* 49679 */ /*GILLT_s32*//*Label 1266*/ GIMT_Encode4(49687),
19536 /* 49683 */ /*GILLT_s64*//*Label 1267*/ GIMT_Encode4(49925),
19537 /* 49687 */ // Label 1266: @49687
19538 /* 49687 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(49924),
19539 /* 49692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19540 /* 49695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
19541 /* 49699 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(49731), // Rule ID 336 //
19542 /* 49704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19543 /* 49707 */ // MIs[0] Operand 1
19544 /* 49707 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19545 /* 49712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19546 /* 49716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19547 /* 49720 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19548 /* 49720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
19549 /* 49723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19550 /* 49725 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19551 /* 49727 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19552 /* 49729 */ GIR_RootConstrainSelectedInstOperands,
19553 /* 49730 */ // GIR_Coverage, 336,
19554 /* 49730 */ GIR_EraseRootFromParent_Done,
19555 /* 49731 */ // Label 1270: @49731
19556 /* 49731 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(49763), // Rule ID 337 //
19557 /* 49736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19558 /* 49739 */ // MIs[0] Operand 1
19559 /* 49739 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19560 /* 49744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19561 /* 49748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19562 /* 49752 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19563 /* 49752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
19564 /* 49755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19565 /* 49757 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19566 /* 49759 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19567 /* 49761 */ GIR_RootConstrainSelectedInstOperands,
19568 /* 49762 */ // GIR_Coverage, 337,
19569 /* 49762 */ GIR_EraseRootFromParent_Done,
19570 /* 49763 */ // Label 1271: @49763
19571 /* 49763 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(49795), // Rule ID 338 //
19572 /* 49768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19573 /* 49771 */ // MIs[0] Operand 1
19574 /* 49771 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19575 /* 49776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19576 /* 49780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19577 /* 49784 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19578 /* 49784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
19579 /* 49787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19580 /* 49789 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19581 /* 49791 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19582 /* 49793 */ GIR_RootConstrainSelectedInstOperands,
19583 /* 49794 */ // GIR_Coverage, 338,
19584 /* 49794 */ GIR_EraseRootFromParent_Done,
19585 /* 49795 */ // Label 1272: @49795
19586 /* 49795 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(49827), // Rule ID 339 //
19587 /* 49800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19588 /* 49803 */ // MIs[0] Operand 1
19589 /* 49803 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19590 /* 49808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19591 /* 49812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19592 /* 49816 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19593 /* 49816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
19594 /* 49819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19595 /* 49821 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19596 /* 49823 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19597 /* 49825 */ GIR_RootConstrainSelectedInstOperands,
19598 /* 49826 */ // GIR_Coverage, 339,
19599 /* 49826 */ GIR_EraseRootFromParent_Done,
19600 /* 49827 */ // Label 1273: @49827
19601 /* 49827 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(49859), // Rule ID 340 //
19602 /* 49832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19603 /* 49835 */ // MIs[0] Operand 1
19604 /* 49835 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19605 /* 49840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19606 /* 49844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19607 /* 49848 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19608 /* 49848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
19609 /* 49851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19610 /* 49853 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19611 /* 49855 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19612 /* 49857 */ GIR_RootConstrainSelectedInstOperands,
19613 /* 49858 */ // GIR_Coverage, 340,
19614 /* 49858 */ GIR_EraseRootFromParent_Done,
19615 /* 49859 */ // Label 1274: @49859
19616 /* 49859 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(49891), // Rule ID 341 //
19617 /* 49864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19618 /* 49867 */ // MIs[0] Operand 1
19619 /* 49867 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19620 /* 49872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19621 /* 49876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19622 /* 49880 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19623 /* 49880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
19624 /* 49883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19625 /* 49885 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19626 /* 49887 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19627 /* 49889 */ GIR_RootConstrainSelectedInstOperands,
19628 /* 49890 */ // GIR_Coverage, 341,
19629 /* 49890 */ GIR_EraseRootFromParent_Done,
19630 /* 49891 */ // Label 1275: @49891
19631 /* 49891 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(49923), // Rule ID 342 //
19632 /* 49896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19633 /* 49899 */ // MIs[0] Operand 1
19634 /* 49899 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19635 /* 49904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19636 /* 49908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19637 /* 49912 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19638 /* 49912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
19639 /* 49915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19640 /* 49917 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19641 /* 49919 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19642 /* 49921 */ GIR_RootConstrainSelectedInstOperands,
19643 /* 49922 */ // GIR_Coverage, 342,
19644 /* 49922 */ GIR_EraseRootFromParent_Done,
19645 /* 49923 */ // Label 1276: @49923
19646 /* 49923 */ GIM_Reject,
19647 /* 49924 */ // Label 1269: @49924
19648 /* 49924 */ GIM_Reject,
19649 /* 49925 */ // Label 1267: @49925
19650 /* 49925 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(50162),
19651 /* 49930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19652 /* 49933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
19653 /* 49937 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(49969), // Rule ID 343 //
19654 /* 49942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19655 /* 49945 */ // MIs[0] Operand 1
19656 /* 49945 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19657 /* 49950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19658 /* 49954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19659 /* 49958 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19660 /* 49958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
19661 /* 49961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19662 /* 49963 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19663 /* 49965 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19664 /* 49967 */ GIR_RootConstrainSelectedInstOperands,
19665 /* 49968 */ // GIR_Coverage, 343,
19666 /* 49968 */ GIR_EraseRootFromParent_Done,
19667 /* 49969 */ // Label 1278: @49969
19668 /* 49969 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(50001), // Rule ID 344 //
19669 /* 49974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19670 /* 49977 */ // MIs[0] Operand 1
19671 /* 49977 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19672 /* 49982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19673 /* 49986 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19674 /* 49990 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19675 /* 49990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
19676 /* 49993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19677 /* 49995 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19678 /* 49997 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19679 /* 49999 */ GIR_RootConstrainSelectedInstOperands,
19680 /* 50000 */ // GIR_Coverage, 344,
19681 /* 50000 */ GIR_EraseRootFromParent_Done,
19682 /* 50001 */ // Label 1279: @50001
19683 /* 50001 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(50033), // Rule ID 345 //
19684 /* 50006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19685 /* 50009 */ // MIs[0] Operand 1
19686 /* 50009 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19687 /* 50014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19688 /* 50018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19689 /* 50022 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19690 /* 50022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
19691 /* 50025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19692 /* 50027 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19693 /* 50029 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19694 /* 50031 */ GIR_RootConstrainSelectedInstOperands,
19695 /* 50032 */ // GIR_Coverage, 345,
19696 /* 50032 */ GIR_EraseRootFromParent_Done,
19697 /* 50033 */ // Label 1280: @50033
19698 /* 50033 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(50065), // Rule ID 346 //
19699 /* 50038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19700 /* 50041 */ // MIs[0] Operand 1
19701 /* 50041 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19702 /* 50046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19703 /* 50050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19704 /* 50054 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19705 /* 50054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
19706 /* 50057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19707 /* 50059 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19708 /* 50061 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19709 /* 50063 */ GIR_RootConstrainSelectedInstOperands,
19710 /* 50064 */ // GIR_Coverage, 346,
19711 /* 50064 */ GIR_EraseRootFromParent_Done,
19712 /* 50065 */ // Label 1281: @50065
19713 /* 50065 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(50097), // Rule ID 347 //
19714 /* 50070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19715 /* 50073 */ // MIs[0] Operand 1
19716 /* 50073 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19717 /* 50078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19718 /* 50082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19719 /* 50086 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19720 /* 50086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
19721 /* 50089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19722 /* 50091 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19723 /* 50093 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19724 /* 50095 */ GIR_RootConstrainSelectedInstOperands,
19725 /* 50096 */ // GIR_Coverage, 347,
19726 /* 50096 */ GIR_EraseRootFromParent_Done,
19727 /* 50097 */ // Label 1282: @50097
19728 /* 50097 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(50129), // Rule ID 348 //
19729 /* 50102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19730 /* 50105 */ // MIs[0] Operand 1
19731 /* 50105 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19732 /* 50110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19733 /* 50114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19734 /* 50118 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19735 /* 50118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
19736 /* 50121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19737 /* 50123 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19738 /* 50125 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19739 /* 50127 */ GIR_RootConstrainSelectedInstOperands,
19740 /* 50128 */ // GIR_Coverage, 348,
19741 /* 50128 */ GIR_EraseRootFromParent_Done,
19742 /* 50129 */ // Label 1283: @50129
19743 /* 50129 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(50161), // Rule ID 349 //
19744 /* 50134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
19745 /* 50137 */ // MIs[0] Operand 1
19746 /* 50137 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19747 /* 50142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19748 /* 50146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19749 /* 50150 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19750 /* 50150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
19751 /* 50153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19752 /* 50155 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19753 /* 50157 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19754 /* 50159 */ GIR_RootConstrainSelectedInstOperands,
19755 /* 50160 */ // GIR_Coverage, 349,
19756 /* 50160 */ GIR_EraseRootFromParent_Done,
19757 /* 50161 */ // Label 1284: @50161
19758 /* 50161 */ GIM_Reject,
19759 /* 50162 */ // Label 1277: @50162
19760 /* 50162 */ GIM_Reject,
19761 /* 50163 */ // Label 1268: @50163
19762 /* 50163 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1287*/ GIMT_Encode4(50658),
19763 /* 50174 */ /*GILLT_s32*//*Label 1285*/ GIMT_Encode4(50182),
19764 /* 50178 */ /*GILLT_s64*//*Label 1286*/ GIMT_Encode4(50420),
19765 /* 50182 */ // Label 1285: @50182
19766 /* 50182 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(50419),
19767 /* 50187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19768 /* 50190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
19769 /* 50194 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(50226), // Rule ID 1216 //
19770 /* 50199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19771 /* 50202 */ // MIs[0] Operand 1
19772 /* 50202 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19773 /* 50207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19774 /* 50211 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19775 /* 50215 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19776 /* 50215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
19777 /* 50218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19778 /* 50220 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19779 /* 50222 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19780 /* 50224 */ GIR_RootConstrainSelectedInstOperands,
19781 /* 50225 */ // GIR_Coverage, 1216,
19782 /* 50225 */ GIR_EraseRootFromParent_Done,
19783 /* 50226 */ // Label 1289: @50226
19784 /* 50226 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(50258), // Rule ID 1217 //
19785 /* 50231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19786 /* 50234 */ // MIs[0] Operand 1
19787 /* 50234 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19788 /* 50239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19789 /* 50243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19790 /* 50247 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19791 /* 50247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
19792 /* 50250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19793 /* 50252 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19794 /* 50254 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19795 /* 50256 */ GIR_RootConstrainSelectedInstOperands,
19796 /* 50257 */ // GIR_Coverage, 1217,
19797 /* 50257 */ GIR_EraseRootFromParent_Done,
19798 /* 50258 */ // Label 1290: @50258
19799 /* 50258 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(50290), // Rule ID 1218 //
19800 /* 50263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19801 /* 50266 */ // MIs[0] Operand 1
19802 /* 50266 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19803 /* 50271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19804 /* 50275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19805 /* 50279 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19806 /* 50279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
19807 /* 50282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19808 /* 50284 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19809 /* 50286 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19810 /* 50288 */ GIR_RootConstrainSelectedInstOperands,
19811 /* 50289 */ // GIR_Coverage, 1218,
19812 /* 50289 */ GIR_EraseRootFromParent_Done,
19813 /* 50290 */ // Label 1291: @50290
19814 /* 50290 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(50322), // Rule ID 1219 //
19815 /* 50295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19816 /* 50298 */ // MIs[0] Operand 1
19817 /* 50298 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19818 /* 50303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19819 /* 50307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19820 /* 50311 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19821 /* 50311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
19822 /* 50314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19823 /* 50316 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19824 /* 50318 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19825 /* 50320 */ GIR_RootConstrainSelectedInstOperands,
19826 /* 50321 */ // GIR_Coverage, 1219,
19827 /* 50321 */ GIR_EraseRootFromParent_Done,
19828 /* 50322 */ // Label 1292: @50322
19829 /* 50322 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(50354), // Rule ID 1220 //
19830 /* 50327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19831 /* 50330 */ // MIs[0] Operand 1
19832 /* 50330 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19833 /* 50335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19834 /* 50339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19835 /* 50343 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19836 /* 50343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
19837 /* 50346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19838 /* 50348 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19839 /* 50350 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19840 /* 50352 */ GIR_RootConstrainSelectedInstOperands,
19841 /* 50353 */ // GIR_Coverage, 1220,
19842 /* 50353 */ GIR_EraseRootFromParent_Done,
19843 /* 50354 */ // Label 1293: @50354
19844 /* 50354 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(50386), // Rule ID 1221 //
19845 /* 50359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19846 /* 50362 */ // MIs[0] Operand 1
19847 /* 50362 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19848 /* 50367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19849 /* 50371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19850 /* 50375 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19851 /* 50375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
19852 /* 50378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19853 /* 50380 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19854 /* 50382 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19855 /* 50384 */ GIR_RootConstrainSelectedInstOperands,
19856 /* 50385 */ // GIR_Coverage, 1221,
19857 /* 50385 */ GIR_EraseRootFromParent_Done,
19858 /* 50386 */ // Label 1294: @50386
19859 /* 50386 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(50418), // Rule ID 1222 //
19860 /* 50391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19861 /* 50394 */ // MIs[0] Operand 1
19862 /* 50394 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19863 /* 50399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19864 /* 50403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19865 /* 50407 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
19866 /* 50407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
19867 /* 50410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19868 /* 50412 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19869 /* 50414 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19870 /* 50416 */ GIR_RootConstrainSelectedInstOperands,
19871 /* 50417 */ // GIR_Coverage, 1222,
19872 /* 50417 */ GIR_EraseRootFromParent_Done,
19873 /* 50418 */ // Label 1295: @50418
19874 /* 50418 */ GIM_Reject,
19875 /* 50419 */ // Label 1288: @50419
19876 /* 50419 */ GIM_Reject,
19877 /* 50420 */ // Label 1286: @50420
19878 /* 50420 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(50657),
19879 /* 50425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19880 /* 50428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
19881 /* 50432 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(50464), // Rule ID 1223 //
19882 /* 50437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19883 /* 50440 */ // MIs[0] Operand 1
19884 /* 50440 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
19885 /* 50445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19886 /* 50449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19887 /* 50453 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19888 /* 50453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
19889 /* 50456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19890 /* 50458 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19891 /* 50460 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19892 /* 50462 */ GIR_RootConstrainSelectedInstOperands,
19893 /* 50463 */ // GIR_Coverage, 1223,
19894 /* 50463 */ GIR_EraseRootFromParent_Done,
19895 /* 50464 */ // Label 1297: @50464
19896 /* 50464 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(50496), // Rule ID 1224 //
19897 /* 50469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19898 /* 50472 */ // MIs[0] Operand 1
19899 /* 50472 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
19900 /* 50477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19901 /* 50481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19902 /* 50485 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19903 /* 50485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
19904 /* 50488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19905 /* 50490 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19906 /* 50492 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19907 /* 50494 */ GIR_RootConstrainSelectedInstOperands,
19908 /* 50495 */ // GIR_Coverage, 1224,
19909 /* 50495 */ GIR_EraseRootFromParent_Done,
19910 /* 50496 */ // Label 1298: @50496
19911 /* 50496 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(50528), // Rule ID 1225 //
19912 /* 50501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19913 /* 50504 */ // MIs[0] Operand 1
19914 /* 50504 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
19915 /* 50509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19916 /* 50513 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19917 /* 50517 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19918 /* 50517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
19919 /* 50520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19920 /* 50522 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19921 /* 50524 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19922 /* 50526 */ GIR_RootConstrainSelectedInstOperands,
19923 /* 50527 */ // GIR_Coverage, 1225,
19924 /* 50527 */ GIR_EraseRootFromParent_Done,
19925 /* 50528 */ // Label 1299: @50528
19926 /* 50528 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(50560), // Rule ID 1226 //
19927 /* 50533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19928 /* 50536 */ // MIs[0] Operand 1
19929 /* 50536 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
19930 /* 50541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19931 /* 50545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19932 /* 50549 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19933 /* 50549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
19934 /* 50552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19935 /* 50554 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19936 /* 50556 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19937 /* 50558 */ GIR_RootConstrainSelectedInstOperands,
19938 /* 50559 */ // GIR_Coverage, 1226,
19939 /* 50559 */ GIR_EraseRootFromParent_Done,
19940 /* 50560 */ // Label 1300: @50560
19941 /* 50560 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(50592), // Rule ID 1227 //
19942 /* 50565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19943 /* 50568 */ // MIs[0] Operand 1
19944 /* 50568 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
19945 /* 50573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19946 /* 50577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19947 /* 50581 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19948 /* 50581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
19949 /* 50584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19950 /* 50586 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19951 /* 50588 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19952 /* 50590 */ GIR_RootConstrainSelectedInstOperands,
19953 /* 50591 */ // GIR_Coverage, 1227,
19954 /* 50591 */ GIR_EraseRootFromParent_Done,
19955 /* 50592 */ // Label 1301: @50592
19956 /* 50592 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(50624), // Rule ID 1228 //
19957 /* 50597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19958 /* 50600 */ // MIs[0] Operand 1
19959 /* 50600 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
19960 /* 50605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19961 /* 50609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19962 /* 50613 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19963 /* 50613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
19964 /* 50616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19965 /* 50618 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19966 /* 50620 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19967 /* 50622 */ GIR_RootConstrainSelectedInstOperands,
19968 /* 50623 */ // GIR_Coverage, 1228,
19969 /* 50623 */ GIR_EraseRootFromParent_Done,
19970 /* 50624 */ // Label 1302: @50624
19971 /* 50624 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(50656), // Rule ID 1229 //
19972 /* 50629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
19973 /* 50632 */ // MIs[0] Operand 1
19974 /* 50632 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
19975 /* 50637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19976 /* 50641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
19977 /* 50645 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
19978 /* 50645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
19979 /* 50648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19980 /* 50650 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
19981 /* 50652 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
19982 /* 50654 */ GIR_RootConstrainSelectedInstOperands,
19983 /* 50655 */ // GIR_Coverage, 1229,
19984 /* 50655 */ GIR_EraseRootFromParent_Done,
19985 /* 50656 */ // Label 1303: @50656
19986 /* 50656 */ GIM_Reject,
19987 /* 50657 */ // Label 1296: @50657
19988 /* 50657 */ GIM_Reject,
19989 /* 50658 */ // Label 1287: @50658
19990 /* 50658 */ GIM_Reject,
19991 /* 50659 */ // Label 1265: @50659
19992 /* 50659 */ GIM_Reject,
19993 /* 50660 */ // Label 43: @50660
19994 /* 50660 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(62789),
19995 /* 50671 */ /*GILLT_s32*//*Label 1304*/ GIMT_Encode4(50703),
19996 /* 50675 */ /*GILLT_s64*//*Label 1305*/ GIMT_Encode4(57380), GIMT_Encode4(0),
19997 /* 50683 */ /*GILLT_v2s64*//*Label 1306*/ GIMT_Encode4(62499), GIMT_Encode4(0),
19998 /* 50691 */ /*GILLT_v4s32*//*Label 1307*/ GIMT_Encode4(62573),
19999 /* 50695 */ /*GILLT_v8s16*//*Label 1308*/ GIMT_Encode4(62647),
20000 /* 50699 */ /*GILLT_v16s8*//*Label 1309*/ GIMT_Encode4(62694),
20001 /* 50703 */ // Label 1304: @50703
20002 /* 50703 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(50779), // Rule ID 1745 //
20003 /* 50708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20004 /* 50711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20005 /* 50714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20006 /* 50717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20007 /* 50720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20008 /* 50724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20009 /* 50728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20010 /* 50732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20011 /* 50736 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20012 /* 50740 */ // MIs[1] Operand 1
20013 /* 50740 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20014 /* 50745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20015 /* 50750 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20016 /* 50754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20017 /* 50758 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20018 /* 50762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20019 /* 50764 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20020 /* 50764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20021 /* 50767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20022 /* 50769 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20023 /* 50771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20024 /* 50775 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20025 /* 50777 */ GIR_RootConstrainSelectedInstOperands,
20026 /* 50778 */ // GIR_Coverage, 1745,
20027 /* 50778 */ GIR_EraseRootFromParent_Done,
20028 /* 50779 */ // Label 1311: @50779
20029 /* 50779 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(50855), // Rule ID 1749 //
20030 /* 50784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20031 /* 50787 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20032 /* 50790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20033 /* 50793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20034 /* 50796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20035 /* 50800 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20036 /* 50804 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20037 /* 50808 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20038 /* 50812 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20039 /* 50816 */ // MIs[1] Operand 1
20040 /* 50816 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20041 /* 50821 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20042 /* 50826 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20043 /* 50830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20044 /* 50834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20045 /* 50838 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20046 /* 50840 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20047 /* 50840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20048 /* 50843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20049 /* 50845 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20050 /* 50847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20051 /* 50851 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20052 /* 50853 */ GIR_RootConstrainSelectedInstOperands,
20053 /* 50854 */ // GIR_Coverage, 1749,
20054 /* 50854 */ GIR_EraseRootFromParent_Done,
20055 /* 50855 */ // Label 1312: @50855
20056 /* 50855 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(50931), // Rule ID 1777 //
20057 /* 50860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20058 /* 50863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20059 /* 50866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20060 /* 50869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20061 /* 50872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20062 /* 50876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20063 /* 50880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20064 /* 50884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20065 /* 50888 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20066 /* 50892 */ // MIs[1] Operand 1
20067 /* 50892 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20068 /* 50897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20069 /* 50902 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20070 /* 50906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20071 /* 50910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20072 /* 50914 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20073 /* 50916 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
20074 /* 50916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
20075 /* 50919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20076 /* 50921 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20077 /* 50923 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20078 /* 50927 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20079 /* 50929 */ GIR_RootConstrainSelectedInstOperands,
20080 /* 50930 */ // GIR_Coverage, 1777,
20081 /* 50930 */ GIR_EraseRootFromParent_Done,
20082 /* 50931 */ // Label 1313: @50931
20083 /* 50931 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(51007), // Rule ID 1788 //
20084 /* 50936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20085 /* 50939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20086 /* 50942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20087 /* 50945 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20088 /* 50948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20089 /* 50952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20090 /* 50956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20091 /* 50960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20092 /* 50964 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20093 /* 50968 */ // MIs[1] Operand 1
20094 /* 50968 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20095 /* 50973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20096 /* 50978 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20097 /* 50982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20098 /* 50986 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20099 /* 50990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20100 /* 50992 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
20101 /* 50992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20102 /* 50995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20103 /* 50997 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20104 /* 50999 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20105 /* 51003 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20106 /* 51005 */ GIR_RootConstrainSelectedInstOperands,
20107 /* 51006 */ // GIR_Coverage, 1788,
20108 /* 51006 */ GIR_EraseRootFromParent_Done,
20109 /* 51007 */ // Label 1314: @51007
20110 /* 51007 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(51083), // Rule ID 1801 //
20111 /* 51012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20112 /* 51015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20113 /* 51018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20114 /* 51021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20115 /* 51024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20116 /* 51028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20117 /* 51032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20118 /* 51036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20119 /* 51040 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20120 /* 51044 */ // MIs[1] Operand 1
20121 /* 51044 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20122 /* 51049 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20123 /* 51054 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20124 /* 51058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20125 /* 51062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20126 /* 51066 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20127 /* 51068 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20128 /* 51068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20129 /* 51071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20130 /* 51073 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20131 /* 51075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20132 /* 51079 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20133 /* 51081 */ GIR_RootConstrainSelectedInstOperands,
20134 /* 51082 */ // GIR_Coverage, 1801,
20135 /* 51082 */ GIR_EraseRootFromParent_Done,
20136 /* 51083 */ // Label 1315: @51083
20137 /* 51083 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(51159), // Rule ID 1804 //
20138 /* 51088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20139 /* 51091 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20140 /* 51094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20141 /* 51097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20142 /* 51100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20143 /* 51104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20144 /* 51108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20145 /* 51112 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20146 /* 51116 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20147 /* 51120 */ // MIs[1] Operand 1
20148 /* 51120 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20149 /* 51125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20150 /* 51130 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20151 /* 51134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20152 /* 51138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20153 /* 51142 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20154 /* 51144 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20155 /* 51144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20156 /* 51147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20157 /* 51149 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20158 /* 51151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20159 /* 51155 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20160 /* 51157 */ GIR_RootConstrainSelectedInstOperands,
20161 /* 51158 */ // GIR_Coverage, 1804,
20162 /* 51158 */ GIR_EraseRootFromParent_Done,
20163 /* 51159 */ // Label 1316: @51159
20164 /* 51159 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(51235), // Rule ID 1814 //
20165 /* 51164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20166 /* 51167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20167 /* 51170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20168 /* 51173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20169 /* 51176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20170 /* 51180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20171 /* 51184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20172 /* 51188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20173 /* 51192 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20174 /* 51196 */ // MIs[1] Operand 1
20175 /* 51196 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20176 /* 51201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20177 /* 51206 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20178 /* 51210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20179 /* 51214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20180 /* 51218 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20181 /* 51220 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
20182 /* 51220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
20183 /* 51223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20184 /* 51225 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20185 /* 51227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20186 /* 51231 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20187 /* 51233 */ GIR_RootConstrainSelectedInstOperands,
20188 /* 51234 */ // GIR_Coverage, 1814,
20189 /* 51234 */ GIR_EraseRootFromParent_Done,
20190 /* 51235 */ // Label 1317: @51235
20191 /* 51235 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(51311), // Rule ID 1817 //
20192 /* 51240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20193 /* 51243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20194 /* 51246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20195 /* 51249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20196 /* 51252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20197 /* 51256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20198 /* 51260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20199 /* 51264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20200 /* 51268 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20201 /* 51272 */ // MIs[1] Operand 1
20202 /* 51272 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20203 /* 51277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20204 /* 51282 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20205 /* 51286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20206 /* 51290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20207 /* 51294 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20208 /* 51296 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
20209 /* 51296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20210 /* 51299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20211 /* 51301 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20212 /* 51303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20213 /* 51307 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20214 /* 51309 */ GIR_RootConstrainSelectedInstOperands,
20215 /* 51310 */ // GIR_Coverage, 1817,
20216 /* 51310 */ GIR_EraseRootFromParent_Done,
20217 /* 51311 */ // Label 1318: @51311
20218 /* 51311 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(51387), // Rule ID 2006 //
20219 /* 51316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20220 /* 51319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20221 /* 51322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20222 /* 51325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20223 /* 51328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20224 /* 51332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20225 /* 51336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20226 /* 51340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20227 /* 51344 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20228 /* 51348 */ // MIs[1] Operand 1
20229 /* 51348 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20230 /* 51353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20231 /* 51358 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20232 /* 51362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20233 /* 51366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20234 /* 51370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20235 /* 51372 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20236 /* 51372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
20237 /* 51375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20238 /* 51377 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20239 /* 51379 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20240 /* 51381 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20241 /* 51385 */ GIR_RootConstrainSelectedInstOperands,
20242 /* 51386 */ // GIR_Coverage, 2006,
20243 /* 51386 */ GIR_EraseRootFromParent_Done,
20244 /* 51387 */ // Label 1319: @51387
20245 /* 51387 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(51463), // Rule ID 2009 //
20246 /* 51392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20247 /* 51395 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20248 /* 51398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20249 /* 51401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20250 /* 51404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20251 /* 51408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20252 /* 51412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20253 /* 51416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20254 /* 51420 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20255 /* 51424 */ // MIs[1] Operand 1
20256 /* 51424 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20257 /* 51429 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20258 /* 51434 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20259 /* 51438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20260 /* 51442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20261 /* 51446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20262 /* 51448 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20263 /* 51448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
20264 /* 51451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20265 /* 51453 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20266 /* 51455 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20267 /* 51457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20268 /* 51461 */ GIR_RootConstrainSelectedInstOperands,
20269 /* 51462 */ // GIR_Coverage, 2009,
20270 /* 51462 */ GIR_EraseRootFromParent_Done,
20271 /* 51463 */ // Label 1320: @51463
20272 /* 51463 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(51539), // Rule ID 2355 //
20273 /* 51468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20274 /* 51471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20275 /* 51474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20276 /* 51477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20277 /* 51480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20278 /* 51484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20279 /* 51488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20280 /* 51492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20281 /* 51496 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20282 /* 51500 */ // MIs[1] Operand 1
20283 /* 51500 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20284 /* 51505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20285 /* 51510 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20286 /* 51514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20287 /* 51518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20288 /* 51522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20289 /* 51524 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20290 /* 51524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20291 /* 51527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20292 /* 51529 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20293 /* 51531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20294 /* 51535 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20295 /* 51537 */ GIR_RootConstrainSelectedInstOperands,
20296 /* 51538 */ // GIR_Coverage, 2355,
20297 /* 51538 */ GIR_EraseRootFromParent_Done,
20298 /* 51539 */ // Label 1321: @51539
20299 /* 51539 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(51615), // Rule ID 2359 //
20300 /* 51544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
20301 /* 51547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20302 /* 51550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20303 /* 51553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20304 /* 51556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20305 /* 51560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20306 /* 51564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20307 /* 51568 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20308 /* 51572 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20309 /* 51576 */ // MIs[1] Operand 1
20310 /* 51576 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20311 /* 51581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20312 /* 51586 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20313 /* 51590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20314 /* 51594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20315 /* 51598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20316 /* 51600 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20317 /* 51600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20318 /* 51603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20319 /* 51605 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20320 /* 51607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20321 /* 51611 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20322 /* 51613 */ GIR_RootConstrainSelectedInstOperands,
20323 /* 51614 */ // GIR_Coverage, 2359,
20324 /* 51614 */ GIR_EraseRootFromParent_Done,
20325 /* 51615 */ // Label 1322: @51615
20326 /* 51615 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(51691), // Rule ID 2369 //
20327 /* 51620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20328 /* 51623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20329 /* 51626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20330 /* 51629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20331 /* 51632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20332 /* 51636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20333 /* 51640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20334 /* 51644 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20335 /* 51648 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20336 /* 51652 */ // MIs[1] Operand 1
20337 /* 51652 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20338 /* 51657 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20339 /* 51662 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20340 /* 51666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20341 /* 51670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20342 /* 51674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20343 /* 51676 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20344 /* 51676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20345 /* 51679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20346 /* 51681 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20347 /* 51683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20348 /* 51687 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20349 /* 51689 */ GIR_RootConstrainSelectedInstOperands,
20350 /* 51690 */ // GIR_Coverage, 2369,
20351 /* 51690 */ GIR_EraseRootFromParent_Done,
20352 /* 51691 */ // Label 1323: @51691
20353 /* 51691 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(51767), // Rule ID 2373 //
20354 /* 51696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20355 /* 51699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20356 /* 51702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20357 /* 51705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20358 /* 51708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20359 /* 51712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20360 /* 51716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20361 /* 51720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20362 /* 51724 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20363 /* 51728 */ // MIs[1] Operand 1
20364 /* 51728 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20365 /* 51733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20366 /* 51738 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20367 /* 51742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20368 /* 51746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20369 /* 51750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20370 /* 51752 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
20371 /* 51752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20372 /* 51755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20373 /* 51757 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20374 /* 51759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20375 /* 51763 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20376 /* 51765 */ GIR_RootConstrainSelectedInstOperands,
20377 /* 51766 */ // GIR_Coverage, 2373,
20378 /* 51766 */ GIR_EraseRootFromParent_Done,
20379 /* 51767 */ // Label 1324: @51767
20380 /* 51767 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(51843), // Rule ID 2416 //
20381 /* 51772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20382 /* 51775 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20383 /* 51778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20384 /* 51781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20385 /* 51784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20386 /* 51788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20387 /* 51792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20388 /* 51796 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20389 /* 51800 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20390 /* 51804 */ // MIs[1] Operand 1
20391 /* 51804 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20392 /* 51809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20393 /* 51814 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20394 /* 51818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20395 /* 51822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20396 /* 51826 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20397 /* 51828 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20398 /* 51828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20399 /* 51831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20400 /* 51833 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20401 /* 51835 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20402 /* 51839 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20403 /* 51841 */ GIR_RootConstrainSelectedInstOperands,
20404 /* 51842 */ // GIR_Coverage, 2416,
20405 /* 51842 */ GIR_EraseRootFromParent_Done,
20406 /* 51843 */ // Label 1325: @51843
20407 /* 51843 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(51919), // Rule ID 2419 //
20408 /* 51848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20409 /* 51851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20410 /* 51854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20411 /* 51857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20412 /* 51860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20413 /* 51864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20414 /* 51868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20415 /* 51872 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20416 /* 51876 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20417 /* 51880 */ // MIs[1] Operand 1
20418 /* 51880 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20419 /* 51885 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20420 /* 51890 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20421 /* 51894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20422 /* 51898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20423 /* 51902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20424 /* 51904 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
20425 /* 51904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20426 /* 51907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20427 /* 51909 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20428 /* 51911 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20429 /* 51915 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20430 /* 51917 */ GIR_RootConstrainSelectedInstOperands,
20431 /* 51918 */ // GIR_Coverage, 2419,
20432 /* 51918 */ GIR_EraseRootFromParent_Done,
20433 /* 51919 */ // Label 1326: @51919
20434 /* 51919 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(52017), // Rule ID 1736 //
20435 /* 51924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20436 /* 51927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20437 /* 51930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20438 /* 51933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20439 /* 51936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20440 /* 51940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20441 /* 51944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20442 /* 51948 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20443 /* 51952 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20444 /* 51956 */ // MIs[1] Operand 1
20445 /* 51956 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20446 /* 51961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20447 /* 51966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20448 /* 51971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20449 /* 51975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20450 /* 51979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20451 /* 51981 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20452 /* 51981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20453 /* 51984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20454 /* 51988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20455 /* 51993 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20456 /* 51997 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20457 /* 52001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20458 /* 52003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20459 /* 52006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20460 /* 52008 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20461 /* 52010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20462 /* 52013 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20463 /* 52015 */ GIR_RootConstrainSelectedInstOperands,
20464 /* 52016 */ // GIR_Coverage, 1736,
20465 /* 52016 */ GIR_EraseRootFromParent_Done,
20466 /* 52017 */ // Label 1327: @52017
20467 /* 52017 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(52115), // Rule ID 1737 //
20468 /* 52022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20469 /* 52025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20470 /* 52028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20471 /* 52031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20472 /* 52034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20473 /* 52038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20474 /* 52042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20475 /* 52046 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20476 /* 52050 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20477 /* 52054 */ // MIs[1] Operand 1
20478 /* 52054 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20479 /* 52059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20480 /* 52064 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20481 /* 52069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20482 /* 52073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20483 /* 52077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20484 /* 52079 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20485 /* 52079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20486 /* 52082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20487 /* 52086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20488 /* 52091 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20489 /* 52095 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20490 /* 52099 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20491 /* 52101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20492 /* 52104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20493 /* 52106 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20494 /* 52108 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20495 /* 52111 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20496 /* 52113 */ GIR_RootConstrainSelectedInstOperands,
20497 /* 52114 */ // GIR_Coverage, 1737,
20498 /* 52114 */ GIR_EraseRootFromParent_Done,
20499 /* 52115 */ // Label 1328: @52115
20500 /* 52115 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(52213), // Rule ID 1740 //
20501 /* 52120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20502 /* 52123 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20503 /* 52126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20504 /* 52129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20505 /* 52132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20506 /* 52136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20507 /* 52140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20508 /* 52144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20509 /* 52148 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20510 /* 52152 */ // MIs[1] Operand 1
20511 /* 52152 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20512 /* 52157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20513 /* 52162 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20514 /* 52167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20515 /* 52171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20516 /* 52175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20517 /* 52177 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20518 /* 52177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20519 /* 52180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20520 /* 52184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20521 /* 52189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20522 /* 52193 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20523 /* 52197 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20524 /* 52199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20525 /* 52202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20526 /* 52204 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20527 /* 52206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20528 /* 52209 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20529 /* 52211 */ GIR_RootConstrainSelectedInstOperands,
20530 /* 52212 */ // GIR_Coverage, 1740,
20531 /* 52212 */ GIR_EraseRootFromParent_Done,
20532 /* 52213 */ // Label 1329: @52213
20533 /* 52213 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(52311), // Rule ID 1741 //
20534 /* 52218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20535 /* 52221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20536 /* 52224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20537 /* 52227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20538 /* 52230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20539 /* 52234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20540 /* 52238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20541 /* 52242 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20542 /* 52246 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20543 /* 52250 */ // MIs[1] Operand 1
20544 /* 52250 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20545 /* 52255 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20546 /* 52260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20547 /* 52265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20548 /* 52269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20549 /* 52273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20550 /* 52275 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20551 /* 52275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20552 /* 52278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20553 /* 52282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20554 /* 52287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20555 /* 52291 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20556 /* 52295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20557 /* 52297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20558 /* 52300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20559 /* 52302 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20560 /* 52304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20561 /* 52307 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20562 /* 52309 */ GIR_RootConstrainSelectedInstOperands,
20563 /* 52310 */ // GIR_Coverage, 1741,
20564 /* 52310 */ GIR_EraseRootFromParent_Done,
20565 /* 52311 */ // Label 1330: @52311
20566 /* 52311 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(52409), // Rule ID 1744 //
20567 /* 52316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20568 /* 52319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20569 /* 52322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20570 /* 52325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20571 /* 52328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20572 /* 52332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20573 /* 52336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20574 /* 52340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20575 /* 52344 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20576 /* 52348 */ // MIs[1] Operand 1
20577 /* 52348 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20578 /* 52353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20579 /* 52358 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20580 /* 52363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20581 /* 52367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20582 /* 52371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20583 /* 52373 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20584 /* 52373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20585 /* 52376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20586 /* 52380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20587 /* 52385 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20588 /* 52389 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20589 /* 52393 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20590 /* 52395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20591 /* 52398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20592 /* 52400 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20593 /* 52402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20594 /* 52405 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20595 /* 52407 */ GIR_RootConstrainSelectedInstOperands,
20596 /* 52408 */ // GIR_Coverage, 1744,
20597 /* 52408 */ GIR_EraseRootFromParent_Done,
20598 /* 52409 */ // Label 1331: @52409
20599 /* 52409 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(52507), // Rule ID 1747 //
20600 /* 52414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20601 /* 52417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20602 /* 52420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20603 /* 52423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20604 /* 52426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20605 /* 52430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20606 /* 52434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20607 /* 52438 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20608 /* 52442 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20609 /* 52446 */ // MIs[1] Operand 1
20610 /* 52446 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20611 /* 52451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20612 /* 52456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20613 /* 52461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20614 /* 52465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20615 /* 52469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20616 /* 52471 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20617 /* 52471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20618 /* 52474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20619 /* 52478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20620 /* 52483 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20621 /* 52487 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20622 /* 52491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20623 /* 52493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20624 /* 52496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20625 /* 52498 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20626 /* 52500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20627 /* 52503 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20628 /* 52505 */ GIR_RootConstrainSelectedInstOperands,
20629 /* 52506 */ // GIR_Coverage, 1747,
20630 /* 52506 */ GIR_EraseRootFromParent_Done,
20631 /* 52507 */ // Label 1332: @52507
20632 /* 52507 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(52605), // Rule ID 1758 //
20633 /* 52512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20634 /* 52515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20635 /* 52518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20636 /* 52521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20637 /* 52524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20638 /* 52528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20639 /* 52532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20640 /* 52536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20641 /* 52540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20642 /* 52544 */ // MIs[1] Operand 1
20643 /* 52544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20644 /* 52549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20645 /* 52554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20646 /* 52559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20647 /* 52563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20648 /* 52567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20649 /* 52569 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20650 /* 52569 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20651 /* 52572 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20652 /* 52576 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20653 /* 52581 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20654 /* 52585 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20655 /* 52589 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20656 /* 52591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20657 /* 52594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20658 /* 52596 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20659 /* 52598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20660 /* 52601 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20661 /* 52603 */ GIR_RootConstrainSelectedInstOperands,
20662 /* 52604 */ // GIR_Coverage, 1758,
20663 /* 52604 */ GIR_EraseRootFromParent_Done,
20664 /* 52605 */ // Label 1333: @52605
20665 /* 52605 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(52703), // Rule ID 1759 //
20666 /* 52610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20667 /* 52613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20668 /* 52616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20669 /* 52619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20670 /* 52622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20671 /* 52626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20672 /* 52630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20673 /* 52634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20674 /* 52638 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20675 /* 52642 */ // MIs[1] Operand 1
20676 /* 52642 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20677 /* 52647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20678 /* 52652 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20679 /* 52657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20680 /* 52661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20681 /* 52665 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20682 /* 52667 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20683 /* 52667 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20684 /* 52670 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20685 /* 52674 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20686 /* 52679 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20687 /* 52683 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20688 /* 52687 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20689 /* 52689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20690 /* 52692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20691 /* 52694 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20692 /* 52696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20693 /* 52699 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20694 /* 52701 */ GIR_RootConstrainSelectedInstOperands,
20695 /* 52702 */ // GIR_Coverage, 1759,
20696 /* 52702 */ GIR_EraseRootFromParent_Done,
20697 /* 52703 */ // Label 1334: @52703
20698 /* 52703 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(52801), // Rule ID 1762 //
20699 /* 52708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20700 /* 52711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20701 /* 52714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20702 /* 52717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20703 /* 52720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20704 /* 52724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20705 /* 52728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20706 /* 52732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20707 /* 52736 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20708 /* 52740 */ // MIs[1] Operand 1
20709 /* 52740 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20710 /* 52745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20711 /* 52750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20712 /* 52755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20713 /* 52759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20714 /* 52763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20715 /* 52765 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20716 /* 52765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20717 /* 52768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
20718 /* 52772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20719 /* 52777 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20720 /* 52781 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20721 /* 52785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20722 /* 52787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20723 /* 52790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20724 /* 52792 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20725 /* 52794 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20726 /* 52797 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20727 /* 52799 */ GIR_RootConstrainSelectedInstOperands,
20728 /* 52800 */ // GIR_Coverage, 1762,
20729 /* 52800 */ GIR_EraseRootFromParent_Done,
20730 /* 52801 */ // Label 1335: @52801
20731 /* 52801 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(52899), // Rule ID 1763 //
20732 /* 52806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20733 /* 52809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20734 /* 52812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20735 /* 52815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20736 /* 52818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20737 /* 52822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20738 /* 52826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20739 /* 52830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20740 /* 52834 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20741 /* 52838 */ // MIs[1] Operand 1
20742 /* 52838 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20743 /* 52843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20744 /* 52848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20745 /* 52853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20746 /* 52857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20747 /* 52861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20748 /* 52863 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
20749 /* 52863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20750 /* 52866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
20751 /* 52870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20752 /* 52875 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20753 /* 52879 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20754 /* 52883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20755 /* 52885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
20756 /* 52888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20757 /* 52890 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20758 /* 52892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20759 /* 52895 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20760 /* 52897 */ GIR_RootConstrainSelectedInstOperands,
20761 /* 52898 */ // GIR_Coverage, 1763,
20762 /* 52898 */ GIR_EraseRootFromParent_Done,
20763 /* 52899 */ // Label 1336: @52899
20764 /* 52899 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(52997), // Rule ID 1776 //
20765 /* 52904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20766 /* 52907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20767 /* 52910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20768 /* 52913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20769 /* 52916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20770 /* 52920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20771 /* 52924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20772 /* 52928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20773 /* 52932 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20774 /* 52936 */ // MIs[1] Operand 1
20775 /* 52936 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20776 /* 52941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20777 /* 52946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20778 /* 52951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20779 /* 52955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20780 /* 52959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20781 /* 52961 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20782 /* 52961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20783 /* 52964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20784 /* 52968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20785 /* 52973 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20786 /* 52977 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20787 /* 52981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20788 /* 52983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
20789 /* 52986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20790 /* 52988 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20791 /* 52990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20792 /* 52993 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20793 /* 52995 */ GIR_RootConstrainSelectedInstOperands,
20794 /* 52996 */ // GIR_Coverage, 1776,
20795 /* 52996 */ GIR_EraseRootFromParent_Done,
20796 /* 52997 */ // Label 1337: @52997
20797 /* 52997 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(53095), // Rule ID 1786 //
20798 /* 53002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20799 /* 53005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20800 /* 53008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20801 /* 53011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20802 /* 53014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20803 /* 53018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20804 /* 53022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20805 /* 53026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20806 /* 53030 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20807 /* 53034 */ // MIs[1] Operand 1
20808 /* 53034 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20809 /* 53039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20810 /* 53044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20811 /* 53049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20812 /* 53053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20813 /* 53057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20814 /* 53059 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
20815 /* 53059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
20816 /* 53062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
20817 /* 53066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20818 /* 53071 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20819 /* 53075 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20820 /* 53079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20821 /* 53081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20822 /* 53084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20823 /* 53086 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20824 /* 53088 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20825 /* 53091 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20826 /* 53093 */ GIR_RootConstrainSelectedInstOperands,
20827 /* 53094 */ // GIR_Coverage, 1786,
20828 /* 53094 */ GIR_EraseRootFromParent_Done,
20829 /* 53095 */ // Label 1338: @53095
20830 /* 53095 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(53193), // Rule ID 1792 //
20831 /* 53100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20832 /* 53103 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20833 /* 53106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20834 /* 53109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20835 /* 53112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20836 /* 53116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20837 /* 53120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20838 /* 53124 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20839 /* 53128 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20840 /* 53132 */ // MIs[1] Operand 1
20841 /* 53132 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20842 /* 53137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20843 /* 53142 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20844 /* 53147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20845 /* 53151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20846 /* 53155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20847 /* 53157 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20848 /* 53157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20849 /* 53160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20850 /* 53164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20851 /* 53169 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20852 /* 53173 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20853 /* 53177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20854 /* 53179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20855 /* 53182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20856 /* 53184 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20857 /* 53186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20858 /* 53189 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20859 /* 53191 */ GIR_RootConstrainSelectedInstOperands,
20860 /* 53192 */ // GIR_Coverage, 1792,
20861 /* 53192 */ GIR_EraseRootFromParent_Done,
20862 /* 53193 */ // Label 1339: @53193
20863 /* 53193 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(53291), // Rule ID 1793 //
20864 /* 53198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20865 /* 53201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20866 /* 53204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20867 /* 53207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20868 /* 53210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20869 /* 53214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20870 /* 53218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20871 /* 53222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20872 /* 53226 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20873 /* 53230 */ // MIs[1] Operand 1
20874 /* 53230 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20875 /* 53235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20876 /* 53240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20877 /* 53245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20878 /* 53249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20879 /* 53253 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20880 /* 53255 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20881 /* 53255 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20882 /* 53258 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20883 /* 53262 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20884 /* 53267 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20885 /* 53271 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20886 /* 53275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20887 /* 53277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20888 /* 53280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20889 /* 53282 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20890 /* 53284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20891 /* 53287 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20892 /* 53289 */ GIR_RootConstrainSelectedInstOperands,
20893 /* 53290 */ // GIR_Coverage, 1793,
20894 /* 53290 */ GIR_EraseRootFromParent_Done,
20895 /* 53291 */ // Label 1340: @53291
20896 /* 53291 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(53389), // Rule ID 1796 //
20897 /* 53296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20898 /* 53299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20899 /* 53302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20900 /* 53305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20901 /* 53308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20902 /* 53312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20903 /* 53316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20904 /* 53320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20905 /* 53324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20906 /* 53328 */ // MIs[1] Operand 1
20907 /* 53328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20908 /* 53333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20909 /* 53338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20910 /* 53343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20911 /* 53347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20912 /* 53351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20913 /* 53353 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20914 /* 53353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20915 /* 53356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
20916 /* 53360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20917 /* 53365 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20918 /* 53369 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20919 /* 53373 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20920 /* 53375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20921 /* 53378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20922 /* 53380 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20923 /* 53382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20924 /* 53385 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20925 /* 53387 */ GIR_RootConstrainSelectedInstOperands,
20926 /* 53388 */ // GIR_Coverage, 1796,
20927 /* 53388 */ GIR_EraseRootFromParent_Done,
20928 /* 53389 */ // Label 1341: @53389
20929 /* 53389 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(53487), // Rule ID 1797 //
20930 /* 53394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20931 /* 53397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20932 /* 53400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20933 /* 53403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20934 /* 53406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20935 /* 53410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20936 /* 53414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20937 /* 53418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20938 /* 53422 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20939 /* 53426 */ // MIs[1] Operand 1
20940 /* 53426 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20941 /* 53431 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20942 /* 53436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20943 /* 53441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20944 /* 53445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20945 /* 53449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20946 /* 53451 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20947 /* 53451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20948 /* 53454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
20949 /* 53458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20950 /* 53463 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20951 /* 53467 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20952 /* 53471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20953 /* 53473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20954 /* 53476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20955 /* 53478 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20956 /* 53480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20957 /* 53483 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20958 /* 53485 */ GIR_RootConstrainSelectedInstOperands,
20959 /* 53486 */ // GIR_Coverage, 1797,
20960 /* 53486 */ GIR_EraseRootFromParent_Done,
20961 /* 53487 */ // Label 1342: @53487
20962 /* 53487 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(53585), // Rule ID 1800 //
20963 /* 53492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20964 /* 53495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20965 /* 53498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20966 /* 53501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20967 /* 53504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20968 /* 53508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20969 /* 53512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20970 /* 53516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20971 /* 53520 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20972 /* 53524 */ // MIs[1] Operand 1
20973 /* 53524 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20974 /* 53529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20975 /* 53534 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20976 /* 53539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20977 /* 53543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20978 /* 53547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20979 /* 53549 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20980 /* 53549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20981 /* 53552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
20982 /* 53556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20983 /* 53561 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20984 /* 53565 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20985 /* 53569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20986 /* 53571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
20987 /* 53574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20988 /* 53576 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20989 /* 53578 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20990 /* 53581 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20991 /* 53583 */ GIR_RootConstrainSelectedInstOperands,
20992 /* 53584 */ // GIR_Coverage, 1800,
20993 /* 53584 */ GIR_EraseRootFromParent_Done,
20994 /* 53585 */ // Label 1343: @53585
20995 /* 53585 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(53683), // Rule ID 1802 //
20996 /* 53590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20997 /* 53593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20998 /* 53596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20999 /* 53599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21000 /* 53602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21001 /* 53606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21002 /* 53610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21003 /* 53614 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21004 /* 53618 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21005 /* 53622 */ // MIs[1] Operand 1
21006 /* 53622 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21007 /* 53627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21008 /* 53632 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21009 /* 53637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21010 /* 53641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21011 /* 53645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21012 /* 53647 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21013 /* 53647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21014 /* 53650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21015 /* 53654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21016 /* 53659 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21017 /* 53663 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21018 /* 53667 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21019 /* 53669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
21020 /* 53672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21021 /* 53674 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21022 /* 53676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21023 /* 53679 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21024 /* 53681 */ GIR_RootConstrainSelectedInstOperands,
21025 /* 53682 */ // GIR_Coverage, 1802,
21026 /* 53682 */ GIR_EraseRootFromParent_Done,
21027 /* 53683 */ // Label 1344: @53683
21028 /* 53683 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(53781), // Rule ID 1805 //
21029 /* 53688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21030 /* 53691 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21031 /* 53694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21032 /* 53697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21033 /* 53700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21034 /* 53704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21035 /* 53708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21036 /* 53712 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21037 /* 53716 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21038 /* 53720 */ // MIs[1] Operand 1
21039 /* 53720 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21040 /* 53725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21041 /* 53730 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21042 /* 53735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21043 /* 53739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21044 /* 53743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21045 /* 53745 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21046 /* 53745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21047 /* 53748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21048 /* 53752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21049 /* 53757 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21050 /* 53761 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21051 /* 53765 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21052 /* 53767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21053 /* 53770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21054 /* 53772 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21055 /* 53774 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21056 /* 53777 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21057 /* 53779 */ GIR_RootConstrainSelectedInstOperands,
21058 /* 53780 */ // GIR_Coverage, 1805,
21059 /* 53780 */ GIR_EraseRootFromParent_Done,
21060 /* 53781 */ // Label 1345: @53781
21061 /* 53781 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(53879), // Rule ID 1806 //
21062 /* 53786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21063 /* 53789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21064 /* 53792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21065 /* 53795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21066 /* 53798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21067 /* 53802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21068 /* 53806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21069 /* 53810 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21070 /* 53814 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21071 /* 53818 */ // MIs[1] Operand 1
21072 /* 53818 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21073 /* 53823 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21074 /* 53828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21075 /* 53833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21076 /* 53837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21077 /* 53841 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21078 /* 53843 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21079 /* 53843 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21080 /* 53846 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21081 /* 53850 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21082 /* 53855 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21083 /* 53859 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21084 /* 53863 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21085 /* 53865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21086 /* 53868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21087 /* 53870 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21088 /* 53872 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21089 /* 53875 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21090 /* 53877 */ GIR_RootConstrainSelectedInstOperands,
21091 /* 53878 */ // GIR_Coverage, 1806,
21092 /* 53878 */ GIR_EraseRootFromParent_Done,
21093 /* 53879 */ // Label 1346: @53879
21094 /* 53879 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(53977), // Rule ID 1809 //
21095 /* 53884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21096 /* 53887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21097 /* 53890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21098 /* 53893 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21099 /* 53896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21100 /* 53900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21101 /* 53904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21102 /* 53908 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21103 /* 53912 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21104 /* 53916 */ // MIs[1] Operand 1
21105 /* 53916 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21106 /* 53921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21107 /* 53926 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21108 /* 53931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21109 /* 53935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21110 /* 53939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21111 /* 53941 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
21112 /* 53941 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21113 /* 53944 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21114 /* 53948 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21115 /* 53953 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21116 /* 53957 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21117 /* 53961 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21118 /* 53963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21119 /* 53966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21120 /* 53968 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21121 /* 53970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21122 /* 53973 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21123 /* 53975 */ GIR_RootConstrainSelectedInstOperands,
21124 /* 53976 */ // GIR_Coverage, 1809,
21125 /* 53976 */ GIR_EraseRootFromParent_Done,
21126 /* 53977 */ // Label 1347: @53977
21127 /* 53977 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(54075), // Rule ID 1810 //
21128 /* 53982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21129 /* 53985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21130 /* 53988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21131 /* 53991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21132 /* 53994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21133 /* 53998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21134 /* 54002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21135 /* 54006 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21136 /* 54010 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21137 /* 54014 */ // MIs[1] Operand 1
21138 /* 54014 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21139 /* 54019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21140 /* 54024 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21141 /* 54029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21142 /* 54033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21143 /* 54037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21144 /* 54039 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
21145 /* 54039 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21146 /* 54042 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21147 /* 54046 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21148 /* 54051 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21149 /* 54055 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21150 /* 54059 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21151 /* 54061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
21152 /* 54064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21153 /* 54066 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21154 /* 54068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21155 /* 54071 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21156 /* 54073 */ GIR_RootConstrainSelectedInstOperands,
21157 /* 54074 */ // GIR_Coverage, 1810,
21158 /* 54074 */ GIR_EraseRootFromParent_Done,
21159 /* 54075 */ // Label 1348: @54075
21160 /* 54075 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(54173), // Rule ID 1813 //
21161 /* 54080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21162 /* 54083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21163 /* 54086 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21164 /* 54089 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21165 /* 54092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21166 /* 54096 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21167 /* 54100 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21168 /* 54104 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21169 /* 54108 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21170 /* 54112 */ // MIs[1] Operand 1
21171 /* 54112 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21172 /* 54117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21173 /* 54122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21174 /* 54127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21175 /* 54131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21176 /* 54135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21177 /* 54137 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21178 /* 54137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21179 /* 54140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21180 /* 54144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21181 /* 54149 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21182 /* 54153 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21183 /* 54157 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21184 /* 54159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
21185 /* 54162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21186 /* 54164 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21187 /* 54166 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21188 /* 54169 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21189 /* 54171 */ GIR_RootConstrainSelectedInstOperands,
21190 /* 54172 */ // GIR_Coverage, 1813,
21191 /* 54172 */ GIR_EraseRootFromParent_Done,
21192 /* 54173 */ // Label 1349: @54173
21193 /* 54173 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(54271), // Rule ID 1815 //
21194 /* 54178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21195 /* 54181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21196 /* 54184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21197 /* 54187 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21198 /* 54190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21199 /* 54194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21200 /* 54198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21201 /* 54202 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21202 /* 54206 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21203 /* 54210 */ // MIs[1] Operand 1
21204 /* 54210 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21205 /* 54215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21206 /* 54220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21207 /* 54225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21208 /* 54229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21209 /* 54233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21210 /* 54235 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
21211 /* 54235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21212 /* 54238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21213 /* 54242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21214 /* 54247 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21215 /* 54251 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21216 /* 54255 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21217 /* 54257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
21218 /* 54260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21219 /* 54262 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21220 /* 54264 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21221 /* 54267 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21222 /* 54269 */ GIR_RootConstrainSelectedInstOperands,
21223 /* 54270 */ // GIR_Coverage, 1815,
21224 /* 54270 */ GIR_EraseRootFromParent_Done,
21225 /* 54271 */ // Label 1350: @54271
21226 /* 54271 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(54352), // Rule ID 1998 //
21227 /* 54276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21228 /* 54279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21229 /* 54282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21230 /* 54285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21231 /* 54288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21232 /* 54292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21233 /* 54296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21234 /* 54300 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21235 /* 54304 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21236 /* 54308 */ // MIs[1] Operand 1
21237 /* 54308 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21238 /* 54313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21239 /* 54318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21240 /* 54323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21241 /* 54327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21242 /* 54331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21243 /* 54333 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
21244 /* 54333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
21245 /* 54336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21246 /* 54338 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21247 /* 54340 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21248 /* 54342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21249 /* 54346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21250 /* 54350 */ GIR_RootConstrainSelectedInstOperands,
21251 /* 54351 */ // GIR_Coverage, 1998,
21252 /* 54351 */ GIR_EraseRootFromParent_Done,
21253 /* 54352 */ // Label 1351: @54352
21254 /* 54352 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(54433), // Rule ID 1999 //
21255 /* 54357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21256 /* 54360 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21257 /* 54363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21258 /* 54366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21259 /* 54369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21260 /* 54373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21261 /* 54377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21262 /* 54381 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21263 /* 54385 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21264 /* 54389 */ // MIs[1] Operand 1
21265 /* 54389 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
21266 /* 54394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21267 /* 54399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21268 /* 54404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21269 /* 54408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21270 /* 54412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21271 /* 54414 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21272 /* 54414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
21273 /* 54417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21274 /* 54419 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21275 /* 54421 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21276 /* 54423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21277 /* 54427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21278 /* 54431 */ GIR_RootConstrainSelectedInstOperands,
21279 /* 54432 */ // GIR_Coverage, 1999,
21280 /* 54432 */ GIR_EraseRootFromParent_Done,
21281 /* 54433 */ // Label 1352: @54433
21282 /* 54433 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(54514), // Rule ID 2000 //
21283 /* 54438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21284 /* 54441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21285 /* 54444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21286 /* 54447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21287 /* 54450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21288 /* 54454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21289 /* 54458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21290 /* 54462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21291 /* 54466 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21292 /* 54470 */ // MIs[1] Operand 1
21293 /* 54470 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21294 /* 54475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21295 /* 54480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21296 /* 54485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21297 /* 54489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21298 /* 54493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21299 /* 54495 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
21300 /* 54495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
21301 /* 54498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21302 /* 54500 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21303 /* 54502 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21304 /* 54504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21305 /* 54508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21306 /* 54512 */ GIR_RootConstrainSelectedInstOperands,
21307 /* 54513 */ // GIR_Coverage, 2000,
21308 /* 54513 */ GIR_EraseRootFromParent_Done,
21309 /* 54514 */ // Label 1353: @54514
21310 /* 54514 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(54595), // Rule ID 2001 //
21311 /* 54519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21312 /* 54522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21313 /* 54525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21314 /* 54528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21315 /* 54531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21316 /* 54535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21317 /* 54539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21318 /* 54543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21319 /* 54547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21320 /* 54551 */ // MIs[1] Operand 1
21321 /* 54551 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
21322 /* 54556 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21323 /* 54561 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21324 /* 54566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21325 /* 54570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21326 /* 54574 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21327 /* 54576 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21328 /* 54576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
21329 /* 54579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21330 /* 54581 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21331 /* 54583 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21332 /* 54585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21333 /* 54589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21334 /* 54593 */ GIR_RootConstrainSelectedInstOperands,
21335 /* 54594 */ // GIR_Coverage, 2001,
21336 /* 54594 */ GIR_EraseRootFromParent_Done,
21337 /* 54595 */ // Label 1354: @54595
21338 /* 54595 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(54676), // Rule ID 2003 //
21339 /* 54600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21340 /* 54603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21341 /* 54606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21342 /* 54609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21343 /* 54612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21344 /* 54616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21345 /* 54620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21346 /* 54624 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21347 /* 54628 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21348 /* 54632 */ // MIs[1] Operand 1
21349 /* 54632 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21350 /* 54637 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21351 /* 54642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21352 /* 54647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21353 /* 54651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21354 /* 54655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21355 /* 54657 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21356 /* 54657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
21357 /* 54660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21358 /* 54662 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21359 /* 54664 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21360 /* 54666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21361 /* 54670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21362 /* 54674 */ GIR_RootConstrainSelectedInstOperands,
21363 /* 54675 */ // GIR_Coverage, 2003,
21364 /* 54675 */ GIR_EraseRootFromParent_Done,
21365 /* 54676 */ // Label 1355: @54676
21366 /* 54676 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(54757), // Rule ID 2004 //
21367 /* 54681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21368 /* 54684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21369 /* 54687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21370 /* 54690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21371 /* 54693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21372 /* 54697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21373 /* 54701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21374 /* 54705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21375 /* 54709 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21376 /* 54713 */ // MIs[1] Operand 1
21377 /* 54713 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21378 /* 54718 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21379 /* 54723 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21380 /* 54728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21381 /* 54732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21382 /* 54736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21383 /* 54738 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21384 /* 54738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
21385 /* 54741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21386 /* 54743 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21387 /* 54745 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21388 /* 54747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21389 /* 54751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21390 /* 54755 */ GIR_RootConstrainSelectedInstOperands,
21391 /* 54756 */ // GIR_Coverage, 2004,
21392 /* 54756 */ GIR_EraseRootFromParent_Done,
21393 /* 54757 */ // Label 1356: @54757
21394 /* 54757 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(54838), // Rule ID 2005 //
21395 /* 54762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21396 /* 54765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21397 /* 54768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21398 /* 54771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21399 /* 54774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21400 /* 54778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21401 /* 54782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21402 /* 54786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21403 /* 54790 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21404 /* 54794 */ // MIs[1] Operand 1
21405 /* 54794 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21406 /* 54799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21407 /* 54804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21408 /* 54809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21409 /* 54813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21410 /* 54817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21411 /* 54819 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21412 /* 54819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
21413 /* 54822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21414 /* 54824 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21415 /* 54826 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21416 /* 54828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21417 /* 54832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21418 /* 54836 */ GIR_RootConstrainSelectedInstOperands,
21419 /* 54837 */ // GIR_Coverage, 2005,
21420 /* 54837 */ GIR_EraseRootFromParent_Done,
21421 /* 54838 */ // Label 1357: @54838
21422 /* 54838 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(54919), // Rule ID 2008 //
21423 /* 54843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
21424 /* 54846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21425 /* 54849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21426 /* 54852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21427 /* 54855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21428 /* 54859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21429 /* 54863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21430 /* 54867 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21431 /* 54871 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21432 /* 54875 */ // MIs[1] Operand 1
21433 /* 54875 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21434 /* 54880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21435 /* 54885 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21436 /* 54890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21437 /* 54894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
21438 /* 54898 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21439 /* 54900 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
21440 /* 54900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
21441 /* 54903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
21442 /* 54905 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
21443 /* 54907 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
21444 /* 54909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
21445 /* 54913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
21446 /* 54917 */ GIR_RootConstrainSelectedInstOperands,
21447 /* 54918 */ // GIR_Coverage, 2008,
21448 /* 54918 */ GIR_EraseRootFromParent_Done,
21449 /* 54919 */ // Label 1358: @54919
21450 /* 54919 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(55017), // Rule ID 2346 //
21451 /* 54924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21452 /* 54927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21453 /* 54930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21454 /* 54933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21455 /* 54936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21456 /* 54940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21457 /* 54944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21458 /* 54948 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21459 /* 54952 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21460 /* 54956 */ // MIs[1] Operand 1
21461 /* 54956 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21462 /* 54961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21463 /* 54966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21464 /* 54971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21465 /* 54975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21466 /* 54979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21467 /* 54981 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21468 /* 54981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21469 /* 54984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21470 /* 54988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21471 /* 54993 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21472 /* 54997 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21473 /* 55001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21474 /* 55003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21475 /* 55006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21476 /* 55008 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21477 /* 55010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21478 /* 55013 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21479 /* 55015 */ GIR_RootConstrainSelectedInstOperands,
21480 /* 55016 */ // GIR_Coverage, 2346,
21481 /* 55016 */ GIR_EraseRootFromParent_Done,
21482 /* 55017 */ // Label 1359: @55017
21483 /* 55017 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(55115), // Rule ID 2347 //
21484 /* 55022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21485 /* 55025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21486 /* 55028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21487 /* 55031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21488 /* 55034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21489 /* 55038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21490 /* 55042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21491 /* 55046 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21492 /* 55050 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21493 /* 55054 */ // MIs[1] Operand 1
21494 /* 55054 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21495 /* 55059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21496 /* 55064 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21497 /* 55069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21498 /* 55073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21499 /* 55077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21500 /* 55079 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21501 /* 55079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21502 /* 55082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21503 /* 55086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21504 /* 55091 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21505 /* 55095 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21506 /* 55099 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21507 /* 55101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21508 /* 55104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21509 /* 55106 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21510 /* 55108 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21511 /* 55111 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21512 /* 55113 */ GIR_RootConstrainSelectedInstOperands,
21513 /* 55114 */ // GIR_Coverage, 2347,
21514 /* 55114 */ GIR_EraseRootFromParent_Done,
21515 /* 55115 */ // Label 1360: @55115
21516 /* 55115 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(55213), // Rule ID 2350 //
21517 /* 55120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21518 /* 55123 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21519 /* 55126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21520 /* 55129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21521 /* 55132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21522 /* 55136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21523 /* 55140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21524 /* 55144 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21525 /* 55148 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21526 /* 55152 */ // MIs[1] Operand 1
21527 /* 55152 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21528 /* 55157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21529 /* 55162 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21530 /* 55167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21531 /* 55171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21532 /* 55175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21533 /* 55177 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21534 /* 55177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21535 /* 55180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21536 /* 55184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21537 /* 55189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21538 /* 55193 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21539 /* 55197 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21540 /* 55199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21541 /* 55202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21542 /* 55204 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21543 /* 55206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21544 /* 55209 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21545 /* 55211 */ GIR_RootConstrainSelectedInstOperands,
21546 /* 55212 */ // GIR_Coverage, 2350,
21547 /* 55212 */ GIR_EraseRootFromParent_Done,
21548 /* 55213 */ // Label 1361: @55213
21549 /* 55213 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(55311), // Rule ID 2351 //
21550 /* 55218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21551 /* 55221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21552 /* 55224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21553 /* 55227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21554 /* 55230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21555 /* 55234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21556 /* 55238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21557 /* 55242 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21558 /* 55246 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21559 /* 55250 */ // MIs[1] Operand 1
21560 /* 55250 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21561 /* 55255 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21562 /* 55260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21563 /* 55265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21564 /* 55269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21565 /* 55273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21566 /* 55275 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21567 /* 55275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21568 /* 55278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21569 /* 55282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21570 /* 55287 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21571 /* 55291 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21572 /* 55295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21573 /* 55297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21574 /* 55300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21575 /* 55302 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21576 /* 55304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21577 /* 55307 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21578 /* 55309 */ GIR_RootConstrainSelectedInstOperands,
21579 /* 55310 */ // GIR_Coverage, 2351,
21580 /* 55310 */ GIR_EraseRootFromParent_Done,
21581 /* 55311 */ // Label 1362: @55311
21582 /* 55311 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(55409), // Rule ID 2354 //
21583 /* 55316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21584 /* 55319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21585 /* 55322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21586 /* 55325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21587 /* 55328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21588 /* 55332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21589 /* 55336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21590 /* 55340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21591 /* 55344 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21592 /* 55348 */ // MIs[1] Operand 1
21593 /* 55348 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21594 /* 55353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21595 /* 55358 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21596 /* 55363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21597 /* 55367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21598 /* 55371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21599 /* 55373 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21600 /* 55373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21601 /* 55376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21602 /* 55380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21603 /* 55385 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21604 /* 55389 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21605 /* 55393 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21606 /* 55395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21607 /* 55398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21608 /* 55400 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21609 /* 55402 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21610 /* 55405 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21611 /* 55407 */ GIR_RootConstrainSelectedInstOperands,
21612 /* 55408 */ // GIR_Coverage, 2354,
21613 /* 55408 */ GIR_EraseRootFromParent_Done,
21614 /* 55409 */ // Label 1363: @55409
21615 /* 55409 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(55507), // Rule ID 2357 //
21616 /* 55414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
21617 /* 55417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21618 /* 55420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21619 /* 55423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21620 /* 55426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21621 /* 55430 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21622 /* 55434 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21623 /* 55438 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21624 /* 55442 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21625 /* 55446 */ // MIs[1] Operand 1
21626 /* 55446 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21627 /* 55451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21628 /* 55456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21629 /* 55461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21630 /* 55465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21631 /* 55469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21632 /* 55471 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21633 /* 55471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21634 /* 55474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21635 /* 55478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21636 /* 55483 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21637 /* 55487 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21638 /* 55491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21639 /* 55493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21640 /* 55496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21641 /* 55498 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21642 /* 55500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21643 /* 55503 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21644 /* 55505 */ GIR_RootConstrainSelectedInstOperands,
21645 /* 55506 */ // GIR_Coverage, 2357,
21646 /* 55506 */ GIR_EraseRootFromParent_Done,
21647 /* 55507 */ // Label 1364: @55507
21648 /* 55507 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(55605), // Rule ID 2360 //
21649 /* 55512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21650 /* 55515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21651 /* 55518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21652 /* 55521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21653 /* 55524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21654 /* 55528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21655 /* 55532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21656 /* 55536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21657 /* 55540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21658 /* 55544 */ // MIs[1] Operand 1
21659 /* 55544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21660 /* 55549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21661 /* 55554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21662 /* 55559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21663 /* 55563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21664 /* 55567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21665 /* 55569 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21666 /* 55569 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21667 /* 55572 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21668 /* 55576 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21669 /* 55581 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21670 /* 55585 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21671 /* 55589 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21672 /* 55591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21673 /* 55594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21674 /* 55596 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21675 /* 55598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21676 /* 55601 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21677 /* 55603 */ GIR_RootConstrainSelectedInstOperands,
21678 /* 55604 */ // GIR_Coverage, 2360,
21679 /* 55604 */ GIR_EraseRootFromParent_Done,
21680 /* 55605 */ // Label 1365: @55605
21681 /* 55605 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(55703), // Rule ID 2361 //
21682 /* 55610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21683 /* 55613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21684 /* 55616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21685 /* 55619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21686 /* 55622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21687 /* 55626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21688 /* 55630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21689 /* 55634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21690 /* 55638 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21691 /* 55642 */ // MIs[1] Operand 1
21692 /* 55642 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21693 /* 55647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21694 /* 55652 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21695 /* 55657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21696 /* 55661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21697 /* 55665 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21698 /* 55667 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21699 /* 55667 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21700 /* 55670 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21701 /* 55674 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21702 /* 55679 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21703 /* 55683 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21704 /* 55687 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21705 /* 55689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21706 /* 55692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21707 /* 55694 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21708 /* 55696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21709 /* 55699 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21710 /* 55701 */ GIR_RootConstrainSelectedInstOperands,
21711 /* 55702 */ // GIR_Coverage, 2361,
21712 /* 55702 */ GIR_EraseRootFromParent_Done,
21713 /* 55703 */ // Label 1366: @55703
21714 /* 55703 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(55801), // Rule ID 2364 //
21715 /* 55708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21716 /* 55711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21717 /* 55714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21718 /* 55717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21719 /* 55720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21720 /* 55724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21721 /* 55728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21722 /* 55732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21723 /* 55736 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21724 /* 55740 */ // MIs[1] Operand 1
21725 /* 55740 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21726 /* 55745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21727 /* 55750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21728 /* 55755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21729 /* 55759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21730 /* 55763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21731 /* 55765 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21732 /* 55765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21733 /* 55768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21734 /* 55772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21735 /* 55777 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21736 /* 55781 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21737 /* 55785 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21738 /* 55787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21739 /* 55790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21740 /* 55792 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21741 /* 55794 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21742 /* 55797 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21743 /* 55799 */ GIR_RootConstrainSelectedInstOperands,
21744 /* 55800 */ // GIR_Coverage, 2364,
21745 /* 55800 */ GIR_EraseRootFromParent_Done,
21746 /* 55801 */ // Label 1367: @55801
21747 /* 55801 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(55899), // Rule ID 2365 //
21748 /* 55806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21749 /* 55809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21750 /* 55812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21751 /* 55815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21752 /* 55818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21753 /* 55822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21754 /* 55826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21755 /* 55830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21756 /* 55834 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21757 /* 55838 */ // MIs[1] Operand 1
21758 /* 55838 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21759 /* 55843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21760 /* 55848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21761 /* 55853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21762 /* 55857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21763 /* 55861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21764 /* 55863 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
21765 /* 55863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21766 /* 55866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21767 /* 55870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21768 /* 55875 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21769 /* 55879 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21770 /* 55883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21771 /* 55885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21772 /* 55888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21773 /* 55890 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21774 /* 55892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21775 /* 55895 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21776 /* 55897 */ GIR_RootConstrainSelectedInstOperands,
21777 /* 55898 */ // GIR_Coverage, 2365,
21778 /* 55898 */ GIR_EraseRootFromParent_Done,
21779 /* 55899 */ // Label 1368: @55899
21780 /* 55899 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(55997), // Rule ID 2368 //
21781 /* 55904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21782 /* 55907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21783 /* 55910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21784 /* 55913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21785 /* 55916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21786 /* 55920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21787 /* 55924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21788 /* 55928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21789 /* 55932 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21790 /* 55936 */ // MIs[1] Operand 1
21791 /* 55936 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21792 /* 55941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21793 /* 55946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21794 /* 55951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21795 /* 55955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21796 /* 55959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21797 /* 55961 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21798 /* 55961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21799 /* 55964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21800 /* 55968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21801 /* 55973 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21802 /* 55977 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21803 /* 55981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21804 /* 55983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
21805 /* 55986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21806 /* 55988 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21807 /* 55990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21808 /* 55993 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21809 /* 55995 */ GIR_RootConstrainSelectedInstOperands,
21810 /* 55996 */ // GIR_Coverage, 2368,
21811 /* 55996 */ GIR_EraseRootFromParent_Done,
21812 /* 55997 */ // Label 1369: @55997
21813 /* 55997 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(56095), // Rule ID 2371 //
21814 /* 56002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21815 /* 56005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21816 /* 56008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21817 /* 56011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21818 /* 56014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21819 /* 56018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21820 /* 56022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21821 /* 56026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21822 /* 56030 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21823 /* 56034 */ // MIs[1] Operand 1
21824 /* 56034 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21825 /* 56039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21826 /* 56044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21827 /* 56049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21828 /* 56053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21829 /* 56057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21830 /* 56059 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
21831 /* 56059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21832 /* 56062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21833 /* 56066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21834 /* 56071 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21835 /* 56075 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21836 /* 56079 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21837 /* 56081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
21838 /* 56084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21839 /* 56086 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21840 /* 56088 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21841 /* 56091 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21842 /* 56093 */ GIR_RootConstrainSelectedInstOperands,
21843 /* 56094 */ // GIR_Coverage, 2371,
21844 /* 56094 */ GIR_EraseRootFromParent_Done,
21845 /* 56095 */ // Label 1370: @56095
21846 /* 56095 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(56193), // Rule ID 2407 //
21847 /* 56100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21848 /* 56103 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21849 /* 56106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21850 /* 56109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21851 /* 56112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21852 /* 56116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21853 /* 56120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21854 /* 56124 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21855 /* 56128 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21856 /* 56132 */ // MIs[1] Operand 1
21857 /* 56132 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21858 /* 56137 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21859 /* 56142 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21860 /* 56147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21861 /* 56151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21862 /* 56155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21863 /* 56157 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21864 /* 56157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21865 /* 56160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21866 /* 56164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21867 /* 56169 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21868 /* 56173 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21869 /* 56177 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21870 /* 56179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21871 /* 56182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21872 /* 56184 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21873 /* 56186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21874 /* 56189 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21875 /* 56191 */ GIR_RootConstrainSelectedInstOperands,
21876 /* 56192 */ // GIR_Coverage, 2407,
21877 /* 56192 */ GIR_EraseRootFromParent_Done,
21878 /* 56193 */ // Label 1371: @56193
21879 /* 56193 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(56291), // Rule ID 2408 //
21880 /* 56198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21881 /* 56201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21882 /* 56204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21883 /* 56207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21884 /* 56210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21885 /* 56214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21886 /* 56218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21887 /* 56222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21888 /* 56226 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21889 /* 56230 */ // MIs[1] Operand 1
21890 /* 56230 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21891 /* 56235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21892 /* 56240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21893 /* 56245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21894 /* 56249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21895 /* 56253 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21896 /* 56255 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21897 /* 56255 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21898 /* 56258 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21899 /* 56262 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21900 /* 56267 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21901 /* 56271 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21902 /* 56275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21903 /* 56277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21904 /* 56280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21905 /* 56282 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21906 /* 56284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21907 /* 56287 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21908 /* 56289 */ GIR_RootConstrainSelectedInstOperands,
21909 /* 56290 */ // GIR_Coverage, 2408,
21910 /* 56290 */ GIR_EraseRootFromParent_Done,
21911 /* 56291 */ // Label 1372: @56291
21912 /* 56291 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(56389), // Rule ID 2411 //
21913 /* 56296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21914 /* 56299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21915 /* 56302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21916 /* 56305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21917 /* 56308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21918 /* 56312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21919 /* 56316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21920 /* 56320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21921 /* 56324 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21922 /* 56328 */ // MIs[1] Operand 1
21923 /* 56328 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21924 /* 56333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21925 /* 56338 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21926 /* 56343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21927 /* 56347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21928 /* 56351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21929 /* 56353 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21930 /* 56353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21931 /* 56356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21932 /* 56360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21933 /* 56365 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21934 /* 56369 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21935 /* 56373 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21936 /* 56375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21937 /* 56378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21938 /* 56380 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21939 /* 56382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21940 /* 56385 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21941 /* 56387 */ GIR_RootConstrainSelectedInstOperands,
21942 /* 56388 */ // GIR_Coverage, 2411,
21943 /* 56388 */ GIR_EraseRootFromParent_Done,
21944 /* 56389 */ // Label 1373: @56389
21945 /* 56389 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(56487), // Rule ID 2412 //
21946 /* 56394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21947 /* 56397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21948 /* 56400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21949 /* 56403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21950 /* 56406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21951 /* 56410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21952 /* 56414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21953 /* 56418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21954 /* 56422 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21955 /* 56426 */ // MIs[1] Operand 1
21956 /* 56426 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21957 /* 56431 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21958 /* 56436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21959 /* 56441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21960 /* 56445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21961 /* 56449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21962 /* 56451 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
21963 /* 56451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21964 /* 56454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21965 /* 56458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21966 /* 56463 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21967 /* 56467 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21968 /* 56471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21969 /* 56473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
21970 /* 56476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21971 /* 56478 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21972 /* 56480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21973 /* 56483 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21974 /* 56485 */ GIR_RootConstrainSelectedInstOperands,
21975 /* 56486 */ // GIR_Coverage, 2412,
21976 /* 56486 */ GIR_EraseRootFromParent_Done,
21977 /* 56487 */ // Label 1374: @56487
21978 /* 56487 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(56585), // Rule ID 2415 //
21979 /* 56492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
21980 /* 56495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21981 /* 56498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
21982 /* 56501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
21983 /* 56504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21984 /* 56508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21985 /* 56512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21986 /* 56516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21987 /* 56520 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21988 /* 56524 */ // MIs[1] Operand 1
21989 /* 56524 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21990 /* 56529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21991 /* 56534 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21992 /* 56539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21993 /* 56543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
21994 /* 56547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21995 /* 56549 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
21996 /* 56549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21997 /* 56552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21998 /* 56556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21999 /* 56561 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22000 /* 56565 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22001 /* 56569 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22002 /* 56571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
22003 /* 56574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22004 /* 56576 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22005 /* 56578 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22006 /* 56581 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22007 /* 56583 */ GIR_RootConstrainSelectedInstOperands,
22008 /* 56584 */ // GIR_Coverage, 2415,
22009 /* 56584 */ GIR_EraseRootFromParent_Done,
22010 /* 56585 */ // Label 1375: @56585
22011 /* 56585 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(56683), // Rule ID 2417 //
22012 /* 56590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22013 /* 56593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22014 /* 56596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22015 /* 56599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22016 /* 56602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22017 /* 56606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22018 /* 56610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22019 /* 56614 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22020 /* 56618 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22021 /* 56622 */ // MIs[1] Operand 1
22022 /* 56622 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22023 /* 56627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22024 /* 56632 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22025 /* 56637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22026 /* 56641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22027 /* 56645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22028 /* 56647 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
22029 /* 56647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22030 /* 56650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22031 /* 56654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22032 /* 56659 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22033 /* 56663 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22034 /* 56667 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22035 /* 56669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
22036 /* 56672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22037 /* 56674 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22038 /* 56676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22039 /* 56679 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22040 /* 56681 */ GIR_RootConstrainSelectedInstOperands,
22041 /* 56682 */ // GIR_Coverage, 2417,
22042 /* 56682 */ GIR_EraseRootFromParent_Done,
22043 /* 56683 */ // Label 1376: @56683
22044 /* 56683 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(56723), // Rule ID 319 //
22045 /* 56688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
22046 /* 56691 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22047 /* 56694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22048 /* 56697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22049 /* 56700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22050 /* 56704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22051 /* 56708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22052 /* 56712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22053 /* 56716 */ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
22054 /* 56716 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
22055 /* 56721 */ GIR_RootConstrainSelectedInstOperands,
22056 /* 56722 */ // GIR_Coverage, 319,
22057 /* 56722 */ GIR_Done,
22058 /* 56723 */ // Label 1377: @56723
22059 /* 56723 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(56763), // Rule ID 321 //
22060 /* 56728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
22061 /* 56731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22062 /* 56734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22063 /* 56737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22064 /* 56740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22065 /* 56744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22066 /* 56748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22067 /* 56752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22068 /* 56756 */ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
22069 /* 56756 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
22070 /* 56761 */ GIR_RootConstrainSelectedInstOperands,
22071 /* 56762 */ // GIR_Coverage, 321,
22072 /* 56762 */ GIR_Done,
22073 /* 56763 */ // Label 1378: @56763
22074 /* 56763 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(56809), // Rule ID 358 //
22075 /* 56768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
22076 /* 56771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22077 /* 56774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22078 /* 56777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22079 /* 56780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22080 /* 56784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
22081 /* 56788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22082 /* 56792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22083 /* 56796 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22084 /* 56796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
22085 /* 56799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22086 /* 56801 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22087 /* 56803 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22088 /* 56805 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22089 /* 56807 */ GIR_RootConstrainSelectedInstOperands,
22090 /* 56808 */ // GIR_Coverage, 358,
22091 /* 56808 */ GIR_EraseRootFromParent_Done,
22092 /* 56809 */ // Label 1379: @56809
22093 /* 56809 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(56855), // Rule ID 1236 //
22094 /* 56814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22095 /* 56817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22096 /* 56820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22097 /* 56823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22098 /* 56826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22099 /* 56830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
22100 /* 56834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22101 /* 56838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22102 /* 56842 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22103 /* 56842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
22104 /* 56845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22105 /* 56847 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22106 /* 56849 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22107 /* 56851 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22108 /* 56853 */ GIR_RootConstrainSelectedInstOperands,
22109 /* 56854 */ // GIR_Coverage, 1236,
22110 /* 56854 */ GIR_EraseRootFromParent_Done,
22111 /* 56855 */ // Label 1380: @56855
22112 /* 56855 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(56901), // Rule ID 1748 //
22113 /* 56860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
22114 /* 56863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22115 /* 56866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22116 /* 56869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22117 /* 56872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22118 /* 56876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22119 /* 56880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22120 /* 56884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22121 /* 56888 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22122 /* 56888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
22123 /* 56891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22124 /* 56893 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22125 /* 56895 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22126 /* 56897 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22127 /* 56899 */ GIR_RootConstrainSelectedInstOperands,
22128 /* 56900 */ // GIR_Coverage, 1748,
22129 /* 56900 */ GIR_EraseRootFromParent_Done,
22130 /* 56901 */ // Label 1381: @56901
22131 /* 56901 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(56947), // Rule ID 1787 //
22132 /* 56906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22133 /* 56909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22134 /* 56912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22135 /* 56915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22136 /* 56918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22137 /* 56922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22138 /* 56926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22139 /* 56930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22140 /* 56934 */ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
22141 /* 56934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
22142 /* 56937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22143 /* 56939 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22144 /* 56941 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22145 /* 56943 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22146 /* 56945 */ GIR_RootConstrainSelectedInstOperands,
22147 /* 56946 */ // GIR_Coverage, 1787,
22148 /* 56946 */ GIR_EraseRootFromParent_Done,
22149 /* 56947 */ // Label 1382: @56947
22150 /* 56947 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(56993), // Rule ID 1803 //
22151 /* 56952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
22152 /* 56955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22153 /* 56958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22154 /* 56961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22155 /* 56964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22156 /* 56968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22157 /* 56972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22158 /* 56976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22159 /* 56980 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
22160 /* 56980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
22161 /* 56983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22162 /* 56985 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22163 /* 56987 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22164 /* 56989 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22165 /* 56991 */ GIR_RootConstrainSelectedInstOperands,
22166 /* 56992 */ // GIR_Coverage, 1803,
22167 /* 56992 */ GIR_EraseRootFromParent_Done,
22168 /* 56993 */ // Label 1383: @56993
22169 /* 56993 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(57039), // Rule ID 1816 //
22170 /* 56998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22171 /* 57001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22172 /* 57004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22173 /* 57007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22174 /* 57010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22175 /* 57014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22176 /* 57018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22177 /* 57022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22178 /* 57026 */ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
22179 /* 57026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
22180 /* 57029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22181 /* 57031 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22182 /* 57033 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22183 /* 57035 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22184 /* 57037 */ GIR_RootConstrainSelectedInstOperands,
22185 /* 57038 */ // GIR_Coverage, 1816,
22186 /* 57038 */ GIR_EraseRootFromParent_Done,
22187 /* 57039 */ // Label 1384: @57039
22188 /* 57039 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(57085), // Rule ID 2010 //
22189 /* 57044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
22190 /* 57047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22191 /* 57050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22192 /* 57053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22193 /* 57056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22194 /* 57060 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22195 /* 57064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22196 /* 57068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
22197 /* 57072 */ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
22198 /* 57072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
22199 /* 57075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
22200 /* 57077 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
22201 /* 57079 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
22202 /* 57081 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
22203 /* 57083 */ GIR_RootConstrainSelectedInstOperands,
22204 /* 57084 */ // GIR_Coverage, 2010,
22205 /* 57084 */ GIR_EraseRootFromParent_Done,
22206 /* 57085 */ // Label 1385: @57085
22207 /* 57085 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(57131), // Rule ID 2358 //
22208 /* 57090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
22209 /* 57093 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22210 /* 57096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22211 /* 57099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22212 /* 57102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22213 /* 57106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22214 /* 57110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22215 /* 57114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22216 /* 57118 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22217 /* 57118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
22218 /* 57121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22219 /* 57123 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22220 /* 57125 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22221 /* 57127 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22222 /* 57129 */ GIR_RootConstrainSelectedInstOperands,
22223 /* 57130 */ // GIR_Coverage, 2358,
22224 /* 57130 */ GIR_EraseRootFromParent_Done,
22225 /* 57131 */ // Label 1386: @57131
22226 /* 57131 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(57177), // Rule ID 2372 //
22227 /* 57136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22228 /* 57139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22229 /* 57142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22230 /* 57145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22231 /* 57148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22232 /* 57152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22233 /* 57156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22234 /* 57160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22235 /* 57164 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
22236 /* 57164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
22237 /* 57167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22238 /* 57169 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22239 /* 57171 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22240 /* 57173 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22241 /* 57175 */ GIR_RootConstrainSelectedInstOperands,
22242 /* 57176 */ // GIR_Coverage, 2372,
22243 /* 57176 */ GIR_EraseRootFromParent_Done,
22244 /* 57177 */ // Label 1387: @57177
22245 /* 57177 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(57223), // Rule ID 2418 //
22246 /* 57182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
22247 /* 57185 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22248 /* 57188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22249 /* 57191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22250 /* 57194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22251 /* 57198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22252 /* 57202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22253 /* 57206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22254 /* 57210 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
22255 /* 57210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
22256 /* 57213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22257 /* 57215 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22258 /* 57217 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22259 /* 57219 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22260 /* 57221 */ GIR_RootConstrainSelectedInstOperands,
22261 /* 57222 */ // GIR_Coverage, 2418,
22262 /* 57222 */ GIR_EraseRootFromParent_Done,
22263 /* 57223 */ // Label 1388: @57223
22264 /* 57223 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(57301), // Rule ID 1877 //
22265 /* 57228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
22266 /* 57231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22267 /* 57234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22268 /* 57237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22269 /* 57240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22270 /* 57244 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
22271 /* 57244 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
22272 /* 57247 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
22273 /* 57251 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22274 /* 57256 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22275 /* 57260 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22276 /* 57264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22277 /* 57266 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22278 /* 57269 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
22279 /* 57273 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22280 /* 57278 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22281 /* 57282 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22282 /* 57286 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22283 /* 57288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
22284 /* 57291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22285 /* 57293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22286 /* 57296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22287 /* 57299 */ GIR_RootConstrainSelectedInstOperands,
22288 /* 57300 */ // GIR_Coverage, 1877,
22289 /* 57300 */ GIR_EraseRootFromParent_Done,
22290 /* 57301 */ // Label 1389: @57301
22291 /* 57301 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(57379), // Rule ID 2435 //
22292 /* 57306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22293 /* 57309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22294 /* 57312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22295 /* 57315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22296 /* 57318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22297 /* 57322 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
22298 /* 57322 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
22299 /* 57325 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
22300 /* 57329 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22301 /* 57334 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22302 /* 57338 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22303 /* 57342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22304 /* 57344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22305 /* 57347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
22306 /* 57351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22307 /* 57356 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22308 /* 57360 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22309 /* 57364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22310 /* 57366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
22311 /* 57369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22312 /* 57371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22313 /* 57374 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22314 /* 57377 */ GIR_RootConstrainSelectedInstOperands,
22315 /* 57378 */ // GIR_Coverage, 2435,
22316 /* 57378 */ GIR_EraseRootFromParent_Done,
22317 /* 57379 */ // Label 1390: @57379
22318 /* 57379 */ GIM_Reject,
22319 /* 57380 */ // Label 1305: @57380
22320 /* 57380 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(57456), // Rule ID 1775 //
22321 /* 57385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22322 /* 57388 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22323 /* 57391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22324 /* 57394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22325 /* 57397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22326 /* 57401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22327 /* 57405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22328 /* 57409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22329 /* 57413 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22330 /* 57417 */ // MIs[1] Operand 1
22331 /* 57417 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22332 /* 57422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22333 /* 57427 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22334 /* 57431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22335 /* 57435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22336 /* 57439 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22337 /* 57441 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
22338 /* 57441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22339 /* 57444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22340 /* 57446 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22341 /* 57448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22342 /* 57452 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22343 /* 57454 */ GIR_RootConstrainSelectedInstOperands,
22344 /* 57455 */ // GIR_Coverage, 1775,
22345 /* 57455 */ GIR_EraseRootFromParent_Done,
22346 /* 57456 */ // Label 1391: @57456
22347 /* 57456 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(57532), // Rule ID 1779 //
22348 /* 57461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22349 /* 57464 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22350 /* 57467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22351 /* 57470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22352 /* 57473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22353 /* 57477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22354 /* 57481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22355 /* 57485 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22356 /* 57489 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22357 /* 57493 */ // MIs[1] Operand 1
22358 /* 57493 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22359 /* 57498 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22360 /* 57503 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22361 /* 57507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22362 /* 57511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22363 /* 57515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22364 /* 57517 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
22365 /* 57517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
22366 /* 57520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22367 /* 57522 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22368 /* 57524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22369 /* 57528 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22370 /* 57530 */ GIR_RootConstrainSelectedInstOperands,
22371 /* 57531 */ // GIR_Coverage, 1779,
22372 /* 57531 */ GIR_EraseRootFromParent_Done,
22373 /* 57532 */ // Label 1392: @57532
22374 /* 57532 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(57608), // Rule ID 1785 //
22375 /* 57537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22376 /* 57540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22377 /* 57543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22378 /* 57546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22379 /* 57549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22380 /* 57553 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22381 /* 57557 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22382 /* 57561 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22383 /* 57565 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22384 /* 57569 */ // MIs[1] Operand 1
22385 /* 57569 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22386 /* 57574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22387 /* 57579 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22388 /* 57583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22389 /* 57587 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22390 /* 57591 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22391 /* 57593 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
22392 /* 57593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22393 /* 57596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22394 /* 57598 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22395 /* 57600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22396 /* 57604 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22397 /* 57606 */ GIR_RootConstrainSelectedInstOperands,
22398 /* 57607 */ // GIR_Coverage, 1785,
22399 /* 57607 */ GIR_EraseRootFromParent_Done,
22400 /* 57608 */ // Label 1393: @57608
22401 /* 57608 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(57684), // Rule ID 1791 //
22402 /* 57613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22403 /* 57616 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22404 /* 57619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22405 /* 57622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22406 /* 57625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22407 /* 57629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22408 /* 57633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22409 /* 57637 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22410 /* 57641 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22411 /* 57645 */ // MIs[1] Operand 1
22412 /* 57645 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22413 /* 57650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22414 /* 57655 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22415 /* 57659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22416 /* 57663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22417 /* 57667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22418 /* 57669 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
22419 /* 57669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22420 /* 57672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22421 /* 57674 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22422 /* 57676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22423 /* 57680 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22424 /* 57682 */ GIR_RootConstrainSelectedInstOperands,
22425 /* 57683 */ // GIR_Coverage, 1791,
22426 /* 57683 */ GIR_EraseRootFromParent_Done,
22427 /* 57684 */ // Label 1394: @57684
22428 /* 57684 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(57760), // Rule ID 1827 //
22429 /* 57689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22430 /* 57692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22431 /* 57695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22432 /* 57698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22433 /* 57701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22434 /* 57705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22435 /* 57709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22436 /* 57713 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22437 /* 57717 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22438 /* 57721 */ // MIs[1] Operand 1
22439 /* 57721 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22440 /* 57726 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22441 /* 57731 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22442 /* 57735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22443 /* 57739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22444 /* 57743 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22445 /* 57745 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22446 /* 57745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
22447 /* 57748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22448 /* 57750 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22449 /* 57752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22450 /* 57756 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22451 /* 57758 */ GIR_RootConstrainSelectedInstOperands,
22452 /* 57759 */ // GIR_Coverage, 1827,
22453 /* 57759 */ GIR_EraseRootFromParent_Done,
22454 /* 57760 */ // Label 1395: @57760
22455 /* 57760 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(57836), // Rule ID 1830 //
22456 /* 57765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22457 /* 57768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22458 /* 57771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22459 /* 57774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22460 /* 57777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22461 /* 57781 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22462 /* 57785 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22463 /* 57789 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22464 /* 57793 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22465 /* 57797 */ // MIs[1] Operand 1
22466 /* 57797 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22467 /* 57802 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22468 /* 57807 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22469 /* 57811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22470 /* 57815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22471 /* 57819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22472 /* 57821 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22473 /* 57821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22474 /* 57824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22475 /* 57826 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22476 /* 57828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22477 /* 57832 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22478 /* 57834 */ GIR_RootConstrainSelectedInstOperands,
22479 /* 57835 */ // GIR_Coverage, 1830,
22480 /* 57835 */ GIR_EraseRootFromParent_Done,
22481 /* 57836 */ // Label 1396: @57836
22482 /* 57836 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(57912), // Rule ID 1848 //
22483 /* 57841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22484 /* 57844 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22485 /* 57847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22486 /* 57850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22487 /* 57853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22488 /* 57857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22489 /* 57861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22490 /* 57865 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22491 /* 57869 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22492 /* 57873 */ // MIs[1] Operand 1
22493 /* 57873 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22494 /* 57878 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22495 /* 57883 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22496 /* 57887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22497 /* 57891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22498 /* 57895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22499 /* 57897 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22500 /* 57897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
22501 /* 57900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22502 /* 57902 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22503 /* 57904 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22504 /* 57908 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22505 /* 57910 */ GIR_RootConstrainSelectedInstOperands,
22506 /* 57911 */ // GIR_Coverage, 1848,
22507 /* 57911 */ GIR_EraseRootFromParent_Done,
22508 /* 57912 */ // Label 1397: @57912
22509 /* 57912 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(57988), // Rule ID 1850 //
22510 /* 57917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22511 /* 57920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22512 /* 57923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22513 /* 57926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22514 /* 57929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22515 /* 57933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22516 /* 57937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22517 /* 57941 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22518 /* 57945 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22519 /* 57949 */ // MIs[1] Operand 1
22520 /* 57949 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22521 /* 57954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22522 /* 57959 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22523 /* 57963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22524 /* 57967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22525 /* 57971 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22526 /* 57973 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22527 /* 57973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
22528 /* 57976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22529 /* 57978 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22530 /* 57980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22531 /* 57984 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22532 /* 57986 */ GIR_RootConstrainSelectedInstOperands,
22533 /* 57987 */ // GIR_Coverage, 1850,
22534 /* 57987 */ GIR_EraseRootFromParent_Done,
22535 /* 57988 */ // Label 1398: @57988
22536 /* 57988 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(58064), // Rule ID 1853 //
22537 /* 57993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22538 /* 57996 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22539 /* 57999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22540 /* 58002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22541 /* 58005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22542 /* 58009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22543 /* 58013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22544 /* 58017 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22545 /* 58021 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22546 /* 58025 */ // MIs[1] Operand 1
22547 /* 58025 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22548 /* 58030 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22549 /* 58035 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22550 /* 58039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22551 /* 58043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22552 /* 58047 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22553 /* 58049 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
22554 /* 58049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22555 /* 58052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22556 /* 58054 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22557 /* 58056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22558 /* 58060 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22559 /* 58062 */ GIR_RootConstrainSelectedInstOperands,
22560 /* 58063 */ // GIR_Coverage, 1853,
22561 /* 58063 */ GIR_EraseRootFromParent_Done,
22562 /* 58064 */ // Label 1399: @58064
22563 /* 58064 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(58140), // Rule ID 1856 //
22564 /* 58069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22565 /* 58072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22566 /* 58075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22567 /* 58078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22568 /* 58081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22569 /* 58085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22570 /* 58089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22571 /* 58093 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22572 /* 58097 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22573 /* 58101 */ // MIs[1] Operand 1
22574 /* 58101 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22575 /* 58106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22576 /* 58111 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22577 /* 58115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22578 /* 58119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22579 /* 58123 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22580 /* 58125 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
22581 /* 58125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22582 /* 58128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22583 /* 58130 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22584 /* 58132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22585 /* 58136 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22586 /* 58138 */ GIR_RootConstrainSelectedInstOperands,
22587 /* 58139 */ // GIR_Coverage, 1856,
22588 /* 58139 */ GIR_EraseRootFromParent_Done,
22589 /* 58140 */ // Label 1400: @58140
22590 /* 58140 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(58216), // Rule ID 2429 //
22591 /* 58145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22592 /* 58148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22593 /* 58151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22594 /* 58154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22595 /* 58157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22596 /* 58161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22597 /* 58165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22598 /* 58169 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22599 /* 58173 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22600 /* 58177 */ // MIs[1] Operand 1
22601 /* 58177 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22602 /* 58182 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22603 /* 58187 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22604 /* 58191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22605 /* 58195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22606 /* 58199 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22607 /* 58201 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22608 /* 58201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22609 /* 58204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22610 /* 58206 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22611 /* 58208 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22612 /* 58212 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22613 /* 58214 */ GIR_RootConstrainSelectedInstOperands,
22614 /* 58215 */ // GIR_Coverage, 2429,
22615 /* 58215 */ GIR_EraseRootFromParent_Done,
22616 /* 58216 */ // Label 1401: @58216
22617 /* 58216 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(58292), // Rule ID 2432 //
22618 /* 58221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22619 /* 58224 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22620 /* 58227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22621 /* 58230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22622 /* 58233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22623 /* 58237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22624 /* 58241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22625 /* 58245 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22626 /* 58249 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22627 /* 58253 */ // MIs[1] Operand 1
22628 /* 58253 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22629 /* 58258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22630 /* 58263 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
22631 /* 58267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22632 /* 58271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22633 /* 58275 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22634 /* 58277 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
22635 /* 58277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22636 /* 58280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22637 /* 58282 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22638 /* 58284 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22639 /* 58288 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22640 /* 58290 */ GIR_RootConstrainSelectedInstOperands,
22641 /* 58291 */ // GIR_Coverage, 2432,
22642 /* 58291 */ GIR_EraseRootFromParent_Done,
22643 /* 58292 */ // Label 1402: @58292
22644 /* 58292 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(58390), // Rule ID 1750 //
22645 /* 58297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22646 /* 58300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22647 /* 58303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22648 /* 58306 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22649 /* 58309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22650 /* 58313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22651 /* 58317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22652 /* 58321 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22653 /* 58325 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22654 /* 58329 */ // MIs[1] Operand 1
22655 /* 58329 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22656 /* 58334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22657 /* 58339 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22658 /* 58344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22659 /* 58348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22660 /* 58352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22661 /* 58354 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22662 /* 58354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22663 /* 58357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22664 /* 58361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22665 /* 58366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22666 /* 58370 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22667 /* 58374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22668 /* 58376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22669 /* 58379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22670 /* 58381 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22671 /* 58383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22672 /* 58386 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22673 /* 58388 */ GIR_RootConstrainSelectedInstOperands,
22674 /* 58389 */ // GIR_Coverage, 1750,
22675 /* 58389 */ GIR_EraseRootFromParent_Done,
22676 /* 58390 */ // Label 1403: @58390
22677 /* 58390 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(58488), // Rule ID 1751 //
22678 /* 58395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22679 /* 58398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22680 /* 58401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22681 /* 58404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22682 /* 58407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22683 /* 58411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22684 /* 58415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22685 /* 58419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22686 /* 58423 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22687 /* 58427 */ // MIs[1] Operand 1
22688 /* 58427 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22689 /* 58432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22690 /* 58437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22691 /* 58442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22692 /* 58446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22693 /* 58450 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22694 /* 58452 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22695 /* 58452 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22696 /* 58455 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22697 /* 58459 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22698 /* 58464 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22699 /* 58468 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22700 /* 58472 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22701 /* 58474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22702 /* 58477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22703 /* 58479 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22704 /* 58481 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22705 /* 58484 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22706 /* 58486 */ GIR_RootConstrainSelectedInstOperands,
22707 /* 58487 */ // GIR_Coverage, 1751,
22708 /* 58487 */ GIR_EraseRootFromParent_Done,
22709 /* 58488 */ // Label 1404: @58488
22710 /* 58488 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(58586), // Rule ID 1754 //
22711 /* 58493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22712 /* 58496 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22713 /* 58499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22714 /* 58502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22715 /* 58505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22716 /* 58509 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22717 /* 58513 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22718 /* 58517 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22719 /* 58521 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22720 /* 58525 */ // MIs[1] Operand 1
22721 /* 58525 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22722 /* 58530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22723 /* 58535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22724 /* 58540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22725 /* 58544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22726 /* 58548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22727 /* 58550 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22728 /* 58550 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22729 /* 58553 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
22730 /* 58557 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22731 /* 58562 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22732 /* 58566 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22733 /* 58570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22734 /* 58572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22735 /* 58575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22736 /* 58577 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22737 /* 58579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22738 /* 58582 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22739 /* 58584 */ GIR_RootConstrainSelectedInstOperands,
22740 /* 58585 */ // GIR_Coverage, 1754,
22741 /* 58585 */ GIR_EraseRootFromParent_Done,
22742 /* 58586 */ // Label 1405: @58586
22743 /* 58586 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(58684), // Rule ID 1755 //
22744 /* 58591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22745 /* 58594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22746 /* 58597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22747 /* 58600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22748 /* 58603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22749 /* 58607 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22750 /* 58611 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22751 /* 58615 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22752 /* 58619 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22753 /* 58623 */ // MIs[1] Operand 1
22754 /* 58623 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22755 /* 58628 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22756 /* 58633 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22757 /* 58638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22758 /* 58642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22759 /* 58646 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22760 /* 58648 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
22761 /* 58648 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22762 /* 58651 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
22763 /* 58655 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22764 /* 58660 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22765 /* 58664 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22766 /* 58668 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22767 /* 58670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22768 /* 58673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22769 /* 58675 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22770 /* 58677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22771 /* 58680 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22772 /* 58682 */ GIR_RootConstrainSelectedInstOperands,
22773 /* 58683 */ // GIR_Coverage, 1755,
22774 /* 58683 */ GIR_EraseRootFromParent_Done,
22775 /* 58684 */ // Label 1406: @58684
22776 /* 58684 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(58782), // Rule ID 1766 //
22777 /* 58689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22778 /* 58692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22779 /* 58695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22780 /* 58698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22781 /* 58701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22782 /* 58705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22783 /* 58709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22784 /* 58713 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22785 /* 58717 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22786 /* 58721 */ // MIs[1] Operand 1
22787 /* 58721 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22788 /* 58726 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22789 /* 58731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22790 /* 58736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22791 /* 58740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22792 /* 58744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22793 /* 58746 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22794 /* 58746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22795 /* 58749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22796 /* 58753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22797 /* 58758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22798 /* 58762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22799 /* 58766 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22800 /* 58768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22801 /* 58771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22802 /* 58773 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22803 /* 58775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22804 /* 58778 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22805 /* 58780 */ GIR_RootConstrainSelectedInstOperands,
22806 /* 58781 */ // GIR_Coverage, 1766,
22807 /* 58781 */ GIR_EraseRootFromParent_Done,
22808 /* 58782 */ // Label 1407: @58782
22809 /* 58782 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(58880), // Rule ID 1767 //
22810 /* 58787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22811 /* 58790 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22812 /* 58793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22813 /* 58796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22814 /* 58799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22815 /* 58803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22816 /* 58807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22817 /* 58811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22818 /* 58815 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22819 /* 58819 */ // MIs[1] Operand 1
22820 /* 58819 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22821 /* 58824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22822 /* 58829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22823 /* 58834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22824 /* 58838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22825 /* 58842 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22826 /* 58844 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22827 /* 58844 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22828 /* 58847 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22829 /* 58851 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22830 /* 58856 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22831 /* 58860 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22832 /* 58864 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22833 /* 58866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22834 /* 58869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22835 /* 58871 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22836 /* 58873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22837 /* 58876 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22838 /* 58878 */ GIR_RootConstrainSelectedInstOperands,
22839 /* 58879 */ // GIR_Coverage, 1767,
22840 /* 58879 */ GIR_EraseRootFromParent_Done,
22841 /* 58880 */ // Label 1408: @58880
22842 /* 58880 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(58978), // Rule ID 1770 //
22843 /* 58885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22844 /* 58888 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22845 /* 58891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22846 /* 58894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22847 /* 58897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22848 /* 58901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22849 /* 58905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22850 /* 58909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22851 /* 58913 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22852 /* 58917 */ // MIs[1] Operand 1
22853 /* 58917 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22854 /* 58922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22855 /* 58927 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22856 /* 58932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22857 /* 58936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22858 /* 58940 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22859 /* 58942 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22860 /* 58942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22861 /* 58945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
22862 /* 58949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22863 /* 58954 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22864 /* 58958 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22865 /* 58962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22866 /* 58964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22867 /* 58967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22868 /* 58969 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22869 /* 58971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22870 /* 58974 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22871 /* 58976 */ GIR_RootConstrainSelectedInstOperands,
22872 /* 58977 */ // GIR_Coverage, 1770,
22873 /* 58977 */ GIR_EraseRootFromParent_Done,
22874 /* 58978 */ // Label 1409: @58978
22875 /* 58978 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(59076), // Rule ID 1771 //
22876 /* 58983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22877 /* 58986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22878 /* 58989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22879 /* 58992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22880 /* 58995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22881 /* 58999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22882 /* 59003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22883 /* 59007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22884 /* 59011 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22885 /* 59015 */ // MIs[1] Operand 1
22886 /* 59015 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22887 /* 59020 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22888 /* 59025 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22889 /* 59030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22890 /* 59034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22891 /* 59038 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22892 /* 59040 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
22893 /* 59040 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22894 /* 59043 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
22895 /* 59047 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22896 /* 59052 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22897 /* 59056 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22898 /* 59060 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22899 /* 59062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22900 /* 59065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22901 /* 59067 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22902 /* 59069 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22903 /* 59072 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22904 /* 59074 */ GIR_RootConstrainSelectedInstOperands,
22905 /* 59075 */ // GIR_Coverage, 1771,
22906 /* 59075 */ GIR_EraseRootFromParent_Done,
22907 /* 59076 */ // Label 1410: @59076
22908 /* 59076 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(59174), // Rule ID 1774 //
22909 /* 59081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22910 /* 59084 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22911 /* 59087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22912 /* 59090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22913 /* 59093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22914 /* 59097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22915 /* 59101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22916 /* 59105 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22917 /* 59109 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22918 /* 59113 */ // MIs[1] Operand 1
22919 /* 59113 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22920 /* 59118 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22921 /* 59123 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22922 /* 59128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22923 /* 59132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22924 /* 59136 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22925 /* 59138 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22926 /* 59138 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22927 /* 59141 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22928 /* 59145 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22929 /* 59150 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22930 /* 59154 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22931 /* 59158 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22932 /* 59160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
22933 /* 59163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22934 /* 59165 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22935 /* 59167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22936 /* 59170 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22937 /* 59172 */ GIR_RootConstrainSelectedInstOperands,
22938 /* 59173 */ // GIR_Coverage, 1774,
22939 /* 59173 */ GIR_EraseRootFromParent_Done,
22940 /* 59174 */ // Label 1411: @59174
22941 /* 59174 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(59272), // Rule ID 1778 //
22942 /* 59179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22943 /* 59182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22944 /* 59185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22945 /* 59188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22946 /* 59191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22947 /* 59195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22948 /* 59199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22949 /* 59203 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22950 /* 59207 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
22951 /* 59211 */ // MIs[1] Operand 1
22952 /* 59211 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22953 /* 59216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22954 /* 59221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22955 /* 59226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22956 /* 59230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22957 /* 59234 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22958 /* 59236 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
22959 /* 59236 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22960 /* 59239 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22961 /* 59243 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22962 /* 59248 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22963 /* 59252 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22964 /* 59256 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22965 /* 59258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
22966 /* 59261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22967 /* 59263 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22968 /* 59265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22969 /* 59268 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22970 /* 59270 */ GIR_RootConstrainSelectedInstOperands,
22971 /* 59271 */ // GIR_Coverage, 1778,
22972 /* 59271 */ GIR_EraseRootFromParent_Done,
22973 /* 59272 */ // Label 1412: @59272
22974 /* 59272 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(59370), // Rule ID 1783 //
22975 /* 59277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22976 /* 59280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22977 /* 59283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22978 /* 59286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22979 /* 59289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22980 /* 59293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22981 /* 59297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22982 /* 59301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22983 /* 59305 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22984 /* 59309 */ // MIs[1] Operand 1
22985 /* 59309 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22986 /* 59314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22987 /* 59319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22988 /* 59324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22989 /* 59328 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22990 /* 59332 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22991 /* 59334 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
22992 /* 59334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22993 /* 59337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
22994 /* 59341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22995 /* 59346 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22996 /* 59350 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22997 /* 59354 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22998 /* 59356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22999 /* 59359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23000 /* 59361 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23001 /* 59363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23002 /* 59366 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23003 /* 59368 */ GIR_RootConstrainSelectedInstOperands,
23004 /* 59369 */ // GIR_Coverage, 1783,
23005 /* 59369 */ GIR_EraseRootFromParent_Done,
23006 /* 59370 */ // Label 1413: @59370
23007 /* 59370 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(59468), // Rule ID 1789 //
23008 /* 59375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23009 /* 59378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23010 /* 59381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23011 /* 59384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23012 /* 59387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23013 /* 59391 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23014 /* 59395 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23015 /* 59399 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23016 /* 59403 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23017 /* 59407 */ // MIs[1] Operand 1
23018 /* 59407 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23019 /* 59412 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23020 /* 59417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23021 /* 59422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23022 /* 59426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23023 /* 59430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23024 /* 59432 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
23025 /* 59432 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23026 /* 59435 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23027 /* 59439 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23028 /* 59444 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23029 /* 59448 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23030 /* 59452 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23031 /* 59454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
23032 /* 59457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23033 /* 59459 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23034 /* 59461 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23035 /* 59464 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23036 /* 59466 */ GIR_RootConstrainSelectedInstOperands,
23037 /* 59467 */ // GIR_Coverage, 1789,
23038 /* 59467 */ GIR_EraseRootFromParent_Done,
23039 /* 59468 */ // Label 1414: @59468
23040 /* 59468 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(59566), // Rule ID 1818 //
23041 /* 59473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23042 /* 59476 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23043 /* 59479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23044 /* 59482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23045 /* 59485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23046 /* 59489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23047 /* 59493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23048 /* 59497 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23049 /* 59501 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23050 /* 59505 */ // MIs[1] Operand 1
23051 /* 59505 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23052 /* 59510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23053 /* 59515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23054 /* 59520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23055 /* 59524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23056 /* 59528 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23057 /* 59530 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23058 /* 59530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23059 /* 59533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23060 /* 59537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23061 /* 59542 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23062 /* 59546 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23063 /* 59550 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23064 /* 59552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23065 /* 59555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23066 /* 59557 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23067 /* 59559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23068 /* 59562 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23069 /* 59564 */ GIR_RootConstrainSelectedInstOperands,
23070 /* 59565 */ // GIR_Coverage, 1818,
23071 /* 59565 */ GIR_EraseRootFromParent_Done,
23072 /* 59566 */ // Label 1415: @59566
23073 /* 59566 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(59664), // Rule ID 1819 //
23074 /* 59571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23075 /* 59574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23076 /* 59577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23077 /* 59580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23078 /* 59583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23079 /* 59587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23080 /* 59591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23081 /* 59595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23082 /* 59599 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23083 /* 59603 */ // MIs[1] Operand 1
23084 /* 59603 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23085 /* 59608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23086 /* 59613 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23087 /* 59618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23088 /* 59622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23089 /* 59626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23090 /* 59628 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23091 /* 59628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23092 /* 59631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23093 /* 59635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23094 /* 59640 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23095 /* 59644 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23096 /* 59648 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23097 /* 59650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23098 /* 59653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23099 /* 59655 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23100 /* 59657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23101 /* 59660 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23102 /* 59662 */ GIR_RootConstrainSelectedInstOperands,
23103 /* 59663 */ // GIR_Coverage, 1819,
23104 /* 59663 */ GIR_EraseRootFromParent_Done,
23105 /* 59664 */ // Label 1416: @59664
23106 /* 59664 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(59762), // Rule ID 1822 //
23107 /* 59669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23108 /* 59672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23109 /* 59675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23110 /* 59678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23111 /* 59681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23112 /* 59685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23113 /* 59689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23114 /* 59693 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23115 /* 59697 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23116 /* 59701 */ // MIs[1] Operand 1
23117 /* 59701 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23118 /* 59706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23119 /* 59711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23120 /* 59716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23121 /* 59720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23122 /* 59724 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23123 /* 59726 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23124 /* 59726 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23125 /* 59729 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23126 /* 59733 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23127 /* 59738 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23128 /* 59742 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23129 /* 59746 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23130 /* 59748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23131 /* 59751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23132 /* 59753 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23133 /* 59755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23134 /* 59758 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23135 /* 59760 */ GIR_RootConstrainSelectedInstOperands,
23136 /* 59761 */ // GIR_Coverage, 1822,
23137 /* 59761 */ GIR_EraseRootFromParent_Done,
23138 /* 59762 */ // Label 1417: @59762
23139 /* 59762 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(59860), // Rule ID 1823 //
23140 /* 59767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23141 /* 59770 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23142 /* 59773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23143 /* 59776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23144 /* 59779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23145 /* 59783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23146 /* 59787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23147 /* 59791 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23148 /* 59795 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23149 /* 59799 */ // MIs[1] Operand 1
23150 /* 59799 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23151 /* 59804 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23152 /* 59809 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23153 /* 59814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23154 /* 59818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23155 /* 59822 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23156 /* 59824 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23157 /* 59824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23158 /* 59827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23159 /* 59831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23160 /* 59836 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23161 /* 59840 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23162 /* 59844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23163 /* 59846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23164 /* 59849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23165 /* 59851 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23166 /* 59853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23167 /* 59856 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23168 /* 59858 */ GIR_RootConstrainSelectedInstOperands,
23169 /* 59859 */ // GIR_Coverage, 1823,
23170 /* 59859 */ GIR_EraseRootFromParent_Done,
23171 /* 59860 */ // Label 1418: @59860
23172 /* 59860 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(59958), // Rule ID 1826 //
23173 /* 59865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23174 /* 59868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23175 /* 59871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23176 /* 59874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23177 /* 59877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23178 /* 59881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23179 /* 59885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23180 /* 59889 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23181 /* 59893 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23182 /* 59897 */ // MIs[1] Operand 1
23183 /* 59897 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23184 /* 59902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23185 /* 59907 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23186 /* 59912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23187 /* 59916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23188 /* 59920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23189 /* 59922 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23190 /* 59922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23191 /* 59925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23192 /* 59929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23193 /* 59934 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23194 /* 59938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23195 /* 59942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23196 /* 59944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
23197 /* 59947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23198 /* 59949 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23199 /* 59951 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23200 /* 59954 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23201 /* 59956 */ GIR_RootConstrainSelectedInstOperands,
23202 /* 59957 */ // GIR_Coverage, 1826,
23203 /* 59957 */ GIR_EraseRootFromParent_Done,
23204 /* 59958 */ // Label 1419: @59958
23205 /* 59958 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(60056), // Rule ID 1828 //
23206 /* 59963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23207 /* 59966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23208 /* 59969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23209 /* 59972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23210 /* 59975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23211 /* 59979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23212 /* 59983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23213 /* 59987 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23214 /* 59991 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23215 /* 59995 */ // MIs[1] Operand 1
23216 /* 59995 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23217 /* 60000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23218 /* 60005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23219 /* 60010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23220 /* 60014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23221 /* 60018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23222 /* 60020 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23223 /* 60020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23224 /* 60023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23225 /* 60027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23226 /* 60032 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23227 /* 60036 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23228 /* 60040 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23229 /* 60042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
23230 /* 60045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23231 /* 60047 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23232 /* 60049 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23233 /* 60052 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23234 /* 60054 */ GIR_RootConstrainSelectedInstOperands,
23235 /* 60055 */ // GIR_Coverage, 1828,
23236 /* 60055 */ GIR_EraseRootFromParent_Done,
23237 /* 60056 */ // Label 1420: @60056
23238 /* 60056 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(60154), // Rule ID 1831 //
23239 /* 60061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23240 /* 60064 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23241 /* 60067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23242 /* 60070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23243 /* 60073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23244 /* 60077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23245 /* 60081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23246 /* 60085 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23247 /* 60089 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23248 /* 60093 */ // MIs[1] Operand 1
23249 /* 60093 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23250 /* 60098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23251 /* 60103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23252 /* 60108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23253 /* 60112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23254 /* 60116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23255 /* 60118 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23256 /* 60118 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23257 /* 60121 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23258 /* 60125 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23259 /* 60130 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23260 /* 60134 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23261 /* 60138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23262 /* 60140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23263 /* 60143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23264 /* 60145 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23265 /* 60147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23266 /* 60150 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23267 /* 60152 */ GIR_RootConstrainSelectedInstOperands,
23268 /* 60153 */ // GIR_Coverage, 1831,
23269 /* 60153 */ GIR_EraseRootFromParent_Done,
23270 /* 60154 */ // Label 1421: @60154
23271 /* 60154 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(60252), // Rule ID 1832 //
23272 /* 60159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23273 /* 60162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23274 /* 60165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23275 /* 60168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23276 /* 60171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23277 /* 60175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23278 /* 60179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23279 /* 60183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23280 /* 60187 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23281 /* 60191 */ // MIs[1] Operand 1
23282 /* 60191 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23283 /* 60196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23284 /* 60201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23285 /* 60206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23286 /* 60210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23287 /* 60214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23288 /* 60216 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23289 /* 60216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23290 /* 60219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23291 /* 60223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23292 /* 60228 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23293 /* 60232 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23294 /* 60236 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23295 /* 60238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23296 /* 60241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23297 /* 60243 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23298 /* 60245 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23299 /* 60248 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23300 /* 60250 */ GIR_RootConstrainSelectedInstOperands,
23301 /* 60251 */ // GIR_Coverage, 1832,
23302 /* 60251 */ GIR_EraseRootFromParent_Done,
23303 /* 60252 */ // Label 1422: @60252
23304 /* 60252 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(60350), // Rule ID 1835 //
23305 /* 60257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23306 /* 60260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23307 /* 60263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23308 /* 60266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23309 /* 60269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23310 /* 60273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23311 /* 60277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23312 /* 60281 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23313 /* 60285 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23314 /* 60289 */ // MIs[1] Operand 1
23315 /* 60289 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23316 /* 60294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23317 /* 60299 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23318 /* 60304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23319 /* 60308 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23320 /* 60312 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23321 /* 60314 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
23322 /* 60314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23323 /* 60317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
23324 /* 60321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23325 /* 60326 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23326 /* 60330 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23327 /* 60334 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23328 /* 60336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23329 /* 60339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23330 /* 60341 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23331 /* 60343 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23332 /* 60346 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23333 /* 60348 */ GIR_RootConstrainSelectedInstOperands,
23334 /* 60349 */ // GIR_Coverage, 1835,
23335 /* 60349 */ GIR_EraseRootFromParent_Done,
23336 /* 60350 */ // Label 1423: @60350
23337 /* 60350 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(60448), // Rule ID 1836 //
23338 /* 60355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23339 /* 60358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23340 /* 60361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23341 /* 60364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23342 /* 60367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23343 /* 60371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23344 /* 60375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23345 /* 60379 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23346 /* 60383 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23347 /* 60387 */ // MIs[1] Operand 1
23348 /* 60387 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23349 /* 60392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23350 /* 60397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23351 /* 60402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23352 /* 60406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23353 /* 60410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23354 /* 60412 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
23355 /* 60412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23356 /* 60415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
23357 /* 60419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23358 /* 60424 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23359 /* 60428 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23360 /* 60432 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23361 /* 60434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23362 /* 60437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23363 /* 60439 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23364 /* 60441 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23365 /* 60444 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23366 /* 60446 */ GIR_RootConstrainSelectedInstOperands,
23367 /* 60447 */ // GIR_Coverage, 1836,
23368 /* 60447 */ GIR_EraseRootFromParent_Done,
23369 /* 60448 */ // Label 1424: @60448
23370 /* 60448 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(60546), // Rule ID 1839 //
23371 /* 60453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23372 /* 60456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23373 /* 60459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23374 /* 60462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23375 /* 60465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23376 /* 60469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23377 /* 60473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23378 /* 60477 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23379 /* 60481 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23380 /* 60485 */ // MIs[1] Operand 1
23381 /* 60485 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23382 /* 60490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23383 /* 60495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23384 /* 60500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23385 /* 60504 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23386 /* 60508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23387 /* 60510 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23388 /* 60510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23389 /* 60513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
23390 /* 60517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23391 /* 60522 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23392 /* 60526 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23393 /* 60530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23394 /* 60532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23395 /* 60535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23396 /* 60537 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23397 /* 60539 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23398 /* 60542 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23399 /* 60544 */ GIR_RootConstrainSelectedInstOperands,
23400 /* 60545 */ // GIR_Coverage, 1839,
23401 /* 60545 */ GIR_EraseRootFromParent_Done,
23402 /* 60546 */ // Label 1425: @60546
23403 /* 60546 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(60644), // Rule ID 1840 //
23404 /* 60551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23405 /* 60554 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23406 /* 60557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23407 /* 60560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23408 /* 60563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23409 /* 60567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23410 /* 60571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23411 /* 60575 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23412 /* 60579 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23413 /* 60583 */ // MIs[1] Operand 1
23414 /* 60583 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23415 /* 60588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23416 /* 60593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23417 /* 60598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23418 /* 60602 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23419 /* 60606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23420 /* 60608 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23421 /* 60608 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23422 /* 60611 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
23423 /* 60615 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23424 /* 60620 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23425 /* 60624 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23426 /* 60628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23427 /* 60630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23428 /* 60633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23429 /* 60635 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23430 /* 60637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23431 /* 60640 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23432 /* 60642 */ GIR_RootConstrainSelectedInstOperands,
23433 /* 60643 */ // GIR_Coverage, 1840,
23434 /* 60643 */ GIR_EraseRootFromParent_Done,
23435 /* 60644 */ // Label 1426: @60644
23436 /* 60644 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(60742), // Rule ID 1843 //
23437 /* 60649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23438 /* 60652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23439 /* 60655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23440 /* 60658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23441 /* 60661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23442 /* 60665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23443 /* 60669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23444 /* 60673 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23445 /* 60677 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23446 /* 60681 */ // MIs[1] Operand 1
23447 /* 60681 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23448 /* 60686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23449 /* 60691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23450 /* 60696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23451 /* 60700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23452 /* 60704 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23453 /* 60706 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23454 /* 60706 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23455 /* 60709 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
23456 /* 60713 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23457 /* 60718 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23458 /* 60722 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23459 /* 60726 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23460 /* 60728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23461 /* 60731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23462 /* 60733 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23463 /* 60735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23464 /* 60738 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23465 /* 60740 */ GIR_RootConstrainSelectedInstOperands,
23466 /* 60741 */ // GIR_Coverage, 1843,
23467 /* 60741 */ GIR_EraseRootFromParent_Done,
23468 /* 60742 */ // Label 1427: @60742
23469 /* 60742 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(60840), // Rule ID 1844 //
23470 /* 60747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23471 /* 60750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23472 /* 60753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23473 /* 60756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23474 /* 60759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23475 /* 60763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23476 /* 60767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23477 /* 60771 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23478 /* 60775 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23479 /* 60779 */ // MIs[1] Operand 1
23480 /* 60779 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23481 /* 60784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23482 /* 60789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23483 /* 60794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23484 /* 60798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23485 /* 60802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23486 /* 60804 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
23487 /* 60804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23488 /* 60807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
23489 /* 60811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23490 /* 60816 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23491 /* 60820 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23492 /* 60824 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23493 /* 60826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23494 /* 60829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23495 /* 60831 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23496 /* 60833 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23497 /* 60836 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23498 /* 60838 */ GIR_RootConstrainSelectedInstOperands,
23499 /* 60839 */ // GIR_Coverage, 1844,
23500 /* 60839 */ GIR_EraseRootFromParent_Done,
23501 /* 60840 */ // Label 1428: @60840
23502 /* 60840 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(60938), // Rule ID 1847 //
23503 /* 60845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23504 /* 60848 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23505 /* 60851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23506 /* 60854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23507 /* 60857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23508 /* 60861 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23509 /* 60865 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23510 /* 60869 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23511 /* 60873 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23512 /* 60877 */ // MIs[1] Operand 1
23513 /* 60877 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23514 /* 60882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23515 /* 60887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23516 /* 60892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23517 /* 60896 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23518 /* 60900 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23519 /* 60902 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23520 /* 60902 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23521 /* 60905 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23522 /* 60909 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23523 /* 60914 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23524 /* 60918 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23525 /* 60922 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23526 /* 60924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
23527 /* 60927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23528 /* 60929 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23529 /* 60931 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23530 /* 60934 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23531 /* 60936 */ GIR_RootConstrainSelectedInstOperands,
23532 /* 60937 */ // GIR_Coverage, 1847,
23533 /* 60937 */ GIR_EraseRootFromParent_Done,
23534 /* 60938 */ // Label 1429: @60938
23535 /* 60938 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(61036), // Rule ID 1849 //
23536 /* 60943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23537 /* 60946 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23538 /* 60949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23539 /* 60952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23540 /* 60955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23541 /* 60959 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23542 /* 60963 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23543 /* 60967 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23544 /* 60971 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23545 /* 60975 */ // MIs[1] Operand 1
23546 /* 60975 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23547 /* 60980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23548 /* 60985 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23549 /* 60990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23550 /* 60994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23551 /* 60998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23552 /* 61000 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23553 /* 61000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23554 /* 61003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23555 /* 61007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23556 /* 61012 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23557 /* 61016 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23558 /* 61020 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23559 /* 61022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
23560 /* 61025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23561 /* 61027 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23562 /* 61029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23563 /* 61032 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23564 /* 61034 */ GIR_RootConstrainSelectedInstOperands,
23565 /* 61035 */ // GIR_Coverage, 1849,
23566 /* 61035 */ GIR_EraseRootFromParent_Done,
23567 /* 61036 */ // Label 1430: @61036
23568 /* 61036 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(61134), // Rule ID 1851 //
23569 /* 61041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23570 /* 61044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23571 /* 61047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23572 /* 61050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23573 /* 61053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23574 /* 61057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23575 /* 61061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23576 /* 61065 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23577 /* 61069 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23578 /* 61073 */ // MIs[1] Operand 1
23579 /* 61073 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23580 /* 61078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23581 /* 61083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23582 /* 61088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23583 /* 61092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23584 /* 61096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23585 /* 61098 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
23586 /* 61098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23587 /* 61101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
23588 /* 61105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23589 /* 61110 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23590 /* 61114 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23591 /* 61118 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23592 /* 61120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23593 /* 61123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23594 /* 61125 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23595 /* 61127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23596 /* 61130 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23597 /* 61132 */ GIR_RootConstrainSelectedInstOperands,
23598 /* 61133 */ // GIR_Coverage, 1851,
23599 /* 61133 */ GIR_EraseRootFromParent_Done,
23600 /* 61134 */ // Label 1431: @61134
23601 /* 61134 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(61232), // Rule ID 1854 //
23602 /* 61139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23603 /* 61142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23604 /* 61145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23605 /* 61148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23606 /* 61151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23607 /* 61155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23608 /* 61159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23609 /* 61163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23610 /* 61167 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
23611 /* 61171 */ // MIs[1] Operand 1
23612 /* 61171 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23613 /* 61176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23614 /* 61181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23615 /* 61186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23616 /* 61190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23617 /* 61194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23618 /* 61196 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
23619 /* 61196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23620 /* 61199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
23621 /* 61203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23622 /* 61208 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23623 /* 61212 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23624 /* 61216 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23625 /* 61218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
23626 /* 61221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23627 /* 61223 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23628 /* 61225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23629 /* 61228 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23630 /* 61230 */ GIR_RootConstrainSelectedInstOperands,
23631 /* 61231 */ // GIR_Coverage, 1854,
23632 /* 61231 */ GIR_EraseRootFromParent_Done,
23633 /* 61232 */ // Label 1432: @61232
23634 /* 61232 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(61330), // Rule ID 2420 //
23635 /* 61237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23636 /* 61240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23637 /* 61243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23638 /* 61246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23639 /* 61249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23640 /* 61253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23641 /* 61257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23642 /* 61261 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23643 /* 61265 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23644 /* 61269 */ // MIs[1] Operand 1
23645 /* 61269 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
23646 /* 61274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23647 /* 61279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23648 /* 61284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23649 /* 61288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23650 /* 61292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23651 /* 61294 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23652 /* 61294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23653 /* 61297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23654 /* 61301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23655 /* 61306 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23656 /* 61310 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23657 /* 61314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23658 /* 61316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23659 /* 61319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23660 /* 61321 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23661 /* 61323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23662 /* 61326 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23663 /* 61328 */ GIR_RootConstrainSelectedInstOperands,
23664 /* 61329 */ // GIR_Coverage, 2420,
23665 /* 61329 */ GIR_EraseRootFromParent_Done,
23666 /* 61330 */ // Label 1433: @61330
23667 /* 61330 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(61428), // Rule ID 2421 //
23668 /* 61335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23669 /* 61338 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23670 /* 61341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23671 /* 61344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23672 /* 61347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23673 /* 61351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23674 /* 61355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23675 /* 61359 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23676 /* 61363 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23677 /* 61367 */ // MIs[1] Operand 1
23678 /* 61367 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
23679 /* 61372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23680 /* 61377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23681 /* 61382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23682 /* 61386 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23683 /* 61390 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23684 /* 61392 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23685 /* 61392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23686 /* 61395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23687 /* 61399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23688 /* 61404 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23689 /* 61408 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23690 /* 61412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23691 /* 61414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23692 /* 61417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23693 /* 61419 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23694 /* 61421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23695 /* 61424 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23696 /* 61426 */ GIR_RootConstrainSelectedInstOperands,
23697 /* 61427 */ // GIR_Coverage, 2421,
23698 /* 61427 */ GIR_EraseRootFromParent_Done,
23699 /* 61428 */ // Label 1434: @61428
23700 /* 61428 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(61526), // Rule ID 2424 //
23701 /* 61433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23702 /* 61436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23703 /* 61439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23704 /* 61442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23705 /* 61445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23706 /* 61449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23707 /* 61453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23708 /* 61457 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23709 /* 61461 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23710 /* 61465 */ // MIs[1] Operand 1
23711 /* 61465 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
23712 /* 61470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23713 /* 61475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23714 /* 61480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23715 /* 61484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23716 /* 61488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23717 /* 61490 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23718 /* 61490 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23719 /* 61493 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
23720 /* 61497 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23721 /* 61502 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23722 /* 61506 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23723 /* 61510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23724 /* 61512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23725 /* 61515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23726 /* 61517 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23727 /* 61519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23728 /* 61522 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23729 /* 61524 */ GIR_RootConstrainSelectedInstOperands,
23730 /* 61525 */ // GIR_Coverage, 2424,
23731 /* 61525 */ GIR_EraseRootFromParent_Done,
23732 /* 61526 */ // Label 1435: @61526
23733 /* 61526 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(61624), // Rule ID 2425 //
23734 /* 61531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23735 /* 61534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23736 /* 61537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23737 /* 61540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23738 /* 61543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23739 /* 61547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23740 /* 61551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23741 /* 61555 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23742 /* 61559 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23743 /* 61563 */ // MIs[1] Operand 1
23744 /* 61563 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
23745 /* 61568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23746 /* 61573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23747 /* 61578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23748 /* 61582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23749 /* 61586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23750 /* 61588 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
23751 /* 61588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23752 /* 61591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
23753 /* 61595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23754 /* 61600 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23755 /* 61604 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23756 /* 61608 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23757 /* 61610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23758 /* 61613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23759 /* 61615 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23760 /* 61617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23761 /* 61620 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23762 /* 61622 */ GIR_RootConstrainSelectedInstOperands,
23763 /* 61623 */ // GIR_Coverage, 2425,
23764 /* 61623 */ GIR_EraseRootFromParent_Done,
23765 /* 61624 */ // Label 1436: @61624
23766 /* 61624 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(61722), // Rule ID 2428 //
23767 /* 61629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23768 /* 61632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23769 /* 61635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23770 /* 61638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23771 /* 61641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23772 /* 61645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23773 /* 61649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23774 /* 61653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23775 /* 61657 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23776 /* 61661 */ // MIs[1] Operand 1
23777 /* 61661 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
23778 /* 61666 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23779 /* 61671 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23780 /* 61676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23781 /* 61680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23782 /* 61684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23783 /* 61686 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23784 /* 61686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23785 /* 61689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23786 /* 61693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23787 /* 61698 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23788 /* 61702 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23789 /* 61706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23790 /* 61708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
23791 /* 61711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23792 /* 61713 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23793 /* 61715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23794 /* 61718 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23795 /* 61720 */ GIR_RootConstrainSelectedInstOperands,
23796 /* 61721 */ // GIR_Coverage, 2428,
23797 /* 61721 */ GIR_EraseRootFromParent_Done,
23798 /* 61722 */ // Label 1437: @61722
23799 /* 61722 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(61820), // Rule ID 2430 //
23800 /* 61727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
23801 /* 61730 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23802 /* 61733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23803 /* 61736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23804 /* 61739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23805 /* 61743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23806 /* 61747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
23807 /* 61751 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23808 /* 61755 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
23809 /* 61759 */ // MIs[1] Operand 1
23810 /* 61759 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
23811 /* 61764 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23812 /* 61769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23813 /* 61774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23814 /* 61778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23815 /* 61782 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23816 /* 61784 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
23817 /* 61784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23818 /* 61787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
23819 /* 61791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23820 /* 61796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
23821 /* 61800 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
23822 /* 61804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23823 /* 61806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
23824 /* 61809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23825 /* 61811 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23826 /* 61813 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23827 /* 61816 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23828 /* 61818 */ GIR_RootConstrainSelectedInstOperands,
23829 /* 61819 */ // GIR_Coverage, 2430,
23830 /* 61819 */ GIR_EraseRootFromParent_Done,
23831 /* 61820 */ // Label 1438: @61820
23832 /* 61820 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(61860), // Rule ID 320 //
23833 /* 61825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
23834 /* 61828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23835 /* 61831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23836 /* 61834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23837 /* 61837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23838 /* 61841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23839 /* 61845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23840 /* 61849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23841 /* 61853 */ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
23842 /* 61853 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
23843 /* 61858 */ GIR_RootConstrainSelectedInstOperands,
23844 /* 61859 */ // GIR_Coverage, 320,
23845 /* 61859 */ GIR_Done,
23846 /* 61860 */ // Label 1439: @61860
23847 /* 61860 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(61900), // Rule ID 322 //
23848 /* 61865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotMips4_32),
23849 /* 61868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23850 /* 61871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23851 /* 61874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23852 /* 61877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23853 /* 61881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23854 /* 61885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23855 /* 61889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23856 /* 61893 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
23857 /* 61893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
23858 /* 61898 */ GIR_RootConstrainSelectedInstOperands,
23859 /* 61899 */ // GIR_Coverage, 322,
23860 /* 61899 */ GIR_Done,
23861 /* 61900 */ // Label 1440: @61900
23862 /* 61900 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(61940), // Rule ID 323 //
23863 /* 61905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotMips4_32),
23864 /* 61908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23865 /* 61911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23866 /* 61914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23867 /* 61917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23868 /* 61921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23869 /* 61925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23870 /* 61929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23871 /* 61933 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
23872 /* 61933 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
23873 /* 61938 */ GIR_RootConstrainSelectedInstOperands,
23874 /* 61939 */ // GIR_Coverage, 323,
23875 /* 61939 */ GIR_Done,
23876 /* 61940 */ // Label 1441: @61940
23877 /* 61940 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(61986), // Rule ID 357 //
23878 /* 61945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23879 /* 61948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23880 /* 61951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23881 /* 61954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23882 /* 61957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23883 /* 61961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
23884 /* 61965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23885 /* 61969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23886 /* 61973 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23887 /* 61973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D),
23888 /* 61976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23889 /* 61978 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
23890 /* 61980 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
23891 /* 61982 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23892 /* 61984 */ GIR_RootConstrainSelectedInstOperands,
23893 /* 61985 */ // GIR_Coverage, 357,
23894 /* 61985 */ GIR_EraseRootFromParent_Done,
23895 /* 61986 */ // Label 1442: @61986
23896 /* 61986 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(62032), // Rule ID 1237 //
23897 /* 61991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
23898 /* 61994 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23899 /* 61997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23900 /* 62000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23901 /* 62003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23902 /* 62007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
23903 /* 62011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23904 /* 62015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23905 /* 62019 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D_MMR6:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23906 /* 62019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D_MMR6),
23907 /* 62022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23908 /* 62024 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
23909 /* 62026 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
23910 /* 62028 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23911 /* 62030 */ GIR_RootConstrainSelectedInstOperands,
23912 /* 62031 */ // GIR_Coverage, 1237,
23913 /* 62031 */ GIR_EraseRootFromParent_Done,
23914 /* 62032 */ // Label 1443: @62032
23915 /* 62032 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(62078), // Rule ID 1784 //
23916 /* 62037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23917 /* 62040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23918 /* 62043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23919 /* 62046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23920 /* 62049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23921 /* 62053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23922 /* 62057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23923 /* 62061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23924 /* 62065 */ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
23925 /* 62065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
23926 /* 62068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23927 /* 62070 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23928 /* 62072 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23929 /* 62074 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23930 /* 62076 */ GIR_RootConstrainSelectedInstOperands,
23931 /* 62077 */ // GIR_Coverage, 1784,
23932 /* 62077 */ GIR_EraseRootFromParent_Done,
23933 /* 62078 */ // Label 1444: @62078
23934 /* 62078 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(62124), // Rule ID 1790 //
23935 /* 62083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23936 /* 62086 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23937 /* 62089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23938 /* 62092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23939 /* 62095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23940 /* 62099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23941 /* 62103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23942 /* 62107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23943 /* 62111 */ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
23944 /* 62111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
23945 /* 62114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
23946 /* 62116 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23947 /* 62118 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23948 /* 62120 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23949 /* 62122 */ GIR_RootConstrainSelectedInstOperands,
23950 /* 62123 */ // GIR_Coverage, 1790,
23951 /* 62123 */ GIR_EraseRootFromParent_Done,
23952 /* 62124 */ // Label 1445: @62124
23953 /* 62124 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(62170), // Rule ID 1829 //
23954 /* 62129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23955 /* 62132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23956 /* 62135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23957 /* 62138 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23958 /* 62141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23959 /* 62145 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23960 /* 62149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23961 /* 62153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23962 /* 62157 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
23963 /* 62157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
23964 /* 62160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23965 /* 62162 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23966 /* 62164 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23967 /* 62166 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23968 /* 62168 */ GIR_RootConstrainSelectedInstOperands,
23969 /* 62169 */ // GIR_Coverage, 1829,
23970 /* 62169 */ GIR_EraseRootFromParent_Done,
23971 /* 62170 */ // Label 1446: @62170
23972 /* 62170 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(62216), // Rule ID 1852 //
23973 /* 62175 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23974 /* 62178 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23975 /* 62181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23976 /* 62184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23977 /* 62187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23978 /* 62191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23979 /* 62195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23980 /* 62199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23981 /* 62203 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
23982 /* 62203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
23983 /* 62206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23984 /* 62208 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
23985 /* 62210 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
23986 /* 62212 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
23987 /* 62214 */ GIR_RootConstrainSelectedInstOperands,
23988 /* 62215 */ // GIR_Coverage, 1852,
23989 /* 62215 */ GIR_EraseRootFromParent_Done,
23990 /* 62216 */ // Label 1447: @62216
23991 /* 62216 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(62262), // Rule ID 1855 //
23992 /* 62221 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23993 /* 62224 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23994 /* 62227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23995 /* 62230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23996 /* 62233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23997 /* 62237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23998 /* 62241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23999 /* 62245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24000 /* 62249 */ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
24001 /* 62249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
24002 /* 62252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24003 /* 62254 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
24004 /* 62256 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
24005 /* 62258 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
24006 /* 62260 */ GIR_RootConstrainSelectedInstOperands,
24007 /* 62261 */ // GIR_Coverage, 1855,
24008 /* 62261 */ GIR_EraseRootFromParent_Done,
24009 /* 62262 */ // Label 1448: @62262
24010 /* 62262 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(62308), // Rule ID 2431 //
24011 /* 62267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
24012 /* 62270 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24013 /* 62273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24014 /* 62276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24015 /* 62279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24016 /* 62283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24017 /* 62287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24018 /* 62291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24019 /* 62295 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
24020 /* 62295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
24021 /* 62298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24022 /* 62300 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
24023 /* 62302 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
24024 /* 62304 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
24025 /* 62306 */ GIR_RootConstrainSelectedInstOperands,
24026 /* 62307 */ // GIR_Coverage, 2431,
24027 /* 62307 */ GIR_EraseRootFromParent_Done,
24028 /* 62308 */ // Label 1449: @62308
24029 /* 62308 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(62386), // Rule ID 1908 //
24030 /* 62313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
24031 /* 62316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24032 /* 62319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24033 /* 62322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24034 /* 62325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24035 /* 62329 */ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
24036 /* 62329 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
24037 /* 62332 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
24038 /* 62336 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24039 /* 62341 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
24040 /* 62345 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
24041 /* 62349 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24042 /* 62351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24043 /* 62354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
24044 /* 62358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24045 /* 62363 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
24046 /* 62367 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
24047 /* 62371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24048 /* 62373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
24049 /* 62376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24050 /* 62378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24051 /* 62381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
24052 /* 62384 */ GIR_RootConstrainSelectedInstOperands,
24053 /* 62385 */ // GIR_Coverage, 1908,
24054 /* 62385 */ GIR_EraseRootFromParent_Done,
24055 /* 62386 */ // Label 1450: @62386
24056 /* 62386 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(62498), // Rule ID 1919 //
24057 /* 62391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
24058 /* 62394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24059 /* 62397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24060 /* 62400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
24061 /* 62403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24062 /* 62407 */ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
24063 /* 62407 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
24064 /* 62410 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
24065 /* 62414 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24066 /* 62419 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
24067 /* 62423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
24068 /* 62425 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
24069 /* 62428 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
24070 /* 62432 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24071 /* 62437 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
24072 /* 62441 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
24073 /* 62444 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
24074 /* 62446 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
24075 /* 62449 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
24076 /* 62453 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24077 /* 62458 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
24078 /* 62462 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
24079 /* 62464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24080 /* 62467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
24081 /* 62471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24082 /* 62476 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
24083 /* 62480 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24084 /* 62483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24085 /* 62485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
24086 /* 62488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24087 /* 62490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24088 /* 62493 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
24089 /* 62496 */ GIR_RootConstrainSelectedInstOperands,
24090 /* 62497 */ // GIR_Coverage, 1919,
24091 /* 62497 */ GIR_EraseRootFromParent_Done,
24092 /* 62498 */ // Label 1451: @62498
24093 /* 62498 */ GIM_Reject,
24094 /* 62499 */ // Label 1306: @62499
24095 /* 62499 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(62572),
24096 /* 62504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24097 /* 62507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24098 /* 62510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
24099 /* 62513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24100 /* 62517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24101 /* 62521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24102 /* 62525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24103 /* 62529 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(62550), // Rule ID 607 //
24104 /* 62534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24105 /* 62537 */ // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24106 /* 62537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
24107 /* 62540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24108 /* 62542 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24109 /* 62544 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24110 /* 62546 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24111 /* 62548 */ GIR_RootConstrainSelectedInstOperands,
24112 /* 62549 */ // GIR_Coverage, 607,
24113 /* 62549 */ GIR_EraseRootFromParent_Done,
24114 /* 62550 */ // Label 1453: @62550
24115 /* 62550 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(62571), // Rule ID 609 //
24116 /* 62555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24117 /* 62558 */ // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24118 /* 62558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
24119 /* 62561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24120 /* 62563 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24121 /* 62565 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24122 /* 62567 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24123 /* 62569 */ GIR_RootConstrainSelectedInstOperands,
24124 /* 62570 */ // GIR_Coverage, 609,
24125 /* 62570 */ GIR_EraseRootFromParent_Done,
24126 /* 62571 */ // Label 1454: @62571
24127 /* 62571 */ GIM_Reject,
24128 /* 62572 */ // Label 1452: @62572
24129 /* 62572 */ GIM_Reject,
24130 /* 62573 */ // Label 1307: @62573
24131 /* 62573 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(62646),
24132 /* 62578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24133 /* 62581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24134 /* 62584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24135 /* 62587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24136 /* 62591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24137 /* 62595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24138 /* 62599 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24139 /* 62603 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(62624), // Rule ID 606 //
24140 /* 62608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24141 /* 62611 */ // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24142 /* 62611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
24143 /* 62614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24144 /* 62616 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24145 /* 62618 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24146 /* 62620 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24147 /* 62622 */ GIR_RootConstrainSelectedInstOperands,
24148 /* 62623 */ // GIR_Coverage, 606,
24149 /* 62623 */ GIR_EraseRootFromParent_Done,
24150 /* 62624 */ // Label 1456: @62624
24151 /* 62624 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(62645), // Rule ID 608 //
24152 /* 62629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24153 /* 62632 */ // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24154 /* 62632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
24155 /* 62635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24156 /* 62637 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24157 /* 62639 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24158 /* 62641 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24159 /* 62643 */ GIR_RootConstrainSelectedInstOperands,
24160 /* 62644 */ // GIR_Coverage, 608,
24161 /* 62644 */ GIR_EraseRootFromParent_Done,
24162 /* 62645 */ // Label 1457: @62645
24163 /* 62645 */ GIM_Reject,
24164 /* 62646 */ // Label 1455: @62646
24165 /* 62646 */ GIM_Reject,
24166 /* 62647 */ // Label 1308: @62647
24167 /* 62647 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(62693), // Rule ID 605 //
24168 /* 62652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24169 /* 62655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24170 /* 62658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24171 /* 62661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24172 /* 62664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24173 /* 62668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24174 /* 62672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24175 /* 62676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24176 /* 62680 */ // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24177 /* 62680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
24178 /* 62683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24179 /* 62685 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24180 /* 62687 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24181 /* 62689 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24182 /* 62691 */ GIR_RootConstrainSelectedInstOperands,
24183 /* 62692 */ // GIR_Coverage, 605,
24184 /* 62692 */ GIR_EraseRootFromParent_Done,
24185 /* 62693 */ // Label 1458: @62693
24186 /* 62693 */ GIM_Reject,
24187 /* 62694 */ // Label 1309: @62694
24188 /* 62694 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(62788),
24189 /* 62699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24190 /* 62702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24191 /* 62705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24192 /* 62708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24193 /* 62712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24194 /* 62716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24195 /* 62720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24196 /* 62724 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(62745), // Rule ID 592 //
24197 /* 62729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24198 /* 62732 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24199 /* 62732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
24200 /* 62735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24201 /* 62737 */ GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
24202 /* 62739 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
24203 /* 62741 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
24204 /* 62743 */ GIR_RootConstrainSelectedInstOperands,
24205 /* 62744 */ // GIR_Coverage, 592,
24206 /* 62744 */ GIR_EraseRootFromParent_Done,
24207 /* 62745 */ // Label 1460: @62745
24208 /* 62745 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(62766), // Rule ID 594 //
24209 /* 62750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24210 /* 62753 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24211 /* 62753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
24212 /* 62756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24213 /* 62758 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
24214 /* 62760 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24215 /* 62762 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
24216 /* 62764 */ GIR_RootConstrainSelectedInstOperands,
24217 /* 62765 */ // GIR_Coverage, 594,
24218 /* 62765 */ GIR_EraseRootFromParent_Done,
24219 /* 62766 */ // Label 1461: @62766
24220 /* 62766 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(62787), // Rule ID 604 //
24221 /* 62771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24222 /* 62774 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24223 /* 62774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
24224 /* 62777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24225 /* 62779 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24226 /* 62781 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
24227 /* 62783 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
24228 /* 62785 */ GIR_RootConstrainSelectedInstOperands,
24229 /* 62786 */ // GIR_Coverage, 604,
24230 /* 62786 */ GIR_EraseRootFromParent_Done,
24231 /* 62787 */ // Label 1462: @62787
24232 /* 62787 */ GIM_Reject,
24233 /* 62788 */ // Label 1459: @62788
24234 /* 62788 */ GIM_Reject,
24235 /* 62789 */ // Label 1310: @62789
24236 /* 62789 */ GIM_Reject,
24237 /* 62790 */ // Label 44: @62790
24238 /* 62790 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1465*/ GIMT_Encode4(62898),
24239 /* 62801 */ /*GILLT_s32*//*Label 1463*/ GIMT_Encode4(62809),
24240 /* 62805 */ /*GILLT_s64*//*Label 1464*/ GIMT_Encode4(62864),
24241 /* 62809 */ // Label 1463: @62809
24242 /* 62809 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(62863),
24243 /* 62814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24244 /* 62817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24245 /* 62820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24246 /* 62824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24247 /* 62828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24248 /* 62832 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(62847), // Rule ID 355 //
24249 /* 62837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24250 /* 62840 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24251 /* 62840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
24252 /* 62845 */ GIR_RootConstrainSelectedInstOperands,
24253 /* 62846 */ // GIR_Coverage, 355,
24254 /* 62846 */ GIR_Done,
24255 /* 62847 */ // Label 1467: @62847
24256 /* 62847 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(62862), // Rule ID 1204 //
24257 /* 62852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
24258 /* 62855 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24259 /* 62855 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
24260 /* 62860 */ GIR_RootConstrainSelectedInstOperands,
24261 /* 62861 */ // GIR_Coverage, 1204,
24262 /* 62861 */ GIR_Done,
24263 /* 62862 */ // Label 1468: @62862
24264 /* 62862 */ GIM_Reject,
24265 /* 62863 */ // Label 1466: @62863
24266 /* 62863 */ GIM_Reject,
24267 /* 62864 */ // Label 1464: @62864
24268 /* 62864 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(62897), // Rule ID 370 //
24269 /* 62869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
24270 /* 62872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24271 /* 62875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24272 /* 62878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24273 /* 62882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24274 /* 62886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24275 /* 62890 */ // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
24276 /* 62890 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
24277 /* 62895 */ GIR_RootConstrainSelectedInstOperands,
24278 /* 62896 */ // GIR_Coverage, 370,
24279 /* 62896 */ GIR_Done,
24280 /* 62897 */ // Label 1469: @62897
24281 /* 62897 */ GIM_Reject,
24282 /* 62898 */ // Label 1465: @62898
24283 /* 62898 */ GIM_Reject,
24284 /* 62899 */ // Label 45: @62899
24285 /* 62899 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1472*/ GIMT_Encode4(63007),
24286 /* 62910 */ /*GILLT_s32*//*Label 1470*/ GIMT_Encode4(62918),
24287 /* 62914 */ /*GILLT_s64*//*Label 1471*/ GIMT_Encode4(62973),
24288 /* 62918 */ // Label 1470: @62918
24289 /* 62918 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(62972),
24290 /* 62923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24291 /* 62926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24292 /* 62929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24293 /* 62933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24294 /* 62937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24295 /* 62941 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(62956), // Rule ID 354 //
24296 /* 62946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24297 /* 62949 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24298 /* 62949 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
24299 /* 62954 */ GIR_RootConstrainSelectedInstOperands,
24300 /* 62955 */ // GIR_Coverage, 354,
24301 /* 62955 */ GIR_Done,
24302 /* 62956 */ // Label 1474: @62956
24303 /* 62956 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(62971), // Rule ID 1203 //
24304 /* 62961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
24305 /* 62964 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
24306 /* 62964 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
24307 /* 62969 */ GIR_RootConstrainSelectedInstOperands,
24308 /* 62970 */ // GIR_Coverage, 1203,
24309 /* 62970 */ GIR_Done,
24310 /* 62971 */ // Label 1475: @62971
24311 /* 62971 */ GIM_Reject,
24312 /* 62972 */ // Label 1473: @62972
24313 /* 62972 */ GIM_Reject,
24314 /* 62973 */ // Label 1471: @62973
24315 /* 62973 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(63006), // Rule ID 369 //
24316 /* 62978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
24317 /* 62981 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24318 /* 62984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24319 /* 62987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24320 /* 62991 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24321 /* 62995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24322 /* 62999 */ // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
24323 /* 62999 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
24324 /* 63004 */ GIR_RootConstrainSelectedInstOperands,
24325 /* 63005 */ // GIR_Coverage, 369,
24326 /* 63005 */ GIR_Done,
24327 /* 63006 */ // Label 1476: @63006
24328 /* 63006 */ GIM_Reject,
24329 /* 63007 */ // Label 1472: @63007
24330 /* 63007 */ GIM_Reject,
24331 /* 63008 */ // Label 46: @63008
24332 /* 63008 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1481*/ GIMT_Encode4(64302),
24333 /* 63019 */ /*GILLT_s32*//*Label 1477*/ GIMT_Encode4(63043),
24334 /* 63023 */ /*GILLT_s64*//*Label 1478*/ GIMT_Encode4(63369), GIMT_Encode4(0),
24335 /* 63031 */ /*GILLT_v2s64*//*Label 1479*/ GIMT_Encode4(63994), GIMT_Encode4(0),
24336 /* 63039 */ /*GILLT_v4s32*//*Label 1480*/ GIMT_Encode4(64148),
24337 /* 63043 */ // Label 1477: @63043
24338 /* 63043 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(63368),
24339 /* 63048 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24340 /* 63051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24341 /* 63054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24342 /* 63058 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(63115), // Rule ID 178 //
24343 /* 63063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24344 /* 63066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24345 /* 63070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24346 /* 63074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24347 /* 63078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24348 /* 63082 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24349 /* 63087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24350 /* 63092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24351 /* 63096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24352 /* 63098 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24353 /* 63098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24354 /* 63101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24355 /* 63103 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24356 /* 63105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24357 /* 63109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24358 /* 63113 */ GIR_RootConstrainSelectedInstOperands,
24359 /* 63114 */ // GIR_Coverage, 178,
24360 /* 63114 */ GIR_EraseRootFromParent_Done,
24361 /* 63115 */ // Label 1483: @63115
24362 /* 63115 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(63172), // Rule ID 177 //
24363 /* 63120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24364 /* 63123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24365 /* 63127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24366 /* 63131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24367 /* 63135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24368 /* 63139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24369 /* 63144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24370 /* 63149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24371 /* 63153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24372 /* 63155 */ // (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24373 /* 63155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24374 /* 63158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24375 /* 63160 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24376 /* 63162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24377 /* 63166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24378 /* 63170 */ GIR_RootConstrainSelectedInstOperands,
24379 /* 63171 */ // GIR_Coverage, 177,
24380 /* 63171 */ GIR_EraseRootFromParent_Done,
24381 /* 63172 */ // Label 1484: @63172
24382 /* 63172 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(63229), // Rule ID 2490 //
24383 /* 63177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24384 /* 63180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24385 /* 63184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24386 /* 63188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24387 /* 63192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24388 /* 63196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24389 /* 63200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24390 /* 63205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24391 /* 63210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24392 /* 63212 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24393 /* 63212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24394 /* 63215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24395 /* 63217 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24396 /* 63219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24397 /* 63223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24398 /* 63227 */ GIR_RootConstrainSelectedInstOperands,
24399 /* 63228 */ // GIR_Coverage, 2490,
24400 /* 63228 */ GIR_EraseRootFromParent_Done,
24401 /* 63229 */ // Label 1485: @63229
24402 /* 63229 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(63286), // Rule ID 2489 //
24403 /* 63234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24404 /* 63237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24405 /* 63241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24406 /* 63245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24407 /* 63249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24408 /* 63253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24409 /* 63257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24410 /* 63262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24411 /* 63267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24412 /* 63269 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24413 /* 63269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
24414 /* 63272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24415 /* 63274 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24416 /* 63276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24417 /* 63280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24418 /* 63284 */ GIR_RootConstrainSelectedInstOperands,
24419 /* 63285 */ // GIR_Coverage, 2489,
24420 /* 63285 */ GIR_EraseRootFromParent_Done,
24421 /* 63286 */ // Label 1486: @63286
24422 /* 63286 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(63313), // Rule ID 152 //
24423 /* 63291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24424 /* 63294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24425 /* 63298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24426 /* 63302 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24427 /* 63302 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
24428 /* 63307 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24429 /* 63311 */ GIR_RootConstrainSelectedInstOperands,
24430 /* 63312 */ // GIR_Coverage, 152,
24431 /* 63312 */ GIR_Done,
24432 /* 63313 */ // Label 1487: @63313
24433 /* 63313 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(63340), // Rule ID 1154 //
24434 /* 63318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24435 /* 63321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24436 /* 63325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24437 /* 63329 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24438 /* 63329 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
24439 /* 63334 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24440 /* 63338 */ GIR_RootConstrainSelectedInstOperands,
24441 /* 63339 */ // GIR_Coverage, 1154,
24442 /* 63339 */ GIR_Done,
24443 /* 63340 */ // Label 1488: @63340
24444 /* 63340 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(63367), // Rule ID 1211 //
24445 /* 63345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24446 /* 63348 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24447 /* 63352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24448 /* 63356 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24449 /* 63356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
24450 /* 63359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24451 /* 63361 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24452 /* 63363 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24453 /* 63365 */ GIR_RootConstrainSelectedInstOperands,
24454 /* 63366 */ // GIR_Coverage, 1211,
24455 /* 63366 */ GIR_EraseRootFromParent_Done,
24456 /* 63367 */ // Label 1489: @63367
24457 /* 63367 */ GIM_Reject,
24458 /* 63368 */ // Label 1482: @63368
24459 /* 63368 */ GIM_Reject,
24460 /* 63369 */ // Label 1478: @63369
24461 /* 63369 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(63993),
24462 /* 63374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24463 /* 63377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24464 /* 63380 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(63441), // Rule ID 186 //
24465 /* 63385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24466 /* 63388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24467 /* 63392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24468 /* 63396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24469 /* 63400 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24470 /* 63404 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24471 /* 63408 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24472 /* 63413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24473 /* 63418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24474 /* 63422 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24475 /* 63424 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24476 /* 63424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24477 /* 63427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24478 /* 63429 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24479 /* 63431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24480 /* 63435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24481 /* 63439 */ GIR_RootConstrainSelectedInstOperands,
24482 /* 63440 */ // GIR_Coverage, 186,
24483 /* 63440 */ GIR_EraseRootFromParent_Done,
24484 /* 63441 */ // Label 1491: @63441
24485 /* 63441 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(63502), // Rule ID 194 //
24486 /* 63446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24487 /* 63449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24488 /* 63453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24489 /* 63457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24490 /* 63461 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24491 /* 63465 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24492 /* 63469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24493 /* 63474 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24494 /* 63479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24495 /* 63483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24496 /* 63485 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24497 /* 63485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24498 /* 63488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24499 /* 63490 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24500 /* 63492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24501 /* 63496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24502 /* 63500 */ GIR_RootConstrainSelectedInstOperands,
24503 /* 63501 */ // GIR_Coverage, 194,
24504 /* 63501 */ GIR_EraseRootFromParent_Done,
24505 /* 63502 */ // Label 1492: @63502
24506 /* 63502 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(63563), // Rule ID 185 //
24507 /* 63507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24508 /* 63510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24509 /* 63514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24510 /* 63518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24511 /* 63522 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24512 /* 63526 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24513 /* 63530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24514 /* 63535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24515 /* 63540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24516 /* 63544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24517 /* 63546 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24518 /* 63546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24519 /* 63549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24520 /* 63551 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24521 /* 63553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24522 /* 63557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24523 /* 63561 */ GIR_RootConstrainSelectedInstOperands,
24524 /* 63562 */ // GIR_Coverage, 185,
24525 /* 63562 */ GIR_EraseRootFromParent_Done,
24526 /* 63563 */ // Label 1493: @63563
24527 /* 63563 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(63624), // Rule ID 193 //
24528 /* 63568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24529 /* 63571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24530 /* 63575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24531 /* 63579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24532 /* 63583 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24533 /* 63587 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24534 /* 63591 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24535 /* 63596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24536 /* 63601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24537 /* 63605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24538 /* 63607 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24539 /* 63607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24540 /* 63610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24541 /* 63612 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24542 /* 63614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24543 /* 63618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24544 /* 63622 */ GIR_RootConstrainSelectedInstOperands,
24545 /* 63623 */ // GIR_Coverage, 193,
24546 /* 63623 */ GIR_EraseRootFromParent_Done,
24547 /* 63624 */ // Label 1494: @63624
24548 /* 63624 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(63685), // Rule ID 2494 //
24549 /* 63629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24550 /* 63632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24551 /* 63636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24552 /* 63640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24553 /* 63644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24554 /* 63648 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24555 /* 63652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24556 /* 63656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24557 /* 63661 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24558 /* 63666 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24559 /* 63668 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24560 /* 63668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24561 /* 63671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24562 /* 63673 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24563 /* 63675 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24564 /* 63679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24565 /* 63683 */ GIR_RootConstrainSelectedInstOperands,
24566 /* 63684 */ // GIR_Coverage, 2494,
24567 /* 63684 */ GIR_EraseRootFromParent_Done,
24568 /* 63685 */ // Label 1495: @63685
24569 /* 63685 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(63746), // Rule ID 2498 //
24570 /* 63690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24571 /* 63693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24572 /* 63697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24573 /* 63701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24574 /* 63705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24575 /* 63709 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24576 /* 63713 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24577 /* 63717 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24578 /* 63722 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24579 /* 63727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24580 /* 63729 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24581 /* 63729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24582 /* 63732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24583 /* 63734 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24584 /* 63736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24585 /* 63740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24586 /* 63744 */ GIR_RootConstrainSelectedInstOperands,
24587 /* 63745 */ // GIR_Coverage, 2498,
24588 /* 63745 */ GIR_EraseRootFromParent_Done,
24589 /* 63746 */ // Label 1496: @63746
24590 /* 63746 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(63807), // Rule ID 2493 //
24591 /* 63751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24592 /* 63754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24593 /* 63758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24594 /* 63762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24595 /* 63766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24596 /* 63770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24597 /* 63774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24598 /* 63778 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24599 /* 63783 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24600 /* 63788 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24601 /* 63790 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24602 /* 63790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
24603 /* 63793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24604 /* 63795 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24605 /* 63797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24606 /* 63801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24607 /* 63805 */ GIR_RootConstrainSelectedInstOperands,
24608 /* 63806 */ // GIR_Coverage, 2493,
24609 /* 63806 */ GIR_EraseRootFromParent_Done,
24610 /* 63807 */ // Label 1497: @63807
24611 /* 63807 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(63868), // Rule ID 2497 //
24612 /* 63812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24613 /* 63815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24614 /* 63819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24615 /* 63823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24616 /* 63827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24617 /* 63831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24618 /* 63835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24619 /* 63839 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24620 /* 63844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24621 /* 63849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24622 /* 63851 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24623 /* 63851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
24624 /* 63854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24625 /* 63856 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
24626 /* 63858 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24627 /* 63862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24628 /* 63866 */ GIR_RootConstrainSelectedInstOperands,
24629 /* 63867 */ // GIR_Coverage, 2497,
24630 /* 63867 */ GIR_EraseRootFromParent_Done,
24631 /* 63868 */ // Label 1498: @63868
24632 /* 63868 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(63899), // Rule ID 154 //
24633 /* 63873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24634 /* 63876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24635 /* 63880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24636 /* 63884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24637 /* 63888 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24638 /* 63888 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
24639 /* 63893 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24640 /* 63897 */ GIR_RootConstrainSelectedInstOperands,
24641 /* 63898 */ // GIR_Coverage, 154,
24642 /* 63898 */ GIR_Done,
24643 /* 63899 */ // Label 1499: @63899
24644 /* 63899 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(63930), // Rule ID 156 //
24645 /* 63904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24646 /* 63907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24647 /* 63911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24648 /* 63915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24649 /* 63919 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24650 /* 63919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
24651 /* 63924 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24652 /* 63928 */ GIR_RootConstrainSelectedInstOperands,
24653 /* 63929 */ // GIR_Coverage, 156,
24654 /* 63929 */ GIR_Done,
24655 /* 63930 */ // Label 1500: @63930
24656 /* 63930 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(63961), // Rule ID 1158 //
24657 /* 63935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24658 /* 63938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24659 /* 63942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24660 /* 63946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24661 /* 63950 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24662 /* 63950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
24663 /* 63955 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24664 /* 63959 */ GIR_RootConstrainSelectedInstOperands,
24665 /* 63960 */ // GIR_Coverage, 1158,
24666 /* 63960 */ GIR_Done,
24667 /* 63961 */ // Label 1501: @63961
24668 /* 63961 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(63992), // Rule ID 1159 //
24669 /* 63966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24670 /* 63969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24671 /* 63973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24672 /* 63977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24673 /* 63981 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24674 /* 63981 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
24675 /* 63986 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24676 /* 63990 */ GIR_RootConstrainSelectedInstOperands,
24677 /* 63991 */ // GIR_Coverage, 1159,
24678 /* 63991 */ GIR_Done,
24679 /* 63992 */ // Label 1502: @63992
24680 /* 63992 */ GIM_Reject,
24681 /* 63993 */ // Label 1490: @63993
24682 /* 63993 */ GIM_Reject,
24683 /* 63994 */ // Label 1479: @63994
24684 /* 63994 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(64147),
24685 /* 63999 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24686 /* 64002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24687 /* 64005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24688 /* 64009 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(64066), // Rule ID 2633 //
24689 /* 64014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24690 /* 64017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24691 /* 64021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24692 /* 64025 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24693 /* 64029 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24694 /* 64033 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24695 /* 64038 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24696 /* 64043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24697 /* 64047 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24698 /* 64049 */ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24699 /* 64049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24700 /* 64052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24701 /* 64054 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24702 /* 64056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24703 /* 64060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24704 /* 64064 */ GIR_RootConstrainSelectedInstOperands,
24705 /* 64065 */ // GIR_Coverage, 2633,
24706 /* 64065 */ GIR_EraseRootFromParent_Done,
24707 /* 64066 */ // Label 1504: @64066
24708 /* 64066 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(64123), // Rule ID 2119 //
24709 /* 64071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24710 /* 64074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24711 /* 64078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24712 /* 64082 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24713 /* 64086 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
24714 /* 64090 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
24715 /* 64094 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24716 /* 64099 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24717 /* 64104 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24718 /* 64106 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24719 /* 64106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
24720 /* 64109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24721 /* 64111 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24722 /* 64113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24723 /* 64117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24724 /* 64121 */ GIR_RootConstrainSelectedInstOperands,
24725 /* 64122 */ // GIR_Coverage, 2119,
24726 /* 64122 */ GIR_EraseRootFromParent_Done,
24727 /* 64123 */ // Label 1505: @64123
24728 /* 64123 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(64146), // Rule ID 695 //
24729 /* 64128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24730 /* 64131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24731 /* 64135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24732 /* 64139 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
24733 /* 64139 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
24734 /* 64144 */ GIR_RootConstrainSelectedInstOperands,
24735 /* 64145 */ // GIR_Coverage, 695,
24736 /* 64145 */ GIR_Done,
24737 /* 64146 */ // Label 1506: @64146
24738 /* 64146 */ GIM_Reject,
24739 /* 64147 */ // Label 1503: @64147
24740 /* 64147 */ GIM_Reject,
24741 /* 64148 */ // Label 1480: @64148
24742 /* 64148 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(64301),
24743 /* 64153 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24744 /* 64156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24745 /* 64159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24746 /* 64163 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(64220), // Rule ID 2632 //
24747 /* 64168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24748 /* 64171 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24749 /* 64175 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24750 /* 64179 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24751 /* 64183 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24752 /* 64187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24753 /* 64192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24754 /* 64197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24755 /* 64201 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24756 /* 64203 */ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24757 /* 64203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24758 /* 64206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24759 /* 64208 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
24760 /* 64210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24761 /* 64214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24762 /* 64218 */ GIR_RootConstrainSelectedInstOperands,
24763 /* 64219 */ // GIR_Coverage, 2632,
24764 /* 64219 */ GIR_EraseRootFromParent_Done,
24765 /* 64220 */ // Label 1508: @64220
24766 /* 64220 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(64277), // Rule ID 2118 //
24767 /* 64225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
24768 /* 64228 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24769 /* 64232 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24770 /* 64236 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24771 /* 64240 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
24772 /* 64244 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
24773 /* 64248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24774 /* 64253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24775 /* 64258 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24776 /* 64260 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24777 /* 64260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
24778 /* 64263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24779 /* 64265 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
24780 /* 64267 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
24781 /* 64271 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
24782 /* 64275 */ GIR_RootConstrainSelectedInstOperands,
24783 /* 64276 */ // GIR_Coverage, 2118,
24784 /* 64276 */ GIR_EraseRootFromParent_Done,
24785 /* 64277 */ // Label 1509: @64277
24786 /* 64277 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(64300), // Rule ID 694 //
24787 /* 64282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24788 /* 64285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24789 /* 64289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24790 /* 64293 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
24791 /* 64293 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
24792 /* 64298 */ GIR_RootConstrainSelectedInstOperands,
24793 /* 64299 */ // GIR_Coverage, 694,
24794 /* 64299 */ GIR_Done,
24795 /* 64300 */ // Label 1510: @64300
24796 /* 64300 */ GIM_Reject,
24797 /* 64301 */ // Label 1507: @64301
24798 /* 64301 */ GIM_Reject,
24799 /* 64302 */ // Label 1481: @64302
24800 /* 64302 */ GIM_Reject,
24801 /* 64303 */ // Label 47: @64303
24802 /* 64303 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1515*/ GIMT_Encode4(65117),
24803 /* 64314 */ /*GILLT_s32*//*Label 1511*/ GIMT_Encode4(64338),
24804 /* 64318 */ /*GILLT_s64*//*Label 1512*/ GIMT_Encode4(64550), GIMT_Encode4(0),
24805 /* 64326 */ /*GILLT_v2s64*//*Label 1513*/ GIMT_Encode4(64931), GIMT_Encode4(0),
24806 /* 64334 */ /*GILLT_v4s32*//*Label 1514*/ GIMT_Encode4(65024),
24807 /* 64338 */ // Label 1511: @64338
24808 /* 64338 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(64549),
24809 /* 64343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24810 /* 64346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24811 /* 64349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24812 /* 64353 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(64410), // Rule ID 182 //
24813 /* 64358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24814 /* 64361 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24815 /* 64365 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24816 /* 64369 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24817 /* 64373 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24818 /* 64377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24819 /* 64382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24820 /* 64387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24821 /* 64391 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24822 /* 64393 */ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24823 /* 64393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
24824 /* 64396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24825 /* 64398 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24826 /* 64400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24827 /* 64404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24828 /* 64408 */ GIR_RootConstrainSelectedInstOperands,
24829 /* 64409 */ // GIR_Coverage, 182,
24830 /* 64409 */ GIR_EraseRootFromParent_Done,
24831 /* 64410 */ // Label 1517: @64410
24832 /* 64410 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(64467), // Rule ID 181 //
24833 /* 64415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24834 /* 64418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24835 /* 64422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24836 /* 64426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24837 /* 64430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24838 /* 64434 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24839 /* 64439 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24840 /* 64444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24841 /* 64448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24842 /* 64450 */ // (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24843 /* 64450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
24844 /* 64453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24845 /* 64455 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24846 /* 64457 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24847 /* 64461 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24848 /* 64465 */ GIR_RootConstrainSelectedInstOperands,
24849 /* 64466 */ // GIR_Coverage, 181,
24850 /* 64466 */ GIR_EraseRootFromParent_Done,
24851 /* 64467 */ // Label 1518: @64467
24852 /* 64467 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(64494), // Rule ID 170 //
24853 /* 64472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
24854 /* 64475 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24855 /* 64479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24856 /* 64483 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24857 /* 64483 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
24858 /* 64488 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24859 /* 64492 */ GIR_RootConstrainSelectedInstOperands,
24860 /* 64493 */ // GIR_Coverage, 170,
24861 /* 64493 */ GIR_Done,
24862 /* 64494 */ // Label 1519: @64494
24863 /* 64494 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(64521), // Rule ID 1157 //
24864 /* 64499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
24865 /* 64502 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24866 /* 64506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24867 /* 64510 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
24868 /* 64510 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
24869 /* 64515 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24870 /* 64519 */ GIR_RootConstrainSelectedInstOperands,
24871 /* 64520 */ // GIR_Coverage, 1157,
24872 /* 64520 */ GIR_Done,
24873 /* 64521 */ // Label 1520: @64521
24874 /* 64521 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(64548), // Rule ID 1212 //
24875 /* 64526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
24876 /* 64529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24877 /* 64533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24878 /* 64537 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
24879 /* 64537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
24880 /* 64540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24881 /* 64542 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
24882 /* 64544 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
24883 /* 64546 */ GIR_RootConstrainSelectedInstOperands,
24884 /* 64547 */ // GIR_Coverage, 1212,
24885 /* 64547 */ GIR_EraseRootFromParent_Done,
24886 /* 64548 */ // Label 1521: @64548
24887 /* 64548 */ GIM_Reject,
24888 /* 64549 */ // Label 1516: @64549
24889 /* 64549 */ GIM_Reject,
24890 /* 64550 */ // Label 1512: @64550
24891 /* 64550 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(64930),
24892 /* 64555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24893 /* 64558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24894 /* 64561 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(64622), // Rule ID 190 //
24895 /* 64566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24896 /* 64569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24897 /* 64573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24898 /* 64577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24899 /* 64581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24900 /* 64585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24901 /* 64589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24902 /* 64594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24903 /* 64599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24904 /* 64603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24905 /* 64605 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24906 /* 64605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
24907 /* 64608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24908 /* 64610 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24909 /* 64612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24910 /* 64616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24911 /* 64620 */ GIR_RootConstrainSelectedInstOperands,
24912 /* 64621 */ // GIR_Coverage, 190,
24913 /* 64621 */ GIR_EraseRootFromParent_Done,
24914 /* 64622 */ // Label 1523: @64622
24915 /* 64622 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(64683), // Rule ID 198 //
24916 /* 64627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24917 /* 64630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24918 /* 64634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24919 /* 64638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
24920 /* 64642 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24921 /* 64646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24922 /* 64650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24923 /* 64655 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24924 /* 64660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24925 /* 64664 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24926 /* 64666 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24927 /* 64666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
24928 /* 64669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24929 /* 64671 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24930 /* 64673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24931 /* 64677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24932 /* 64681 */ GIR_RootConstrainSelectedInstOperands,
24933 /* 64682 */ // GIR_Coverage, 198,
24934 /* 64682 */ GIR_EraseRootFromParent_Done,
24935 /* 64683 */ // Label 1524: @64683
24936 /* 64683 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(64744), // Rule ID 189 //
24937 /* 64688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24938 /* 64691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24939 /* 64695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24940 /* 64699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24941 /* 64703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24942 /* 64707 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24943 /* 64711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24944 /* 64716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24945 /* 64721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24946 /* 64725 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24947 /* 64727 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24948 /* 64727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
24949 /* 64730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24950 /* 64732 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24951 /* 64734 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24952 /* 64738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24953 /* 64742 */ GIR_RootConstrainSelectedInstOperands,
24954 /* 64743 */ // GIR_Coverage, 189,
24955 /* 64743 */ GIR_EraseRootFromParent_Done,
24956 /* 64744 */ // Label 1525: @64744
24957 /* 64744 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(64805), // Rule ID 197 //
24958 /* 64749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
24959 /* 64752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24960 /* 64756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24961 /* 64760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
24962 /* 64764 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24963 /* 64768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24964 /* 64772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24965 /* 64777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24966 /* 64782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24967 /* 64786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24968 /* 64788 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24969 /* 64788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
24970 /* 64791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24971 /* 64793 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
24972 /* 64795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
24973 /* 64799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
24974 /* 64803 */ GIR_RootConstrainSelectedInstOperands,
24975 /* 64804 */ // GIR_Coverage, 197,
24976 /* 64804 */ GIR_EraseRootFromParent_Done,
24977 /* 64805 */ // Label 1526: @64805
24978 /* 64805 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(64836), // Rule ID 172 //
24979 /* 64810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24980 /* 64813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24981 /* 64817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24982 /* 64821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24983 /* 64825 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24984 /* 64825 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
24985 /* 64830 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24986 /* 64834 */ GIR_RootConstrainSelectedInstOperands,
24987 /* 64835 */ // GIR_Coverage, 172,
24988 /* 64835 */ GIR_Done,
24989 /* 64836 */ // Label 1527: @64836
24990 /* 64836 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(64867), // Rule ID 174 //
24991 /* 64841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24992 /* 64844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24993 /* 64848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24994 /* 64852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24995 /* 64856 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24996 /* 64856 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
24997 /* 64861 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
24998 /* 64865 */ GIR_RootConstrainSelectedInstOperands,
24999 /* 64866 */ // GIR_Coverage, 174,
25000 /* 64866 */ GIR_Done,
25001 /* 64867 */ // Label 1528: @64867
25002 /* 64867 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(64898), // Rule ID 1164 //
25003 /* 64872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25004 /* 64875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25005 /* 64879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25006 /* 64883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25007 /* 64887 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25008 /* 64887 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
25009 /* 64892 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25010 /* 64896 */ GIR_RootConstrainSelectedInstOperands,
25011 /* 64897 */ // GIR_Coverage, 1164,
25012 /* 64897 */ GIR_Done,
25013 /* 64898 */ // Label 1529: @64898
25014 /* 64898 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(64929), // Rule ID 1165 //
25015 /* 64903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25016 /* 64906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25017 /* 64910 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25018 /* 64914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25019 /* 64918 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25020 /* 64918 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
25021 /* 64923 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25022 /* 64927 */ GIR_RootConstrainSelectedInstOperands,
25023 /* 64928 */ // GIR_Coverage, 1165,
25024 /* 64928 */ GIR_Done,
25025 /* 64929 */ // Label 1530: @64929
25026 /* 64929 */ GIM_Reject,
25027 /* 64930 */ // Label 1522: @64930
25028 /* 64930 */ GIM_Reject,
25029 /* 64931 */ // Label 1513: @64931
25030 /* 64931 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(65023),
25031 /* 64936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25032 /* 64939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25033 /* 64942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25034 /* 64946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25035 /* 64950 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(65003), // Rule ID 2117 //
25036 /* 64955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
25037 /* 64958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25038 /* 64962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25039 /* 64966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25040 /* 64970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
25041 /* 64974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25042 /* 64979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25043 /* 64984 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25044 /* 64986 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25045 /* 64986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
25046 /* 64989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25047 /* 64991 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
25048 /* 64993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
25049 /* 64997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
25050 /* 65001 */ GIR_RootConstrainSelectedInstOperands,
25051 /* 65002 */ // GIR_Coverage, 2117,
25052 /* 65002 */ GIR_EraseRootFromParent_Done,
25053 /* 65003 */ // Label 1532: @65003
25054 /* 65003 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(65022), // Rule ID 783 //
25055 /* 65008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25056 /* 65011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25057 /* 65015 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25058 /* 65015 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
25059 /* 65020 */ GIR_RootConstrainSelectedInstOperands,
25060 /* 65021 */ // GIR_Coverage, 783,
25061 /* 65021 */ GIR_Done,
25062 /* 65022 */ // Label 1533: @65022
25063 /* 65022 */ GIM_Reject,
25064 /* 65023 */ // Label 1531: @65023
25065 /* 65023 */ GIM_Reject,
25066 /* 65024 */ // Label 1514: @65024
25067 /* 65024 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(65116),
25068 /* 65029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25069 /* 65032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25070 /* 65035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25071 /* 65039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25072 /* 65043 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(65096), // Rule ID 2116 //
25073 /* 65048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
25074 /* 65051 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25075 /* 65055 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25076 /* 65059 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25077 /* 65063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
25078 /* 65067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25079 /* 65072 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25080 /* 65077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25081 /* 65079 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25082 /* 65079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
25083 /* 65082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25084 /* 65084 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
25085 /* 65086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
25086 /* 65090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
25087 /* 65094 */ GIR_RootConstrainSelectedInstOperands,
25088 /* 65095 */ // GIR_Coverage, 2116,
25089 /* 65095 */ GIR_EraseRootFromParent_Done,
25090 /* 65096 */ // Label 1535: @65096
25091 /* 65096 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(65115), // Rule ID 782 //
25092 /* 65101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25093 /* 65104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25094 /* 65108 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25095 /* 65108 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
25096 /* 65113 */ GIR_RootConstrainSelectedInstOperands,
25097 /* 65114 */ // GIR_Coverage, 782,
25098 /* 65114 */ GIR_Done,
25099 /* 65115 */ // Label 1536: @65115
25100 /* 65115 */ GIM_Reject,
25101 /* 65116 */ // Label 1534: @65116
25102 /* 65116 */ GIM_Reject,
25103 /* 65117 */ // Label 1515: @65117
25104 /* 65117 */ GIM_Reject,
25105 /* 65118 */ // Label 48: @65118
25106 /* 65118 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1541*/ GIMT_Encode4(65628),
25107 /* 65129 */ /*GILLT_s32*//*Label 1537*/ GIMT_Encode4(65153),
25108 /* 65133 */ /*GILLT_s64*//*Label 1538*/ GIMT_Encode4(65235), GIMT_Encode4(0),
25109 /* 65141 */ /*GILLT_v2s64*//*Label 1539*/ GIMT_Encode4(65372), GIMT_Encode4(0),
25110 /* 65149 */ /*GILLT_v4s32*//*Label 1540*/ GIMT_Encode4(65500),
25111 /* 65153 */ // Label 1537: @65153
25112 /* 65153 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(65234),
25113 /* 65158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25114 /* 65161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25115 /* 65164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25116 /* 65168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25117 /* 65172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25118 /* 65176 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(65195), // Rule ID 164 //
25119 /* 65181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
25120 /* 65184 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25121 /* 65184 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
25122 /* 65189 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25123 /* 65193 */ GIR_RootConstrainSelectedInstOperands,
25124 /* 65194 */ // GIR_Coverage, 164,
25125 /* 65194 */ GIR_Done,
25126 /* 65195 */ // Label 1543: @65195
25127 /* 65195 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(65214), // Rule ID 1156 //
25128 /* 65200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25129 /* 65203 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25130 /* 65203 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
25131 /* 65208 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25132 /* 65212 */ GIR_RootConstrainSelectedInstOperands,
25133 /* 65213 */ // GIR_Coverage, 1156,
25134 /* 65213 */ GIR_Done,
25135 /* 65214 */ // Label 1544: @65214
25136 /* 65214 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(65233), // Rule ID 1213 //
25137 /* 65219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25138 /* 65222 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
25139 /* 65222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
25140 /* 65225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25141 /* 65227 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
25142 /* 65229 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
25143 /* 65231 */ GIR_RootConstrainSelectedInstOperands,
25144 /* 65232 */ // GIR_Coverage, 1213,
25145 /* 65232 */ GIR_EraseRootFromParent_Done,
25146 /* 65233 */ // Label 1545: @65233
25147 /* 65233 */ GIM_Reject,
25148 /* 65234 */ // Label 1542: @65234
25149 /* 65234 */ GIM_Reject,
25150 /* 65235 */ // Label 1538: @65235
25151 /* 65235 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(65371),
25152 /* 65240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25153 /* 65243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25154 /* 65246 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(65277), // Rule ID 166 //
25155 /* 65251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25156 /* 65254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25157 /* 65258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25158 /* 65262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25159 /* 65266 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25160 /* 65266 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
25161 /* 65271 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25162 /* 65275 */ GIR_RootConstrainSelectedInstOperands,
25163 /* 65276 */ // GIR_Coverage, 166,
25164 /* 65276 */ GIR_Done,
25165 /* 65277 */ // Label 1547: @65277
25166 /* 65277 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(65308), // Rule ID 168 //
25167 /* 65282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
25168 /* 65285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25169 /* 65289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25170 /* 65293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25171 /* 65297 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25172 /* 65297 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
25173 /* 65302 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25174 /* 65306 */ GIR_RootConstrainSelectedInstOperands,
25175 /* 65307 */ // GIR_Coverage, 168,
25176 /* 65307 */ GIR_Done,
25177 /* 65308 */ // Label 1548: @65308
25178 /* 65308 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(65339), // Rule ID 1162 //
25179 /* 65313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25180 /* 65316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25181 /* 65320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25182 /* 65324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25183 /* 65328 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25184 /* 65328 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
25185 /* 65333 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25186 /* 65337 */ GIR_RootConstrainSelectedInstOperands,
25187 /* 65338 */ // GIR_Coverage, 1162,
25188 /* 65338 */ GIR_Done,
25189 /* 65339 */ // Label 1549: @65339
25190 /* 65339 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(65370), // Rule ID 1163 //
25191 /* 65344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25192 /* 65347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25193 /* 65351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25194 /* 65355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25195 /* 65359 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25196 /* 65359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
25197 /* 65364 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25198 /* 65368 */ GIR_RootConstrainSelectedInstOperands,
25199 /* 65369 */ // GIR_Coverage, 1163,
25200 /* 65369 */ GIR_Done,
25201 /* 65370 */ // Label 1550: @65370
25202 /* 65370 */ GIM_Reject,
25203 /* 65371 */ // Label 1546: @65371
25204 /* 65371 */ GIM_Reject,
25205 /* 65372 */ // Label 1539: @65372
25206 /* 65372 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(65499),
25207 /* 65377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25208 /* 65380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25209 /* 65383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25210 /* 65387 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(65431), // Rule ID 2536 //
25211 /* 65392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25212 /* 65395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25213 /* 65399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25214 /* 65403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25215 /* 65407 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25216 /* 65412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25217 /* 65416 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25218 /* 65418 */ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25219 /* 65418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
25220 /* 65421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25221 /* 65423 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
25222 /* 65425 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25223 /* 65429 */ GIR_RootConstrainSelectedInstOperands,
25224 /* 65430 */ // GIR_Coverage, 2536,
25225 /* 65430 */ GIR_EraseRootFromParent_Done,
25226 /* 65431 */ // Label 1552: @65431
25227 /* 65431 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(65475), // Rule ID 725 //
25228 /* 65436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25229 /* 65439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25230 /* 65443 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25231 /* 65447 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25232 /* 65451 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
25233 /* 65455 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25234 /* 65460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25235 /* 65462 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25236 /* 65462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
25237 /* 65465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25238 /* 65467 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
25239 /* 65469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25240 /* 65473 */ GIR_RootConstrainSelectedInstOperands,
25241 /* 65474 */ // GIR_Coverage, 725,
25242 /* 65474 */ GIR_EraseRootFromParent_Done,
25243 /* 65475 */ // Label 1553: @65475
25244 /* 65475 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(65498), // Rule ID 761 //
25245 /* 65480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25246 /* 65483 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25247 /* 65487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25248 /* 65491 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25249 /* 65491 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
25250 /* 65496 */ GIR_RootConstrainSelectedInstOperands,
25251 /* 65497 */ // GIR_Coverage, 761,
25252 /* 65497 */ GIR_Done,
25253 /* 65498 */ // Label 1554: @65498
25254 /* 65498 */ GIM_Reject,
25255 /* 65499 */ // Label 1551: @65499
25256 /* 65499 */ GIM_Reject,
25257 /* 65500 */ // Label 1540: @65500
25258 /* 65500 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(65627),
25259 /* 65505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25260 /* 65508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25261 /* 65511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25262 /* 65515 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(65559), // Rule ID 2535 //
25263 /* 65520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25264 /* 65523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25265 /* 65527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25266 /* 65531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25267 /* 65535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25268 /* 65540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25269 /* 65544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25270 /* 65546 */ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25271 /* 65546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
25272 /* 65549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25273 /* 65551 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
25274 /* 65553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25275 /* 65557 */ GIR_RootConstrainSelectedInstOperands,
25276 /* 65558 */ // GIR_Coverage, 2535,
25277 /* 65558 */ GIR_EraseRootFromParent_Done,
25278 /* 65559 */ // Label 1556: @65559
25279 /* 65559 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(65603), // Rule ID 724 //
25280 /* 65564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25281 /* 65567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25282 /* 65571 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25283 /* 65575 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
25284 /* 65579 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
25285 /* 65583 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25286 /* 65588 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25287 /* 65590 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25288 /* 65590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
25289 /* 65593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25290 /* 65595 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
25291 /* 65597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
25292 /* 65601 */ GIR_RootConstrainSelectedInstOperands,
25293 /* 65602 */ // GIR_Coverage, 724,
25294 /* 65602 */ GIR_EraseRootFromParent_Done,
25295 /* 65603 */ // Label 1557: @65603
25296 /* 65603 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(65626), // Rule ID 760 //
25297 /* 65608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25298 /* 65611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25299 /* 65615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25300 /* 65619 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25301 /* 65619 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
25302 /* 65624 */ GIR_RootConstrainSelectedInstOperands,
25303 /* 65625 */ // GIR_Coverage, 760,
25304 /* 65625 */ GIR_Done,
25305 /* 65626 */ // Label 1558: @65626
25306 /* 65626 */ GIM_Reject,
25307 /* 65627 */ // Label 1555: @65627
25308 /* 65627 */ GIM_Reject,
25309 /* 65628 */ // Label 1541: @65628
25310 /* 65628 */ GIM_Reject,
25311 /* 65629 */ // Label 49: @65629
25312 /* 65629 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1561*/ GIMT_Encode4(65734),
25313 /* 65640 */ /*GILLT_v2s64*//*Label 1559*/ GIMT_Encode4(65652), GIMT_Encode4(0),
25314 /* 65648 */ /*GILLT_v4s32*//*Label 1560*/ GIMT_Encode4(65693),
25315 /* 65652 */ // Label 1559: @65652
25316 /* 65652 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(65692), // Rule ID 749 //
25317 /* 65657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25318 /* 65660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25319 /* 65663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25320 /* 65666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
25321 /* 65669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25322 /* 65673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25323 /* 65677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25324 /* 65681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25325 /* 65685 */ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25326 /* 65685 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
25327 /* 65690 */ GIR_RootConstrainSelectedInstOperands,
25328 /* 65691 */ // GIR_Coverage, 749,
25329 /* 65691 */ GIR_Done,
25330 /* 65692 */ // Label 1562: @65692
25331 /* 65692 */ GIM_Reject,
25332 /* 65693 */ // Label 1560: @65693
25333 /* 65693 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(65733), // Rule ID 748 //
25334 /* 65698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25335 /* 65701 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25336 /* 65704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25337 /* 65707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25338 /* 65710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25339 /* 65714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25340 /* 65718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25341 /* 65722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25342 /* 65726 */ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25343 /* 65726 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
25344 /* 65731 */ GIR_RootConstrainSelectedInstOperands,
25345 /* 65732 */ // GIR_Coverage, 748,
25346 /* 65732 */ GIR_Done,
25347 /* 65733 */ // Label 1563: @65733
25348 /* 65733 */ GIM_Reject,
25349 /* 65734 */ // Label 1561: @65734
25350 /* 65734 */ GIM_Reject,
25351 /* 65735 */ // Label 50: @65735
25352 /* 65735 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1568*/ GIMT_Encode4(66057),
25353 /* 65746 */ /*GILLT_s32*//*Label 1564*/ GIMT_Encode4(65770),
25354 /* 65750 */ /*GILLT_s64*//*Label 1565*/ GIMT_Encode4(65852), GIMT_Encode4(0),
25355 /* 65758 */ /*GILLT_v2s64*//*Label 1566*/ GIMT_Encode4(65989), GIMT_Encode4(0),
25356 /* 65766 */ /*GILLT_v4s32*//*Label 1567*/ GIMT_Encode4(66023),
25357 /* 65770 */ // Label 1564: @65770
25358 /* 65770 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(65851),
25359 /* 65775 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25360 /* 65778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25361 /* 65781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25362 /* 65785 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25363 /* 65789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25364 /* 65793 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(65812), // Rule ID 158 //
25365 /* 65798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
25366 /* 65801 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25367 /* 65801 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
25368 /* 65806 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25369 /* 65810 */ GIR_RootConstrainSelectedInstOperands,
25370 /* 65811 */ // GIR_Coverage, 158,
25371 /* 65811 */ GIR_Done,
25372 /* 65812 */ // Label 1570: @65812
25373 /* 65812 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(65831), // Rule ID 1155 //
25374 /* 65817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25375 /* 65820 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25376 /* 65820 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
25377 /* 65825 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25378 /* 65829 */ GIR_RootConstrainSelectedInstOperands,
25379 /* 65830 */ // GIR_Coverage, 1155,
25380 /* 65830 */ GIR_Done,
25381 /* 65831 */ // Label 1571: @65831
25382 /* 65831 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(65850), // Rule ID 1214 //
25383 /* 65836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25384 /* 65839 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
25385 /* 65839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
25386 /* 65842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25387 /* 65844 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
25388 /* 65846 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
25389 /* 65848 */ GIR_RootConstrainSelectedInstOperands,
25390 /* 65849 */ // GIR_Coverage, 1214,
25391 /* 65849 */ GIR_EraseRootFromParent_Done,
25392 /* 65850 */ // Label 1572: @65850
25393 /* 65850 */ GIM_Reject,
25394 /* 65851 */ // Label 1569: @65851
25395 /* 65851 */ GIM_Reject,
25396 /* 65852 */ // Label 1565: @65852
25397 /* 65852 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(65988),
25398 /* 65857 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25399 /* 65860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25400 /* 65863 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(65894), // Rule ID 160 //
25401 /* 65868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25402 /* 65871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25403 /* 65875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25404 /* 65879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25405 /* 65883 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25406 /* 65883 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
25407 /* 65888 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25408 /* 65892 */ GIR_RootConstrainSelectedInstOperands,
25409 /* 65893 */ // GIR_Coverage, 160,
25410 /* 65893 */ GIR_Done,
25411 /* 65894 */ // Label 1574: @65894
25412 /* 65894 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(65925), // Rule ID 162 //
25413 /* 65899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
25414 /* 65902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25415 /* 65906 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25416 /* 65910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25417 /* 65914 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25418 /* 65914 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
25419 /* 65919 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25420 /* 65923 */ GIR_RootConstrainSelectedInstOperands,
25421 /* 65924 */ // GIR_Coverage, 162,
25422 /* 65924 */ GIR_Done,
25423 /* 65925 */ // Label 1575: @65925
25424 /* 65925 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(65956), // Rule ID 1160 //
25425 /* 65930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25426 /* 65933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25427 /* 65937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25428 /* 65941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25429 /* 65945 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25430 /* 65945 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
25431 /* 65950 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25432 /* 65954 */ GIR_RootConstrainSelectedInstOperands,
25433 /* 65955 */ // GIR_Coverage, 1160,
25434 /* 65955 */ GIR_Done,
25435 /* 65956 */ // Label 1576: @65956
25436 /* 65956 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(65987), // Rule ID 1161 //
25437 /* 65961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25438 /* 65964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25439 /* 65968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25440 /* 65972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25441 /* 65976 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25442 /* 65976 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
25443 /* 65981 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25444 /* 65985 */ GIR_RootConstrainSelectedInstOperands,
25445 /* 65986 */ // GIR_Coverage, 1161,
25446 /* 65986 */ GIR_Done,
25447 /* 65987 */ // Label 1577: @65987
25448 /* 65987 */ GIM_Reject,
25449 /* 65988 */ // Label 1573: @65988
25450 /* 65988 */ GIM_Reject,
25451 /* 65989 */ // Label 1566: @65989
25452 /* 65989 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(66022), // Rule ID 721 //
25453 /* 65994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25454 /* 65997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25455 /* 66000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
25456 /* 66003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25457 /* 66007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25458 /* 66011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25459 /* 66015 */ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
25460 /* 66015 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
25461 /* 66020 */ GIR_RootConstrainSelectedInstOperands,
25462 /* 66021 */ // GIR_Coverage, 721,
25463 /* 66021 */ GIR_Done,
25464 /* 66022 */ // Label 1578: @66022
25465 /* 66022 */ GIM_Reject,
25466 /* 66023 */ // Label 1567: @66023
25467 /* 66023 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(66056), // Rule ID 720 //
25468 /* 66028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25469 /* 66031 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25470 /* 66034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25471 /* 66037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25472 /* 66041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25473 /* 66045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25474 /* 66049 */ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
25475 /* 66049 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
25476 /* 66054 */ GIR_RootConstrainSelectedInstOperands,
25477 /* 66055 */ // GIR_Coverage, 720,
25478 /* 66055 */ GIR_Done,
25479 /* 66056 */ // Label 1579: @66056
25480 /* 66056 */ GIM_Reject,
25481 /* 66057 */ // Label 1568: @66057
25482 /* 66057 */ GIM_Reject,
25483 /* 66058 */ // Label 51: @66058
25484 /* 66058 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(66135),
25485 /* 66069 */ /*GILLT_v2s64*//*Label 1580*/ GIMT_Encode4(66081), GIMT_Encode4(0),
25486 /* 66077 */ /*GILLT_v4s32*//*Label 1581*/ GIMT_Encode4(66108),
25487 /* 66081 */ // Label 1580: @66081
25488 /* 66081 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(66107), // Rule ID 727 //
25489 /* 66086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25490 /* 66089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25491 /* 66092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25492 /* 66096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25493 /* 66100 */ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
25494 /* 66100 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
25495 /* 66105 */ GIR_RootConstrainSelectedInstOperands,
25496 /* 66106 */ // GIR_Coverage, 727,
25497 /* 66106 */ GIR_Done,
25498 /* 66107 */ // Label 1583: @66107
25499 /* 66107 */ GIM_Reject,
25500 /* 66108 */ // Label 1581: @66108
25501 /* 66108 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(66134), // Rule ID 726 //
25502 /* 66113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25503 /* 66116 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25504 /* 66119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25505 /* 66123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25506 /* 66127 */ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
25507 /* 66127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
25508 /* 66132 */ GIR_RootConstrainSelectedInstOperands,
25509 /* 66133 */ // GIR_Coverage, 726,
25510 /* 66133 */ GIR_Done,
25511 /* 66134 */ // Label 1584: @66134
25512 /* 66134 */ GIM_Reject,
25513 /* 66135 */ // Label 1582: @66135
25514 /* 66135 */ GIM_Reject,
25515 /* 66136 */ // Label 52: @66136
25516 /* 66136 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1587*/ GIMT_Encode4(66213),
25517 /* 66147 */ /*GILLT_v2s64*//*Label 1585*/ GIMT_Encode4(66159), GIMT_Encode4(0),
25518 /* 66155 */ /*GILLT_v4s32*//*Label 1586*/ GIMT_Encode4(66186),
25519 /* 66159 */ // Label 1585: @66159
25520 /* 66159 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(66185), // Rule ID 747 //
25521 /* 66164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25522 /* 66167 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25523 /* 66170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25524 /* 66174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25525 /* 66178 */ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25526 /* 66178 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
25527 /* 66183 */ GIR_RootConstrainSelectedInstOperands,
25528 /* 66184 */ // GIR_Coverage, 747,
25529 /* 66184 */ GIR_Done,
25530 /* 66185 */ // Label 1588: @66185
25531 /* 66185 */ GIM_Reject,
25532 /* 66186 */ // Label 1586: @66186
25533 /* 66186 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(66212), // Rule ID 746 //
25534 /* 66191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25535 /* 66194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25536 /* 66197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25537 /* 66201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25538 /* 66205 */ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25539 /* 66205 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
25540 /* 66210 */ GIR_RootConstrainSelectedInstOperands,
25541 /* 66211 */ // GIR_Coverage, 746,
25542 /* 66211 */ GIR_Done,
25543 /* 66212 */ // Label 1589: @66212
25544 /* 66212 */ GIM_Reject,
25545 /* 66213 */ // Label 1587: @66213
25546 /* 66213 */ GIM_Reject,
25547 /* 66214 */ // Label 53: @66214
25548 /* 66214 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1592*/ GIMT_Encode4(66406),
25549 /* 66225 */ /*GILLT_s32*//*Label 1590*/ GIMT_Encode4(66233),
25550 /* 66229 */ /*GILLT_s64*//*Label 1591*/ GIMT_Encode4(66296),
25551 /* 66233 */ // Label 1590: @66233
25552 /* 66233 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(66295),
25553 /* 66238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25554 /* 66241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25555 /* 66245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25556 /* 66249 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(66264), // Rule ID 126 //
25557 /* 66254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat),
25558 /* 66257 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25559 /* 66257 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
25560 /* 66262 */ GIR_RootConstrainSelectedInstOperands,
25561 /* 66263 */ // GIR_Coverage, 126,
25562 /* 66263 */ GIR_Done,
25563 /* 66264 */ // Label 1594: @66264
25564 /* 66264 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(66279), // Rule ID 1176 //
25565 /* 66269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25566 /* 66272 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25567 /* 66272 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
25568 /* 66277 */ GIR_RootConstrainSelectedInstOperands,
25569 /* 66278 */ // GIR_Coverage, 1176,
25570 /* 66278 */ GIR_Done,
25571 /* 66279 */ // Label 1595: @66279
25572 /* 66279 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(66294), // Rule ID 1215 //
25573 /* 66284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
25574 /* 66287 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25575 /* 66287 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
25576 /* 66292 */ GIR_RootConstrainSelectedInstOperands,
25577 /* 66293 */ // GIR_Coverage, 1215,
25578 /* 66293 */ GIR_Done,
25579 /* 66294 */ // Label 1596: @66294
25580 /* 66294 */ GIM_Reject,
25581 /* 66295 */ // Label 1593: @66295
25582 /* 66295 */ GIM_Reject,
25583 /* 66296 */ // Label 1591: @66296
25584 /* 66296 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(66405),
25585 /* 66301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25586 /* 66304 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(66331), // Rule ID 127 //
25587 /* 66309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25588 /* 66312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25589 /* 66316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25590 /* 66320 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25591 /* 66320 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
25592 /* 66325 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25593 /* 66329 */ GIR_RootConstrainSelectedInstOperands,
25594 /* 66330 */ // GIR_Coverage, 127,
25595 /* 66330 */ GIR_Done,
25596 /* 66331 */ // Label 1598: @66331
25597 /* 66331 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(66358), // Rule ID 128 //
25598 /* 66336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
25599 /* 66339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25600 /* 66343 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25601 /* 66347 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25602 /* 66347 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
25603 /* 66352 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25604 /* 66356 */ GIR_RootConstrainSelectedInstOperands,
25605 /* 66357 */ // GIR_Coverage, 128,
25606 /* 66357 */ GIR_Done,
25607 /* 66358 */ // Label 1599: @66358
25608 /* 66358 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(66381), // Rule ID 1177 //
25609 /* 66363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25610 /* 66366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25611 /* 66370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25612 /* 66374 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25613 /* 66374 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
25614 /* 66379 */ GIR_RootConstrainSelectedInstOperands,
25615 /* 66380 */ // GIR_Coverage, 1177,
25616 /* 66380 */ GIR_Done,
25617 /* 66381 */ // Label 1600: @66381
25618 /* 66381 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(66404), // Rule ID 1178 //
25619 /* 66386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25620 /* 66389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25621 /* 66393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25622 /* 66397 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25623 /* 66397 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
25624 /* 66402 */ GIR_RootConstrainSelectedInstOperands,
25625 /* 66403 */ // GIR_Coverage, 1178,
25626 /* 66403 */ GIR_Done,
25627 /* 66404 */ // Label 1601: @66404
25628 /* 66404 */ GIM_Reject,
25629 /* 66405 */ // Label 1597: @66405
25630 /* 66405 */ GIM_Reject,
25631 /* 66406 */ // Label 1592: @66406
25632 /* 66406 */ GIM_Reject,
25633 /* 66407 */ // Label 54: @66407
25634 /* 66407 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1604*/ GIMT_Encode4(66600),
25635 /* 66418 */ /*GILLT_s32*//*Label 1602*/ GIMT_Encode4(66426),
25636 /* 66422 */ /*GILLT_s64*//*Label 1603*/ GIMT_Encode4(66453),
25637 /* 66426 */ // Label 1602: @66426
25638 /* 66426 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(66452), // Rule ID 1080 //
25639 /* 66431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25640 /* 66434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25641 /* 66437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25642 /* 66441 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25643 /* 66445 */ // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
25644 /* 66445 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_W_PSEUDO),
25645 /* 66450 */ GIR_RootConstrainSelectedInstOperands,
25646 /* 66451 */ // GIR_Coverage, 1080,
25647 /* 66451 */ GIR_Done,
25648 /* 66452 */ // Label 1605: @66452
25649 /* 66452 */ GIM_Reject,
25650 /* 66453 */ // Label 1603: @66453
25651 /* 66453 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(66479), // Rule ID 1082 //
25652 /* 66458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25653 /* 66461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
25654 /* 66464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25655 /* 66468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25656 /* 66472 */ // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
25657 /* 66472 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_D_PSEUDO),
25658 /* 66477 */ GIR_RootConstrainSelectedInstOperands,
25659 /* 66478 */ // GIR_Coverage, 1082,
25660 /* 66478 */ GIR_Done,
25661 /* 66479 */ // Label 1606: @66479
25662 /* 66479 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(66509), // Rule ID 1527 //
25663 /* 66484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
25664 /* 66487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25665 /* 66490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25666 /* 66494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25667 /* 66498 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25668 /* 66498 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
25669 /* 66503 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25670 /* 66507 */ GIR_RootConstrainSelectedInstOperands,
25671 /* 66508 */ // GIR_Coverage, 1527,
25672 /* 66508 */ GIR_Done,
25673 /* 66509 */ // Label 1607: @66509
25674 /* 66509 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(66539), // Rule ID 1542 //
25675 /* 66514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
25676 /* 66517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25677 /* 66520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25678 /* 66524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25679 /* 66528 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25680 /* 66528 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
25681 /* 66533 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25682 /* 66537 */ GIR_RootConstrainSelectedInstOperands,
25683 /* 66538 */ // GIR_Coverage, 1542,
25684 /* 66538 */ GIR_Done,
25685 /* 66539 */ // Label 1608: @66539
25686 /* 66539 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(66569), // Rule ID 2401 //
25687 /* 66544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
25688 /* 66547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25689 /* 66550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25690 /* 66554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25691 /* 66558 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25692 /* 66558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
25693 /* 66563 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25694 /* 66567 */ GIR_RootConstrainSelectedInstOperands,
25695 /* 66568 */ // GIR_Coverage, 2401,
25696 /* 66568 */ GIR_Done,
25697 /* 66569 */ // Label 1609: @66569
25698 /* 66569 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(66599), // Rule ID 2403 //
25699 /* 66574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
25700 /* 66577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25701 /* 66580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25702 /* 66584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25703 /* 66588 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
25704 /* 66588 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
25705 /* 66593 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25706 /* 66597 */ GIR_RootConstrainSelectedInstOperands,
25707 /* 66598 */ // GIR_Coverage, 2403,
25708 /* 66598 */ GIR_Done,
25709 /* 66599 */ // Label 1610: @66599
25710 /* 66599 */ GIM_Reject,
25711 /* 66600 */ // Label 1604: @66600
25712 /* 66600 */ GIM_Reject,
25713 /* 66601 */ // Label 55: @66601
25714 /* 66601 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1613*/ GIMT_Encode4(66779),
25715 /* 66612 */ /*GILLT_s16*//*Label 1611*/ GIMT_Encode4(66620),
25716 /* 66616 */ /*GILLT_s32*//*Label 1612*/ GIMT_Encode4(66673),
25717 /* 66620 */ // Label 1611: @66620
25718 /* 66620 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(66646), // Rule ID 1081 //
25719 /* 66625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25720 /* 66628 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25721 /* 66631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25722 /* 66635 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25723 /* 66639 */ // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
25724 /* 66639 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_W_PSEUDO),
25725 /* 66644 */ GIR_RootConstrainSelectedInstOperands,
25726 /* 66645 */ // GIR_Coverage, 1081,
25727 /* 66645 */ GIR_Done,
25728 /* 66646 */ // Label 1614: @66646
25729 /* 66646 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(66672), // Rule ID 1083 //
25730 /* 66651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25731 /* 66654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25732 /* 66657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
25733 /* 66661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25734 /* 66665 */ // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
25735 /* 66665 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_D_PSEUDO),
25736 /* 66670 */ GIR_RootConstrainSelectedInstOperands,
25737 /* 66671 */ // GIR_Coverage, 1083,
25738 /* 66671 */ GIR_Done,
25739 /* 66672 */ // Label 1615: @66672
25740 /* 66672 */ GIM_Reject,
25741 /* 66673 */ // Label 1612: @66673
25742 /* 66673 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(66778),
25743 /* 66678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25744 /* 66681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25745 /* 66685 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(66708), // Rule ID 1525 //
25746 /* 66690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
25747 /* 66693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25748 /* 66697 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25749 /* 66697 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
25750 /* 66702 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25751 /* 66706 */ GIR_RootConstrainSelectedInstOperands,
25752 /* 66707 */ // GIR_Coverage, 1525,
25753 /* 66707 */ GIR_Done,
25754 /* 66708 */ // Label 1617: @66708
25755 /* 66708 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(66731), // Rule ID 1540 //
25756 /* 66713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
25757 /* 66716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25758 /* 66720 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25759 /* 66720 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
25760 /* 66725 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25761 /* 66729 */ GIR_RootConstrainSelectedInstOperands,
25762 /* 66730 */ // GIR_Coverage, 1540,
25763 /* 66730 */ GIR_Done,
25764 /* 66731 */ // Label 1618: @66731
25765 /* 66731 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(66754), // Rule ID 2400 //
25766 /* 66736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
25767 /* 66739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25768 /* 66743 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
25769 /* 66743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
25770 /* 66748 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25771 /* 66752 */ GIR_RootConstrainSelectedInstOperands,
25772 /* 66753 */ // GIR_Coverage, 2400,
25773 /* 66753 */ GIR_Done,
25774 /* 66754 */ // Label 1619: @66754
25775 /* 66754 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(66777), // Rule ID 2402 //
25776 /* 66759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
25777 /* 66762 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25778 /* 66766 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
25779 /* 66766 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
25780 /* 66771 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25781 /* 66775 */ GIR_RootConstrainSelectedInstOperands,
25782 /* 66776 */ // GIR_Coverage, 2402,
25783 /* 66776 */ GIR_Done,
25784 /* 66777 */ // Label 1620: @66777
25785 /* 66777 */ GIM_Reject,
25786 /* 66778 */ // Label 1616: @66778
25787 /* 66778 */ GIM_Reject,
25788 /* 66779 */ // Label 1613: @66779
25789 /* 66779 */ GIM_Reject,
25790 /* 66780 */ // Label 56: @66780
25791 /* 66780 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1623*/ GIMT_Encode4(66857),
25792 /* 66791 */ /*GILLT_v2s64*//*Label 1621*/ GIMT_Encode4(66803), GIMT_Encode4(0),
25793 /* 66799 */ /*GILLT_v4s32*//*Label 1622*/ GIMT_Encode4(66830),
25794 /* 66803 */ // Label 1621: @66803
25795 /* 66803 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(66829), // Rule ID 801 //
25796 /* 66808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25797 /* 66811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25798 /* 66814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25799 /* 66818 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25800 /* 66822 */ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25801 /* 66822 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
25802 /* 66827 */ GIR_RootConstrainSelectedInstOperands,
25803 /* 66828 */ // GIR_Coverage, 801,
25804 /* 66828 */ GIR_Done,
25805 /* 66829 */ // Label 1624: @66829
25806 /* 66829 */ GIM_Reject,
25807 /* 66830 */ // Label 1622: @66830
25808 /* 66830 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(66856), // Rule ID 800 //
25809 /* 66835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25810 /* 66838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25811 /* 66841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25812 /* 66845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25813 /* 66849 */ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25814 /* 66849 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
25815 /* 66854 */ GIR_RootConstrainSelectedInstOperands,
25816 /* 66855 */ // GIR_Coverage, 800,
25817 /* 66855 */ GIR_Done,
25818 /* 66856 */ // Label 1625: @66856
25819 /* 66856 */ GIM_Reject,
25820 /* 66857 */ // Label 1623: @66857
25821 /* 66857 */ GIM_Reject,
25822 /* 66858 */ // Label 57: @66858
25823 /* 66858 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1628*/ GIMT_Encode4(66935),
25824 /* 66869 */ /*GILLT_v2s64*//*Label 1626*/ GIMT_Encode4(66881), GIMT_Encode4(0),
25825 /* 66877 */ /*GILLT_v4s32*//*Label 1627*/ GIMT_Encode4(66908),
25826 /* 66881 */ // Label 1626: @66881
25827 /* 66881 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(66907), // Rule ID 803 //
25828 /* 66886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25829 /* 66889 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25830 /* 66892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25831 /* 66896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25832 /* 66900 */ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25833 /* 66900 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
25834 /* 66905 */ GIR_RootConstrainSelectedInstOperands,
25835 /* 66906 */ // GIR_Coverage, 803,
25836 /* 66906 */ GIR_Done,
25837 /* 66907 */ // Label 1629: @66907
25838 /* 66907 */ GIM_Reject,
25839 /* 66908 */ // Label 1627: @66908
25840 /* 66908 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(66934), // Rule ID 802 //
25841 /* 66913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25842 /* 66916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25843 /* 66919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25844 /* 66923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25845 /* 66927 */ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25846 /* 66927 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
25847 /* 66932 */ GIR_RootConstrainSelectedInstOperands,
25848 /* 66933 */ // GIR_Coverage, 802,
25849 /* 66933 */ GIR_Done,
25850 /* 66934 */ // Label 1630: @66934
25851 /* 66934 */ GIM_Reject,
25852 /* 66935 */ // Label 1628: @66935
25853 /* 66935 */ GIM_Reject,
25854 /* 66936 */ // Label 58: @66936
25855 /* 66936 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1635*/ GIMT_Encode4(67188),
25856 /* 66947 */ /*GILLT_s32*//*Label 1631*/ GIMT_Encode4(66971),
25857 /* 66951 */ /*GILLT_s64*//*Label 1632*/ GIMT_Encode4(67055), GIMT_Encode4(0),
25858 /* 66959 */ /*GILLT_v2s64*//*Label 1633*/ GIMT_Encode4(67134), GIMT_Encode4(0),
25859 /* 66967 */ /*GILLT_v4s32*//*Label 1634*/ GIMT_Encode4(67161),
25860 /* 66971 */ // Label 1631: @66971
25861 /* 66971 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(66994), // Rule ID 1518 //
25862 /* 66976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25863 /* 66979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25864 /* 66983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25865 /* 66987 */ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
25866 /* 66987 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
25867 /* 66992 */ GIR_RootConstrainSelectedInstOperands,
25868 /* 66993 */ // GIR_Coverage, 1518,
25869 /* 66993 */ GIR_Done,
25870 /* 66994 */ // Label 1636: @66994
25871 /* 66994 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(67054), // Rule ID 1533 //
25872 /* 66999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25873 /* 67002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25874 /* 67005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25875 /* 67009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25876 /* 67013 */ // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
25877 /* 67013 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25878 /* 67016 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
25879 /* 67020 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25880 /* 67025 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
25881 /* 67029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25882 /* 67031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
25883 /* 67034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
25884 /* 67036 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
25885 /* 67043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
25886 /* 67048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
25887 /* 67053 */ // GIR_Coverage, 1533,
25888 /* 67053 */ GIR_EraseRootFromParent_Done,
25889 /* 67054 */ // Label 1637: @67054
25890 /* 67054 */ GIM_Reject,
25891 /* 67055 */ // Label 1632: @67055
25892 /* 67055 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(67081), // Rule ID 1522 //
25893 /* 67060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotFP64bit),
25894 /* 67063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25895 /* 67066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25896 /* 67070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25897 /* 67074 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25898 /* 67074 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
25899 /* 67079 */ GIR_RootConstrainSelectedInstOperands,
25900 /* 67080 */ // GIR_Coverage, 1522,
25901 /* 67080 */ GIR_Done,
25902 /* 67081 */ // Label 1638: @67081
25903 /* 67081 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(67107), // Rule ID 1531 //
25904 /* 67086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25905 /* 67089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25906 /* 67092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25907 /* 67096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25908 /* 67100 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
25909 /* 67100 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
25910 /* 67105 */ GIR_RootConstrainSelectedInstOperands,
25911 /* 67106 */ // GIR_Coverage, 1531,
25912 /* 67106 */ GIR_Done,
25913 /* 67107 */ // Label 1639: @67107
25914 /* 67107 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(67133), // Rule ID 1535 //
25915 /* 67112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
25916 /* 67115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25917 /* 67118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25918 /* 67122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25919 /* 67126 */ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
25920 /* 67126 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
25921 /* 67131 */ GIR_RootConstrainSelectedInstOperands,
25922 /* 67132 */ // GIR_Coverage, 1535,
25923 /* 67132 */ GIR_Done,
25924 /* 67133 */ // Label 1640: @67133
25925 /* 67133 */ GIM_Reject,
25926 /* 67134 */ // Label 1633: @67134
25927 /* 67134 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(67160), // Rule ID 733 //
25928 /* 67139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25929 /* 67142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25930 /* 67145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25931 /* 67149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25932 /* 67153 */ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25933 /* 67153 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
25934 /* 67158 */ GIR_RootConstrainSelectedInstOperands,
25935 /* 67159 */ // GIR_Coverage, 733,
25936 /* 67159 */ GIR_Done,
25937 /* 67160 */ // Label 1641: @67160
25938 /* 67160 */ GIM_Reject,
25939 /* 67161 */ // Label 1634: @67161
25940 /* 67161 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(67187), // Rule ID 732 //
25941 /* 67166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25942 /* 67169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25943 /* 67172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25944 /* 67176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25945 /* 67180 */ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25946 /* 67180 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
25947 /* 67185 */ GIR_RootConstrainSelectedInstOperands,
25948 /* 67186 */ // GIR_Coverage, 732,
25949 /* 67186 */ GIR_Done,
25950 /* 67187 */ // Label 1642: @67187
25951 /* 67187 */ GIM_Reject,
25952 /* 67188 */ // Label 1635: @67188
25953 /* 67188 */ GIM_Reject,
25954 /* 67189 */ // Label 59: @67189
25955 /* 67189 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1645*/ GIMT_Encode4(67266),
25956 /* 67200 */ /*GILLT_v2s64*//*Label 1643*/ GIMT_Encode4(67212), GIMT_Encode4(0),
25957 /* 67208 */ /*GILLT_v4s32*//*Label 1644*/ GIMT_Encode4(67239),
25958 /* 67212 */ // Label 1643: @67212
25959 /* 67212 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(67238), // Rule ID 735 //
25960 /* 67217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25961 /* 67220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25962 /* 67223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25963 /* 67227 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25964 /* 67231 */ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25965 /* 67231 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
25966 /* 67236 */ GIR_RootConstrainSelectedInstOperands,
25967 /* 67237 */ // GIR_Coverage, 735,
25968 /* 67237 */ GIR_Done,
25969 /* 67238 */ // Label 1646: @67238
25970 /* 67238 */ GIM_Reject,
25971 /* 67239 */ // Label 1644: @67239
25972 /* 67239 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(67265), // Rule ID 734 //
25973 /* 67244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25974 /* 67247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25975 /* 67250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25976 /* 67254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25977 /* 67258 */ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25978 /* 67258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
25979 /* 67263 */ GIR_RootConstrainSelectedInstOperands,
25980 /* 67264 */ // GIR_Coverage, 734,
25981 /* 67264 */ GIR_Done,
25982 /* 67265 */ // Label 1647: @67265
25983 /* 67265 */ GIM_Reject,
25984 /* 67266 */ // Label 1645: @67266
25985 /* 67266 */ GIM_Reject,
25986 /* 67267 */ // Label 60: @67267
25987 /* 67267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(7), /*)*//*default:*//*Label 1651*/ GIMT_Encode4(67408),
25988 /* 67278 */ /*GILLT_s64*//*Label 1648*/ GIMT_Encode4(67298), GIMT_Encode4(0),
25989 /* 67286 */ /*GILLT_v2s64*//*Label 1649*/ GIMT_Encode4(67354), GIMT_Encode4(0),
25990 /* 67294 */ /*GILLT_v4s32*//*Label 1650*/ GIMT_Encode4(67381),
25991 /* 67298 */ // Label 1648: @67298
25992 /* 67298 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(67353),
25993 /* 67303 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25994 /* 67306 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(67329), // Rule ID 1174 //
25995 /* 67311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25996 /* 67314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25997 /* 67318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25998 /* 67322 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25999 /* 67322 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
26000 /* 67327 */ GIR_RootConstrainSelectedInstOperands,
26001 /* 67328 */ // GIR_Coverage, 1174,
26002 /* 67328 */ GIR_Done,
26003 /* 67329 */ // Label 1653: @67329
26004 /* 67329 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(67352), // Rule ID 1175 //
26005 /* 67334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
26006 /* 67337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26007 /* 67341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26008 /* 67345 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
26009 /* 67345 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
26010 /* 67350 */ GIR_RootConstrainSelectedInstOperands,
26011 /* 67351 */ // GIR_Coverage, 1175,
26012 /* 67351 */ GIR_Done,
26013 /* 67352 */ // Label 1654: @67352
26014 /* 67352 */ GIM_Reject,
26015 /* 67353 */ // Label 1652: @67353
26016 /* 67353 */ GIM_Reject,
26017 /* 67354 */ // Label 1649: @67354
26018 /* 67354 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(67380), // Rule ID 1067 //
26019 /* 67359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26020 /* 67362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26021 /* 67365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26022 /* 67369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26023 /* 67373 */ // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
26024 /* 67373 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
26025 /* 67378 */ GIR_RootConstrainSelectedInstOperands,
26026 /* 67379 */ // GIR_Coverage, 1067,
26027 /* 67379 */ GIR_Done,
26028 /* 67380 */ // Label 1655: @67380
26029 /* 67380 */ GIM_Reject,
26030 /* 67381 */ // Label 1650: @67381
26031 /* 67381 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(67407), // Rule ID 1066 //
26032 /* 67386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26033 /* 67389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26034 /* 67392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26035 /* 67396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26036 /* 67400 */ // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
26037 /* 67400 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
26038 /* 67405 */ GIR_RootConstrainSelectedInstOperands,
26039 /* 67406 */ // GIR_Coverage, 1066,
26040 /* 67406 */ GIR_Done,
26041 /* 67407 */ // Label 1656: @67407
26042 /* 67407 */ GIM_Reject,
26043 /* 67408 */ // Label 1651: @67408
26044 /* 67408 */ GIM_Reject,
26045 /* 67409 */ // Label 61: @67409
26046 /* 67409 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1659*/ GIMT_Encode4(67482),
26047 /* 67420 */ /*GILLT_s32*//*Label 1657*/ GIMT_Encode4(67428),
26048 /* 67424 */ /*GILLT_s64*//*Label 1658*/ GIMT_Encode4(67455),
26049 /* 67428 */ // Label 1657: @67428
26050 /* 67428 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(67454), // Rule ID 1888 //
26051 /* 67433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26052 /* 67436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26053 /* 67439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26054 /* 67443 */ // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
26055 /* 67443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26056 /* 67446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
26057 /* 67448 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26058 /* 67450 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26059 /* 67452 */ GIR_RootConstrainSelectedInstOperands,
26060 /* 67453 */ // GIR_Coverage, 1888,
26061 /* 67453 */ GIR_EraseRootFromParent_Done,
26062 /* 67454 */ // Label 1660: @67454
26063 /* 67454 */ GIM_Reject,
26064 /* 67455 */ // Label 1658: @67455
26065 /* 67455 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(67481), // Rule ID 1889 //
26066 /* 67460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26067 /* 67463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26068 /* 67466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26069 /* 67470 */ // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
26070 /* 67470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26071 /* 67473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
26072 /* 67475 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26073 /* 67477 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
26074 /* 67479 */ GIR_RootConstrainSelectedInstOperands,
26075 /* 67480 */ // GIR_Coverage, 1889,
26076 /* 67480 */ GIR_EraseRootFromParent_Done,
26077 /* 67481 */ // Label 1661: @67481
26078 /* 67481 */ GIM_Reject,
26079 /* 67482 */ // Label 1659: @67482
26080 /* 67482 */ GIM_Reject,
26081 /* 67483 */ // Label 62: @67483
26082 /* 67483 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1664*/ GIMT_Encode4(67554),
26083 /* 67494 */ /*GILLT_s32*//*Label 1662*/ GIMT_Encode4(67502),
26084 /* 67498 */ /*GILLT_s64*//*Label 1663*/ GIMT_Encode4(67528),
26085 /* 67502 */ // Label 1662: @67502
26086 /* 67502 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(67527), // Rule ID 1885 //
26087 /* 67507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26088 /* 67510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26089 /* 67513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26090 /* 67516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26091 /* 67520 */ // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26092 /* 67520 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26093 /* 67525 */ GIR_RootConstrainSelectedInstOperands,
26094 /* 67526 */ // GIR_Coverage, 1885,
26095 /* 67526 */ GIR_Done,
26096 /* 67527 */ // Label 1665: @67527
26097 /* 67527 */ GIM_Reject,
26098 /* 67528 */ // Label 1663: @67528
26099 /* 67528 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(67553), // Rule ID 1887 //
26100 /* 67533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26101 /* 67536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26102 /* 67539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26103 /* 67542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26104 /* 67546 */ // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26105 /* 67546 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26106 /* 67551 */ GIR_RootConstrainSelectedInstOperands,
26107 /* 67552 */ // GIR_Coverage, 1887,
26108 /* 67552 */ GIR_Done,
26109 /* 67553 */ // Label 1666: @67553
26110 /* 67553 */ GIM_Reject,
26111 /* 67554 */ // Label 1664: @67554
26112 /* 67554 */ GIM_Reject,
26113 /* 67555 */ // Label 63: @67555
26114 /* 67555 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1669*/ GIMT_Encode4(67626),
26115 /* 67566 */ /*GILLT_s32*//*Label 1667*/ GIMT_Encode4(67574),
26116 /* 67570 */ /*GILLT_s64*//*Label 1668*/ GIMT_Encode4(67600),
26117 /* 67574 */ // Label 1667: @67574
26118 /* 67574 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(67599), // Rule ID 1881 //
26119 /* 67579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26120 /* 67582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26121 /* 67585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26122 /* 67588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26123 /* 67592 */ // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26124 /* 67592 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
26125 /* 67597 */ GIR_RootConstrainSelectedInstOperands,
26126 /* 67598 */ // GIR_Coverage, 1881,
26127 /* 67598 */ GIR_Done,
26128 /* 67599 */ // Label 1670: @67599
26129 /* 67599 */ GIM_Reject,
26130 /* 67600 */ // Label 1668: @67600
26131 /* 67600 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(67625), // Rule ID 1883 //
26132 /* 67605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26133 /* 67608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26134 /* 67611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26135 /* 67614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26136 /* 67618 */ // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26137 /* 67618 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
26138 /* 67623 */ GIR_RootConstrainSelectedInstOperands,
26139 /* 67624 */ // GIR_Coverage, 1883,
26140 /* 67624 */ GIR_Done,
26141 /* 67625 */ // Label 1671: @67625
26142 /* 67625 */ GIM_Reject,
26143 /* 67626 */ // Label 1669: @67626
26144 /* 67626 */ GIM_Reject,
26145 /* 67627 */ // Label 64: @67627
26146 /* 67627 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1674*/ GIMT_Encode4(67698),
26147 /* 67638 */ /*GILLT_s32*//*Label 1672*/ GIMT_Encode4(67646),
26148 /* 67642 */ /*GILLT_s64*//*Label 1673*/ GIMT_Encode4(67672),
26149 /* 67646 */ // Label 1672: @67646
26150 /* 67646 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(67671), // Rule ID 1884 //
26151 /* 67651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26152 /* 67654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26153 /* 67657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26154 /* 67660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26155 /* 67664 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26156 /* 67664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
26157 /* 67669 */ GIR_RootConstrainSelectedInstOperands,
26158 /* 67670 */ // GIR_Coverage, 1884,
26159 /* 67670 */ GIR_Done,
26160 /* 67671 */ // Label 1675: @67671
26161 /* 67671 */ GIM_Reject,
26162 /* 67672 */ // Label 1673: @67672
26163 /* 67672 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(67697), // Rule ID 1886 //
26164 /* 67677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26165 /* 67680 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26166 /* 67683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26167 /* 67686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26168 /* 67690 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26169 /* 67690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
26170 /* 67695 */ GIR_RootConstrainSelectedInstOperands,
26171 /* 67696 */ // GIR_Coverage, 1886,
26172 /* 67696 */ GIR_Done,
26173 /* 67697 */ // Label 1676: @67697
26174 /* 67697 */ GIM_Reject,
26175 /* 67698 */ // Label 1674: @67698
26176 /* 67698 */ GIM_Reject,
26177 /* 67699 */ // Label 65: @67699
26178 /* 67699 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1679*/ GIMT_Encode4(67770),
26179 /* 67710 */ /*GILLT_s32*//*Label 1677*/ GIMT_Encode4(67718),
26180 /* 67714 */ /*GILLT_s64*//*Label 1678*/ GIMT_Encode4(67744),
26181 /* 67718 */ // Label 1677: @67718
26182 /* 67718 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(67743), // Rule ID 1880 //
26183 /* 67723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26184 /* 67726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26185 /* 67729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26186 /* 67732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26187 /* 67736 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
26188 /* 67736 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
26189 /* 67741 */ GIR_RootConstrainSelectedInstOperands,
26190 /* 67742 */ // GIR_Coverage, 1880,
26191 /* 67742 */ GIR_Done,
26192 /* 67743 */ // Label 1680: @67743
26193 /* 67743 */ GIM_Reject,
26194 /* 67744 */ // Label 1678: @67744
26195 /* 67744 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(67769), // Rule ID 1882 //
26196 /* 67749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
26197 /* 67752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26198 /* 67755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26199 /* 67758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26200 /* 67762 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
26201 /* 67762 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
26202 /* 67767 */ GIR_RootConstrainSelectedInstOperands,
26203 /* 67768 */ // GIR_Coverage, 1882,
26204 /* 67768 */ GIR_Done,
26205 /* 67769 */ // Label 1681: @67769
26206 /* 67769 */ GIM_Reject,
26207 /* 67770 */ // Label 1679: @67770
26208 /* 67770 */ GIM_Reject,
26209 /* 67771 */ // Label 66: @67771
26210 /* 67771 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1686*/ GIMT_Encode4(67938),
26211 /* 67782 */ /*GILLT_v2s64*//*Label 1682*/ GIMT_Encode4(67802), GIMT_Encode4(0),
26212 /* 67790 */ /*GILLT_v4s32*//*Label 1683*/ GIMT_Encode4(67836),
26213 /* 67794 */ /*GILLT_v8s16*//*Label 1684*/ GIMT_Encode4(67870),
26214 /* 67798 */ /*GILLT_v16s8*//*Label 1685*/ GIMT_Encode4(67904),
26215 /* 67802 */ // Label 1682: @67802
26216 /* 67802 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(67835), // Rule ID 895 //
26217 /* 67807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26218 /* 67810 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26219 /* 67813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26220 /* 67816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26221 /* 67820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26222 /* 67824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26223 /* 67828 */ // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26224 /* 67828 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
26225 /* 67833 */ GIR_RootConstrainSelectedInstOperands,
26226 /* 67834 */ // GIR_Coverage, 895,
26227 /* 67834 */ GIR_Done,
26228 /* 67835 */ // Label 1687: @67835
26229 /* 67835 */ GIM_Reject,
26230 /* 67836 */ // Label 1683: @67836
26231 /* 67836 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(67869), // Rule ID 894 //
26232 /* 67841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26233 /* 67844 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26234 /* 67847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26235 /* 67850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26236 /* 67854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26237 /* 67858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26238 /* 67862 */ // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26239 /* 67862 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
26240 /* 67867 */ GIR_RootConstrainSelectedInstOperands,
26241 /* 67868 */ // GIR_Coverage, 894,
26242 /* 67868 */ GIR_Done,
26243 /* 67869 */ // Label 1688: @67869
26244 /* 67869 */ GIM_Reject,
26245 /* 67870 */ // Label 1684: @67870
26246 /* 67870 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(67903), // Rule ID 893 //
26247 /* 67875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26248 /* 67878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26249 /* 67881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26250 /* 67884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26251 /* 67888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26252 /* 67892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26253 /* 67896 */ // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26254 /* 67896 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
26255 /* 67901 */ GIR_RootConstrainSelectedInstOperands,
26256 /* 67902 */ // GIR_Coverage, 893,
26257 /* 67902 */ GIR_Done,
26258 /* 67903 */ // Label 1689: @67903
26259 /* 67903 */ GIM_Reject,
26260 /* 67904 */ // Label 1685: @67904
26261 /* 67904 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(67937), // Rule ID 892 //
26262 /* 67909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26263 /* 67912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26264 /* 67915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26265 /* 67918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26266 /* 67922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26267 /* 67926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26268 /* 67930 */ // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26269 /* 67930 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
26270 /* 67935 */ GIR_RootConstrainSelectedInstOperands,
26271 /* 67936 */ // GIR_Coverage, 892,
26272 /* 67936 */ GIR_Done,
26273 /* 67937 */ // Label 1690: @67937
26274 /* 67937 */ GIM_Reject,
26275 /* 67938 */ // Label 1686: @67938
26276 /* 67938 */ GIM_Reject,
26277 /* 67939 */ // Label 67: @67939
26278 /* 67939 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1695*/ GIMT_Encode4(68106),
26279 /* 67950 */ /*GILLT_v2s64*//*Label 1691*/ GIMT_Encode4(67970), GIMT_Encode4(0),
26280 /* 67958 */ /*GILLT_v4s32*//*Label 1692*/ GIMT_Encode4(68004),
26281 /* 67962 */ /*GILLT_v8s16*//*Label 1693*/ GIMT_Encode4(68038),
26282 /* 67966 */ /*GILLT_v16s8*//*Label 1694*/ GIMT_Encode4(68072),
26283 /* 67970 */ // Label 1691: @67970
26284 /* 67970 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(68003), // Rule ID 875 //
26285 /* 67975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26286 /* 67978 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26287 /* 67981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26288 /* 67984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26289 /* 67988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26290 /* 67992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26291 /* 67996 */ // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26292 /* 67996 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
26293 /* 68001 */ GIR_RootConstrainSelectedInstOperands,
26294 /* 68002 */ // GIR_Coverage, 875,
26295 /* 68002 */ GIR_Done,
26296 /* 68003 */ // Label 1696: @68003
26297 /* 68003 */ GIM_Reject,
26298 /* 68004 */ // Label 1692: @68004
26299 /* 68004 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(68037), // Rule ID 874 //
26300 /* 68009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26301 /* 68012 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26302 /* 68015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26303 /* 68018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26304 /* 68022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26305 /* 68026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26306 /* 68030 */ // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26307 /* 68030 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
26308 /* 68035 */ GIR_RootConstrainSelectedInstOperands,
26309 /* 68036 */ // GIR_Coverage, 874,
26310 /* 68036 */ GIR_Done,
26311 /* 68037 */ // Label 1697: @68037
26312 /* 68037 */ GIM_Reject,
26313 /* 68038 */ // Label 1693: @68038
26314 /* 68038 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(68071), // Rule ID 873 //
26315 /* 68043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26316 /* 68046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26317 /* 68049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26318 /* 68052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26319 /* 68056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26320 /* 68060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26321 /* 68064 */ // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26322 /* 68064 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
26323 /* 68069 */ GIR_RootConstrainSelectedInstOperands,
26324 /* 68070 */ // GIR_Coverage, 873,
26325 /* 68070 */ GIR_Done,
26326 /* 68071 */ // Label 1698: @68071
26327 /* 68071 */ GIM_Reject,
26328 /* 68072 */ // Label 1694: @68072
26329 /* 68072 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(68105), // Rule ID 872 //
26330 /* 68077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26331 /* 68080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26332 /* 68083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26333 /* 68086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26334 /* 68090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26335 /* 68094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26336 /* 68098 */ // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26337 /* 68098 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
26338 /* 68103 */ GIR_RootConstrainSelectedInstOperands,
26339 /* 68104 */ // GIR_Coverage, 872,
26340 /* 68104 */ GIR_Done,
26341 /* 68105 */ // Label 1699: @68105
26342 /* 68105 */ GIM_Reject,
26343 /* 68106 */ // Label 1695: @68106
26344 /* 68106 */ GIM_Reject,
26345 /* 68107 */ // Label 68: @68107
26346 /* 68107 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1704*/ GIMT_Encode4(68274),
26347 /* 68118 */ /*GILLT_v2s64*//*Label 1700*/ GIMT_Encode4(68138), GIMT_Encode4(0),
26348 /* 68126 */ /*GILLT_v4s32*//*Label 1701*/ GIMT_Encode4(68172),
26349 /* 68130 */ /*GILLT_v8s16*//*Label 1702*/ GIMT_Encode4(68206),
26350 /* 68134 */ /*GILLT_v16s8*//*Label 1703*/ GIMT_Encode4(68240),
26351 /* 68138 */ // Label 1700: @68138
26352 /* 68138 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(68171), // Rule ID 899 //
26353 /* 68143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26354 /* 68146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26355 /* 68149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26356 /* 68152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26357 /* 68156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26358 /* 68160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26359 /* 68164 */ // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26360 /* 68164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
26361 /* 68169 */ GIR_RootConstrainSelectedInstOperands,
26362 /* 68170 */ // GIR_Coverage, 899,
26363 /* 68170 */ GIR_Done,
26364 /* 68171 */ // Label 1705: @68171
26365 /* 68171 */ GIM_Reject,
26366 /* 68172 */ // Label 1701: @68172
26367 /* 68172 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(68205), // Rule ID 898 //
26368 /* 68177 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26369 /* 68180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26370 /* 68183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26371 /* 68186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26372 /* 68190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26373 /* 68194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26374 /* 68198 */ // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26375 /* 68198 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
26376 /* 68203 */ GIR_RootConstrainSelectedInstOperands,
26377 /* 68204 */ // GIR_Coverage, 898,
26378 /* 68204 */ GIR_Done,
26379 /* 68205 */ // Label 1706: @68205
26380 /* 68205 */ GIM_Reject,
26381 /* 68206 */ // Label 1702: @68206
26382 /* 68206 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(68239), // Rule ID 897 //
26383 /* 68211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26384 /* 68214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26385 /* 68217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26386 /* 68220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26387 /* 68224 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26388 /* 68228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26389 /* 68232 */ // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26390 /* 68232 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
26391 /* 68237 */ GIR_RootConstrainSelectedInstOperands,
26392 /* 68238 */ // GIR_Coverage, 897,
26393 /* 68238 */ GIR_Done,
26394 /* 68239 */ // Label 1707: @68239
26395 /* 68239 */ GIM_Reject,
26396 /* 68240 */ // Label 1703: @68240
26397 /* 68240 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(68273), // Rule ID 896 //
26398 /* 68245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26399 /* 68248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26400 /* 68251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26401 /* 68254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26402 /* 68258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26403 /* 68262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26404 /* 68266 */ // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26405 /* 68266 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
26406 /* 68271 */ GIR_RootConstrainSelectedInstOperands,
26407 /* 68272 */ // GIR_Coverage, 896,
26408 /* 68272 */ GIR_Done,
26409 /* 68273 */ // Label 1708: @68273
26410 /* 68273 */ GIM_Reject,
26411 /* 68274 */ // Label 1704: @68274
26412 /* 68274 */ GIM_Reject,
26413 /* 68275 */ // Label 69: @68275
26414 /* 68275 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1713*/ GIMT_Encode4(68442),
26415 /* 68286 */ /*GILLT_v2s64*//*Label 1709*/ GIMT_Encode4(68306), GIMT_Encode4(0),
26416 /* 68294 */ /*GILLT_v4s32*//*Label 1710*/ GIMT_Encode4(68340),
26417 /* 68298 */ /*GILLT_v8s16*//*Label 1711*/ GIMT_Encode4(68374),
26418 /* 68302 */ /*GILLT_v16s8*//*Label 1712*/ GIMT_Encode4(68408),
26419 /* 68306 */ // Label 1709: @68306
26420 /* 68306 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(68339), // Rule ID 879 //
26421 /* 68311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26422 /* 68314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26423 /* 68317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
26424 /* 68320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26425 /* 68324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26426 /* 68328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26427 /* 68332 */ // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
26428 /* 68332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
26429 /* 68337 */ GIR_RootConstrainSelectedInstOperands,
26430 /* 68338 */ // GIR_Coverage, 879,
26431 /* 68338 */ GIR_Done,
26432 /* 68339 */ // Label 1714: @68339
26433 /* 68339 */ GIM_Reject,
26434 /* 68340 */ // Label 1710: @68340
26435 /* 68340 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(68373), // Rule ID 878 //
26436 /* 68345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26437 /* 68348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26438 /* 68351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26439 /* 68354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26440 /* 68358 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26441 /* 68362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26442 /* 68366 */ // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
26443 /* 68366 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
26444 /* 68371 */ GIR_RootConstrainSelectedInstOperands,
26445 /* 68372 */ // GIR_Coverage, 878,
26446 /* 68372 */ GIR_Done,
26447 /* 68373 */ // Label 1715: @68373
26448 /* 68373 */ GIM_Reject,
26449 /* 68374 */ // Label 1711: @68374
26450 /* 68374 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(68407), // Rule ID 877 //
26451 /* 68379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26452 /* 68382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26453 /* 68385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26454 /* 68388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26455 /* 68392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26456 /* 68396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26457 /* 68400 */ // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
26458 /* 68400 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
26459 /* 68405 */ GIR_RootConstrainSelectedInstOperands,
26460 /* 68406 */ // GIR_Coverage, 877,
26461 /* 68406 */ GIR_Done,
26462 /* 68407 */ // Label 1716: @68407
26463 /* 68407 */ GIM_Reject,
26464 /* 68408 */ // Label 1712: @68408
26465 /* 68408 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(68441), // Rule ID 876 //
26466 /* 68413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26467 /* 68416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26468 /* 68419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26469 /* 68422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26470 /* 68426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26471 /* 68430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26472 /* 68434 */ // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
26473 /* 68434 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
26474 /* 68439 */ GIR_RootConstrainSelectedInstOperands,
26475 /* 68440 */ // GIR_Coverage, 876,
26476 /* 68440 */ GIR_Done,
26477 /* 68441 */ // Label 1717: @68441
26478 /* 68441 */ GIM_Reject,
26479 /* 68442 */ // Label 1713: @68442
26480 /* 68442 */ GIM_Reject,
26481 /* 68443 */ // Label 70: @68443
26482 /* 68443 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(68566),
26483 /* 68448 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
26484 /* 68451 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(68472), // Rule ID 91 //
26485 /* 68456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC),
26486 /* 68459 */ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
26487 /* 68459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
26488 /* 68464 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26489 /* 68470 */ GIR_RootConstrainSelectedInstOperands,
26490 /* 68471 */ // GIR_Coverage, 91,
26491 /* 68471 */ GIR_Done,
26492 /* 68472 */ // Label 1719: @68472
26493 /* 68472 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(68493), // Rule ID 98 //
26494 /* 68477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
26495 /* 68480 */ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
26496 /* 68480 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
26497 /* 68485 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26498 /* 68491 */ GIR_RootConstrainSelectedInstOperands,
26499 /* 68492 */ // GIR_Coverage, 98,
26500 /* 68492 */ GIR_Done,
26501 /* 68493 */ // Label 1720: @68493
26502 /* 68493 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(68514), // Rule ID 1128 //
26503 /* 68498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC),
26504 /* 68501 */ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
26505 /* 68501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
26506 /* 68506 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26507 /* 68512 */ GIR_RootConstrainSelectedInstOperands,
26508 /* 68513 */ // GIR_Coverage, 1128,
26509 /* 68513 */ GIR_Done,
26510 /* 68514 */ // Label 1721: @68514
26511 /* 68514 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(68535), // Rule ID 1137 //
26512 /* 68519 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC),
26513 /* 68522 */ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
26514 /* 68522 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
26515 /* 68527 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
26516 /* 68533 */ GIR_RootConstrainSelectedInstOperands,
26517 /* 68534 */ // GIR_Coverage, 1137,
26518 /* 68534 */ GIR_Done,
26519 /* 68535 */ // Label 1722: @68535
26520 /* 68535 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(68550), // Rule ID 1194 //
26521 /* 68540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
26522 /* 68543 */ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
26523 /* 68543 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
26524 /* 68548 */ GIR_RootConstrainSelectedInstOperands,
26525 /* 68549 */ // GIR_Coverage, 1194,
26526 /* 68549 */ GIR_Done,
26527 /* 68550 */ // Label 1723: @68550
26528 /* 68550 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(68565), // Rule ID 1993 //
26529 /* 68555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
26530 /* 68558 */ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
26531 /* 68558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
26532 /* 68563 */ GIR_RootConstrainSelectedInstOperands,
26533 /* 68564 */ // GIR_Coverage, 1993,
26534 /* 68564 */ GIR_Done,
26535 /* 68565 */ // Label 1724: @68565
26536 /* 68565 */ GIM_Reject,
26537 /* 68566 */ // Label 1718: @68566
26538 /* 68566 */ GIM_Reject,
26539 /* 68567 */ // Label 71: @68567
26540 /* 68567 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1729*/ GIMT_Encode4(69130),
26541 /* 68578 */ /*GILLT_v2s64*//*Label 1725*/ GIMT_Encode4(68598), GIMT_Encode4(0),
26542 /* 68586 */ /*GILLT_v4s32*//*Label 1726*/ GIMT_Encode4(68771),
26543 /* 68590 */ /*GILLT_v8s16*//*Label 1727*/ GIMT_Encode4(68944),
26544 /* 68594 */ /*GILLT_v16s8*//*Label 1728*/ GIMT_Encode4(69037),
26545 /* 68598 */ // Label 1725: @68598
26546 /* 68598 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(68770),
26547 /* 68603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26548 /* 68606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
26549 /* 68609 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(68649), // Rule ID 845 //
26550 /* 68614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26551 /* 68617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26552 /* 68620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26553 /* 68624 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26554 /* 68628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26555 /* 68632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26556 /* 68636 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26557 /* 68636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
26558 /* 68639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26559 /* 68641 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26560 /* 68643 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26561 /* 68645 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26562 /* 68647 */ GIR_RootConstrainSelectedInstOperands,
26563 /* 68648 */ // GIR_Coverage, 845,
26564 /* 68648 */ GIR_EraseRootFromParent_Done,
26565 /* 68649 */ // Label 1731: @68649
26566 /* 68649 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(68689), // Rule ID 847 //
26567 /* 68654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26568 /* 68657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26569 /* 68660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26570 /* 68664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26571 /* 68668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26572 /* 68672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26573 /* 68676 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26574 /* 68676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
26575 /* 68679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26576 /* 68681 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26577 /* 68683 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26578 /* 68685 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26579 /* 68687 */ GIR_RootConstrainSelectedInstOperands,
26580 /* 68688 */ // GIR_Coverage, 847,
26581 /* 68688 */ GIR_EraseRootFromParent_Done,
26582 /* 68689 */ // Label 1732: @68689
26583 /* 68689 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(68729), // Rule ID 851 //
26584 /* 68694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26585 /* 68697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26586 /* 68700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26587 /* 68704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26588 /* 68708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26589 /* 68712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26590 /* 68716 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
26591 /* 68716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
26592 /* 68719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26593 /* 68721 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26594 /* 68723 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26595 /* 68725 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26596 /* 68727 */ GIR_RootConstrainSelectedInstOperands,
26597 /* 68728 */ // GIR_Coverage, 851,
26598 /* 68728 */ GIR_EraseRootFromParent_Done,
26599 /* 68729 */ // Label 1733: @68729
26600 /* 68729 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(68769), // Rule ID 853 //
26601 /* 68734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26602 /* 68737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26603 /* 68740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26604 /* 68744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26605 /* 68748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
26606 /* 68752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26607 /* 68756 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
26608 /* 68756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
26609 /* 68759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26610 /* 68761 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26611 /* 68763 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26612 /* 68765 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26613 /* 68767 */ GIR_RootConstrainSelectedInstOperands,
26614 /* 68768 */ // GIR_Coverage, 853,
26615 /* 68768 */ GIR_EraseRootFromParent_Done,
26616 /* 68769 */ // Label 1734: @68769
26617 /* 68769 */ GIM_Reject,
26618 /* 68770 */ // Label 1730: @68770
26619 /* 68770 */ GIM_Reject,
26620 /* 68771 */ // Label 1726: @68771
26621 /* 68771 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(68943),
26622 /* 68776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26623 /* 68779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26624 /* 68782 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(68822), // Rule ID 844 //
26625 /* 68787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26626 /* 68790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26627 /* 68793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26628 /* 68797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26629 /* 68801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26630 /* 68805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26631 /* 68809 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26632 /* 68809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
26633 /* 68812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26634 /* 68814 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26635 /* 68816 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26636 /* 68818 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26637 /* 68820 */ GIR_RootConstrainSelectedInstOperands,
26638 /* 68821 */ // GIR_Coverage, 844,
26639 /* 68821 */ GIR_EraseRootFromParent_Done,
26640 /* 68822 */ // Label 1736: @68822
26641 /* 68822 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(68862), // Rule ID 846 //
26642 /* 68827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26643 /* 68830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26644 /* 68833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26645 /* 68837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26646 /* 68841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26647 /* 68845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26648 /* 68849 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26649 /* 68849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
26650 /* 68852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26651 /* 68854 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26652 /* 68856 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26653 /* 68858 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26654 /* 68860 */ GIR_RootConstrainSelectedInstOperands,
26655 /* 68861 */ // GIR_Coverage, 846,
26656 /* 68861 */ GIR_EraseRootFromParent_Done,
26657 /* 68862 */ // Label 1737: @68862
26658 /* 68862 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(68902), // Rule ID 850 //
26659 /* 68867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26660 /* 68870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26661 /* 68873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26662 /* 68877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26663 /* 68881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26664 /* 68885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26665 /* 68889 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26666 /* 68889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
26667 /* 68892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26668 /* 68894 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26669 /* 68896 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26670 /* 68898 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26671 /* 68900 */ GIR_RootConstrainSelectedInstOperands,
26672 /* 68901 */ // GIR_Coverage, 850,
26673 /* 68901 */ GIR_EraseRootFromParent_Done,
26674 /* 68902 */ // Label 1738: @68902
26675 /* 68902 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(68942), // Rule ID 852 //
26676 /* 68907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26677 /* 68910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26678 /* 68913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26679 /* 68917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26680 /* 68921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
26681 /* 68925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26682 /* 68929 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
26683 /* 68929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
26684 /* 68932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26685 /* 68934 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26686 /* 68936 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26687 /* 68938 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26688 /* 68940 */ GIR_RootConstrainSelectedInstOperands,
26689 /* 68941 */ // GIR_Coverage, 852,
26690 /* 68941 */ GIR_EraseRootFromParent_Done,
26691 /* 68942 */ // Label 1739: @68942
26692 /* 68942 */ GIM_Reject,
26693 /* 68943 */ // Label 1735: @68943
26694 /* 68943 */ GIM_Reject,
26695 /* 68944 */ // Label 1727: @68944
26696 /* 68944 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(69036),
26697 /* 68949 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26698 /* 68952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26699 /* 68955 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(68995), // Rule ID 843 //
26700 /* 68960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26701 /* 68963 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26702 /* 68966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26703 /* 68970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26704 /* 68974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26705 /* 68978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26706 /* 68982 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26707 /* 68982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
26708 /* 68985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26709 /* 68987 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26710 /* 68989 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26711 /* 68991 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26712 /* 68993 */ GIR_RootConstrainSelectedInstOperands,
26713 /* 68994 */ // GIR_Coverage, 843,
26714 /* 68994 */ GIR_EraseRootFromParent_Done,
26715 /* 68995 */ // Label 1741: @68995
26716 /* 68995 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(69035), // Rule ID 849 //
26717 /* 69000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26718 /* 69003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26719 /* 69006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26720 /* 69010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26721 /* 69014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26722 /* 69018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26723 /* 69022 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26724 /* 69022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
26725 /* 69025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26726 /* 69027 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26727 /* 69029 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26728 /* 69031 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26729 /* 69033 */ GIR_RootConstrainSelectedInstOperands,
26730 /* 69034 */ // GIR_Coverage, 849,
26731 /* 69034 */ GIR_EraseRootFromParent_Done,
26732 /* 69035 */ // Label 1742: @69035
26733 /* 69035 */ GIM_Reject,
26734 /* 69036 */ // Label 1740: @69036
26735 /* 69036 */ GIM_Reject,
26736 /* 69037 */ // Label 1728: @69037
26737 /* 69037 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(69129),
26738 /* 69042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26739 /* 69045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26740 /* 69048 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(69088), // Rule ID 842 //
26741 /* 69053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26742 /* 69056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26743 /* 69059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26744 /* 69063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26745 /* 69067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26746 /* 69071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26747 /* 69075 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26748 /* 69075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
26749 /* 69078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26750 /* 69080 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26751 /* 69082 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26752 /* 69084 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26753 /* 69086 */ GIR_RootConstrainSelectedInstOperands,
26754 /* 69087 */ // GIR_Coverage, 842,
26755 /* 69087 */ GIR_EraseRootFromParent_Done,
26756 /* 69088 */ // Label 1744: @69088
26757 /* 69088 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(69128), // Rule ID 848 //
26758 /* 69093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26759 /* 69096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
26760 /* 69099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26761 /* 69103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26762 /* 69107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26763 /* 69111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26764 /* 69115 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
26765 /* 69115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
26766 /* 69118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
26767 /* 69120 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
26768 /* 69122 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
26769 /* 69124 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
26770 /* 69126 */ GIR_RootConstrainSelectedInstOperands,
26771 /* 69127 */ // GIR_Coverage, 848,
26772 /* 69127 */ GIR_EraseRootFromParent_Done,
26773 /* 69128 */ // Label 1745: @69128
26774 /* 69128 */ GIM_Reject,
26775 /* 69129 */ // Label 1743: @69129
26776 /* 69129 */ GIM_Reject,
26777 /* 69130 */ // Label 1729: @69130
26778 /* 69130 */ GIM_Reject,
26779 /* 69131 */ // Label 72: @69131
26780 /* 69131 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(69182), // Rule ID 2120 //
26781 /* 69136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
26782 /* 69139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26783 /* 69142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26784 /* 69145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26785 /* 69148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26786 /* 69152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26787 /* 69156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26788 /* 69160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26789 /* 69164 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
26790 /* 69168 */ // MIs[1] Operand 1
26791 /* 69168 */ // No operand predicates
26792 /* 69168 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26793 /* 69170 */ // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
26794 /* 69170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
26795 /* 69173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26796 /* 69175 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
26797 /* 69177 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
26798 /* 69180 */ GIR_RootConstrainSelectedInstOperands,
26799 /* 69181 */ // GIR_Coverage, 2120,
26800 /* 69181 */ GIR_EraseRootFromParent_Done,
26801 /* 69182 */ // Label 1746: @69182
26802 /* 69182 */ GIM_Reject,
26803 /* 69183 */ // Label 73: @69183
26804 /* 69183 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1753*/ GIMT_Encode4(69687),
26805 /* 69194 */ /*GILLT_s32*//*Label 1747*/ GIMT_Encode4(69226),
26806 /* 69198 */ /*GILLT_s64*//*Label 1748*/ GIMT_Encode4(69435), GIMT_Encode4(0),
26807 /* 69206 */ /*GILLT_v2s64*//*Label 1749*/ GIMT_Encode4(69579), GIMT_Encode4(0),
26808 /* 69214 */ /*GILLT_v4s32*//*Label 1750*/ GIMT_Encode4(69606),
26809 /* 69218 */ /*GILLT_v8s16*//*Label 1751*/ GIMT_Encode4(69633),
26810 /* 69222 */ /*GILLT_v16s8*//*Label 1752*/ GIMT_Encode4(69660),
26811 /* 69226 */ // Label 1747: @69226
26812 /* 69226 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(69434),
26813 /* 69231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
26814 /* 69234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26815 /* 69238 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(69284), // Rule ID 109 //
26816 /* 69243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26817 /* 69246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26818 /* 69250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26819 /* 69254 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26820 /* 69258 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26821 /* 69262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26822 /* 69267 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26823 /* 69271 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26824 /* 69273 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26825 /* 69273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
26826 /* 69276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26827 /* 69278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26828 /* 69282 */ GIR_RootConstrainSelectedInstOperands,
26829 /* 69283 */ // GIR_Coverage, 109,
26830 /* 69283 */ GIR_EraseRootFromParent_Done,
26831 /* 69284 */ // Label 1755: @69284
26832 /* 69284 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(69330), // Rule ID 334 //
26833 /* 69289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26834 /* 69292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26835 /* 69296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26836 /* 69300 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26837 /* 69304 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26838 /* 69308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26839 /* 69313 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26840 /* 69317 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26841 /* 69319 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26842 /* 69319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
26843 /* 69322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26844 /* 69324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26845 /* 69328 */ GIR_RootConstrainSelectedInstOperands,
26846 /* 69329 */ // GIR_Coverage, 334,
26847 /* 69329 */ GIR_EraseRootFromParent_Done,
26848 /* 69330 */ // Label 1756: @69330
26849 /* 69330 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(69376), // Rule ID 1124 //
26850 /* 69335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26851 /* 69338 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26852 /* 69342 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26853 /* 69346 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
26854 /* 69350 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
26855 /* 69354 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26856 /* 69359 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26857 /* 69363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26858 /* 69365 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26859 /* 69365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
26860 /* 69368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26861 /* 69370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26862 /* 69374 */ GIR_RootConstrainSelectedInstOperands,
26863 /* 69375 */ // GIR_Coverage, 1124,
26864 /* 69375 */ GIR_EraseRootFromParent_Done,
26865 /* 69376 */ // Label 1757: @69376
26866 /* 69376 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(69395), // Rule ID 108 //
26867 /* 69381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
26868 /* 69384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26869 /* 69388 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26870 /* 69388 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
26871 /* 69393 */ GIR_RootConstrainSelectedInstOperands,
26872 /* 69394 */ // GIR_Coverage, 108,
26873 /* 69394 */ GIR_Done,
26874 /* 69395 */ // Label 1758: @69395
26875 /* 69395 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(69414), // Rule ID 335 //
26876 /* 69400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
26877 /* 69403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26878 /* 69407 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26879 /* 69407 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
26880 /* 69412 */ GIR_RootConstrainSelectedInstOperands,
26881 /* 69413 */ // GIR_Coverage, 335,
26882 /* 69413 */ GIR_Done,
26883 /* 69414 */ // Label 1759: @69414
26884 /* 69414 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(69433), // Rule ID 1123 //
26885 /* 69419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
26886 /* 69422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
26887 /* 69426 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
26888 /* 69426 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
26889 /* 69431 */ GIR_RootConstrainSelectedInstOperands,
26890 /* 69432 */ // GIR_Coverage, 1123,
26891 /* 69432 */ GIR_Done,
26892 /* 69433 */ // Label 1760: @69433
26893 /* 69433 */ GIM_Reject,
26894 /* 69434 */ // Label 1754: @69434
26895 /* 69434 */ GIM_Reject,
26896 /* 69435 */ // Label 1748: @69435
26897 /* 69435 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(69578),
26898 /* 69440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
26899 /* 69443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26900 /* 69447 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(69493), // Rule ID 288 //
26901 /* 69452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26902 /* 69455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26903 /* 69459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26904 /* 69463 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26905 /* 69467 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26906 /* 69471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26907 /* 69476 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26908 /* 69480 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26909 /* 69482 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26910 /* 69482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
26911 /* 69485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26912 /* 69487 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26913 /* 69491 */ GIR_RootConstrainSelectedInstOperands,
26914 /* 69492 */ // GIR_Coverage, 288,
26915 /* 69492 */ GIR_EraseRootFromParent_Done,
26916 /* 69493 */ // Label 1762: @69493
26917 /* 69493 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(69539), // Rule ID 363 //
26918 /* 69498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26919 /* 69501 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
26920 /* 69505 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
26921 /* 69509 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
26922 /* 69513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
26923 /* 69517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26924 /* 69522 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
26925 /* 69526 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26926 /* 69528 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26927 /* 69528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
26928 /* 69531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
26929 /* 69533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
26930 /* 69537 */ GIR_RootConstrainSelectedInstOperands,
26931 /* 69538 */ // GIR_Coverage, 363,
26932 /* 69538 */ GIR_EraseRootFromParent_Done,
26933 /* 69539 */ // Label 1763: @69539
26934 /* 69539 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(69558), // Rule ID 287 //
26935 /* 69544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
26936 /* 69547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26937 /* 69551 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26938 /* 69551 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
26939 /* 69556 */ GIR_RootConstrainSelectedInstOperands,
26940 /* 69557 */ // GIR_Coverage, 287,
26941 /* 69557 */ GIR_Done,
26942 /* 69558 */ // Label 1764: @69558
26943 /* 69558 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(69577), // Rule ID 364 //
26944 /* 69563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
26945 /* 69566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
26946 /* 69570 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
26947 /* 69570 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
26948 /* 69575 */ GIR_RootConstrainSelectedInstOperands,
26949 /* 69576 */ // GIR_Coverage, 364,
26950 /* 69576 */ GIR_Done,
26951 /* 69577 */ // Label 1765: @69577
26952 /* 69577 */ GIM_Reject,
26953 /* 69578 */ // Label 1761: @69578
26954 /* 69578 */ GIM_Reject,
26955 /* 69579 */ // Label 1749: @69579
26956 /* 69579 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(69605), // Rule ID 939 //
26957 /* 69584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26958 /* 69587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
26959 /* 69590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26960 /* 69594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
26961 /* 69598 */ // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
26962 /* 69598 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
26963 /* 69603 */ GIR_RootConstrainSelectedInstOperands,
26964 /* 69604 */ // GIR_Coverage, 939,
26965 /* 69604 */ GIR_Done,
26966 /* 69605 */ // Label 1766: @69605
26967 /* 69605 */ GIM_Reject,
26968 /* 69606 */ // Label 1750: @69606
26969 /* 69606 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(69632), // Rule ID 938 //
26970 /* 69611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26971 /* 69614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
26972 /* 69617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26973 /* 69621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
26974 /* 69625 */ // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
26975 /* 69625 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
26976 /* 69630 */ GIR_RootConstrainSelectedInstOperands,
26977 /* 69631 */ // GIR_Coverage, 938,
26978 /* 69631 */ GIR_Done,
26979 /* 69632 */ // Label 1767: @69632
26980 /* 69632 */ GIM_Reject,
26981 /* 69633 */ // Label 1751: @69633
26982 /* 69633 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(69659), // Rule ID 937 //
26983 /* 69638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26984 /* 69641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
26985 /* 69644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26986 /* 69648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
26987 /* 69652 */ // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
26988 /* 69652 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
26989 /* 69657 */ GIR_RootConstrainSelectedInstOperands,
26990 /* 69658 */ // GIR_Coverage, 937,
26991 /* 69658 */ GIR_Done,
26992 /* 69659 */ // Label 1768: @69659
26993 /* 69659 */ GIM_Reject,
26994 /* 69660 */ // Label 1752: @69660
26995 /* 69660 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(69686), // Rule ID 936 //
26996 /* 69665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
26997 /* 69668 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
26998 /* 69671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
26999 /* 69675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
27000 /* 69679 */ // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
27001 /* 69679 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
27002 /* 69684 */ GIR_RootConstrainSelectedInstOperands,
27003 /* 69685 */ // GIR_Coverage, 936,
27004 /* 69685 */ GIR_Done,
27005 /* 69686 */ // Label 1769: @69686
27006 /* 69686 */ GIM_Reject,
27007 /* 69687 */ // Label 1753: @69687
27008 /* 69687 */ GIM_Reject,
27009 /* 69688 */ // Label 74: @69688
27010 /* 69688 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1776*/ GIMT_Encode4(69893),
27011 /* 69699 */ /*GILLT_s32*//*Label 1770*/ GIMT_Encode4(69731),
27012 /* 69703 */ /*GILLT_s64*//*Label 1771*/ GIMT_Encode4(69758), GIMT_Encode4(0),
27013 /* 69711 */ /*GILLT_v2s64*//*Label 1772*/ GIMT_Encode4(69785), GIMT_Encode4(0),
27014 /* 69719 */ /*GILLT_v4s32*//*Label 1773*/ GIMT_Encode4(69812),
27015 /* 69723 */ /*GILLT_v8s16*//*Label 1774*/ GIMT_Encode4(69839),
27016 /* 69727 */ /*GILLT_v16s8*//*Label 1775*/ GIMT_Encode4(69866),
27017 /* 69731 */ // Label 1770: @69731
27018 /* 69731 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(69757), // Rule ID 302 //
27019 /* 69736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
27020 /* 69739 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27021 /* 69742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27022 /* 69746 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27023 /* 69750 */ // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
27024 /* 69750 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
27025 /* 69755 */ GIR_RootConstrainSelectedInstOperands,
27026 /* 69756 */ // GIR_Coverage, 302,
27027 /* 69756 */ GIR_Done,
27028 /* 69757 */ // Label 1777: @69757
27029 /* 69757 */ GIM_Reject,
27030 /* 69758 */ // Label 1771: @69758
27031 /* 69758 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(69784), // Rule ID 303 //
27032 /* 69763 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
27033 /* 69766 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27034 /* 69769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27035 /* 69773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27036 /* 69777 */ // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
27037 /* 69777 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
27038 /* 69782 */ GIR_RootConstrainSelectedInstOperands,
27039 /* 69783 */ // GIR_Coverage, 303,
27040 /* 69783 */ GIR_Done,
27041 /* 69784 */ // Label 1778: @69784
27042 /* 69784 */ GIM_Reject,
27043 /* 69785 */ // Label 1772: @69785
27044 /* 69785 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(69811), // Rule ID 961 //
27045 /* 69790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27046 /* 69793 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27047 /* 69796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27048 /* 69800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27049 /* 69804 */ // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
27050 /* 69804 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
27051 /* 69809 */ GIR_RootConstrainSelectedInstOperands,
27052 /* 69810 */ // GIR_Coverage, 961,
27053 /* 69810 */ GIR_Done,
27054 /* 69811 */ // Label 1779: @69811
27055 /* 69811 */ GIM_Reject,
27056 /* 69812 */ // Label 1773: @69812
27057 /* 69812 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(69838), // Rule ID 960 //
27058 /* 69817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27059 /* 69820 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27060 /* 69823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27061 /* 69827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27062 /* 69831 */ // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
27063 /* 69831 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
27064 /* 69836 */ GIR_RootConstrainSelectedInstOperands,
27065 /* 69837 */ // GIR_Coverage, 960,
27066 /* 69837 */ GIR_Done,
27067 /* 69838 */ // Label 1780: @69838
27068 /* 69838 */ GIM_Reject,
27069 /* 69839 */ // Label 1774: @69839
27070 /* 69839 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(69865), // Rule ID 959 //
27071 /* 69844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27072 /* 69847 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
27073 /* 69850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
27074 /* 69854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
27075 /* 69858 */ // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
27076 /* 69858 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
27077 /* 69863 */ GIR_RootConstrainSelectedInstOperands,
27078 /* 69864 */ // GIR_Coverage, 959,
27079 /* 69864 */ GIR_Done,
27080 /* 69865 */ // Label 1781: @69865
27081 /* 69865 */ GIM_Reject,
27082 /* 69866 */ // Label 1775: @69866
27083 /* 69866 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(69892), // Rule ID 958 //
27084 /* 69871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27085 /* 69874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
27086 /* 69877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
27087 /* 69881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
27088 /* 69885 */ // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
27089 /* 69885 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
27090 /* 69890 */ GIR_RootConstrainSelectedInstOperands,
27091 /* 69891 */ // GIR_Coverage, 958,
27092 /* 69891 */ GIR_Done,
27093 /* 69892 */ // Label 1782: @69892
27094 /* 69892 */ GIM_Reject,
27095 /* 69893 */ // Label 1776: @69893
27096 /* 69893 */ GIM_Reject,
27097 /* 69894 */ // Label 75: @69894
27098 /* 69894 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1785*/ GIMT_Encode4(70057),
27099 /* 69905 */ /*GILLT_s32*//*Label 1783*/ GIMT_Encode4(69913),
27100 /* 69909 */ /*GILLT_s64*//*Label 1784*/ GIMT_Encode4(70009),
27101 /* 69913 */ // Label 1783: @69913
27102 /* 69913 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(70008),
27103 /* 69918 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27104 /* 69921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27105 /* 69925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
27106 /* 69929 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(69968), // Rule ID 1450 //
27107 /* 69934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
27108 /* 69937 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
27109 /* 69937 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27110 /* 69940 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
27111 /* 69944 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27112 /* 69949 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27113 /* 69953 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27114 /* 69955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
27115 /* 69958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27116 /* 69960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27117 /* 69963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
27118 /* 69966 */ GIR_RootConstrainSelectedInstOperands,
27119 /* 69967 */ // GIR_Coverage, 1450,
27120 /* 69967 */ GIR_EraseRootFromParent_Done,
27121 /* 69968 */ // Label 1787: @69968
27122 /* 69968 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(70007), // Rule ID 2317 //
27123 /* 69973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
27124 /* 69976 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
27125 /* 69976 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
27126 /* 69979 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
27127 /* 69983 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27128 /* 69988 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27129 /* 69992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27130 /* 69994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
27131 /* 69997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27132 /* 69999 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27133 /* 70002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
27134 /* 70005 */ GIR_RootConstrainSelectedInstOperands,
27135 /* 70006 */ // GIR_Coverage, 2317,
27136 /* 70006 */ GIR_EraseRootFromParent_Done,
27137 /* 70007 */ // Label 1788: @70007
27138 /* 70007 */ GIM_Reject,
27139 /* 70008 */ // Label 1786: @70008
27140 /* 70008 */ GIM_Reject,
27141 /* 70009 */ // Label 1784: @70009
27142 /* 70009 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(70056), // Rule ID 1691 //
27143 /* 70014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc),
27144 /* 70017 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27145 /* 70020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27146 /* 70024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
27147 /* 70028 */ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
27148 /* 70028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
27149 /* 70031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
27150 /* 70035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27151 /* 70040 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
27152 /* 70044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
27153 /* 70046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
27154 /* 70049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
27155 /* 70051 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27156 /* 70054 */ GIR_RootConstrainSelectedInstOperands,
27157 /* 70055 */ // GIR_Coverage, 1691,
27158 /* 70055 */ GIR_EraseRootFromParent_Done,
27159 /* 70056 */ // Label 1789: @70056
27160 /* 70056 */ GIM_Reject,
27161 /* 70057 */ // Label 1785: @70057
27162 /* 70057 */ GIM_Reject,
27163 /* 70058 */ // Label 76: @70058
27164 /* 70058 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1794*/ GIMT_Encode4(70321),
27165 /* 70069 */ /*GILLT_s32*//*Label 1790*/ GIMT_Encode4(70093),
27166 /* 70073 */ /*GILLT_s64*//*Label 1791*/ GIMT_Encode4(70149), GIMT_Encode4(0),
27167 /* 70081 */ /*GILLT_v2s64*//*Label 1792*/ GIMT_Encode4(70267), GIMT_Encode4(0),
27168 /* 70089 */ /*GILLT_v4s32*//*Label 1793*/ GIMT_Encode4(70294),
27169 /* 70093 */ // Label 1790: @70093
27170 /* 70093 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(70148),
27171 /* 70098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27172 /* 70101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27173 /* 70105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27174 /* 70109 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(70128), // Rule ID 130 //
27175 /* 70114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27176 /* 70117 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27177 /* 70117 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
27178 /* 70122 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27179 /* 70126 */ GIR_RootConstrainSelectedInstOperands,
27180 /* 70127 */ // GIR_Coverage, 130,
27181 /* 70127 */ GIR_Done,
27182 /* 70128 */ // Label 1796: @70128
27183 /* 70128 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(70147), // Rule ID 1185 //
27184 /* 70133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
27185 /* 70136 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27186 /* 70136 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
27187 /* 70141 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27188 /* 70145 */ GIR_RootConstrainSelectedInstOperands,
27189 /* 70146 */ // GIR_Coverage, 1185,
27190 /* 70146 */ GIR_Done,
27191 /* 70147 */ // Label 1797: @70147
27192 /* 70147 */ GIM_Reject,
27193 /* 70148 */ // Label 1795: @70148
27194 /* 70148 */ GIM_Reject,
27195 /* 70149 */ // Label 1791: @70149
27196 /* 70149 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(70266),
27197 /* 70154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27198 /* 70157 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(70184), // Rule ID 132 //
27199 /* 70162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27200 /* 70165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27201 /* 70169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27202 /* 70173 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27203 /* 70173 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
27204 /* 70178 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27205 /* 70182 */ GIR_RootConstrainSelectedInstOperands,
27206 /* 70183 */ // GIR_Coverage, 132,
27207 /* 70183 */ GIR_Done,
27208 /* 70184 */ // Label 1799: @70184
27209 /* 70184 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(70211), // Rule ID 134 //
27210 /* 70189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27211 /* 70192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27212 /* 70196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27213 /* 70200 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27214 /* 70200 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
27215 /* 70205 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27216 /* 70209 */ GIR_RootConstrainSelectedInstOperands,
27217 /* 70210 */ // GIR_Coverage, 134,
27218 /* 70210 */ GIR_Done,
27219 /* 70211 */ // Label 1800: @70211
27220 /* 70211 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(70238), // Rule ID 1172 //
27221 /* 70216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
27222 /* 70219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27223 /* 70223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27224 /* 70227 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27225 /* 70227 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
27226 /* 70232 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27227 /* 70236 */ GIR_RootConstrainSelectedInstOperands,
27228 /* 70237 */ // GIR_Coverage, 1172,
27229 /* 70237 */ GIR_Done,
27230 /* 70238 */ // Label 1801: @70238
27231 /* 70238 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(70265), // Rule ID 1173 //
27232 /* 70243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
27233 /* 70246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27234 /* 70250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27235 /* 70254 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27236 /* 70254 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
27237 /* 70259 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27238 /* 70263 */ GIR_RootConstrainSelectedInstOperands,
27239 /* 70264 */ // GIR_Coverage, 1173,
27240 /* 70264 */ GIR_Done,
27241 /* 70265 */ // Label 1802: @70265
27242 /* 70265 */ GIM_Reject,
27243 /* 70266 */ // Label 1798: @70266
27244 /* 70266 */ GIM_Reject,
27245 /* 70267 */ // Label 1792: @70267
27246 /* 70267 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(70293), // Rule ID 781 //
27247 /* 70272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27248 /* 70275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27249 /* 70278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27250 /* 70282 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27251 /* 70286 */ // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
27252 /* 70286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
27253 /* 70291 */ GIR_RootConstrainSelectedInstOperands,
27254 /* 70292 */ // GIR_Coverage, 781,
27255 /* 70292 */ GIR_Done,
27256 /* 70293 */ // Label 1803: @70293
27257 /* 70293 */ GIM_Reject,
27258 /* 70294 */ // Label 1793: @70294
27259 /* 70294 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(70320), // Rule ID 780 //
27260 /* 70299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27261 /* 70302 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27262 /* 70305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27263 /* 70309 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27264 /* 70313 */ // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
27265 /* 70313 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
27266 /* 70318 */ GIR_RootConstrainSelectedInstOperands,
27267 /* 70319 */ // GIR_Coverage, 780,
27268 /* 70319 */ GIR_Done,
27269 /* 70320 */ // Label 1804: @70320
27270 /* 70320 */ GIM_Reject,
27271 /* 70321 */ // Label 1794: @70321
27272 /* 70321 */ GIM_Reject,
27273 /* 70322 */ // Label 77: @70322
27274 /* 70322 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1807*/ GIMT_Encode4(70399),
27275 /* 70333 */ /*GILLT_v2s64*//*Label 1805*/ GIMT_Encode4(70345), GIMT_Encode4(0),
27276 /* 70341 */ /*GILLT_v4s32*//*Label 1806*/ GIMT_Encode4(70372),
27277 /* 70345 */ // Label 1805: @70345
27278 /* 70345 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(70371), // Rule ID 763 //
27279 /* 70350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27280 /* 70353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
27281 /* 70356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27282 /* 70360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
27283 /* 70364 */ // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
27284 /* 70364 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
27285 /* 70369 */ GIR_RootConstrainSelectedInstOperands,
27286 /* 70370 */ // GIR_Coverage, 763,
27287 /* 70370 */ GIR_Done,
27288 /* 70371 */ // Label 1808: @70371
27289 /* 70371 */ GIM_Reject,
27290 /* 70372 */ // Label 1806: @70372
27291 /* 70372 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(70398), // Rule ID 762 //
27292 /* 70377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
27293 /* 70380 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
27294 /* 70383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27295 /* 70387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
27296 /* 70391 */ // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
27297 /* 70391 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
27298 /* 70396 */ GIR_RootConstrainSelectedInstOperands,
27299 /* 70397 */ // GIR_Coverage, 762,
27300 /* 70397 */ GIR_Done,
27301 /* 70398 */ // Label 1809: @70398
27302 /* 70398 */ GIM_Reject,
27303 /* 70399 */ // Label 1807: @70399
27304 /* 70399 */ GIM_Reject,
27305 /* 70400 */ // Label 78: @70400
27306 /* 70400 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1812*/ GIMT_Encode4(71254),
27307 /* 70411 */ /*GILLT_s32*//*Label 1810*/ GIMT_Encode4(70419),
27308 /* 70415 */ /*GILLT_s64*//*Label 1811*/ GIMT_Encode4(70691),
27309 /* 70419 */ // Label 1810: @70419
27310 /* 70419 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(70690),
27311 /* 70424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27312 /* 70427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27313 /* 70430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27314 /* 70434 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(70491), // Rule ID 176 //
27315 /* 70439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27316 /* 70442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27317 /* 70446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27318 /* 70450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27319 /* 70454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27320 /* 70458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27321 /* 70463 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27322 /* 70468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27323 /* 70472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27324 /* 70474 */ // (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27325 /* 70474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27326 /* 70477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27327 /* 70479 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27328 /* 70481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27329 /* 70485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27330 /* 70489 */ GIR_RootConstrainSelectedInstOperands,
27331 /* 70490 */ // GIR_Coverage, 176,
27332 /* 70490 */ GIR_EraseRootFromParent_Done,
27333 /* 70491 */ // Label 1814: @70491
27334 /* 70491 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(70548), // Rule ID 175 //
27335 /* 70496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27336 /* 70499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27337 /* 70503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27338 /* 70507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27339 /* 70511 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27340 /* 70515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27341 /* 70520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27342 /* 70525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27343 /* 70529 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27344 /* 70531 */ // (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27345 /* 70531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27346 /* 70534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27347 /* 70536 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27348 /* 70538 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27349 /* 70542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27350 /* 70546 */ GIR_RootConstrainSelectedInstOperands,
27351 /* 70547 */ // GIR_Coverage, 175,
27352 /* 70547 */ GIR_EraseRootFromParent_Done,
27353 /* 70548 */ // Label 1815: @70548
27354 /* 70548 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(70605), // Rule ID 2488 //
27355 /* 70553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27356 /* 70556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27357 /* 70560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27358 /* 70564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27359 /* 70568 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27360 /* 70572 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27361 /* 70576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27362 /* 70581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27363 /* 70586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27364 /* 70588 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27365 /* 70588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27366 /* 70591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27367 /* 70593 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27368 /* 70595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27369 /* 70599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27370 /* 70603 */ GIR_RootConstrainSelectedInstOperands,
27371 /* 70604 */ // GIR_Coverage, 2488,
27372 /* 70604 */ GIR_EraseRootFromParent_Done,
27373 /* 70605 */ // Label 1816: @70605
27374 /* 70605 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(70662), // Rule ID 2487 //
27375 /* 70610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27376 /* 70613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27377 /* 70617 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27378 /* 70621 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27379 /* 70625 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27380 /* 70629 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27381 /* 70633 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27382 /* 70638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27383 /* 70643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27384 /* 70645 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27385 /* 70645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
27386 /* 70648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27387 /* 70650 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27388 /* 70652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27389 /* 70656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27390 /* 70660 */ GIR_RootConstrainSelectedInstOperands,
27391 /* 70661 */ // GIR_Coverage, 2487,
27392 /* 70661 */ GIR_EraseRootFromParent_Done,
27393 /* 70662 */ // Label 1817: @70662
27394 /* 70662 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(70689), // Rule ID 151 //
27395 /* 70667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27396 /* 70670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27397 /* 70674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27398 /* 70678 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27399 /* 70678 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
27400 /* 70683 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27401 /* 70687 */ GIR_RootConstrainSelectedInstOperands,
27402 /* 70688 */ // GIR_Coverage, 151,
27403 /* 70688 */ GIR_Done,
27404 /* 70689 */ // Label 1818: @70689
27405 /* 70689 */ GIM_Reject,
27406 /* 70690 */ // Label 1813: @70690
27407 /* 70690 */ GIM_Reject,
27408 /* 70691 */ // Label 1811: @70691
27409 /* 70691 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(71253),
27410 /* 70696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27411 /* 70699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27412 /* 70702 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(70763), // Rule ID 184 //
27413 /* 70707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27414 /* 70710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27415 /* 70714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27416 /* 70718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27417 /* 70722 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27418 /* 70726 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27419 /* 70730 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27420 /* 70735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27421 /* 70740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27422 /* 70744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27423 /* 70746 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27424 /* 70746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27425 /* 70749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27426 /* 70751 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27427 /* 70753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27428 /* 70757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27429 /* 70761 */ GIR_RootConstrainSelectedInstOperands,
27430 /* 70762 */ // GIR_Coverage, 184,
27431 /* 70762 */ GIR_EraseRootFromParent_Done,
27432 /* 70763 */ // Label 1820: @70763
27433 /* 70763 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(70824), // Rule ID 192 //
27434 /* 70768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27435 /* 70771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27436 /* 70775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27437 /* 70779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27438 /* 70783 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27439 /* 70787 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27440 /* 70791 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27441 /* 70796 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27442 /* 70801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27443 /* 70805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27444 /* 70807 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27445 /* 70807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27446 /* 70810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27447 /* 70812 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27448 /* 70814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27449 /* 70818 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27450 /* 70822 */ GIR_RootConstrainSelectedInstOperands,
27451 /* 70823 */ // GIR_Coverage, 192,
27452 /* 70823 */ GIR_EraseRootFromParent_Done,
27453 /* 70824 */ // Label 1821: @70824
27454 /* 70824 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(70885), // Rule ID 183 //
27455 /* 70829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27456 /* 70832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27457 /* 70836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27458 /* 70840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27459 /* 70844 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27460 /* 70848 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27461 /* 70852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27462 /* 70857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27463 /* 70862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27464 /* 70866 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27465 /* 70868 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27466 /* 70868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27467 /* 70871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27468 /* 70873 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27469 /* 70875 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27470 /* 70879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27471 /* 70883 */ GIR_RootConstrainSelectedInstOperands,
27472 /* 70884 */ // GIR_Coverage, 183,
27473 /* 70884 */ GIR_EraseRootFromParent_Done,
27474 /* 70885 */ // Label 1822: @70885
27475 /* 70885 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(70946), // Rule ID 191 //
27476 /* 70890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27477 /* 70893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27478 /* 70897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27479 /* 70901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27480 /* 70905 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27481 /* 70909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27482 /* 70913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27483 /* 70918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27484 /* 70923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27485 /* 70927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27486 /* 70929 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27487 /* 70929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27488 /* 70932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27489 /* 70934 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27490 /* 70936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27491 /* 70940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27492 /* 70944 */ GIR_RootConstrainSelectedInstOperands,
27493 /* 70945 */ // GIR_Coverage, 191,
27494 /* 70945 */ GIR_EraseRootFromParent_Done,
27495 /* 70946 */ // Label 1823: @70946
27496 /* 70946 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(71007), // Rule ID 2492 //
27497 /* 70951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27498 /* 70954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27499 /* 70958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27500 /* 70962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27501 /* 70966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27502 /* 70970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27503 /* 70974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27504 /* 70978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27505 /* 70983 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27506 /* 70988 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27507 /* 70990 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27508 /* 70990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27509 /* 70993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27510 /* 70995 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27511 /* 70997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27512 /* 71001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27513 /* 71005 */ GIR_RootConstrainSelectedInstOperands,
27514 /* 71006 */ // GIR_Coverage, 2492,
27515 /* 71006 */ GIR_EraseRootFromParent_Done,
27516 /* 71007 */ // Label 1824: @71007
27517 /* 71007 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(71068), // Rule ID 2496 //
27518 /* 71012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27519 /* 71015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27520 /* 71019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27521 /* 71023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27522 /* 71027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27523 /* 71031 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27524 /* 71035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27525 /* 71039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27526 /* 71044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27527 /* 71049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27528 /* 71051 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27529 /* 71051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27530 /* 71054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27531 /* 71056 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27532 /* 71058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27533 /* 71062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27534 /* 71066 */ GIR_RootConstrainSelectedInstOperands,
27535 /* 71067 */ // GIR_Coverage, 2496,
27536 /* 71067 */ GIR_EraseRootFromParent_Done,
27537 /* 71068 */ // Label 1825: @71068
27538 /* 71068 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(71129), // Rule ID 2491 //
27539 /* 71073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27540 /* 71076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27541 /* 71080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27542 /* 71084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27543 /* 71088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27544 /* 71092 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27545 /* 71096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27546 /* 71100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27547 /* 71105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27548 /* 71110 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27549 /* 71112 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27550 /* 71112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
27551 /* 71115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27552 /* 71117 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27553 /* 71119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27554 /* 71123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27555 /* 71127 */ GIR_RootConstrainSelectedInstOperands,
27556 /* 71128 */ // GIR_Coverage, 2491,
27557 /* 71128 */ GIR_EraseRootFromParent_Done,
27558 /* 71129 */ // Label 1826: @71129
27559 /* 71129 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(71190), // Rule ID 2495 //
27560 /* 71134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27561 /* 71137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27562 /* 71141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27563 /* 71145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27564 /* 71149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27565 /* 71153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27566 /* 71157 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27567 /* 71161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27568 /* 71166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27569 /* 71171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27570 /* 71173 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27571 /* 71173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
27572 /* 71176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27573 /* 71178 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
27574 /* 71180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27575 /* 71184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27576 /* 71188 */ GIR_RootConstrainSelectedInstOperands,
27577 /* 71189 */ // GIR_Coverage, 2495,
27578 /* 71189 */ GIR_EraseRootFromParent_Done,
27579 /* 71190 */ // Label 1827: @71190
27580 /* 71190 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(71221), // Rule ID 153 //
27581 /* 71195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27582 /* 71198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27583 /* 71202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27584 /* 71206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27585 /* 71210 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27586 /* 71210 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
27587 /* 71215 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27588 /* 71219 */ GIR_RootConstrainSelectedInstOperands,
27589 /* 71220 */ // GIR_Coverage, 153,
27590 /* 71220 */ GIR_Done,
27591 /* 71221 */ // Label 1828: @71221
27592 /* 71221 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(71252), // Rule ID 155 //
27593 /* 71226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27594 /* 71229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27595 /* 71233 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27596 /* 71237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27597 /* 71241 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27598 /* 71241 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
27599 /* 71246 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27600 /* 71250 */ GIR_RootConstrainSelectedInstOperands,
27601 /* 71251 */ // GIR_Coverage, 155,
27602 /* 71251 */ GIR_Done,
27603 /* 71252 */ // Label 1829: @71252
27604 /* 71252 */ GIM_Reject,
27605 /* 71253 */ // Label 1819: @71253
27606 /* 71253 */ GIM_Reject,
27607 /* 71254 */ // Label 1812: @71254
27608 /* 71254 */ GIM_Reject,
27609 /* 71255 */ // Label 79: @71255
27610 /* 71255 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1832*/ GIMT_Encode4(71751),
27611 /* 71266 */ /*GILLT_s32*//*Label 1830*/ GIMT_Encode4(71274),
27612 /* 71270 */ /*GILLT_s64*//*Label 1831*/ GIMT_Encode4(71432),
27613 /* 71274 */ // Label 1830: @71274
27614 /* 71274 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(71431),
27615 /* 71279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27616 /* 71282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27617 /* 71285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27618 /* 71289 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(71346), // Rule ID 180 //
27619 /* 71294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27620 /* 71297 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27621 /* 71301 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27622 /* 71305 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27623 /* 71309 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27624 /* 71313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27625 /* 71318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27626 /* 71323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27627 /* 71327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27628 /* 71329 */ // (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27629 /* 71329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
27630 /* 71332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27631 /* 71334 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27632 /* 71336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27633 /* 71340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27634 /* 71344 */ GIR_RootConstrainSelectedInstOperands,
27635 /* 71345 */ // GIR_Coverage, 180,
27636 /* 71345 */ GIR_EraseRootFromParent_Done,
27637 /* 71346 */ // Label 1834: @71346
27638 /* 71346 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(71403), // Rule ID 179 //
27639 /* 71351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27640 /* 71354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27641 /* 71358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27642 /* 71362 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
27643 /* 71366 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
27644 /* 71370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27645 /* 71375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27646 /* 71380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27647 /* 71384 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27648 /* 71386 */ // (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27649 /* 71386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
27650 /* 71389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27651 /* 71391 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27652 /* 71393 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27653 /* 71397 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27654 /* 71401 */ GIR_RootConstrainSelectedInstOperands,
27655 /* 71402 */ // GIR_Coverage, 179,
27656 /* 71402 */ GIR_EraseRootFromParent_Done,
27657 /* 71403 */ // Label 1835: @71403
27658 /* 71403 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(71430), // Rule ID 169 //
27659 /* 71408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27660 /* 71411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27661 /* 71415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27662 /* 71419 */ // (strict_fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27663 /* 71419 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
27664 /* 71424 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27665 /* 71428 */ GIR_RootConstrainSelectedInstOperands,
27666 /* 71429 */ // GIR_Coverage, 169,
27667 /* 71429 */ GIR_Done,
27668 /* 71430 */ // Label 1836: @71430
27669 /* 71430 */ GIM_Reject,
27670 /* 71431 */ // Label 1833: @71431
27671 /* 71431 */ GIM_Reject,
27672 /* 71432 */ // Label 1831: @71432
27673 /* 71432 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(71750),
27674 /* 71437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27675 /* 71440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27676 /* 71443 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(71504), // Rule ID 188 //
27677 /* 71448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27678 /* 71451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27679 /* 71455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27680 /* 71459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27681 /* 71463 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27682 /* 71467 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27683 /* 71471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27684 /* 71476 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27685 /* 71481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27686 /* 71485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27687 /* 71487 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27688 /* 71487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
27689 /* 71490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27690 /* 71492 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27691 /* 71494 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27692 /* 71498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27693 /* 71502 */ GIR_RootConstrainSelectedInstOperands,
27694 /* 71503 */ // GIR_Coverage, 188,
27695 /* 71503 */ GIR_EraseRootFromParent_Done,
27696 /* 71504 */ // Label 1838: @71504
27697 /* 71504 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(71565), // Rule ID 196 //
27698 /* 71509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27699 /* 71512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27700 /* 71516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27701 /* 71520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
27702 /* 71524 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27703 /* 71528 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27704 /* 71532 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27705 /* 71537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27706 /* 71542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27707 /* 71546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27708 /* 71548 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27709 /* 71548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
27710 /* 71551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27711 /* 71553 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27712 /* 71555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27713 /* 71559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27714 /* 71563 */ GIR_RootConstrainSelectedInstOperands,
27715 /* 71564 */ // GIR_Coverage, 196,
27716 /* 71564 */ GIR_EraseRootFromParent_Done,
27717 /* 71565 */ // Label 1839: @71565
27718 /* 71565 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(71626), // Rule ID 187 //
27719 /* 71570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
27720 /* 71573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27721 /* 71577 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27722 /* 71581 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27723 /* 71585 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27724 /* 71589 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27725 /* 71593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27726 /* 71598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27727 /* 71603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27728 /* 71607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27729 /* 71609 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27730 /* 71609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
27731 /* 71612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27732 /* 71614 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27733 /* 71616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27734 /* 71620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27735 /* 71624 */ GIR_RootConstrainSelectedInstOperands,
27736 /* 71625 */ // GIR_Coverage, 187,
27737 /* 71625 */ GIR_EraseRootFromParent_Done,
27738 /* 71626 */ // Label 1840: @71626
27739 /* 71626 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(71687), // Rule ID 195 //
27740 /* 71631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
27741 /* 71634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27742 /* 71638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
27743 /* 71642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
27744 /* 71646 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
27745 /* 71650 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
27746 /* 71654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27747 /* 71659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27748 /* 71664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27749 /* 71668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27750 /* 71670 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27751 /* 71670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
27752 /* 71673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
27753 /* 71675 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
27754 /* 71677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
27755 /* 71681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
27756 /* 71685 */ GIR_RootConstrainSelectedInstOperands,
27757 /* 71686 */ // GIR_Coverage, 195,
27758 /* 71686 */ GIR_EraseRootFromParent_Done,
27759 /* 71687 */ // Label 1841: @71687
27760 /* 71687 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(71718), // Rule ID 171 //
27761 /* 71692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27762 /* 71695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27763 /* 71699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27764 /* 71703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27765 /* 71707 */ // (strict_fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27766 /* 71707 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
27767 /* 71712 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27768 /* 71716 */ GIR_RootConstrainSelectedInstOperands,
27769 /* 71717 */ // GIR_Coverage, 171,
27770 /* 71717 */ GIR_Done,
27771 /* 71718 */ // Label 1842: @71718
27772 /* 71718 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(71749), // Rule ID 173 //
27773 /* 71723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27774 /* 71726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27775 /* 71730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27776 /* 71734 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27777 /* 71738 */ // (strict_fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27778 /* 71738 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
27779 /* 71743 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27780 /* 71747 */ GIR_RootConstrainSelectedInstOperands,
27781 /* 71748 */ // GIR_Coverage, 173,
27782 /* 71748 */ GIR_Done,
27783 /* 71749 */ // Label 1843: @71749
27784 /* 71749 */ GIM_Reject,
27785 /* 71750 */ // Label 1837: @71750
27786 /* 71750 */ GIM_Reject,
27787 /* 71751 */ // Label 1832: @71751
27788 /* 71751 */ GIM_Reject,
27789 /* 71752 */ // Label 80: @71752
27790 /* 71752 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1846*/ GIMT_Encode4(71884),
27791 /* 71763 */ /*GILLT_s32*//*Label 1844*/ GIMT_Encode4(71771),
27792 /* 71767 */ /*GILLT_s64*//*Label 1845*/ GIMT_Encode4(71809),
27793 /* 71771 */ // Label 1844: @71771
27794 /* 71771 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(71808), // Rule ID 163 //
27795 /* 71776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27796 /* 71779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27797 /* 71782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27798 /* 71785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27799 /* 71789 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27800 /* 71793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27801 /* 71797 */ // (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27802 /* 71797 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
27803 /* 71802 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27804 /* 71806 */ GIR_RootConstrainSelectedInstOperands,
27805 /* 71807 */ // GIR_Coverage, 163,
27806 /* 71807 */ GIR_Done,
27807 /* 71808 */ // Label 1847: @71808
27808 /* 71808 */ GIM_Reject,
27809 /* 71809 */ // Label 1845: @71809
27810 /* 71809 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(71883),
27811 /* 71814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27812 /* 71817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27813 /* 71820 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(71851), // Rule ID 165 //
27814 /* 71825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27815 /* 71828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27816 /* 71832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27817 /* 71836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27818 /* 71840 */ // (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27819 /* 71840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
27820 /* 71845 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27821 /* 71849 */ GIR_RootConstrainSelectedInstOperands,
27822 /* 71850 */ // GIR_Coverage, 165,
27823 /* 71850 */ GIR_Done,
27824 /* 71851 */ // Label 1849: @71851
27825 /* 71851 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(71882), // Rule ID 167 //
27826 /* 71856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27827 /* 71859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27828 /* 71863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27829 /* 71867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27830 /* 71871 */ // (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27831 /* 71871 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
27832 /* 71876 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27833 /* 71880 */ GIR_RootConstrainSelectedInstOperands,
27834 /* 71881 */ // GIR_Coverage, 167,
27835 /* 71881 */ GIR_Done,
27836 /* 71882 */ // Label 1850: @71882
27837 /* 71882 */ GIM_Reject,
27838 /* 71883 */ // Label 1848: @71883
27839 /* 71883 */ GIM_Reject,
27840 /* 71884 */ // Label 1846: @71884
27841 /* 71884 */ GIM_Reject,
27842 /* 71885 */ // Label 81: @71885
27843 /* 71885 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1853*/ GIMT_Encode4(72017),
27844 /* 71896 */ /*GILLT_s32*//*Label 1851*/ GIMT_Encode4(71904),
27845 /* 71900 */ /*GILLT_s64*//*Label 1852*/ GIMT_Encode4(71942),
27846 /* 71904 */ // Label 1851: @71904
27847 /* 71904 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(71941), // Rule ID 157 //
27848 /* 71909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27849 /* 71912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27850 /* 71915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27851 /* 71918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27852 /* 71922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27853 /* 71926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27854 /* 71930 */ // (strict_fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
27855 /* 71930 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
27856 /* 71935 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27857 /* 71939 */ GIR_RootConstrainSelectedInstOperands,
27858 /* 71940 */ // GIR_Coverage, 157,
27859 /* 71940 */ GIR_Done,
27860 /* 71941 */ // Label 1854: @71941
27861 /* 71941 */ GIM_Reject,
27862 /* 71942 */ // Label 1852: @71942
27863 /* 71942 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(72016),
27864 /* 71947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27865 /* 71950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
27866 /* 71953 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(71984), // Rule ID 159 //
27867 /* 71958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27868 /* 71961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27869 /* 71965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27870 /* 71969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27871 /* 71973 */ // (strict_fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
27872 /* 71973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
27873 /* 71978 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27874 /* 71982 */ GIR_RootConstrainSelectedInstOperands,
27875 /* 71983 */ // GIR_Coverage, 159,
27876 /* 71983 */ GIR_Done,
27877 /* 71984 */ // Label 1856: @71984
27878 /* 71984 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(72015), // Rule ID 161 //
27879 /* 71989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27880 /* 71992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27881 /* 71996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27882 /* 72000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27883 /* 72004 */ // (strict_fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
27884 /* 72004 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
27885 /* 72009 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27886 /* 72013 */ GIR_RootConstrainSelectedInstOperands,
27887 /* 72014 */ // GIR_Coverage, 161,
27888 /* 72014 */ GIR_Done,
27889 /* 72015 */ // Label 1857: @72015
27890 /* 72015 */ GIM_Reject,
27891 /* 72016 */ // Label 1855: @72016
27892 /* 72016 */ GIM_Reject,
27893 /* 72017 */ // Label 1853: @72017
27894 /* 72017 */ GIM_Reject,
27895 /* 72018 */ // Label 82: @72018
27896 /* 72018 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1860*/ GIMT_Encode4(72132),
27897 /* 72029 */ /*GILLT_s32*//*Label 1858*/ GIMT_Encode4(72037),
27898 /* 72033 */ /*GILLT_s64*//*Label 1859*/ GIMT_Encode4(72068),
27899 /* 72037 */ // Label 1858: @72037
27900 /* 72037 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(72067), // Rule ID 129 //
27901 /* 72042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
27902 /* 72045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
27903 /* 72048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27904 /* 72052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
27905 /* 72056 */ // (strict_fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
27906 /* 72056 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
27907 /* 72061 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27908 /* 72065 */ GIR_RootConstrainSelectedInstOperands,
27909 /* 72066 */ // GIR_Coverage, 129,
27910 /* 72066 */ GIR_Done,
27911 /* 72067 */ // Label 1861: @72067
27912 /* 72067 */ GIM_Reject,
27913 /* 72068 */ // Label 1859: @72068
27914 /* 72068 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(72131),
27915 /* 72073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
27916 /* 72076 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(72103), // Rule ID 131 //
27917 /* 72081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
27918 /* 72084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27919 /* 72088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
27920 /* 72092 */ // (strict_fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
27921 /* 72092 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
27922 /* 72097 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27923 /* 72101 */ GIR_RootConstrainSelectedInstOperands,
27924 /* 72102 */ // GIR_Coverage, 131,
27925 /* 72102 */ GIR_Done,
27926 /* 72103 */ // Label 1863: @72103
27927 /* 72103 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(72130), // Rule ID 133 //
27928 /* 72108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
27929 /* 72111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27930 /* 72115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
27931 /* 72119 */ // (strict_fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
27932 /* 72119 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
27933 /* 72124 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
27934 /* 72128 */ GIR_RootConstrainSelectedInstOperands,
27935 /* 72129 */ // GIR_Coverage, 133,
27936 /* 72129 */ GIR_Done,
27937 /* 72130 */ // Label 1864: @72130
27938 /* 72130 */ GIM_Reject,
27939 /* 72131 */ // Label 1862: @72131
27940 /* 72131 */ GIM_Reject,
27941 /* 72132 */ // Label 1860: @72132
27942 /* 72132 */ GIM_Reject,
27943 /* 72133 */ // Label 83: @72133
27944 /* 72133 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(72148), // Rule ID 90 //
27945 /* 72138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
27946 /* 72141 */ // (trap) => (TRAP)
27947 /* 72141 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
27948 /* 72146 */ GIR_RootConstrainSelectedInstOperands,
27949 /* 72147 */ // GIR_Coverage, 90,
27950 /* 72147 */ GIR_Done,
27951 /* 72148 */ // Label 1865: @72148
27952 /* 72148 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(72163), // Rule ID 1139 //
27953 /* 72153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
27954 /* 72156 */ // (trap) => (TRAP_MM)
27955 /* 72156 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
27956 /* 72161 */ GIR_RootConstrainSelectedInstOperands,
27957 /* 72162 */ // GIR_Coverage, 1139,
27958 /* 72162 */ GIR_Done,
27959 /* 72163 */ // Label 1866: @72163
27960 /* 72163 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(72178), // Rule ID 2036 //
27961 /* 72168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
27962 /* 72171 */ // (trap) => (Break16)
27963 /* 72171 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
27964 /* 72176 */ GIR_RootConstrainSelectedInstOperands,
27965 /* 72177 */ // GIR_Coverage, 2036,
27966 /* 72177 */ GIR_Done,
27967 /* 72178 */ // Label 1867: @72178
27968 /* 72178 */ GIM_Reject,
27969 /* 72179 */ // Label 84: @72179
27970 /* 72179 */ GIM_Reject,
27971 /* 72180 */ }; // Size: 72180 bytes
27972 return MatchTable0;
27973}
27974#undef GIMT_Encode2
27975#undef GIMT_Encode4
27976#undef GIMT_Encode8
27977
27978
27979#endif // GET_GLOBALISEL_IMPL
27980
27981#ifdef GET_GLOBALISEL_PREDICATES_DECL
27982
27983PredicateBitset AvailableModuleFeatures;
27984mutable PredicateBitset AvailableFunctionFeatures;
27985PredicateBitset getAvailableFeatures() const {
27986 return AvailableModuleFeatures | AvailableFunctionFeatures;
27987}
27988PredicateBitset
27989computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
27990PredicateBitset
27991computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
27992 const MachineFunction *MF) const;
27993void setupGeneratedPerFunctionState(MachineFunction &MF) override;
27994
27995#endif // GET_GLOBALISEL_PREDICATES_DECL
27996
27997#ifdef GET_GLOBALISEL_PREDICATES_INIT
27998
27999AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
28000AvailableFunctionFeatures()
28001
28002#endif // GET_GLOBALISEL_PREDICATES_INIT
28003
28004