1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 44;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s32,
47 GILLT_s64,
48 GILLT_v4s8,
49 GILLT_v16s8,
50 GILLT_v2s16,
51 GILLT_v8s16,
52 GILLT_v4s32,
53 GILLT_v2s64,
54};
55const static size_t NumTypeObjects = 8;
56const static LLT TypeObjects[] = {
57 LLT::scalar(32),
58 LLT::scalar(64),
59 LLT::vector(ElementCount::getFixed(4), LLT::scalar(8)),
60 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
61 LLT::vector(ElementCount::getFixed(2), LLT::scalar(16)),
62 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
63 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
64 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
65};
66
67// Bits for subtarget features that participate in instruction matching.
68enum SubtargetFeatureBits : uint8_t {
69 Feature_IsPTR64bitBit = 23,
70 Feature_UseCompactBranchesBit = 41,
71 Feature_HasMips2Bit = 7,
72 Feature_HasMips3Bit = 18,
73 Feature_HasMips4_32Bit = 26,
74 Feature_NotMips4_32Bit = 27,
75 Feature_HasMips4_32r2Bit = 19,
76 Feature_HasMips32Bit = 3,
77 Feature_HasMips32r2Bit = 6,
78 Feature_HasMips32r6Bit = 28,
79 Feature_NotMips32r6Bit = 4,
80 Feature_IsGP64bitBit = 21,
81 Feature_HasMips64Bit = 24,
82 Feature_HasMips64r2Bit = 22,
83 Feature_HasMips64r6Bit = 29,
84 Feature_NotMips64r6Bit = 5,
85 Feature_InMips16ModeBit = 30,
86 Feature_NotInMips16ModeBit = 0,
87 Feature_HasCnMipsBit = 25,
88 Feature_NotCnMipsBit = 8,
89 Feature_IsSym32Bit = 38,
90 Feature_IsSym64Bit = 39,
91 Feature_IsN64Bit = 40,
92 Feature_RelocNotPICBit = 10,
93 Feature_RelocPICBit = 36,
94 Feature_HasStdEncBit = 1,
95 Feature_NotDSPBit = 12,
96 Feature_InMicroMipsBit = 34,
97 Feature_NotInMicroMipsBit = 2,
98 Feature_IsLEBit = 42,
99 Feature_IsBEBit = 43,
100 Feature_HasEVABit = 35,
101 Feature_HasMSABit = 33,
102 Feature_HasMadd4Bit = 20,
103 Feature_UseIndirectJumpsHazardBit = 13,
104 Feature_NoIndirectJumpGuardsBit = 11,
105 Feature_IsR5900Bit = 37,
106 Feature_NotR5900Bit = 9,
107 Feature_IsFP64bitBit = 17,
108 Feature_NotFP64bitBit = 16,
109 Feature_IsNotSingleFloatBit = 15,
110 Feature_IsNotSoftFloatBit = 14,
111 Feature_HasDSPBit = 31,
112 Feature_HasDSPR2Bit = 32,
113};
114
115PredicateBitset MipsInstructionSelector::
116computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
117 PredicateBitset Features{};
118 if (Subtarget->isABI_N64())
119 Features.set(Feature_IsPTR64bitBit);
120 if (Subtarget->useCompactBranches())
121 Features.set(Feature_UseCompactBranchesBit);
122 if (Subtarget->hasMips2())
123 Features.set(Feature_HasMips2Bit);
124 if (Subtarget->hasMips3())
125 Features.set(Feature_HasMips3Bit);
126 if (Subtarget->hasMips4_32())
127 Features.set(Feature_HasMips4_32Bit);
128 if (!Subtarget->hasMips4_32())
129 Features.set(Feature_NotMips4_32Bit);
130 if (Subtarget->hasMips4_32r2())
131 Features.set(Feature_HasMips4_32r2Bit);
132 if (Subtarget->hasMips32())
133 Features.set(Feature_HasMips32Bit);
134 if (Subtarget->hasMips32r2())
135 Features.set(Feature_HasMips32r2Bit);
136 if (Subtarget->hasMips32r6())
137 Features.set(Feature_HasMips32r6Bit);
138 if (!Subtarget->hasMips32r6())
139 Features.set(Feature_NotMips32r6Bit);
140 if (Subtarget->isGP64bit())
141 Features.set(Feature_IsGP64bitBit);
142 if (Subtarget->hasMips64())
143 Features.set(Feature_HasMips64Bit);
144 if (Subtarget->hasMips64r2())
145 Features.set(Feature_HasMips64r2Bit);
146 if (Subtarget->hasMips64r6())
147 Features.set(Feature_HasMips64r6Bit);
148 if (!Subtarget->hasMips64r6())
149 Features.set(Feature_NotMips64r6Bit);
150 if (Subtarget->inMips16Mode())
151 Features.set(Feature_InMips16ModeBit);
152 if (!Subtarget->inMips16Mode())
153 Features.set(Feature_NotInMips16ModeBit);
154 if (Subtarget->hasCnMips())
155 Features.set(Feature_HasCnMipsBit);
156 if (!Subtarget->hasCnMips())
157 Features.set(Feature_NotCnMipsBit);
158 if (Subtarget->hasSym32())
159 Features.set(Feature_IsSym32Bit);
160 if (!Subtarget->hasSym32())
161 Features.set(Feature_IsSym64Bit);
162 if (Subtarget->isABI_N64())
163 Features.set(Feature_IsN64Bit);
164 if (!TM.isPositionIndependent())
165 Features.set(Feature_RelocNotPICBit);
166 if (TM.isPositionIndependent())
167 Features.set(Feature_RelocPICBit);
168 if (Subtarget->hasStandardEncoding())
169 Features.set(Feature_HasStdEncBit);
170 if (!Subtarget->hasDSP())
171 Features.set(Feature_NotDSPBit);
172 if (Subtarget->inMicroMipsMode())
173 Features.set(Feature_InMicroMipsBit);
174 if (!Subtarget->inMicroMipsMode())
175 Features.set(Feature_NotInMicroMipsBit);
176 if (Subtarget->isLittle())
177 Features.set(Feature_IsLEBit);
178 if (!Subtarget->isLittle())
179 Features.set(Feature_IsBEBit);
180 if (Subtarget->hasEVA())
181 Features.set(Feature_HasEVABit);
182 if (Subtarget->hasMSA())
183 Features.set(Feature_HasMSABit);
184 if (!Subtarget->disableMadd4())
185 Features.set(Feature_HasMadd4Bit);
186 if (Subtarget->useIndirectJumpsHazard())
187 Features.set(Feature_UseIndirectJumpsHazardBit);
188 if (!Subtarget->useIndirectJumpsHazard())
189 Features.set(Feature_NoIndirectJumpGuardsBit);
190 if (Subtarget->isR5900())
191 Features.set(Feature_IsR5900Bit);
192 if (!Subtarget->isR5900())
193 Features.set(Feature_NotR5900Bit);
194 if (Subtarget->isFP64bit())
195 Features.set(Feature_IsFP64bitBit);
196 if (!Subtarget->isFP64bit())
197 Features.set(Feature_NotFP64bitBit);
198 if (!Subtarget->isSingleFloat())
199 Features.set(Feature_IsNotSingleFloatBit);
200 if (!Subtarget->useSoftFloat())
201 Features.set(Feature_IsNotSoftFloatBit);
202 if (Subtarget->hasDSP())
203 Features.set(Feature_HasDSPBit);
204 if (Subtarget->hasDSPR2())
205 Features.set(Feature_HasDSPR2Bit);
206 return Features;
207}
208
209void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
210 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
211}
212PredicateBitset MipsInstructionSelector::
213computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
214 PredicateBitset Features{};
215 return Features;
216}
217
218// Feature bitsets.
219enum {
220 GIFBS_Invalid,
221 GIFBS_HasCnMips,
222 GIFBS_HasDSP,
223 GIFBS_HasDSPR2,
224 GIFBS_HasMSA,
225 GIFBS_InMicroMips,
226 GIFBS_InMips16Mode,
227 GIFBS_NotInMips16Mode,
228 GIFBS_HasDSP_InMicroMips,
229 GIFBS_HasDSP_NotInMicroMips,
230 GIFBS_HasDSPR2_InMicroMips,
231 GIFBS_HasMSA_HasStdEnc,
232 GIFBS_HasMSA_IsBE,
233 GIFBS_HasMSA_IsLE,
234 GIFBS_HasMips32r6_HasStdEnc,
235 GIFBS_HasMips32r6_InMicroMips,
236 GIFBS_HasMips64r2_HasStdEnc,
237 GIFBS_HasMips64r6_HasStdEnc,
238 GIFBS_HasStdEnc_IsNotSoftFloat,
239 GIFBS_HasStdEnc_NotInMicroMips,
240 GIFBS_HasStdEnc_NotMips4_32,
241 GIFBS_InMicroMips_IsNotSoftFloat,
242 GIFBS_InMicroMips_NotMips32r6,
243 GIFBS_IsFP64bit_IsNotSingleFloat,
244 GIFBS_IsGP64bit_NotInMips16Mode,
245 GIFBS_IsNotSingleFloat_NotFP64bit,
246 GIFBS_HasMSA_HasMips64_HasStdEnc,
247 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
248 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
249 GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
250 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
251 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
252 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
253 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
254 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
255 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
256 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
257 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat,
258 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit,
259 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
260 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
261 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
262 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
263 GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat,
264 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
265 GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat,
266 GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit,
267 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
268 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
269 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
270 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
271 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
272 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips,
273 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32,
274 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips,
275 GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32,
276 GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat,
277 GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit,
278 GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6,
279 GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode,
280 GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
281 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
282 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
283 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
284 GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
285 GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
286 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips,
287 GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
288 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
289 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
290 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
291 GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
292 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
293 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
294};
295constexpr static PredicateBitset FeatureBitsets[] {
296 {}, // GIFBS_Invalid
297 {Feature_HasCnMipsBit, },
298 {Feature_HasDSPBit, },
299 {Feature_HasDSPR2Bit, },
300 {Feature_HasMSABit, },
301 {Feature_InMicroMipsBit, },
302 {Feature_InMips16ModeBit, },
303 {Feature_NotInMips16ModeBit, },
304 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
305 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
306 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
307 {Feature_HasMSABit, Feature_HasStdEncBit, },
308 {Feature_HasMSABit, Feature_IsBEBit, },
309 {Feature_HasMSABit, Feature_IsLEBit, },
310 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
311 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
312 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
313 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
314 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
315 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
316 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
317 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
318 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
319 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
320 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
321 {Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
322 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
323 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
324 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
325 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
326 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
327 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
328 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
329 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
330 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
331 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
332 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
333 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
334 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
335 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
336 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
337 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
338 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
339 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
340 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
341 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, },
342 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, },
343 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
344 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
345 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
346 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
347 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
348 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, },
349 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotMips4_32Bit, },
350 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
351 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
352 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, },
353 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
354 {Feature_InMicroMipsBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
355 {Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
356 {Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
357 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
358 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
359 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
360 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
361 {Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
362 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
363 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
364 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
365 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
366 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
367 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
368 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
369 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSingleFloatBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
370};
371
372// ComplexPattern predicates.
373enum {
374 GICP_Invalid,
375};
376// See constructor for table contents
377
378MipsInstructionSelector::ComplexMatcherMemFn
379MipsInstructionSelector::ComplexPredicateFns[] = {
380 nullptr, // GICP_Invalid
381};
382
383// PatFrag predicates.
384enum {
385 GICXXPred_MI_Predicate_fadd_contract = GICXXPred_Invalid + 1,
386 GICXXPred_MI_Predicate_ffloor_nnan,
387 GICXXPred_MI_Predicate_fmul_contract,
388 GICXXPred_MI_Predicate_fsub_contract,
389 GICXXPred_MI_Predicate_or_disjoint,
390};
391bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
392 const MachineFunction &MF = *MI.getParent()->getParent();
393 const MachineRegisterInfo &MRI = MF.getRegInfo();
394 const auto &Operands = State.RecordedOperands;
395 (void)Operands;
396 (void)MRI;
397 switch (PredicateID) {
398 case GICXXPred_MI_Predicate_fadd_contract: {
399
400 return MI.getFlag(MachineInstr::FmContract);
401
402 }
403 case GICXXPred_MI_Predicate_ffloor_nnan: {
404
405 return MI.getFlag(MachineInstr::FmNoNans);
406
407 }
408 case GICXXPred_MI_Predicate_fmul_contract: {
409
410 return MI.getFlag(MachineInstr::FmContract);
411
412 }
413 case GICXXPred_MI_Predicate_fsub_contract: {
414
415 return MI.getFlag(MachineInstr::FmContract);
416
417 }
418 case GICXXPred_MI_Predicate_or_disjoint: {
419
420 return MI.getFlag(MachineInstr::Disjoint);
421
422 }
423 }
424 llvm_unreachable("Unknown predicate");
425 return false;
426}
427// PatFrag predicates.
428bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
429 const auto &Operands = State.RecordedOperands;
430 Register Reg = MO.getReg();
431 (void)Operands;
432 (void)Reg;
433 llvm_unreachable("Unknown predicate");
434 return false;
435}
436// PatFrag predicates.
437enum {
438 GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1,
439 GICXXPred_I64_Predicate_Float8E4M3FN,
440 GICXXPred_I64_Predicate_Float8E5M2,
441 GICXXPred_I64_Predicate_NearestTiesToEven,
442 GICXXPred_I64_Predicate_immLi16,
443 GICXXPred_I64_Predicate_immSExt6,
444 GICXXPred_I64_Predicate_immSExt10,
445 GICXXPred_I64_Predicate_immSExtAddiur2,
446 GICXXPred_I64_Predicate_immSExtAddius5,
447 GICXXPred_I64_Predicate_immZExt1,
448 GICXXPred_I64_Predicate_immZExt1Ptr,
449 GICXXPred_I64_Predicate_immZExt2,
450 GICXXPred_I64_Predicate_immZExt2Lsa,
451 GICXXPred_I64_Predicate_immZExt2Ptr,
452 GICXXPred_I64_Predicate_immZExt2Shift,
453 GICXXPred_I64_Predicate_immZExt3,
454 GICXXPred_I64_Predicate_immZExt3Ptr,
455 GICXXPred_I64_Predicate_immZExt4,
456 GICXXPred_I64_Predicate_immZExt4Ptr,
457 GICXXPred_I64_Predicate_immZExt5,
458 GICXXPred_I64_Predicate_immZExt5_64,
459 GICXXPred_I64_Predicate_immZExt6,
460 GICXXPred_I64_Predicate_immZExt8,
461 GICXXPred_I64_Predicate_immZExt10,
462 GICXXPred_I64_Predicate_immZExtAndi16,
463 GICXXPred_I64_Predicate_immi32Cst7,
464 GICXXPred_I64_Predicate_immi32Cst15,
465 GICXXPred_I64_Predicate_immi32Cst31,
466 GICXXPred_I64_Predicate_timmSExt6,
467 GICXXPred_I64_Predicate_timmZExt1,
468 GICXXPred_I64_Predicate_timmZExt1Ptr,
469 GICXXPred_I64_Predicate_timmZExt2,
470 GICXXPred_I64_Predicate_timmZExt2Ptr,
471 GICXXPred_I64_Predicate_timmZExt3,
472 GICXXPred_I64_Predicate_timmZExt3Ptr,
473 GICXXPred_I64_Predicate_timmZExt4,
474 GICXXPred_I64_Predicate_timmZExt4Ptr,
475 GICXXPred_I64_Predicate_timmZExt5,
476 GICXXPred_I64_Predicate_timmZExt6,
477 GICXXPred_I64_Predicate_timmZExt8,
478 GICXXPred_I64_Predicate_timmZExt10,
479};
480bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
481 switch (PredicateID) {
482 case GICXXPred_I64_Predicate_FPNoSaturation: {
483 return Imm == 0;
484 }
485 case GICXXPred_I64_Predicate_Float8E4M3FN: {
486 return Imm == APFloatBase::S_Float8E4M3FN;
487 }
488 case GICXXPred_I64_Predicate_Float8E5M2: {
489 return Imm == APFloatBase::S_Float8E5M2;
490 }
491 case GICXXPred_I64_Predicate_NearestTiesToEven: {
492 return Imm == static_cast<int>(RoundingMode::NearestTiesToEven);
493 }
494 case GICXXPred_I64_Predicate_immLi16: {
495 return Imm >= -1 && Imm <= 126;
496 }
497 case GICXXPred_I64_Predicate_immSExt6: {
498 return isInt<6>(Imm);
499 }
500 case GICXXPred_I64_Predicate_immSExt10: {
501 return isInt<10>(Imm);
502 }
503 case GICXXPred_I64_Predicate_immSExtAddiur2: {
504 return Imm == 1 || Imm == -1 ||
505 ((Imm % 4 == 0) &&
506 Imm < 28 && Imm > 0);
507 }
508 case GICXXPred_I64_Predicate_immSExtAddius5: {
509 return Imm >= -8 && Imm <= 7;
510 }
511 case GICXXPred_I64_Predicate_immZExt1: {
512 return isUInt<1>(Imm);
513 }
514 case GICXXPred_I64_Predicate_immZExt1Ptr: {
515 return isUInt<1>(Imm);
516 }
517 case GICXXPred_I64_Predicate_immZExt2: {
518 return isUInt<2>(Imm);
519 }
520 case GICXXPred_I64_Predicate_immZExt2Lsa: {
521 return isUInt<2>(Imm - 1);
522 }
523 case GICXXPred_I64_Predicate_immZExt2Ptr: {
524 return isUInt<2>(Imm);
525 }
526 case GICXXPred_I64_Predicate_immZExt2Shift: {
527 return Imm >= 1 && Imm <= 8;
528 }
529 case GICXXPred_I64_Predicate_immZExt3: {
530 return isUInt<3>(Imm);
531 }
532 case GICXXPred_I64_Predicate_immZExt3Ptr: {
533 return isUInt<3>(Imm);
534 }
535 case GICXXPred_I64_Predicate_immZExt4: {
536 return isUInt<4>(Imm);
537 }
538 case GICXXPred_I64_Predicate_immZExt4Ptr: {
539 return isUInt<4>(Imm);
540 }
541 case GICXXPred_I64_Predicate_immZExt5: {
542 return Imm == (Imm & 0x1f);
543 }
544 case GICXXPred_I64_Predicate_immZExt5_64: {
545 return Imm == (Imm & 0x1f);
546 }
547 case GICXXPred_I64_Predicate_immZExt6: {
548 return Imm == (Imm & 0x3f);
549 }
550 case GICXXPred_I64_Predicate_immZExt8: {
551 return isUInt<8>(Imm);
552 }
553 case GICXXPred_I64_Predicate_immZExt10: {
554 return isUInt<10>(Imm);
555 }
556 case GICXXPred_I64_Predicate_immZExtAndi16: {
557 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
558 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
559 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
560 }
561 case GICXXPred_I64_Predicate_immi32Cst7: {
562 return isUInt<32>(Imm) && Imm == 7;
563 }
564 case GICXXPred_I64_Predicate_immi32Cst15: {
565 return isUInt<32>(Imm) && Imm == 15;
566 }
567 case GICXXPred_I64_Predicate_immi32Cst31: {
568 return isUInt<32>(Imm) && Imm == 31;
569 }
570 case GICXXPred_I64_Predicate_timmSExt6: {
571 return isInt<6>(Imm);
572 }
573 case GICXXPred_I64_Predicate_timmZExt1: {
574 return isUInt<1>(Imm);
575 }
576 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
577 return isUInt<1>(Imm);
578 }
579 case GICXXPred_I64_Predicate_timmZExt2: {
580 return isUInt<2>(Imm);
581 }
582 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
583 return isUInt<2>(Imm);
584 }
585 case GICXXPred_I64_Predicate_timmZExt3: {
586 return isUInt<3>(Imm);
587 }
588 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
589 return isUInt<3>(Imm);
590 }
591 case GICXXPred_I64_Predicate_timmZExt4: {
592 return isUInt<4>(Imm);
593 }
594 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
595 return isUInt<4>(Imm);
596 }
597 case GICXXPred_I64_Predicate_timmZExt5: {
598 return Imm == (Imm & 0x1f);
599 }
600 case GICXXPred_I64_Predicate_timmZExt6: {
601 return Imm == (Imm & 0x3f);
602 }
603 case GICXXPred_I64_Predicate_timmZExt8: {
604 return isUInt<8>(Imm);
605 }
606 case GICXXPred_I64_Predicate_timmZExt10: {
607 return isUInt<10>(Imm);
608 }
609 }
610 llvm_unreachable("Unknown predicate");
611 return false;
612}
613// PatFrag predicates.
614bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
615 llvm_unreachable("Unknown predicate");
616 return false;
617}
618// PatFrag predicates.
619enum {
620 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
621 GICXXPred_APInt_Predicate_imm32ZExt16,
622};
623bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
624 switch (PredicateID) {
625 case GICXXPred_APInt_Predicate_imm32SExt16: {
626 return isInt<16>(Imm.getSExtValue());
627 }
628 case GICXXPred_APInt_Predicate_imm32ZExt16: {
629
630 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
631
632 }
633 }
634 llvm_unreachable("Unknown predicate");
635 return false;
636}
637bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
638 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
639 return false;
640}
641// Custom renderers.
642enum {
643 GICR_Invalid,
644 GICR_renderFrameIndex,
645};
646MipsInstructionSelector::CustomRendererFn
647MipsInstructionSelector::CustomRenderers[] = {
648 nullptr, // GICR_Invalid
649 &MipsInstructionSelector::renderFrameIndex,
650};
651
652bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
653 const PredicateBitset AvailableFeatures = getAvailableFeatures();
654 MachineIRBuilder B(I);
655 State.MIs.clear();
656 State.MIs.push_back(&I);
657
658 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
659 return true;
660 }
661
662 return false;
663}
664
665bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
666 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
667}
668#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
669#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
670#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
671#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
672#else
673#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
674#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
675#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
676#endif
677const uint8_t *MipsInstructionSelector::getMatchTable() const {
678 constexpr static uint8_t MatchTable0[] = {
679 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(311), /*)*//*default:*//*Label 84*/ GIMT_Encode4(68088),
680 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1034),
681 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2315),
682 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2989),
683 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3428),
684 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3690),
685 /* 30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(3952),
686 /* 34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4214), GIMT_Encode4(0), GIMT_Encode4(0),
687 /* 46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4476),
688 /* 50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5010),
689 /* 54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5395), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
690 /* 118 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6232),
691 /* 122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6331), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
692 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6666), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
693 /* 186 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(10660),
694 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(10724),
695 /* 194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(10791), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
696 /* 230 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(10858),
697 /* 234 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11046),
698 /* 238 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11212),
699 /* 242 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11378),
700 /* 246 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(11544),
701 /* 250 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(11710),
702 /* 254 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(11876),
703 /* 258 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12042),
704 /* 262 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12208),
705 /* 266 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12374),
706 /* 270 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(12540),
707 /* 274 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(12706), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
708 /* 334 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(12872), GIMT_Encode4(0), GIMT_Encode4(0),
709 /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 29*/ GIMT_Encode4(19036),
710 /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ GIMT_Encode4(32978), GIMT_Encode4(0), GIMT_Encode4(0),
711 /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 31*/ GIMT_Encode4(37938),
712 /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 32*/ GIMT_Encode4(38003), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
713 /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 33*/ GIMT_Encode4(38066), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
714 /* 398 */ /*TargetOpcode::G_SEXT*//*Label 34*/ GIMT_Encode4(38125),
715 /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 35*/ GIMT_Encode4(39582),
716 /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 36*/ GIMT_Encode4(39901),
717 /* 410 */ /*TargetOpcode::G_SHL*//*Label 37*/ GIMT_Encode4(40098),
718 /* 414 */ /*TargetOpcode::G_LSHR*//*Label 38*/ GIMT_Encode4(41873),
719 /* 418 */ /*TargetOpcode::G_ASHR*//*Label 39*/ GIMT_Encode4(43648), GIMT_Encode4(0), GIMT_Encode4(0),
720 /* 430 */ /*TargetOpcode::G_ROTR*//*Label 40*/ GIMT_Encode4(45382), GIMT_Encode4(0),
721 /* 438 */ /*TargetOpcode::G_ICMP*//*Label 41*/ GIMT_Encode4(45665),
722 /* 442 */ /*TargetOpcode::G_FCMP*//*Label 42*/ GIMT_Encode4(48159), GIMT_Encode4(0), GIMT_Encode4(0),
723 /* 454 */ /*TargetOpcode::G_SELECT*//*Label 43*/ GIMT_Encode4(49084), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
724 /* 498 */ /*TargetOpcode::G_UMULH*//*Label 44*/ GIMT_Encode4(58818),
725 /* 502 */ /*TargetOpcode::G_SMULH*//*Label 45*/ GIMT_Encode4(58924), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
726 /* 562 */ /*TargetOpcode::G_FADD*//*Label 46*/ GIMT_Encode4(59030),
727 /* 566 */ /*TargetOpcode::G_FSUB*//*Label 47*/ GIMT_Encode4(60342),
728 /* 570 */ /*TargetOpcode::G_FMUL*//*Label 48*/ GIMT_Encode4(61172),
729 /* 574 */ /*TargetOpcode::G_FMA*//*Label 49*/ GIMT_Encode4(61682), GIMT_Encode4(0),
730 /* 582 */ /*TargetOpcode::G_FDIV*//*Label 50*/ GIMT_Encode4(61782), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
731 /* 606 */ /*TargetOpcode::G_FEXP2*//*Label 51*/ GIMT_Encode4(62104), GIMT_Encode4(0), GIMT_Encode4(0),
732 /* 618 */ /*TargetOpcode::G_FLOG2*//*Label 52*/ GIMT_Encode4(62176), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
733 /* 634 */ /*TargetOpcode::G_FNEG*//*Label 53*/ GIMT_Encode4(62248),
734 /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 54*/ GIMT_Encode4(62426),
735 /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 55*/ GIMT_Encode4(62541),
736 /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 56*/ GIMT_Encode4(62648),
737 /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 57*/ GIMT_Encode4(62720),
738 /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 58*/ GIMT_Encode4(62792),
739 /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 59*/ GIMT_Encode4(63074), GIMT_Encode4(0), GIMT_Encode4(0),
740 /* 670 */ /*TargetOpcode::G_FABS*//*Label 60*/ GIMT_Encode4(63146), GIMT_Encode4(0), GIMT_Encode4(0),
741 /* 682 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 61*/ GIMT_Encode4(63386),
742 /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 62*/ GIMT_Encode4(63458),
743 /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 63*/ GIMT_Encode4(63528),
744 /* 694 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 64*/ GIMT_Encode4(63598),
745 /* 698 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 65*/ GIMT_Encode4(63668), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
746 /* 758 */ /*TargetOpcode::G_SMIN*//*Label 66*/ GIMT_Encode4(63738),
747 /* 762 */ /*TargetOpcode::G_SMAX*//*Label 67*/ GIMT_Encode4(63902),
748 /* 766 */ /*TargetOpcode::G_UMIN*//*Label 68*/ GIMT_Encode4(64066),
749 /* 770 */ /*TargetOpcode::G_UMAX*//*Label 69*/ GIMT_Encode4(64230), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
750 /* 786 */ /*TargetOpcode::G_BR*//*Label 70*/ GIMT_Encode4(64394), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
751 /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(64512),
752 /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(65104), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
753 /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 73*/ GIMT_Encode4(65155), GIMT_Encode4(0), GIMT_Encode4(0),
754 /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(65646),
755 /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(65846), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
756 /* 918 */ /*TargetOpcode::G_FSQRT*//*Label 76*/ GIMT_Encode4(66007), GIMT_Encode4(0),
757 /* 926 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(66271), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
758 /* 958 */ /*TargetOpcode::G_STRICT_FADD*//*Label 78*/ GIMT_Encode4(66343),
759 /* 962 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 79*/ GIMT_Encode4(67183),
760 /* 966 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 80*/ GIMT_Encode4(67673),
761 /* 970 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 81*/ GIMT_Encode4(67803), GIMT_Encode4(0), GIMT_Encode4(0),
762 /* 982 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 82*/ GIMT_Encode4(67933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
763 /* 1030 */ /*TargetOpcode::G_TRAP*//*Label 83*/ GIMT_Encode4(68045),
764 /* 1034 */ // Label 0: @1034
765 /* 1034 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 93*/ GIMT_Encode4(2314),
766 /* 1045 */ /*GILLT_s32*//*Label 85*/ GIMT_Encode4(1077),
767 /* 1049 */ /*GILLT_s64*//*Label 86*/ GIMT_Encode4(1475),
768 /* 1053 */ /*GILLT_v4s8*//*Label 87*/ GIMT_Encode4(1640),
769 /* 1057 */ /*GILLT_v16s8*//*Label 88*/ GIMT_Encode4(1671),
770 /* 1061 */ /*GILLT_v2s16*//*Label 89*/ GIMT_Encode4(1824),
771 /* 1065 */ /*GILLT_v8s16*//*Label 90*/ GIMT_Encode4(1855),
772 /* 1069 */ /*GILLT_v4s32*//*Label 91*/ GIMT_Encode4(2008),
773 /* 1073 */ /*GILLT_v2s64*//*Label 92*/ GIMT_Encode4(2161),
774 /* 1077 */ // Label 85: @1077
775 /* 1077 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1474),
776 /* 1082 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
777 /* 1085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
778 /* 1088 */ GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1261),
779 /* 1093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
780 /* 1097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 96*/ GIMT_Encode4(1159), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2539 //
781 /* 1104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
782 /* 1108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
783 /* 1112 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
784 /* 1116 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
785 /* 1120 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
786 /* 1125 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
787 /* 1129 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
788 /* 1133 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
789 /* 1137 */ // MIs[2] Operand 1
790 /* 1137 */ // No operand predicates
791 /* 1137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
792 /* 1141 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
793 /* 1143 */ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
794 /* 1143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
795 /* 1146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
796 /* 1148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
797 /* 1152 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
798 /* 1154 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
799 /* 1157 */ GIR_RootConstrainSelectedInstOperands,
800 /* 1158 */ // GIR_Coverage, 2539,
801 /* 1158 */ GIR_EraseRootFromParent_Done,
802 /* 1159 */ // Label 96: @1159
803 /* 1159 */ GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1260),
804 /* 1164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
805 /* 1168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 98*/ GIMT_Encode4(1226), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 862 //
806 /* 1175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
807 /* 1179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
808 /* 1183 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
809 /* 1187 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
810 /* 1191 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
811 /* 1196 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
812 /* 1200 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
813 /* 1204 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
814 /* 1208 */ // MIs[2] Operand 1
815 /* 1208 */ // No operand predicates
816 /* 1208 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
817 /* 1210 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
818 /* 1210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
819 /* 1213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
820 /* 1215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
821 /* 1219 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
822 /* 1221 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
823 /* 1224 */ GIR_RootConstrainSelectedInstOperands,
824 /* 1225 */ // GIR_Coverage, 862,
825 /* 1225 */ GIR_EraseRootFromParent_Done,
826 /* 1226 */ // Label 98: @1226
827 /* 1226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 99*/ GIMT_Encode4(1259), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 40 //
828 /* 1233 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
829 /* 1237 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
830 /* 1241 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
831 /* 1245 */ // MIs[1] Operand 1
832 /* 1245 */ // No operand predicates
833 /* 1245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
834 /* 1247 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
835 /* 1247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
836 /* 1250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
837 /* 1252 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
838 /* 1254 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
839 /* 1257 */ GIR_RootConstrainSelectedInstOperands,
840 /* 1258 */ // GIR_Coverage, 40,
841 /* 1258 */ GIR_EraseRootFromParent_Done,
842 /* 1259 */ // Label 99: @1259
843 /* 1259 */ GIM_Reject,
844 /* 1260 */ // Label 97: @1260
845 /* 1260 */ GIM_Reject,
846 /* 1261 */ // Label 95: @1261
847 /* 1261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 100*/ GIMT_Encode4(1302), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2297 //
848 /* 1268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
849 /* 1272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
850 /* 1276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
851 /* 1280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
852 /* 1284 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
853 /* 1288 */ // MIs[1] Operand 1
854 /* 1288 */ // No operand predicates
855 /* 1288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
856 /* 1290 */ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
857 /* 1290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
858 /* 1293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
859 /* 1295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
860 /* 1297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
861 /* 1300 */ GIR_RootConstrainSelectedInstOperands,
862 /* 1301 */ // GIR_Coverage, 2297,
863 /* 1301 */ GIR_EraseRootFromParent_Done,
864 /* 1302 */ // Label 100: @1302
865 /* 1302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 101*/ GIMT_Encode4(1343), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2298 //
866 /* 1309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
867 /* 1313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
868 /* 1317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
869 /* 1321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
870 /* 1325 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
871 /* 1329 */ // MIs[1] Operand 1
872 /* 1329 */ // No operand predicates
873 /* 1329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
874 /* 1331 */ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
875 /* 1331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
876 /* 1334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
877 /* 1336 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
878 /* 1338 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
879 /* 1341 */ GIR_RootConstrainSelectedInstOperands,
880 /* 1342 */ // GIR_Coverage, 2298,
881 /* 1342 */ GIR_EraseRootFromParent_Done,
882 /* 1343 */ // Label 101: @1343
883 /* 1343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 102*/ GIMT_Encode4(1369), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1230 //
884 /* 1350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
885 /* 1354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
886 /* 1358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
887 /* 1362 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
888 /* 1362 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
889 /* 1367 */ GIR_RootConstrainSelectedInstOperands,
890 /* 1368 */ // GIR_Coverage, 1230,
891 /* 1368 */ GIR_Done,
892 /* 1369 */ // Label 102: @1369
893 /* 1369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 103*/ GIMT_Encode4(1395), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 46 //
894 /* 1376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
895 /* 1380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
896 /* 1384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
897 /* 1388 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
898 /* 1388 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
899 /* 1393 */ GIR_RootConstrainSelectedInstOperands,
900 /* 1394 */ // GIR_Coverage, 46,
901 /* 1394 */ GIR_Done,
902 /* 1395 */ // Label 103: @1395
903 /* 1395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 104*/ GIMT_Encode4(1421), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1082 //
904 /* 1402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
905 /* 1406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
906 /* 1410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
907 /* 1414 */ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
908 /* 1414 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
909 /* 1419 */ GIR_RootConstrainSelectedInstOperands,
910 /* 1420 */ // GIR_Coverage, 1082,
911 /* 1420 */ GIR_Done,
912 /* 1421 */ // Label 104: @1421
913 /* 1421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 105*/ GIMT_Encode4(1447), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1094 //
914 /* 1428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
915 /* 1432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
916 /* 1436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
917 /* 1440 */ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
918 /* 1440 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
919 /* 1445 */ GIR_RootConstrainSelectedInstOperands,
920 /* 1446 */ // GIR_Coverage, 1094,
921 /* 1446 */ GIR_Done,
922 /* 1447 */ // Label 105: @1447
923 /* 1447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 106*/ GIMT_Encode4(1473), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1957 //
924 /* 1454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
925 /* 1458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
926 /* 1462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
927 /* 1466 */ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
928 /* 1466 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
929 /* 1471 */ GIR_RootConstrainSelectedInstOperands,
930 /* 1472 */ // GIR_Coverage, 1957,
931 /* 1472 */ GIR_Done,
932 /* 1473 */ // Label 106: @1473
933 /* 1473 */ GIM_Reject,
934 /* 1474 */ // Label 94: @1474
935 /* 1474 */ GIM_Reject,
936 /* 1475 */ // Label 86: @1475
937 /* 1475 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1639),
938 /* 1480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
939 /* 1483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
940 /* 1486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
941 /* 1490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 108*/ GIMT_Encode4(1552), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 2540 //
942 /* 1497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
943 /* 1501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
944 /* 1505 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
945 /* 1509 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
946 /* 1513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
947 /* 1518 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
948 /* 1522 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
949 /* 1526 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
950 /* 1530 */ // MIs[2] Operand 1
951 /* 1530 */ // No operand predicates
952 /* 1530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
953 /* 1534 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
954 /* 1536 */ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
955 /* 1536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
956 /* 1539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
957 /* 1541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
958 /* 1545 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
959 /* 1547 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
960 /* 1550 */ GIR_RootConstrainSelectedInstOperands,
961 /* 1551 */ // GIR_Coverage, 2540,
962 /* 1551 */ GIR_EraseRootFromParent_Done,
963 /* 1552 */ // Label 108: @1552
964 /* 1552 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1638),
965 /* 1557 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
966 /* 1561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 110*/ GIMT_Encode4(1619), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 863 //
967 /* 1568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
968 /* 1572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
969 /* 1576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
970 /* 1580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
971 /* 1584 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
972 /* 1589 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
973 /* 1593 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
974 /* 1597 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
975 /* 1601 */ // MIs[2] Operand 1
976 /* 1601 */ // No operand predicates
977 /* 1601 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
978 /* 1603 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
979 /* 1603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
980 /* 1606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
981 /* 1608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
982 /* 1612 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
983 /* 1614 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
984 /* 1617 */ GIR_RootConstrainSelectedInstOperands,
985 /* 1618 */ // GIR_Coverage, 863,
986 /* 1618 */ GIR_EraseRootFromParent_Done,
987 /* 1619 */ // Label 110: @1619
988 /* 1619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1637), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 230 //
989 /* 1626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
990 /* 1630 */ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
991 /* 1630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
992 /* 1635 */ GIR_RootConstrainSelectedInstOperands,
993 /* 1636 */ // GIR_Coverage, 230,
994 /* 1636 */ GIR_Done,
995 /* 1637 */ // Label 111: @1637
996 /* 1637 */ GIM_Reject,
997 /* 1638 */ // Label 109: @1638
998 /* 1638 */ GIM_Reject,
999 /* 1639 */ // Label 107: @1639
1000 /* 1639 */ GIM_Reject,
1001 /* 1640 */ // Label 87: @1640
1002 /* 1640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 112*/ GIMT_Encode4(1670), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2062 //
1003 /* 1647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1004 /* 1650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1005 /* 1653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1006 /* 1657 */ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1007 /* 1657 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
1008 /* 1662 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1009 /* 1668 */ GIR_RootConstrainSelectedInstOperands,
1010 /* 1669 */ // GIR_Coverage, 2062,
1011 /* 1669 */ GIR_Done,
1012 /* 1670 */ // Label 112: @1670
1013 /* 1670 */ GIM_Reject,
1014 /* 1671 */ // Label 88: @1671
1015 /* 1671 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1823),
1016 /* 1676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1017 /* 1679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1018 /* 1682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1019 /* 1686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 114*/ GIMT_Encode4(1742), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2541 //
1020 /* 1693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1021 /* 1697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1022 /* 1701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1023 /* 1705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1024 /* 1709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1025 /* 1714 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1026 /* 1719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1027 /* 1723 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1028 /* 1725 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1029 /* 1725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1030 /* 1728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1031 /* 1730 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1032 /* 1732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1033 /* 1736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1034 /* 1740 */ GIR_RootConstrainSelectedInstOperands,
1035 /* 1741 */ // GIR_Coverage, 2541,
1036 /* 1741 */ GIR_EraseRootFromParent_Done,
1037 /* 1742 */ // Label 114: @1742
1038 /* 1742 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1822),
1039 /* 1747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1040 /* 1751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 116*/ GIMT_Encode4(1803), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 868 //
1041 /* 1758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1042 /* 1762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1043 /* 1766 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1044 /* 1770 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1045 /* 1774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1046 /* 1779 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1047 /* 1784 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1048 /* 1786 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1049 /* 1786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1050 /* 1789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1051 /* 1791 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1052 /* 1793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1053 /* 1797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1054 /* 1801 */ GIR_RootConstrainSelectedInstOperands,
1055 /* 1802 */ // GIR_Coverage, 868,
1056 /* 1802 */ GIR_EraseRootFromParent_Done,
1057 /* 1803 */ // Label 116: @1803
1058 /* 1803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 117*/ GIMT_Encode4(1821), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 535 //
1059 /* 1810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1060 /* 1814 */ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1061 /* 1814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1062 /* 1819 */ GIR_RootConstrainSelectedInstOperands,
1063 /* 1820 */ // GIR_Coverage, 535,
1064 /* 1820 */ GIR_Done,
1065 /* 1821 */ // Label 117: @1821
1066 /* 1821 */ GIM_Reject,
1067 /* 1822 */ // Label 115: @1822
1068 /* 1822 */ GIM_Reject,
1069 /* 1823 */ // Label 113: @1823
1070 /* 1823 */ GIM_Reject,
1071 /* 1824 */ // Label 89: @1824
1072 /* 1824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1854), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2056 //
1073 /* 1831 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1074 /* 1834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1075 /* 1837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1076 /* 1841 */ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1077 /* 1841 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
1078 /* 1846 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1079 /* 1852 */ GIR_RootConstrainSelectedInstOperands,
1080 /* 1853 */ // GIR_Coverage, 2056,
1081 /* 1853 */ GIR_Done,
1082 /* 1854 */ // Label 118: @1854
1083 /* 1854 */ GIM_Reject,
1084 /* 1855 */ // Label 90: @1855
1085 /* 1855 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2007),
1086 /* 1860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1087 /* 1863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1088 /* 1866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1089 /* 1870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 120*/ GIMT_Encode4(1926), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2542 //
1090 /* 1877 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1091 /* 1881 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1092 /* 1885 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1093 /* 1889 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1094 /* 1893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1095 /* 1898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1096 /* 1903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1097 /* 1907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1098 /* 1909 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1099 /* 1909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1100 /* 1912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1101 /* 1914 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1102 /* 1916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1103 /* 1920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1104 /* 1924 */ GIR_RootConstrainSelectedInstOperands,
1105 /* 1925 */ // GIR_Coverage, 2542,
1106 /* 1925 */ GIR_EraseRootFromParent_Done,
1107 /* 1926 */ // Label 120: @1926
1108 /* 1926 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2006),
1109 /* 1931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1110 /* 1935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 122*/ GIMT_Encode4(1987), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 869 //
1111 /* 1942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1112 /* 1946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1113 /* 1950 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1114 /* 1954 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1115 /* 1958 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1116 /* 1963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1117 /* 1968 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1118 /* 1970 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1119 /* 1970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1120 /* 1973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1121 /* 1975 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1122 /* 1977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1123 /* 1981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1124 /* 1985 */ GIR_RootConstrainSelectedInstOperands,
1125 /* 1986 */ // GIR_Coverage, 869,
1126 /* 1986 */ GIR_EraseRootFromParent_Done,
1127 /* 1987 */ // Label 122: @1987
1128 /* 1987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 123*/ GIMT_Encode4(2005), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 536 //
1129 /* 1994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1130 /* 1998 */ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1131 /* 1998 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1132 /* 2003 */ GIR_RootConstrainSelectedInstOperands,
1133 /* 2004 */ // GIR_Coverage, 536,
1134 /* 2004 */ GIR_Done,
1135 /* 2005 */ // Label 123: @2005
1136 /* 2005 */ GIM_Reject,
1137 /* 2006 */ // Label 121: @2006
1138 /* 2006 */ GIM_Reject,
1139 /* 2007 */ // Label 119: @2007
1140 /* 2007 */ GIM_Reject,
1141 /* 2008 */ // Label 91: @2008
1142 /* 2008 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2160),
1143 /* 2013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1144 /* 2016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1145 /* 2019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1146 /* 2023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 125*/ GIMT_Encode4(2079), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2543 //
1147 /* 2030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1148 /* 2034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1149 /* 2038 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1150 /* 2042 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1151 /* 2046 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1152 /* 2051 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1153 /* 2056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1154 /* 2060 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1155 /* 2062 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1156 /* 2062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1157 /* 2065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1158 /* 2067 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1159 /* 2069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1160 /* 2073 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1161 /* 2077 */ GIR_RootConstrainSelectedInstOperands,
1162 /* 2078 */ // GIR_Coverage, 2543,
1163 /* 2078 */ GIR_EraseRootFromParent_Done,
1164 /* 2079 */ // Label 125: @2079
1165 /* 2079 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2159),
1166 /* 2084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1167 /* 2088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 127*/ GIMT_Encode4(2140), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 870 //
1168 /* 2095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1169 /* 2099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1170 /* 2103 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1171 /* 2107 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1172 /* 2111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1173 /* 2116 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1174 /* 2121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1175 /* 2123 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1176 /* 2123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1177 /* 2126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1178 /* 2128 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1179 /* 2130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1180 /* 2134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1181 /* 2138 */ GIR_RootConstrainSelectedInstOperands,
1182 /* 2139 */ // GIR_Coverage, 870,
1183 /* 2139 */ GIR_EraseRootFromParent_Done,
1184 /* 2140 */ // Label 127: @2140
1185 /* 2140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2158), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 537 //
1186 /* 2147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1187 /* 2151 */ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1188 /* 2151 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1189 /* 2156 */ GIR_RootConstrainSelectedInstOperands,
1190 /* 2157 */ // GIR_Coverage, 537,
1191 /* 2157 */ GIR_Done,
1192 /* 2158 */ // Label 128: @2158
1193 /* 2158 */ GIM_Reject,
1194 /* 2159 */ // Label 126: @2159
1195 /* 2159 */ GIM_Reject,
1196 /* 2160 */ // Label 124: @2160
1197 /* 2160 */ GIM_Reject,
1198 /* 2161 */ // Label 92: @2161
1199 /* 2161 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(2313),
1200 /* 2166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1201 /* 2169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1202 /* 2172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1203 /* 2176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 130*/ GIMT_Encode4(2232), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2544 //
1204 /* 2183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1205 /* 2187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1206 /* 2191 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1207 /* 2195 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1208 /* 2199 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1209 /* 2204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1210 /* 2209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1211 /* 2213 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1212 /* 2215 */ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1213 /* 2215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1214 /* 2218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1215 /* 2220 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1216 /* 2222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1217 /* 2226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1218 /* 2230 */ GIR_RootConstrainSelectedInstOperands,
1219 /* 2231 */ // GIR_Coverage, 2544,
1220 /* 2231 */ GIR_EraseRootFromParent_Done,
1221 /* 2232 */ // Label 130: @2232
1222 /* 2232 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(2312),
1223 /* 2237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1224 /* 2241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 132*/ GIMT_Encode4(2293), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 871 //
1225 /* 2248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1226 /* 2252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1227 /* 2256 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1228 /* 2260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1229 /* 2264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1230 /* 2269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1231 /* 2274 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1232 /* 2276 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1233 /* 2276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
1234 /* 2279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1235 /* 2281 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1236 /* 2283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1237 /* 2287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1238 /* 2291 */ GIR_RootConstrainSelectedInstOperands,
1239 /* 2292 */ // GIR_Coverage, 871,
1240 /* 2292 */ GIR_EraseRootFromParent_Done,
1241 /* 2293 */ // Label 132: @2293
1242 /* 2293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(2311), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 538 //
1243 /* 2300 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1244 /* 2304 */ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1245 /* 2304 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
1246 /* 2309 */ GIR_RootConstrainSelectedInstOperands,
1247 /* 2310 */ // GIR_Coverage, 538,
1248 /* 2310 */ GIR_Done,
1249 /* 2311 */ // Label 133: @2311
1250 /* 2311 */ GIM_Reject,
1251 /* 2312 */ // Label 131: @2312
1252 /* 2312 */ GIM_Reject,
1253 /* 2313 */ // Label 129: @2313
1254 /* 2313 */ GIM_Reject,
1255 /* 2314 */ // Label 93: @2314
1256 /* 2314 */ GIM_Reject,
1257 /* 2315 */ // Label 1: @2315
1258 /* 2315 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 142*/ GIMT_Encode4(2988),
1259 /* 2326 */ /*GILLT_s32*//*Label 134*/ GIMT_Encode4(2358),
1260 /* 2330 */ /*GILLT_s64*//*Label 135*/ GIMT_Encode4(2529),
1261 /* 2334 */ /*GILLT_v4s8*//*Label 136*/ GIMT_Encode4(2562),
1262 /* 2338 */ /*GILLT_v16s8*//*Label 137*/ GIMT_Encode4(2593),
1263 /* 2342 */ /*GILLT_v2s16*//*Label 138*/ GIMT_Encode4(2684),
1264 /* 2346 */ /*GILLT_v8s16*//*Label 139*/ GIMT_Encode4(2715),
1265 /* 2350 */ /*GILLT_v4s32*//*Label 140*/ GIMT_Encode4(2806),
1266 /* 2354 */ /*GILLT_v2s64*//*Label 141*/ GIMT_Encode4(2897),
1267 /* 2358 */ // Label 134: @2358
1268 /* 2358 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2528),
1269 /* 2363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1270 /* 2366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1271 /* 2369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 144*/ GIMT_Encode4(2397), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1956 //
1272 /* 2376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1273 /* 2380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1274 /* 2384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1275 /* 2388 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1276 /* 2388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1277 /* 2391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1278 /* 2393 */ GIR_RootToRootCopy, /*OpIdx*/2, // r
1279 /* 2395 */ GIR_RootConstrainSelectedInstOperands,
1280 /* 2396 */ // GIR_Coverage, 1956,
1281 /* 2396 */ GIR_EraseRootFromParent_Done,
1282 /* 2397 */ // Label 144: @2397
1283 /* 2397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 145*/ GIMT_Encode4(2423), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1232 //
1284 /* 2404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1285 /* 2408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1286 /* 2412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1287 /* 2416 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1288 /* 2416 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1289 /* 2421 */ GIR_RootConstrainSelectedInstOperands,
1290 /* 2422 */ // GIR_Coverage, 1232,
1291 /* 2422 */ GIR_Done,
1292 /* 2423 */ // Label 145: @2423
1293 /* 2423 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 146*/ GIMT_Encode4(2449), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 47 //
1294 /* 2430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1295 /* 2434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1296 /* 2438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1297 /* 2442 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1298 /* 2442 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1299 /* 2447 */ GIR_RootConstrainSelectedInstOperands,
1300 /* 2448 */ // GIR_Coverage, 47,
1301 /* 2448 */ GIR_Done,
1302 /* 2449 */ // Label 146: @2449
1303 /* 2449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(2475), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1086 //
1304 /* 2456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1305 /* 2460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1306 /* 2464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1307 /* 2468 */ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1308 /* 2468 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1309 /* 2473 */ GIR_RootConstrainSelectedInstOperands,
1310 /* 2474 */ // GIR_Coverage, 1086,
1311 /* 2474 */ GIR_Done,
1312 /* 2475 */ // Label 147: @2475
1313 /* 2475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(2501), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1095 //
1314 /* 2482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1315 /* 2486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1316 /* 2490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1317 /* 2494 */ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1318 /* 2494 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1319 /* 2499 */ GIR_RootConstrainSelectedInstOperands,
1320 /* 2500 */ // GIR_Coverage, 1095,
1321 /* 2500 */ GIR_Done,
1322 /* 2501 */ // Label 148: @2501
1323 /* 2501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 149*/ GIMT_Encode4(2527), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1961 //
1324 /* 2508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1325 /* 2512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1326 /* 2516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1327 /* 2520 */ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1328 /* 2520 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1329 /* 2525 */ GIR_RootConstrainSelectedInstOperands,
1330 /* 2526 */ // GIR_Coverage, 1961,
1331 /* 2526 */ GIR_Done,
1332 /* 2527 */ // Label 149: @2527
1333 /* 2527 */ GIM_Reject,
1334 /* 2528 */ // Label 143: @2528
1335 /* 2528 */ GIM_Reject,
1336 /* 2529 */ // Label 135: @2529
1337 /* 2529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 150*/ GIMT_Encode4(2561), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 231 //
1338 /* 2536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1339 /* 2539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1340 /* 2542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1341 /* 2546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1342 /* 2550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1343 /* 2554 */ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1344 /* 2554 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1345 /* 2559 */ GIR_RootConstrainSelectedInstOperands,
1346 /* 2560 */ // GIR_Coverage, 231,
1347 /* 2560 */ GIR_Done,
1348 /* 2561 */ // Label 150: @2561
1349 /* 2561 */ GIM_Reject,
1350 /* 2562 */ // Label 136: @2562
1351 /* 2562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(2592), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2064 //
1352 /* 2569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1353 /* 2572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1354 /* 2575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1355 /* 2579 */ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1356 /* 2579 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1357 /* 2584 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1358 /* 2590 */ GIR_RootConstrainSelectedInstOperands,
1359 /* 2591 */ // GIR_Coverage, 2064,
1360 /* 2591 */ GIR_Done,
1361 /* 2592 */ // Label 151: @2592
1362 /* 2592 */ GIM_Reject,
1363 /* 2593 */ // Label 137: @2593
1364 /* 2593 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2683),
1365 /* 2598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1366 /* 2601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1367 /* 2604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1368 /* 2608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1369 /* 2612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 153*/ GIMT_Encode4(2664), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 924 //
1370 /* 2619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1371 /* 2623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1372 /* 2627 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1373 /* 2631 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1374 /* 2635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1375 /* 2640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1376 /* 2645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1377 /* 2647 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1378 /* 2647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1379 /* 2650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1380 /* 2652 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1381 /* 2654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1382 /* 2658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1383 /* 2662 */ GIR_RootConstrainSelectedInstOperands,
1384 /* 2663 */ // GIR_Coverage, 924,
1385 /* 2663 */ GIR_EraseRootFromParent_Done,
1386 /* 2664 */ // Label 153: @2664
1387 /* 2664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 154*/ GIMT_Encode4(2682), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1053 //
1388 /* 2671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1389 /* 2675 */ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1390 /* 2675 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1391 /* 2680 */ GIR_RootConstrainSelectedInstOperands,
1392 /* 2681 */ // GIR_Coverage, 1053,
1393 /* 2681 */ GIR_Done,
1394 /* 2682 */ // Label 154: @2682
1395 /* 2682 */ GIM_Reject,
1396 /* 2683 */ // Label 152: @2683
1397 /* 2683 */ GIM_Reject,
1398 /* 2684 */ // Label 138: @2684
1399 /* 2684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 155*/ GIMT_Encode4(2714), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2058 //
1400 /* 2691 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1401 /* 2694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1402 /* 2697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1403 /* 2701 */ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1404 /* 2701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1405 /* 2706 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1406 /* 2712 */ GIR_RootConstrainSelectedInstOperands,
1407 /* 2713 */ // GIR_Coverage, 2058,
1408 /* 2713 */ GIR_Done,
1409 /* 2714 */ // Label 155: @2714
1410 /* 2714 */ GIM_Reject,
1411 /* 2715 */ // Label 139: @2715
1412 /* 2715 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2805),
1413 /* 2720 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1414 /* 2723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1415 /* 2726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1416 /* 2730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1417 /* 2734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 157*/ GIMT_Encode4(2786), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 925 //
1418 /* 2741 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1419 /* 2745 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1420 /* 2749 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1421 /* 2753 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1422 /* 2757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1423 /* 2762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1424 /* 2767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1425 /* 2769 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1426 /* 2769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1427 /* 2772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1428 /* 2774 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1429 /* 2776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1430 /* 2780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1431 /* 2784 */ GIR_RootConstrainSelectedInstOperands,
1432 /* 2785 */ // GIR_Coverage, 925,
1433 /* 2785 */ GIR_EraseRootFromParent_Done,
1434 /* 2786 */ // Label 157: @2786
1435 /* 2786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 158*/ GIMT_Encode4(2804), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1054 //
1436 /* 2793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1437 /* 2797 */ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1438 /* 2797 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1439 /* 2802 */ GIR_RootConstrainSelectedInstOperands,
1440 /* 2803 */ // GIR_Coverage, 1054,
1441 /* 2803 */ GIR_Done,
1442 /* 2804 */ // Label 158: @2804
1443 /* 2804 */ GIM_Reject,
1444 /* 2805 */ // Label 156: @2805
1445 /* 2805 */ GIM_Reject,
1446 /* 2806 */ // Label 140: @2806
1447 /* 2806 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(2896),
1448 /* 2811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1449 /* 2814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1450 /* 2817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1451 /* 2821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1452 /* 2825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 160*/ GIMT_Encode4(2877), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 926 //
1453 /* 2832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1454 /* 2836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1455 /* 2840 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1456 /* 2844 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1457 /* 2848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1458 /* 2853 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1459 /* 2858 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1460 /* 2860 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1461 /* 2860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1462 /* 2863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1463 /* 2865 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1464 /* 2867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1465 /* 2871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1466 /* 2875 */ GIR_RootConstrainSelectedInstOperands,
1467 /* 2876 */ // GIR_Coverage, 926,
1468 /* 2876 */ GIR_EraseRootFromParent_Done,
1469 /* 2877 */ // Label 160: @2877
1470 /* 2877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 161*/ GIMT_Encode4(2895), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1055 //
1471 /* 2884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1472 /* 2888 */ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1473 /* 2888 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1474 /* 2893 */ GIR_RootConstrainSelectedInstOperands,
1475 /* 2894 */ // GIR_Coverage, 1055,
1476 /* 2894 */ GIR_Done,
1477 /* 2895 */ // Label 161: @2895
1478 /* 2895 */ GIM_Reject,
1479 /* 2896 */ // Label 159: @2896
1480 /* 2896 */ GIM_Reject,
1481 /* 2897 */ // Label 141: @2897
1482 /* 2897 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(2987),
1483 /* 2902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1484 /* 2905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1485 /* 2908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1486 /* 2912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1487 /* 2916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 163*/ GIMT_Encode4(2968), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 927 //
1488 /* 2923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1489 /* 2927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1490 /* 2931 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1491 /* 2935 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1492 /* 2939 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1493 /* 2944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1494 /* 2949 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1495 /* 2951 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1496 /* 2951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1497 /* 2954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1498 /* 2956 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1499 /* 2958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1500 /* 2962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1501 /* 2966 */ GIR_RootConstrainSelectedInstOperands,
1502 /* 2967 */ // GIR_Coverage, 927,
1503 /* 2967 */ GIR_EraseRootFromParent_Done,
1504 /* 2968 */ // Label 163: @2968
1505 /* 2968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 164*/ GIMT_Encode4(2986), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1056 //
1506 /* 2975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1507 /* 2979 */ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1508 /* 2979 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1509 /* 2984 */ GIR_RootConstrainSelectedInstOperands,
1510 /* 2985 */ // GIR_Coverage, 1056,
1511 /* 2985 */ GIR_Done,
1512 /* 2986 */ // Label 164: @2986
1513 /* 2986 */ GIM_Reject,
1514 /* 2987 */ // Label 162: @2987
1515 /* 2987 */ GIM_Reject,
1516 /* 2988 */ // Label 142: @2988
1517 /* 2988 */ GIM_Reject,
1518 /* 2989 */ // Label 2: @2989
1519 /* 2989 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 172*/ GIMT_Encode4(3427),
1520 /* 3000 */ /*GILLT_s32*//*Label 165*/ GIMT_Encode4(3032),
1521 /* 3004 */ /*GILLT_s64*//*Label 166*/ GIMT_Encode4(3181), GIMT_Encode4(0),
1522 /* 3012 */ /*GILLT_v16s8*//*Label 167*/ GIMT_Encode4(3264),
1523 /* 3016 */ /*GILLT_v2s16*//*Label 168*/ GIMT_Encode4(3297),
1524 /* 3020 */ /*GILLT_v8s16*//*Label 169*/ GIMT_Encode4(3328),
1525 /* 3024 */ /*GILLT_v4s32*//*Label 170*/ GIMT_Encode4(3361),
1526 /* 3028 */ /*GILLT_v2s64*//*Label 171*/ GIMT_Encode4(3394),
1527 /* 3032 */ // Label 165: @3032
1528 /* 3032 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3180),
1529 /* 3037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1530 /* 3040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1531 /* 3043 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3141),
1532 /* 3048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1533 /* 3052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1534 /* 3056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1535 /* 3060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 175*/ GIMT_Encode4(3086), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 48 //
1536 /* 3067 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1537 /* 3067 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1538 /* 3072 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1539 /* 3078 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1540 /* 3084 */ GIR_RootConstrainSelectedInstOperands,
1541 /* 3085 */ // GIR_Coverage, 48,
1542 /* 3085 */ GIR_Done,
1543 /* 3086 */ // Label 175: @3086
1544 /* 3086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 176*/ GIMT_Encode4(3100), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 360 //
1545 /* 3093 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1546 /* 3093 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1547 /* 3098 */ GIR_RootConstrainSelectedInstOperands,
1548 /* 3099 */ // GIR_Coverage, 360,
1549 /* 3099 */ GIR_Done,
1550 /* 3100 */ // Label 176: @3100
1551 /* 3100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 177*/ GIMT_Encode4(3126), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1096 //
1552 /* 3107 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1553 /* 3107 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1554 /* 3112 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1555 /* 3118 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1556 /* 3124 */ GIR_RootConstrainSelectedInstOperands,
1557 /* 3125 */ // GIR_Coverage, 1096,
1558 /* 3125 */ GIR_Done,
1559 /* 3126 */ // Label 177: @3126
1560 /* 3126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(3140), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1201 //
1561 /* 3133 */ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1562 /* 3133 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1563 /* 3138 */ GIR_RootConstrainSelectedInstOperands,
1564 /* 3139 */ // GIR_Coverage, 1201,
1565 /* 3139 */ GIR_Done,
1566 /* 3140 */ // Label 178: @3140
1567 /* 3140 */ GIM_Reject,
1568 /* 3141 */ // Label 174: @3141
1569 /* 3141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(3179), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1959 //
1570 /* 3148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1571 /* 3152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1572 /* 3156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1573 /* 3160 */ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1574 /* 3160 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1575 /* 3165 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1576 /* 3171 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1577 /* 3177 */ GIR_RootConstrainSelectedInstOperands,
1578 /* 3178 */ // GIR_Coverage, 1959,
1579 /* 3178 */ GIR_Done,
1580 /* 3179 */ // Label 179: @3179
1581 /* 3179 */ GIM_Reject,
1582 /* 3180 */ // Label 173: @3180
1583 /* 3180 */ GIM_Reject,
1584 /* 3181 */ // Label 166: @3181
1585 /* 3181 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(3263),
1586 /* 3186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1587 /* 3189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1588 /* 3192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1589 /* 3196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1590 /* 3200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1591 /* 3204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 181*/ GIMT_Encode4(3248), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 302 //
1592 /* 3211 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1593 /* 3211 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1594 /* 3216 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1595 /* 3222 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1596 /* 3228 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1597 /* 3234 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1598 /* 3240 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1599 /* 3246 */ GIR_RootConstrainSelectedInstOperands,
1600 /* 3247 */ // GIR_Coverage, 302,
1601 /* 3247 */ GIR_Done,
1602 /* 3248 */ // Label 181: @3248
1603 /* 3248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(3262), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 375 //
1604 /* 3255 */ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1605 /* 3255 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1606 /* 3260 */ GIR_RootConstrainSelectedInstOperands,
1607 /* 3261 */ // GIR_Coverage, 375,
1608 /* 3261 */ GIR_Done,
1609 /* 3262 */ // Label 182: @3262
1610 /* 3262 */ GIM_Reject,
1611 /* 3263 */ // Label 180: @3263
1612 /* 3263 */ GIM_Reject,
1613 /* 3264 */ // Label 167: @3264
1614 /* 3264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 183*/ GIMT_Encode4(3296), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 932 //
1615 /* 3271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1616 /* 3274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1617 /* 3277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1618 /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1619 /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1620 /* 3289 */ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1621 /* 3289 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1622 /* 3294 */ GIR_RootConstrainSelectedInstOperands,
1623 /* 3295 */ // GIR_Coverage, 932,
1624 /* 3295 */ GIR_Done,
1625 /* 3296 */ // Label 183: @3296
1626 /* 3296 */ GIM_Reject,
1627 /* 3297 */ // Label 168: @3297
1628 /* 3297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 184*/ GIMT_Encode4(3327), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2060 //
1629 /* 3304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1630 /* 3307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1631 /* 3310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1632 /* 3314 */ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1633 /* 3314 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1634 /* 3319 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
1635 /* 3325 */ GIR_RootConstrainSelectedInstOperands,
1636 /* 3326 */ // GIR_Coverage, 2060,
1637 /* 3326 */ GIR_Done,
1638 /* 3327 */ // Label 184: @3327
1639 /* 3327 */ GIM_Reject,
1640 /* 3328 */ // Label 169: @3328
1641 /* 3328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(3360), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 933 //
1642 /* 3335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1643 /* 3338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1644 /* 3341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1645 /* 3345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1646 /* 3349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1647 /* 3353 */ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1648 /* 3353 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1649 /* 3358 */ GIR_RootConstrainSelectedInstOperands,
1650 /* 3359 */ // GIR_Coverage, 933,
1651 /* 3359 */ GIR_Done,
1652 /* 3360 */ // Label 185: @3360
1653 /* 3360 */ GIM_Reject,
1654 /* 3361 */ // Label 170: @3361
1655 /* 3361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(3393), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 934 //
1656 /* 3368 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1657 /* 3371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1658 /* 3374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1659 /* 3378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1660 /* 3382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1661 /* 3386 */ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1662 /* 3386 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1663 /* 3391 */ GIR_RootConstrainSelectedInstOperands,
1664 /* 3392 */ // GIR_Coverage, 934,
1665 /* 3392 */ GIR_Done,
1666 /* 3393 */ // Label 186: @3393
1667 /* 3393 */ GIM_Reject,
1668 /* 3394 */ // Label 171: @3394
1669 /* 3394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(3426), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 935 //
1670 /* 3401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1671 /* 3404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1672 /* 3407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1673 /* 3411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1674 /* 3415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1675 /* 3419 */ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1676 /* 3419 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1677 /* 3424 */ GIR_RootConstrainSelectedInstOperands,
1678 /* 3425 */ // GIR_Coverage, 935,
1679 /* 3425 */ GIR_Done,
1680 /* 3426 */ // Label 187: @3426
1681 /* 3426 */ GIM_Reject,
1682 /* 3427 */ // Label 172: @3427
1683 /* 3427 */ GIM_Reject,
1684 /* 3428 */ // Label 3: @3428
1685 /* 3428 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 194*/ GIMT_Encode4(3689),
1686 /* 3439 */ /*GILLT_s32*//*Label 188*/ GIMT_Encode4(3471),
1687 /* 3443 */ /*GILLT_s64*//*Label 189*/ GIMT_Encode4(3524), GIMT_Encode4(0),
1688 /* 3451 */ /*GILLT_v16s8*//*Label 190*/ GIMT_Encode4(3557), GIMT_Encode4(0),
1689 /* 3459 */ /*GILLT_v8s16*//*Label 191*/ GIMT_Encode4(3590),
1690 /* 3463 */ /*GILLT_v4s32*//*Label 192*/ GIMT_Encode4(3623),
1691 /* 3467 */ /*GILLT_v2s64*//*Label 193*/ GIMT_Encode4(3656),
1692 /* 3471 */ // Label 188: @3471
1693 /* 3471 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(3523),
1694 /* 3476 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1695 /* 3479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1696 /* 3482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1697 /* 3486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1698 /* 3490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1699 /* 3494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 196*/ GIMT_Encode4(3508), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 354 //
1700 /* 3501 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1701 /* 3501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1702 /* 3506 */ GIR_RootConstrainSelectedInstOperands,
1703 /* 3507 */ // GIR_Coverage, 354,
1704 /* 3507 */ GIR_Done,
1705 /* 3508 */ // Label 196: @3508
1706 /* 3508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(3522), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1194 //
1707 /* 3515 */ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1708 /* 3515 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1709 /* 3520 */ GIR_RootConstrainSelectedInstOperands,
1710 /* 3521 */ // GIR_Coverage, 1194,
1711 /* 3521 */ GIR_Done,
1712 /* 3522 */ // Label 197: @3522
1713 /* 3522 */ GIM_Reject,
1714 /* 3523 */ // Label 195: @3523
1715 /* 3523 */ GIM_Reject,
1716 /* 3524 */ // Label 189: @3524
1717 /* 3524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 198*/ GIMT_Encode4(3556), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 369 //
1718 /* 3531 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1719 /* 3534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1720 /* 3537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1721 /* 3541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1722 /* 3545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1723 /* 3549 */ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1724 /* 3549 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1725 /* 3554 */ GIR_RootConstrainSelectedInstOperands,
1726 /* 3555 */ // GIR_Coverage, 369,
1727 /* 3555 */ GIR_Done,
1728 /* 3556 */ // Label 198: @3556
1729 /* 3556 */ GIM_Reject,
1730 /* 3557 */ // Label 190: @3557
1731 /* 3557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 199*/ GIMT_Encode4(3589), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 672 //
1732 /* 3564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1733 /* 3567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1734 /* 3570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1735 /* 3574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1736 /* 3578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1737 /* 3582 */ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1738 /* 3582 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1739 /* 3587 */ GIR_RootConstrainSelectedInstOperands,
1740 /* 3588 */ // GIR_Coverage, 672,
1741 /* 3588 */ GIR_Done,
1742 /* 3589 */ // Label 199: @3589
1743 /* 3589 */ GIM_Reject,
1744 /* 3590 */ // Label 191: @3590
1745 /* 3590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 200*/ GIMT_Encode4(3622), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 673 //
1746 /* 3597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1747 /* 3600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1748 /* 3603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1749 /* 3607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1750 /* 3611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1751 /* 3615 */ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1752 /* 3615 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1753 /* 3620 */ GIR_RootConstrainSelectedInstOperands,
1754 /* 3621 */ // GIR_Coverage, 673,
1755 /* 3621 */ GIR_Done,
1756 /* 3622 */ // Label 200: @3622
1757 /* 3622 */ GIM_Reject,
1758 /* 3623 */ // Label 192: @3623
1759 /* 3623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(3655), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 674 //
1760 /* 3630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1761 /* 3633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1762 /* 3636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1763 /* 3640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1764 /* 3644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1765 /* 3648 */ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1766 /* 3648 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1767 /* 3653 */ GIR_RootConstrainSelectedInstOperands,
1768 /* 3654 */ // GIR_Coverage, 674,
1769 /* 3654 */ GIR_Done,
1770 /* 3655 */ // Label 201: @3655
1771 /* 3655 */ GIM_Reject,
1772 /* 3656 */ // Label 193: @3656
1773 /* 3656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(3688), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 675 //
1774 /* 3663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1775 /* 3666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1776 /* 3669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1777 /* 3673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1778 /* 3677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1779 /* 3681 */ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1780 /* 3681 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1781 /* 3686 */ GIR_RootConstrainSelectedInstOperands,
1782 /* 3687 */ // GIR_Coverage, 675,
1783 /* 3687 */ GIR_Done,
1784 /* 3688 */ // Label 202: @3688
1785 /* 3688 */ GIM_Reject,
1786 /* 3689 */ // Label 194: @3689
1787 /* 3689 */ GIM_Reject,
1788 /* 3690 */ // Label 4: @3690
1789 /* 3690 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 209*/ GIMT_Encode4(3951),
1790 /* 3701 */ /*GILLT_s32*//*Label 203*/ GIMT_Encode4(3733),
1791 /* 3705 */ /*GILLT_s64*//*Label 204*/ GIMT_Encode4(3786), GIMT_Encode4(0),
1792 /* 3713 */ /*GILLT_v16s8*//*Label 205*/ GIMT_Encode4(3819), GIMT_Encode4(0),
1793 /* 3721 */ /*GILLT_v8s16*//*Label 206*/ GIMT_Encode4(3852),
1794 /* 3725 */ /*GILLT_v4s32*//*Label 207*/ GIMT_Encode4(3885),
1795 /* 3729 */ /*GILLT_v2s64*//*Label 208*/ GIMT_Encode4(3918),
1796 /* 3733 */ // Label 203: @3733
1797 /* 3733 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(3785),
1798 /* 3738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1799 /* 3741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1800 /* 3744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1801 /* 3748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1802 /* 3752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1803 /* 3756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 211*/ GIMT_Encode4(3770), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 355 //
1804 /* 3763 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1805 /* 3763 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1806 /* 3768 */ GIR_RootConstrainSelectedInstOperands,
1807 /* 3769 */ // GIR_Coverage, 355,
1808 /* 3769 */ GIR_Done,
1809 /* 3770 */ // Label 211: @3770
1810 /* 3770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(3784), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1195 //
1811 /* 3777 */ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1812 /* 3777 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1813 /* 3782 */ GIR_RootConstrainSelectedInstOperands,
1814 /* 3783 */ // GIR_Coverage, 1195,
1815 /* 3783 */ GIR_Done,
1816 /* 3784 */ // Label 212: @3784
1817 /* 3784 */ GIM_Reject,
1818 /* 3785 */ // Label 210: @3785
1819 /* 3785 */ GIM_Reject,
1820 /* 3786 */ // Label 204: @3786
1821 /* 3786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(3818), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 370 //
1822 /* 3793 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1823 /* 3796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1824 /* 3799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1825 /* 3803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1826 /* 3807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1827 /* 3811 */ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1828 /* 3811 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1829 /* 3816 */ GIR_RootConstrainSelectedInstOperands,
1830 /* 3817 */ // GIR_Coverage, 370,
1831 /* 3817 */ GIR_Done,
1832 /* 3818 */ // Label 213: @3818
1833 /* 3818 */ GIM_Reject,
1834 /* 3819 */ // Label 205: @3819
1835 /* 3819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 214*/ GIMT_Encode4(3851), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 676 //
1836 /* 3826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1837 /* 3829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1838 /* 3832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1839 /* 3836 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1840 /* 3840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1841 /* 3844 */ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1842 /* 3844 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1843 /* 3849 */ GIR_RootConstrainSelectedInstOperands,
1844 /* 3850 */ // GIR_Coverage, 676,
1845 /* 3850 */ GIR_Done,
1846 /* 3851 */ // Label 214: @3851
1847 /* 3851 */ GIM_Reject,
1848 /* 3852 */ // Label 206: @3852
1849 /* 3852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 215*/ GIMT_Encode4(3884), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 677 //
1850 /* 3859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1851 /* 3862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1852 /* 3865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1853 /* 3869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1854 /* 3873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1855 /* 3877 */ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1856 /* 3877 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1857 /* 3882 */ GIR_RootConstrainSelectedInstOperands,
1858 /* 3883 */ // GIR_Coverage, 677,
1859 /* 3883 */ GIR_Done,
1860 /* 3884 */ // Label 215: @3884
1861 /* 3884 */ GIM_Reject,
1862 /* 3885 */ // Label 207: @3885
1863 /* 3885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(3917), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 678 //
1864 /* 3892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1865 /* 3895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1866 /* 3898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1867 /* 3902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1868 /* 3906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1869 /* 3910 */ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1870 /* 3910 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1871 /* 3915 */ GIR_RootConstrainSelectedInstOperands,
1872 /* 3916 */ // GIR_Coverage, 678,
1873 /* 3916 */ GIR_Done,
1874 /* 3917 */ // Label 216: @3917
1875 /* 3917 */ GIM_Reject,
1876 /* 3918 */ // Label 208: @3918
1877 /* 3918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(3950), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 679 //
1878 /* 3925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1879 /* 3928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1880 /* 3931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1881 /* 3935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1882 /* 3939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1883 /* 3943 */ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1884 /* 3943 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1885 /* 3948 */ GIR_RootConstrainSelectedInstOperands,
1886 /* 3949 */ // GIR_Coverage, 679,
1887 /* 3949 */ GIR_Done,
1888 /* 3950 */ // Label 217: @3950
1889 /* 3950 */ GIM_Reject,
1890 /* 3951 */ // Label 209: @3951
1891 /* 3951 */ GIM_Reject,
1892 /* 3952 */ // Label 5: @3952
1893 /* 3952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 224*/ GIMT_Encode4(4213),
1894 /* 3963 */ /*GILLT_s32*//*Label 218*/ GIMT_Encode4(3995),
1895 /* 3967 */ /*GILLT_s64*//*Label 219*/ GIMT_Encode4(4048), GIMT_Encode4(0),
1896 /* 3975 */ /*GILLT_v16s8*//*Label 220*/ GIMT_Encode4(4081), GIMT_Encode4(0),
1897 /* 3983 */ /*GILLT_v8s16*//*Label 221*/ GIMT_Encode4(4114),
1898 /* 3987 */ /*GILLT_v4s32*//*Label 222*/ GIMT_Encode4(4147),
1899 /* 3991 */ /*GILLT_v2s64*//*Label 223*/ GIMT_Encode4(4180),
1900 /* 3995 */ // Label 218: @3995
1901 /* 3995 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(4047),
1902 /* 4000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1903 /* 4003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1904 /* 4006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1905 /* 4010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1906 /* 4014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1907 /* 4018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 226*/ GIMT_Encode4(4032), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 356 //
1908 /* 4025 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1909 /* 4025 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1910 /* 4030 */ GIR_RootConstrainSelectedInstOperands,
1911 /* 4031 */ // GIR_Coverage, 356,
1912 /* 4031 */ GIR_Done,
1913 /* 4032 */ // Label 226: @4032
1914 /* 4032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(4046), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1199 //
1915 /* 4039 */ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1916 /* 4039 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1917 /* 4044 */ GIR_RootConstrainSelectedInstOperands,
1918 /* 4045 */ // GIR_Coverage, 1199,
1919 /* 4045 */ GIR_Done,
1920 /* 4046 */ // Label 227: @4046
1921 /* 4046 */ GIM_Reject,
1922 /* 4047 */ // Label 225: @4047
1923 /* 4047 */ GIM_Reject,
1924 /* 4048 */ // Label 219: @4048
1925 /* 4048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(4080), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 371 //
1926 /* 4055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1927 /* 4058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1928 /* 4061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1929 /* 4065 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1930 /* 4069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1931 /* 4073 */ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1932 /* 4073 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1933 /* 4078 */ GIR_RootConstrainSelectedInstOperands,
1934 /* 4079 */ // GIR_Coverage, 371,
1935 /* 4079 */ GIR_Done,
1936 /* 4080 */ // Label 228: @4080
1937 /* 4080 */ GIM_Reject,
1938 /* 4081 */ // Label 220: @4081
1939 /* 4081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(4113), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 912 //
1940 /* 4088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1941 /* 4091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1942 /* 4094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1943 /* 4098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1944 /* 4102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1945 /* 4106 */ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1946 /* 4106 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
1947 /* 4111 */ GIR_RootConstrainSelectedInstOperands,
1948 /* 4112 */ // GIR_Coverage, 912,
1949 /* 4112 */ GIR_Done,
1950 /* 4113 */ // Label 229: @4113
1951 /* 4113 */ GIM_Reject,
1952 /* 4114 */ // Label 221: @4114
1953 /* 4114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 230*/ GIMT_Encode4(4146), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 913 //
1954 /* 4121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1955 /* 4124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1956 /* 4127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1957 /* 4131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1958 /* 4135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1959 /* 4139 */ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1960 /* 4139 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
1961 /* 4144 */ GIR_RootConstrainSelectedInstOperands,
1962 /* 4145 */ // GIR_Coverage, 913,
1963 /* 4145 */ GIR_Done,
1964 /* 4146 */ // Label 230: @4146
1965 /* 4146 */ GIM_Reject,
1966 /* 4147 */ // Label 222: @4147
1967 /* 4147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 231*/ GIMT_Encode4(4179), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 914 //
1968 /* 4154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1969 /* 4157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1970 /* 4160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1971 /* 4164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1972 /* 4168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1973 /* 4172 */ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1974 /* 4172 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
1975 /* 4177 */ GIR_RootConstrainSelectedInstOperands,
1976 /* 4178 */ // GIR_Coverage, 914,
1977 /* 4178 */ GIR_Done,
1978 /* 4179 */ // Label 231: @4179
1979 /* 4179 */ GIM_Reject,
1980 /* 4180 */ // Label 223: @4180
1981 /* 4180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 232*/ GIMT_Encode4(4212), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 915 //
1982 /* 4187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1983 /* 4190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1984 /* 4193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1985 /* 4197 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1986 /* 4201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1987 /* 4205 */ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1988 /* 4205 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
1989 /* 4210 */ GIR_RootConstrainSelectedInstOperands,
1990 /* 4211 */ // GIR_Coverage, 915,
1991 /* 4211 */ GIR_Done,
1992 /* 4212 */ // Label 232: @4212
1993 /* 4212 */ GIM_Reject,
1994 /* 4213 */ // Label 224: @4213
1995 /* 4213 */ GIM_Reject,
1996 /* 4214 */ // Label 6: @4214
1997 /* 4214 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 239*/ GIMT_Encode4(4475),
1998 /* 4225 */ /*GILLT_s32*//*Label 233*/ GIMT_Encode4(4257),
1999 /* 4229 */ /*GILLT_s64*//*Label 234*/ GIMT_Encode4(4310), GIMT_Encode4(0),
2000 /* 4237 */ /*GILLT_v16s8*//*Label 235*/ GIMT_Encode4(4343), GIMT_Encode4(0),
2001 /* 4245 */ /*GILLT_v8s16*//*Label 236*/ GIMT_Encode4(4376),
2002 /* 4249 */ /*GILLT_v4s32*//*Label 237*/ GIMT_Encode4(4409),
2003 /* 4253 */ /*GILLT_v2s64*//*Label 238*/ GIMT_Encode4(4442),
2004 /* 4257 */ // Label 233: @4257
2005 /* 4257 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(4309),
2006 /* 4262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2007 /* 4265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2008 /* 4268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2009 /* 4272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2010 /* 4276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2011 /* 4280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 241*/ GIMT_Encode4(4294), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 357 //
2012 /* 4287 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2013 /* 4287 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2014 /* 4292 */ GIR_RootConstrainSelectedInstOperands,
2015 /* 4293 */ // GIR_Coverage, 357,
2016 /* 4293 */ GIR_Done,
2017 /* 4294 */ // Label 241: @4294
2018 /* 4294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(4308), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1200 //
2019 /* 4301 */ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2020 /* 4301 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2021 /* 4306 */ GIR_RootConstrainSelectedInstOperands,
2022 /* 4307 */ // GIR_Coverage, 1200,
2023 /* 4307 */ GIR_Done,
2024 /* 4308 */ // Label 242: @4308
2025 /* 4308 */ GIM_Reject,
2026 /* 4309 */ // Label 240: @4309
2027 /* 4309 */ GIM_Reject,
2028 /* 4310 */ // Label 234: @4310
2029 /* 4310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 243*/ GIMT_Encode4(4342), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 372 //
2030 /* 4317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2031 /* 4320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2032 /* 4323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2033 /* 4327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2034 /* 4331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2035 /* 4335 */ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2036 /* 4335 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2037 /* 4340 */ GIR_RootConstrainSelectedInstOperands,
2038 /* 4341 */ // GIR_Coverage, 372,
2039 /* 4341 */ GIR_Done,
2040 /* 4342 */ // Label 243: @4342
2041 /* 4342 */ GIM_Reject,
2042 /* 4343 */ // Label 235: @4343
2043 /* 4343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 244*/ GIMT_Encode4(4375), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 916 //
2044 /* 4350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2045 /* 4353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2046 /* 4356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2047 /* 4360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2048 /* 4364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2049 /* 4368 */ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2050 /* 4368 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2051 /* 4373 */ GIR_RootConstrainSelectedInstOperands,
2052 /* 4374 */ // GIR_Coverage, 916,
2053 /* 4374 */ GIR_Done,
2054 /* 4375 */ // Label 244: @4375
2055 /* 4375 */ GIM_Reject,
2056 /* 4376 */ // Label 236: @4376
2057 /* 4376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(4408), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 917 //
2058 /* 4383 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2059 /* 4386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2060 /* 4389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2061 /* 4393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2062 /* 4397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2063 /* 4401 */ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2064 /* 4401 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2065 /* 4406 */ GIR_RootConstrainSelectedInstOperands,
2066 /* 4407 */ // GIR_Coverage, 917,
2067 /* 4407 */ GIR_Done,
2068 /* 4408 */ // Label 245: @4408
2069 /* 4408 */ GIM_Reject,
2070 /* 4409 */ // Label 237: @4409
2071 /* 4409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(4441), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 918 //
2072 /* 4416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2073 /* 4419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2074 /* 4422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2075 /* 4426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2076 /* 4430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2077 /* 4434 */ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2078 /* 4434 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2079 /* 4439 */ GIR_RootConstrainSelectedInstOperands,
2080 /* 4440 */ // GIR_Coverage, 918,
2081 /* 4440 */ GIR_Done,
2082 /* 4441 */ // Label 246: @4441
2083 /* 4441 */ GIM_Reject,
2084 /* 4442 */ // Label 238: @4442
2085 /* 4442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(4474), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 919 //
2086 /* 4449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2087 /* 4452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2088 /* 4455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2089 /* 4459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2090 /* 4463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2091 /* 4467 */ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2092 /* 4467 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2093 /* 4472 */ GIR_RootConstrainSelectedInstOperands,
2094 /* 4473 */ // GIR_Coverage, 919,
2095 /* 4473 */ GIR_Done,
2096 /* 4474 */ // Label 247: @4474
2097 /* 4474 */ GIM_Reject,
2098 /* 4475 */ // Label 239: @4475
2099 /* 4475 */ GIM_Reject,
2100 /* 4476 */ // Label 7: @4476
2101 /* 4476 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 254*/ GIMT_Encode4(5009),
2102 /* 4487 */ /*GILLT_s32*//*Label 248*/ GIMT_Encode4(4519),
2103 /* 4491 */ /*GILLT_s64*//*Label 249*/ GIMT_Encode4(4777), GIMT_Encode4(0),
2104 /* 4499 */ /*GILLT_v16s8*//*Label 250*/ GIMT_Encode4(4877), GIMT_Encode4(0),
2105 /* 4507 */ /*GILLT_v8s16*//*Label 251*/ GIMT_Encode4(4910),
2106 /* 4511 */ /*GILLT_v4s32*//*Label 252*/ GIMT_Encode4(4943),
2107 /* 4515 */ /*GILLT_v2s64*//*Label 253*/ GIMT_Encode4(4976),
2108 /* 4519 */ // Label 248: @4519
2109 /* 4519 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4776),
2110 /* 4524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2111 /* 4527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2112 /* 4530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 256*/ GIMT_Encode4(4571), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 41 //
2113 /* 4537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2114 /* 4541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2115 /* 4545 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2116 /* 4549 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2117 /* 4553 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2118 /* 4557 */ // MIs[1] Operand 1
2119 /* 4557 */ // No operand predicates
2120 /* 4557 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2121 /* 4559 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2122 /* 4559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2123 /* 4562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2124 /* 4564 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2125 /* 4566 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2126 /* 4569 */ GIR_RootConstrainSelectedInstOperands,
2127 /* 4570 */ // GIR_Coverage, 41,
2128 /* 4570 */ GIR_EraseRootFromParent_Done,
2129 /* 4571 */ // Label 256: @4571
2130 /* 4571 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4651),
2131 /* 4576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2132 /* 4580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2133 /* 4584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 258*/ GIMT_Encode4(4617), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2300 //
2134 /* 4591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2135 /* 4595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2136 /* 4599 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2137 /* 4603 */ // MIs[1] Operand 1
2138 /* 4603 */ // No operand predicates
2139 /* 4603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2140 /* 4605 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2141 /* 4605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2142 /* 4608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2143 /* 4610 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2144 /* 4612 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2145 /* 4615 */ GIR_RootConstrainSelectedInstOperands,
2146 /* 4616 */ // GIR_Coverage, 2300,
2147 /* 4616 */ GIR_EraseRootFromParent_Done,
2148 /* 4617 */ // Label 258: @4617
2149 /* 4617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 259*/ GIMT_Encode4(4650), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2464 //
2150 /* 4624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2151 /* 4628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2152 /* 4632 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2153 /* 4636 */ // MIs[1] Operand 1
2154 /* 4636 */ // No operand predicates
2155 /* 4636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2156 /* 4638 */ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2157 /* 4638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2158 /* 4641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2159 /* 4643 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
2160 /* 4645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2161 /* 4648 */ GIR_RootConstrainSelectedInstOperands,
2162 /* 4649 */ // GIR_Coverage, 2464,
2163 /* 4649 */ GIR_EraseRootFromParent_Done,
2164 /* 4650 */ // Label 259: @4650
2165 /* 4650 */ GIM_Reject,
2166 /* 4651 */ // Label 257: @4651
2167 /* 4651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 260*/ GIMT_Encode4(4677), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 51 //
2168 /* 4658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2169 /* 4662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2170 /* 4666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2171 /* 4670 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2172 /* 4670 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2173 /* 4675 */ GIR_RootConstrainSelectedInstOperands,
2174 /* 4676 */ // GIR_Coverage, 51,
2175 /* 4676 */ GIR_Done,
2176 /* 4677 */ // Label 260: @4677
2177 /* 4677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 261*/ GIMT_Encode4(4703), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1083 //
2178 /* 4684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2179 /* 4688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2180 /* 4692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2181 /* 4696 */ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2182 /* 4696 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2183 /* 4701 */ GIR_RootConstrainSelectedInstOperands,
2184 /* 4702 */ // GIR_Coverage, 1083,
2185 /* 4702 */ GIR_Done,
2186 /* 4703 */ // Label 261: @4703
2187 /* 4703 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(4749),
2188 /* 4708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2189 /* 4712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2190 /* 4716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2191 /* 4720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 263*/ GIMT_Encode4(4734), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1099 //
2192 /* 4727 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2193 /* 4727 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2194 /* 4732 */ GIR_RootConstrainSelectedInstOperands,
2195 /* 4733 */ // GIR_Coverage, 1099,
2196 /* 4733 */ GIR_Done,
2197 /* 4734 */ // Label 263: @4734
2198 /* 4734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 264*/ GIMT_Encode4(4748), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1192 //
2199 /* 4741 */ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2200 /* 4741 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2201 /* 4746 */ GIR_RootConstrainSelectedInstOperands,
2202 /* 4747 */ // GIR_Coverage, 1192,
2203 /* 4747 */ GIR_Done,
2204 /* 4748 */ // Label 264: @4748
2205 /* 4748 */ GIM_Reject,
2206 /* 4749 */ // Label 262: @4749
2207 /* 4749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 265*/ GIMT_Encode4(4775), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1958 //
2208 /* 4756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2209 /* 4760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2210 /* 4764 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2211 /* 4768 */ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2212 /* 4768 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2213 /* 4773 */ GIR_RootConstrainSelectedInstOperands,
2214 /* 4774 */ // GIR_Coverage, 1958,
2215 /* 4774 */ GIR_Done,
2216 /* 4775 */ // Label 265: @4775
2217 /* 4775 */ GIM_Reject,
2218 /* 4776 */ // Label 255: @4776
2219 /* 4776 */ GIM_Reject,
2220 /* 4777 */ // Label 249: @4777
2221 /* 4777 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(4876),
2222 /* 4782 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2223 /* 4785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2224 /* 4788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2225 /* 4792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 267*/ GIMT_Encode4(4853), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 297 //
2226 /* 4799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2227 /* 4803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2228 /* 4807 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2229 /* 4811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2230 /* 4815 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2231 /* 4820 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2232 /* 4825 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2233 /* 4836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2234 /* 4838 */ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2235 /* 4838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2236 /* 4841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2237 /* 4843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2238 /* 4847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2239 /* 4851 */ GIR_RootConstrainSelectedInstOperands,
2240 /* 4852 */ // GIR_Coverage, 297,
2241 /* 4852 */ GIR_EraseRootFromParent_Done,
2242 /* 4853 */ // Label 267: @4853
2243 /* 4853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(4875), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 234 //
2244 /* 4860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2245 /* 4864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2246 /* 4868 */ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2247 /* 4868 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2248 /* 4873 */ GIR_RootConstrainSelectedInstOperands,
2249 /* 4874 */ // GIR_Coverage, 234,
2250 /* 4874 */ GIR_Done,
2251 /* 4875 */ // Label 268: @4875
2252 /* 4875 */ GIM_Reject,
2253 /* 4876 */ // Label 266: @4876
2254 /* 4876 */ GIM_Reject,
2255 /* 4877 */ // Label 250: @4877
2256 /* 4877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 269*/ GIMT_Encode4(4909), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 543 //
2257 /* 4884 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2258 /* 4887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2259 /* 4890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2260 /* 4894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2261 /* 4898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2262 /* 4902 */ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2263 /* 4902 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2264 /* 4907 */ GIR_RootConstrainSelectedInstOperands,
2265 /* 4908 */ // GIR_Coverage, 543,
2266 /* 4908 */ GIR_Done,
2267 /* 4909 */ // Label 269: @4909
2268 /* 4909 */ GIM_Reject,
2269 /* 4910 */ // Label 251: @4910
2270 /* 4910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 270*/ GIMT_Encode4(4942), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 544 //
2271 /* 4917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2272 /* 4920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2273 /* 4923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2274 /* 4927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2275 /* 4931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2276 /* 4935 */ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2277 /* 4935 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2278 /* 4940 */ GIR_RootConstrainSelectedInstOperands,
2279 /* 4941 */ // GIR_Coverage, 544,
2280 /* 4941 */ GIR_Done,
2281 /* 4942 */ // Label 270: @4942
2282 /* 4942 */ GIM_Reject,
2283 /* 4943 */ // Label 252: @4943
2284 /* 4943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 271*/ GIMT_Encode4(4975), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 545 //
2285 /* 4950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2286 /* 4953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2287 /* 4956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2288 /* 4960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2289 /* 4964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2290 /* 4968 */ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2291 /* 4968 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2292 /* 4973 */ GIR_RootConstrainSelectedInstOperands,
2293 /* 4974 */ // GIR_Coverage, 545,
2294 /* 4974 */ GIR_Done,
2295 /* 4975 */ // Label 271: @4975
2296 /* 4975 */ GIM_Reject,
2297 /* 4976 */ // Label 253: @4976
2298 /* 4976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(5008), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 546 //
2299 /* 4983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2300 /* 4986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2301 /* 4989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2302 /* 4993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2303 /* 4997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2304 /* 5001 */ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2305 /* 5001 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2306 /* 5006 */ GIR_RootConstrainSelectedInstOperands,
2307 /* 5007 */ // GIR_Coverage, 546,
2308 /* 5007 */ GIR_Done,
2309 /* 5008 */ // Label 272: @5008
2310 /* 5008 */ GIM_Reject,
2311 /* 5009 */ // Label 254: @5009
2312 /* 5009 */ GIM_Reject,
2313 /* 5010 */ // Label 8: @5010
2314 /* 5010 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 279*/ GIMT_Encode4(5394),
2315 /* 5021 */ /*GILLT_s32*//*Label 273*/ GIMT_Encode4(5053),
2316 /* 5025 */ /*GILLT_s64*//*Label 274*/ GIMT_Encode4(5229), GIMT_Encode4(0),
2317 /* 5033 */ /*GILLT_v16s8*//*Label 275*/ GIMT_Encode4(5262), GIMT_Encode4(0),
2318 /* 5041 */ /*GILLT_v8s16*//*Label 276*/ GIMT_Encode4(5295),
2319 /* 5045 */ /*GILLT_v4s32*//*Label 277*/ GIMT_Encode4(5328),
2320 /* 5049 */ /*GILLT_v2s64*//*Label 278*/ GIMT_Encode4(5361),
2321 /* 5053 */ // Label 273: @5053
2322 /* 5053 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5228),
2323 /* 5058 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2324 /* 5061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2325 /* 5064 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5129),
2326 /* 5069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2327 /* 5073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2328 /* 5077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 282*/ GIMT_Encode4(5110), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 42 //
2329 /* 5084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2330 /* 5088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2331 /* 5092 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2332 /* 5096 */ // MIs[1] Operand 1
2333 /* 5096 */ // No operand predicates
2334 /* 5096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2335 /* 5098 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2336 /* 5098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2337 /* 5101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2338 /* 5103 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2339 /* 5105 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2340 /* 5108 */ GIR_RootConstrainSelectedInstOperands,
2341 /* 5109 */ // GIR_Coverage, 42,
2342 /* 5109 */ GIR_EraseRootFromParent_Done,
2343 /* 5110 */ // Label 282: @5110
2344 /* 5110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 283*/ GIMT_Encode4(5128), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 52 //
2345 /* 5117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2346 /* 5121 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2347 /* 5121 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2348 /* 5126 */ GIR_RootConstrainSelectedInstOperands,
2349 /* 5127 */ // GIR_Coverage, 52,
2350 /* 5127 */ GIR_Done,
2351 /* 5128 */ // Label 283: @5128
2352 /* 5128 */ GIM_Reject,
2353 /* 5129 */ // Label 281: @5129
2354 /* 5129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(5155), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1085 //
2355 /* 5136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2356 /* 5140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2357 /* 5144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2358 /* 5148 */ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2359 /* 5148 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2360 /* 5153 */ GIR_RootConstrainSelectedInstOperands,
2361 /* 5154 */ // GIR_Coverage, 1085,
2362 /* 5154 */ GIR_Done,
2363 /* 5155 */ // Label 284: @5155
2364 /* 5155 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(5201),
2365 /* 5160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2366 /* 5164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2367 /* 5168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2368 /* 5172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 286*/ GIMT_Encode4(5186), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1100 //
2369 /* 5179 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2370 /* 5179 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2371 /* 5184 */ GIR_RootConstrainSelectedInstOperands,
2372 /* 5185 */ // GIR_Coverage, 1100,
2373 /* 5185 */ GIR_Done,
2374 /* 5186 */ // Label 286: @5186
2375 /* 5186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(5200), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1205 //
2376 /* 5193 */ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2377 /* 5193 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2378 /* 5198 */ GIR_RootConstrainSelectedInstOperands,
2379 /* 5199 */ // GIR_Coverage, 1205,
2380 /* 5199 */ GIR_Done,
2381 /* 5200 */ // Label 287: @5200
2382 /* 5200 */ GIM_Reject,
2383 /* 5201 */ // Label 285: @5201
2384 /* 5201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(5227), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1960 //
2385 /* 5208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2386 /* 5212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2387 /* 5216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2388 /* 5220 */ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2389 /* 5220 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2390 /* 5225 */ GIR_RootConstrainSelectedInstOperands,
2391 /* 5226 */ // GIR_Coverage, 1960,
2392 /* 5226 */ GIR_Done,
2393 /* 5227 */ // Label 288: @5227
2394 /* 5227 */ GIM_Reject,
2395 /* 5228 */ // Label 280: @5228
2396 /* 5228 */ GIM_Reject,
2397 /* 5229 */ // Label 274: @5229
2398 /* 5229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 289*/ GIMT_Encode4(5261), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 235 //
2399 /* 5236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2400 /* 5239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2401 /* 5242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2402 /* 5246 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2403 /* 5250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2404 /* 5254 */ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2405 /* 5254 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2406 /* 5259 */ GIR_RootConstrainSelectedInstOperands,
2407 /* 5260 */ // GIR_Coverage, 235,
2408 /* 5260 */ GIR_Done,
2409 /* 5261 */ // Label 289: @5261
2410 /* 5261 */ GIM_Reject,
2411 /* 5262 */ // Label 275: @5262
2412 /* 5262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 290*/ GIMT_Encode4(5294), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 949 //
2413 /* 5269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2414 /* 5272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2415 /* 5275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2416 /* 5279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2417 /* 5283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2418 /* 5287 */ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2419 /* 5287 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2420 /* 5292 */ GIR_RootConstrainSelectedInstOperands,
2421 /* 5293 */ // GIR_Coverage, 949,
2422 /* 5293 */ GIR_Done,
2423 /* 5294 */ // Label 290: @5294
2424 /* 5294 */ GIM_Reject,
2425 /* 5295 */ // Label 276: @5295
2426 /* 5295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(5327), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 950 //
2427 /* 5302 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2428 /* 5305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2429 /* 5308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2430 /* 5312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2431 /* 5316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2432 /* 5320 */ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2433 /* 5320 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2434 /* 5325 */ GIR_RootConstrainSelectedInstOperands,
2435 /* 5326 */ // GIR_Coverage, 950,
2436 /* 5326 */ GIR_Done,
2437 /* 5327 */ // Label 291: @5327
2438 /* 5327 */ GIM_Reject,
2439 /* 5328 */ // Label 277: @5328
2440 /* 5328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(5360), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 951 //
2441 /* 5335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2442 /* 5338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2443 /* 5341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2444 /* 5345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2445 /* 5349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2446 /* 5353 */ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2447 /* 5353 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2448 /* 5358 */ GIR_RootConstrainSelectedInstOperands,
2449 /* 5359 */ // GIR_Coverage, 951,
2450 /* 5359 */ GIR_Done,
2451 /* 5360 */ // Label 292: @5360
2452 /* 5360 */ GIM_Reject,
2453 /* 5361 */ // Label 278: @5361
2454 /* 5361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(5393), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 952 //
2455 /* 5368 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2456 /* 5371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2457 /* 5374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2458 /* 5378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2459 /* 5382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2460 /* 5386 */ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2461 /* 5386 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2462 /* 5391 */ GIR_RootConstrainSelectedInstOperands,
2463 /* 5392 */ // GIR_Coverage, 952,
2464 /* 5392 */ GIR_Done,
2465 /* 5393 */ // Label 293: @5393
2466 /* 5393 */ GIM_Reject,
2467 /* 5394 */ // Label 279: @5394
2468 /* 5394 */ GIM_Reject,
2469 /* 5395 */ // Label 9: @5395
2470 /* 5395 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 300*/ GIMT_Encode4(6231),
2471 /* 5406 */ /*GILLT_s32*//*Label 294*/ GIMT_Encode4(5438),
2472 /* 5410 */ /*GILLT_s64*//*Label 295*/ GIMT_Encode4(6006), GIMT_Encode4(0),
2473 /* 5418 */ /*GILLT_v16s8*//*Label 296*/ GIMT_Encode4(6099), GIMT_Encode4(0),
2474 /* 5426 */ /*GILLT_v8s16*//*Label 297*/ GIMT_Encode4(6132),
2475 /* 5430 */ /*GILLT_v4s32*//*Label 298*/ GIMT_Encode4(6165),
2476 /* 5434 */ /*GILLT_v2s64*//*Label 299*/ GIMT_Encode4(6198),
2477 /* 5438 */ // Label 294: @5438
2478 /* 5438 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6005),
2479 /* 5443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2480 /* 5446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2481 /* 5449 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(5613),
2482 /* 5454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2483 /* 5458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2484 /* 5462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 303*/ GIMT_Encode4(5512), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 54 //
2485 /* 5469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2486 /* 5473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2487 /* 5477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2488 /* 5481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2489 /* 5485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2490 /* 5490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2491 /* 5495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2492 /* 5497 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2493 /* 5497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2494 /* 5500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2495 /* 5502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2496 /* 5506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2497 /* 5510 */ GIR_RootConstrainSelectedInstOperands,
2498 /* 5511 */ // GIR_Coverage, 54,
2499 /* 5511 */ GIR_EraseRootFromParent_Done,
2500 /* 5512 */ // Label 303: @5512
2501 /* 5512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(5562), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1102 //
2502 /* 5519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2503 /* 5523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2504 /* 5527 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2505 /* 5531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2506 /* 5535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2507 /* 5540 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2508 /* 5545 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2509 /* 5547 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2510 /* 5547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2511 /* 5550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2512 /* 5552 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2513 /* 5556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2514 /* 5560 */ GIR_RootConstrainSelectedInstOperands,
2515 /* 5561 */ // GIR_Coverage, 1102,
2516 /* 5561 */ GIR_EraseRootFromParent_Done,
2517 /* 5562 */ // Label 304: @5562
2518 /* 5562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(5612), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1204 //
2519 /* 5569 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2520 /* 5573 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2521 /* 5577 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2522 /* 5581 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2523 /* 5585 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2524 /* 5590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2525 /* 5595 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2526 /* 5597 */ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2527 /* 5597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2528 /* 5600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2529 /* 5602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2530 /* 5606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2531 /* 5610 */ GIR_RootConstrainSelectedInstOperands,
2532 /* 5611 */ // GIR_Coverage, 1204,
2533 /* 5611 */ GIR_EraseRootFromParent_Done,
2534 /* 5612 */ // Label 305: @5612
2535 /* 5612 */ GIM_Reject,
2536 /* 5613 */ // Label 302: @5613
2537 /* 5613 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(5663),
2538 /* 5618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2539 /* 5622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2540 /* 5626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2541 /* 5630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 307*/ GIMT_Encode4(5646), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1231 //
2542 /* 5637 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2543 /* 5637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2544 /* 5640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2545 /* 5642 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2546 /* 5644 */ GIR_RootConstrainSelectedInstOperands,
2547 /* 5645 */ // GIR_Coverage, 1231,
2548 /* 5645 */ GIR_EraseRootFromParent_Done,
2549 /* 5646 */ // Label 307: @5646
2550 /* 5646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 308*/ GIMT_Encode4(5662), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1084 //
2551 /* 5653 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2552 /* 5653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2553 /* 5656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2554 /* 5658 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2555 /* 5660 */ GIR_RootConstrainSelectedInstOperands,
2556 /* 5661 */ // GIR_Coverage, 1084,
2557 /* 5661 */ GIR_EraseRootFromParent_Done,
2558 /* 5662 */ // Label 308: @5662
2559 /* 5662 */ GIM_Reject,
2560 /* 5663 */ // Label 306: @5663
2561 /* 5663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(5697), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1419 //
2562 /* 5670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2563 /* 5674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2564 /* 5678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2565 /* 5682 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2566 /* 5682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2567 /* 5685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2568 /* 5687 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2569 /* 5689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2570 /* 5695 */ GIR_RootConstrainSelectedInstOperands,
2571 /* 5696 */ // GIR_Coverage, 1419,
2572 /* 5696 */ GIR_EraseRootFromParent_Done,
2573 /* 5697 */ // Label 309: @5697
2574 /* 5697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 310*/ GIMT_Encode4(5725), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1955 //
2575 /* 5704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2576 /* 5708 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2577 /* 5712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2578 /* 5716 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2579 /* 5716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2580 /* 5719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2581 /* 5721 */ GIR_RootToRootCopy, /*OpIdx*/1, // r
2582 /* 5723 */ GIR_RootConstrainSelectedInstOperands,
2583 /* 5724 */ // GIR_Coverage, 1955,
2584 /* 5724 */ GIR_EraseRootFromParent_Done,
2585 /* 5725 */ // Label 310: @5725
2586 /* 5725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 311*/ GIMT_Encode4(5753), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2295 //
2587 /* 5732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2588 /* 5736 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2589 /* 5740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2590 /* 5744 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2591 /* 5744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2592 /* 5747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2593 /* 5749 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2594 /* 5751 */ GIR_RootConstrainSelectedInstOperands,
2595 /* 5752 */ // GIR_Coverage, 2295,
2596 /* 5752 */ GIR_EraseRootFromParent_Done,
2597 /* 5753 */ // Label 311: @5753
2598 /* 5753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(5787), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2296 //
2599 /* 5760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2600 /* 5764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2601 /* 5768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2602 /* 5772 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2603 /* 5772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2604 /* 5775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2605 /* 5777 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2606 /* 5779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2607 /* 5785 */ GIR_RootConstrainSelectedInstOperands,
2608 /* 5786 */ // GIR_Coverage, 2296,
2609 /* 5786 */ GIR_EraseRootFromParent_Done,
2610 /* 5787 */ // Label 312: @5787
2611 /* 5787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(5815), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2467 //
2612 /* 5794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2613 /* 5798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2614 /* 5802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2615 /* 5806 */ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2616 /* 5806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2617 /* 5809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2618 /* 5811 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2619 /* 5813 */ GIR_RootConstrainSelectedInstOperands,
2620 /* 5814 */ // GIR_Coverage, 2467,
2621 /* 5814 */ GIR_EraseRootFromParent_Done,
2622 /* 5815 */ // Label 313: @5815
2623 /* 5815 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(5906),
2624 /* 5820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2625 /* 5824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2626 /* 5828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 315*/ GIMT_Encode4(5854), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2468 //
2627 /* 5835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2628 /* 5839 */ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2629 /* 5839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2630 /* 5842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2631 /* 5844 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
2632 /* 5846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2633 /* 5852 */ GIR_RootConstrainSelectedInstOperands,
2634 /* 5853 */ // GIR_Coverage, 2468,
2635 /* 5853 */ GIR_EraseRootFromParent_Done,
2636 /* 5854 */ // Label 315: @5854
2637 /* 5854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(5887), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 43 //
2638 /* 5861 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2639 /* 5865 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2640 /* 5869 */ GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2641 /* 5873 */ // MIs[1] Operand 1
2642 /* 5873 */ // No operand predicates
2643 /* 5873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2644 /* 5875 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2645 /* 5875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2646 /* 5878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2647 /* 5880 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2648 /* 5882 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2649 /* 5885 */ GIR_RootConstrainSelectedInstOperands,
2650 /* 5886 */ // GIR_Coverage, 43,
2651 /* 5886 */ GIR_EraseRootFromParent_Done,
2652 /* 5887 */ // Label 316: @5887
2653 /* 5887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(5905), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 53 //
2654 /* 5894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2655 /* 5898 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2656 /* 5898 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2657 /* 5903 */ GIR_RootConstrainSelectedInstOperands,
2658 /* 5904 */ // GIR_Coverage, 53,
2659 /* 5904 */ GIR_Done,
2660 /* 5905 */ // Label 317: @5905
2661 /* 5905 */ GIM_Reject,
2662 /* 5906 */ // Label 314: @5906
2663 /* 5906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(5932), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1087 //
2664 /* 5913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2665 /* 5917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2666 /* 5921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2667 /* 5925 */ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2668 /* 5925 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2669 /* 5930 */ GIR_RootConstrainSelectedInstOperands,
2670 /* 5931 */ // GIR_Coverage, 1087,
2671 /* 5931 */ GIR_Done,
2672 /* 5932 */ // Label 318: @5932
2673 /* 5932 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(5978),
2674 /* 5937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2675 /* 5941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2676 /* 5945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2677 /* 5949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 320*/ GIMT_Encode4(5963), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1101 //
2678 /* 5956 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2679 /* 5956 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2680 /* 5961 */ GIR_RootConstrainSelectedInstOperands,
2681 /* 5962 */ // GIR_Coverage, 1101,
2682 /* 5962 */ GIR_Done,
2683 /* 5963 */ // Label 320: @5963
2684 /* 5963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 321*/ GIMT_Encode4(5977), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1208 //
2685 /* 5970 */ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2686 /* 5970 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2687 /* 5975 */ GIR_RootConstrainSelectedInstOperands,
2688 /* 5976 */ // GIR_Coverage, 1208,
2689 /* 5976 */ GIR_Done,
2690 /* 5977 */ // Label 321: @5977
2691 /* 5977 */ GIM_Reject,
2692 /* 5978 */ // Label 319: @5978
2693 /* 5978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 322*/ GIMT_Encode4(6004), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1962 //
2694 /* 5985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2695 /* 5989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2696 /* 5993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2697 /* 5997 */ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2698 /* 5997 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2699 /* 6002 */ GIR_RootConstrainSelectedInstOperands,
2700 /* 6003 */ // GIR_Coverage, 1962,
2701 /* 6003 */ GIR_Done,
2702 /* 6004 */ // Label 322: @6004
2703 /* 6004 */ GIM_Reject,
2704 /* 6005 */ // Label 301: @6005
2705 /* 6005 */ GIM_Reject,
2706 /* 6006 */ // Label 295: @6006
2707 /* 6006 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6098),
2708 /* 6011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2709 /* 6014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2710 /* 6017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2711 /* 6021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 324*/ GIMT_Encode4(6075), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 237 //
2712 /* 6028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2713 /* 6032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2714 /* 6036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2715 /* 6040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2716 /* 6044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2717 /* 6049 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2718 /* 6054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
2719 /* 6058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2720 /* 6060 */ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2721 /* 6060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2722 /* 6063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2723 /* 6065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2724 /* 6069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2725 /* 6073 */ GIR_RootConstrainSelectedInstOperands,
2726 /* 6074 */ // GIR_Coverage, 237,
2727 /* 6074 */ GIR_EraseRootFromParent_Done,
2728 /* 6075 */ // Label 324: @6075
2729 /* 6075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 325*/ GIMT_Encode4(6097), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 236 //
2730 /* 6082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2731 /* 6086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2732 /* 6090 */ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2733 /* 6090 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2734 /* 6095 */ GIR_RootConstrainSelectedInstOperands,
2735 /* 6096 */ // GIR_Coverage, 236,
2736 /* 6096 */ GIR_Done,
2737 /* 6097 */ // Label 325: @6097
2738 /* 6097 */ GIM_Reject,
2739 /* 6098 */ // Label 323: @6098
2740 /* 6098 */ GIM_Reject,
2741 /* 6099 */ // Label 296: @6099
2742 /* 6099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 326*/ GIMT_Encode4(6131), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1065 //
2743 /* 6106 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2744 /* 6109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2745 /* 6112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2746 /* 6116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2747 /* 6120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2748 /* 6124 */ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2749 /* 6124 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2750 /* 6129 */ GIR_RootConstrainSelectedInstOperands,
2751 /* 6130 */ // GIR_Coverage, 1065,
2752 /* 6130 */ GIR_Done,
2753 /* 6131 */ // Label 326: @6131
2754 /* 6131 */ GIM_Reject,
2755 /* 6132 */ // Label 297: @6132
2756 /* 6132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 327*/ GIMT_Encode4(6164), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1066 //
2757 /* 6139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2758 /* 6142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2759 /* 6145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2760 /* 6149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2761 /* 6153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2762 /* 6157 */ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2763 /* 6157 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2764 /* 6162 */ GIR_RootConstrainSelectedInstOperands,
2765 /* 6163 */ // GIR_Coverage, 1066,
2766 /* 6163 */ GIR_Done,
2767 /* 6164 */ // Label 327: @6164
2768 /* 6164 */ GIM_Reject,
2769 /* 6165 */ // Label 298: @6165
2770 /* 6165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 328*/ GIMT_Encode4(6197), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1067 //
2771 /* 6172 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2772 /* 6175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2773 /* 6178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2774 /* 6182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2775 /* 6186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2776 /* 6190 */ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2777 /* 6190 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2778 /* 6195 */ GIR_RootConstrainSelectedInstOperands,
2779 /* 6196 */ // GIR_Coverage, 1067,
2780 /* 6196 */ GIR_Done,
2781 /* 6197 */ // Label 328: @6197
2782 /* 6197 */ GIM_Reject,
2783 /* 6198 */ // Label 299: @6198
2784 /* 6198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 329*/ GIMT_Encode4(6230), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1068 //
2785 /* 6205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2786 /* 6208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2787 /* 6211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2788 /* 6215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2789 /* 6219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2790 /* 6223 */ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2791 /* 6223 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2792 /* 6228 */ GIR_RootConstrainSelectedInstOperands,
2793 /* 6229 */ // GIR_Coverage, 1068,
2794 /* 6229 */ GIR_Done,
2795 /* 6230 */ // Label 329: @6230
2796 /* 6230 */ GIM_Reject,
2797 /* 6231 */ // Label 300: @6231
2798 /* 6231 */ GIM_Reject,
2799 /* 6232 */ // Label 10: @6232
2800 /* 6232 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(6330),
2801 /* 6237 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2802 /* 6240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2803 /* 6243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2804 /* 6246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2805 /* 6249 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(6303),
2806 /* 6254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2807 /* 6258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 332*/ GIMT_Encode4(6280), GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode), // Rule ID 207 //
2808 /* 6265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2809 /* 6269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2810 /* 6273 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2811 /* 6273 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2812 /* 6278 */ GIR_RootConstrainSelectedInstOperands,
2813 /* 6279 */ // GIR_Coverage, 207,
2814 /* 6279 */ GIR_Done,
2815 /* 6280 */ // Label 332: @6280
2816 /* 6280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(6302), GIMT_Encode2(GIFBS_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMips16Mode), // Rule ID 208 //
2817 /* 6287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2818 /* 6291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2819 /* 6295 */ // (MipsBuildPairF64_FPR:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$lo, FGR32Opnd:{ *:[f32] }:$hi) => (BuildPairF64_FPR:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$lo, FGR32Opnd:{ *:[f32] }:$hi)
2820 /* 6295 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_FPR),
2821 /* 6300 */ GIR_RootConstrainSelectedInstOperands,
2822 /* 6301 */ // GIR_Coverage, 208,
2823 /* 6301 */ GIR_Done,
2824 /* 6302 */ // Label 333: @6302
2825 /* 6302 */ GIM_Reject,
2826 /* 6303 */ // Label 331: @6303
2827 /* 6303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 334*/ GIMT_Encode4(6329), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMips16Mode), // Rule ID 209 //
2828 /* 6310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2829 /* 6314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2830 /* 6318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2831 /* 6322 */ // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2832 /* 6322 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2833 /* 6327 */ GIR_RootConstrainSelectedInstOperands,
2834 /* 6328 */ // GIR_Coverage, 209,
2835 /* 6328 */ GIR_Done,
2836 /* 6329 */ // Label 334: @6329
2837 /* 6329 */ GIM_Reject,
2838 /* 6330 */ // Label 330: @6330
2839 /* 6330 */ GIM_Reject,
2840 /* 6331 */ // Label 11: @6331
2841 /* 6331 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(6400),
2842 /* 6336 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2843 /* 6339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2844 /* 6342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2845 /* 6345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2846 /* 6349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 336*/ GIMT_Encode4(6374), GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc), // Rule ID 747 //
2847 /* 6356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2848 /* 6360 */ // MIs[0] rs
2849 /* 6360 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2850 /* 6365 */ // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2851 /* 6365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2852 /* 6368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2853 /* 6370 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2854 /* 6372 */ GIR_RootConstrainSelectedInstOperands,
2855 /* 6373 */ // GIR_Coverage, 747,
2856 /* 6373 */ GIR_EraseRootFromParent_Done,
2857 /* 6374 */ // Label 336: @6374
2858 /* 6374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(6399), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 749 //
2859 /* 6381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2860 /* 6385 */ // MIs[0] fs
2861 /* 6385 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2862 /* 6390 */ // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2863 /* 6390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2864 /* 6393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2865 /* 6395 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2866 /* 6397 */ GIR_RootConstrainSelectedInstOperands,
2867 /* 6398 */ // GIR_Coverage, 749,
2868 /* 6398 */ GIR_EraseRootFromParent_Done,
2869 /* 6399 */ // Label 337: @6399
2870 /* 6399 */ GIM_Reject,
2871 /* 6400 */ // Label 335: @6400
2872 /* 6400 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(6489),
2873 /* 6405 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2874 /* 6408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2875 /* 6411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2876 /* 6414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2877 /* 6418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 339*/ GIMT_Encode4(6453), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 746 //
2878 /* 6425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2879 /* 6429 */ // MIs[0] rs
2880 /* 6429 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2881 /* 6434 */ // MIs[0] rs
2882 /* 6434 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2883 /* 6439 */ // MIs[0] rs
2884 /* 6439 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2885 /* 6444 */ // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2886 /* 6444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2887 /* 6447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2888 /* 6449 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2889 /* 6451 */ GIR_RootConstrainSelectedInstOperands,
2890 /* 6452 */ // GIR_Coverage, 746,
2891 /* 6452 */ GIR_EraseRootFromParent_Done,
2892 /* 6453 */ // Label 339: @6453
2893 /* 6453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(6488), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 748 //
2894 /* 6460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2895 /* 6464 */ // MIs[0] fs
2896 /* 6464 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2897 /* 6469 */ // MIs[0] fs
2898 /* 6469 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2899 /* 6474 */ // MIs[0] fs
2900 /* 6474 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2901 /* 6479 */ // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2902 /* 6479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2903 /* 6482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2904 /* 6484 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
2905 /* 6486 */ GIR_RootConstrainSelectedInstOperands,
2906 /* 6487 */ // GIR_Coverage, 748,
2907 /* 6487 */ GIR_EraseRootFromParent_Done,
2908 /* 6488 */ // Label 340: @6488
2909 /* 6488 */ GIM_Reject,
2910 /* 6489 */ // Label 338: @6489
2911 /* 6489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(6557), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 745 //
2912 /* 6496 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
2913 /* 6499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
2914 /* 6502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2915 /* 6505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2916 /* 6509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2917 /* 6513 */ // MIs[0] rs
2918 /* 6513 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2919 /* 6518 */ // MIs[0] rs
2920 /* 6518 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2921 /* 6523 */ // MIs[0] rs
2922 /* 6523 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2923 /* 6528 */ // MIs[0] rs
2924 /* 6528 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2925 /* 6533 */ // MIs[0] rs
2926 /* 6533 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2927 /* 6538 */ // MIs[0] rs
2928 /* 6538 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2929 /* 6543 */ // MIs[0] rs
2930 /* 6543 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
2931 /* 6548 */ // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
2932 /* 6548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
2933 /* 6551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2934 /* 6553 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2935 /* 6555 */ GIR_RootConstrainSelectedInstOperands,
2936 /* 6556 */ // GIR_Coverage, 745,
2937 /* 6556 */ GIR_EraseRootFromParent_Done,
2938 /* 6557 */ // Label 341: @6557
2939 /* 6557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(6665), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 744 //
2940 /* 6564 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
2941 /* 6567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
2942 /* 6570 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2943 /* 6573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2944 /* 6577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2945 /* 6581 */ // MIs[0] rs
2946 /* 6581 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2947 /* 6586 */ // MIs[0] rs
2948 /* 6586 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2949 /* 6591 */ // MIs[0] rs
2950 /* 6591 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2951 /* 6596 */ // MIs[0] rs
2952 /* 6596 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2953 /* 6601 */ // MIs[0] rs
2954 /* 6601 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2955 /* 6606 */ // MIs[0] rs
2956 /* 6606 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2957 /* 6611 */ // MIs[0] rs
2958 /* 6611 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
2959 /* 6616 */ // MIs[0] rs
2960 /* 6616 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
2961 /* 6621 */ // MIs[0] rs
2962 /* 6621 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
2963 /* 6626 */ // MIs[0] rs
2964 /* 6626 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
2965 /* 6631 */ // MIs[0] rs
2966 /* 6631 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
2967 /* 6636 */ // MIs[0] rs
2968 /* 6636 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
2969 /* 6641 */ // MIs[0] rs
2970 /* 6641 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
2971 /* 6646 */ // MIs[0] rs
2972 /* 6646 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
2973 /* 6651 */ // MIs[0] rs
2974 /* 6651 */ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
2975 /* 6656 */ // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
2976 /* 6656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
2977 /* 6659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2978 /* 6661 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
2979 /* 6663 */ GIR_RootConstrainSelectedInstOperands,
2980 /* 6664 */ // GIR_Coverage, 744,
2981 /* 6664 */ GIR_EraseRootFromParent_Done,
2982 /* 6665 */ // Label 342: @6665
2983 /* 6665 */ GIM_Reject,
2984 /* 6666 */ // Label 12: @6666
2985 /* 6666 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 351*/ GIMT_Encode4(10659),
2986 /* 6677 */ /*GILLT_s32*//*Label 343*/ GIMT_Encode4(6709),
2987 /* 6681 */ /*GILLT_s64*//*Label 344*/ GIMT_Encode4(6978),
2988 /* 6685 */ /*GILLT_v4s8*//*Label 345*/ GIMT_Encode4(7032),
2989 /* 6689 */ /*GILLT_v16s8*//*Label 346*/ GIMT_Encode4(7090),
2990 /* 6693 */ /*GILLT_v2s16*//*Label 347*/ GIMT_Encode4(7735),
2991 /* 6697 */ /*GILLT_v8s16*//*Label 348*/ GIMT_Encode4(7793),
2992 /* 6701 */ /*GILLT_v4s32*//*Label 349*/ GIMT_Encode4(8657),
2993 /* 6705 */ /*GILLT_v2s64*//*Label 350*/ GIMT_Encode4(9625),
2994 /* 6709 */ // Label 343: @6709
2995 /* 6709 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(5), /*)*//*default:*//*Label 355*/ GIMT_Encode4(6977),
2996 /* 6720 */ /*GILLT_s32*//*Label 352*/ GIMT_Encode4(6740), GIMT_Encode4(0),
2997 /* 6728 */ /*GILLT_v4s8*//*Label 353*/ GIMT_Encode4(6871), GIMT_Encode4(0),
2998 /* 6736 */ /*GILLT_v2s16*//*Label 354*/ GIMT_Encode4(6924),
2999 /* 6740 */ // Label 352: @6740
3000 /* 6740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 356*/ GIMT_Encode4(6762), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 138 //
3001 /* 6747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3002 /* 6751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3003 /* 6755 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3004 /* 6755 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3005 /* 6760 */ GIR_RootConstrainSelectedInstOperands,
3006 /* 6761 */ // GIR_Coverage, 138,
3007 /* 6761 */ GIR_Done,
3008 /* 6762 */ // Label 356: @6762
3009 /* 6762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(6784), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 139 //
3010 /* 6769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3011 /* 6773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3012 /* 6777 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3013 /* 6777 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3014 /* 6782 */ GIR_RootConstrainSelectedInstOperands,
3015 /* 6783 */ // GIR_Coverage, 139,
3016 /* 6783 */ GIR_Done,
3017 /* 6784 */ // Label 357: @6784
3018 /* 6784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(6806), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1182 //
3019 /* 6791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3020 /* 6795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3021 /* 6799 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3022 /* 6799 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3023 /* 6804 */ GIR_RootConstrainSelectedInstOperands,
3024 /* 6805 */ // GIR_Coverage, 1182,
3025 /* 6805 */ GIR_Done,
3026 /* 6806 */ // Label 358: @6806
3027 /* 6806 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(6848),
3028 /* 6811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3029 /* 6815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3030 /* 6819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 360*/ GIMT_Encode4(6833), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1183 //
3031 /* 6826 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3032 /* 6826 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3033 /* 6831 */ GIR_RootConstrainSelectedInstOperands,
3034 /* 6832 */ // GIR_Coverage, 1183,
3035 /* 6832 */ GIR_Done,
3036 /* 6833 */ // Label 360: @6833
3037 /* 6833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 361*/ GIMT_Encode4(6847), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1197 //
3038 /* 6840 */ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3039 /* 6840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3040 /* 6845 */ GIR_RootConstrainSelectedInstOperands,
3041 /* 6846 */ // GIR_Coverage, 1197,
3042 /* 6846 */ GIR_Done,
3043 /* 6847 */ // Label 361: @6847
3044 /* 6847 */ GIM_Reject,
3045 /* 6848 */ // Label 359: @6848
3046 /* 6848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 362*/ GIMT_Encode4(6870), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1198 //
3047 /* 6855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3048 /* 6859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3049 /* 6863 */ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3050 /* 6863 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3051 /* 6868 */ GIR_RootConstrainSelectedInstOperands,
3052 /* 6869 */ // GIR_Coverage, 1198,
3053 /* 6869 */ GIR_Done,
3054 /* 6870 */ // Label 362: @6870
3055 /* 6870 */ GIM_Reject,
3056 /* 6871 */ // Label 353: @6871
3057 /* 6871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(6897), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2044 //
3058 /* 6878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3059 /* 6882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3060 /* 6886 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3061 /* 6886 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3062 /* 6891 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3063 /* 6896 */ // GIR_Coverage, 2044,
3064 /* 6896 */ GIR_Done,
3065 /* 6897 */ // Label 363: @6897
3066 /* 6897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(6923), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2048 //
3067 /* 6904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3068 /* 6908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3069 /* 6912 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3070 /* 6912 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3071 /* 6917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3072 /* 6922 */ // GIR_Coverage, 2048,
3073 /* 6922 */ GIR_Done,
3074 /* 6923 */ // Label 364: @6923
3075 /* 6923 */ GIM_Reject,
3076 /* 6924 */ // Label 354: @6924
3077 /* 6924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(6950), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2043 //
3078 /* 6931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3079 /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3080 /* 6939 */ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3081 /* 6939 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3082 /* 6944 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3083 /* 6949 */ // GIR_Coverage, 2043,
3084 /* 6949 */ GIR_Done,
3085 /* 6950 */ // Label 365: @6950
3086 /* 6950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(6976), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2047 //
3087 /* 6957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3088 /* 6961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3089 /* 6965 */ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3090 /* 6965 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3091 /* 6970 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3092 /* 6975 */ // GIR_Coverage, 2047,
3093 /* 6975 */ GIR_Done,
3094 /* 6976 */ // Label 366: @6976
3095 /* 6976 */ GIM_Reject,
3096 /* 6977 */ // Label 355: @6977
3097 /* 6977 */ GIM_Reject,
3098 /* 6978 */ // Label 344: @6978
3099 /* 6978 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(7031),
3100 /* 6983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3101 /* 6986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 368*/ GIMT_Encode4(7008), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 140 //
3102 /* 6993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3103 /* 6997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3104 /* 7001 */ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3105 /* 7001 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3106 /* 7006 */ GIR_RootConstrainSelectedInstOperands,
3107 /* 7007 */ // GIR_Coverage, 140,
3108 /* 7007 */ GIR_Done,
3109 /* 7008 */ // Label 368: @7008
3110 /* 7008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 369*/ GIMT_Encode4(7030), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 141 //
3111 /* 7015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3112 /* 7019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3113 /* 7023 */ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3114 /* 7023 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3115 /* 7028 */ GIR_RootConstrainSelectedInstOperands,
3116 /* 7029 */ // GIR_Coverage, 141,
3117 /* 7029 */ GIR_Done,
3118 /* 7030 */ // Label 369: @7030
3119 /* 7030 */ GIM_Reject,
3120 /* 7031 */ // Label 367: @7031
3121 /* 7031 */ GIM_Reject,
3122 /* 7032 */ // Label 345: @7032
3123 /* 7032 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(7089),
3124 /* 7037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3125 /* 7040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3126 /* 7044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 371*/ GIMT_Encode4(7066), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2046 //
3127 /* 7051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3128 /* 7055 */ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3129 /* 7055 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3130 /* 7060 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3131 /* 7065 */ // GIR_Coverage, 2046,
3132 /* 7065 */ GIR_Done,
3133 /* 7066 */ // Label 371: @7066
3134 /* 7066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 372*/ GIMT_Encode4(7088), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2050 //
3135 /* 7073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3136 /* 7077 */ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3137 /* 7077 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3138 /* 7082 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3139 /* 7087 */ // GIR_Coverage, 2050,
3140 /* 7087 */ GIR_Done,
3141 /* 7088 */ // Label 372: @7088
3142 /* 7088 */ GIM_Reject,
3143 /* 7089 */ // Label 370: @7089
3144 /* 7089 */ GIM_Reject,
3145 /* 7090 */ // Label 346: @7090
3146 /* 7090 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 376*/ GIMT_Encode4(7734),
3147 /* 7101 */ /*GILLT_v8s16*//*Label 373*/ GIMT_Encode4(7113),
3148 /* 7105 */ /*GILLT_v4s32*//*Label 374*/ GIMT_Encode4(7298),
3149 /* 7109 */ /*GILLT_v2s64*//*Label 375*/ GIMT_Encode4(7469),
3150 /* 7113 */ // Label 373: @7113
3151 /* 7113 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(7297),
3152 /* 7118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3153 /* 7122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 378*/ GIMT_Encode4(7140), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2134 //
3154 /* 7129 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
3155 /* 7129 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3156 /* 7134 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3157 /* 7139 */ // GIR_Coverage, 2134,
3158 /* 7139 */ GIR_Done,
3159 /* 7140 */ // Label 378: @7140
3160 /* 7140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 379*/ GIMT_Encode4(7158), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2137 //
3161 /* 7147 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
3162 /* 7147 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3163 /* 7152 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3164 /* 7157 */ // GIR_Coverage, 2137,
3165 /* 7157 */ GIR_Done,
3166 /* 7158 */ // Label 379: @7158
3167 /* 7158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(7227), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2171 //
3168 /* 7165 */ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3169 /* 7165 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3170 /* 7168 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3171 /* 7172 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3172 /* 7177 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3173 /* 7181 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3174 /* 7186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3175 /* 7189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3176 /* 7193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3177 /* 7198 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3178 /* 7201 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3179 /* 7211 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3180 /* 7213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3181 /* 7216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3182 /* 7218 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3183 /* 7221 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3184 /* 7226 */ // GIR_Coverage, 2171,
3185 /* 7226 */ GIR_EraseRootFromParent_Done,
3186 /* 7227 */ // Label 380: @7227
3187 /* 7227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(7296), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2176 //
3188 /* 7234 */ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3189 /* 7234 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3190 /* 7237 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3191 /* 7241 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3192 /* 7246 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3193 /* 7250 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3194 /* 7255 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3195 /* 7258 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3196 /* 7262 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3197 /* 7267 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3198 /* 7270 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3199 /* 7280 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3200 /* 7282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3201 /* 7285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3202 /* 7287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3203 /* 7290 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3204 /* 7295 */ // GIR_Coverage, 2176,
3205 /* 7295 */ GIR_EraseRootFromParent_Done,
3206 /* 7296 */ // Label 381: @7296
3207 /* 7296 */ GIM_Reject,
3208 /* 7297 */ // Label 377: @7297
3209 /* 7297 */ GIM_Reject,
3210 /* 7298 */ // Label 374: @7298
3211 /* 7298 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(7468),
3212 /* 7303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3213 /* 7307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 383*/ GIMT_Encode4(7325), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2135 //
3214 /* 7314 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
3215 /* 7314 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3216 /* 7319 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3217 /* 7324 */ // GIR_Coverage, 2135,
3218 /* 7324 */ GIR_Done,
3219 /* 7325 */ // Label 383: @7325
3220 /* 7325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(7343), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2138 //
3221 /* 7332 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
3222 /* 7332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3223 /* 7337 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3224 /* 7342 */ // GIR_Coverage, 2138,
3225 /* 7342 */ GIR_Done,
3226 /* 7343 */ // Label 384: @7343
3227 /* 7343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 385*/ GIMT_Encode4(7405), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2181 //
3228 /* 7350 */ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3229 /* 7350 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3230 /* 7353 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3231 /* 7357 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3232 /* 7362 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3233 /* 7366 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3234 /* 7371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3235 /* 7374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3236 /* 7378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3237 /* 7383 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3238 /* 7386 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3239 /* 7389 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3240 /* 7391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3241 /* 7394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3242 /* 7396 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3243 /* 7399 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3244 /* 7404 */ // GIR_Coverage, 2181,
3245 /* 7404 */ GIR_EraseRootFromParent_Done,
3246 /* 7405 */ // Label 385: @7405
3247 /* 7405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 386*/ GIMT_Encode4(7467), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2186 //
3248 /* 7412 */ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
3249 /* 7412 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3250 /* 7415 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3251 /* 7419 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3252 /* 7424 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3253 /* 7428 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3254 /* 7433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3255 /* 7436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3256 /* 7440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3257 /* 7445 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3258 /* 7448 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3259 /* 7451 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3260 /* 7453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3261 /* 7456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3262 /* 7458 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3263 /* 7461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3264 /* 7466 */ // GIR_Coverage, 2186,
3265 /* 7466 */ GIR_EraseRootFromParent_Done,
3266 /* 7467 */ // Label 386: @7467
3267 /* 7467 */ GIM_Reject,
3268 /* 7468 */ // Label 382: @7468
3269 /* 7468 */ GIM_Reject,
3270 /* 7469 */ // Label 375: @7469
3271 /* 7469 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(7733),
3272 /* 7474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
3273 /* 7478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 388*/ GIMT_Encode4(7496), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2136 //
3274 /* 7485 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
3275 /* 7485 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3276 /* 7490 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3277 /* 7495 */ // GIR_Coverage, 2136,
3278 /* 7495 */ GIR_Done,
3279 /* 7496 */ // Label 388: @7496
3280 /* 7496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(7514), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2139 //
3281 /* 7503 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
3282 /* 7503 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3283 /* 7508 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3284 /* 7513 */ // GIR_Coverage, 2139,
3285 /* 7513 */ GIR_Done,
3286 /* 7514 */ // Label 389: @7514
3287 /* 7514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(7623), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2191 //
3288 /* 7521 */ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3289 /* 7521 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3290 /* 7524 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3291 /* 7528 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3292 /* 7533 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3293 /* 7537 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3294 /* 7542 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3295 /* 7545 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3296 /* 7549 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3297 /* 7554 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3298 /* 7557 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3299 /* 7560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3300 /* 7562 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3301 /* 7565 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3302 /* 7569 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3303 /* 7574 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3304 /* 7577 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3305 /* 7582 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3306 /* 7585 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3307 /* 7589 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3308 /* 7594 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3309 /* 7597 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3310 /* 7607 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3311 /* 7609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3312 /* 7612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3313 /* 7614 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3314 /* 7617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3315 /* 7622 */ // GIR_Coverage, 2191,
3316 /* 7622 */ GIR_EraseRootFromParent_Done,
3317 /* 7623 */ // Label 390: @7623
3318 /* 7623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 391*/ GIMT_Encode4(7732), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2196 //
3319 /* 7630 */ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
3320 /* 7630 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3321 /* 7633 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3322 /* 7637 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3323 /* 7642 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3324 /* 7646 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3325 /* 7651 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3326 /* 7654 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3327 /* 7658 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3328 /* 7663 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3329 /* 7666 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3330 /* 7669 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3331 /* 7671 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3332 /* 7674 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3333 /* 7678 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3334 /* 7683 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3335 /* 7686 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3336 /* 7691 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3337 /* 7694 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3338 /* 7698 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3339 /* 7703 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3340 /* 7706 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3341 /* 7716 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3342 /* 7718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3343 /* 7721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3344 /* 7723 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3345 /* 7726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3346 /* 7731 */ // GIR_Coverage, 2196,
3347 /* 7731 */ GIR_EraseRootFromParent_Done,
3348 /* 7732 */ // Label 391: @7732
3349 /* 7732 */ GIM_Reject,
3350 /* 7733 */ // Label 387: @7733
3351 /* 7733 */ GIM_Reject,
3352 /* 7734 */ // Label 376: @7734
3353 /* 7734 */ GIM_Reject,
3354 /* 7735 */ // Label 347: @7735
3355 /* 7735 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(7792),
3356 /* 7740 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3357 /* 7743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3358 /* 7747 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 393*/ GIMT_Encode4(7769), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2045 //
3359 /* 7754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3360 /* 7758 */ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3361 /* 7758 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3362 /* 7763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3363 /* 7768 */ // GIR_Coverage, 2045,
3364 /* 7768 */ GIR_Done,
3365 /* 7769 */ // Label 393: @7769
3366 /* 7769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(7791), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2049 //
3367 /* 7776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3368 /* 7780 */ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3369 /* 7780 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3370 /* 7785 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3371 /* 7790 */ // GIR_Coverage, 2049,
3372 /* 7790 */ GIR_Done,
3373 /* 7791 */ // Label 394: @7791
3374 /* 7791 */ GIM_Reject,
3375 /* 7792 */ // Label 392: @7792
3376 /* 7792 */ GIM_Reject,
3377 /* 7793 */ // Label 348: @7793
3378 /* 7793 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 399*/ GIMT_Encode4(8656),
3379 /* 7804 */ /*GILLT_v16s8*//*Label 395*/ GIMT_Encode4(7824), GIMT_Encode4(0),
3380 /* 7812 */ /*GILLT_v8s16*//*Label 396*/ GIMT_Encode4(7991),
3381 /* 7816 */ /*GILLT_v4s32*//*Label 397*/ GIMT_Encode4(8038),
3382 /* 7820 */ /*GILLT_v2s64*//*Label 398*/ GIMT_Encode4(8361),
3383 /* 7824 */ // Label 395: @7824
3384 /* 7824 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(7990),
3385 /* 7829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3386 /* 7833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 401*/ GIMT_Encode4(7851), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2140 //
3387 /* 7840 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3388 /* 7840 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3389 /* 7845 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3390 /* 7850 */ // GIR_Coverage, 2140,
3391 /* 7850 */ GIR_Done,
3392 /* 7851 */ // Label 401: @7851
3393 /* 7851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 402*/ GIMT_Encode4(7920), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2165 //
3394 /* 7858 */ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3395 /* 7858 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3396 /* 7861 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3397 /* 7865 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3398 /* 7870 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3399 /* 7874 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3400 /* 7879 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3401 /* 7882 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3402 /* 7886 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3403 /* 7891 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3404 /* 7894 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3405 /* 7904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3406 /* 7906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3407 /* 7909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3408 /* 7911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3409 /* 7914 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3410 /* 7919 */ // GIR_Coverage, 2165,
3411 /* 7919 */ GIR_EraseRootFromParent_Done,
3412 /* 7920 */ // Label 402: @7920
3413 /* 7920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 403*/ GIMT_Encode4(7989), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2166 //
3414 /* 7927 */ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3415 /* 7927 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3416 /* 7930 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3417 /* 7934 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3418 /* 7939 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3419 /* 7943 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3420 /* 7948 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3421 /* 7951 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3422 /* 7955 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3423 /* 7960 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3424 /* 7963 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3425 /* 7973 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3426 /* 7975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3427 /* 7978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3428 /* 7980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3429 /* 7983 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3430 /* 7988 */ // GIR_Coverage, 2166,
3431 /* 7988 */ GIR_EraseRootFromParent_Done,
3432 /* 7989 */ // Label 403: @7989
3433 /* 7989 */ GIM_Reject,
3434 /* 7990 */ // Label 400: @7990
3435 /* 7990 */ GIM_Reject,
3436 /* 7991 */ // Label 396: @7991
3437 /* 7991 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(8037),
3438 /* 7996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3439 /* 8000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 405*/ GIMT_Encode4(8018), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2128 //
3440 /* 8007 */ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3441 /* 8007 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3442 /* 8012 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3443 /* 8017 */ // GIR_Coverage, 2128,
3444 /* 8017 */ GIR_Done,
3445 /* 8018 */ // Label 405: @8018
3446 /* 8018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 406*/ GIMT_Encode4(8036), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2131 //
3447 /* 8025 */ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3448 /* 8025 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3449 /* 8030 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3450 /* 8035 */ // GIR_Coverage, 2131,
3451 /* 8035 */ GIR_Done,
3452 /* 8036 */ // Label 406: @8036
3453 /* 8036 */ GIM_Reject,
3454 /* 8037 */ // Label 404: @8037
3455 /* 8037 */ GIM_Reject,
3456 /* 8038 */ // Label 397: @8038
3457 /* 8038 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(8360),
3458 /* 8043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3459 /* 8047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(8065), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2141 //
3460 /* 8054 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3461 /* 8054 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3462 /* 8059 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3463 /* 8064 */ // GIR_Coverage, 2141,
3464 /* 8064 */ GIR_Done,
3465 /* 8065 */ // Label 408: @8065
3466 /* 8065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 409*/ GIMT_Encode4(8083), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2143 //
3467 /* 8072 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
3468 /* 8072 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3469 /* 8077 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3470 /* 8082 */ // GIR_Coverage, 2143,
3471 /* 8082 */ GIR_Done,
3472 /* 8083 */ // Label 409: @8083
3473 /* 8083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(8152), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2182 //
3474 /* 8090 */ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3475 /* 8090 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3476 /* 8093 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3477 /* 8097 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3478 /* 8102 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3479 /* 8106 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3480 /* 8111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3481 /* 8114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3482 /* 8118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3483 /* 8123 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3484 /* 8126 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3485 /* 8136 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3486 /* 8138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3487 /* 8141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3488 /* 8143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3489 /* 8146 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3490 /* 8151 */ // GIR_Coverage, 2182,
3491 /* 8151 */ GIR_EraseRootFromParent_Done,
3492 /* 8152 */ // Label 410: @8152
3493 /* 8152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(8221), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2183 //
3494 /* 8159 */ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3495 /* 8159 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3496 /* 8162 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3497 /* 8166 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3498 /* 8171 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3499 /* 8175 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3500 /* 8180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3501 /* 8183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3502 /* 8187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3503 /* 8192 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3504 /* 8195 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3505 /* 8205 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3506 /* 8207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3507 /* 8210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3508 /* 8212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3509 /* 8215 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3510 /* 8220 */ // GIR_Coverage, 2183,
3511 /* 8220 */ GIR_EraseRootFromParent_Done,
3512 /* 8221 */ // Label 411: @8221
3513 /* 8221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(8290), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2187 //
3514 /* 8228 */ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3515 /* 8228 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3516 /* 8231 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3517 /* 8235 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3518 /* 8240 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3519 /* 8244 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3520 /* 8249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3521 /* 8252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3522 /* 8256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3523 /* 8261 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3524 /* 8264 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3525 /* 8274 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3526 /* 8276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3527 /* 8279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3528 /* 8281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3529 /* 8284 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3530 /* 8289 */ // GIR_Coverage, 2187,
3531 /* 8289 */ GIR_EraseRootFromParent_Done,
3532 /* 8290 */ // Label 412: @8290
3533 /* 8290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 413*/ GIMT_Encode4(8359), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2188 //
3534 /* 8297 */ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
3535 /* 8297 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3536 /* 8300 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3537 /* 8304 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3538 /* 8309 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3539 /* 8313 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3540 /* 8318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3541 /* 8321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3542 /* 8325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3543 /* 8330 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3544 /* 8333 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3545 /* 8343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3546 /* 8345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3547 /* 8348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3548 /* 8350 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3549 /* 8353 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3550 /* 8358 */ // GIR_Coverage, 2188,
3551 /* 8358 */ GIR_EraseRootFromParent_Done,
3552 /* 8359 */ // Label 413: @8359
3553 /* 8359 */ GIM_Reject,
3554 /* 8360 */ // Label 407: @8360
3555 /* 8360 */ GIM_Reject,
3556 /* 8361 */ // Label 398: @8361
3557 /* 8361 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(8655),
3558 /* 8366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3559 /* 8370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(8388), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2142 //
3560 /* 8377 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3561 /* 8377 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3562 /* 8382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3563 /* 8387 */ // GIR_Coverage, 2142,
3564 /* 8387 */ GIR_Done,
3565 /* 8388 */ // Label 415: @8388
3566 /* 8388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(8406), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2144 //
3567 /* 8395 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
3568 /* 8395 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3569 /* 8400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3570 /* 8405 */ // GIR_Coverage, 2144,
3571 /* 8405 */ GIR_Done,
3572 /* 8406 */ // Label 416: @8406
3573 /* 8406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(8468), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2192 //
3574 /* 8413 */ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3575 /* 8413 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3576 /* 8416 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3577 /* 8420 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3578 /* 8425 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3579 /* 8429 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3580 /* 8434 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3581 /* 8437 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3582 /* 8441 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3583 /* 8446 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3584 /* 8449 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3585 /* 8452 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3586 /* 8454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3587 /* 8457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3588 /* 8459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3589 /* 8462 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3590 /* 8467 */ // GIR_Coverage, 2192,
3591 /* 8467 */ GIR_EraseRootFromParent_Done,
3592 /* 8468 */ // Label 417: @8468
3593 /* 8468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 418*/ GIMT_Encode4(8530), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2193 //
3594 /* 8475 */ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3595 /* 8475 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3596 /* 8478 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3597 /* 8482 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3598 /* 8487 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3599 /* 8491 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3600 /* 8496 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3601 /* 8499 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3602 /* 8503 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3603 /* 8508 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3604 /* 8511 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3605 /* 8514 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3606 /* 8516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3607 /* 8519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3608 /* 8521 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3609 /* 8524 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3610 /* 8529 */ // GIR_Coverage, 2193,
3611 /* 8529 */ GIR_EraseRootFromParent_Done,
3612 /* 8530 */ // Label 418: @8530
3613 /* 8530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 419*/ GIMT_Encode4(8592), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2197 //
3614 /* 8537 */ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3615 /* 8537 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3616 /* 8540 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3617 /* 8544 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3618 /* 8549 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3619 /* 8553 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3620 /* 8558 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3621 /* 8561 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3622 /* 8565 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3623 /* 8570 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3624 /* 8573 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3625 /* 8576 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3626 /* 8578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3627 /* 8581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3628 /* 8583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3629 /* 8586 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3630 /* 8591 */ // GIR_Coverage, 2197,
3631 /* 8591 */ GIR_EraseRootFromParent_Done,
3632 /* 8592 */ // Label 419: @8592
3633 /* 8592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 420*/ GIMT_Encode4(8654), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2198 //
3634 /* 8599 */ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
3635 /* 8599 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3636 /* 8602 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3637 /* 8606 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3638 /* 8611 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3639 /* 8615 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3640 /* 8620 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3641 /* 8623 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3642 /* 8627 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3643 /* 8632 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3644 /* 8635 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3645 /* 8638 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3646 /* 8640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3647 /* 8643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3648 /* 8645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3649 /* 8648 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3650 /* 8653 */ // GIR_Coverage, 2198,
3651 /* 8653 */ GIR_EraseRootFromParent_Done,
3652 /* 8654 */ // Label 420: @8654
3653 /* 8654 */ GIM_Reject,
3654 /* 8655 */ // Label 414: @8655
3655 /* 8655 */ GIM_Reject,
3656 /* 8656 */ // Label 399: @8656
3657 /* 8656 */ GIM_Reject,
3658 /* 8657 */ // Label 349: @8657
3659 /* 8657 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 425*/ GIMT_Encode4(9624),
3660 /* 8668 */ /*GILLT_v16s8*//*Label 421*/ GIMT_Encode4(8688), GIMT_Encode4(0),
3661 /* 8676 */ /*GILLT_v8s16*//*Label 422*/ GIMT_Encode4(8859),
3662 /* 8680 */ /*GILLT_v4s32*//*Label 423*/ GIMT_Encode4(9218),
3663 /* 8684 */ /*GILLT_v2s64*//*Label 424*/ GIMT_Encode4(9265),
3664 /* 8688 */ // Label 421: @8688
3665 /* 8688 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(8858),
3666 /* 8693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3667 /* 8697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 427*/ GIMT_Encode4(8715), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2145 //
3668 /* 8704 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3669 /* 8704 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3670 /* 8709 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3671 /* 8714 */ // GIR_Coverage, 2145,
3672 /* 8714 */ GIR_Done,
3673 /* 8715 */ // Label 427: @8715
3674 /* 8715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 428*/ GIMT_Encode4(8733), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2155 //
3675 /* 8722 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3676 /* 8722 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3677 /* 8727 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3678 /* 8732 */ // GIR_Coverage, 2155,
3679 /* 8732 */ GIR_Done,
3680 /* 8733 */ // Label 428: @8733
3681 /* 8733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 429*/ GIMT_Encode4(8795), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2167 //
3682 /* 8740 */ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3683 /* 8740 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3684 /* 8743 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3685 /* 8747 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3686 /* 8752 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3687 /* 8756 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3688 /* 8761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3689 /* 8764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3690 /* 8768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3691 /* 8773 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3692 /* 8776 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3693 /* 8779 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3694 /* 8781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3695 /* 8784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3696 /* 8786 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3697 /* 8789 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3698 /* 8794 */ // GIR_Coverage, 2167,
3699 /* 8794 */ GIR_EraseRootFromParent_Done,
3700 /* 8795 */ // Label 429: @8795
3701 /* 8795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 430*/ GIMT_Encode4(8857), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2168 //
3702 /* 8802 */ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3703 /* 8802 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3704 /* 8805 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3705 /* 8809 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3706 /* 8814 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3707 /* 8818 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
3708 /* 8823 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3709 /* 8826 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3710 /* 8830 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3711 /* 8835 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3712 /* 8838 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3713 /* 8841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3714 /* 8843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3715 /* 8846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3716 /* 8848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3717 /* 8851 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3718 /* 8856 */ // GIR_Coverage, 2168,
3719 /* 8856 */ GIR_EraseRootFromParent_Done,
3720 /* 8857 */ // Label 430: @8857
3721 /* 8857 */ GIM_Reject,
3722 /* 8858 */ // Label 426: @8858
3723 /* 8858 */ GIM_Reject,
3724 /* 8859 */ // Label 422: @8859
3725 /* 8859 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(9217),
3726 /* 8864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3727 /* 8868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 432*/ GIMT_Encode4(8886), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2146 //
3728 /* 8875 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3729 /* 8875 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3730 /* 8880 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3731 /* 8885 */ // GIR_Coverage, 2146,
3732 /* 8885 */ GIR_Done,
3733 /* 8886 */ // Label 432: @8886
3734 /* 8886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 433*/ GIMT_Encode4(8904), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2148 //
3735 /* 8893 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3736 /* 8893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3737 /* 8898 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3738 /* 8903 */ // GIR_Coverage, 2148,
3739 /* 8903 */ GIR_Done,
3740 /* 8904 */ // Label 433: @8904
3741 /* 8904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(8922), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2156 //
3742 /* 8911 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3743 /* 8911 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3744 /* 8916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3745 /* 8921 */ // GIR_Coverage, 2156,
3746 /* 8921 */ GIR_Done,
3747 /* 8922 */ // Label 434: @8922
3748 /* 8922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 435*/ GIMT_Encode4(8940), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2158 //
3749 /* 8929 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3750 /* 8929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3751 /* 8934 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3752 /* 8939 */ // GIR_Coverage, 2158,
3753 /* 8939 */ GIR_Done,
3754 /* 8940 */ // Label 435: @8940
3755 /* 8940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 436*/ GIMT_Encode4(9009), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2172 //
3756 /* 8947 */ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3757 /* 8947 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3758 /* 8950 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3759 /* 8954 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3760 /* 8959 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3761 /* 8963 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3762 /* 8968 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3763 /* 8971 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3764 /* 8975 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3765 /* 8980 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3766 /* 8983 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3767 /* 8993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3768 /* 8995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3769 /* 8998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3770 /* 9000 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3771 /* 9003 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3772 /* 9008 */ // GIR_Coverage, 2172,
3773 /* 9008 */ GIR_EraseRootFromParent_Done,
3774 /* 9009 */ // Label 436: @9009
3775 /* 9009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 437*/ GIMT_Encode4(9078), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2173 //
3776 /* 9016 */ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3777 /* 9016 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3778 /* 9019 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3779 /* 9023 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3780 /* 9028 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3781 /* 9032 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3782 /* 9037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3783 /* 9040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3784 /* 9044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3785 /* 9049 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3786 /* 9052 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3787 /* 9062 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3788 /* 9064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3789 /* 9067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3790 /* 9069 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3791 /* 9072 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3792 /* 9077 */ // GIR_Coverage, 2173,
3793 /* 9077 */ GIR_EraseRootFromParent_Done,
3794 /* 9078 */ // Label 437: @9078
3795 /* 9078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 438*/ GIMT_Encode4(9147), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2177 //
3796 /* 9085 */ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3797 /* 9085 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3798 /* 9088 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3799 /* 9092 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3800 /* 9097 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3801 /* 9101 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3802 /* 9106 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3803 /* 9109 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3804 /* 9113 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3805 /* 9118 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3806 /* 9121 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3807 /* 9131 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3808 /* 9133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3809 /* 9136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3810 /* 9138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3811 /* 9141 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3812 /* 9146 */ // GIR_Coverage, 2177,
3813 /* 9146 */ GIR_EraseRootFromParent_Done,
3814 /* 9147 */ // Label 438: @9147
3815 /* 9147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 439*/ GIMT_Encode4(9216), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2178 //
3816 /* 9154 */ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3817 /* 9154 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3818 /* 9157 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3819 /* 9161 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3820 /* 9166 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3821 /* 9170 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3822 /* 9175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3823 /* 9178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3824 /* 9182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3825 /* 9187 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3826 /* 9190 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3827 /* 9200 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3828 /* 9202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3829 /* 9205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3830 /* 9207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3831 /* 9210 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3832 /* 9215 */ // GIR_Coverage, 2178,
3833 /* 9215 */ GIR_EraseRootFromParent_Done,
3834 /* 9216 */ // Label 439: @9216
3835 /* 9216 */ GIM_Reject,
3836 /* 9217 */ // Label 431: @9217
3837 /* 9217 */ GIM_Reject,
3838 /* 9218 */ // Label 423: @9218
3839 /* 9218 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(9264),
3840 /* 9223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3841 /* 9227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 441*/ GIMT_Encode4(9245), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2129 //
3842 /* 9234 */ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3843 /* 9234 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3844 /* 9239 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3845 /* 9244 */ // GIR_Coverage, 2129,
3846 /* 9244 */ GIR_Done,
3847 /* 9245 */ // Label 441: @9245
3848 /* 9245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 442*/ GIMT_Encode4(9263), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2132 //
3849 /* 9252 */ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3850 /* 9252 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3851 /* 9257 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3852 /* 9262 */ // GIR_Coverage, 2132,
3853 /* 9262 */ GIR_Done,
3854 /* 9263 */ // Label 442: @9263
3855 /* 9263 */ GIM_Reject,
3856 /* 9264 */ // Label 440: @9264
3857 /* 9264 */ GIM_Reject,
3858 /* 9265 */ // Label 424: @9265
3859 /* 9265 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(9623),
3860 /* 9270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3861 /* 9274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 444*/ GIMT_Encode4(9292), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2147 //
3862 /* 9281 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3863 /* 9281 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3864 /* 9286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3865 /* 9291 */ // GIR_Coverage, 2147,
3866 /* 9291 */ GIR_Done,
3867 /* 9292 */ // Label 444: @9292
3868 /* 9292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 445*/ GIMT_Encode4(9310), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2149 //
3869 /* 9299 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3870 /* 9299 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3871 /* 9304 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3872 /* 9309 */ // GIR_Coverage, 2149,
3873 /* 9309 */ GIR_Done,
3874 /* 9310 */ // Label 445: @9310
3875 /* 9310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 446*/ GIMT_Encode4(9328), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2157 //
3876 /* 9317 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3877 /* 9317 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3878 /* 9322 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3879 /* 9327 */ // GIR_Coverage, 2157,
3880 /* 9327 */ GIR_Done,
3881 /* 9328 */ // Label 446: @9328
3882 /* 9328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 447*/ GIMT_Encode4(9346), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2159 //
3883 /* 9335 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3884 /* 9335 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3885 /* 9340 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3886 /* 9345 */ // GIR_Coverage, 2159,
3887 /* 9345 */ GIR_Done,
3888 /* 9346 */ // Label 447: @9346
3889 /* 9346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 448*/ GIMT_Encode4(9415), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2194 //
3890 /* 9353 */ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3891 /* 9353 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3892 /* 9356 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3893 /* 9360 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3894 /* 9365 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3895 /* 9369 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3896 /* 9374 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3897 /* 9377 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3898 /* 9381 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3899 /* 9386 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3900 /* 9389 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3901 /* 9399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3902 /* 9401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3903 /* 9404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3904 /* 9406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3905 /* 9409 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3906 /* 9414 */ // GIR_Coverage, 2194,
3907 /* 9414 */ GIR_EraseRootFromParent_Done,
3908 /* 9415 */ // Label 448: @9415
3909 /* 9415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 449*/ GIMT_Encode4(9484), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2195 //
3910 /* 9422 */ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3911 /* 9422 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3912 /* 9425 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3913 /* 9429 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3914 /* 9434 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3915 /* 9438 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3916 /* 9443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3917 /* 9446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3918 /* 9450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3919 /* 9455 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3920 /* 9458 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3921 /* 9468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3922 /* 9470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3923 /* 9473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3924 /* 9475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3925 /* 9478 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3926 /* 9483 */ // GIR_Coverage, 2195,
3927 /* 9483 */ GIR_EraseRootFromParent_Done,
3928 /* 9484 */ // Label 449: @9484
3929 /* 9484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 450*/ GIMT_Encode4(9553), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2199 //
3930 /* 9491 */ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3931 /* 9491 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3932 /* 9494 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3933 /* 9498 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3934 /* 9503 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3935 /* 9507 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3936 /* 9512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3937 /* 9515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3938 /* 9519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3939 /* 9524 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3940 /* 9527 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3941 /* 9537 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3942 /* 9539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3943 /* 9542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3944 /* 9544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3945 /* 9547 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3946 /* 9552 */ // GIR_Coverage, 2199,
3947 /* 9552 */ GIR_EraseRootFromParent_Done,
3948 /* 9553 */ // Label 450: @9553
3949 /* 9553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 451*/ GIMT_Encode4(9622), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2200 //
3950 /* 9560 */ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3951 /* 9560 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3952 /* 9563 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3953 /* 9567 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3954 /* 9572 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3955 /* 9576 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3956 /* 9581 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3957 /* 9584 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3958 /* 9588 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3959 /* 9593 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3960 /* 9596 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3961 /* 9606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3962 /* 9608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3963 /* 9611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3964 /* 9613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3965 /* 9616 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3966 /* 9621 */ // GIR_Coverage, 2200,
3967 /* 9621 */ GIR_EraseRootFromParent_Done,
3968 /* 9622 */ // Label 451: @9622
3969 /* 9622 */ GIM_Reject,
3970 /* 9623 */ // Label 443: @9623
3971 /* 9623 */ GIM_Reject,
3972 /* 9624 */ // Label 425: @9624
3973 /* 9624 */ GIM_Reject,
3974 /* 9625 */ // Label 350: @9625
3975 /* 9625 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 456*/ GIMT_Encode4(10658),
3976 /* 9636 */ /*GILLT_v16s8*//*Label 452*/ GIMT_Encode4(9656), GIMT_Encode4(0),
3977 /* 9644 */ /*GILLT_v8s16*//*Label 453*/ GIMT_Encode4(9921),
3978 /* 9648 */ /*GILLT_v4s32*//*Label 454*/ GIMT_Encode4(10252),
3979 /* 9652 */ /*GILLT_v2s64*//*Label 455*/ GIMT_Encode4(10611),
3980 /* 9656 */ // Label 452: @9656
3981 /* 9656 */ GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(9920),
3982 /* 9661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3983 /* 9665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 458*/ GIMT_Encode4(9683), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2150 //
3984 /* 9672 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3985 /* 9672 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3986 /* 9677 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3987 /* 9682 */ // GIR_Coverage, 2150,
3988 /* 9682 */ GIR_Done,
3989 /* 9683 */ // Label 458: @9683
3990 /* 9683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 459*/ GIMT_Encode4(9701), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2160 //
3991 /* 9690 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3992 /* 9690 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3993 /* 9695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3994 /* 9700 */ // GIR_Coverage, 2160,
3995 /* 9700 */ GIR_Done,
3996 /* 9701 */ // Label 459: @9701
3997 /* 9701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 460*/ GIMT_Encode4(9810), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2169 //
3998 /* 9708 */ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3999 /* 9708 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4000 /* 9711 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4001 /* 9715 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4002 /* 9720 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4003 /* 9724 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4004 /* 9729 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4005 /* 9732 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4006 /* 9736 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4007 /* 9741 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4008 /* 9744 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4009 /* 9747 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4010 /* 9749 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4011 /* 9752 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4012 /* 9756 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4013 /* 9761 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4014 /* 9764 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4015 /* 9769 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4016 /* 9772 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4017 /* 9776 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4018 /* 9781 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4019 /* 9784 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4020 /* 9794 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4021 /* 9796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4022 /* 9799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4023 /* 9801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4024 /* 9804 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4025 /* 9809 */ // GIR_Coverage, 2169,
4026 /* 9809 */ GIR_EraseRootFromParent_Done,
4027 /* 9810 */ // Label 460: @9810
4028 /* 9810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 461*/ GIMT_Encode4(9919), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2170 //
4029 /* 9817 */ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4030 /* 9817 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4031 /* 9820 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4032 /* 9824 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4033 /* 9829 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4034 /* 9833 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4035 /* 9838 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4036 /* 9841 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4037 /* 9845 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4038 /* 9850 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4039 /* 9853 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4040 /* 9856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4041 /* 9858 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4042 /* 9861 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4043 /* 9865 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4044 /* 9870 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4045 /* 9873 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4046 /* 9878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4047 /* 9881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4048 /* 9885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4049 /* 9890 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4050 /* 9893 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4051 /* 9903 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4052 /* 9905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4053 /* 9908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4054 /* 9910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4055 /* 9913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4056 /* 9918 */ // GIR_Coverage, 2170,
4057 /* 9918 */ GIR_EraseRootFromParent_Done,
4058 /* 9919 */ // Label 461: @9919
4059 /* 9919 */ GIM_Reject,
4060 /* 9920 */ // Label 457: @9920
4061 /* 9920 */ GIM_Reject,
4062 /* 9921 */ // Label 453: @9921
4063 /* 9921 */ GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(10251),
4064 /* 9926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4065 /* 9930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 463*/ GIMT_Encode4(9948), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2151 //
4066 /* 9937 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4067 /* 9937 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4068 /* 9942 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4069 /* 9947 */ // GIR_Coverage, 2151,
4070 /* 9947 */ GIR_Done,
4071 /* 9948 */ // Label 463: @9948
4072 /* 9948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(9966), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2153 //
4073 /* 9955 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4074 /* 9955 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4075 /* 9960 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4076 /* 9965 */ // GIR_Coverage, 2153,
4077 /* 9965 */ GIR_Done,
4078 /* 9966 */ // Label 464: @9966
4079 /* 9966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(9984), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2161 //
4080 /* 9973 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
4081 /* 9973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4082 /* 9978 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4083 /* 9983 */ // GIR_Coverage, 2161,
4084 /* 9983 */ GIR_Done,
4085 /* 9984 */ // Label 465: @9984
4086 /* 9984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(10002), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2163 //
4087 /* 9991 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
4088 /* 9991 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4089 /* 9996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4090 /* 10001 */ // GIR_Coverage, 2163,
4091 /* 10001 */ GIR_Done,
4092 /* 10002 */ // Label 466: @10002
4093 /* 10002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(10064), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2174 //
4094 /* 10009 */ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4095 /* 10009 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4096 /* 10012 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4097 /* 10016 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4098 /* 10021 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4099 /* 10025 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4100 /* 10030 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4101 /* 10033 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4102 /* 10037 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4103 /* 10042 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4104 /* 10045 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4105 /* 10048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4106 /* 10050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4107 /* 10053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4108 /* 10055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4109 /* 10058 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4110 /* 10063 */ // GIR_Coverage, 2174,
4111 /* 10063 */ GIR_EraseRootFromParent_Done,
4112 /* 10064 */ // Label 467: @10064
4113 /* 10064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 468*/ GIMT_Encode4(10126), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2175 //
4114 /* 10071 */ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4115 /* 10071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4116 /* 10074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4117 /* 10078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4118 /* 10083 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4119 /* 10087 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4120 /* 10092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4121 /* 10095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4122 /* 10099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4123 /* 10104 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4124 /* 10107 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4125 /* 10110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4126 /* 10112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4127 /* 10115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4128 /* 10117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4129 /* 10120 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4130 /* 10125 */ // GIR_Coverage, 2175,
4131 /* 10125 */ GIR_EraseRootFromParent_Done,
4132 /* 10126 */ // Label 468: @10126
4133 /* 10126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(10188), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2179 //
4134 /* 10133 */ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4135 /* 10133 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4136 /* 10136 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4137 /* 10140 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4138 /* 10145 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4139 /* 10149 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4140 /* 10154 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4141 /* 10157 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4142 /* 10161 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4143 /* 10166 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4144 /* 10169 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4145 /* 10172 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4146 /* 10174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4147 /* 10177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4148 /* 10179 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4149 /* 10182 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4150 /* 10187 */ // GIR_Coverage, 2179,
4151 /* 10187 */ GIR_EraseRootFromParent_Done,
4152 /* 10188 */ // Label 469: @10188
4153 /* 10188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(10250), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2180 //
4154 /* 10195 */ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
4155 /* 10195 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4156 /* 10198 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4157 /* 10202 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4158 /* 10207 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4159 /* 10211 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4160 /* 10216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4161 /* 10219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4162 /* 10223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4163 /* 10228 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4164 /* 10231 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4165 /* 10234 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4166 /* 10236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4167 /* 10239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4168 /* 10241 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4169 /* 10244 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4170 /* 10249 */ // GIR_Coverage, 2180,
4171 /* 10249 */ GIR_EraseRootFromParent_Done,
4172 /* 10250 */ // Label 470: @10250
4173 /* 10250 */ GIM_Reject,
4174 /* 10251 */ // Label 462: @10251
4175 /* 10251 */ GIM_Reject,
4176 /* 10252 */ // Label 454: @10252
4177 /* 10252 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(10610),
4178 /* 10257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4179 /* 10261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(10279), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2152 //
4180 /* 10268 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4181 /* 10268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4182 /* 10273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4183 /* 10278 */ // GIR_Coverage, 2152,
4184 /* 10278 */ GIR_Done,
4185 /* 10279 */ // Label 472: @10279
4186 /* 10279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(10297), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2154 //
4187 /* 10286 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4188 /* 10286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4189 /* 10291 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4190 /* 10296 */ // GIR_Coverage, 2154,
4191 /* 10296 */ GIR_Done,
4192 /* 10297 */ // Label 473: @10297
4193 /* 10297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(10315), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2162 //
4194 /* 10304 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
4195 /* 10304 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4196 /* 10309 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4197 /* 10314 */ // GIR_Coverage, 2162,
4198 /* 10314 */ GIR_Done,
4199 /* 10315 */ // Label 474: @10315
4200 /* 10315 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(10333), GIMT_Encode2(GIFBS_HasMSA_IsLE), // Rule ID 2164 //
4201 /* 10322 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
4202 /* 10322 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4203 /* 10327 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4204 /* 10332 */ // GIR_Coverage, 2164,
4205 /* 10332 */ GIR_Done,
4206 /* 10333 */ // Label 475: @10333
4207 /* 10333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(10402), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2184 //
4208 /* 10340 */ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4209 /* 10340 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4210 /* 10343 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4211 /* 10347 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4212 /* 10352 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4213 /* 10356 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4214 /* 10361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4215 /* 10364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4216 /* 10368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4217 /* 10373 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4218 /* 10376 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4219 /* 10386 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4220 /* 10388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4221 /* 10391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4222 /* 10393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4223 /* 10396 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4224 /* 10401 */ // GIR_Coverage, 2184,
4225 /* 10401 */ GIR_EraseRootFromParent_Done,
4226 /* 10402 */ // Label 476: @10402
4227 /* 10402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 477*/ GIMT_Encode4(10471), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2185 //
4228 /* 10409 */ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4229 /* 10409 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4230 /* 10412 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4231 /* 10416 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4232 /* 10421 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4233 /* 10425 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4234 /* 10430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4235 /* 10433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4236 /* 10437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4237 /* 10442 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4238 /* 10445 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4239 /* 10455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4240 /* 10457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4241 /* 10460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4242 /* 10462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4243 /* 10465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4244 /* 10470 */ // GIR_Coverage, 2185,
4245 /* 10470 */ GIR_EraseRootFromParent_Done,
4246 /* 10471 */ // Label 477: @10471
4247 /* 10471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 478*/ GIMT_Encode4(10540), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2189 //
4248 /* 10478 */ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4249 /* 10478 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4250 /* 10481 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4251 /* 10485 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4252 /* 10490 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4253 /* 10494 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4254 /* 10499 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4255 /* 10502 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4256 /* 10506 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4257 /* 10511 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4258 /* 10514 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4259 /* 10524 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4260 /* 10526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4261 /* 10529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4262 /* 10531 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4263 /* 10534 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4264 /* 10539 */ // GIR_Coverage, 2189,
4265 /* 10539 */ GIR_EraseRootFromParent_Done,
4266 /* 10540 */ // Label 478: @10540
4267 /* 10540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(10609), GIMT_Encode2(GIFBS_HasMSA_IsBE), // Rule ID 2190 //
4268 /* 10547 */ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
4269 /* 10547 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4270 /* 10550 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4271 /* 10554 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4272 /* 10559 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4273 /* 10563 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
4274 /* 10568 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4275 /* 10571 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4276 /* 10575 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4277 /* 10580 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4278 /* 10583 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4279 /* 10593 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4280 /* 10595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4281 /* 10598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4282 /* 10600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4283 /* 10603 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4284 /* 10608 */ // GIR_Coverage, 2190,
4285 /* 10608 */ GIR_EraseRootFromParent_Done,
4286 /* 10609 */ // Label 479: @10609
4287 /* 10609 */ GIM_Reject,
4288 /* 10610 */ // Label 471: @10610
4289 /* 10610 */ GIM_Reject,
4290 /* 10611 */ // Label 455: @10611
4291 /* 10611 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(10657),
4292 /* 10616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
4293 /* 10620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 481*/ GIMT_Encode4(10638), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2130 //
4294 /* 10627 */ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
4295 /* 10627 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4296 /* 10632 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4297 /* 10637 */ // GIR_Coverage, 2130,
4298 /* 10637 */ GIR_Done,
4299 /* 10638 */ // Label 481: @10638
4300 /* 10638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(10656), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2133 //
4301 /* 10645 */ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
4302 /* 10645 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4303 /* 10650 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
4304 /* 10655 */ // GIR_Coverage, 2133,
4305 /* 10655 */ GIR_Done,
4306 /* 10656 */ // Label 482: @10656
4307 /* 10656 */ GIM_Reject,
4308 /* 10657 */ // Label 480: @10657
4309 /* 10657 */ GIM_Reject,
4310 /* 10658 */ // Label 456: @10658
4311 /* 10658 */ GIM_Reject,
4312 /* 10659 */ // Label 351: @10659
4313 /* 10659 */ GIM_Reject,
4314 /* 10660 */ // Label 13: @10660
4315 /* 10660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(10723), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2119 //
4316 /* 10667 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4317 /* 10670 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4318 /* 10673 */ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4319 /* 10677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4320 /* 10681 */ // MIs[0] Operand 1
4321 /* 10681 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4322 /* 10685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4323 /* 10689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4324 /* 10693 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4325 /* 10697 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4326 /* 10701 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4327 /* 10703 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4328 /* 10703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4329 /* 10706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4330 /* 10708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4331 /* 10712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4332 /* 10716 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4333 /* 10721 */ GIR_RootConstrainSelectedInstOperands,
4334 /* 10722 */ // GIR_Coverage, 2119,
4335 /* 10722 */ GIR_EraseRootFromParent_Done,
4336 /* 10723 */ // Label 483: @10723
4337 /* 10723 */ GIM_Reject,
4338 /* 10724 */ // Label 14: @10724
4339 /* 10724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(10790), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2118 //
4340 /* 10731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4341 /* 10734 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4342 /* 10737 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4343 /* 10744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4344 /* 10748 */ // MIs[0] Operand 1
4345 /* 10748 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4346 /* 10752 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4347 /* 10756 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4348 /* 10760 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4349 /* 10764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4350 /* 10768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4351 /* 10770 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4352 /* 10770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4353 /* 10773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4354 /* 10775 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4355 /* 10779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4356 /* 10783 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4357 /* 10788 */ GIR_RootConstrainSelectedInstOperands,
4358 /* 10789 */ // GIR_Coverage, 2118,
4359 /* 10789 */ GIR_EraseRootFromParent_Done,
4360 /* 10790 */ // Label 484: @10790
4361 /* 10790 */ GIM_Reject,
4362 /* 10791 */ // Label 15: @10791
4363 /* 10791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(10857), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2117 //
4364 /* 10798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4365 /* 10801 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4366 /* 10804 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4367 /* 10811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4368 /* 10815 */ // MIs[0] Operand 1
4369 /* 10815 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4370 /* 10819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4371 /* 10823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4372 /* 10827 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4373 /* 10831 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4374 /* 10835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4375 /* 10837 */ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4376 /* 10837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4377 /* 10840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4378 /* 10842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4379 /* 10846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4380 /* 10850 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4381 /* 10855 */ GIR_RootConstrainSelectedInstOperands,
4382 /* 10856 */ // GIR_Coverage, 2117,
4383 /* 10856 */ GIR_EraseRootFromParent_Done,
4384 /* 10857 */ // Label 485: @10857
4385 /* 10857 */ GIM_Reject,
4386 /* 10858 */ // Label 16: @10858
4387 /* 10858 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 488*/ GIMT_Encode4(11045),
4388 /* 10869 */ /*GILLT_s32*//*Label 486*/ GIMT_Encode4(10877),
4389 /* 10873 */ /*GILLT_s64*//*Label 487*/ GIMT_Encode4(11001),
4390 /* 10877 */ // Label 486: @10877
4391 /* 10877 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(11000),
4392 /* 10882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4393 /* 10885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
4394 /* 10888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(10925), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 25 //
4395 /* 10895 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4396 /* 10902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4397 /* 10906 */ // MIs[0] ptr
4398 /* 10906 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4399 /* 10910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4400 /* 10914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4401 /* 10918 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>> => (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4402 /* 10918 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
4403 /* 10923 */ GIR_RootConstrainSelectedInstOperands,
4404 /* 10924 */ // GIR_Coverage, 25,
4405 /* 10924 */ GIR_Done,
4406 /* 10925 */ // Label 490: @10925
4407 /* 10925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(10962), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 26 //
4408 /* 10932 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4409 /* 10939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4410 /* 10943 */ // MIs[0] ptr
4411 /* 10943 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4412 /* 10947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4413 /* 10951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4414 /* 10955 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>> => (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4415 /* 10955 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
4416 /* 10960 */ GIR_RootConstrainSelectedInstOperands,
4417 /* 10961 */ // GIR_Coverage, 26,
4418 /* 10961 */ GIR_Done,
4419 /* 10962 */ // Label 491: @10962
4420 /* 10962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 492*/ GIMT_Encode4(10999), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 27 //
4421 /* 10969 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4422 /* 10976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4423 /* 10980 */ // MIs[0] ptr
4424 /* 10980 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4425 /* 10984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4426 /* 10988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4427 /* 10992 */ // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>> => (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
4428 /* 10992 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
4429 /* 10997 */ GIR_RootConstrainSelectedInstOperands,
4430 /* 10998 */ // GIR_Coverage, 27,
4431 /* 10998 */ GIR_Done,
4432 /* 10999 */ // Label 492: @10999
4433 /* 10999 */ GIM_Reject,
4434 /* 11000 */ // Label 489: @11000
4435 /* 11000 */ GIM_Reject,
4436 /* 11001 */ // Label 487: @11001
4437 /* 11001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 493*/ GIMT_Encode4(11044), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 219 //
4438 /* 11008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4439 /* 11011 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
4440 /* 11014 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4441 /* 11021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4442 /* 11025 */ // MIs[0] ptr
4443 /* 11025 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4444 /* 11029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4445 /* 11033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4446 /* 11037 */ // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>> => (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
4447 /* 11037 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
4448 /* 11042 */ GIR_RootConstrainSelectedInstOperands,
4449 /* 11043 */ // GIR_Coverage, 219,
4450 /* 11043 */ GIR_Done,
4451 /* 11044 */ // Label 493: @11044
4452 /* 11044 */ GIM_Reject,
4453 /* 11045 */ // Label 488: @11045
4454 /* 11045 */ GIM_Reject,
4455 /* 11046 */ // Label 17: @11046
4456 /* 11046 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 496*/ GIMT_Encode4(11211),
4457 /* 11057 */ /*GILLT_s32*//*Label 494*/ GIMT_Encode4(11065),
4458 /* 11061 */ /*GILLT_s64*//*Label 495*/ GIMT_Encode4(11174),
4459 /* 11065 */ // Label 494: @11065
4460 /* 11065 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(11173),
4461 /* 11070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4462 /* 11073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(11106), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 22 //
4463 /* 11080 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4464 /* 11087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4465 /* 11091 */ // MIs[0] ptr
4466 /* 11091 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4467 /* 11095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4468 /* 11099 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>> => (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4469 /* 11099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
4470 /* 11104 */ GIR_RootConstrainSelectedInstOperands,
4471 /* 11105 */ // GIR_Coverage, 22,
4472 /* 11105 */ GIR_Done,
4473 /* 11106 */ // Label 498: @11106
4474 /* 11106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 499*/ GIMT_Encode4(11139), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 23 //
4475 /* 11113 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4476 /* 11120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4477 /* 11124 */ // MIs[0] ptr
4478 /* 11124 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4479 /* 11128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4480 /* 11132 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>> => (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4481 /* 11132 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
4482 /* 11137 */ GIR_RootConstrainSelectedInstOperands,
4483 /* 11138 */ // GIR_Coverage, 23,
4484 /* 11138 */ GIR_Done,
4485 /* 11139 */ // Label 499: @11139
4486 /* 11139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 500*/ GIMT_Encode4(11172), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 24 //
4487 /* 11146 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4488 /* 11153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4489 /* 11157 */ // MIs[0] ptr
4490 /* 11157 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4491 /* 11161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4492 /* 11165 */ // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>> => (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4493 /* 11165 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
4494 /* 11170 */ GIR_RootConstrainSelectedInstOperands,
4495 /* 11171 */ // GIR_Coverage, 24,
4496 /* 11171 */ GIR_Done,
4497 /* 11172 */ // Label 500: @11172
4498 /* 11172 */ GIM_Reject,
4499 /* 11173 */ // Label 497: @11173
4500 /* 11173 */ GIM_Reject,
4501 /* 11174 */ // Label 495: @11174
4502 /* 11174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 501*/ GIMT_Encode4(11210), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 218 //
4503 /* 11181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4504 /* 11184 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4505 /* 11191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4506 /* 11195 */ // MIs[0] ptr
4507 /* 11195 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4508 /* 11199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4509 /* 11203 */ // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>> => (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4510 /* 11203 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
4511 /* 11208 */ GIR_RootConstrainSelectedInstOperands,
4512 /* 11209 */ // GIR_Coverage, 218,
4513 /* 11209 */ GIR_Done,
4514 /* 11210 */ // Label 501: @11210
4515 /* 11210 */ GIM_Reject,
4516 /* 11211 */ // Label 496: @11211
4517 /* 11211 */ GIM_Reject,
4518 /* 11212 */ // Label 18: @11212
4519 /* 11212 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 504*/ GIMT_Encode4(11377),
4520 /* 11223 */ /*GILLT_s32*//*Label 502*/ GIMT_Encode4(11231),
4521 /* 11227 */ /*GILLT_s64*//*Label 503*/ GIMT_Encode4(11340),
4522 /* 11231 */ // Label 502: @11231
4523 /* 11231 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(11339),
4524 /* 11236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4525 /* 11239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 506*/ GIMT_Encode4(11272), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 4 //
4526 /* 11246 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4527 /* 11253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4528 /* 11257 */ // MIs[0] ptr
4529 /* 11257 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4530 /* 11261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4531 /* 11265 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>> => (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4532 /* 11265 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
4533 /* 11270 */ GIR_RootConstrainSelectedInstOperands,
4534 /* 11271 */ // GIR_Coverage, 4,
4535 /* 11271 */ GIR_Done,
4536 /* 11272 */ // Label 506: @11272
4537 /* 11272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 507*/ GIMT_Encode4(11305), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 5 //
4538 /* 11279 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4539 /* 11286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4540 /* 11290 */ // MIs[0] ptr
4541 /* 11290 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4542 /* 11294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4543 /* 11298 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>> => (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4544 /* 11298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
4545 /* 11303 */ GIR_RootConstrainSelectedInstOperands,
4546 /* 11304 */ // GIR_Coverage, 5,
4547 /* 11304 */ GIR_Done,
4548 /* 11305 */ // Label 507: @11305
4549 /* 11305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 508*/ GIMT_Encode4(11338), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 6 //
4550 /* 11312 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4551 /* 11319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4552 /* 11323 */ // MIs[0] ptr
4553 /* 11323 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4554 /* 11327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4555 /* 11331 */ // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>> => (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4556 /* 11331 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
4557 /* 11336 */ GIR_RootConstrainSelectedInstOperands,
4558 /* 11337 */ // GIR_Coverage, 6,
4559 /* 11337 */ GIR_Done,
4560 /* 11338 */ // Label 508: @11338
4561 /* 11338 */ GIM_Reject,
4562 /* 11339 */ // Label 505: @11339
4563 /* 11339 */ GIM_Reject,
4564 /* 11340 */ // Label 503: @11340
4565 /* 11340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 509*/ GIMT_Encode4(11376), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 212 //
4566 /* 11347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4567 /* 11350 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4568 /* 11357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4569 /* 11361 */ // MIs[0] ptr
4570 /* 11361 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4571 /* 11365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4572 /* 11369 */ // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>> => (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4573 /* 11369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
4574 /* 11374 */ GIR_RootConstrainSelectedInstOperands,
4575 /* 11375 */ // GIR_Coverage, 212,
4576 /* 11375 */ GIR_Done,
4577 /* 11376 */ // Label 509: @11376
4578 /* 11376 */ GIM_Reject,
4579 /* 11377 */ // Label 504: @11377
4580 /* 11377 */ GIM_Reject,
4581 /* 11378 */ // Label 19: @11378
4582 /* 11378 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 512*/ GIMT_Encode4(11543),
4583 /* 11389 */ /*GILLT_s32*//*Label 510*/ GIMT_Encode4(11397),
4584 /* 11393 */ /*GILLT_s64*//*Label 511*/ GIMT_Encode4(11506),
4585 /* 11397 */ // Label 510: @11397
4586 /* 11397 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(11505),
4587 /* 11402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4588 /* 11405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 514*/ GIMT_Encode4(11438), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 7 //
4589 /* 11412 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4590 /* 11419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4591 /* 11423 */ // MIs[0] ptr
4592 /* 11423 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4593 /* 11427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4594 /* 11431 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>> => (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4595 /* 11431 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
4596 /* 11436 */ GIR_RootConstrainSelectedInstOperands,
4597 /* 11437 */ // GIR_Coverage, 7,
4598 /* 11437 */ GIR_Done,
4599 /* 11438 */ // Label 514: @11438
4600 /* 11438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 515*/ GIMT_Encode4(11471), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 8 //
4601 /* 11445 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4602 /* 11452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4603 /* 11456 */ // MIs[0] ptr
4604 /* 11456 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4605 /* 11460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4606 /* 11464 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>> => (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4607 /* 11464 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
4608 /* 11469 */ GIR_RootConstrainSelectedInstOperands,
4609 /* 11470 */ // GIR_Coverage, 8,
4610 /* 11470 */ GIR_Done,
4611 /* 11471 */ // Label 515: @11471
4612 /* 11471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 516*/ GIMT_Encode4(11504), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 9 //
4613 /* 11478 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4614 /* 11485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4615 /* 11489 */ // MIs[0] ptr
4616 /* 11489 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4617 /* 11493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4618 /* 11497 */ // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>> => (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4619 /* 11497 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
4620 /* 11502 */ GIR_RootConstrainSelectedInstOperands,
4621 /* 11503 */ // GIR_Coverage, 9,
4622 /* 11503 */ GIR_Done,
4623 /* 11504 */ // Label 516: @11504
4624 /* 11504 */ GIM_Reject,
4625 /* 11505 */ // Label 513: @11505
4626 /* 11505 */ GIM_Reject,
4627 /* 11506 */ // Label 511: @11506
4628 /* 11506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 517*/ GIMT_Encode4(11542), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 213 //
4629 /* 11513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4630 /* 11516 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4631 /* 11523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4632 /* 11527 */ // MIs[0] ptr
4633 /* 11527 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4634 /* 11531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4635 /* 11535 */ // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>> => (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4636 /* 11535 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
4637 /* 11540 */ GIR_RootConstrainSelectedInstOperands,
4638 /* 11541 */ // GIR_Coverage, 213,
4639 /* 11541 */ GIR_Done,
4640 /* 11542 */ // Label 517: @11542
4641 /* 11542 */ GIM_Reject,
4642 /* 11543 */ // Label 512: @11543
4643 /* 11543 */ GIM_Reject,
4644 /* 11544 */ // Label 20: @11544
4645 /* 11544 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 520*/ GIMT_Encode4(11709),
4646 /* 11555 */ /*GILLT_s32*//*Label 518*/ GIMT_Encode4(11563),
4647 /* 11559 */ /*GILLT_s64*//*Label 519*/ GIMT_Encode4(11672),
4648 /* 11563 */ // Label 518: @11563
4649 /* 11563 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(11671),
4650 /* 11568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4651 /* 11571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 522*/ GIMT_Encode4(11604), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 10 //
4652 /* 11578 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4653 /* 11585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4654 /* 11589 */ // MIs[0] ptr
4655 /* 11589 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4656 /* 11593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4657 /* 11597 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>> => (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4658 /* 11597 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
4659 /* 11602 */ GIR_RootConstrainSelectedInstOperands,
4660 /* 11603 */ // GIR_Coverage, 10,
4661 /* 11603 */ GIR_Done,
4662 /* 11604 */ // Label 522: @11604
4663 /* 11604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 523*/ GIMT_Encode4(11637), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 11 //
4664 /* 11611 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4665 /* 11618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4666 /* 11622 */ // MIs[0] ptr
4667 /* 11622 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4668 /* 11626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4669 /* 11630 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>> => (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4670 /* 11630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
4671 /* 11635 */ GIR_RootConstrainSelectedInstOperands,
4672 /* 11636 */ // GIR_Coverage, 11,
4673 /* 11636 */ GIR_Done,
4674 /* 11637 */ // Label 523: @11637
4675 /* 11637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 524*/ GIMT_Encode4(11670), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 12 //
4676 /* 11644 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4677 /* 11651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4678 /* 11655 */ // MIs[0] ptr
4679 /* 11655 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4680 /* 11659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4681 /* 11663 */ // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>> => (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4682 /* 11663 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
4683 /* 11668 */ GIR_RootConstrainSelectedInstOperands,
4684 /* 11669 */ // GIR_Coverage, 12,
4685 /* 11669 */ GIR_Done,
4686 /* 11670 */ // Label 524: @11670
4687 /* 11670 */ GIM_Reject,
4688 /* 11671 */ // Label 521: @11671
4689 /* 11671 */ GIM_Reject,
4690 /* 11672 */ // Label 519: @11672
4691 /* 11672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 525*/ GIMT_Encode4(11708), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 214 //
4692 /* 11679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4693 /* 11682 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4694 /* 11689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4695 /* 11693 */ // MIs[0] ptr
4696 /* 11693 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4697 /* 11697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4698 /* 11701 */ // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>> => (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4699 /* 11701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
4700 /* 11706 */ GIR_RootConstrainSelectedInstOperands,
4701 /* 11707 */ // GIR_Coverage, 214,
4702 /* 11707 */ GIR_Done,
4703 /* 11708 */ // Label 525: @11708
4704 /* 11708 */ GIM_Reject,
4705 /* 11709 */ // Label 520: @11709
4706 /* 11709 */ GIM_Reject,
4707 /* 11710 */ // Label 21: @11710
4708 /* 11710 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 528*/ GIMT_Encode4(11875),
4709 /* 11721 */ /*GILLT_s32*//*Label 526*/ GIMT_Encode4(11729),
4710 /* 11725 */ /*GILLT_s64*//*Label 527*/ GIMT_Encode4(11838),
4711 /* 11729 */ // Label 526: @11729
4712 /* 11729 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(11837),
4713 /* 11734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4714 /* 11737 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(11770), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 19 //
4715 /* 11744 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4716 /* 11751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4717 /* 11755 */ // MIs[0] ptr
4718 /* 11755 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4719 /* 11759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4720 /* 11763 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>> => (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4721 /* 11763 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
4722 /* 11768 */ GIR_RootConstrainSelectedInstOperands,
4723 /* 11769 */ // GIR_Coverage, 19,
4724 /* 11769 */ GIR_Done,
4725 /* 11770 */ // Label 530: @11770
4726 /* 11770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(11803), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 20 //
4727 /* 11777 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4728 /* 11784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4729 /* 11788 */ // MIs[0] ptr
4730 /* 11788 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4731 /* 11792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4732 /* 11796 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>> => (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4733 /* 11796 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
4734 /* 11801 */ GIR_RootConstrainSelectedInstOperands,
4735 /* 11802 */ // GIR_Coverage, 20,
4736 /* 11802 */ GIR_Done,
4737 /* 11803 */ // Label 531: @11803
4738 /* 11803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 532*/ GIMT_Encode4(11836), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 21 //
4739 /* 11810 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4740 /* 11817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4741 /* 11821 */ // MIs[0] ptr
4742 /* 11821 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4743 /* 11825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4744 /* 11829 */ // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>> => (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4745 /* 11829 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
4746 /* 11834 */ GIR_RootConstrainSelectedInstOperands,
4747 /* 11835 */ // GIR_Coverage, 21,
4748 /* 11835 */ GIR_Done,
4749 /* 11836 */ // Label 532: @11836
4750 /* 11836 */ GIM_Reject,
4751 /* 11837 */ // Label 529: @11837
4752 /* 11837 */ GIM_Reject,
4753 /* 11838 */ // Label 527: @11838
4754 /* 11838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 533*/ GIMT_Encode4(11874), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 217 //
4755 /* 11845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4756 /* 11848 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4757 /* 11855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4758 /* 11859 */ // MIs[0] ptr
4759 /* 11859 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4760 /* 11863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4761 /* 11867 */ // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>> => (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4762 /* 11867 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
4763 /* 11872 */ GIR_RootConstrainSelectedInstOperands,
4764 /* 11873 */ // GIR_Coverage, 217,
4765 /* 11873 */ GIR_Done,
4766 /* 11874 */ // Label 533: @11874
4767 /* 11874 */ GIM_Reject,
4768 /* 11875 */ // Label 528: @11875
4769 /* 11875 */ GIM_Reject,
4770 /* 11876 */ // Label 22: @11876
4771 /* 11876 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 536*/ GIMT_Encode4(12041),
4772 /* 11887 */ /*GILLT_s32*//*Label 534*/ GIMT_Encode4(11895),
4773 /* 11891 */ /*GILLT_s64*//*Label 535*/ GIMT_Encode4(12004),
4774 /* 11895 */ // Label 534: @11895
4775 /* 11895 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(12003),
4776 /* 11900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4777 /* 11903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(11936), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 13 //
4778 /* 11910 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4779 /* 11917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4780 /* 11921 */ // MIs[0] ptr
4781 /* 11921 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4782 /* 11925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4783 /* 11929 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>> => (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4784 /* 11929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
4785 /* 11934 */ GIR_RootConstrainSelectedInstOperands,
4786 /* 11935 */ // GIR_Coverage, 13,
4787 /* 11935 */ GIR_Done,
4788 /* 11936 */ // Label 538: @11936
4789 /* 11936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(11969), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 14 //
4790 /* 11943 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4791 /* 11950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4792 /* 11954 */ // MIs[0] ptr
4793 /* 11954 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4794 /* 11958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4795 /* 11962 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>> => (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4796 /* 11962 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
4797 /* 11967 */ GIR_RootConstrainSelectedInstOperands,
4798 /* 11968 */ // GIR_Coverage, 14,
4799 /* 11968 */ GIR_Done,
4800 /* 11969 */ // Label 539: @11969
4801 /* 11969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 540*/ GIMT_Encode4(12002), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 15 //
4802 /* 11976 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4803 /* 11983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4804 /* 11987 */ // MIs[0] ptr
4805 /* 11987 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4806 /* 11991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4807 /* 11995 */ // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>> => (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4808 /* 11995 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
4809 /* 12000 */ GIR_RootConstrainSelectedInstOperands,
4810 /* 12001 */ // GIR_Coverage, 15,
4811 /* 12001 */ GIR_Done,
4812 /* 12002 */ // Label 540: @12002
4813 /* 12002 */ GIM_Reject,
4814 /* 12003 */ // Label 537: @12003
4815 /* 12003 */ GIM_Reject,
4816 /* 12004 */ // Label 535: @12004
4817 /* 12004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 541*/ GIMT_Encode4(12040), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 215 //
4818 /* 12011 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4819 /* 12014 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4820 /* 12021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4821 /* 12025 */ // MIs[0] ptr
4822 /* 12025 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4823 /* 12029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4824 /* 12033 */ // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>> => (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4825 /* 12033 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
4826 /* 12038 */ GIR_RootConstrainSelectedInstOperands,
4827 /* 12039 */ // GIR_Coverage, 215,
4828 /* 12039 */ GIR_Done,
4829 /* 12040 */ // Label 541: @12040
4830 /* 12040 */ GIM_Reject,
4831 /* 12041 */ // Label 536: @12041
4832 /* 12041 */ GIM_Reject,
4833 /* 12042 */ // Label 23: @12042
4834 /* 12042 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 544*/ GIMT_Encode4(12207),
4835 /* 12053 */ /*GILLT_s32*//*Label 542*/ GIMT_Encode4(12061),
4836 /* 12057 */ /*GILLT_s64*//*Label 543*/ GIMT_Encode4(12170),
4837 /* 12061 */ // Label 542: @12061
4838 /* 12061 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(12169),
4839 /* 12066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4840 /* 12069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(12102), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 16 //
4841 /* 12076 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4842 /* 12083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4843 /* 12087 */ // MIs[0] ptr
4844 /* 12087 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4845 /* 12091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4846 /* 12095 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>> => (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4847 /* 12095 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
4848 /* 12100 */ GIR_RootConstrainSelectedInstOperands,
4849 /* 12101 */ // GIR_Coverage, 16,
4850 /* 12101 */ GIR_Done,
4851 /* 12102 */ // Label 546: @12102
4852 /* 12102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(12135), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 17 //
4853 /* 12109 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4854 /* 12116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4855 /* 12120 */ // MIs[0] ptr
4856 /* 12120 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4857 /* 12124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4858 /* 12128 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>> => (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4859 /* 12128 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
4860 /* 12133 */ GIR_RootConstrainSelectedInstOperands,
4861 /* 12134 */ // GIR_Coverage, 17,
4862 /* 12134 */ GIR_Done,
4863 /* 12135 */ // Label 547: @12135
4864 /* 12135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 548*/ GIMT_Encode4(12168), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 18 //
4865 /* 12142 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4866 /* 12149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4867 /* 12153 */ // MIs[0] ptr
4868 /* 12153 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4869 /* 12157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4870 /* 12161 */ // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>> => (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4871 /* 12161 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
4872 /* 12166 */ GIR_RootConstrainSelectedInstOperands,
4873 /* 12167 */ // GIR_Coverage, 18,
4874 /* 12167 */ GIR_Done,
4875 /* 12168 */ // Label 548: @12168
4876 /* 12168 */ GIM_Reject,
4877 /* 12169 */ // Label 545: @12169
4878 /* 12169 */ GIM_Reject,
4879 /* 12170 */ // Label 543: @12170
4880 /* 12170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 549*/ GIMT_Encode4(12206), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 216 //
4881 /* 12177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4882 /* 12180 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4883 /* 12187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4884 /* 12191 */ // MIs[0] ptr
4885 /* 12191 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4886 /* 12195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4887 /* 12199 */ // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>> => (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4888 /* 12199 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
4889 /* 12204 */ GIR_RootConstrainSelectedInstOperands,
4890 /* 12205 */ // GIR_Coverage, 216,
4891 /* 12205 */ GIR_Done,
4892 /* 12206 */ // Label 549: @12206
4893 /* 12206 */ GIM_Reject,
4894 /* 12207 */ // Label 544: @12207
4895 /* 12207 */ GIM_Reject,
4896 /* 12208 */ // Label 24: @12208
4897 /* 12208 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 552*/ GIMT_Encode4(12373),
4898 /* 12219 */ /*GILLT_s32*//*Label 550*/ GIMT_Encode4(12227),
4899 /* 12223 */ /*GILLT_s64*//*Label 551*/ GIMT_Encode4(12336),
4900 /* 12227 */ // Label 550: @12227
4901 /* 12227 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(12335),
4902 /* 12232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4903 /* 12235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(12268), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 31 //
4904 /* 12242 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4905 /* 12249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4906 /* 12253 */ // MIs[0] ptr
4907 /* 12253 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4908 /* 12257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4909 /* 12261 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>> => (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4910 /* 12261 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
4911 /* 12266 */ GIR_RootConstrainSelectedInstOperands,
4912 /* 12267 */ // GIR_Coverage, 31,
4913 /* 12267 */ GIR_Done,
4914 /* 12268 */ // Label 554: @12268
4915 /* 12268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 555*/ GIMT_Encode4(12301), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 32 //
4916 /* 12275 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4917 /* 12282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4918 /* 12286 */ // MIs[0] ptr
4919 /* 12286 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4920 /* 12290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4921 /* 12294 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>> => (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4922 /* 12294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
4923 /* 12299 */ GIR_RootConstrainSelectedInstOperands,
4924 /* 12300 */ // GIR_Coverage, 32,
4925 /* 12300 */ GIR_Done,
4926 /* 12301 */ // Label 555: @12301
4927 /* 12301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 556*/ GIMT_Encode4(12334), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 33 //
4928 /* 12308 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4929 /* 12315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4930 /* 12319 */ // MIs[0] ptr
4931 /* 12319 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4932 /* 12323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4933 /* 12327 */ // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>> => (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4934 /* 12327 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
4935 /* 12332 */ GIR_RootConstrainSelectedInstOperands,
4936 /* 12333 */ // GIR_Coverage, 33,
4937 /* 12333 */ GIR_Done,
4938 /* 12334 */ // Label 556: @12334
4939 /* 12334 */ GIM_Reject,
4940 /* 12335 */ // Label 553: @12335
4941 /* 12335 */ GIM_Reject,
4942 /* 12336 */ // Label 551: @12336
4943 /* 12336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 557*/ GIMT_Encode4(12372), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 221 //
4944 /* 12343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4945 /* 12346 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
4946 /* 12353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4947 /* 12357 */ // MIs[0] ptr
4948 /* 12357 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4949 /* 12361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4950 /* 12365 */ // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>> => (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
4951 /* 12365 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
4952 /* 12370 */ GIR_RootConstrainSelectedInstOperands,
4953 /* 12371 */ // GIR_Coverage, 221,
4954 /* 12371 */ GIR_Done,
4955 /* 12372 */ // Label 557: @12372
4956 /* 12372 */ GIM_Reject,
4957 /* 12373 */ // Label 552: @12373
4958 /* 12373 */ GIM_Reject,
4959 /* 12374 */ // Label 25: @12374
4960 /* 12374 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 560*/ GIMT_Encode4(12539),
4961 /* 12385 */ /*GILLT_s32*//*Label 558*/ GIMT_Encode4(12393),
4962 /* 12389 */ /*GILLT_s64*//*Label 559*/ GIMT_Encode4(12502),
4963 /* 12393 */ // Label 558: @12393
4964 /* 12393 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(12501),
4965 /* 12398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4966 /* 12401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(12434), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 28 //
4967 /* 12408 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4968 /* 12415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4969 /* 12419 */ // MIs[0] ptr
4970 /* 12419 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4971 /* 12423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4972 /* 12427 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>> => (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4973 /* 12427 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
4974 /* 12432 */ GIR_RootConstrainSelectedInstOperands,
4975 /* 12433 */ // GIR_Coverage, 28,
4976 /* 12433 */ GIR_Done,
4977 /* 12434 */ // Label 562: @12434
4978 /* 12434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(12467), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 29 //
4979 /* 12441 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4980 /* 12448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4981 /* 12452 */ // MIs[0] ptr
4982 /* 12452 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4983 /* 12456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4984 /* 12460 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>> => (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4985 /* 12460 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
4986 /* 12465 */ GIR_RootConstrainSelectedInstOperands,
4987 /* 12466 */ // GIR_Coverage, 29,
4988 /* 12466 */ GIR_Done,
4989 /* 12467 */ // Label 563: @12467
4990 /* 12467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 564*/ GIMT_Encode4(12500), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 30 //
4991 /* 12474 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
4992 /* 12481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4993 /* 12485 */ // MIs[0] ptr
4994 /* 12485 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
4995 /* 12489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4996 /* 12493 */ // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>> => (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
4997 /* 12493 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
4998 /* 12498 */ GIR_RootConstrainSelectedInstOperands,
4999 /* 12499 */ // GIR_Coverage, 30,
5000 /* 12499 */ GIR_Done,
5001 /* 12500 */ // Label 564: @12500
5002 /* 12500 */ GIM_Reject,
5003 /* 12501 */ // Label 561: @12501
5004 /* 12501 */ GIM_Reject,
5005 /* 12502 */ // Label 559: @12502
5006 /* 12502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 565*/ GIMT_Encode4(12538), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 220 //
5007 /* 12509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5008 /* 12512 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5009 /* 12519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5010 /* 12523 */ // MIs[0] ptr
5011 /* 12523 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5012 /* 12527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5013 /* 12531 */ // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>> => (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5014 /* 12531 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
5015 /* 12536 */ GIR_RootConstrainSelectedInstOperands,
5016 /* 12537 */ // GIR_Coverage, 220,
5017 /* 12537 */ GIR_Done,
5018 /* 12538 */ // Label 565: @12538
5019 /* 12538 */ GIM_Reject,
5020 /* 12539 */ // Label 560: @12539
5021 /* 12539 */ GIM_Reject,
5022 /* 12540 */ // Label 26: @12540
5023 /* 12540 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 568*/ GIMT_Encode4(12705),
5024 /* 12551 */ /*GILLT_s32*//*Label 566*/ GIMT_Encode4(12559),
5025 /* 12555 */ /*GILLT_s64*//*Label 567*/ GIMT_Encode4(12668),
5026 /* 12559 */ // Label 566: @12559
5027 /* 12559 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(12667),
5028 /* 12564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5029 /* 12567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(12600), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 37 //
5030 /* 12574 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5031 /* 12581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5032 /* 12585 */ // MIs[0] ptr
5033 /* 12585 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5034 /* 12589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5035 /* 12593 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>> => (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5036 /* 12593 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
5037 /* 12598 */ GIR_RootConstrainSelectedInstOperands,
5038 /* 12599 */ // GIR_Coverage, 37,
5039 /* 12599 */ GIR_Done,
5040 /* 12600 */ // Label 570: @12600
5041 /* 12600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(12633), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 38 //
5042 /* 12607 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5043 /* 12614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5044 /* 12618 */ // MIs[0] ptr
5045 /* 12618 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5046 /* 12622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5047 /* 12626 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>> => (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5048 /* 12626 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
5049 /* 12631 */ GIR_RootConstrainSelectedInstOperands,
5050 /* 12632 */ // GIR_Coverage, 38,
5051 /* 12632 */ GIR_Done,
5052 /* 12633 */ // Label 571: @12633
5053 /* 12633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 572*/ GIMT_Encode4(12666), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 39 //
5054 /* 12640 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5055 /* 12647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5056 /* 12651 */ // MIs[0] ptr
5057 /* 12651 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5058 /* 12655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5059 /* 12659 */ // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>> => (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5060 /* 12659 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
5061 /* 12664 */ GIR_RootConstrainSelectedInstOperands,
5062 /* 12665 */ // GIR_Coverage, 39,
5063 /* 12665 */ GIR_Done,
5064 /* 12666 */ // Label 572: @12666
5065 /* 12666 */ GIM_Reject,
5066 /* 12667 */ // Label 569: @12667
5067 /* 12667 */ GIM_Reject,
5068 /* 12668 */ // Label 567: @12668
5069 /* 12668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 573*/ GIMT_Encode4(12704), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 223 //
5070 /* 12675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5071 /* 12678 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5072 /* 12685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5073 /* 12689 */ // MIs[0] ptr
5074 /* 12689 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5075 /* 12693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5076 /* 12697 */ // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>> => (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5077 /* 12697 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
5078 /* 12702 */ GIR_RootConstrainSelectedInstOperands,
5079 /* 12703 */ // GIR_Coverage, 223,
5080 /* 12703 */ GIR_Done,
5081 /* 12704 */ // Label 573: @12704
5082 /* 12704 */ GIM_Reject,
5083 /* 12705 */ // Label 568: @12705
5084 /* 12705 */ GIM_Reject,
5085 /* 12706 */ // Label 27: @12706
5086 /* 12706 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 576*/ GIMT_Encode4(12871),
5087 /* 12717 */ /*GILLT_s32*//*Label 574*/ GIMT_Encode4(12725),
5088 /* 12721 */ /*GILLT_s64*//*Label 575*/ GIMT_Encode4(12834),
5089 /* 12725 */ // Label 574: @12725
5090 /* 12725 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(12833),
5091 /* 12730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5092 /* 12733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 578*/ GIMT_Encode4(12766), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 34 //
5093 /* 12740 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
5094 /* 12747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5095 /* 12751 */ // MIs[0] ptr
5096 /* 12751 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5097 /* 12755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5098 /* 12759 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>> => (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5099 /* 12759 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
5100 /* 12764 */ GIR_RootConstrainSelectedInstOperands,
5101 /* 12765 */ // GIR_Coverage, 34,
5102 /* 12765 */ GIR_Done,
5103 /* 12766 */ // Label 578: @12766
5104 /* 12766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 579*/ GIMT_Encode4(12799), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 35 //
5105 /* 12773 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
5106 /* 12780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5107 /* 12784 */ // MIs[0] ptr
5108 /* 12784 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5109 /* 12788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5110 /* 12792 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>> => (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5111 /* 12792 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
5112 /* 12797 */ GIR_RootConstrainSelectedInstOperands,
5113 /* 12798 */ // GIR_Coverage, 35,
5114 /* 12798 */ GIR_Done,
5115 /* 12799 */ // Label 579: @12799
5116 /* 12799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 580*/ GIMT_Encode4(12832), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 36 //
5117 /* 12806 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
5118 /* 12813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5119 /* 12817 */ // MIs[0] ptr
5120 /* 12817 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5121 /* 12821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5122 /* 12825 */ // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>> => (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
5123 /* 12825 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
5124 /* 12830 */ GIR_RootConstrainSelectedInstOperands,
5125 /* 12831 */ // GIR_Coverage, 36,
5126 /* 12831 */ GIR_Done,
5127 /* 12832 */ // Label 580: @12832
5128 /* 12832 */ GIM_Reject,
5129 /* 12833 */ // Label 577: @12833
5130 /* 12833 */ GIM_Reject,
5131 /* 12834 */ // Label 575: @12834
5132 /* 12834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 581*/ GIMT_Encode4(12870), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 222 //
5133 /* 12841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5134 /* 12844 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
5135 /* 12851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5136 /* 12855 */ // MIs[0] ptr
5137 /* 12855 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
5138 /* 12859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5139 /* 12863 */ // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>> => (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
5140 /* 12863 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
5141 /* 12868 */ GIR_RootConstrainSelectedInstOperands,
5142 /* 12869 */ // GIR_Coverage, 222,
5143 /* 12869 */ GIR_Done,
5144 /* 12870 */ // Label 581: @12870
5145 /* 12870 */ GIM_Reject,
5146 /* 12871 */ // Label 576: @12871
5147 /* 12871 */ GIM_Reject,
5148 /* 12872 */ // Label 28: @12872
5149 /* 12872 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 584*/ GIMT_Encode4(19035),
5150 /* 12883 */ /*GILLT_s32*//*Label 582*/ GIMT_Encode4(12891),
5151 /* 12887 */ /*GILLT_s64*//*Label 583*/ GIMT_Encode4(19002),
5152 /* 12891 */ // Label 582: @12891
5153 /* 12891 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(18890),
5154 /* 12896 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5155 /* 12899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 586*/ GIMT_Encode4(13003), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2504 //
5156 /* 12906 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5157 /* 12910 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5158 /* 12914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5159 /* 12918 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5160 /* 12922 */ // MIs[1] Operand 1
5161 /* 12922 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5162 /* 12927 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5163 /* 12931 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5164 /* 12935 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5165 /* 12939 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5166 /* 12943 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5167 /* 12947 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5168 /* 12951 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5169 /* 12955 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5170 /* 12959 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5171 /* 12963 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5172 /* 12967 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5173 /* 12971 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5174 /* 12975 */ // MIs[4] Operand 1
5175 /* 12975 */ // No operand predicates
5176 /* 12975 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5177 /* 12980 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5178 /* 12984 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5179 /* 12986 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5180 /* 12986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5181 /* 12989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5182 /* 12993 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5183 /* 12996 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5184 /* 12998 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5185 /* 13001 */ GIR_RootConstrainSelectedInstOperands,
5186 /* 13002 */ // GIR_Coverage, 2504,
5187 /* 13002 */ GIR_EraseRootFromParent_Done,
5188 /* 13003 */ // Label 586: @13003
5189 /* 13003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 587*/ GIMT_Encode4(13114), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2505 //
5190 /* 13010 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5191 /* 13014 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5192 /* 13018 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5193 /* 13022 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5194 /* 13026 */ // MIs[1] Operand 1
5195 /* 13026 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5196 /* 13031 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5197 /* 13035 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5198 /* 13039 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5199 /* 13043 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5200 /* 13047 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5201 /* 13051 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5202 /* 13055 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5203 /* 13059 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5204 /* 13063 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5205 /* 13074 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5206 /* 13078 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5207 /* 13082 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5208 /* 13086 */ // MIs[4] Operand 1
5209 /* 13086 */ // No operand predicates
5210 /* 13086 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5211 /* 13091 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5212 /* 13095 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5213 /* 13097 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5214 /* 13097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5215 /* 13100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5216 /* 13104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5217 /* 13107 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5218 /* 13109 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5219 /* 13112 */ GIR_RootConstrainSelectedInstOperands,
5220 /* 13113 */ // GIR_Coverage, 2505,
5221 /* 13113 */ GIR_EraseRootFromParent_Done,
5222 /* 13114 */ // Label 587: @13114
5223 /* 13114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 588*/ GIMT_Encode4(13218), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2506 //
5224 /* 13121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5225 /* 13125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5226 /* 13129 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5227 /* 13133 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5228 /* 13137 */ // MIs[1] Operand 1
5229 /* 13137 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5230 /* 13142 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5231 /* 13146 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5232 /* 13150 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5233 /* 13154 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5234 /* 13158 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5235 /* 13162 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5236 /* 13166 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5237 /* 13170 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5238 /* 13174 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5239 /* 13178 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5240 /* 13182 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5241 /* 13186 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5242 /* 13190 */ // MIs[4] Operand 1
5243 /* 13190 */ // No operand predicates
5244 /* 13190 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5245 /* 13195 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5246 /* 13199 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5247 /* 13201 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5248 /* 13201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5249 /* 13204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5250 /* 13208 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5251 /* 13211 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5252 /* 13213 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5253 /* 13216 */ GIR_RootConstrainSelectedInstOperands,
5254 /* 13217 */ // GIR_Coverage, 2506,
5255 /* 13217 */ GIR_EraseRootFromParent_Done,
5256 /* 13218 */ // Label 588: @13218
5257 /* 13218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 589*/ GIMT_Encode4(13329), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 2507 //
5258 /* 13225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5259 /* 13229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5260 /* 13233 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5261 /* 13237 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5262 /* 13241 */ // MIs[1] Operand 1
5263 /* 13241 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5264 /* 13246 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5265 /* 13250 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5266 /* 13254 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5267 /* 13258 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5268 /* 13262 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
5269 /* 13266 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5270 /* 13270 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5271 /* 13274 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5272 /* 13278 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5273 /* 13289 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5274 /* 13293 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5275 /* 13297 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5276 /* 13301 */ // MIs[4] Operand 1
5277 /* 13301 */ // No operand predicates
5278 /* 13301 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5279 /* 13306 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5280 /* 13310 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5281 /* 13312 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5282 /* 13312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5283 /* 13315 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
5284 /* 13319 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5285 /* 13322 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5286 /* 13324 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5287 /* 13327 */ GIR_RootConstrainSelectedInstOperands,
5288 /* 13328 */ // GIR_Coverage, 2507,
5289 /* 13328 */ GIR_EraseRootFromParent_Done,
5290 /* 13329 */ // Label 589: @13329
5291 /* 13329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 590*/ GIMT_Encode4(13433), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 298 //
5292 /* 13336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5293 /* 13340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5294 /* 13344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5295 /* 13348 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5296 /* 13352 */ // MIs[1] Operand 1
5297 /* 13352 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5298 /* 13357 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5299 /* 13361 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5300 /* 13365 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5301 /* 13369 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5302 /* 13373 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5303 /* 13378 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5304 /* 13382 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5305 /* 13386 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5306 /* 13390 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5307 /* 13394 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5308 /* 13398 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5309 /* 13402 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5310 /* 13406 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5311 /* 13410 */ // MIs[4] Operand 1
5312 /* 13410 */ // No operand predicates
5313 /* 13410 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5314 /* 13414 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5315 /* 13416 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5316 /* 13416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
5317 /* 13419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5318 /* 13423 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5319 /* 13426 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5320 /* 13428 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5321 /* 13431 */ GIR_RootConstrainSelectedInstOperands,
5322 /* 13432 */ // GIR_Coverage, 298,
5323 /* 13432 */ GIR_EraseRootFromParent_Done,
5324 /* 13433 */ // Label 590: @13433
5325 /* 13433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 591*/ GIMT_Encode4(13544), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 299 //
5326 /* 13440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5327 /* 13444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5328 /* 13448 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5329 /* 13452 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5330 /* 13456 */ // MIs[1] Operand 1
5331 /* 13456 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5332 /* 13461 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5333 /* 13465 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5334 /* 13469 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5335 /* 13473 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5336 /* 13477 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5337 /* 13482 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5338 /* 13486 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5339 /* 13490 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5340 /* 13494 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5341 /* 13498 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5342 /* 13509 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5343 /* 13513 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5344 /* 13517 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5345 /* 13521 */ // MIs[4] Operand 1
5346 /* 13521 */ // No operand predicates
5347 /* 13521 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5348 /* 13525 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5349 /* 13527 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5350 /* 13527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
5351 /* 13530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5352 /* 13534 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5353 /* 13537 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5354 /* 13539 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5355 /* 13542 */ GIR_RootConstrainSelectedInstOperands,
5356 /* 13543 */ // GIR_Coverage, 299,
5357 /* 13543 */ GIR_EraseRootFromParent_Done,
5358 /* 13544 */ // Label 591: @13544
5359 /* 13544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 592*/ GIMT_Encode4(13648), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 300 //
5360 /* 13551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5361 /* 13555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5362 /* 13559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5363 /* 13563 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5364 /* 13567 */ // MIs[1] Operand 1
5365 /* 13567 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5366 /* 13572 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5367 /* 13576 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5368 /* 13580 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5369 /* 13584 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5370 /* 13588 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5371 /* 13593 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5372 /* 13597 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5373 /* 13601 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5374 /* 13605 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5375 /* 13609 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
5376 /* 13613 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5377 /* 13617 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5378 /* 13621 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5379 /* 13625 */ // MIs[4] Operand 1
5380 /* 13625 */ // No operand predicates
5381 /* 13625 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5382 /* 13629 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5383 /* 13631 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5384 /* 13631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
5385 /* 13634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5386 /* 13638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5387 /* 13641 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5388 /* 13643 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5389 /* 13646 */ GIR_RootConstrainSelectedInstOperands,
5390 /* 13647 */ // GIR_Coverage, 300,
5391 /* 13647 */ GIR_EraseRootFromParent_Done,
5392 /* 13648 */ // Label 592: @13648
5393 /* 13648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 593*/ GIMT_Encode4(13759), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 301 //
5394 /* 13655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5395 /* 13659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5396 /* 13663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5397 /* 13667 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5398 /* 13671 */ // MIs[1] Operand 1
5399 /* 13671 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5400 /* 13676 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
5401 /* 13680 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
5402 /* 13684 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
5403 /* 13688 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
5404 /* 13692 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5405 /* 13697 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
5406 /* 13701 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
5407 /* 13705 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
5408 /* 13709 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
5409 /* 13713 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
5410 /* 13724 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
5411 /* 13728 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5412 /* 13732 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
5413 /* 13736 */ // MIs[4] Operand 1
5414 /* 13736 */ // No operand predicates
5415 /* 13736 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5416 /* 13740 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
5417 /* 13742 */ // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
5418 /* 13742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
5419 /* 13745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
5420 /* 13749 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
5421 /* 13752 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5422 /* 13754 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5423 /* 13757 */ GIR_RootConstrainSelectedInstOperands,
5424 /* 13758 */ // GIR_Coverage, 301,
5425 /* 13758 */ GIR_EraseRootFromParent_Done,
5426 /* 13759 */ // Label 593: @13759
5427 /* 13759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 594*/ GIMT_Encode4(13812), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 94 //
5428 /* 13766 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5429 /* 13770 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5430 /* 13774 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5431 /* 13778 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5432 /* 13782 */ // MIs[1] Operand 1
5433 /* 13782 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5434 /* 13787 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5435 /* 13792 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5436 /* 13796 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5437 /* 13798 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5438 /* 13798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5439 /* 13801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5440 /* 13805 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5441 /* 13807 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5442 /* 13810 */ GIR_RootConstrainSelectedInstOperands,
5443 /* 13811 */ // GIR_Coverage, 94,
5444 /* 13811 */ GIR_EraseRootFromParent_Done,
5445 /* 13812 */ // Label 594: @13812
5446 /* 13812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 595*/ GIMT_Encode4(13865), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 95 //
5447 /* 13819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5448 /* 13823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5449 /* 13827 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5450 /* 13831 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5451 /* 13835 */ // MIs[1] Operand 1
5452 /* 13835 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5453 /* 13840 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5454 /* 13845 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5455 /* 13849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5456 /* 13851 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5457 /* 13851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
5458 /* 13854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5459 /* 13858 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5460 /* 13860 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5461 /* 13863 */ GIR_RootConstrainSelectedInstOperands,
5462 /* 13864 */ // GIR_Coverage, 95,
5463 /* 13864 */ GIR_EraseRootFromParent_Done,
5464 /* 13865 */ // Label 595: @13865
5465 /* 13865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 596*/ GIMT_Encode4(13918), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 96 //
5466 /* 13872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5467 /* 13876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5468 /* 13880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5469 /* 13884 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5470 /* 13888 */ // MIs[1] Operand 1
5471 /* 13888 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5472 /* 13893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5473 /* 13898 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5474 /* 13902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5475 /* 13904 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5476 /* 13904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5477 /* 13907 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5478 /* 13911 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5479 /* 13913 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5480 /* 13916 */ GIR_RootConstrainSelectedInstOperands,
5481 /* 13917 */ // GIR_Coverage, 96,
5482 /* 13917 */ GIR_EraseRootFromParent_Done,
5483 /* 13918 */ // Label 596: @13918
5484 /* 13918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 597*/ GIMT_Encode4(13971), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 97 //
5485 /* 13925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5486 /* 13929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5487 /* 13933 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5488 /* 13937 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5489 /* 13941 */ // MIs[1] Operand 1
5490 /* 13941 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5491 /* 13946 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5492 /* 13951 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5493 /* 13955 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5494 /* 13957 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5495 /* 13957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
5496 /* 13960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5497 /* 13964 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5498 /* 13966 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5499 /* 13969 */ GIR_RootConstrainSelectedInstOperands,
5500 /* 13970 */ // GIR_Coverage, 97,
5501 /* 13970 */ GIR_EraseRootFromParent_Done,
5502 /* 13971 */ // Label 597: @13971
5503 /* 13971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 598*/ GIMT_Encode4(14024), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 273 //
5504 /* 13978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5505 /* 13982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5506 /* 13986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5507 /* 13990 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5508 /* 13994 */ // MIs[1] Operand 1
5509 /* 13994 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5510 /* 13999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5511 /* 14004 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5512 /* 14008 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5513 /* 14010 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5514 /* 14010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5515 /* 14013 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5516 /* 14017 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5517 /* 14019 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5518 /* 14022 */ GIR_RootConstrainSelectedInstOperands,
5519 /* 14023 */ // GIR_Coverage, 273,
5520 /* 14023 */ GIR_EraseRootFromParent_Done,
5521 /* 14024 */ // Label 598: @14024
5522 /* 14024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 599*/ GIMT_Encode4(14077), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 274 //
5523 /* 14031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5524 /* 14035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5525 /* 14039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5526 /* 14043 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5527 /* 14047 */ // MIs[1] Operand 1
5528 /* 14047 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5529 /* 14052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5530 /* 14057 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5531 /* 14061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5532 /* 14063 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5533 /* 14063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
5534 /* 14066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5535 /* 14070 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5536 /* 14072 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5537 /* 14075 */ GIR_RootConstrainSelectedInstOperands,
5538 /* 14076 */ // GIR_Coverage, 274,
5539 /* 14076 */ GIR_EraseRootFromParent_Done,
5540 /* 14077 */ // Label 599: @14077
5541 /* 14077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 600*/ GIMT_Encode4(14130), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 275 //
5542 /* 14084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5543 /* 14088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5544 /* 14092 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5545 /* 14096 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5546 /* 14100 */ // MIs[1] Operand 1
5547 /* 14100 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5548 /* 14105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5549 /* 14110 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5550 /* 14114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5551 /* 14116 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5552 /* 14116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5553 /* 14119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5554 /* 14123 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5555 /* 14125 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5556 /* 14128 */ GIR_RootConstrainSelectedInstOperands,
5557 /* 14129 */ // GIR_Coverage, 275,
5558 /* 14129 */ GIR_EraseRootFromParent_Done,
5559 /* 14130 */ // Label 600: @14130
5560 /* 14130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 601*/ GIMT_Encode4(14183), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 276 //
5561 /* 14137 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5562 /* 14141 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5563 /* 14145 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5564 /* 14149 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5565 /* 14153 */ // MIs[1] Operand 1
5566 /* 14153 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5567 /* 14158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5568 /* 14163 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5569 /* 14167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5570 /* 14169 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5571 /* 14169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5572 /* 14172 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5573 /* 14176 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5574 /* 14178 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5575 /* 14181 */ GIR_RootConstrainSelectedInstOperands,
5576 /* 14182 */ // GIR_Coverage, 276,
5577 /* 14182 */ GIR_EraseRootFromParent_Done,
5578 /* 14183 */ // Label 601: @14183
5579 /* 14183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 602*/ GIMT_Encode4(14236), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1131 //
5580 /* 14190 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5581 /* 14194 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5582 /* 14198 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5583 /* 14202 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5584 /* 14206 */ // MIs[1] Operand 1
5585 /* 14206 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5586 /* 14211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5587 /* 14216 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5588 /* 14220 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5589 /* 14222 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5590 /* 14222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5591 /* 14225 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5592 /* 14229 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5593 /* 14231 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5594 /* 14234 */ GIR_RootConstrainSelectedInstOperands,
5595 /* 14235 */ // GIR_Coverage, 1131,
5596 /* 14235 */ GIR_EraseRootFromParent_Done,
5597 /* 14236 */ // Label 602: @14236
5598 /* 14236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 603*/ GIMT_Encode4(14289), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1132 //
5599 /* 14243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5600 /* 14247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5601 /* 14251 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5602 /* 14255 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5603 /* 14259 */ // MIs[1] Operand 1
5604 /* 14259 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5605 /* 14264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5606 /* 14269 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5607 /* 14273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5608 /* 14275 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5609 /* 14275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5610 /* 14278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5611 /* 14282 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5612 /* 14284 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5613 /* 14287 */ GIR_RootConstrainSelectedInstOperands,
5614 /* 14288 */ // GIR_Coverage, 1132,
5615 /* 14288 */ GIR_EraseRootFromParent_Done,
5616 /* 14289 */ // Label 603: @14289
5617 /* 14289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 604*/ GIMT_Encode4(14342), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1133 //
5618 /* 14296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5619 /* 14300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5620 /* 14304 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5621 /* 14308 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5622 /* 14312 */ // MIs[1] Operand 1
5623 /* 14312 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5624 /* 14317 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5625 /* 14322 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5626 /* 14326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5627 /* 14328 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5628 /* 14328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5629 /* 14331 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5630 /* 14335 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5631 /* 14337 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5632 /* 14340 */ GIR_RootConstrainSelectedInstOperands,
5633 /* 14341 */ // GIR_Coverage, 1133,
5634 /* 14341 */ GIR_EraseRootFromParent_Done,
5635 /* 14342 */ // Label 604: @14342
5636 /* 14342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 605*/ GIMT_Encode4(14395), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1134 //
5637 /* 14349 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5638 /* 14353 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5639 /* 14357 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5640 /* 14361 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5641 /* 14365 */ // MIs[1] Operand 1
5642 /* 14365 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5643 /* 14370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5644 /* 14375 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5645 /* 14379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5646 /* 14381 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5647 /* 14381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5648 /* 14384 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5649 /* 14388 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5650 /* 14390 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5651 /* 14393 */ GIR_RootConstrainSelectedInstOperands,
5652 /* 14394 */ // GIR_Coverage, 1134,
5653 /* 14394 */ GIR_EraseRootFromParent_Done,
5654 /* 14395 */ // Label 605: @14395
5655 /* 14395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 606*/ GIMT_Encode4(14454), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1424 //
5656 /* 14402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5657 /* 14406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5658 /* 14410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5659 /* 14414 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5660 /* 14418 */ // MIs[1] Operand 1
5661 /* 14418 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5662 /* 14423 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5663 /* 14428 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5664 /* 14432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5665 /* 14434 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5666 /* 14434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5667 /* 14437 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5668 /* 14441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5669 /* 14447 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5670 /* 14449 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5671 /* 14452 */ GIR_RootConstrainSelectedInstOperands,
5672 /* 14453 */ // GIR_Coverage, 1424,
5673 /* 14453 */ GIR_EraseRootFromParent_Done,
5674 /* 14454 */ // Label 606: @14454
5675 /* 14454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 607*/ GIMT_Encode4(14513), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1425 //
5676 /* 14461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5677 /* 14465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5678 /* 14469 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5679 /* 14473 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5680 /* 14477 */ // MIs[1] Operand 1
5681 /* 14477 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5682 /* 14482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5683 /* 14487 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5684 /* 14491 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5685 /* 14493 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5686 /* 14493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5687 /* 14496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5688 /* 14500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5689 /* 14506 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5690 /* 14508 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5691 /* 14511 */ GIR_RootConstrainSelectedInstOperands,
5692 /* 14512 */ // GIR_Coverage, 1425,
5693 /* 14512 */ GIR_EraseRootFromParent_Done,
5694 /* 14513 */ // Label 607: @14513
5695 /* 14513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 608*/ GIMT_Encode4(14572), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1654 //
5696 /* 14520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5697 /* 14524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5698 /* 14528 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5699 /* 14532 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5700 /* 14536 */ // MIs[1] Operand 1
5701 /* 14536 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5702 /* 14541 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5703 /* 14546 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5704 /* 14550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5705 /* 14552 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5706 /* 14552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
5707 /* 14555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5708 /* 14559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5709 /* 14565 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5710 /* 14567 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5711 /* 14570 */ GIR_RootConstrainSelectedInstOperands,
5712 /* 14571 */ // GIR_Coverage, 1654,
5713 /* 14571 */ GIR_EraseRootFromParent_Done,
5714 /* 14572 */ // Label 608: @14572
5715 /* 14572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(14631), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1655 //
5716 /* 14579 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5717 /* 14583 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5718 /* 14587 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5719 /* 14591 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5720 /* 14595 */ // MIs[1] Operand 1
5721 /* 14595 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5722 /* 14600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5723 /* 14605 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5724 /* 14609 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5725 /* 14611 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5726 /* 14611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
5727 /* 14614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5728 /* 14618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5729 /* 14624 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5730 /* 14626 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5731 /* 14629 */ GIR_RootConstrainSelectedInstOperands,
5732 /* 14630 */ // GIR_Coverage, 1655,
5733 /* 14630 */ GIR_EraseRootFromParent_Done,
5734 /* 14631 */ // Label 609: @14631
5735 /* 14631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(14681), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1986 //
5736 /* 14638 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5737 /* 14642 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5738 /* 14646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5739 /* 14650 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5740 /* 14654 */ // MIs[1] Operand 1
5741 /* 14654 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5742 /* 14659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5743 /* 14664 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5744 /* 14668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5745 /* 14670 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5746 /* 14670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
5747 /* 14673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5748 /* 14677 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5749 /* 14679 */ GIR_RootConstrainSelectedInstOperands,
5750 /* 14680 */ // GIR_Coverage, 1986,
5751 /* 14680 */ GIR_EraseRootFromParent_Done,
5752 /* 14681 */ // Label 610: @14681
5753 /* 14681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(14731), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1995 //
5754 /* 14688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5755 /* 14692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5756 /* 14696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5757 /* 14700 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5758 /* 14704 */ // MIs[1] Operand 1
5759 /* 14704 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5760 /* 14709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5761 /* 14714 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5762 /* 14718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5763 /* 14720 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5764 /* 14720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
5765 /* 14723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5766 /* 14727 */ GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5767 /* 14729 */ GIR_RootConstrainSelectedInstOperands,
5768 /* 14730 */ // GIR_Coverage, 1995,
5769 /* 14730 */ GIR_EraseRootFromParent_Done,
5770 /* 14731 */ // Label 611: @14731
5771 /* 14731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(14790), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2323 //
5772 /* 14738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5773 /* 14742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5774 /* 14746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5775 /* 14750 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5776 /* 14754 */ // MIs[1] Operand 1
5777 /* 14754 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5778 /* 14759 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5779 /* 14764 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5780 /* 14768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5781 /* 14770 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5782 /* 14770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
5783 /* 14773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5784 /* 14777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5785 /* 14783 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5786 /* 14785 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5787 /* 14788 */ GIR_RootConstrainSelectedInstOperands,
5788 /* 14789 */ // GIR_Coverage, 2323,
5789 /* 14789 */ GIR_EraseRootFromParent_Done,
5790 /* 14790 */ // Label 612: @14790
5791 /* 14790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(14849), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2324 //
5792 /* 14797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5793 /* 14801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5794 /* 14805 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5795 /* 14809 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5796 /* 14813 */ // MIs[1] Operand 1
5797 /* 14813 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5798 /* 14818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5799 /* 14823 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5800 /* 14827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5801 /* 14829 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5802 /* 14829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
5803 /* 14832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5804 /* 14836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5805 /* 14842 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5806 /* 14844 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5807 /* 14847 */ GIR_RootConstrainSelectedInstOperands,
5808 /* 14848 */ // GIR_Coverage, 2324,
5809 /* 14848 */ GIR_EraseRootFromParent_Done,
5810 /* 14849 */ // Label 613: @14849
5811 /* 14849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(14902), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2475 //
5812 /* 14856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5813 /* 14860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5814 /* 14864 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5815 /* 14868 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5816 /* 14872 */ // MIs[1] Operand 1
5817 /* 14872 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5818 /* 14877 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5819 /* 14882 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5820 /* 14886 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5821 /* 14888 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5822 /* 14888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
5823 /* 14891 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5824 /* 14895 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5825 /* 14897 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5826 /* 14900 */ GIR_RootConstrainSelectedInstOperands,
5827 /* 14901 */ // GIR_Coverage, 2475,
5828 /* 14901 */ GIR_EraseRootFromParent_Done,
5829 /* 14902 */ // Label 614: @14902
5830 /* 14902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(14955), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2476 //
5831 /* 14909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5832 /* 14913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5833 /* 14917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5834 /* 14921 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5835 /* 14925 */ // MIs[1] Operand 1
5836 /* 14925 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5837 /* 14930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5838 /* 14935 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5839 /* 14939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5840 /* 14941 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5841 /* 14941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
5842 /* 14944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5843 /* 14948 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5844 /* 14950 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5845 /* 14953 */ GIR_RootConstrainSelectedInstOperands,
5846 /* 14954 */ // GIR_Coverage, 2476,
5847 /* 14954 */ GIR_EraseRootFromParent_Done,
5848 /* 14955 */ // Label 615: @14955
5849 /* 14955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(15003), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1435 //
5850 /* 14962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5851 /* 14966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5852 /* 14970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5853 /* 14974 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5854 /* 14978 */ // MIs[1] Operand 1
5855 /* 14978 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5856 /* 14983 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5857 /* 14987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5858 /* 14989 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5859 /* 14989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5860 /* 14992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5861 /* 14996 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5862 /* 14998 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5863 /* 15001 */ GIR_RootConstrainSelectedInstOperands,
5864 /* 15002 */ // GIR_Coverage, 1435,
5865 /* 15002 */ GIR_EraseRootFromParent_Done,
5866 /* 15003 */ // Label 616: @15003
5867 /* 15003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(15051), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1436 //
5868 /* 15010 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5869 /* 15014 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5870 /* 15018 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5871 /* 15022 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5872 /* 15026 */ // MIs[1] Operand 1
5873 /* 15026 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5874 /* 15031 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
5875 /* 15035 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5876 /* 15037 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5877 /* 15037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5878 /* 15040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5879 /* 15044 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5880 /* 15046 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5881 /* 15049 */ GIR_RootConstrainSelectedInstOperands,
5882 /* 15050 */ // GIR_Coverage, 1436,
5883 /* 15050 */ GIR_EraseRootFromParent_Done,
5884 /* 15051 */ // Label 617: @15051
5885 /* 15051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(15099), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1665 //
5886 /* 15058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5887 /* 15062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5888 /* 15066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5889 /* 15070 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5890 /* 15074 */ // MIs[1] Operand 1
5891 /* 15074 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5892 /* 15079 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5893 /* 15083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5894 /* 15085 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5895 /* 15085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5896 /* 15088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5897 /* 15092 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5898 /* 15094 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5899 /* 15097 */ GIR_RootConstrainSelectedInstOperands,
5900 /* 15098 */ // GIR_Coverage, 1665,
5901 /* 15098 */ GIR_EraseRootFromParent_Done,
5902 /* 15099 */ // Label 618: @15099
5903 /* 15099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(15147), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1666 //
5904 /* 15106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5905 /* 15110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5906 /* 15114 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5907 /* 15118 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5908 /* 15122 */ // MIs[1] Operand 1
5909 /* 15122 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5910 /* 15127 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
5911 /* 15131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5912 /* 15133 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5913 /* 15133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5914 /* 15136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5915 /* 15140 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
5916 /* 15142 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5917 /* 15145 */ GIR_RootConstrainSelectedInstOperands,
5918 /* 15146 */ // GIR_Coverage, 1666,
5919 /* 15146 */ GIR_EraseRootFromParent_Done,
5920 /* 15147 */ // Label 619: @15147
5921 /* 15147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(15195), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1896 //
5922 /* 15154 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5923 /* 15158 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5924 /* 15162 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5925 /* 15166 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5926 /* 15170 */ // MIs[1] Operand 1
5927 /* 15170 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5928 /* 15175 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5929 /* 15179 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5930 /* 15181 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5931 /* 15181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
5932 /* 15184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5933 /* 15188 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5934 /* 15190 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5935 /* 15193 */ GIR_RootConstrainSelectedInstOperands,
5936 /* 15194 */ // GIR_Coverage, 1896,
5937 /* 15194 */ GIR_EraseRootFromParent_Done,
5938 /* 15195 */ // Label 620: @15195
5939 /* 15195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(15243), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1897 //
5940 /* 15202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5941 /* 15206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5942 /* 15210 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5943 /* 15214 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5944 /* 15218 */ // MIs[1] Operand 1
5945 /* 15218 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5946 /* 15223 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5947 /* 15227 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5948 /* 15229 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5949 /* 15229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
5950 /* 15232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5951 /* 15236 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5952 /* 15238 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5953 /* 15241 */ GIR_RootConstrainSelectedInstOperands,
5954 /* 15242 */ // GIR_Coverage, 1897,
5955 /* 15242 */ GIR_EraseRootFromParent_Done,
5956 /* 15243 */ // Label 621: @15243
5957 /* 15243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(15291), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1898 //
5958 /* 15250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5959 /* 15254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5960 /* 15258 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5961 /* 15262 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5962 /* 15266 */ // MIs[1] Operand 1
5963 /* 15266 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5964 /* 15271 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5965 /* 15275 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5966 /* 15277 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5967 /* 15277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
5968 /* 15280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5969 /* 15284 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5970 /* 15286 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5971 /* 15289 */ GIR_RootConstrainSelectedInstOperands,
5972 /* 15290 */ // GIR_Coverage, 1898,
5973 /* 15290 */ GIR_EraseRootFromParent_Done,
5974 /* 15291 */ // Label 622: @15291
5975 /* 15291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(15339), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1899 //
5976 /* 15298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5977 /* 15302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5978 /* 15306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5979 /* 15310 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5980 /* 15314 */ // MIs[1] Operand 1
5981 /* 15314 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5982 /* 15319 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5983 /* 15323 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5984 /* 15325 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5985 /* 15325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
5986 /* 15328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5987 /* 15332 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
5988 /* 15334 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5989 /* 15337 */ GIR_RootConstrainSelectedInstOperands,
5990 /* 15338 */ // GIR_Coverage, 1899,
5991 /* 15338 */ GIR_EraseRootFromParent_Done,
5992 /* 15339 */ // Label 623: @15339
5993 /* 15339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 624*/ GIMT_Encode4(15387), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1900 //
5994 /* 15346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5995 /* 15350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5996 /* 15354 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5997 /* 15358 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5998 /* 15362 */ // MIs[1] Operand 1
5999 /* 15362 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6000 /* 15367 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6001 /* 15371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6002 /* 15373 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6003 /* 15373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
6004 /* 15376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6005 /* 15380 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6006 /* 15382 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6007 /* 15385 */ GIR_RootConstrainSelectedInstOperands,
6008 /* 15386 */ // GIR_Coverage, 1900,
6009 /* 15386 */ GIR_EraseRootFromParent_Done,
6010 /* 15387 */ // Label 624: @15387
6011 /* 15387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 625*/ GIMT_Encode4(15435), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1901 //
6012 /* 15394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6013 /* 15398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6014 /* 15402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6015 /* 15406 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6016 /* 15410 */ // MIs[1] Operand 1
6017 /* 15410 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6018 /* 15415 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6019 /* 15419 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6020 /* 15421 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6021 /* 15421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
6022 /* 15424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6023 /* 15428 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6024 /* 15430 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6025 /* 15433 */ GIR_RootConstrainSelectedInstOperands,
6026 /* 15434 */ // GIR_Coverage, 1901,
6027 /* 15434 */ GIR_EraseRootFromParent_Done,
6028 /* 15435 */ // Label 625: @15435
6029 /* 15435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(15483), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1902 //
6030 /* 15442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6031 /* 15446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6032 /* 15450 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6033 /* 15454 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6034 /* 15458 */ // MIs[1] Operand 1
6035 /* 15458 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6036 /* 15463 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6037 /* 15467 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6038 /* 15469 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6039 /* 15469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
6040 /* 15472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6041 /* 15476 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6042 /* 15478 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6043 /* 15481 */ GIR_RootConstrainSelectedInstOperands,
6044 /* 15482 */ // GIR_Coverage, 1902,
6045 /* 15482 */ GIR_EraseRootFromParent_Done,
6046 /* 15483 */ // Label 626: @15483
6047 /* 15483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(15531), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1903 //
6048 /* 15490 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6049 /* 15494 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6050 /* 15498 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6051 /* 15502 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6052 /* 15506 */ // MIs[1] Operand 1
6053 /* 15506 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6054 /* 15511 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6055 /* 15515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6056 /* 15517 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6057 /* 15517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
6058 /* 15520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6059 /* 15524 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6060 /* 15526 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6061 /* 15529 */ GIR_RootConstrainSelectedInstOperands,
6062 /* 15530 */ // GIR_Coverage, 1903,
6063 /* 15530 */ GIR_EraseRootFromParent_Done,
6064 /* 15531 */ // Label 627: @15531
6065 /* 15531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 628*/ GIMT_Encode4(15579), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1939 //
6066 /* 15538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6067 /* 15542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6068 /* 15546 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6069 /* 15550 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6070 /* 15554 */ // MIs[1] Operand 1
6071 /* 15554 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6072 /* 15559 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6073 /* 15563 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6074 /* 15565 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6075 /* 15565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6076 /* 15568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6077 /* 15572 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6078 /* 15574 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6079 /* 15577 */ GIR_RootConstrainSelectedInstOperands,
6080 /* 15578 */ // GIR_Coverage, 1939,
6081 /* 15578 */ GIR_EraseRootFromParent_Done,
6082 /* 15579 */ // Label 628: @15579
6083 /* 15579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 629*/ GIMT_Encode4(15627), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1940 //
6084 /* 15586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6085 /* 15590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6086 /* 15594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6087 /* 15598 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6088 /* 15602 */ // MIs[1] Operand 1
6089 /* 15602 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6090 /* 15607 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6091 /* 15611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6092 /* 15613 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6093 /* 15613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6094 /* 15616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6095 /* 15620 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6096 /* 15622 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6097 /* 15625 */ GIR_RootConstrainSelectedInstOperands,
6098 /* 15626 */ // GIR_Coverage, 1940,
6099 /* 15626 */ GIR_EraseRootFromParent_Done,
6100 /* 15627 */ // Label 629: @15627
6101 /* 15627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(15675), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1941 //
6102 /* 15634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6103 /* 15638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6104 /* 15642 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6105 /* 15646 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6106 /* 15650 */ // MIs[1] Operand 1
6107 /* 15650 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6108 /* 15655 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6109 /* 15659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6110 /* 15661 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6111 /* 15661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6112 /* 15664 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6113 /* 15668 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6114 /* 15670 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6115 /* 15673 */ GIR_RootConstrainSelectedInstOperands,
6116 /* 15674 */ // GIR_Coverage, 1941,
6117 /* 15674 */ GIR_EraseRootFromParent_Done,
6118 /* 15675 */ // Label 630: @15675
6119 /* 15675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(15723), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1942 //
6120 /* 15682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6121 /* 15686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6122 /* 15690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6123 /* 15694 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6124 /* 15698 */ // MIs[1] Operand 1
6125 /* 15698 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6126 /* 15703 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6127 /* 15707 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6128 /* 15709 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6129 /* 15709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6130 /* 15712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6131 /* 15716 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6132 /* 15718 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6133 /* 15721 */ GIR_RootConstrainSelectedInstOperands,
6134 /* 15722 */ // GIR_Coverage, 1942,
6135 /* 15722 */ GIR_EraseRootFromParent_Done,
6136 /* 15723 */ // Label 631: @15723
6137 /* 15723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 632*/ GIMT_Encode4(15771), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1943 //
6138 /* 15730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6139 /* 15734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6140 /* 15738 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6141 /* 15742 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6142 /* 15746 */ // MIs[1] Operand 1
6143 /* 15746 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6144 /* 15751 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6145 /* 15755 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6146 /* 15757 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6147 /* 15757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
6148 /* 15760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6149 /* 15764 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6150 /* 15766 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6151 /* 15769 */ GIR_RootConstrainSelectedInstOperands,
6152 /* 15770 */ // GIR_Coverage, 1943,
6153 /* 15770 */ GIR_EraseRootFromParent_Done,
6154 /* 15771 */ // Label 632: @15771
6155 /* 15771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 633*/ GIMT_Encode4(15819), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1944 //
6156 /* 15778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6157 /* 15782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6158 /* 15786 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6159 /* 15790 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6160 /* 15794 */ // MIs[1] Operand 1
6161 /* 15794 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6162 /* 15799 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6163 /* 15803 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6164 /* 15805 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6165 /* 15805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
6166 /* 15808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6167 /* 15812 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6168 /* 15814 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6169 /* 15817 */ GIR_RootConstrainSelectedInstOperands,
6170 /* 15818 */ // GIR_Coverage, 1944,
6171 /* 15818 */ GIR_EraseRootFromParent_Done,
6172 /* 15819 */ // Label 633: @15819
6173 /* 15819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(15867), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1945 //
6174 /* 15826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6175 /* 15830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6176 /* 15834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6177 /* 15838 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6178 /* 15842 */ // MIs[1] Operand 1
6179 /* 15842 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6180 /* 15847 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
6181 /* 15851 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6182 /* 15853 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6183 /* 15853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
6184 /* 15856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6185 /* 15860 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6186 /* 15862 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6187 /* 15865 */ GIR_RootConstrainSelectedInstOperands,
6188 /* 15866 */ // GIR_Coverage, 1945,
6189 /* 15866 */ GIR_EraseRootFromParent_Done,
6190 /* 15867 */ // Label 634: @15867
6191 /* 15867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 635*/ GIMT_Encode4(15915), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1946 //
6192 /* 15874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6193 /* 15878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6194 /* 15882 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6195 /* 15886 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6196 /* 15890 */ // MIs[1] Operand 1
6197 /* 15890 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6198 /* 15895 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6199 /* 15899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6200 /* 15901 */ // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6201 /* 15901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
6202 /* 15904 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6203 /* 15908 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6204 /* 15910 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6205 /* 15913 */ GIR_RootConstrainSelectedInstOperands,
6206 /* 15914 */ // GIR_Coverage, 1946,
6207 /* 15914 */ GIR_EraseRootFromParent_Done,
6208 /* 15915 */ // Label 635: @15915
6209 /* 15915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 636*/ GIMT_Encode4(15963), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2334 //
6210 /* 15922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6211 /* 15926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6212 /* 15930 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6213 /* 15934 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6214 /* 15938 */ // MIs[1] Operand 1
6215 /* 15938 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6216 /* 15943 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
6217 /* 15947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6218 /* 15949 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6219 /* 15949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
6220 /* 15952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6221 /* 15956 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6222 /* 15958 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6223 /* 15961 */ GIR_RootConstrainSelectedInstOperands,
6224 /* 15962 */ // GIR_Coverage, 2334,
6225 /* 15962 */ GIR_EraseRootFromParent_Done,
6226 /* 15963 */ // Label 636: @15963
6227 /* 15963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(16011), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2335 //
6228 /* 15970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6229 /* 15974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6230 /* 15978 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6231 /* 15982 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6232 /* 15986 */ // MIs[1] Operand 1
6233 /* 15986 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6234 /* 15991 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
6235 /* 15995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6236 /* 15997 */ // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
6237 /* 15997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
6238 /* 16000 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6239 /* 16004 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6240 /* 16006 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6241 /* 16009 */ GIR_RootConstrainSelectedInstOperands,
6242 /* 16010 */ // GIR_Coverage, 2335,
6243 /* 16010 */ GIR_EraseRootFromParent_Done,
6244 /* 16011 */ // Label 637: @16011
6245 /* 16011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 638*/ GIMT_Encode4(16069), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 92 //
6246 /* 16018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6247 /* 16022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6248 /* 16026 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6249 /* 16030 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6250 /* 16034 */ // MIs[1] Operand 1
6251 /* 16034 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6252 /* 16039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6253 /* 16044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6254 /* 16049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6255 /* 16051 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6256 /* 16051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6257 /* 16054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6258 /* 16058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6259 /* 16062 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6260 /* 16064 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6261 /* 16067 */ GIR_RootConstrainSelectedInstOperands,
6262 /* 16068 */ // GIR_Coverage, 92,
6263 /* 16068 */ GIR_EraseRootFromParent_Done,
6264 /* 16069 */ // Label 638: @16069
6265 /* 16069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 639*/ GIMT_Encode4(16127), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 93 //
6266 /* 16076 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6267 /* 16080 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6268 /* 16084 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6269 /* 16088 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6270 /* 16092 */ // MIs[1] Operand 1
6271 /* 16092 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6272 /* 16097 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6273 /* 16102 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6274 /* 16107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6275 /* 16109 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6276 /* 16109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6277 /* 16112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6278 /* 16116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6279 /* 16120 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6280 /* 16122 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6281 /* 16125 */ GIR_RootConstrainSelectedInstOperands,
6282 /* 16126 */ // GIR_Coverage, 93,
6283 /* 16126 */ GIR_EraseRootFromParent_Done,
6284 /* 16127 */ // Label 639: @16127
6285 /* 16127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 640*/ GIMT_Encode4(16185), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 271 //
6286 /* 16134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6287 /* 16138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6288 /* 16142 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6289 /* 16146 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6290 /* 16150 */ // MIs[1] Operand 1
6291 /* 16150 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6292 /* 16155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6293 /* 16160 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6294 /* 16165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6295 /* 16167 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6296 /* 16167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
6297 /* 16170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6298 /* 16174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6299 /* 16178 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6300 /* 16180 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6301 /* 16183 */ GIR_RootConstrainSelectedInstOperands,
6302 /* 16184 */ // GIR_Coverage, 271,
6303 /* 16184 */ GIR_EraseRootFromParent_Done,
6304 /* 16185 */ // Label 640: @16185
6305 /* 16185 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 641*/ GIMT_Encode4(16243), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 272 //
6306 /* 16192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6307 /* 16196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6308 /* 16200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6309 /* 16204 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6310 /* 16208 */ // MIs[1] Operand 1
6311 /* 16208 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6312 /* 16213 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6313 /* 16218 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6314 /* 16223 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6315 /* 16225 */ // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6316 /* 16225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6317 /* 16228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6318 /* 16232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6319 /* 16236 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6320 /* 16238 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6321 /* 16241 */ GIR_RootConstrainSelectedInstOperands,
6322 /* 16242 */ // GIR_Coverage, 272,
6323 /* 16242 */ GIR_EraseRootFromParent_Done,
6324 /* 16243 */ // Label 641: @16243
6325 /* 16243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 642*/ GIMT_Encode4(16301), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1129 //
6326 /* 16250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6327 /* 16254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6328 /* 16258 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6329 /* 16262 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6330 /* 16266 */ // MIs[1] Operand 1
6331 /* 16266 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6332 /* 16271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6333 /* 16276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6334 /* 16281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6335 /* 16283 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6336 /* 16283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6337 /* 16286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6338 /* 16290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6339 /* 16294 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6340 /* 16296 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6341 /* 16299 */ GIR_RootConstrainSelectedInstOperands,
6342 /* 16300 */ // GIR_Coverage, 1129,
6343 /* 16300 */ GIR_EraseRootFromParent_Done,
6344 /* 16301 */ // Label 642: @16301
6345 /* 16301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 643*/ GIMT_Encode4(16359), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 1130 //
6346 /* 16308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6347 /* 16312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6348 /* 16316 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6349 /* 16320 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6350 /* 16324 */ // MIs[1] Operand 1
6351 /* 16324 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6352 /* 16329 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6353 /* 16334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6354 /* 16339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6355 /* 16341 */ // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6356 /* 16341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6357 /* 16344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6358 /* 16348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6359 /* 16352 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6360 /* 16354 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6361 /* 16357 */ GIR_RootConstrainSelectedInstOperands,
6362 /* 16358 */ // GIR_Coverage, 1130,
6363 /* 16358 */ GIR_EraseRootFromParent_Done,
6364 /* 16359 */ // Label 643: @16359
6365 /* 16359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 644*/ GIMT_Encode4(16440), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1426 //
6366 /* 16366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6367 /* 16370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6368 /* 16374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6369 /* 16378 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6370 /* 16382 */ // MIs[1] Operand 1
6371 /* 16382 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6372 /* 16387 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6373 /* 16392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6374 /* 16397 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6375 /* 16399 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6376 /* 16399 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6377 /* 16402 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6378 /* 16406 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6379 /* 16411 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6380 /* 16415 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6381 /* 16419 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6382 /* 16421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6383 /* 16424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6384 /* 16427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6385 /* 16433 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6386 /* 16435 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6387 /* 16438 */ GIR_RootConstrainSelectedInstOperands,
6388 /* 16439 */ // GIR_Coverage, 1426,
6389 /* 16439 */ GIR_EraseRootFromParent_Done,
6390 /* 16440 */ // Label 644: @16440
6391 /* 16440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 645*/ GIMT_Encode4(16521), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1427 //
6392 /* 16447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6393 /* 16451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6394 /* 16455 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6395 /* 16459 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6396 /* 16463 */ // MIs[1] Operand 1
6397 /* 16463 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6398 /* 16468 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6399 /* 16473 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6400 /* 16478 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6401 /* 16480 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6402 /* 16480 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6403 /* 16483 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6404 /* 16487 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6405 /* 16492 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6406 /* 16496 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6407 /* 16500 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6408 /* 16502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6409 /* 16505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6410 /* 16508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6411 /* 16514 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6412 /* 16516 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6413 /* 16519 */ GIR_RootConstrainSelectedInstOperands,
6414 /* 16520 */ // GIR_Coverage, 1427,
6415 /* 16520 */ GIR_EraseRootFromParent_Done,
6416 /* 16521 */ // Label 645: @16521
6417 /* 16521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 646*/ GIMT_Encode4(16602), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1432 //
6418 /* 16528 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6419 /* 16532 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6420 /* 16536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6421 /* 16540 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6422 /* 16544 */ // MIs[1] Operand 1
6423 /* 16544 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6424 /* 16549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6425 /* 16554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6426 /* 16559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6427 /* 16561 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6428 /* 16561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6429 /* 16564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
6430 /* 16568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6431 /* 16573 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6432 /* 16577 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6433 /* 16581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6434 /* 16583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6435 /* 16586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6436 /* 16589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6437 /* 16595 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6438 /* 16597 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6439 /* 16600 */ GIR_RootConstrainSelectedInstOperands,
6440 /* 16601 */ // GIR_Coverage, 1432,
6441 /* 16601 */ GIR_EraseRootFromParent_Done,
6442 /* 16602 */ // Label 646: @16602
6443 /* 16602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 647*/ GIMT_Encode4(16683), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1433 //
6444 /* 16609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6445 /* 16613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6446 /* 16617 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6447 /* 16621 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6448 /* 16625 */ // MIs[1] Operand 1
6449 /* 16625 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6450 /* 16630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6451 /* 16635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6452 /* 16640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6453 /* 16642 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6454 /* 16642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6455 /* 16645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
6456 /* 16649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6457 /* 16654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6458 /* 16658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6459 /* 16662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6460 /* 16664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6461 /* 16667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6462 /* 16670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6463 /* 16676 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6464 /* 16678 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6465 /* 16681 */ GIR_RootConstrainSelectedInstOperands,
6466 /* 16682 */ // GIR_Coverage, 1433,
6467 /* 16682 */ GIR_EraseRootFromParent_Done,
6468 /* 16683 */ // Label 647: @16683
6469 /* 16683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(16764), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1656 //
6470 /* 16690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6471 /* 16694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6472 /* 16698 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6473 /* 16702 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6474 /* 16706 */ // MIs[1] Operand 1
6475 /* 16706 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6476 /* 16711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6477 /* 16716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6478 /* 16721 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6479 /* 16723 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6480 /* 16723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6481 /* 16726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6482 /* 16730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6483 /* 16735 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6484 /* 16739 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6485 /* 16743 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6486 /* 16745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6487 /* 16748 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6488 /* 16751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6489 /* 16757 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6490 /* 16759 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6491 /* 16762 */ GIR_RootConstrainSelectedInstOperands,
6492 /* 16763 */ // GIR_Coverage, 1656,
6493 /* 16763 */ GIR_EraseRootFromParent_Done,
6494 /* 16764 */ // Label 648: @16764
6495 /* 16764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(16845), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1657 //
6496 /* 16771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6497 /* 16775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6498 /* 16779 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6499 /* 16783 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6500 /* 16787 */ // MIs[1] Operand 1
6501 /* 16787 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6502 /* 16792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6503 /* 16797 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6504 /* 16802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6505 /* 16804 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6506 /* 16804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6507 /* 16807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6508 /* 16811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6509 /* 16816 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6510 /* 16820 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6511 /* 16824 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6512 /* 16826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6513 /* 16829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6514 /* 16832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6515 /* 16838 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6516 /* 16840 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6517 /* 16843 */ GIR_RootConstrainSelectedInstOperands,
6518 /* 16844 */ // GIR_Coverage, 1657,
6519 /* 16844 */ GIR_EraseRootFromParent_Done,
6520 /* 16845 */ // Label 649: @16845
6521 /* 16845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 650*/ GIMT_Encode4(16926), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1662 //
6522 /* 16852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6523 /* 16856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6524 /* 16860 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6525 /* 16864 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6526 /* 16868 */ // MIs[1] Operand 1
6527 /* 16868 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6528 /* 16873 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6529 /* 16878 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6530 /* 16883 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6531 /* 16885 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6532 /* 16885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6533 /* 16888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
6534 /* 16892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6535 /* 16897 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6536 /* 16901 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6537 /* 16905 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6538 /* 16907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6539 /* 16910 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6540 /* 16913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6541 /* 16919 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6542 /* 16921 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6543 /* 16924 */ GIR_RootConstrainSelectedInstOperands,
6544 /* 16925 */ // GIR_Coverage, 1662,
6545 /* 16925 */ GIR_EraseRootFromParent_Done,
6546 /* 16926 */ // Label 650: @16926
6547 /* 16926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 651*/ GIMT_Encode4(17007), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1663 //
6548 /* 16933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6549 /* 16937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6550 /* 16941 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6551 /* 16945 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6552 /* 16949 */ // MIs[1] Operand 1
6553 /* 16949 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6554 /* 16954 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6555 /* 16959 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6556 /* 16964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6557 /* 16966 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6558 /* 16966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6559 /* 16969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
6560 /* 16973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6561 /* 16978 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6562 /* 16982 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6563 /* 16986 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6564 /* 16988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
6565 /* 16991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6566 /* 16994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6567 /* 17000 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
6568 /* 17002 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6569 /* 17005 */ GIR_RootConstrainSelectedInstOperands,
6570 /* 17006 */ // GIR_Coverage, 1663,
6571 /* 17006 */ GIR_EraseRootFromParent_Done,
6572 /* 17007 */ // Label 651: @17007
6573 /* 17007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(17065), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1904 //
6574 /* 17014 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6575 /* 17018 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6576 /* 17022 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6577 /* 17026 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6578 /* 17030 */ // MIs[1] Operand 1
6579 /* 17030 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6580 /* 17035 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6581 /* 17040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6582 /* 17045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6583 /* 17047 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6584 /* 17047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
6585 /* 17050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6586 /* 17054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6587 /* 17058 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6588 /* 17060 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6589 /* 17063 */ GIR_RootConstrainSelectedInstOperands,
6590 /* 17064 */ // GIR_Coverage, 1904,
6591 /* 17064 */ GIR_EraseRootFromParent_Done,
6592 /* 17065 */ // Label 652: @17065
6593 /* 17065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(17123), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1905 //
6594 /* 17072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6595 /* 17076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6596 /* 17080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6597 /* 17084 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6598 /* 17088 */ // MIs[1] Operand 1
6599 /* 17088 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6600 /* 17093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6601 /* 17098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6602 /* 17103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6603 /* 17105 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6604 /* 17105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
6605 /* 17108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6606 /* 17112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6607 /* 17116 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6608 /* 17118 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6609 /* 17121 */ GIR_RootConstrainSelectedInstOperands,
6610 /* 17122 */ // GIR_Coverage, 1905,
6611 /* 17122 */ GIR_EraseRootFromParent_Done,
6612 /* 17123 */ // Label 653: @17123
6613 /* 17123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 654*/ GIMT_Encode4(17181), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1906 //
6614 /* 17130 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6615 /* 17134 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6616 /* 17138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6617 /* 17142 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6618 /* 17146 */ // MIs[1] Operand 1
6619 /* 17146 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6620 /* 17151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6621 /* 17156 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6622 /* 17161 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6623 /* 17163 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6624 /* 17163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
6625 /* 17166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6626 /* 17170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6627 /* 17174 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6628 /* 17176 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6629 /* 17179 */ GIR_RootConstrainSelectedInstOperands,
6630 /* 17180 */ // GIR_Coverage, 1906,
6631 /* 17180 */ GIR_EraseRootFromParent_Done,
6632 /* 17181 */ // Label 654: @17181
6633 /* 17181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 655*/ GIMT_Encode4(17239), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1907 //
6634 /* 17188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6635 /* 17192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6636 /* 17196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6637 /* 17200 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6638 /* 17204 */ // MIs[1] Operand 1
6639 /* 17204 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6640 /* 17209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6641 /* 17214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6642 /* 17219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6643 /* 17221 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6644 /* 17221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
6645 /* 17224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6646 /* 17228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6647 /* 17232 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6648 /* 17234 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6649 /* 17237 */ GIR_RootConstrainSelectedInstOperands,
6650 /* 17238 */ // GIR_Coverage, 1907,
6651 /* 17238 */ GIR_EraseRootFromParent_Done,
6652 /* 17239 */ // Label 655: @17239
6653 /* 17239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(17297), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1908 //
6654 /* 17246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6655 /* 17250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6656 /* 17254 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6657 /* 17258 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6658 /* 17262 */ // MIs[1] Operand 1
6659 /* 17262 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
6660 /* 17267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6661 /* 17272 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6662 /* 17277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6663 /* 17279 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6664 /* 17279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
6665 /* 17282 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6666 /* 17286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6667 /* 17290 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6668 /* 17292 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6669 /* 17295 */ GIR_RootConstrainSelectedInstOperands,
6670 /* 17296 */ // GIR_Coverage, 1908,
6671 /* 17296 */ GIR_EraseRootFromParent_Done,
6672 /* 17297 */ // Label 656: @17297
6673 /* 17297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 657*/ GIMT_Encode4(17355), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1909 //
6674 /* 17304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6675 /* 17308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6676 /* 17312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6677 /* 17316 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6678 /* 17320 */ // MIs[1] Operand 1
6679 /* 17320 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6680 /* 17325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6681 /* 17330 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6682 /* 17335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6683 /* 17337 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
6684 /* 17337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
6685 /* 17340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6686 /* 17344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6687 /* 17348 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6688 /* 17350 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6689 /* 17353 */ GIR_RootConstrainSelectedInstOperands,
6690 /* 17354 */ // GIR_Coverage, 1909,
6691 /* 17354 */ GIR_EraseRootFromParent_Done,
6692 /* 17355 */ // Label 657: @17355
6693 /* 17355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 658*/ GIMT_Encode4(17413), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1910 //
6694 /* 17362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6695 /* 17366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6696 /* 17370 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6697 /* 17374 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6698 /* 17378 */ // MIs[1] Operand 1
6699 /* 17378 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
6700 /* 17383 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6701 /* 17388 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6702 /* 17393 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6703 /* 17395 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6704 /* 17395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
6705 /* 17398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6706 /* 17402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6707 /* 17406 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6708 /* 17408 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6709 /* 17411 */ GIR_RootConstrainSelectedInstOperands,
6710 /* 17412 */ // GIR_Coverage, 1910,
6711 /* 17412 */ GIR_EraseRootFromParent_Done,
6712 /* 17413 */ // Label 658: @17413
6713 /* 17413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 659*/ GIMT_Encode4(17471), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1911 //
6714 /* 17420 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6715 /* 17424 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6716 /* 17428 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6717 /* 17432 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6718 /* 17436 */ // MIs[1] Operand 1
6719 /* 17436 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6720 /* 17441 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6721 /* 17446 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6722 /* 17451 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6723 /* 17453 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
6724 /* 17453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
6725 /* 17456 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6726 /* 17460 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6727 /* 17464 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6728 /* 17466 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6729 /* 17469 */ GIR_RootConstrainSelectedInstOperands,
6730 /* 17470 */ // GIR_Coverage, 1911,
6731 /* 17470 */ GIR_EraseRootFromParent_Done,
6732 /* 17471 */ // Label 659: @17471
6733 /* 17471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 660*/ GIMT_Encode4(17529), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1947 //
6734 /* 17478 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6735 /* 17482 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6736 /* 17486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6737 /* 17490 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6738 /* 17494 */ // MIs[1] Operand 1
6739 /* 17494 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6740 /* 17499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6741 /* 17504 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6742 /* 17509 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6743 /* 17511 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6744 /* 17511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
6745 /* 17514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6746 /* 17518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6747 /* 17522 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6748 /* 17524 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6749 /* 17527 */ GIR_RootConstrainSelectedInstOperands,
6750 /* 17528 */ // GIR_Coverage, 1947,
6751 /* 17528 */ GIR_EraseRootFromParent_Done,
6752 /* 17529 */ // Label 660: @17529
6753 /* 17529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 661*/ GIMT_Encode4(17587), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1948 //
6754 /* 17536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6755 /* 17540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6756 /* 17544 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6757 /* 17548 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6758 /* 17552 */ // MIs[1] Operand 1
6759 /* 17552 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6760 /* 17557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6761 /* 17562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6762 /* 17567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6763 /* 17569 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6764 /* 17569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
6765 /* 17572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6766 /* 17576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6767 /* 17580 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6768 /* 17582 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6769 /* 17585 */ GIR_RootConstrainSelectedInstOperands,
6770 /* 17586 */ // GIR_Coverage, 1948,
6771 /* 17586 */ GIR_EraseRootFromParent_Done,
6772 /* 17587 */ // Label 661: @17587
6773 /* 17587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 662*/ GIMT_Encode4(17645), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1949 //
6774 /* 17594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6775 /* 17598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6776 /* 17602 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6777 /* 17606 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6778 /* 17610 */ // MIs[1] Operand 1
6779 /* 17610 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6780 /* 17615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6781 /* 17620 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6782 /* 17625 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6783 /* 17627 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6784 /* 17627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
6785 /* 17630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6786 /* 17634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6787 /* 17638 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6788 /* 17640 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6789 /* 17643 */ GIR_RootConstrainSelectedInstOperands,
6790 /* 17644 */ // GIR_Coverage, 1949,
6791 /* 17644 */ GIR_EraseRootFromParent_Done,
6792 /* 17645 */ // Label 662: @17645
6793 /* 17645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 663*/ GIMT_Encode4(17703), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1950 //
6794 /* 17652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6795 /* 17656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6796 /* 17660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6797 /* 17664 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6798 /* 17668 */ // MIs[1] Operand 1
6799 /* 17668 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6800 /* 17673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6801 /* 17678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6802 /* 17683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6803 /* 17685 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6804 /* 17685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
6805 /* 17688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6806 /* 17692 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6807 /* 17696 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6808 /* 17698 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6809 /* 17701 */ GIR_RootConstrainSelectedInstOperands,
6810 /* 17702 */ // GIR_Coverage, 1950,
6811 /* 17702 */ GIR_EraseRootFromParent_Done,
6812 /* 17703 */ // Label 663: @17703
6813 /* 17703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 664*/ GIMT_Encode4(17761), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1951 //
6814 /* 17710 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6815 /* 17714 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6816 /* 17718 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6817 /* 17722 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6818 /* 17726 */ // MIs[1] Operand 1
6819 /* 17726 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
6820 /* 17731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6821 /* 17736 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6822 /* 17741 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6823 /* 17743 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6824 /* 17743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
6825 /* 17746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6826 /* 17750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6827 /* 17754 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6828 /* 17756 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6829 /* 17759 */ GIR_RootConstrainSelectedInstOperands,
6830 /* 17760 */ // GIR_Coverage, 1951,
6831 /* 17760 */ GIR_EraseRootFromParent_Done,
6832 /* 17761 */ // Label 664: @17761
6833 /* 17761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 665*/ GIMT_Encode4(17819), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1952 //
6834 /* 17768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6835 /* 17772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6836 /* 17776 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6837 /* 17780 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6838 /* 17784 */ // MIs[1] Operand 1
6839 /* 17784 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6840 /* 17789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6841 /* 17794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6842 /* 17799 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6843 /* 17801 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
6844 /* 17801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
6845 /* 17804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6846 /* 17808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6847 /* 17812 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6848 /* 17814 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6849 /* 17817 */ GIR_RootConstrainSelectedInstOperands,
6850 /* 17818 */ // GIR_Coverage, 1952,
6851 /* 17818 */ GIR_EraseRootFromParent_Done,
6852 /* 17819 */ // Label 665: @17819
6853 /* 17819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 666*/ GIMT_Encode4(17877), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1953 //
6854 /* 17826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6855 /* 17830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6856 /* 17834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6857 /* 17838 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6858 /* 17842 */ // MIs[1] Operand 1
6859 /* 17842 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
6860 /* 17847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6861 /* 17852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6862 /* 17857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6863 /* 17859 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6864 /* 17859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
6865 /* 17862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6866 /* 17866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6867 /* 17870 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6868 /* 17872 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6869 /* 17875 */ GIR_RootConstrainSelectedInstOperands,
6870 /* 17876 */ // GIR_Coverage, 1953,
6871 /* 17876 */ GIR_EraseRootFromParent_Done,
6872 /* 17877 */ // Label 666: @17877
6873 /* 17877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(17935), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches), // Rule ID 1954 //
6874 /* 17884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6875 /* 17888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6876 /* 17892 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
6877 /* 17896 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
6878 /* 17900 */ // MIs[1] Operand 1
6879 /* 17900 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6880 /* 17905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6881 /* 17910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6882 /* 17915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6883 /* 17917 */ // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
6884 /* 17917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
6885 /* 17920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
6886 /* 17924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
6887 /* 17928 */ GIR_RootToRootCopy, /*OpIdx*/1, // offset
6888 /* 17930 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6889 /* 17933 */ GIR_RootConstrainSelectedInstOperands,
6890 /* 17934 */ // GIR_Coverage, 1954,
6891 /* 17934 */ GIR_EraseRootFromParent_Done,
6892 /* 17935 */ // Label 667: @17935
6893 /* 17935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(17990), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1984 //
6894 /* 17942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6895 /* 17946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6896 /* 17950 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6897 /* 17954 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6898 /* 17958 */ // MIs[1] Operand 1
6899 /* 17958 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
6900 /* 17963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6901 /* 17968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6902 /* 17973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6903 /* 17975 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6904 /* 17975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
6905 /* 17978 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6906 /* 17982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6907 /* 17986 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6908 /* 17988 */ GIR_RootConstrainSelectedInstOperands,
6909 /* 17989 */ // GIR_Coverage, 1984,
6910 /* 17989 */ GIR_EraseRootFromParent_Done,
6911 /* 17990 */ // Label 668: @17990
6912 /* 17990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 669*/ GIMT_Encode4(18045), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1987 //
6913 /* 17997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6914 /* 18001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6915 /* 18005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6916 /* 18009 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6917 /* 18013 */ // MIs[1] Operand 1
6918 /* 18013 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
6919 /* 18018 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6920 /* 18023 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6921 /* 18028 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6922 /* 18030 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6923 /* 18030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
6924 /* 18033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6925 /* 18037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6926 /* 18041 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6927 /* 18043 */ GIR_RootConstrainSelectedInstOperands,
6928 /* 18044 */ // GIR_Coverage, 1987,
6929 /* 18044 */ GIR_EraseRootFromParent_Done,
6930 /* 18045 */ // Label 669: @18045
6931 /* 18045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 670*/ GIMT_Encode4(18100), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1988 //
6932 /* 18052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6933 /* 18056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6934 /* 18060 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6935 /* 18064 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6936 /* 18068 */ // MIs[1] Operand 1
6937 /* 18068 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6938 /* 18073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6939 /* 18078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6940 /* 18083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6941 /* 18085 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6942 /* 18085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
6943 /* 18088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6944 /* 18092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6945 /* 18096 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6946 /* 18098 */ GIR_RootConstrainSelectedInstOperands,
6947 /* 18099 */ // GIR_Coverage, 1988,
6948 /* 18099 */ GIR_EraseRootFromParent_Done,
6949 /* 18100 */ // Label 670: @18100
6950 /* 18100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(18155), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1990 //
6951 /* 18107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6952 /* 18111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6953 /* 18115 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6954 /* 18119 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6955 /* 18123 */ // MIs[1] Operand 1
6956 /* 18123 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
6957 /* 18128 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6958 /* 18133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6959 /* 18138 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6960 /* 18140 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6961 /* 18140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
6962 /* 18143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6963 /* 18147 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6964 /* 18151 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6965 /* 18153 */ GIR_RootConstrainSelectedInstOperands,
6966 /* 18154 */ // GIR_Coverage, 1990,
6967 /* 18154 */ GIR_EraseRootFromParent_Done,
6968 /* 18155 */ // Label 671: @18155
6969 /* 18155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(18210), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1992 //
6970 /* 18162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6971 /* 18166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6972 /* 18170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6973 /* 18174 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6974 /* 18178 */ // MIs[1] Operand 1
6975 /* 18178 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6976 /* 18183 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6977 /* 18188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6978 /* 18193 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6979 /* 18195 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
6980 /* 18195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
6981 /* 18198 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
6982 /* 18202 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
6983 /* 18206 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
6984 /* 18208 */ GIR_RootConstrainSelectedInstOperands,
6985 /* 18209 */ // GIR_Coverage, 1992,
6986 /* 18209 */ GIR_EraseRootFromParent_Done,
6987 /* 18210 */ // Label 672: @18210
6988 /* 18210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 673*/ GIMT_Encode4(18265), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1993 //
6989 /* 18217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6990 /* 18221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6991 /* 18225 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6992 /* 18229 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6993 /* 18233 */ // MIs[1] Operand 1
6994 /* 18233 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
6995 /* 18238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6996 /* 18243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6997 /* 18248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6998 /* 18250 */ // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
6999 /* 18250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
7000 /* 18253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
7001 /* 18257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
7002 /* 18261 */ GIR_RootToRootCopy, /*OpIdx*/1, // imm16
7003 /* 18263 */ GIR_RootConstrainSelectedInstOperands,
7004 /* 18264 */ // GIR_Coverage, 1993,
7005 /* 18264 */ GIR_EraseRootFromParent_Done,
7006 /* 18265 */ // Label 673: @18265
7007 /* 18265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 674*/ GIMT_Encode4(18346), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2325 //
7008 /* 18272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7009 /* 18276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7010 /* 18280 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7011 /* 18284 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7012 /* 18288 */ // MIs[1] Operand 1
7013 /* 18288 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7014 /* 18293 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7015 /* 18298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7016 /* 18303 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7017 /* 18305 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7018 /* 18305 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7019 /* 18308 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7020 /* 18312 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7021 /* 18317 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7022 /* 18321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7023 /* 18325 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7024 /* 18327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7025 /* 18330 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7026 /* 18333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7027 /* 18339 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7028 /* 18341 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7029 /* 18344 */ GIR_RootConstrainSelectedInstOperands,
7030 /* 18345 */ // GIR_Coverage, 2325,
7031 /* 18345 */ GIR_EraseRootFromParent_Done,
7032 /* 18346 */ // Label 674: @18346
7033 /* 18346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(18427), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2326 //
7034 /* 18353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7035 /* 18357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7036 /* 18361 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7037 /* 18365 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7038 /* 18369 */ // MIs[1] Operand 1
7039 /* 18369 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7040 /* 18374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7041 /* 18379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7042 /* 18384 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7043 /* 18386 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7044 /* 18386 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7045 /* 18389 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7046 /* 18393 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7047 /* 18398 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7048 /* 18402 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7049 /* 18406 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7050 /* 18408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7051 /* 18411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7052 /* 18414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7053 /* 18420 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7054 /* 18422 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7055 /* 18425 */ GIR_RootConstrainSelectedInstOperands,
7056 /* 18426 */ // GIR_Coverage, 2326,
7057 /* 18426 */ GIR_EraseRootFromParent_Done,
7058 /* 18427 */ // Label 675: @18427
7059 /* 18427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 676*/ GIMT_Encode4(18508), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2331 //
7060 /* 18434 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7061 /* 18438 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7062 /* 18442 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7063 /* 18446 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7064 /* 18450 */ // MIs[1] Operand 1
7065 /* 18450 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7066 /* 18455 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7067 /* 18460 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7068 /* 18465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7069 /* 18467 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7070 /* 18467 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7071 /* 18470 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7072 /* 18474 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7073 /* 18479 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7074 /* 18483 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7075 /* 18487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7076 /* 18489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7077 /* 18492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7078 /* 18495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7079 /* 18501 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7080 /* 18503 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7081 /* 18506 */ GIR_RootConstrainSelectedInstOperands,
7082 /* 18507 */ // GIR_Coverage, 2331,
7083 /* 18507 */ GIR_EraseRootFromParent_Done,
7084 /* 18508 */ // Label 676: @18508
7085 /* 18508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 677*/ GIMT_Encode4(18589), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2332 //
7086 /* 18515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7087 /* 18519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7088 /* 18523 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7089 /* 18527 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7090 /* 18531 */ // MIs[1] Operand 1
7091 /* 18531 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7092 /* 18536 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7093 /* 18541 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7094 /* 18546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7095 /* 18548 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7096 /* 18548 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7097 /* 18551 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7098 /* 18555 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7099 /* 18560 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7100 /* 18564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7101 /* 18568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7102 /* 18570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
7103 /* 18573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7104 /* 18576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7105 /* 18582 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7106 /* 18584 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7107 /* 18587 */ GIR_RootConstrainSelectedInstOperands,
7108 /* 18588 */ // GIR_Coverage, 2332,
7109 /* 18588 */ GIR_EraseRootFromParent_Done,
7110 /* 18589 */ // Label 677: @18589
7111 /* 18589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 678*/ GIMT_Encode4(18664), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2477 //
7112 /* 18596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7113 /* 18600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7114 /* 18604 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7115 /* 18608 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7116 /* 18612 */ // MIs[1] Operand 1
7117 /* 18612 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
7118 /* 18617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7119 /* 18622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7120 /* 18627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7121 /* 18629 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7122 /* 18629 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7123 /* 18632 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7124 /* 18636 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7125 /* 18641 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7126 /* 18645 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7127 /* 18649 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7128 /* 18651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7129 /* 18654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7130 /* 18657 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7131 /* 18659 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7132 /* 18662 */ GIR_RootConstrainSelectedInstOperands,
7133 /* 18663 */ // GIR_Coverage, 2477,
7134 /* 18663 */ GIR_EraseRootFromParent_Done,
7135 /* 18664 */ // Label 678: @18664
7136 /* 18664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 679*/ GIMT_Encode4(18739), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2478 //
7137 /* 18671 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7138 /* 18675 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7139 /* 18679 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7140 /* 18683 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7141 /* 18687 */ // MIs[1] Operand 1
7142 /* 18687 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
7143 /* 18692 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7144 /* 18697 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7145 /* 18702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7146 /* 18704 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
7147 /* 18704 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7148 /* 18707 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7149 /* 18711 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7150 /* 18716 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7151 /* 18720 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7152 /* 18724 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7153 /* 18726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7154 /* 18729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7155 /* 18732 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7156 /* 18734 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7157 /* 18737 */ GIR_RootConstrainSelectedInstOperands,
7158 /* 18738 */ // GIR_Coverage, 2478,
7159 /* 18738 */ GIR_EraseRootFromParent_Done,
7160 /* 18739 */ // Label 679: @18739
7161 /* 18739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 680*/ GIMT_Encode4(18814), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2483 //
7162 /* 18746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7163 /* 18750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7164 /* 18754 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7165 /* 18758 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7166 /* 18762 */ // MIs[1] Operand 1
7167 /* 18762 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
7168 /* 18767 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7169 /* 18772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7170 /* 18777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7171 /* 18779 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7172 /* 18779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7173 /* 18782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
7174 /* 18786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7175 /* 18791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7176 /* 18795 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7177 /* 18799 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7178 /* 18801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7179 /* 18804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7180 /* 18807 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7181 /* 18809 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7182 /* 18812 */ GIR_RootConstrainSelectedInstOperands,
7183 /* 18813 */ // GIR_Coverage, 2483,
7184 /* 18813 */ GIR_EraseRootFromParent_Done,
7185 /* 18814 */ // Label 680: @18814
7186 /* 18814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 681*/ GIMT_Encode4(18889), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2484 //
7187 /* 18821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
7188 /* 18825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
7189 /* 18829 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7190 /* 18833 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
7191 /* 18837 */ // MIs[1] Operand 1
7192 /* 18837 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
7193 /* 18842 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7194 /* 18847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7195 /* 18852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7196 /* 18854 */ // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
7197 /* 18854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7198 /* 18857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
7199 /* 18861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7200 /* 18866 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
7201 /* 18870 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
7202 /* 18874 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7203 /* 18876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
7204 /* 18879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7205 /* 18882 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7206 /* 18884 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7207 /* 18887 */ GIR_RootConstrainSelectedInstOperands,
7208 /* 18888 */ // GIR_Coverage, 2484,
7209 /* 18888 */ GIR_EraseRootFromParent_Done,
7210 /* 18889 */ // Label 681: @18889
7211 /* 18889 */ GIM_Reject,
7212 /* 18890 */ // Label 585: @18890
7213 /* 18890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 682*/ GIMT_Encode4(18922), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1434 //
7214 /* 18897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7215 /* 18901 */ // MIs[0] dst
7216 /* 18901 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7217 /* 18904 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7218 /* 18904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
7219 /* 18907 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7220 /* 18909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7221 /* 18915 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7222 /* 18917 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7223 /* 18920 */ GIR_RootConstrainSelectedInstOperands,
7224 /* 18921 */ // GIR_Coverage, 1434,
7225 /* 18921 */ GIR_EraseRootFromParent_Done,
7226 /* 18922 */ // Label 682: @18922
7227 /* 18922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 683*/ GIMT_Encode4(18943), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1996 //
7228 /* 18929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
7229 /* 18933 */ // MIs[0] targ16
7230 /* 18933 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7231 /* 18936 */ // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
7232 /* 18936 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
7233 /* 18941 */ GIR_RootConstrainSelectedInstOperands,
7234 /* 18942 */ // GIR_Coverage, 1996,
7235 /* 18942 */ GIR_Done,
7236 /* 18943 */ // Label 683: @18943
7237 /* 18943 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(19001),
7238 /* 18948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7239 /* 18952 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7240 /* 18955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 685*/ GIMT_Encode4(18980), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2333 //
7241 /* 18962 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
7242 /* 18962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
7243 /* 18965 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7244 /* 18967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7245 /* 18973 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7246 /* 18975 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7247 /* 18978 */ GIR_RootConstrainSelectedInstOperands,
7248 /* 18979 */ // GIR_Coverage, 2333,
7249 /* 18979 */ GIR_EraseRootFromParent_Done,
7250 /* 18980 */ // Label 685: @18980
7251 /* 18980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 686*/ GIMT_Encode4(19000), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2485 //
7252 /* 18987 */ // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
7253 /* 18987 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
7254 /* 18992 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
7255 /* 18998 */ GIR_RootConstrainSelectedInstOperands,
7256 /* 18999 */ // GIR_Coverage, 2485,
7257 /* 18999 */ GIR_Done,
7258 /* 19000 */ // Label 686: @19000
7259 /* 19000 */ GIM_Reject,
7260 /* 19001 */ // Label 684: @19001
7261 /* 19001 */ GIM_Reject,
7262 /* 19002 */ // Label 583: @19002
7263 /* 19002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 687*/ GIMT_Encode4(19034), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1664 //
7264 /* 19009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
7265 /* 19013 */ // MIs[0] dst
7266 /* 19013 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
7267 /* 19016 */ // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
7268 /* 19016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
7269 /* 19019 */ GIR_RootToRootCopy, /*OpIdx*/0, // cond
7270 /* 19021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7271 /* 19027 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
7272 /* 19029 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
7273 /* 19032 */ GIR_RootConstrainSelectedInstOperands,
7274 /* 19033 */ // GIR_Coverage, 1664,
7275 /* 19033 */ GIR_EraseRootFromParent_Done,
7276 /* 19034 */ // Label 687: @19034
7277 /* 19034 */ GIM_Reject,
7278 /* 19035 */ // Label 584: @19035
7279 /* 19035 */ GIM_Reject,
7280 /* 19036 */ // Label 29: @19036
7281 /* 19036 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(20970),
7282 /* 19041 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
7283 /* 19044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 689*/ GIMT_Encode4(19090), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 456 //
7284 /* 19051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7285 /* 19056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7286 /* 19059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7287 /* 19062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7288 /* 19066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7289 /* 19070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7290 /* 19074 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7291 /* 19078 */ // MIs[1] Operand 1
7292 /* 19078 */ // No operand predicates
7293 /* 19078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7294 /* 19080 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7295 /* 19080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
7296 /* 19083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7297 /* 19085 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7298 /* 19088 */ GIR_RootConstrainSelectedInstOperands,
7299 /* 19089 */ // GIR_Coverage, 456,
7300 /* 19089 */ GIR_EraseRootFromParent_Done,
7301 /* 19090 */ // Label 689: @19090
7302 /* 19090 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(19173),
7303 /* 19095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7304 /* 19100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7305 /* 19103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7306 /* 19106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7307 /* 19110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 691*/ GIMT_Encode4(19141), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 457 //
7308 /* 19117 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7309 /* 19121 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7310 /* 19125 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7311 /* 19129 */ // MIs[1] Operand 1
7312 /* 19129 */ // No operand predicates
7313 /* 19129 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7314 /* 19131 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7315 /* 19131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
7316 /* 19134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7317 /* 19136 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7318 /* 19139 */ GIR_RootConstrainSelectedInstOperands,
7319 /* 19140 */ // GIR_Coverage, 457,
7320 /* 19140 */ GIR_EraseRootFromParent_Done,
7321 /* 19141 */ // Label 691: @19141
7322 /* 19141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 692*/ GIMT_Encode4(19172), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1310 //
7323 /* 19148 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7324 /* 19152 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7325 /* 19156 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
7326 /* 19160 */ // MIs[1] Operand 1
7327 /* 19160 */ // No operand predicates
7328 /* 19160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7329 /* 19162 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
7330 /* 19162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
7331 /* 19165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7332 /* 19167 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7333 /* 19170 */ GIR_RootConstrainSelectedInstOperands,
7334 /* 19171 */ // GIR_Coverage, 1310,
7335 /* 19171 */ GIR_EraseRootFromParent_Done,
7336 /* 19172 */ // Label 692: @19172
7337 /* 19172 */ GIM_Reject,
7338 /* 19173 */ // Label 690: @19173
7339 /* 19173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 693*/ GIMT_Encode4(19219), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1311 //
7340 /* 19180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7341 /* 19185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7342 /* 19188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7343 /* 19191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7344 /* 19195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7345 /* 19199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7346 /* 19203 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
7347 /* 19207 */ // MIs[1] Operand 1
7348 /* 19207 */ // No operand predicates
7349 /* 19207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7350 /* 19209 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
7351 /* 19209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
7352 /* 19212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7353 /* 19214 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7354 /* 19217 */ GIR_RootConstrainSelectedInstOperands,
7355 /* 19218 */ // GIR_Coverage, 1311,
7356 /* 19218 */ GIR_EraseRootFromParent_Done,
7357 /* 19219 */ // Label 693: @19219
7358 /* 19219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 694*/ GIMT_Encode4(19254), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 390 //
7359 /* 19226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7360 /* 19231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7361 /* 19234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7362 /* 19237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7363 /* 19241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7364 /* 19245 */ // (intrinsic_wo_chain:{ *:[i32] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7365 /* 19245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
7366 /* 19248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7367 /* 19250 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7368 /* 19252 */ GIR_RootConstrainSelectedInstOperands,
7369 /* 19253 */ // GIR_Coverage, 390,
7370 /* 19253 */ GIR_EraseRootFromParent_Done,
7371 /* 19254 */ // Label 694: @19254
7372 /* 19254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 695*/ GIMT_Encode4(19289), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 397 //
7373 /* 19261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7374 /* 19266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7375 /* 19269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7376 /* 19272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7377 /* 19276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7378 /* 19280 */ // (intrinsic_wo_chain:{ *:[i32] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7379 /* 19280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
7380 /* 19283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7381 /* 19285 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7382 /* 19287 */ GIR_RootConstrainSelectedInstOperands,
7383 /* 19288 */ // GIR_Coverage, 397,
7384 /* 19288 */ GIR_EraseRootFromParent_Done,
7385 /* 19289 */ // Label 695: @19289
7386 /* 19289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 696*/ GIMT_Encode4(19324), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 398 //
7387 /* 19296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7388 /* 19301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7389 /* 19304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7390 /* 19307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7391 /* 19311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7392 /* 19315 */ // (intrinsic_wo_chain:{ *:[i32] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
7393 /* 19315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
7394 /* 19318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7395 /* 19320 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7396 /* 19322 */ GIR_RootConstrainSelectedInstOperands,
7397 /* 19323 */ // GIR_Coverage, 398,
7398 /* 19323 */ GIR_EraseRootFromParent_Done,
7399 /* 19324 */ // Label 696: @19324
7400 /* 19324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 697*/ GIMT_Encode4(19359), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 399 //
7401 /* 19331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7402 /* 19336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7403 /* 19339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7404 /* 19342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7405 /* 19346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7406 /* 19350 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7407 /* 19350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
7408 /* 19353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7409 /* 19355 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7410 /* 19357 */ GIR_RootConstrainSelectedInstOperands,
7411 /* 19358 */ // GIR_Coverage, 399,
7412 /* 19358 */ GIR_EraseRootFromParent_Done,
7413 /* 19359 */ // Label 697: @19359
7414 /* 19359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 698*/ GIMT_Encode4(19394), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 400 //
7415 /* 19366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7416 /* 19371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7417 /* 19374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7418 /* 19377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7419 /* 19381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7420 /* 19385 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7421 /* 19385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
7422 /* 19388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7423 /* 19390 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7424 /* 19392 */ GIR_RootConstrainSelectedInstOperands,
7425 /* 19393 */ // GIR_Coverage, 400,
7426 /* 19393 */ GIR_EraseRootFromParent_Done,
7427 /* 19394 */ // Label 698: @19394
7428 /* 19394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 699*/ GIMT_Encode4(19429), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 401 //
7429 /* 19401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7430 /* 19406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7431 /* 19409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7432 /* 19412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7433 /* 19416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7434 /* 19420 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7435 /* 19420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
7436 /* 19423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7437 /* 19425 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7438 /* 19427 */ GIR_RootConstrainSelectedInstOperands,
7439 /* 19428 */ // GIR_Coverage, 401,
7440 /* 19428 */ GIR_EraseRootFromParent_Done,
7441 /* 19429 */ // Label 699: @19429
7442 /* 19429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 700*/ GIMT_Encode4(19464), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 402 //
7443 /* 19436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7444 /* 19441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7445 /* 19444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7446 /* 19447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7447 /* 19451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7448 /* 19455 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7449 /* 19455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
7450 /* 19458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7451 /* 19460 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7452 /* 19462 */ GIR_RootConstrainSelectedInstOperands,
7453 /* 19463 */ // GIR_Coverage, 402,
7454 /* 19463 */ GIR_EraseRootFromParent_Done,
7455 /* 19464 */ // Label 700: @19464
7456 /* 19464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 701*/ GIMT_Encode4(19499), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 403 //
7457 /* 19471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7458 /* 19476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7459 /* 19479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7460 /* 19482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7461 /* 19486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7462 /* 19490 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7463 /* 19490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
7464 /* 19493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7465 /* 19495 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7466 /* 19497 */ GIR_RootConstrainSelectedInstOperands,
7467 /* 19498 */ // GIR_Coverage, 403,
7468 /* 19498 */ GIR_EraseRootFromParent_Done,
7469 /* 19499 */ // Label 701: @19499
7470 /* 19499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 702*/ GIMT_Encode4(19534), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 404 //
7471 /* 19506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7472 /* 19511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7473 /* 19514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7474 /* 19517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7475 /* 19521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7476 /* 19525 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7477 /* 19525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
7478 /* 19528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7479 /* 19530 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7480 /* 19532 */ GIR_RootConstrainSelectedInstOperands,
7481 /* 19533 */ // GIR_Coverage, 404,
7482 /* 19533 */ GIR_EraseRootFromParent_Done,
7483 /* 19534 */ // Label 702: @19534
7484 /* 19534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 703*/ GIMT_Encode4(19569), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 405 //
7485 /* 19541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7486 /* 19546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7487 /* 19549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7488 /* 19552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7489 /* 19556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7490 /* 19560 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7491 /* 19560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
7492 /* 19563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7493 /* 19565 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7494 /* 19567 */ GIR_RootConstrainSelectedInstOperands,
7495 /* 19568 */ // GIR_Coverage, 405,
7496 /* 19568 */ GIR_EraseRootFromParent_Done,
7497 /* 19569 */ // Label 703: @19569
7498 /* 19569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 704*/ GIMT_Encode4(19604), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 406 //
7499 /* 19576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7500 /* 19581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7501 /* 19584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7502 /* 19587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7503 /* 19591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7504 /* 19595 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
7505 /* 19595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
7506 /* 19598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7507 /* 19600 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7508 /* 19602 */ GIR_RootConstrainSelectedInstOperands,
7509 /* 19603 */ // GIR_Coverage, 406,
7510 /* 19603 */ GIR_EraseRootFromParent_Done,
7511 /* 19604 */ // Label 704: @19604
7512 /* 19604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 705*/ GIMT_Encode4(19639), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 454 //
7513 /* 19611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
7514 /* 19616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7515 /* 19619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7516 /* 19622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7517 /* 19626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7518 /* 19630 */ // (intrinsic_wo_chain:{ *:[i32] } 8055:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
7519 /* 19630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
7520 /* 19633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7521 /* 19635 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7522 /* 19637 */ GIR_RootConstrainSelectedInstOperands,
7523 /* 19638 */ // GIR_Coverage, 454,
7524 /* 19638 */ GIR_EraseRootFromParent_Done,
7525 /* 19639 */ // Label 705: @19639
7526 /* 19639 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 706*/ GIMT_Encode4(19674), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 458 //
7527 /* 19646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7528 /* 19651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7529 /* 19654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7530 /* 19657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7531 /* 19661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7532 /* 19665 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
7533 /* 19665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
7534 /* 19668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7535 /* 19670 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7536 /* 19672 */ GIR_RootConstrainSelectedInstOperands,
7537 /* 19673 */ // GIR_Coverage, 458,
7538 /* 19673 */ GIR_EraseRootFromParent_Done,
7539 /* 19674 */ // Label 706: @19674
7540 /* 19674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 707*/ GIMT_Encode4(19709), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 459 //
7541 /* 19681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7542 /* 19686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7543 /* 19689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7544 /* 19692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7545 /* 19696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7546 /* 19700 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
7547 /* 19700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
7548 /* 19703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7549 /* 19705 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
7550 /* 19707 */ GIR_RootConstrainSelectedInstOperands,
7551 /* 19708 */ // GIR_Coverage, 459,
7552 /* 19708 */ GIR_EraseRootFromParent_Done,
7553 /* 19709 */ // Label 707: @19709
7554 /* 19709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 708*/ GIMT_Encode4(19744), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 708 //
7555 /* 19716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
7556 /* 19721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7557 /* 19724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7558 /* 19727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7559 /* 19731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7560 /* 19735 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8207:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7561 /* 19735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
7562 /* 19738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7563 /* 19740 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7564 /* 19742 */ GIR_RootConstrainSelectedInstOperands,
7565 /* 19743 */ // GIR_Coverage, 708,
7566 /* 19743 */ GIR_EraseRootFromParent_Done,
7567 /* 19744 */ // Label 708: @19744
7568 /* 19744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 709*/ GIMT_Encode4(19779), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 709 //
7569 /* 19751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
7570 /* 19756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7571 /* 19759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7572 /* 19762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7573 /* 19766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7574 /* 19770 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8206:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7575 /* 19770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
7576 /* 19773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7577 /* 19775 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7578 /* 19777 */ GIR_RootConstrainSelectedInstOperands,
7579 /* 19778 */ // GIR_Coverage, 709,
7580 /* 19778 */ GIR_EraseRootFromParent_Done,
7581 /* 19779 */ // Label 709: @19779
7582 /* 19779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 710*/ GIMT_Encode4(19814), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 732 //
7583 /* 19786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
7584 /* 19791 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7585 /* 19794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7586 /* 19797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7587 /* 19801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7588 /* 19805 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8233:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7589 /* 19805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
7590 /* 19808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7591 /* 19810 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7592 /* 19812 */ GIR_RootConstrainSelectedInstOperands,
7593 /* 19813 */ // GIR_Coverage, 732,
7594 /* 19813 */ GIR_EraseRootFromParent_Done,
7595 /* 19814 */ // Label 710: @19814
7596 /* 19814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 711*/ GIMT_Encode4(19849), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 733 //
7597 /* 19821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
7598 /* 19826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7599 /* 19829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7600 /* 19832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7601 /* 19836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7602 /* 19840 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8232:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7603 /* 19840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
7604 /* 19843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7605 /* 19845 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7606 /* 19847 */ GIR_RootConstrainSelectedInstOperands,
7607 /* 19848 */ // GIR_Coverage, 733,
7608 /* 19848 */ GIR_EraseRootFromParent_Done,
7609 /* 19849 */ // Label 711: @19849
7610 /* 19849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 712*/ GIMT_Encode4(19884), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 734 //
7611 /* 19856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
7612 /* 19861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7613 /* 19864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7614 /* 19867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7615 /* 19871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7616 /* 19875 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8235:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
7617 /* 19875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
7618 /* 19878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7619 /* 19880 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7620 /* 19882 */ GIR_RootConstrainSelectedInstOperands,
7621 /* 19883 */ // GIR_Coverage, 734,
7622 /* 19883 */ GIR_EraseRootFromParent_Done,
7623 /* 19884 */ // Label 712: @19884
7624 /* 19884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 713*/ GIMT_Encode4(19919), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 735 //
7625 /* 19891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
7626 /* 19896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7627 /* 19899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7628 /* 19902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7629 /* 19906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7630 /* 19910 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8234:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7631 /* 19910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
7632 /* 19913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7633 /* 19915 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7634 /* 19917 */ GIR_RootConstrainSelectedInstOperands,
7635 /* 19918 */ // GIR_Coverage, 735,
7636 /* 19918 */ GIR_EraseRootFromParent_Done,
7637 /* 19919 */ // Label 713: @19919
7638 /* 19919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 714*/ GIMT_Encode4(19954), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 740 //
7639 /* 19926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
7640 /* 19931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7641 /* 19934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7642 /* 19937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7643 /* 19941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7644 /* 19945 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8241:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7645 /* 19945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
7646 /* 19948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7647 /* 19950 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7648 /* 19952 */ GIR_RootConstrainSelectedInstOperands,
7649 /* 19953 */ // GIR_Coverage, 740,
7650 /* 19953 */ GIR_EraseRootFromParent_Done,
7651 /* 19954 */ // Label 714: @19954
7652 /* 19954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 715*/ GIMT_Encode4(19989), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 741 //
7653 /* 19961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
7654 /* 19966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7655 /* 19969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7656 /* 19972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7657 /* 19976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7658 /* 19980 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7659 /* 19980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
7660 /* 19983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7661 /* 19985 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7662 /* 19987 */ GIR_RootConstrainSelectedInstOperands,
7663 /* 19988 */ // GIR_Coverage, 741,
7664 /* 19988 */ GIR_EraseRootFromParent_Done,
7665 /* 19989 */ // Label 715: @19989
7666 /* 19989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(20024), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 742 //
7667 /* 19996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
7668 /* 20001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7669 /* 20004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7670 /* 20007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7671 /* 20011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7672 /* 20015 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8243:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7673 /* 20015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
7674 /* 20018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7675 /* 20020 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7676 /* 20022 */ GIR_RootConstrainSelectedInstOperands,
7677 /* 20023 */ // GIR_Coverage, 742,
7678 /* 20023 */ GIR_EraseRootFromParent_Done,
7679 /* 20024 */ // Label 716: @20024
7680 /* 20024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(20059), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 743 //
7681 /* 20031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
7682 /* 20036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7683 /* 20039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7684 /* 20042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7685 /* 20046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7686 /* 20050 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8242:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7687 /* 20050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
7688 /* 20053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7689 /* 20055 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7690 /* 20057 */ GIR_RootConstrainSelectedInstOperands,
7691 /* 20058 */ // GIR_Coverage, 743,
7692 /* 20058 */ GIR_EraseRootFromParent_Done,
7693 /* 20059 */ // Label 717: @20059
7694 /* 20059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 718*/ GIMT_Encode4(20094), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 768 //
7695 /* 20066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
7696 /* 20071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7697 /* 20074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7698 /* 20077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7699 /* 20081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7700 /* 20085 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8265:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7701 /* 20085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
7702 /* 20088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7703 /* 20090 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7704 /* 20092 */ GIR_RootConstrainSelectedInstOperands,
7705 /* 20093 */ // GIR_Coverage, 768,
7706 /* 20093 */ GIR_EraseRootFromParent_Done,
7707 /* 20094 */ // Label 718: @20094
7708 /* 20094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 719*/ GIMT_Encode4(20129), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 769 //
7709 /* 20101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
7710 /* 20106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7711 /* 20109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7712 /* 20112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7713 /* 20116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7714 /* 20120 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8264:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7715 /* 20120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
7716 /* 20123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7717 /* 20125 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7718 /* 20127 */ GIR_RootConstrainSelectedInstOperands,
7719 /* 20128 */ // GIR_Coverage, 769,
7720 /* 20128 */ GIR_EraseRootFromParent_Done,
7721 /* 20129 */ // Label 719: @20129
7722 /* 20129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 720*/ GIMT_Encode4(20164), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 770 //
7723 /* 20136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
7724 /* 20141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7725 /* 20144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7726 /* 20147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7727 /* 20151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7728 /* 20155 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8269:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7729 /* 20155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
7730 /* 20158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7731 /* 20160 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7732 /* 20162 */ GIR_RootConstrainSelectedInstOperands,
7733 /* 20163 */ // GIR_Coverage, 770,
7734 /* 20163 */ GIR_EraseRootFromParent_Done,
7735 /* 20164 */ // Label 720: @20164
7736 /* 20164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 721*/ GIMT_Encode4(20199), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 771 //
7737 /* 20171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
7738 /* 20176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7739 /* 20179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7740 /* 20182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7741 /* 20186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7742 /* 20190 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8268:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7743 /* 20190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
7744 /* 20193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7745 /* 20195 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7746 /* 20197 */ GIR_RootConstrainSelectedInstOperands,
7747 /* 20198 */ // GIR_Coverage, 771,
7748 /* 20198 */ GIR_EraseRootFromParent_Done,
7749 /* 20199 */ // Label 721: @20199
7750 /* 20199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 722*/ GIMT_Encode4(20234), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 798 //
7751 /* 20206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
7752 /* 20211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7753 /* 20214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7754 /* 20217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7755 /* 20221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7756 /* 20225 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8297:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7757 /* 20225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
7758 /* 20228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7759 /* 20230 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7760 /* 20232 */ GIR_RootConstrainSelectedInstOperands,
7761 /* 20233 */ // GIR_Coverage, 798,
7762 /* 20233 */ GIR_EraseRootFromParent_Done,
7763 /* 20234 */ // Label 722: @20234
7764 /* 20234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 723*/ GIMT_Encode4(20269), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 799 //
7765 /* 20241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
7766 /* 20246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7767 /* 20249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7768 /* 20252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7769 /* 20256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7770 /* 20260 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8296:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7771 /* 20260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
7772 /* 20263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7773 /* 20265 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7774 /* 20267 */ GIR_RootConstrainSelectedInstOperands,
7775 /* 20268 */ // GIR_Coverage, 799,
7776 /* 20268 */ GIR_EraseRootFromParent_Done,
7777 /* 20269 */ // Label 723: @20269
7778 /* 20269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 724*/ GIMT_Encode4(20304), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 800 //
7779 /* 20276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
7780 /* 20281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7781 /* 20284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7782 /* 20287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7783 /* 20291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7784 /* 20295 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8299:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
7785 /* 20295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
7786 /* 20298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7787 /* 20300 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7788 /* 20302 */ GIR_RootConstrainSelectedInstOperands,
7789 /* 20303 */ // GIR_Coverage, 800,
7790 /* 20303 */ GIR_EraseRootFromParent_Done,
7791 /* 20304 */ // Label 724: @20304
7792 /* 20304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 725*/ GIMT_Encode4(20339), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 801 //
7793 /* 20311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
7794 /* 20316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7795 /* 20319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7796 /* 20322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7797 /* 20326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7798 /* 20330 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8298:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
7799 /* 20330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
7800 /* 20333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7801 /* 20335 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7802 /* 20337 */ GIR_RootConstrainSelectedInstOperands,
7803 /* 20338 */ // GIR_Coverage, 801,
7804 /* 20338 */ GIR_EraseRootFromParent_Done,
7805 /* 20339 */ // Label 725: @20339
7806 /* 20339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 726*/ GIMT_Encode4(20374), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 936 //
7807 /* 20346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
7808 /* 20351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7809 /* 20354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7810 /* 20357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7811 /* 20361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7812 /* 20365 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8454:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
7813 /* 20365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
7814 /* 20368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7815 /* 20370 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7816 /* 20372 */ GIR_RootConstrainSelectedInstOperands,
7817 /* 20373 */ // GIR_Coverage, 936,
7818 /* 20373 */ GIR_EraseRootFromParent_Done,
7819 /* 20374 */ // Label 726: @20374
7820 /* 20374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 727*/ GIMT_Encode4(20409), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 937 //
7821 /* 20381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
7822 /* 20386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7823 /* 20389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7824 /* 20392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7825 /* 20396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7826 /* 20400 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8456:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
7827 /* 20400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
7828 /* 20403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7829 /* 20405 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7830 /* 20407 */ GIR_RootConstrainSelectedInstOperands,
7831 /* 20408 */ // GIR_Coverage, 937,
7832 /* 20408 */ GIR_EraseRootFromParent_Done,
7833 /* 20409 */ // Label 727: @20409
7834 /* 20409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 728*/ GIMT_Encode4(20444), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 938 //
7835 /* 20416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
7836 /* 20421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7837 /* 20424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7838 /* 20427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7839 /* 20431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7840 /* 20435 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8457:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
7841 /* 20435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
7842 /* 20438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7843 /* 20440 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7844 /* 20442 */ GIR_RootConstrainSelectedInstOperands,
7845 /* 20443 */ // GIR_Coverage, 938,
7846 /* 20443 */ GIR_EraseRootFromParent_Done,
7847 /* 20444 */ // Label 728: @20444
7848 /* 20444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 729*/ GIMT_Encode4(20479), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 939 //
7849 /* 20451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
7850 /* 20456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7851 /* 20459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7852 /* 20462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7853 /* 20466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7854 /* 20470 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8455:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
7855 /* 20470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
7856 /* 20473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7857 /* 20475 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
7858 /* 20477 */ GIR_RootConstrainSelectedInstOperands,
7859 /* 20478 */ // GIR_Coverage, 939,
7860 /* 20478 */ GIR_EraseRootFromParent_Done,
7861 /* 20479 */ // Label 729: @20479
7862 /* 20479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 730*/ GIMT_Encode4(20514), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1273 //
7863 /* 20486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
7864 /* 20491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7865 /* 20494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7866 /* 20497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7867 /* 20501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7868 /* 20505 */ // (intrinsic_wo_chain:{ *:[i32] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
7869 /* 20505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
7870 /* 20508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7871 /* 20510 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7872 /* 20512 */ GIR_RootConstrainSelectedInstOperands,
7873 /* 20513 */ // GIR_Coverage, 1273,
7874 /* 20513 */ GIR_EraseRootFromParent_Done,
7875 /* 20514 */ // Label 730: @20514
7876 /* 20514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 731*/ GIMT_Encode4(20549), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1274 //
7877 /* 20521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
7878 /* 20526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7879 /* 20529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7880 /* 20532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7881 /* 20536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7882 /* 20540 */ // (intrinsic_wo_chain:{ *:[i32] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
7883 /* 20540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
7884 /* 20543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7885 /* 20545 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7886 /* 20547 */ GIR_RootConstrainSelectedInstOperands,
7887 /* 20548 */ // GIR_Coverage, 1274,
7888 /* 20548 */ GIR_EraseRootFromParent_Done,
7889 /* 20549 */ // Label 731: @20549
7890 /* 20549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(20584), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1275 //
7891 /* 20556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
7892 /* 20561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7893 /* 20564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7894 /* 20567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7895 /* 20571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7896 /* 20575 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7897 /* 20575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
7898 /* 20578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7899 /* 20580 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7900 /* 20582 */ GIR_RootConstrainSelectedInstOperands,
7901 /* 20583 */ // GIR_Coverage, 1275,
7902 /* 20583 */ GIR_EraseRootFromParent_Done,
7903 /* 20584 */ // Label 732: @20584
7904 /* 20584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 733*/ GIMT_Encode4(20619), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1276 //
7905 /* 20591 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
7906 /* 20596 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7907 /* 20599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7908 /* 20602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7909 /* 20606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7910 /* 20610 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7911 /* 20610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
7912 /* 20613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7913 /* 20615 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7914 /* 20617 */ GIR_RootConstrainSelectedInstOperands,
7915 /* 20618 */ // GIR_Coverage, 1276,
7916 /* 20618 */ GIR_EraseRootFromParent_Done,
7917 /* 20619 */ // Label 733: @20619
7918 /* 20619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 734*/ GIMT_Encode4(20654), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1277 //
7919 /* 20626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
7920 /* 20631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7921 /* 20634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7922 /* 20637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7923 /* 20641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7924 /* 20645 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7925 /* 20645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
7926 /* 20648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7927 /* 20650 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7928 /* 20652 */ GIR_RootConstrainSelectedInstOperands,
7929 /* 20653 */ // GIR_Coverage, 1277,
7930 /* 20653 */ GIR_EraseRootFromParent_Done,
7931 /* 20654 */ // Label 734: @20654
7932 /* 20654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 735*/ GIMT_Encode4(20689), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1278 //
7933 /* 20661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
7934 /* 20666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7935 /* 20669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7936 /* 20672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7937 /* 20676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7938 /* 20680 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7939 /* 20680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
7940 /* 20683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7941 /* 20685 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7942 /* 20687 */ GIR_RootConstrainSelectedInstOperands,
7943 /* 20688 */ // GIR_Coverage, 1278,
7944 /* 20688 */ GIR_EraseRootFromParent_Done,
7945 /* 20689 */ // Label 735: @20689
7946 /* 20689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 736*/ GIMT_Encode4(20724), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1279 //
7947 /* 20696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
7948 /* 20701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7949 /* 20704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7950 /* 20707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7951 /* 20711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7952 /* 20715 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7953 /* 20715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
7954 /* 20718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7955 /* 20720 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7956 /* 20722 */ GIR_RootConstrainSelectedInstOperands,
7957 /* 20723 */ // GIR_Coverage, 1279,
7958 /* 20723 */ GIR_EraseRootFromParent_Done,
7959 /* 20724 */ // Label 736: @20724
7960 /* 20724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 737*/ GIMT_Encode4(20759), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1280 //
7961 /* 20731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7962 /* 20736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7963 /* 20739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7964 /* 20742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7965 /* 20746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7966 /* 20750 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8488:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7967 /* 20750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
7968 /* 20753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7969 /* 20755 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7970 /* 20757 */ GIR_RootConstrainSelectedInstOperands,
7971 /* 20758 */ // GIR_Coverage, 1280,
7972 /* 20758 */ GIR_EraseRootFromParent_Done,
7973 /* 20759 */ // Label 737: @20759
7974 /* 20759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 738*/ GIMT_Encode4(20794), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1281 //
7975 /* 20766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7976 /* 20771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7977 /* 20774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7978 /* 20777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7979 /* 20781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7980 /* 20785 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7981 /* 20785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
7982 /* 20788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7983 /* 20790 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7984 /* 20792 */ GIR_RootConstrainSelectedInstOperands,
7985 /* 20793 */ // GIR_Coverage, 1281,
7986 /* 20793 */ GIR_EraseRootFromParent_Done,
7987 /* 20794 */ // Label 738: @20794
7988 /* 20794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 739*/ GIMT_Encode4(20829), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1282 //
7989 /* 20801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7990 /* 20806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7991 /* 20809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7992 /* 20812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7993 /* 20816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7994 /* 20820 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8490:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7995 /* 20820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
7996 /* 20823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7997 /* 20825 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
7998 /* 20827 */ GIR_RootConstrainSelectedInstOperands,
7999 /* 20828 */ // GIR_Coverage, 1282,
8000 /* 20828 */ GIR_EraseRootFromParent_Done,
8001 /* 20829 */ // Label 739: @20829
8002 /* 20829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(20864), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1308 //
8003 /* 20836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
8004 /* 20841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8005 /* 20844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8006 /* 20847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8007 /* 20851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8008 /* 20855 */ // (intrinsic_wo_chain:{ *:[i32] } 8499:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
8009 /* 20855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
8010 /* 20858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8011 /* 20860 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8012 /* 20862 */ GIR_RootConstrainSelectedInstOperands,
8013 /* 20863 */ // GIR_Coverage, 1308,
8014 /* 20863 */ GIR_EraseRootFromParent_Done,
8015 /* 20864 */ // Label 740: @20864
8016 /* 20864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 741*/ GIMT_Encode4(20899), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1312 //
8017 /* 20871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
8018 /* 20876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8019 /* 20879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8020 /* 20882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8021 /* 20886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8022 /* 20890 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8501:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
8023 /* 20890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
8024 /* 20893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8025 /* 20895 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8026 /* 20897 */ GIR_RootConstrainSelectedInstOperands,
8027 /* 20898 */ // GIR_Coverage, 1312,
8028 /* 20898 */ GIR_EraseRootFromParent_Done,
8029 /* 20899 */ // Label 741: @20899
8030 /* 20899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 742*/ GIMT_Encode4(20934), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1313 //
8031 /* 20906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
8032 /* 20911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8033 /* 20914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8034 /* 20917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8035 /* 20921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8036 /* 20925 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8502:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
8037 /* 20925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
8038 /* 20928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8039 /* 20930 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8040 /* 20932 */ GIR_RootConstrainSelectedInstOperands,
8041 /* 20933 */ // GIR_Coverage, 1313,
8042 /* 20933 */ GIR_EraseRootFromParent_Done,
8043 /* 20934 */ // Label 742: @20934
8044 /* 20934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(20969), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1323 //
8045 /* 20941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
8046 /* 20946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8047 /* 20949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8048 /* 20952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8049 /* 20956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8050 /* 20960 */ // (intrinsic_wo_chain:{ *:[i32] } 8055:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
8051 /* 20960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
8052 /* 20963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8053 /* 20965 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8054 /* 20967 */ GIR_RootConstrainSelectedInstOperands,
8055 /* 20968 */ // GIR_Coverage, 1323,
8056 /* 20968 */ GIR_EraseRootFromParent_Done,
8057 /* 20969 */ // Label 743: @20969
8058 /* 20969 */ GIM_Reject,
8059 /* 20970 */ // Label 688: @20970
8060 /* 20970 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(30509),
8061 /* 20975 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
8062 /* 20978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(21023), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 966 //
8063 /* 20985 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
8064 /* 20990 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8065 /* 20993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8066 /* 20996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8067 /* 21000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8068 /* 21004 */ // MIs[0] m
8069 /* 21004 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8070 /* 21007 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8071 /* 21012 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8503:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8072 /* 21012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
8073 /* 21015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8074 /* 21017 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8075 /* 21019 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8076 /* 21021 */ GIR_RootConstrainSelectedInstOperands,
8077 /* 21022 */ // GIR_Coverage, 966,
8078 /* 21022 */ GIR_EraseRootFromParent_Done,
8079 /* 21023 */ // Label 745: @21023
8080 /* 21023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 746*/ GIMT_Encode4(21068), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 967 //
8081 /* 21030 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
8082 /* 21035 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8083 /* 21038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8084 /* 21041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8085 /* 21045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8086 /* 21049 */ // MIs[0] m
8087 /* 21049 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8088 /* 21052 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8089 /* 21057 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8505:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8090 /* 21057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
8091 /* 21060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8092 /* 21062 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8093 /* 21064 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8094 /* 21066 */ GIR_RootConstrainSelectedInstOperands,
8095 /* 21067 */ // GIR_Coverage, 967,
8096 /* 21067 */ GIR_EraseRootFromParent_Done,
8097 /* 21068 */ // Label 746: @21068
8098 /* 21068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 747*/ GIMT_Encode4(21113), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 968 //
8099 /* 21075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
8100 /* 21080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8101 /* 21083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8102 /* 21086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8103 /* 21090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8104 /* 21094 */ // MIs[0] m
8105 /* 21094 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8106 /* 21097 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8107 /* 21102 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8506:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8108 /* 21102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
8109 /* 21105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8110 /* 21107 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8111 /* 21109 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8112 /* 21111 */ GIR_RootConstrainSelectedInstOperands,
8113 /* 21112 */ // GIR_Coverage, 968,
8114 /* 21112 */ GIR_EraseRootFromParent_Done,
8115 /* 21113 */ // Label 747: @21113
8116 /* 21113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(21158), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 969 //
8117 /* 21120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
8118 /* 21125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8119 /* 21128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8120 /* 21131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8121 /* 21135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8122 /* 21139 */ // MIs[0] m
8123 /* 21139 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8124 /* 21142 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8125 /* 21147 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8504:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8126 /* 21147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
8127 /* 21150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8128 /* 21152 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8129 /* 21154 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8130 /* 21156 */ GIR_RootConstrainSelectedInstOperands,
8131 /* 21157 */ // GIR_Coverage, 969,
8132 /* 21157 */ GIR_EraseRootFromParent_Done,
8133 /* 21158 */ // Label 748: @21158
8134 /* 21158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(21203), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 970 //
8135 /* 21165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
8136 /* 21170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8137 /* 21173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8138 /* 21176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8139 /* 21180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8140 /* 21184 */ // MIs[0] m
8141 /* 21184 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8142 /* 21187 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8143 /* 21192 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8507:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8144 /* 21192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
8145 /* 21195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8146 /* 21197 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8147 /* 21199 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8148 /* 21201 */ GIR_RootConstrainSelectedInstOperands,
8149 /* 21202 */ // GIR_Coverage, 970,
8150 /* 21202 */ GIR_EraseRootFromParent_Done,
8151 /* 21203 */ // Label 749: @21203
8152 /* 21203 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(21248), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 971 //
8153 /* 21210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
8154 /* 21215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8155 /* 21218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8156 /* 21221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8157 /* 21225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8158 /* 21229 */ // MIs[0] m
8159 /* 21229 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8160 /* 21232 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8161 /* 21237 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8509:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8162 /* 21237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
8163 /* 21240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8164 /* 21242 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8165 /* 21244 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8166 /* 21246 */ GIR_RootConstrainSelectedInstOperands,
8167 /* 21247 */ // GIR_Coverage, 971,
8168 /* 21247 */ GIR_EraseRootFromParent_Done,
8169 /* 21248 */ // Label 750: @21248
8170 /* 21248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(21293), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 972 //
8171 /* 21255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
8172 /* 21260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8173 /* 21263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8174 /* 21266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8175 /* 21270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8176 /* 21274 */ // MIs[0] m
8177 /* 21274 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8178 /* 21277 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8179 /* 21282 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8510:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8180 /* 21282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
8181 /* 21285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8182 /* 21287 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8183 /* 21289 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8184 /* 21291 */ GIR_RootConstrainSelectedInstOperands,
8185 /* 21292 */ // GIR_Coverage, 972,
8186 /* 21292 */ GIR_EraseRootFromParent_Done,
8187 /* 21293 */ // Label 751: @21293
8188 /* 21293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(21338), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 973 //
8189 /* 21300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
8190 /* 21305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8191 /* 21308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8192 /* 21311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8193 /* 21315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8194 /* 21319 */ // MIs[0] m
8195 /* 21319 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8196 /* 21322 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8197 /* 21327 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8508:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8198 /* 21327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
8199 /* 21330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8200 /* 21332 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8201 /* 21334 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8202 /* 21336 */ GIR_RootConstrainSelectedInstOperands,
8203 /* 21337 */ // GIR_Coverage, 973,
8204 /* 21337 */ GIR_EraseRootFromParent_Done,
8205 /* 21338 */ // Label 752: @21338
8206 /* 21338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(21383), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1013 //
8207 /* 21345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
8208 /* 21350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8209 /* 21353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8210 /* 21356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8211 /* 21360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8212 /* 21364 */ // MIs[0] m
8213 /* 21364 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8214 /* 21367 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8215 /* 21372 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8216 /* 21372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
8217 /* 21375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8218 /* 21377 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8219 /* 21379 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8220 /* 21381 */ GIR_RootConstrainSelectedInstOperands,
8221 /* 21382 */ // GIR_Coverage, 1013,
8222 /* 21382 */ GIR_EraseRootFromParent_Done,
8223 /* 21383 */ // Label 753: @21383
8224 /* 21383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(21428), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1014 //
8225 /* 21390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
8226 /* 21395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8227 /* 21398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8228 /* 21401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8229 /* 21405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8230 /* 21409 */ // MIs[0] m
8231 /* 21409 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8232 /* 21412 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8233 /* 21417 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8564:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8234 /* 21417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
8235 /* 21420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8236 /* 21422 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8237 /* 21424 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8238 /* 21426 */ GIR_RootConstrainSelectedInstOperands,
8239 /* 21427 */ // GIR_Coverage, 1014,
8240 /* 21427 */ GIR_EraseRootFromParent_Done,
8241 /* 21428 */ // Label 754: @21428
8242 /* 21428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 755*/ GIMT_Encode4(21473), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1015 //
8243 /* 21435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
8244 /* 21440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8245 /* 21443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8246 /* 21446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8247 /* 21450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8248 /* 21454 */ // MIs[0] m
8249 /* 21454 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8250 /* 21457 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8251 /* 21462 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8565:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8252 /* 21462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
8253 /* 21465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8254 /* 21467 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8255 /* 21469 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8256 /* 21471 */ GIR_RootConstrainSelectedInstOperands,
8257 /* 21472 */ // GIR_Coverage, 1015,
8258 /* 21472 */ GIR_EraseRootFromParent_Done,
8259 /* 21473 */ // Label 755: @21473
8260 /* 21473 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 756*/ GIMT_Encode4(21518), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1016 //
8261 /* 21480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
8262 /* 21485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8263 /* 21488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8264 /* 21491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8265 /* 21495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8266 /* 21499 */ // MIs[0] m
8267 /* 21499 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8268 /* 21502 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8269 /* 21507 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8270 /* 21507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
8271 /* 21510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8272 /* 21512 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8273 /* 21514 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8274 /* 21516 */ GIR_RootConstrainSelectedInstOperands,
8275 /* 21517 */ // GIR_Coverage, 1016,
8276 /* 21517 */ GIR_EraseRootFromParent_Done,
8277 /* 21518 */ // Label 756: @21518
8278 /* 21518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(21563), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1029 //
8279 /* 21525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
8280 /* 21530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8281 /* 21533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8282 /* 21536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8283 /* 21540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8284 /* 21544 */ // MIs[0] m
8285 /* 21544 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8286 /* 21547 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
8287 /* 21552 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8578:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
8288 /* 21552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
8289 /* 21555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8290 /* 21557 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8291 /* 21559 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8292 /* 21561 */ GIR_RootConstrainSelectedInstOperands,
8293 /* 21562 */ // GIR_Coverage, 1029,
8294 /* 21562 */ GIR_EraseRootFromParent_Done,
8295 /* 21563 */ // Label 757: @21563
8296 /* 21563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(21608), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1030 //
8297 /* 21570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
8298 /* 21575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8299 /* 21578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8300 /* 21581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8301 /* 21585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8302 /* 21589 */ // MIs[0] m
8303 /* 21589 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8304 /* 21592 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
8305 /* 21597 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8580:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
8306 /* 21597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
8307 /* 21600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8308 /* 21602 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8309 /* 21604 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8310 /* 21606 */ GIR_RootConstrainSelectedInstOperands,
8311 /* 21607 */ // GIR_Coverage, 1030,
8312 /* 21607 */ GIR_EraseRootFromParent_Done,
8313 /* 21608 */ // Label 758: @21608
8314 /* 21608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(21653), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1031 //
8315 /* 21615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
8316 /* 21620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8317 /* 21623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8318 /* 21626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8319 /* 21630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8320 /* 21634 */ // MIs[0] m
8321 /* 21634 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8322 /* 21637 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
8323 /* 21642 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8581:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
8324 /* 21642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
8325 /* 21645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8326 /* 21647 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8327 /* 21649 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8328 /* 21651 */ GIR_RootConstrainSelectedInstOperands,
8329 /* 21652 */ // GIR_Coverage, 1031,
8330 /* 21652 */ GIR_EraseRootFromParent_Done,
8331 /* 21653 */ // Label 759: @21653
8332 /* 21653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(21698), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1032 //
8333 /* 21660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
8334 /* 21665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8335 /* 21668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8336 /* 21671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8337 /* 21675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8338 /* 21679 */ // MIs[0] m
8339 /* 21679 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
8340 /* 21682 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
8341 /* 21687 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8579:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
8342 /* 21687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
8343 /* 21690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8344 /* 21692 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
8345 /* 21694 */ GIR_RootToRootCopy, /*OpIdx*/3, // m
8346 /* 21696 */ GIR_RootConstrainSelectedInstOperands,
8347 /* 21697 */ // GIR_Coverage, 1032,
8348 /* 21697 */ GIR_EraseRootFromParent_Done,
8349 /* 21698 */ // Label 760: @21698
8350 /* 21698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(21753), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 413 //
8351 /* 21705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8352 /* 21710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8353 /* 21713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8354 /* 21716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8355 /* 21719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8356 /* 21723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8357 /* 21727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8358 /* 21731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8359 /* 21735 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8360 /* 21739 */ // MIs[1] Operand 1
8361 /* 21739 */ // No operand predicates
8362 /* 21739 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8363 /* 21741 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8364 /* 21741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
8365 /* 21744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8366 /* 21746 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8367 /* 21748 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8368 /* 21751 */ GIR_RootConstrainSelectedInstOperands,
8369 /* 21752 */ // GIR_Coverage, 413,
8370 /* 21752 */ GIR_EraseRootFromParent_Done,
8371 /* 21753 */ // Label 761: @21753
8372 /* 21753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(21808), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 417 //
8373 /* 21760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8374 /* 21765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8375 /* 21768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8376 /* 21771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8377 /* 21774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8378 /* 21778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8379 /* 21782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8380 /* 21786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8381 /* 21790 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8382 /* 21794 */ // MIs[1] Operand 1
8383 /* 21794 */ // No operand predicates
8384 /* 21794 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8385 /* 21796 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8386 /* 21796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
8387 /* 21799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8388 /* 21801 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8389 /* 21803 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8390 /* 21806 */ GIR_RootConstrainSelectedInstOperands,
8391 /* 21807 */ // GIR_Coverage, 417,
8392 /* 21807 */ GIR_EraseRootFromParent_Done,
8393 /* 21808 */ // Label 762: @21808
8394 /* 21808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(21863), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 508 //
8395 /* 21815 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8396 /* 21820 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8397 /* 21823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8398 /* 21826 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8399 /* 21829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8400 /* 21833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8401 /* 21837 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8402 /* 21841 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8403 /* 21845 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8404 /* 21849 */ // MIs[1] Operand 1
8405 /* 21849 */ // No operand predicates
8406 /* 21849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8407 /* 21851 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
8408 /* 21851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
8409 /* 21854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8410 /* 21856 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8411 /* 21858 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
8412 /* 21861 */ GIR_RootConstrainSelectedInstOperands,
8413 /* 21862 */ // GIR_Coverage, 508,
8414 /* 21862 */ GIR_EraseRootFromParent_Done,
8415 /* 21863 */ // Label 763: @21863
8416 /* 21863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 764*/ GIMT_Encode4(21918), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1267 //
8417 /* 21870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8418 /* 21875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8419 /* 21878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8420 /* 21881 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8421 /* 21884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8422 /* 21888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8423 /* 21892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8424 /* 21896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8425 /* 21900 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8426 /* 21904 */ // MIs[1] Operand 1
8427 /* 21904 */ // No operand predicates
8428 /* 21904 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8429 /* 21906 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
8430 /* 21906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
8431 /* 21909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8432 /* 21911 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8433 /* 21913 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8434 /* 21916 */ GIR_RootConstrainSelectedInstOperands,
8435 /* 21917 */ // GIR_Coverage, 1267,
8436 /* 21917 */ GIR_EraseRootFromParent_Done,
8437 /* 21918 */ // Label 764: @21918
8438 /* 21918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 765*/ GIMT_Encode4(21973), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1271 //
8439 /* 21925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8440 /* 21930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8441 /* 21933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8442 /* 21936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8443 /* 21939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8444 /* 21943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8445 /* 21947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8446 /* 21951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8447 /* 21955 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
8448 /* 21959 */ // MIs[1] Operand 1
8449 /* 21959 */ // No operand predicates
8450 /* 21959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8451 /* 21961 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
8452 /* 21961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
8453 /* 21964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8454 /* 21966 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8455 /* 21968 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8456 /* 21971 */ GIR_RootConstrainSelectedInstOperands,
8457 /* 21972 */ // GIR_Coverage, 1271,
8458 /* 21972 */ GIR_EraseRootFromParent_Done,
8459 /* 21973 */ // Label 765: @21973
8460 /* 21973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 766*/ GIMT_Encode4(22028), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1346 //
8461 /* 21980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8462 /* 21985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8463 /* 21988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8464 /* 21991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8465 /* 21994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8466 /* 21998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8467 /* 22002 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8468 /* 22006 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8469 /* 22010 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8470 /* 22014 */ // MIs[1] Operand 1
8471 /* 22014 */ // No operand predicates
8472 /* 22014 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8473 /* 22016 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
8474 /* 22016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
8475 /* 22019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
8476 /* 22021 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8477 /* 22023 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
8478 /* 22026 */ GIR_RootConstrainSelectedInstOperands,
8479 /* 22027 */ // GIR_Coverage, 1346,
8480 /* 22027 */ GIR_EraseRootFromParent_Done,
8481 /* 22028 */ // Label 766: @22028
8482 /* 22028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 767*/ GIMT_Encode4(22079), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2073 //
8483 /* 22035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8484 /* 22040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8485 /* 22043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8486 /* 22046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8487 /* 22049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8488 /* 22053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8489 /* 22057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8490 /* 22061 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8491 /* 22065 */ // MIs[1] Operand 1
8492 /* 22065 */ // No operand predicates
8493 /* 22065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8494 /* 22067 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8495 /* 22067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
8496 /* 22070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8497 /* 22072 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8498 /* 22074 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8499 /* 22077 */ GIR_RootConstrainSelectedInstOperands,
8500 /* 22078 */ // GIR_Coverage, 2073,
8501 /* 22078 */ GIR_EraseRootFromParent_Done,
8502 /* 22079 */ // Label 767: @22079
8503 /* 22079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 768*/ GIMT_Encode4(22130), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2074 //
8504 /* 22086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8505 /* 22091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8506 /* 22094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8507 /* 22097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8508 /* 22100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8509 /* 22104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8510 /* 22108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8511 /* 22112 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
8512 /* 22116 */ // MIs[1] Operand 1
8513 /* 22116 */ // No operand predicates
8514 /* 22116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8515 /* 22118 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
8516 /* 22118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
8517 /* 22121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8518 /* 22123 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8519 /* 22125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8520 /* 22128 */ GIR_RootConstrainSelectedInstOperands,
8521 /* 22129 */ // GIR_Coverage, 2074,
8522 /* 22129 */ GIR_EraseRootFromParent_Done,
8523 /* 22130 */ // Label 768: @22130
8524 /* 22130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 769*/ GIMT_Encode4(22181), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2079 //
8525 /* 22137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8526 /* 22142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8527 /* 22145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8528 /* 22148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8529 /* 22151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8530 /* 22155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8531 /* 22159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8532 /* 22163 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8533 /* 22167 */ // MIs[1] Operand 1
8534 /* 22167 */ // No operand predicates
8535 /* 22167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8536 /* 22169 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8537 /* 22169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
8538 /* 22172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8539 /* 22174 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8540 /* 22176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8541 /* 22179 */ GIR_RootConstrainSelectedInstOperands,
8542 /* 22180 */ // GIR_Coverage, 2079,
8543 /* 22180 */ GIR_EraseRootFromParent_Done,
8544 /* 22181 */ // Label 769: @22181
8545 /* 22181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(22232), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2080 //
8546 /* 22188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8547 /* 22193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8548 /* 22196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8549 /* 22199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8550 /* 22202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8551 /* 22206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
8552 /* 22210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8553 /* 22214 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
8554 /* 22218 */ // MIs[1] Operand 1
8555 /* 22218 */ // No operand predicates
8556 /* 22218 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8557 /* 22220 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
8558 /* 22220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
8559 /* 22223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8560 /* 22225 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
8561 /* 22227 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
8562 /* 22230 */ GIR_RootConstrainSelectedInstOperands,
8563 /* 22231 */ // GIR_Coverage, 2080,
8564 /* 22231 */ GIR_EraseRootFromParent_Done,
8565 /* 22232 */ // Label 770: @22232
8566 /* 22232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(22279), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 383 //
8567 /* 22239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
8568 /* 22244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8569 /* 22247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8570 /* 22250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8571 /* 22253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8572 /* 22257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8573 /* 22261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8574 /* 22265 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8575 /* 22265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
8576 /* 22268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8577 /* 22270 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8578 /* 22272 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8579 /* 22274 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8580 /* 22277 */ GIR_RootConstrainSelectedInstOperands,
8581 /* 22278 */ // GIR_Coverage, 383,
8582 /* 22278 */ GIR_EraseRootFromParent_Done,
8583 /* 22279 */ // Label 771: @22279
8584 /* 22279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(22326), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 384 //
8585 /* 22286 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
8586 /* 22291 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8587 /* 22294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8588 /* 22297 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8589 /* 22300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8590 /* 22304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8591 /* 22308 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8592 /* 22312 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8593 /* 22312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
8594 /* 22315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8595 /* 22317 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8596 /* 22319 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8597 /* 22321 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8598 /* 22324 */ GIR_RootConstrainSelectedInstOperands,
8599 /* 22325 */ // GIR_Coverage, 384,
8600 /* 22325 */ GIR_EraseRootFromParent_Done,
8601 /* 22326 */ // Label 772: @22326
8602 /* 22326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 773*/ GIMT_Encode4(22373), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 385 //
8603 /* 22333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
8604 /* 22338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8605 /* 22341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8606 /* 22344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8607 /* 22347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8608 /* 22351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8609 /* 22355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8610 /* 22359 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7969:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8611 /* 22359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
8612 /* 22362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8613 /* 22364 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8614 /* 22366 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8615 /* 22368 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8616 /* 22371 */ GIR_RootConstrainSelectedInstOperands,
8617 /* 22372 */ // GIR_Coverage, 385,
8618 /* 22372 */ GIR_EraseRootFromParent_Done,
8619 /* 22373 */ // Label 773: @22373
8620 /* 22373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 774*/ GIMT_Encode4(22420), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 386 //
8621 /* 22380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
8622 /* 22385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8623 /* 22388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8624 /* 22391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8625 /* 22394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8626 /* 22398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8627 /* 22402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8628 /* 22406 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8589:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8629 /* 22406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
8630 /* 22409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8631 /* 22411 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8632 /* 22413 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8633 /* 22415 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
8634 /* 22418 */ GIR_RootConstrainSelectedInstOperands,
8635 /* 22419 */ // GIR_Coverage, 386,
8636 /* 22419 */ GIR_EraseRootFromParent_Done,
8637 /* 22420 */ // Label 774: @22420
8638 /* 22420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(22464), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 389 //
8639 /* 22427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
8640 /* 22432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8641 /* 22435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8642 /* 22438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8643 /* 22441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8644 /* 22445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8645 /* 22449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8646 /* 22453 */ // (intrinsic_wo_chain:{ *:[i32] } 8419:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8647 /* 22453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
8648 /* 22456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8649 /* 22458 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8650 /* 22460 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8651 /* 22462 */ GIR_RootConstrainSelectedInstOperands,
8652 /* 22463 */ // GIR_Coverage, 389,
8653 /* 22463 */ GIR_EraseRootFromParent_Done,
8654 /* 22464 */ // Label 775: @22464
8655 /* 22464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(22508), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 393 //
8656 /* 22471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
8657 /* 22476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8658 /* 22479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8659 /* 22482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8660 /* 22485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8661 /* 22489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8662 /* 22493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8663 /* 22497 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8664 /* 22497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
8665 /* 22500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8666 /* 22502 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8667 /* 22504 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8668 /* 22506 */ GIR_RootConstrainSelectedInstOperands,
8669 /* 22507 */ // GIR_Coverage, 393,
8670 /* 22507 */ GIR_EraseRootFromParent_Done,
8671 /* 22508 */ // Label 776: @22508
8672 /* 22508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(22552), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 394 //
8673 /* 22515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
8674 /* 22520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8675 /* 22523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8676 /* 22526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8677 /* 22529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8678 /* 22533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8679 /* 22537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8680 /* 22541 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8681 /* 22541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
8682 /* 22544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8683 /* 22546 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8684 /* 22548 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8685 /* 22550 */ GIR_RootConstrainSelectedInstOperands,
8686 /* 22551 */ // GIR_Coverage, 394,
8687 /* 22551 */ GIR_EraseRootFromParent_Done,
8688 /* 22552 */ // Label 777: @22552
8689 /* 22552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 778*/ GIMT_Encode4(22596), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 408 //
8690 /* 22559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
8691 /* 22564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8692 /* 22567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8693 /* 22570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8694 /* 22573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8695 /* 22577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8696 /* 22581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8697 /* 22585 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8698 /* 22585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
8699 /* 22588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8700 /* 22590 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8701 /* 22592 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8702 /* 22594 */ GIR_RootConstrainSelectedInstOperands,
8703 /* 22595 */ // GIR_Coverage, 408,
8704 /* 22595 */ GIR_EraseRootFromParent_Done,
8705 /* 22596 */ // Label 778: @22596
8706 /* 22596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 779*/ GIMT_Encode4(22640), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 412 //
8707 /* 22603 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
8708 /* 22608 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8709 /* 22611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8710 /* 22614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8711 /* 22617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8712 /* 22621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8713 /* 22625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8714 /* 22629 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8715 /* 22629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
8716 /* 22632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8717 /* 22634 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8718 /* 22636 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8719 /* 22638 */ GIR_RootConstrainSelectedInstOperands,
8720 /* 22639 */ // GIR_Coverage, 412,
8721 /* 22639 */ GIR_EraseRootFromParent_Done,
8722 /* 22640 */ // Label 779: @22640
8723 /* 22640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(22684), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 414 //
8724 /* 22647 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
8725 /* 22652 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8726 /* 22655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8727 /* 22658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8728 /* 22661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8729 /* 22665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8730 /* 22669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8731 /* 22673 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8732 /* 22673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
8733 /* 22676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8734 /* 22678 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8735 /* 22680 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8736 /* 22682 */ GIR_RootConstrainSelectedInstOperands,
8737 /* 22683 */ // GIR_Coverage, 414,
8738 /* 22683 */ GIR_EraseRootFromParent_Done,
8739 /* 22684 */ // Label 780: @22684
8740 /* 22684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(22728), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 418 //
8741 /* 22691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
8742 /* 22696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8743 /* 22699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8744 /* 22702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8745 /* 22705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8746 /* 22709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8747 /* 22713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8748 /* 22717 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8749 /* 22717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
8750 /* 22720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8751 /* 22722 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8752 /* 22724 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8753 /* 22726 */ GIR_RootConstrainSelectedInstOperands,
8754 /* 22727 */ // GIR_Coverage, 418,
8755 /* 22727 */ GIR_EraseRootFromParent_Done,
8756 /* 22728 */ // Label 781: @22728
8757 /* 22728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(22772), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 455 //
8758 /* 22735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
8759 /* 22740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8760 /* 22743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8761 /* 22746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8762 /* 22749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8763 /* 22753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8764 /* 22757 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8765 /* 22761 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8766 /* 22761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
8767 /* 22764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8768 /* 22766 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8769 /* 22768 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8770 /* 22770 */ GIR_RootConstrainSelectedInstOperands,
8771 /* 22771 */ // GIR_Coverage, 455,
8772 /* 22771 */ GIR_EraseRootFromParent_Done,
8773 /* 22772 */ // Label 782: @22772
8774 /* 22772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 783*/ GIMT_Encode4(22816), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 479 //
8775 /* 22779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
8776 /* 22784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8777 /* 22787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8778 /* 22790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8779 /* 22793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8780 /* 22797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8781 /* 22801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8782 /* 22805 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7992:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8783 /* 22805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
8784 /* 22808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8785 /* 22810 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8786 /* 22812 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8787 /* 22814 */ GIR_RootConstrainSelectedInstOperands,
8788 /* 22815 */ // GIR_Coverage, 479,
8789 /* 22815 */ GIR_EraseRootFromParent_Done,
8790 /* 22816 */ // Label 783: @22816
8791 /* 22816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 784*/ GIMT_Encode4(22860), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 480 //
8792 /* 22823 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
8793 /* 22828 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8794 /* 22831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8795 /* 22834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8796 /* 22837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8797 /* 22841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8798 /* 22845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8799 /* 22849 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8800 /* 22849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
8801 /* 22852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8802 /* 22854 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8803 /* 22856 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8804 /* 22858 */ GIR_RootConstrainSelectedInstOperands,
8805 /* 22859 */ // GIR_Coverage, 480,
8806 /* 22859 */ GIR_EraseRootFromParent_Done,
8807 /* 22860 */ // Label 784: @22860
8808 /* 22860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 785*/ GIMT_Encode4(22904), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 481 //
8809 /* 22867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
8810 /* 22872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8811 /* 22875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8812 /* 22878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8813 /* 22881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8814 /* 22885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8815 /* 22889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8816 /* 22893 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8615:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8817 /* 22893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
8818 /* 22896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8819 /* 22898 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8820 /* 22900 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8821 /* 22902 */ GIR_RootConstrainSelectedInstOperands,
8822 /* 22903 */ // GIR_Coverage, 481,
8823 /* 22903 */ GIR_EraseRootFromParent_Done,
8824 /* 22904 */ // Label 785: @22904
8825 /* 22904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 786*/ GIMT_Encode4(22948), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 482 //
8826 /* 22911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
8827 /* 22916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8828 /* 22919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8829 /* 22922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
8830 /* 22925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8831 /* 22929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8832 /* 22933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8833 /* 22937 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8616:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
8834 /* 22937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
8835 /* 22940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8836 /* 22942 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8837 /* 22944 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8838 /* 22946 */ GIR_RootConstrainSelectedInstOperands,
8839 /* 22947 */ // GIR_Coverage, 482,
8840 /* 22947 */ GIR_EraseRootFromParent_Done,
8841 /* 22948 */ // Label 786: @22948
8842 /* 22948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 787*/ GIMT_Encode4(22992), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 483 //
8843 /* 22955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
8844 /* 22960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8845 /* 22963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8846 /* 22966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8847 /* 22969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8848 /* 22973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8849 /* 22977 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8850 /* 22981 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7971:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8851 /* 22981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
8852 /* 22984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8853 /* 22986 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8854 /* 22988 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8855 /* 22990 */ GIR_RootConstrainSelectedInstOperands,
8856 /* 22991 */ // GIR_Coverage, 483,
8857 /* 22991 */ GIR_EraseRootFromParent_Done,
8858 /* 22992 */ // Label 787: @22992
8859 /* 22992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 788*/ GIMT_Encode4(23036), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 484 //
8860 /* 22999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
8861 /* 23004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8862 /* 23007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8863 /* 23010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8864 /* 23013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8865 /* 23017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8866 /* 23021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8867 /* 23025 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8868 /* 23025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
8869 /* 23028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8870 /* 23030 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8871 /* 23032 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8872 /* 23034 */ GIR_RootConstrainSelectedInstOperands,
8873 /* 23035 */ // GIR_Coverage, 484,
8874 /* 23035 */ GIR_EraseRootFromParent_Done,
8875 /* 23036 */ // Label 788: @23036
8876 /* 23036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(23080), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 485 //
8877 /* 23043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
8878 /* 23048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8879 /* 23051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8880 /* 23054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8881 /* 23057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8882 /* 23061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8883 /* 23065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8884 /* 23069 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8591:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8885 /* 23069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
8886 /* 23072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8887 /* 23074 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8888 /* 23076 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8889 /* 23078 */ GIR_RootConstrainSelectedInstOperands,
8890 /* 23079 */ // GIR_Coverage, 485,
8891 /* 23079 */ GIR_EraseRootFromParent_Done,
8892 /* 23080 */ // Label 789: @23080
8893 /* 23080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(23124), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 486 //
8894 /* 23087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
8895 /* 23092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8896 /* 23095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8897 /* 23098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
8898 /* 23101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8899 /* 23105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8900 /* 23109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8901 /* 23113 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
8902 /* 23113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
8903 /* 23116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8904 /* 23118 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8905 /* 23120 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8906 /* 23122 */ GIR_RootConstrainSelectedInstOperands,
8907 /* 23123 */ // GIR_Coverage, 486,
8908 /* 23123 */ GIR_EraseRootFromParent_Done,
8909 /* 23124 */ // Label 790: @23124
8910 /* 23124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(23168), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 487 //
8911 /* 23131 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
8912 /* 23136 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8913 /* 23139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8914 /* 23142 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8915 /* 23145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8916 /* 23149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8917 /* 23153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8918 /* 23157 */ // (intrinsic_wo_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8919 /* 23157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
8920 /* 23160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8921 /* 23162 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8922 /* 23164 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8923 /* 23166 */ GIR_RootConstrainSelectedInstOperands,
8924 /* 23167 */ // GIR_Coverage, 487,
8925 /* 23167 */ GIR_EraseRootFromParent_Done,
8926 /* 23168 */ // Label 791: @23168
8927 /* 23168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 792*/ GIMT_Encode4(23212), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 488 //
8928 /* 23175 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
8929 /* 23180 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8930 /* 23183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8931 /* 23186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8932 /* 23189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8933 /* 23193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8934 /* 23197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8935 /* 23201 */ // (intrinsic_wo_chain:{ *:[i32] } 7973:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8936 /* 23201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
8937 /* 23204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8938 /* 23206 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8939 /* 23208 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8940 /* 23210 */ GIR_RootConstrainSelectedInstOperands,
8941 /* 23211 */ // GIR_Coverage, 488,
8942 /* 23211 */ GIR_EraseRootFromParent_Done,
8943 /* 23212 */ // Label 792: @23212
8944 /* 23212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 793*/ GIMT_Encode4(23256), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 489 //
8945 /* 23219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
8946 /* 23224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8947 /* 23227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8948 /* 23230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8949 /* 23233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8950 /* 23237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8951 /* 23241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8952 /* 23245 */ // (intrinsic_wo_chain:{ *:[i32] } 8594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8953 /* 23245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
8954 /* 23248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8955 /* 23250 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8956 /* 23252 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8957 /* 23254 */ GIR_RootConstrainSelectedInstOperands,
8958 /* 23255 */ // GIR_Coverage, 489,
8959 /* 23255 */ GIR_EraseRootFromParent_Done,
8960 /* 23256 */ // Label 793: @23256
8961 /* 23256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(23300), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 490 //
8962 /* 23263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
8963 /* 23268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8964 /* 23271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8965 /* 23274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8966 /* 23277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8967 /* 23281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8968 /* 23285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8969 /* 23289 */ // (intrinsic_wo_chain:{ *:[i32] } 8593:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8970 /* 23289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
8971 /* 23292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8972 /* 23294 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
8973 /* 23296 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
8974 /* 23298 */ GIR_RootConstrainSelectedInstOperands,
8975 /* 23299 */ // GIR_Coverage, 490,
8976 /* 23299 */ GIR_EraseRootFromParent_Done,
8977 /* 23300 */ // Label 794: @23300
8978 /* 23300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(23344), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 507 //
8979 /* 23307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8980 /* 23312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8981 /* 23315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8982 /* 23318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8983 /* 23321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8984 /* 23325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8985 /* 23329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8986 /* 23333 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8987 /* 23333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
8988 /* 23336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8989 /* 23338 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
8990 /* 23340 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8991 /* 23342 */ GIR_RootConstrainSelectedInstOperands,
8992 /* 23343 */ // GIR_Coverage, 507,
8993 /* 23343 */ GIR_EraseRootFromParent_Done,
8994 /* 23344 */ // Label 795: @23344
8995 /* 23344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(23388), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 509 //
8996 /* 23351 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8997 /* 23356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8998 /* 23359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8999 /* 23362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9000 /* 23365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9001 /* 23369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9002 /* 23373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9003 /* 23377 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9004 /* 23377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
9005 /* 23380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9006 /* 23382 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9007 /* 23384 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9008 /* 23386 */ GIR_RootConstrainSelectedInstOperands,
9009 /* 23387 */ // GIR_Coverage, 509,
9010 /* 23387 */ GIR_EraseRootFromParent_Done,
9011 /* 23388 */ // Label 796: @23388
9012 /* 23388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 797*/ GIMT_Encode4(23432), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 510 //
9013 /* 23395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
9014 /* 23400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
9015 /* 23403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
9016 /* 23406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
9017 /* 23409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9018 /* 23413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
9019 /* 23417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
9020 /* 23421 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
9021 /* 23421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
9022 /* 23424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
9023 /* 23426 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
9024 /* 23428 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
9025 /* 23430 */ GIR_RootConstrainSelectedInstOperands,
9026 /* 23431 */ // GIR_Coverage, 510,
9027 /* 23431 */ GIR_EraseRootFromParent_Done,
9028 /* 23432 */ // Label 797: @23432
9029 /* 23432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 798*/ GIMT_Encode4(23476), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 519 //
9030 /* 23439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
9031 /* 23444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9032 /* 23447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9033 /* 23450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9034 /* 23453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9035 /* 23457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9036 /* 23461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9037 /* 23465 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7964:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9038 /* 23465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
9039 /* 23468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9040 /* 23470 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9041 /* 23472 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9042 /* 23474 */ GIR_RootConstrainSelectedInstOperands,
9043 /* 23475 */ // GIR_Coverage, 519,
9044 /* 23475 */ GIR_EraseRootFromParent_Done,
9045 /* 23476 */ // Label 798: @23476
9046 /* 23476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(23520), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 520 //
9047 /* 23483 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
9048 /* 23488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9049 /* 23491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9050 /* 23494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9051 /* 23497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9052 /* 23501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9053 /* 23505 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9054 /* 23509 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7966:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9055 /* 23509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
9056 /* 23512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9057 /* 23514 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9058 /* 23516 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9059 /* 23518 */ GIR_RootConstrainSelectedInstOperands,
9060 /* 23519 */ // GIR_Coverage, 520,
9061 /* 23519 */ GIR_EraseRootFromParent_Done,
9062 /* 23520 */ // Label 799: @23520
9063 /* 23520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(23564), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 521 //
9064 /* 23527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
9065 /* 23532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9066 /* 23535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9067 /* 23538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9068 /* 23541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9069 /* 23545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9070 /* 23549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9071 /* 23553 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7967:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9072 /* 23553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
9073 /* 23556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9074 /* 23558 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9075 /* 23560 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9076 /* 23562 */ GIR_RootConstrainSelectedInstOperands,
9077 /* 23563 */ // GIR_Coverage, 521,
9078 /* 23563 */ GIR_EraseRootFromParent_Done,
9079 /* 23564 */ // Label 800: @23564
9080 /* 23564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(23608), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 522 //
9081 /* 23571 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
9082 /* 23576 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9083 /* 23579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9084 /* 23582 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9085 /* 23585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9086 /* 23589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9087 /* 23593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9088 /* 23597 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7965:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9089 /* 23597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
9090 /* 23600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9091 /* 23602 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9092 /* 23604 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9093 /* 23606 */ GIR_RootConstrainSelectedInstOperands,
9094 /* 23607 */ // GIR_Coverage, 522,
9095 /* 23607 */ GIR_EraseRootFromParent_Done,
9096 /* 23608 */ // Label 801: @23608
9097 /* 23608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 802*/ GIMT_Encode4(23652), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 523 //
9098 /* 23615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
9099 /* 23620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9100 /* 23623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9101 /* 23626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9102 /* 23629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9103 /* 23633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9104 /* 23637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9105 /* 23641 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7975:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9106 /* 23641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
9107 /* 23644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9108 /* 23646 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9109 /* 23648 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9110 /* 23650 */ GIR_RootConstrainSelectedInstOperands,
9111 /* 23651 */ // GIR_Coverage, 523,
9112 /* 23651 */ GIR_EraseRootFromParent_Done,
9113 /* 23652 */ // Label 802: @23652
9114 /* 23652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 803*/ GIMT_Encode4(23696), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 524 //
9115 /* 23659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
9116 /* 23664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9117 /* 23667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9118 /* 23670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9119 /* 23673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9120 /* 23677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9121 /* 23681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9122 /* 23685 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7977:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9123 /* 23685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
9124 /* 23688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9125 /* 23690 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9126 /* 23692 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9127 /* 23694 */ GIR_RootConstrainSelectedInstOperands,
9128 /* 23695 */ // GIR_Coverage, 524,
9129 /* 23695 */ GIR_EraseRootFromParent_Done,
9130 /* 23696 */ // Label 803: @23696
9131 /* 23696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(23740), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 525 //
9132 /* 23703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
9133 /* 23708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9134 /* 23711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9135 /* 23714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9136 /* 23717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9137 /* 23721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9138 /* 23725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9139 /* 23729 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7978:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9140 /* 23729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
9141 /* 23732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9142 /* 23734 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9143 /* 23736 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9144 /* 23738 */ GIR_RootConstrainSelectedInstOperands,
9145 /* 23739 */ // GIR_Coverage, 525,
9146 /* 23739 */ GIR_EraseRootFromParent_Done,
9147 /* 23740 */ // Label 804: @23740
9148 /* 23740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(23784), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 526 //
9149 /* 23747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
9150 /* 23752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9151 /* 23755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9152 /* 23758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9153 /* 23761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9154 /* 23765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9155 /* 23769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9156 /* 23773 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7976:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9157 /* 23773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
9158 /* 23776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9159 /* 23778 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9160 /* 23780 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9161 /* 23782 */ GIR_RootConstrainSelectedInstOperands,
9162 /* 23783 */ // GIR_Coverage, 526,
9163 /* 23783 */ GIR_EraseRootFromParent_Done,
9164 /* 23784 */ // Label 805: @23784
9165 /* 23784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(23828), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 527 //
9166 /* 23791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
9167 /* 23796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9168 /* 23799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9169 /* 23802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9170 /* 23805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9171 /* 23809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9172 /* 23813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9173 /* 23817 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7979:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9174 /* 23817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
9175 /* 23820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9176 /* 23822 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9177 /* 23824 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9178 /* 23826 */ GIR_RootConstrainSelectedInstOperands,
9179 /* 23827 */ // GIR_Coverage, 527,
9180 /* 23827 */ GIR_EraseRootFromParent_Done,
9181 /* 23828 */ // Label 806: @23828
9182 /* 23828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 807*/ GIMT_Encode4(23872), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 528 //
9183 /* 23835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
9184 /* 23840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9185 /* 23843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9186 /* 23846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9187 /* 23849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9188 /* 23853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9189 /* 23857 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9190 /* 23861 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7981:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9191 /* 23861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
9192 /* 23864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9193 /* 23866 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9194 /* 23868 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9195 /* 23870 */ GIR_RootConstrainSelectedInstOperands,
9196 /* 23871 */ // GIR_Coverage, 528,
9197 /* 23871 */ GIR_EraseRootFromParent_Done,
9198 /* 23872 */ // Label 807: @23872
9199 /* 23872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 808*/ GIMT_Encode4(23916), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 529 //
9200 /* 23879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
9201 /* 23884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9202 /* 23887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9203 /* 23890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9204 /* 23893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9205 /* 23897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9206 /* 23901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9207 /* 23905 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7982:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9208 /* 23905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
9209 /* 23908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9210 /* 23910 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9211 /* 23912 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9212 /* 23914 */ GIR_RootConstrainSelectedInstOperands,
9213 /* 23915 */ // GIR_Coverage, 529,
9214 /* 23915 */ GIR_EraseRootFromParent_Done,
9215 /* 23916 */ // Label 808: @23916
9216 /* 23916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(23960), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 530 //
9217 /* 23923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
9218 /* 23928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9219 /* 23931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9220 /* 23934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9221 /* 23937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9222 /* 23941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9223 /* 23945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9224 /* 23949 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7980:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9225 /* 23949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
9226 /* 23952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9227 /* 23954 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9228 /* 23956 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9229 /* 23958 */ GIR_RootConstrainSelectedInstOperands,
9230 /* 23959 */ // GIR_Coverage, 530,
9231 /* 23959 */ GIR_EraseRootFromParent_Done,
9232 /* 23960 */ // Label 809: @23960
9233 /* 23960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(24004), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 531 //
9234 /* 23967 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
9235 /* 23972 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9236 /* 23975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9237 /* 23978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9238 /* 23981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9239 /* 23985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9240 /* 23989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9241 /* 23993 */ // (intrinsic_wo_chain:{ *:[v16i8] } 7983:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9242 /* 23993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
9243 /* 23996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9244 /* 23998 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9245 /* 24000 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9246 /* 24002 */ GIR_RootConstrainSelectedInstOperands,
9247 /* 24003 */ // GIR_Coverage, 531,
9248 /* 24003 */ GIR_EraseRootFromParent_Done,
9249 /* 24004 */ // Label 810: @24004
9250 /* 24004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(24048), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 532 //
9251 /* 24011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
9252 /* 24016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9253 /* 24019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9254 /* 24022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9255 /* 24025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9256 /* 24029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9257 /* 24033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9258 /* 24037 */ // (intrinsic_wo_chain:{ *:[v8i16] } 7985:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9259 /* 24037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
9260 /* 24040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9261 /* 24042 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9262 /* 24044 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9263 /* 24046 */ GIR_RootConstrainSelectedInstOperands,
9264 /* 24047 */ // GIR_Coverage, 532,
9265 /* 24047 */ GIR_EraseRootFromParent_Done,
9266 /* 24048 */ // Label 811: @24048
9267 /* 24048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 812*/ GIMT_Encode4(24092), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 533 //
9268 /* 24055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
9269 /* 24060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9270 /* 24063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9271 /* 24066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9272 /* 24069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9273 /* 24073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9274 /* 24077 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9275 /* 24081 */ // (intrinsic_wo_chain:{ *:[v4i32] } 7986:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9276 /* 24081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
9277 /* 24084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9278 /* 24086 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9279 /* 24088 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9280 /* 24090 */ GIR_RootConstrainSelectedInstOperands,
9281 /* 24091 */ // GIR_Coverage, 533,
9282 /* 24091 */ GIR_EraseRootFromParent_Done,
9283 /* 24092 */ // Label 812: @24092
9284 /* 24092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 813*/ GIMT_Encode4(24136), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 534 //
9285 /* 24099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
9286 /* 24104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9287 /* 24107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9288 /* 24110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9289 /* 24113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9290 /* 24117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9291 /* 24121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9292 /* 24125 */ // (intrinsic_wo_chain:{ *:[v2i64] } 7984:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9293 /* 24125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
9294 /* 24128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9295 /* 24130 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9296 /* 24132 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9297 /* 24134 */ GIR_RootConstrainSelectedInstOperands,
9298 /* 24135 */ // GIR_Coverage, 534,
9299 /* 24135 */ GIR_EraseRootFromParent_Done,
9300 /* 24136 */ // Label 813: @24136
9301 /* 24136 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(24180), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 548 //
9302 /* 24143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
9303 /* 24148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9304 /* 24151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9305 /* 24154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9306 /* 24157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9307 /* 24161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9308 /* 24165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9309 /* 24169 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8006:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9310 /* 24169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
9311 /* 24172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9312 /* 24174 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9313 /* 24176 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9314 /* 24178 */ GIR_RootConstrainSelectedInstOperands,
9315 /* 24179 */ // GIR_Coverage, 548,
9316 /* 24179 */ GIR_EraseRootFromParent_Done,
9317 /* 24180 */ // Label 814: @24180
9318 /* 24180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(24224), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 549 //
9319 /* 24187 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
9320 /* 24192 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9321 /* 24195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9322 /* 24198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9323 /* 24201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9324 /* 24205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9325 /* 24209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9326 /* 24213 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8008:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9327 /* 24213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
9328 /* 24216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9329 /* 24218 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9330 /* 24220 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9331 /* 24222 */ GIR_RootConstrainSelectedInstOperands,
9332 /* 24223 */ // GIR_Coverage, 549,
9333 /* 24223 */ GIR_EraseRootFromParent_Done,
9334 /* 24224 */ // Label 815: @24224
9335 /* 24224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(24268), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 550 //
9336 /* 24231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
9337 /* 24236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9338 /* 24239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9339 /* 24242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9340 /* 24245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9341 /* 24249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9342 /* 24253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9343 /* 24257 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8009:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9344 /* 24257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
9345 /* 24260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9346 /* 24262 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9347 /* 24264 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9348 /* 24266 */ GIR_RootConstrainSelectedInstOperands,
9349 /* 24267 */ // GIR_Coverage, 550,
9350 /* 24267 */ GIR_EraseRootFromParent_Done,
9351 /* 24268 */ // Label 816: @24268
9352 /* 24268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 817*/ GIMT_Encode4(24312), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 551 //
9353 /* 24275 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
9354 /* 24280 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9355 /* 24283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9356 /* 24286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9357 /* 24289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9358 /* 24293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9359 /* 24297 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9360 /* 24301 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8007:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9361 /* 24301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
9362 /* 24304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9363 /* 24306 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9364 /* 24308 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9365 /* 24310 */ GIR_RootConstrainSelectedInstOperands,
9366 /* 24311 */ // GIR_Coverage, 551,
9367 /* 24311 */ GIR_EraseRootFromParent_Done,
9368 /* 24312 */ // Label 817: @24312
9369 /* 24312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 818*/ GIMT_Encode4(24356), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 552 //
9370 /* 24319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
9371 /* 24324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9372 /* 24327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9373 /* 24330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9374 /* 24333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9375 /* 24337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9376 /* 24341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9377 /* 24345 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8010:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9378 /* 24345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
9379 /* 24348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9380 /* 24350 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9381 /* 24352 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9382 /* 24354 */ GIR_RootConstrainSelectedInstOperands,
9383 /* 24355 */ // GIR_Coverage, 552,
9384 /* 24355 */ GIR_EraseRootFromParent_Done,
9385 /* 24356 */ // Label 818: @24356
9386 /* 24356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 819*/ GIMT_Encode4(24400), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 553 //
9387 /* 24363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
9388 /* 24368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9389 /* 24371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9390 /* 24374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9391 /* 24377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9392 /* 24381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9393 /* 24385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9394 /* 24389 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8012:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9395 /* 24389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
9396 /* 24392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9397 /* 24394 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9398 /* 24396 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9399 /* 24398 */ GIR_RootConstrainSelectedInstOperands,
9400 /* 24399 */ // GIR_Coverage, 553,
9401 /* 24399 */ GIR_EraseRootFromParent_Done,
9402 /* 24400 */ // Label 819: @24400
9403 /* 24400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 820*/ GIMT_Encode4(24444), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 554 //
9404 /* 24407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
9405 /* 24412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9406 /* 24415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9407 /* 24418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9408 /* 24421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9409 /* 24425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9410 /* 24429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9411 /* 24433 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8013:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9412 /* 24433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
9413 /* 24436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9414 /* 24438 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9415 /* 24440 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9416 /* 24442 */ GIR_RootConstrainSelectedInstOperands,
9417 /* 24443 */ // GIR_Coverage, 554,
9418 /* 24443 */ GIR_EraseRootFromParent_Done,
9419 /* 24444 */ // Label 820: @24444
9420 /* 24444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 821*/ GIMT_Encode4(24488), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 555 //
9421 /* 24451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
9422 /* 24456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9423 /* 24459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9424 /* 24462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9425 /* 24465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9426 /* 24469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9427 /* 24473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9428 /* 24477 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8011:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9429 /* 24477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
9430 /* 24480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9431 /* 24482 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9432 /* 24484 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9433 /* 24486 */ GIR_RootConstrainSelectedInstOperands,
9434 /* 24487 */ // GIR_Coverage, 555,
9435 /* 24487 */ GIR_EraseRootFromParent_Done,
9436 /* 24488 */ // Label 821: @24488
9437 /* 24488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 822*/ GIMT_Encode4(24532), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 556 //
9438 /* 24495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
9439 /* 24500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9440 /* 24503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9441 /* 24506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9442 /* 24509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9443 /* 24513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9444 /* 24517 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9445 /* 24521 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8014:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9446 /* 24521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
9447 /* 24524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9448 /* 24526 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9449 /* 24528 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9450 /* 24530 */ GIR_RootConstrainSelectedInstOperands,
9451 /* 24531 */ // GIR_Coverage, 556,
9452 /* 24531 */ GIR_EraseRootFromParent_Done,
9453 /* 24532 */ // Label 822: @24532
9454 /* 24532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 823*/ GIMT_Encode4(24576), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 557 //
9455 /* 24539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
9456 /* 24544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9457 /* 24547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9458 /* 24550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9459 /* 24553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9460 /* 24557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9461 /* 24561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9462 /* 24565 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8016:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9463 /* 24565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
9464 /* 24568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9465 /* 24570 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9466 /* 24572 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9467 /* 24574 */ GIR_RootConstrainSelectedInstOperands,
9468 /* 24575 */ // GIR_Coverage, 557,
9469 /* 24575 */ GIR_EraseRootFromParent_Done,
9470 /* 24576 */ // Label 823: @24576
9471 /* 24576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(24620), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 558 //
9472 /* 24583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
9473 /* 24588 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9474 /* 24591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9475 /* 24594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9476 /* 24597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9477 /* 24601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9478 /* 24605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9479 /* 24609 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8017:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9480 /* 24609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
9481 /* 24612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9482 /* 24614 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9483 /* 24616 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9484 /* 24618 */ GIR_RootConstrainSelectedInstOperands,
9485 /* 24619 */ // GIR_Coverage, 558,
9486 /* 24619 */ GIR_EraseRootFromParent_Done,
9487 /* 24620 */ // Label 824: @24620
9488 /* 24620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(24664), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 559 //
9489 /* 24627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
9490 /* 24632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9491 /* 24635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9492 /* 24638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9493 /* 24641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9494 /* 24645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9495 /* 24649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9496 /* 24653 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8015:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9497 /* 24653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
9498 /* 24656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9499 /* 24658 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9500 /* 24660 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9501 /* 24662 */ GIR_RootConstrainSelectedInstOperands,
9502 /* 24663 */ // GIR_Coverage, 559,
9503 /* 24663 */ GIR_EraseRootFromParent_Done,
9504 /* 24664 */ // Label 825: @24664
9505 /* 24664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(24708), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 560 //
9506 /* 24671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
9507 /* 24676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9508 /* 24679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9509 /* 24682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9510 /* 24685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9511 /* 24689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9512 /* 24693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9513 /* 24697 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8018:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9514 /* 24697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
9515 /* 24700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9516 /* 24702 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9517 /* 24704 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9518 /* 24706 */ GIR_RootConstrainSelectedInstOperands,
9519 /* 24707 */ // GIR_Coverage, 560,
9520 /* 24707 */ GIR_EraseRootFromParent_Done,
9521 /* 24708 */ // Label 826: @24708
9522 /* 24708 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(24752), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 561 //
9523 /* 24715 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
9524 /* 24720 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9525 /* 24723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9526 /* 24726 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9527 /* 24729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9528 /* 24733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9529 /* 24737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9530 /* 24741 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8020:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9531 /* 24741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
9532 /* 24744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9533 /* 24746 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9534 /* 24748 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9535 /* 24750 */ GIR_RootConstrainSelectedInstOperands,
9536 /* 24751 */ // GIR_Coverage, 561,
9537 /* 24751 */ GIR_EraseRootFromParent_Done,
9538 /* 24752 */ // Label 827: @24752
9539 /* 24752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(24796), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 562 //
9540 /* 24759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
9541 /* 24764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9542 /* 24767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9543 /* 24770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9544 /* 24773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9545 /* 24777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9546 /* 24781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9547 /* 24785 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8021:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9548 /* 24785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
9549 /* 24788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9550 /* 24790 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9551 /* 24792 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9552 /* 24794 */ GIR_RootConstrainSelectedInstOperands,
9553 /* 24795 */ // GIR_Coverage, 562,
9554 /* 24795 */ GIR_EraseRootFromParent_Done,
9555 /* 24796 */ // Label 828: @24796
9556 /* 24796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(24840), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 563 //
9557 /* 24803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
9558 /* 24808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9559 /* 24811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9560 /* 24814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9561 /* 24817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9562 /* 24821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9563 /* 24825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9564 /* 24829 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8019:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9565 /* 24829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
9566 /* 24832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9567 /* 24834 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9568 /* 24836 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9569 /* 24838 */ GIR_RootConstrainSelectedInstOperands,
9570 /* 24839 */ // GIR_Coverage, 563,
9571 /* 24839 */ GIR_EraseRootFromParent_Done,
9572 /* 24840 */ // Label 829: @24840
9573 /* 24840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(24884), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 564 //
9574 /* 24847 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
9575 /* 24852 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9576 /* 24855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9577 /* 24858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9578 /* 24861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9579 /* 24865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9580 /* 24869 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9581 /* 24873 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8022:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9582 /* 24873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
9583 /* 24876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9584 /* 24878 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9585 /* 24880 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9586 /* 24882 */ GIR_RootConstrainSelectedInstOperands,
9587 /* 24883 */ // GIR_Coverage, 564,
9588 /* 24883 */ GIR_EraseRootFromParent_Done,
9589 /* 24884 */ // Label 830: @24884
9590 /* 24884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 831*/ GIMT_Encode4(24928), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 565 //
9591 /* 24891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
9592 /* 24896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9593 /* 24899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9594 /* 24902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9595 /* 24905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9596 /* 24909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9597 /* 24913 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9598 /* 24917 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8024:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9599 /* 24917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
9600 /* 24920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9601 /* 24922 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9602 /* 24924 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9603 /* 24926 */ GIR_RootConstrainSelectedInstOperands,
9604 /* 24927 */ // GIR_Coverage, 565,
9605 /* 24927 */ GIR_EraseRootFromParent_Done,
9606 /* 24928 */ // Label 831: @24928
9607 /* 24928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 832*/ GIMT_Encode4(24972), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 566 //
9608 /* 24935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
9609 /* 24940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9610 /* 24943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9611 /* 24946 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9612 /* 24949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9613 /* 24953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9614 /* 24957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9615 /* 24961 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8025:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9616 /* 24961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
9617 /* 24964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9618 /* 24966 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9619 /* 24968 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9620 /* 24970 */ GIR_RootConstrainSelectedInstOperands,
9621 /* 24971 */ // GIR_Coverage, 566,
9622 /* 24971 */ GIR_EraseRootFromParent_Done,
9623 /* 24972 */ // Label 832: @24972
9624 /* 24972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(25016), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 567 //
9625 /* 24979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
9626 /* 24984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9627 /* 24987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9628 /* 24990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9629 /* 24993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9630 /* 24997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9631 /* 25001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9632 /* 25005 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8023:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9633 /* 25005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
9634 /* 25008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9635 /* 25010 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9636 /* 25012 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9637 /* 25014 */ GIR_RootConstrainSelectedInstOperands,
9638 /* 25015 */ // GIR_Coverage, 567,
9639 /* 25015 */ GIR_EraseRootFromParent_Done,
9640 /* 25016 */ // Label 833: @25016
9641 /* 25016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(25060), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 568 //
9642 /* 25023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
9643 /* 25028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9644 /* 25031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9645 /* 25034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9646 /* 25037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9647 /* 25041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9648 /* 25045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9649 /* 25049 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8026:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9650 /* 25049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
9651 /* 25052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9652 /* 25054 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9653 /* 25056 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9654 /* 25058 */ GIR_RootConstrainSelectedInstOperands,
9655 /* 25059 */ // GIR_Coverage, 568,
9656 /* 25059 */ GIR_EraseRootFromParent_Done,
9657 /* 25060 */ // Label 834: @25060
9658 /* 25060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(25104), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 569 //
9659 /* 25067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
9660 /* 25072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9661 /* 25075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9662 /* 25078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9663 /* 25081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9664 /* 25085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9665 /* 25089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9666 /* 25093 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8028:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9667 /* 25093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
9668 /* 25096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9669 /* 25098 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9670 /* 25100 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9671 /* 25102 */ GIR_RootConstrainSelectedInstOperands,
9672 /* 25103 */ // GIR_Coverage, 569,
9673 /* 25103 */ GIR_EraseRootFromParent_Done,
9674 /* 25104 */ // Label 835: @25104
9675 /* 25104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 836*/ GIMT_Encode4(25148), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 570 //
9676 /* 25111 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
9677 /* 25116 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9678 /* 25119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9679 /* 25122 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9680 /* 25125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9681 /* 25129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9682 /* 25133 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9683 /* 25137 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8029:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9684 /* 25137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
9685 /* 25140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9686 /* 25142 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9687 /* 25144 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9688 /* 25146 */ GIR_RootConstrainSelectedInstOperands,
9689 /* 25147 */ // GIR_Coverage, 570,
9690 /* 25147 */ GIR_EraseRootFromParent_Done,
9691 /* 25148 */ // Label 836: @25148
9692 /* 25148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 837*/ GIMT_Encode4(25192), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 571 //
9693 /* 25155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
9694 /* 25160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9695 /* 25163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9696 /* 25166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9697 /* 25169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9698 /* 25173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9699 /* 25177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9700 /* 25181 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8027:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9701 /* 25181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
9702 /* 25184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9703 /* 25186 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9704 /* 25188 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9705 /* 25190 */ GIR_RootConstrainSelectedInstOperands,
9706 /* 25191 */ // GIR_Coverage, 571,
9707 /* 25191 */ GIR_EraseRootFromParent_Done,
9708 /* 25192 */ // Label 837: @25192
9709 /* 25192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(25236), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 680 //
9710 /* 25199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
9711 /* 25204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9712 /* 25207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9713 /* 25210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9714 /* 25213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9715 /* 25217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9716 /* 25221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9717 /* 25225 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8161:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9718 /* 25225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
9719 /* 25228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9720 /* 25230 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9721 /* 25232 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9722 /* 25234 */ GIR_RootConstrainSelectedInstOperands,
9723 /* 25235 */ // GIR_Coverage, 680,
9724 /* 25235 */ GIR_EraseRootFromParent_Done,
9725 /* 25236 */ // Label 838: @25236
9726 /* 25236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 839*/ GIMT_Encode4(25280), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 681 //
9727 /* 25243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
9728 /* 25248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9729 /* 25251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9730 /* 25254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9731 /* 25257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9732 /* 25261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9733 /* 25265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9734 /* 25269 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8162:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9735 /* 25269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
9736 /* 25272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9737 /* 25274 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9738 /* 25276 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9739 /* 25278 */ GIR_RootConstrainSelectedInstOperands,
9740 /* 25279 */ // GIR_Coverage, 681,
9741 /* 25279 */ GIR_EraseRootFromParent_Done,
9742 /* 25280 */ // Label 839: @25280
9743 /* 25280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 840*/ GIMT_Encode4(25324), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 682 //
9744 /* 25287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
9745 /* 25292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9746 /* 25295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9747 /* 25298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9748 /* 25301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9749 /* 25305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9750 /* 25309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9751 /* 25313 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9752 /* 25313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
9753 /* 25316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9754 /* 25318 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9755 /* 25320 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9756 /* 25322 */ GIR_RootConstrainSelectedInstOperands,
9757 /* 25323 */ // GIR_Coverage, 682,
9758 /* 25323 */ GIR_EraseRootFromParent_Done,
9759 /* 25324 */ // Label 840: @25324
9760 /* 25324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(25368), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 683 //
9761 /* 25331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
9762 /* 25336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9763 /* 25339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9764 /* 25342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9765 /* 25345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9766 /* 25349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9767 /* 25353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9768 /* 25357 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8164:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9769 /* 25357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
9770 /* 25360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9771 /* 25362 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9772 /* 25364 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9773 /* 25366 */ GIR_RootConstrainSelectedInstOperands,
9774 /* 25367 */ // GIR_Coverage, 683,
9775 /* 25367 */ GIR_EraseRootFromParent_Done,
9776 /* 25368 */ // Label 841: @25368
9777 /* 25368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(25412), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 684 //
9778 /* 25375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
9779 /* 25380 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9780 /* 25383 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9781 /* 25386 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9782 /* 25389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9783 /* 25393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9784 /* 25397 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9785 /* 25401 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8165:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9786 /* 25401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
9787 /* 25404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9788 /* 25406 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9789 /* 25408 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9790 /* 25410 */ GIR_RootConstrainSelectedInstOperands,
9791 /* 25411 */ // GIR_Coverage, 684,
9792 /* 25411 */ GIR_EraseRootFromParent_Done,
9793 /* 25412 */ // Label 842: @25412
9794 /* 25412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(25456), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 685 //
9795 /* 25419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
9796 /* 25424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9797 /* 25427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9798 /* 25430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9799 /* 25433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9800 /* 25437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9801 /* 25441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9802 /* 25445 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8163:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9803 /* 25445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
9804 /* 25448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9805 /* 25450 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9806 /* 25452 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9807 /* 25454 */ GIR_RootConstrainSelectedInstOperands,
9808 /* 25455 */ // GIR_Coverage, 685,
9809 /* 25455 */ GIR_EraseRootFromParent_Done,
9810 /* 25456 */ // Label 843: @25456
9811 /* 25456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(25500), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 700 //
9812 /* 25463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
9813 /* 25468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9814 /* 25471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9815 /* 25474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9816 /* 25477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9817 /* 25481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9818 /* 25485 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9819 /* 25489 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9820 /* 25489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
9821 /* 25492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9822 /* 25494 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9823 /* 25496 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9824 /* 25498 */ GIR_RootConstrainSelectedInstOperands,
9825 /* 25499 */ // GIR_Coverage, 700,
9826 /* 25499 */ GIR_EraseRootFromParent_Done,
9827 /* 25500 */ // Label 844: @25500
9828 /* 25500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(25544), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 701 //
9829 /* 25507 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
9830 /* 25512 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9831 /* 25515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9832 /* 25518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9833 /* 25521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9834 /* 25525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9835 /* 25529 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9836 /* 25533 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8202:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9837 /* 25533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
9838 /* 25536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9839 /* 25538 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9840 /* 25540 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9841 /* 25542 */ GIR_RootConstrainSelectedInstOperands,
9842 /* 25543 */ // GIR_Coverage, 701,
9843 /* 25543 */ GIR_EraseRootFromParent_Done,
9844 /* 25544 */ // Label 845: @25544
9845 /* 25544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(25588), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 726 //
9846 /* 25551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
9847 /* 25556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9848 /* 25559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9849 /* 25562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9850 /* 25565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9851 /* 25569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9852 /* 25573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9853 /* 25577 */ // (intrinsic_wo_chain:{ *:[v8f16] } 8228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9854 /* 25577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
9855 /* 25580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9856 /* 25582 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9857 /* 25584 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9858 /* 25586 */ GIR_RootConstrainSelectedInstOperands,
9859 /* 25587 */ // GIR_Coverage, 726,
9860 /* 25587 */ GIR_EraseRootFromParent_Done,
9861 /* 25588 */ // Label 846: @25588
9862 /* 25588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(25632), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 727 //
9863 /* 25595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
9864 /* 25600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9865 /* 25603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9866 /* 25606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9867 /* 25609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9868 /* 25613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9869 /* 25617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9870 /* 25621 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9871 /* 25621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
9872 /* 25624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9873 /* 25626 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9874 /* 25628 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9875 /* 25630 */ GIR_RootConstrainSelectedInstOperands,
9876 /* 25631 */ // GIR_Coverage, 727,
9877 /* 25631 */ GIR_EraseRootFromParent_Done,
9878 /* 25632 */ // Label 847: @25632
9879 /* 25632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 848*/ GIMT_Encode4(25676), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 754 //
9880 /* 25639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
9881 /* 25644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9882 /* 25647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9883 /* 25650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9884 /* 25653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9885 /* 25657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9886 /* 25661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9887 /* 25665 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8255:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9888 /* 25665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
9889 /* 25668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9890 /* 25670 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9891 /* 25672 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9892 /* 25674 */ GIR_RootConstrainSelectedInstOperands,
9893 /* 25675 */ // GIR_Coverage, 754,
9894 /* 25675 */ GIR_EraseRootFromParent_Done,
9895 /* 25676 */ // Label 848: @25676
9896 /* 25676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 849*/ GIMT_Encode4(25720), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 755 //
9897 /* 25683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
9898 /* 25688 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9899 /* 25691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9900 /* 25694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9901 /* 25697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9902 /* 25701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9903 /* 25705 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9904 /* 25709 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8254:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9905 /* 25709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
9906 /* 25712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9907 /* 25714 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9908 /* 25716 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9909 /* 25718 */ GIR_RootConstrainSelectedInstOperands,
9910 /* 25719 */ // GIR_Coverage, 755,
9911 /* 25719 */ GIR_EraseRootFromParent_Done,
9912 /* 25720 */ // Label 849: @25720
9913 /* 25720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 850*/ GIMT_Encode4(25764), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 756 //
9914 /* 25727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
9915 /* 25732 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9916 /* 25735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9917 /* 25738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9918 /* 25741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9919 /* 25745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9920 /* 25749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9921 /* 25753 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9922 /* 25753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
9923 /* 25756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9924 /* 25758 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9925 /* 25760 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9926 /* 25762 */ GIR_RootConstrainSelectedInstOperands,
9927 /* 25763 */ // GIR_Coverage, 756,
9928 /* 25763 */ GIR_EraseRootFromParent_Done,
9929 /* 25764 */ // Label 850: @25764
9930 /* 25764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 851*/ GIMT_Encode4(25808), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 757 //
9931 /* 25771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
9932 /* 25776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9933 /* 25779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9934 /* 25782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9935 /* 25785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9936 /* 25789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9937 /* 25793 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9938 /* 25797 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8252:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9939 /* 25797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
9940 /* 25800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9941 /* 25802 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9942 /* 25804 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9943 /* 25806 */ GIR_RootConstrainSelectedInstOperands,
9944 /* 25807 */ // GIR_Coverage, 757,
9945 /* 25807 */ GIR_EraseRootFromParent_Done,
9946 /* 25808 */ // Label 851: @25808
9947 /* 25808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 852*/ GIMT_Encode4(25852), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 758 //
9948 /* 25815 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
9949 /* 25820 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9950 /* 25823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9951 /* 25826 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9952 /* 25829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9953 /* 25833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9954 /* 25837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9955 /* 25841 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8259:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9956 /* 25841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
9957 /* 25844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9958 /* 25846 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9959 /* 25848 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9960 /* 25850 */ GIR_RootConstrainSelectedInstOperands,
9961 /* 25851 */ // GIR_Coverage, 758,
9962 /* 25851 */ GIR_EraseRootFromParent_Done,
9963 /* 25852 */ // Label 852: @25852
9964 /* 25852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 853*/ GIMT_Encode4(25896), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 759 //
9965 /* 25859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
9966 /* 25864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9967 /* 25867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9968 /* 25870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9969 /* 25873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9970 /* 25877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9971 /* 25881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9972 /* 25885 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8258:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9973 /* 25885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
9974 /* 25888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9975 /* 25890 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9976 /* 25892 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9977 /* 25894 */ GIR_RootConstrainSelectedInstOperands,
9978 /* 25895 */ // GIR_Coverage, 759,
9979 /* 25895 */ GIR_EraseRootFromParent_Done,
9980 /* 25896 */ // Label 853: @25896
9981 /* 25896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 854*/ GIMT_Encode4(25940), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 760 //
9982 /* 25903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
9983 /* 25908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9984 /* 25911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9985 /* 25914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9986 /* 25917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9987 /* 25921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9988 /* 25925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9989 /* 25929 */ // (intrinsic_wo_chain:{ *:[v4f32] } 8257:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9990 /* 25929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
9991 /* 25932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9992 /* 25934 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
9993 /* 25936 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
9994 /* 25938 */ GIR_RootConstrainSelectedInstOperands,
9995 /* 25939 */ // GIR_Coverage, 760,
9996 /* 25939 */ GIR_EraseRootFromParent_Done,
9997 /* 25940 */ // Label 854: @25940
9998 /* 25940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(25984), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 761 //
9999 /* 25947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
10000 /* 25952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10001 /* 25955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10002 /* 25958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10003 /* 25961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10004 /* 25965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10005 /* 25969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10006 /* 25973 */ // (intrinsic_wo_chain:{ *:[v2f64] } 8256:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10007 /* 25973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
10008 /* 25976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10009 /* 25978 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10010 /* 25980 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10011 /* 25982 */ GIR_RootConstrainSelectedInstOperands,
10012 /* 25983 */ // GIR_Coverage, 761,
10013 /* 25983 */ GIR_EraseRootFromParent_Done,
10014 /* 25984 */ // Label 855: @25984
10015 /* 25984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(26028), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 772 //
10016 /* 25991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
10017 /* 25996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10018 /* 25999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10019 /* 26002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10020 /* 26005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10021 /* 26009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10022 /* 26013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10023 /* 26017 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10024 /* 26017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
10025 /* 26020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10026 /* 26022 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10027 /* 26024 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10028 /* 26026 */ GIR_RootConstrainSelectedInstOperands,
10029 /* 26027 */ // GIR_Coverage, 772,
10030 /* 26027 */ GIR_EraseRootFromParent_Done,
10031 /* 26028 */ // Label 856: @26028
10032 /* 26028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(26072), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 773 //
10033 /* 26035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
10034 /* 26040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10035 /* 26043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10036 /* 26046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10037 /* 26049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10038 /* 26053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10039 /* 26057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10040 /* 26061 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8270:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10041 /* 26061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
10042 /* 26064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10043 /* 26066 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10044 /* 26068 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10045 /* 26070 */ GIR_RootConstrainSelectedInstOperands,
10046 /* 26071 */ // GIR_Coverage, 773,
10047 /* 26071 */ GIR_EraseRootFromParent_Done,
10048 /* 26072 */ // Label 857: @26072
10049 /* 26072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 858*/ GIMT_Encode4(26116), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 774 //
10050 /* 26079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
10051 /* 26084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10052 /* 26087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10053 /* 26090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10054 /* 26093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10055 /* 26097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10056 /* 26101 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10057 /* 26105 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8273:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10058 /* 26105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
10059 /* 26108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10060 /* 26110 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10061 /* 26112 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10062 /* 26114 */ GIR_RootConstrainSelectedInstOperands,
10063 /* 26115 */ // GIR_Coverage, 774,
10064 /* 26115 */ GIR_EraseRootFromParent_Done,
10065 /* 26116 */ // Label 858: @26116
10066 /* 26116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 859*/ GIMT_Encode4(26160), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 775 //
10067 /* 26123 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
10068 /* 26128 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10069 /* 26131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10070 /* 26134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10071 /* 26137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10072 /* 26141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10073 /* 26145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10074 /* 26149 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8272:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10075 /* 26149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
10076 /* 26152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10077 /* 26154 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10078 /* 26156 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10079 /* 26158 */ GIR_RootConstrainSelectedInstOperands,
10080 /* 26159 */ // GIR_Coverage, 775,
10081 /* 26159 */ GIR_EraseRootFromParent_Done,
10082 /* 26160 */ // Label 859: @26160
10083 /* 26160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(26204), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 776 //
10084 /* 26167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
10085 /* 26172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10086 /* 26175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10087 /* 26178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10088 /* 26181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10089 /* 26185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10090 /* 26189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10091 /* 26193 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8275:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10092 /* 26193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
10093 /* 26196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10094 /* 26198 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10095 /* 26200 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10096 /* 26202 */ GIR_RootConstrainSelectedInstOperands,
10097 /* 26203 */ // GIR_Coverage, 776,
10098 /* 26203 */ GIR_EraseRootFromParent_Done,
10099 /* 26204 */ // Label 860: @26204
10100 /* 26204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(26248), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 777 //
10101 /* 26211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
10102 /* 26216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10103 /* 26219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10104 /* 26222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10105 /* 26225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10106 /* 26229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10107 /* 26233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10108 /* 26237 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10109 /* 26237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
10110 /* 26240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10111 /* 26242 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10112 /* 26244 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10113 /* 26246 */ GIR_RootConstrainSelectedInstOperands,
10114 /* 26247 */ // GIR_Coverage, 777,
10115 /* 26247 */ GIR_EraseRootFromParent_Done,
10116 /* 26248 */ // Label 861: @26248
10117 /* 26248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(26292), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 778 //
10118 /* 26255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
10119 /* 26260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10120 /* 26263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10121 /* 26266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10122 /* 26269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10123 /* 26273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10124 /* 26277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10125 /* 26281 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10126 /* 26281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
10127 /* 26284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10128 /* 26286 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10129 /* 26288 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10130 /* 26290 */ GIR_RootConstrainSelectedInstOperands,
10131 /* 26291 */ // GIR_Coverage, 778,
10132 /* 26291 */ GIR_EraseRootFromParent_Done,
10133 /* 26292 */ // Label 862: @26292
10134 /* 26292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 863*/ GIMT_Encode4(26336), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 779 //
10135 /* 26299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
10136 /* 26304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10137 /* 26307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10138 /* 26310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10139 /* 26313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10140 /* 26317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10141 /* 26321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10142 /* 26325 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8276:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10143 /* 26325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
10144 /* 26328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10145 /* 26330 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10146 /* 26332 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10147 /* 26334 */ GIR_RootConstrainSelectedInstOperands,
10148 /* 26335 */ // GIR_Coverage, 779,
10149 /* 26335 */ GIR_EraseRootFromParent_Done,
10150 /* 26336 */ // Label 863: @26336
10151 /* 26336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 864*/ GIMT_Encode4(26380), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 780 //
10152 /* 26343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
10153 /* 26348 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10154 /* 26351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10155 /* 26354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10156 /* 26357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10157 /* 26361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10158 /* 26365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10159 /* 26369 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8279:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10160 /* 26369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
10161 /* 26372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10162 /* 26374 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10163 /* 26376 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10164 /* 26378 */ GIR_RootConstrainSelectedInstOperands,
10165 /* 26379 */ // GIR_Coverage, 780,
10166 /* 26379 */ GIR_EraseRootFromParent_Done,
10167 /* 26380 */ // Label 864: @26380
10168 /* 26380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(26424), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 781 //
10169 /* 26387 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
10170 /* 26392 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10171 /* 26395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10172 /* 26398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10173 /* 26401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10174 /* 26405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10175 /* 26409 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10176 /* 26413 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10177 /* 26413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
10178 /* 26416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10179 /* 26418 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10180 /* 26420 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10181 /* 26422 */ GIR_RootConstrainSelectedInstOperands,
10182 /* 26423 */ // GIR_Coverage, 781,
10183 /* 26423 */ GIR_EraseRootFromParent_Done,
10184 /* 26424 */ // Label 865: @26424
10185 /* 26424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 866*/ GIMT_Encode4(26468), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 782 //
10186 /* 26431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
10187 /* 26436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10188 /* 26439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10189 /* 26442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10190 /* 26445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10191 /* 26449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10192 /* 26453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10193 /* 26457 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8281:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10194 /* 26457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
10195 /* 26460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10196 /* 26462 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10197 /* 26464 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10198 /* 26466 */ GIR_RootConstrainSelectedInstOperands,
10199 /* 26467 */ // GIR_Coverage, 782,
10200 /* 26467 */ GIR_EraseRootFromParent_Done,
10201 /* 26468 */ // Label 866: @26468
10202 /* 26468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 867*/ GIMT_Encode4(26512), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 783 //
10203 /* 26475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
10204 /* 26480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10205 /* 26483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10206 /* 26486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10207 /* 26489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10208 /* 26493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10209 /* 26497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10210 /* 26501 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8280:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10211 /* 26501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
10212 /* 26504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10213 /* 26506 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10214 /* 26508 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10215 /* 26510 */ GIR_RootConstrainSelectedInstOperands,
10216 /* 26511 */ // GIR_Coverage, 783,
10217 /* 26511 */ GIR_EraseRootFromParent_Done,
10218 /* 26512 */ // Label 867: @26512
10219 /* 26512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(26556), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 788 //
10220 /* 26519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
10221 /* 26524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10222 /* 26527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10223 /* 26530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10224 /* 26533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10225 /* 26537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10226 /* 26541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10227 /* 26545 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8287:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10228 /* 26545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
10229 /* 26548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10230 /* 26550 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10231 /* 26552 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10232 /* 26554 */ GIR_RootConstrainSelectedInstOperands,
10233 /* 26555 */ // GIR_Coverage, 788,
10234 /* 26555 */ GIR_EraseRootFromParent_Done,
10235 /* 26556 */ // Label 868: @26556
10236 /* 26556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 869*/ GIMT_Encode4(26600), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 789 //
10237 /* 26563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
10238 /* 26568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10239 /* 26571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10240 /* 26574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10241 /* 26577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10242 /* 26581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10243 /* 26585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10244 /* 26589 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10245 /* 26589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
10246 /* 26592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10247 /* 26594 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10248 /* 26596 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10249 /* 26598 */ GIR_RootConstrainSelectedInstOperands,
10250 /* 26599 */ // GIR_Coverage, 789,
10251 /* 26599 */ GIR_EraseRootFromParent_Done,
10252 /* 26600 */ // Label 869: @26600
10253 /* 26600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 870*/ GIMT_Encode4(26644), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 790 //
10254 /* 26607 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
10255 /* 26612 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10256 /* 26615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10257 /* 26618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10258 /* 26621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10259 /* 26625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10260 /* 26629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10261 /* 26633 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8289:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10262 /* 26633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
10263 /* 26636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10264 /* 26638 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10265 /* 26640 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10266 /* 26642 */ GIR_RootConstrainSelectedInstOperands,
10267 /* 26643 */ // GIR_Coverage, 790,
10268 /* 26643 */ GIR_EraseRootFromParent_Done,
10269 /* 26644 */ // Label 870: @26644
10270 /* 26644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(26688), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 791 //
10271 /* 26651 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
10272 /* 26656 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10273 /* 26659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10274 /* 26662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10275 /* 26665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10276 /* 26669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10277 /* 26673 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10278 /* 26677 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8288:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10279 /* 26677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
10280 /* 26680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10281 /* 26682 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10282 /* 26684 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10283 /* 26686 */ GIR_RootConstrainSelectedInstOperands,
10284 /* 26687 */ // GIR_Coverage, 791,
10285 /* 26687 */ GIR_EraseRootFromParent_Done,
10286 /* 26688 */ // Label 871: @26688
10287 /* 26688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(26732), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 792 //
10288 /* 26695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
10289 /* 26700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10290 /* 26703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10291 /* 26706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10292 /* 26709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10293 /* 26713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10294 /* 26717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10295 /* 26721 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8291:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10296 /* 26721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
10297 /* 26724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10298 /* 26726 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10299 /* 26728 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10300 /* 26730 */ GIR_RootConstrainSelectedInstOperands,
10301 /* 26731 */ // GIR_Coverage, 792,
10302 /* 26731 */ GIR_EraseRootFromParent_Done,
10303 /* 26732 */ // Label 872: @26732
10304 /* 26732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(26776), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 793 //
10305 /* 26739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
10306 /* 26744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10307 /* 26747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10308 /* 26750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10309 /* 26753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10310 /* 26757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10311 /* 26761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10312 /* 26765 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8290:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10313 /* 26765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
10314 /* 26768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10315 /* 26770 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10316 /* 26772 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10317 /* 26774 */ GIR_RootConstrainSelectedInstOperands,
10318 /* 26775 */ // GIR_Coverage, 793,
10319 /* 26775 */ GIR_EraseRootFromParent_Done,
10320 /* 26776 */ // Label 873: @26776
10321 /* 26776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(26820), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 794 //
10322 /* 26783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
10323 /* 26788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10324 /* 26791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10325 /* 26794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10326 /* 26797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10327 /* 26801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10328 /* 26805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10329 /* 26809 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8293:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10330 /* 26809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
10331 /* 26812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10332 /* 26814 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10333 /* 26816 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10334 /* 26818 */ GIR_RootConstrainSelectedInstOperands,
10335 /* 26819 */ // GIR_Coverage, 794,
10336 /* 26819 */ GIR_EraseRootFromParent_Done,
10337 /* 26820 */ // Label 874: @26820
10338 /* 26820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(26864), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 795 //
10339 /* 26827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
10340 /* 26832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10341 /* 26835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10342 /* 26838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10343 /* 26841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10344 /* 26845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10345 /* 26849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10346 /* 26853 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8292:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10347 /* 26853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
10348 /* 26856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10349 /* 26858 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10350 /* 26860 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10351 /* 26862 */ GIR_RootConstrainSelectedInstOperands,
10352 /* 26863 */ // GIR_Coverage, 795,
10353 /* 26863 */ GIR_EraseRootFromParent_Done,
10354 /* 26864 */ // Label 875: @26864
10355 /* 26864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(26908), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 796 //
10356 /* 26871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
10357 /* 26876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10358 /* 26879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10359 /* 26882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10360 /* 26885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10361 /* 26889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10362 /* 26893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10363 /* 26897 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8295:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10364 /* 26897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
10365 /* 26900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10366 /* 26902 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10367 /* 26904 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10368 /* 26906 */ GIR_RootConstrainSelectedInstOperands,
10369 /* 26907 */ // GIR_Coverage, 796,
10370 /* 26907 */ GIR_EraseRootFromParent_Done,
10371 /* 26908 */ // Label 876: @26908
10372 /* 26908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(26952), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 797 //
10373 /* 26915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
10374 /* 26920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10375 /* 26923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10376 /* 26926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10377 /* 26929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10378 /* 26933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10379 /* 26937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10380 /* 26941 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10381 /* 26941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
10382 /* 26944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10383 /* 26946 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10384 /* 26948 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10385 /* 26950 */ GIR_RootConstrainSelectedInstOperands,
10386 /* 26951 */ // GIR_Coverage, 797,
10387 /* 26951 */ GIR_EraseRootFromParent_Done,
10388 /* 26952 */ // Label 877: @26952
10389 /* 26952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 878*/ GIMT_Encode4(26996), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 802 //
10390 /* 26959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
10391 /* 26964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10392 /* 26967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10393 /* 26970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10394 /* 26973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10395 /* 26977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10396 /* 26981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10397 /* 26985 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8300:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
10398 /* 26985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
10399 /* 26988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10400 /* 26990 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10401 /* 26992 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10402 /* 26994 */ GIR_RootConstrainSelectedInstOperands,
10403 /* 26995 */ // GIR_Coverage, 802,
10404 /* 26995 */ GIR_EraseRootFromParent_Done,
10405 /* 26996 */ // Label 878: @26996
10406 /* 26996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 879*/ GIMT_Encode4(27040), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 803 //
10407 /* 27003 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
10408 /* 27008 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10409 /* 27011 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10410 /* 27014 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10411 /* 27017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10412 /* 27021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10413 /* 27025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10414 /* 27029 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8301:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
10415 /* 27029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
10416 /* 27032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10417 /* 27034 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10418 /* 27036 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10419 /* 27038 */ GIR_RootConstrainSelectedInstOperands,
10420 /* 27039 */ // GIR_Coverage, 803,
10421 /* 27039 */ GIR_EraseRootFromParent_Done,
10422 /* 27040 */ // Label 879: @27040
10423 /* 27040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(27084), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 808 //
10424 /* 27047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
10425 /* 27052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10426 /* 27055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10427 /* 27058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10428 /* 27061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10429 /* 27065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10430 /* 27069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10431 /* 27073 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8307:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10432 /* 27073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
10433 /* 27076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10434 /* 27078 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10435 /* 27080 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10436 /* 27082 */ GIR_RootConstrainSelectedInstOperands,
10437 /* 27083 */ // GIR_Coverage, 808,
10438 /* 27083 */ GIR_EraseRootFromParent_Done,
10439 /* 27084 */ // Label 880: @27084
10440 /* 27084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(27128), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 809 //
10441 /* 27091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
10442 /* 27096 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10443 /* 27099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10444 /* 27102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10445 /* 27105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10446 /* 27109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10447 /* 27113 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10448 /* 27117 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8308:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10449 /* 27117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
10450 /* 27120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10451 /* 27122 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10452 /* 27124 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10453 /* 27126 */ GIR_RootConstrainSelectedInstOperands,
10454 /* 27127 */ // GIR_Coverage, 809,
10455 /* 27127 */ GIR_EraseRootFromParent_Done,
10456 /* 27128 */ // Label 881: @27128
10457 /* 27128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(27172), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 810 //
10458 /* 27135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
10459 /* 27140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10460 /* 27143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10461 /* 27146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10462 /* 27149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10463 /* 27153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10464 /* 27157 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10465 /* 27161 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8306:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10466 /* 27161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
10467 /* 27164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10468 /* 27166 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10469 /* 27168 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10470 /* 27170 */ GIR_RootConstrainSelectedInstOperands,
10471 /* 27171 */ // GIR_Coverage, 810,
10472 /* 27171 */ GIR_EraseRootFromParent_Done,
10473 /* 27172 */ // Label 882: @27172
10474 /* 27172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(27216), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 811 //
10475 /* 27179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
10476 /* 27184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10477 /* 27187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10478 /* 27190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10479 /* 27193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10480 /* 27197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10481 /* 27201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10482 /* 27205 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8310:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10483 /* 27205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
10484 /* 27208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10485 /* 27210 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10486 /* 27212 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10487 /* 27214 */ GIR_RootConstrainSelectedInstOperands,
10488 /* 27215 */ // GIR_Coverage, 811,
10489 /* 27215 */ GIR_EraseRootFromParent_Done,
10490 /* 27216 */ // Label 883: @27216
10491 /* 27216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(27260), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 812 //
10492 /* 27223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
10493 /* 27228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10494 /* 27231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10495 /* 27234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10496 /* 27237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10497 /* 27241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10498 /* 27245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10499 /* 27249 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8311:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10500 /* 27249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
10501 /* 27252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10502 /* 27254 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10503 /* 27256 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10504 /* 27258 */ GIR_RootConstrainSelectedInstOperands,
10505 /* 27259 */ // GIR_Coverage, 812,
10506 /* 27259 */ GIR_EraseRootFromParent_Done,
10507 /* 27260 */ // Label 884: @27260
10508 /* 27260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(27304), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 813 //
10509 /* 27267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
10510 /* 27272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10511 /* 27275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10512 /* 27278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10513 /* 27281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10514 /* 27285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10515 /* 27289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10516 /* 27293 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10517 /* 27293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
10518 /* 27296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10519 /* 27298 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10520 /* 27300 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10521 /* 27302 */ GIR_RootConstrainSelectedInstOperands,
10522 /* 27303 */ // GIR_Coverage, 813,
10523 /* 27303 */ GIR_EraseRootFromParent_Done,
10524 /* 27304 */ // Label 885: @27304
10525 /* 27304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(27348), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 814 //
10526 /* 27311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
10527 /* 27316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10528 /* 27319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10529 /* 27322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10530 /* 27325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10531 /* 27329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10532 /* 27333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10533 /* 27337 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8313:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10534 /* 27337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
10535 /* 27340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10536 /* 27342 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10537 /* 27344 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10538 /* 27346 */ GIR_RootConstrainSelectedInstOperands,
10539 /* 27347 */ // GIR_Coverage, 814,
10540 /* 27347 */ GIR_EraseRootFromParent_Done,
10541 /* 27348 */ // Label 886: @27348
10542 /* 27348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 887*/ GIMT_Encode4(27392), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 815 //
10543 /* 27355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
10544 /* 27360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10545 /* 27363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10546 /* 27366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10547 /* 27369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10548 /* 27373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10549 /* 27377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10550 /* 27381 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8314:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10551 /* 27381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
10552 /* 27384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10553 /* 27386 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10554 /* 27388 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10555 /* 27390 */ GIR_RootConstrainSelectedInstOperands,
10556 /* 27391 */ // GIR_Coverage, 815,
10557 /* 27391 */ GIR_EraseRootFromParent_Done,
10558 /* 27392 */ // Label 887: @27392
10559 /* 27392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 888*/ GIMT_Encode4(27436), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 816 //
10560 /* 27399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
10561 /* 27404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10562 /* 27407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10563 /* 27410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10564 /* 27413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10565 /* 27417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10566 /* 27421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10567 /* 27425 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8312:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10568 /* 27425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
10569 /* 27428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10570 /* 27430 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10571 /* 27432 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10572 /* 27434 */ GIR_RootConstrainSelectedInstOperands,
10573 /* 27435 */ // GIR_Coverage, 816,
10574 /* 27435 */ GIR_EraseRootFromParent_Done,
10575 /* 27436 */ // Label 888: @27436
10576 /* 27436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(27480), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 817 //
10577 /* 27443 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
10578 /* 27448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10579 /* 27451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10580 /* 27454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10581 /* 27457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10582 /* 27461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10583 /* 27465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10584 /* 27469 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8316:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10585 /* 27469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
10586 /* 27472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10587 /* 27474 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10588 /* 27476 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10589 /* 27478 */ GIR_RootConstrainSelectedInstOperands,
10590 /* 27479 */ // GIR_Coverage, 817,
10591 /* 27479 */ GIR_EraseRootFromParent_Done,
10592 /* 27480 */ // Label 889: @27480
10593 /* 27480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(27524), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 818 //
10594 /* 27487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
10595 /* 27492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10596 /* 27495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10597 /* 27498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10598 /* 27501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10599 /* 27505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10600 /* 27509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10601 /* 27513 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8317:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10602 /* 27513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
10603 /* 27516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10604 /* 27518 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10605 /* 27520 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10606 /* 27522 */ GIR_RootConstrainSelectedInstOperands,
10607 /* 27523 */ // GIR_Coverage, 818,
10608 /* 27523 */ GIR_EraseRootFromParent_Done,
10609 /* 27524 */ // Label 890: @27524
10610 /* 27524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(27568), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 819 //
10611 /* 27531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
10612 /* 27536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10613 /* 27539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10614 /* 27542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10615 /* 27545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10616 /* 27549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10617 /* 27553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10618 /* 27557 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8315:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10619 /* 27557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
10620 /* 27560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10621 /* 27562 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10622 /* 27564 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10623 /* 27566 */ GIR_RootConstrainSelectedInstOperands,
10624 /* 27567 */ // GIR_Coverage, 819,
10625 /* 27567 */ GIR_EraseRootFromParent_Done,
10626 /* 27568 */ // Label 891: @27568
10627 /* 27568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(27612), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 872 //
10628 /* 27575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
10629 /* 27580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10630 /* 27583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10631 /* 27586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10632 /* 27589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10633 /* 27593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10634 /* 27597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10635 /* 27601 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8371:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10636 /* 27601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
10637 /* 27604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10638 /* 27606 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10639 /* 27608 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10640 /* 27610 */ GIR_RootConstrainSelectedInstOperands,
10641 /* 27611 */ // GIR_Coverage, 872,
10642 /* 27611 */ GIR_EraseRootFromParent_Done,
10643 /* 27612 */ // Label 892: @27612
10644 /* 27612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(27656), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 873 //
10645 /* 27619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
10646 /* 27624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10647 /* 27627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10648 /* 27630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10649 /* 27633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10650 /* 27637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10651 /* 27641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10652 /* 27645 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8373:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10653 /* 27645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
10654 /* 27648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10655 /* 27650 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10656 /* 27652 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10657 /* 27654 */ GIR_RootConstrainSelectedInstOperands,
10658 /* 27655 */ // GIR_Coverage, 873,
10659 /* 27655 */ GIR_EraseRootFromParent_Done,
10660 /* 27656 */ // Label 893: @27656
10661 /* 27656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(27700), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 874 //
10662 /* 27663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
10663 /* 27668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10664 /* 27671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10665 /* 27674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10666 /* 27677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10667 /* 27681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10668 /* 27685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10669 /* 27689 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8374:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10670 /* 27689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
10671 /* 27692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10672 /* 27694 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10673 /* 27696 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10674 /* 27698 */ GIR_RootConstrainSelectedInstOperands,
10675 /* 27699 */ // GIR_Coverage, 874,
10676 /* 27699 */ GIR_EraseRootFromParent_Done,
10677 /* 27700 */ // Label 894: @27700
10678 /* 27700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(27744), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 875 //
10679 /* 27707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
10680 /* 27712 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10681 /* 27715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10682 /* 27718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10683 /* 27721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10684 /* 27725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10685 /* 27729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10686 /* 27733 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8372:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10687 /* 27733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
10688 /* 27736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10689 /* 27738 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10690 /* 27740 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10691 /* 27742 */ GIR_RootConstrainSelectedInstOperands,
10692 /* 27743 */ // GIR_Coverage, 875,
10693 /* 27743 */ GIR_EraseRootFromParent_Done,
10694 /* 27744 */ // Label 895: @27744
10695 /* 27744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 896*/ GIMT_Encode4(27788), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 892 //
10696 /* 27751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
10697 /* 27756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10698 /* 27759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10699 /* 27762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10700 /* 27765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10701 /* 27769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10702 /* 27773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10703 /* 27777 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8391:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10704 /* 27777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
10705 /* 27780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10706 /* 27782 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10707 /* 27784 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10708 /* 27786 */ GIR_RootConstrainSelectedInstOperands,
10709 /* 27787 */ // GIR_Coverage, 892,
10710 /* 27787 */ GIR_EraseRootFromParent_Done,
10711 /* 27788 */ // Label 896: @27788
10712 /* 27788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 897*/ GIMT_Encode4(27832), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 893 //
10713 /* 27795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
10714 /* 27800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10715 /* 27803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10716 /* 27806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10717 /* 27809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10718 /* 27813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10719 /* 27817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10720 /* 27821 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8393:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10721 /* 27821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
10722 /* 27824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10723 /* 27826 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10724 /* 27828 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10725 /* 27830 */ GIR_RootConstrainSelectedInstOperands,
10726 /* 27831 */ // GIR_Coverage, 893,
10727 /* 27831 */ GIR_EraseRootFromParent_Done,
10728 /* 27832 */ // Label 897: @27832
10729 /* 27832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(27876), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 894 //
10730 /* 27839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
10731 /* 27844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10732 /* 27847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10733 /* 27850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10734 /* 27853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10735 /* 27857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10736 /* 27861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10737 /* 27865 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8394:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10738 /* 27865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
10739 /* 27868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10740 /* 27870 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10741 /* 27872 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10742 /* 27874 */ GIR_RootConstrainSelectedInstOperands,
10743 /* 27875 */ // GIR_Coverage, 894,
10744 /* 27875 */ GIR_EraseRootFromParent_Done,
10745 /* 27876 */ // Label 898: @27876
10746 /* 27876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(27920), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 895 //
10747 /* 27883 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
10748 /* 27888 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10749 /* 27891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10750 /* 27894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10751 /* 27897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10752 /* 27901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10753 /* 27905 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10754 /* 27909 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8392:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10755 /* 27909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
10756 /* 27912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10757 /* 27914 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10758 /* 27916 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10759 /* 27918 */ GIR_RootConstrainSelectedInstOperands,
10760 /* 27919 */ // GIR_Coverage, 895,
10761 /* 27919 */ GIR_EraseRootFromParent_Done,
10762 /* 27920 */ // Label 899: @27920
10763 /* 27920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(27964), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 928 //
10764 /* 27927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
10765 /* 27932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10766 /* 27935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10767 /* 27938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10768 /* 27941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10769 /* 27945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10770 /* 27949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10771 /* 27953 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8433:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10772 /* 27953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
10773 /* 27956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10774 /* 27958 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10775 /* 27960 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10776 /* 27962 */ GIR_RootConstrainSelectedInstOperands,
10777 /* 27963 */ // GIR_Coverage, 928,
10778 /* 27963 */ GIR_EraseRootFromParent_Done,
10779 /* 27964 */ // Label 900: @27964
10780 /* 27964 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(28008), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 929 //
10781 /* 27971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
10782 /* 27976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10783 /* 27979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10784 /* 27982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10785 /* 27985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10786 /* 27989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10787 /* 27993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10788 /* 27997 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8434:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10789 /* 27997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
10790 /* 28000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10791 /* 28002 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10792 /* 28004 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10793 /* 28006 */ GIR_RootConstrainSelectedInstOperands,
10794 /* 28007 */ // GIR_Coverage, 929,
10795 /* 28007 */ GIR_EraseRootFromParent_Done,
10796 /* 28008 */ // Label 901: @28008
10797 /* 28008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(28052), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 930 //
10798 /* 28015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
10799 /* 28020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10800 /* 28023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10801 /* 28026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10802 /* 28029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10803 /* 28033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10804 /* 28037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10805 /* 28041 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8444:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10806 /* 28041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
10807 /* 28044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10808 /* 28046 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10809 /* 28048 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10810 /* 28050 */ GIR_RootConstrainSelectedInstOperands,
10811 /* 28051 */ // GIR_Coverage, 930,
10812 /* 28051 */ GIR_EraseRootFromParent_Done,
10813 /* 28052 */ // Label 902: @28052
10814 /* 28052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(28096), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 931 //
10815 /* 28059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
10816 /* 28064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10817 /* 28067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10818 /* 28070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10819 /* 28073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10820 /* 28077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10821 /* 28081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10822 /* 28085 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8445:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10823 /* 28085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
10824 /* 28088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10825 /* 28090 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10826 /* 28092 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10827 /* 28094 */ GIR_RootConstrainSelectedInstOperands,
10828 /* 28095 */ // GIR_Coverage, 931,
10829 /* 28095 */ GIR_EraseRootFromParent_Done,
10830 /* 28096 */ // Label 903: @28096
10831 /* 28096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(28140), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1009 //
10832 /* 28103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
10833 /* 28108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10834 /* 28111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10835 /* 28114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10836 /* 28117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10837 /* 28121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10838 /* 28125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10839 /* 28129 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8558:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10840 /* 28129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
10841 /* 28132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10842 /* 28134 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10843 /* 28136 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10844 /* 28138 */ GIR_RootConstrainSelectedInstOperands,
10845 /* 28139 */ // GIR_Coverage, 1009,
10846 /* 28139 */ GIR_EraseRootFromParent_Done,
10847 /* 28140 */ // Label 904: @28140
10848 /* 28140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 905*/ GIMT_Encode4(28184), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1010 //
10849 /* 28147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
10850 /* 28152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10851 /* 28155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10852 /* 28158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10853 /* 28161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10854 /* 28165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10855 /* 28169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10856 /* 28173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8560:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10857 /* 28173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
10858 /* 28176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10859 /* 28178 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10860 /* 28180 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10861 /* 28182 */ GIR_RootConstrainSelectedInstOperands,
10862 /* 28183 */ // GIR_Coverage, 1010,
10863 /* 28183 */ GIR_EraseRootFromParent_Done,
10864 /* 28184 */ // Label 905: @28184
10865 /* 28184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 906*/ GIMT_Encode4(28228), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1011 //
10866 /* 28191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
10867 /* 28196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10868 /* 28199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10869 /* 28202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10870 /* 28205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10871 /* 28209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10872 /* 28213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10873 /* 28217 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8561:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10874 /* 28217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
10875 /* 28220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10876 /* 28222 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10877 /* 28224 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10878 /* 28226 */ GIR_RootConstrainSelectedInstOperands,
10879 /* 28227 */ // GIR_Coverage, 1011,
10880 /* 28227 */ GIR_EraseRootFromParent_Done,
10881 /* 28228 */ // Label 906: @28228
10882 /* 28228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 907*/ GIMT_Encode4(28272), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1012 //
10883 /* 28235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
10884 /* 28240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10885 /* 28243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10886 /* 28246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10887 /* 28249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10888 /* 28253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10889 /* 28257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10890 /* 28261 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8559:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10891 /* 28261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
10892 /* 28264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10893 /* 28266 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10894 /* 28268 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10895 /* 28270 */ GIR_RootConstrainSelectedInstOperands,
10896 /* 28271 */ // GIR_Coverage, 1012,
10897 /* 28271 */ GIR_EraseRootFromParent_Done,
10898 /* 28272 */ // Label 907: @28272
10899 /* 28272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 908*/ GIMT_Encode4(28316), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1025 //
10900 /* 28279 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
10901 /* 28284 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10902 /* 28287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10903 /* 28290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10904 /* 28293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10905 /* 28297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10906 /* 28301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10907 /* 28305 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10908 /* 28305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
10909 /* 28308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10910 /* 28310 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10911 /* 28312 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10912 /* 28314 */ GIR_RootConstrainSelectedInstOperands,
10913 /* 28315 */ // GIR_Coverage, 1025,
10914 /* 28315 */ GIR_EraseRootFromParent_Done,
10915 /* 28316 */ // Label 908: @28316
10916 /* 28316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 909*/ GIMT_Encode4(28360), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1026 //
10917 /* 28323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
10918 /* 28328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10919 /* 28331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10920 /* 28334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10921 /* 28337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10922 /* 28341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10923 /* 28345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10924 /* 28349 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8576:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10925 /* 28349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
10926 /* 28352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10927 /* 28354 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10928 /* 28356 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10929 /* 28358 */ GIR_RootConstrainSelectedInstOperands,
10930 /* 28359 */ // GIR_Coverage, 1026,
10931 /* 28359 */ GIR_EraseRootFromParent_Done,
10932 /* 28360 */ // Label 909: @28360
10933 /* 28360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 910*/ GIMT_Encode4(28404), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1027 //
10934 /* 28367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
10935 /* 28372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10936 /* 28375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10937 /* 28378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10938 /* 28381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10939 /* 28385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10940 /* 28389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10941 /* 28393 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8577:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10942 /* 28393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
10943 /* 28396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10944 /* 28398 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10945 /* 28400 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10946 /* 28402 */ GIR_RootConstrainSelectedInstOperands,
10947 /* 28403 */ // GIR_Coverage, 1027,
10948 /* 28403 */ GIR_EraseRootFromParent_Done,
10949 /* 28404 */ // Label 910: @28404
10950 /* 28404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 911*/ GIMT_Encode4(28448), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1028 //
10951 /* 28411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
10952 /* 28416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10953 /* 28419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10954 /* 28422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10955 /* 28425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10956 /* 28429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10957 /* 28433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10958 /* 28437 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8575:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10959 /* 28437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
10960 /* 28440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10961 /* 28442 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10962 /* 28444 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10963 /* 28446 */ GIR_RootConstrainSelectedInstOperands,
10964 /* 28447 */ // GIR_Coverage, 1028,
10965 /* 28447 */ GIR_EraseRootFromParent_Done,
10966 /* 28448 */ // Label 911: @28448
10967 /* 28448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(28492), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1037 //
10968 /* 28455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
10969 /* 28460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10970 /* 28463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10971 /* 28466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10972 /* 28469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10973 /* 28473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10974 /* 28477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10975 /* 28481 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8595:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10976 /* 28481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
10977 /* 28484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10978 /* 28486 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10979 /* 28488 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10980 /* 28490 */ GIR_RootConstrainSelectedInstOperands,
10981 /* 28491 */ // GIR_Coverage, 1037,
10982 /* 28491 */ GIR_EraseRootFromParent_Done,
10983 /* 28492 */ // Label 912: @28492
10984 /* 28492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(28536), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1038 //
10985 /* 28499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
10986 /* 28504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10987 /* 28507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10988 /* 28510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10989 /* 28513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10990 /* 28517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10991 /* 28521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10992 /* 28525 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8597:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10993 /* 28525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
10994 /* 28528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10995 /* 28530 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
10996 /* 28532 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
10997 /* 28534 */ GIR_RootConstrainSelectedInstOperands,
10998 /* 28535 */ // GIR_Coverage, 1038,
10999 /* 28535 */ GIR_EraseRootFromParent_Done,
11000 /* 28536 */ // Label 913: @28536
11001 /* 28536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(28580), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1039 //
11002 /* 28543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
11003 /* 28548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11004 /* 28551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11005 /* 28554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11006 /* 28557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11007 /* 28561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11008 /* 28565 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11009 /* 28569 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8598:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11010 /* 28569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
11011 /* 28572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11012 /* 28574 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11013 /* 28576 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11014 /* 28578 */ GIR_RootConstrainSelectedInstOperands,
11015 /* 28579 */ // GIR_Coverage, 1039,
11016 /* 28579 */ GIR_EraseRootFromParent_Done,
11017 /* 28580 */ // Label 914: @28580
11018 /* 28580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(28624), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1040 //
11019 /* 28587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
11020 /* 28592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11021 /* 28595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11022 /* 28598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11023 /* 28601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11024 /* 28605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11025 /* 28609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11026 /* 28613 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8596:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11027 /* 28613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
11028 /* 28616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11029 /* 28618 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11030 /* 28620 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11031 /* 28622 */ GIR_RootConstrainSelectedInstOperands,
11032 /* 28623 */ // GIR_Coverage, 1040,
11033 /* 28623 */ GIR_EraseRootFromParent_Done,
11034 /* 28624 */ // Label 915: @28624
11035 /* 28624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(28668), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1041 //
11036 /* 28631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
11037 /* 28636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11038 /* 28639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11039 /* 28642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11040 /* 28645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11041 /* 28649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11042 /* 28653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11043 /* 28657 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8599:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11044 /* 28657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
11045 /* 28660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11046 /* 28662 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11047 /* 28664 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11048 /* 28666 */ GIR_RootConstrainSelectedInstOperands,
11049 /* 28667 */ // GIR_Coverage, 1041,
11050 /* 28667 */ GIR_EraseRootFromParent_Done,
11051 /* 28668 */ // Label 916: @28668
11052 /* 28668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(28712), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1042 //
11053 /* 28675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
11054 /* 28680 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11055 /* 28683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11056 /* 28686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11057 /* 28689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11058 /* 28693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11059 /* 28697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11060 /* 28701 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8601:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11061 /* 28701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
11062 /* 28704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11063 /* 28706 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11064 /* 28708 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11065 /* 28710 */ GIR_RootConstrainSelectedInstOperands,
11066 /* 28711 */ // GIR_Coverage, 1042,
11067 /* 28711 */ GIR_EraseRootFromParent_Done,
11068 /* 28712 */ // Label 917: @28712
11069 /* 28712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(28756), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1043 //
11070 /* 28719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
11071 /* 28724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11072 /* 28727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11073 /* 28730 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11074 /* 28733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11075 /* 28737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11076 /* 28741 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11077 /* 28745 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8602:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11078 /* 28745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
11079 /* 28748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11080 /* 28750 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11081 /* 28752 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11082 /* 28754 */ GIR_RootConstrainSelectedInstOperands,
11083 /* 28755 */ // GIR_Coverage, 1043,
11084 /* 28755 */ GIR_EraseRootFromParent_Done,
11085 /* 28756 */ // Label 918: @28756
11086 /* 28756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 919*/ GIMT_Encode4(28800), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1044 //
11087 /* 28763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
11088 /* 28768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11089 /* 28771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11090 /* 28774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11091 /* 28777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11092 /* 28781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11093 /* 28785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11094 /* 28789 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8600:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11095 /* 28789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
11096 /* 28792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11097 /* 28794 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11098 /* 28796 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11099 /* 28798 */ GIR_RootConstrainSelectedInstOperands,
11100 /* 28799 */ // GIR_Coverage, 1044,
11101 /* 28799 */ GIR_EraseRootFromParent_Done,
11102 /* 28800 */ // Label 919: @28800
11103 /* 28800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 920*/ GIMT_Encode4(28844), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1045 //
11104 /* 28807 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
11105 /* 28812 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11106 /* 28815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11107 /* 28818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11108 /* 28821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11109 /* 28825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11110 /* 28829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11111 /* 28833 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8603:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11112 /* 28833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
11113 /* 28836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11114 /* 28838 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11115 /* 28840 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11116 /* 28842 */ GIR_RootConstrainSelectedInstOperands,
11117 /* 28843 */ // GIR_Coverage, 1045,
11118 /* 28843 */ GIR_EraseRootFromParent_Done,
11119 /* 28844 */ // Label 920: @28844
11120 /* 28844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(28888), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1046 //
11121 /* 28851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
11122 /* 28856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11123 /* 28859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11124 /* 28862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11125 /* 28865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11126 /* 28869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11127 /* 28873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11128 /* 28877 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8605:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11129 /* 28877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
11130 /* 28880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11131 /* 28882 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11132 /* 28884 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11133 /* 28886 */ GIR_RootConstrainSelectedInstOperands,
11134 /* 28887 */ // GIR_Coverage, 1046,
11135 /* 28887 */ GIR_EraseRootFromParent_Done,
11136 /* 28888 */ // Label 921: @28888
11137 /* 28888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(28932), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1047 //
11138 /* 28895 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
11139 /* 28900 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11140 /* 28903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11141 /* 28906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11142 /* 28909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11143 /* 28913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11144 /* 28917 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11145 /* 28921 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8606:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11146 /* 28921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
11147 /* 28924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11148 /* 28926 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11149 /* 28928 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11150 /* 28930 */ GIR_RootConstrainSelectedInstOperands,
11151 /* 28931 */ // GIR_Coverage, 1047,
11152 /* 28931 */ GIR_EraseRootFromParent_Done,
11153 /* 28932 */ // Label 922: @28932
11154 /* 28932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(28976), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1048 //
11155 /* 28939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
11156 /* 28944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11157 /* 28947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11158 /* 28950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11159 /* 28953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11160 /* 28957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11161 /* 28961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11162 /* 28965 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8604:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11163 /* 28965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
11164 /* 28968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11165 /* 28970 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11166 /* 28972 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11167 /* 28974 */ GIR_RootConstrainSelectedInstOperands,
11168 /* 28975 */ // GIR_Coverage, 1048,
11169 /* 28975 */ GIR_EraseRootFromParent_Done,
11170 /* 28976 */ // Label 923: @28976
11171 /* 28976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 924*/ GIMT_Encode4(29020), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1049 //
11172 /* 28983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
11173 /* 28988 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11174 /* 28991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11175 /* 28994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11176 /* 28997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11177 /* 29001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11178 /* 29005 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11179 /* 29009 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8607:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11180 /* 29009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
11181 /* 29012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11182 /* 29014 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11183 /* 29016 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11184 /* 29018 */ GIR_RootConstrainSelectedInstOperands,
11185 /* 29019 */ // GIR_Coverage, 1049,
11186 /* 29019 */ GIR_EraseRootFromParent_Done,
11187 /* 29020 */ // Label 924: @29020
11188 /* 29020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 925*/ GIMT_Encode4(29064), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1050 //
11189 /* 29027 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
11190 /* 29032 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11191 /* 29035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11192 /* 29038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11193 /* 29041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11194 /* 29045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11195 /* 29049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11196 /* 29053 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8609:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11197 /* 29053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
11198 /* 29056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11199 /* 29058 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11200 /* 29060 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11201 /* 29062 */ GIR_RootConstrainSelectedInstOperands,
11202 /* 29063 */ // GIR_Coverage, 1050,
11203 /* 29063 */ GIR_EraseRootFromParent_Done,
11204 /* 29064 */ // Label 925: @29064
11205 /* 29064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(29108), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1051 //
11206 /* 29071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
11207 /* 29076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11208 /* 29079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11209 /* 29082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11210 /* 29085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11211 /* 29089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11212 /* 29093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11213 /* 29097 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8610:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11214 /* 29097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
11215 /* 29100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11216 /* 29102 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11217 /* 29104 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11218 /* 29106 */ GIR_RootConstrainSelectedInstOperands,
11219 /* 29107 */ // GIR_Coverage, 1051,
11220 /* 29107 */ GIR_EraseRootFromParent_Done,
11221 /* 29108 */ // Label 926: @29108
11222 /* 29108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(29152), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1052 //
11223 /* 29115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
11224 /* 29120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11225 /* 29123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11226 /* 29126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11227 /* 29129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11228 /* 29133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11229 /* 29137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11230 /* 29141 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8608:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11231 /* 29141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
11232 /* 29144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11233 /* 29146 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
11234 /* 29148 */ GIR_RootToRootCopy, /*OpIdx*/3, // wt
11235 /* 29150 */ GIR_RootConstrainSelectedInstOperands,
11236 /* 29151 */ // GIR_Coverage, 1052,
11237 /* 29151 */ GIR_EraseRootFromParent_Done,
11238 /* 29152 */ // Label 927: @29152
11239 /* 29152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(29199), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1245 //
11240 /* 29159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
11241 /* 29164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11242 /* 29167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11243 /* 29170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11244 /* 29173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11245 /* 29177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11246 /* 29181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11247 /* 29185 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7969:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11248 /* 29185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
11249 /* 29188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11250 /* 29190 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11251 /* 29192 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11252 /* 29194 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11253 /* 29197 */ GIR_RootConstrainSelectedInstOperands,
11254 /* 29198 */ // GIR_Coverage, 1245,
11255 /* 29198 */ GIR_EraseRootFromParent_Done,
11256 /* 29199 */ // Label 928: @29199
11257 /* 29199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(29246), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1247 //
11258 /* 29206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
11259 /* 29211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11260 /* 29214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11261 /* 29217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11262 /* 29220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11263 /* 29224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11264 /* 29228 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11265 /* 29232 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7991:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11266 /* 29232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
11267 /* 29235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11268 /* 29237 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11269 /* 29239 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11270 /* 29241 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11271 /* 29244 */ GIR_RootConstrainSelectedInstOperands,
11272 /* 29245 */ // GIR_Coverage, 1247,
11273 /* 29245 */ GIR_EraseRootFromParent_Done,
11274 /* 29246 */ // Label 929: @29246
11275 /* 29246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(29290), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1268 //
11276 /* 29253 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
11277 /* 29258 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11278 /* 29261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11279 /* 29264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11280 /* 29267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11281 /* 29271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11282 /* 29275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11283 /* 29279 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8519:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11284 /* 29279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
11285 /* 29282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11286 /* 29284 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11287 /* 29286 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11288 /* 29288 */ GIR_RootConstrainSelectedInstOperands,
11289 /* 29289 */ // GIR_Coverage, 1268,
11290 /* 29289 */ GIR_EraseRootFromParent_Done,
11291 /* 29290 */ // Label 930: @29290
11292 /* 29290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(29334), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1269 //
11293 /* 29297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
11294 /* 29302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11295 /* 29305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11296 /* 29308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11297 /* 29311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11298 /* 29315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11299 /* 29319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11300 /* 29323 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8521:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11301 /* 29323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
11302 /* 29326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11303 /* 29328 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11304 /* 29330 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11305 /* 29332 */ GIR_RootConstrainSelectedInstOperands,
11306 /* 29333 */ // GIR_Coverage, 1269,
11307 /* 29333 */ GIR_EraseRootFromParent_Done,
11308 /* 29334 */ // Label 931: @29334
11309 /* 29334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(29378), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1270 //
11310 /* 29341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
11311 /* 29346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11312 /* 29349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11313 /* 29352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11314 /* 29355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11315 /* 29359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11316 /* 29363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11317 /* 29367 */ // (intrinsic_wo_chain:{ *:[i32] } 8523:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11318 /* 29367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
11319 /* 29370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11320 /* 29372 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11321 /* 29374 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11322 /* 29376 */ GIR_RootConstrainSelectedInstOperands,
11323 /* 29377 */ // GIR_Coverage, 1270,
11324 /* 29377 */ GIR_EraseRootFromParent_Done,
11325 /* 29378 */ // Label 932: @29378
11326 /* 29378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 933*/ GIMT_Encode4(29422), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1272 //
11327 /* 29385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
11328 /* 29390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11329 /* 29393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11330 /* 29396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11331 /* 29399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11332 /* 29403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11333 /* 29407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11334 /* 29411 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8525:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11335 /* 29411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
11336 /* 29414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11337 /* 29416 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11338 /* 29418 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11339 /* 29420 */ GIR_RootConstrainSelectedInstOperands,
11340 /* 29421 */ // GIR_Coverage, 1272,
11341 /* 29421 */ GIR_EraseRootFromParent_Done,
11342 /* 29422 */ // Label 933: @29422
11343 /* 29422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 934*/ GIMT_Encode4(29469), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1283 //
11344 /* 29429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
11345 /* 29434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11346 /* 29437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11347 /* 29440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11348 /* 29443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11349 /* 29447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11350 /* 29451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11351 /* 29455 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8589:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11352 /* 29455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
11353 /* 29458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11354 /* 29460 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11355 /* 29462 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11356 /* 29464 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11357 /* 29467 */ GIR_RootConstrainSelectedInstOperands,
11358 /* 29468 */ // GIR_Coverage, 1283,
11359 /* 29468 */ GIR_EraseRootFromParent_Done,
11360 /* 29469 */ // Label 934: @29469
11361 /* 29469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(29516), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1285 //
11362 /* 29476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
11363 /* 29481 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11364 /* 29484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11365 /* 29487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11366 /* 29490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11367 /* 29494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11368 /* 29498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11369 /* 29502 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8614:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11370 /* 29502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
11371 /* 29505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11372 /* 29507 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11373 /* 29509 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11374 /* 29511 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11375 /* 29514 */ GIR_RootConstrainSelectedInstOperands,
11376 /* 29515 */ // GIR_Coverage, 1285,
11377 /* 29515 */ GIR_EraseRootFromParent_Done,
11378 /* 29516 */ // Label 935: @29516
11379 /* 29516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 936*/ GIMT_Encode4(29560), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1295 //
11380 /* 29523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
11381 /* 29528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11382 /* 29531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11383 /* 29534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11384 /* 29537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11385 /* 29541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11386 /* 29545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11387 /* 29549 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8494:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11388 /* 29549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
11389 /* 29552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11390 /* 29554 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11391 /* 29556 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11392 /* 29558 */ GIR_RootConstrainSelectedInstOperands,
11393 /* 29559 */ // GIR_Coverage, 1295,
11394 /* 29559 */ GIR_EraseRootFromParent_Done,
11395 /* 29560 */ // Label 936: @29560
11396 /* 29560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 937*/ GIMT_Encode4(29604), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1296 //
11397 /* 29567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
11398 /* 29572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11399 /* 29575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11400 /* 29578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11401 /* 29581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11402 /* 29585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11403 /* 29589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11404 /* 29593 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8495:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11405 /* 29593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
11406 /* 29596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11407 /* 29598 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11408 /* 29600 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11409 /* 29602 */ GIR_RootConstrainSelectedInstOperands,
11410 /* 29603 */ // GIR_Coverage, 1296,
11411 /* 29603 */ GIR_EraseRootFromParent_Done,
11412 /* 29604 */ // Label 937: @29604
11413 /* 29604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 938*/ GIMT_Encode4(29648), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1315 //
11414 /* 29611 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
11415 /* 29616 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11416 /* 29619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11417 /* 29622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11418 /* 29625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11419 /* 29629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11420 /* 29633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11421 /* 29637 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11422 /* 29637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
11423 /* 29640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11424 /* 29642 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11425 /* 29644 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11426 /* 29646 */ GIR_RootConstrainSelectedInstOperands,
11427 /* 29647 */ // GIR_Coverage, 1315,
11428 /* 29647 */ GIR_EraseRootFromParent_Done,
11429 /* 29648 */ // Label 938: @29648
11430 /* 29648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 939*/ GIMT_Encode4(29692), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1321 //
11431 /* 29655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
11432 /* 29660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11433 /* 29663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11434 /* 29666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11435 /* 29669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11436 /* 29673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11437 /* 29677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11438 /* 29681 */ // (intrinsic_wo_chain:{ *:[i32] } 8419:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11439 /* 29681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
11440 /* 29684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11441 /* 29686 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11442 /* 29688 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11443 /* 29690 */ GIR_RootConstrainSelectedInstOperands,
11444 /* 29691 */ // GIR_Coverage, 1321,
11445 /* 29691 */ GIR_EraseRootFromParent_Done,
11446 /* 29692 */ // Label 939: @29692
11447 /* 29692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 940*/ GIMT_Encode4(29736), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1334 //
11448 /* 29699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
11449 /* 29704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11450 /* 29707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11451 /* 29710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11452 /* 29713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11453 /* 29717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11454 /* 29721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11455 /* 29725 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7971:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11456 /* 29725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
11457 /* 29728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11458 /* 29730 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11459 /* 29732 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11460 /* 29734 */ GIR_RootConstrainSelectedInstOperands,
11461 /* 29735 */ // GIR_Coverage, 1334,
11462 /* 29735 */ GIR_EraseRootFromParent_Done,
11463 /* 29736 */ // Label 940: @29736
11464 /* 29736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 941*/ GIMT_Encode4(29780), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1335 //
11465 /* 29743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
11466 /* 29748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11467 /* 29751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11468 /* 29754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11469 /* 29757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11470 /* 29761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11471 /* 29765 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11472 /* 29769 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7972:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11473 /* 29769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
11474 /* 29772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11475 /* 29774 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11476 /* 29776 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11477 /* 29778 */ GIR_RootConstrainSelectedInstOperands,
11478 /* 29779 */ // GIR_Coverage, 1335,
11479 /* 29779 */ GIR_EraseRootFromParent_Done,
11480 /* 29780 */ // Label 941: @29780
11481 /* 29780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 942*/ GIMT_Encode4(29824), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1336 //
11482 /* 29787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
11483 /* 29792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11484 /* 29795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11485 /* 29798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11486 /* 29801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11487 /* 29805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11488 /* 29809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11489 /* 29813 */ // (intrinsic_wo_chain:{ *:[i32] } 7974:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11490 /* 29813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
11491 /* 29816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11492 /* 29818 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11493 /* 29820 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11494 /* 29822 */ GIR_RootConstrainSelectedInstOperands,
11495 /* 29823 */ // GIR_Coverage, 1336,
11496 /* 29823 */ GIR_EraseRootFromParent_Done,
11497 /* 29824 */ // Label 942: @29824
11498 /* 29824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(29868), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1337 //
11499 /* 29831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
11500 /* 29836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11501 /* 29839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11502 /* 29842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11503 /* 29845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11504 /* 29849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11505 /* 29853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11506 /* 29857 */ // (intrinsic_wo_chain:{ *:[i32] } 7973:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11507 /* 29857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
11508 /* 29860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11509 /* 29862 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11510 /* 29864 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11511 /* 29866 */ GIR_RootConstrainSelectedInstOperands,
11512 /* 29867 */ // GIR_Coverage, 1337,
11513 /* 29867 */ GIR_EraseRootFromParent_Done,
11514 /* 29868 */ // Label 943: @29868
11515 /* 29868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(29912), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1340 //
11516 /* 29875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
11517 /* 29880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11518 /* 29883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11519 /* 29886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11520 /* 29889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11521 /* 29893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11522 /* 29897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11523 /* 29901 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7992:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11524 /* 29901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
11525 /* 29904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11526 /* 29906 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11527 /* 29908 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11528 /* 29910 */ GIR_RootConstrainSelectedInstOperands,
11529 /* 29911 */ // GIR_Coverage, 1340,
11530 /* 29911 */ GIR_EraseRootFromParent_Done,
11531 /* 29912 */ // Label 944: @29912
11532 /* 29912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(29956), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1341 //
11533 /* 29919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
11534 /* 29924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11535 /* 29927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11536 /* 29930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11537 /* 29933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11538 /* 29937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11539 /* 29941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11540 /* 29945 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7993:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11541 /* 29945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
11542 /* 29948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11543 /* 29950 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11544 /* 29952 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11545 /* 29954 */ GIR_RootConstrainSelectedInstOperands,
11546 /* 29955 */ // GIR_Coverage, 1341,
11547 /* 29955 */ GIR_EraseRootFromParent_Done,
11548 /* 29956 */ // Label 945: @29956
11549 /* 29956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 946*/ GIMT_Encode4(30000), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1347 //
11550 /* 29963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
11551 /* 29968 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11552 /* 29971 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11553 /* 29974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11554 /* 29977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11555 /* 29981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11556 /* 29985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11557 /* 29989 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8520:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11558 /* 29989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
11559 /* 29992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11560 /* 29994 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11561 /* 29996 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11562 /* 29998 */ GIR_RootConstrainSelectedInstOperands,
11563 /* 29999 */ // GIR_Coverage, 1347,
11564 /* 29999 */ GIR_EraseRootFromParent_Done,
11565 /* 30000 */ // Label 946: @30000
11566 /* 30000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 947*/ GIMT_Encode4(30044), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1348 //
11567 /* 30007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
11568 /* 30012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11569 /* 30015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11570 /* 30018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11571 /* 30021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11572 /* 30025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11573 /* 30029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11574 /* 30033 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8522:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11575 /* 30033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
11576 /* 30036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11577 /* 30038 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11578 /* 30040 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11579 /* 30042 */ GIR_RootConstrainSelectedInstOperands,
11580 /* 30043 */ // GIR_Coverage, 1348,
11581 /* 30043 */ GIR_EraseRootFromParent_Done,
11582 /* 30044 */ // Label 947: @30044
11583 /* 30044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(30088), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1353 //
11584 /* 30051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
11585 /* 30056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11586 /* 30059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11587 /* 30062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11588 /* 30065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11589 /* 30069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11590 /* 30073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11591 /* 30077 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8524:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
11592 /* 30077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
11593 /* 30080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11594 /* 30082 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
11595 /* 30084 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11596 /* 30086 */ GIR_RootConstrainSelectedInstOperands,
11597 /* 30087 */ // GIR_Coverage, 1353,
11598 /* 30087 */ GIR_EraseRootFromParent_Done,
11599 /* 30088 */ // Label 948: @30088
11600 /* 30088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(30132), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1354 //
11601 /* 30095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
11602 /* 30100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11603 /* 30103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11604 /* 30106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11605 /* 30109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11606 /* 30113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11607 /* 30117 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11608 /* 30121 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8591:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11609 /* 30121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
11610 /* 30124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11611 /* 30126 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11612 /* 30128 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11613 /* 30130 */ GIR_RootConstrainSelectedInstOperands,
11614 /* 30131 */ // GIR_Coverage, 1354,
11615 /* 30131 */ GIR_EraseRootFromParent_Done,
11616 /* 30132 */ // Label 949: @30132
11617 /* 30132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(30176), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1355 //
11618 /* 30139 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
11619 /* 30144 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11620 /* 30147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11621 /* 30150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11622 /* 30153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11623 /* 30157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11624 /* 30161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11625 /* 30165 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8592:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
11626 /* 30165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
11627 /* 30168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11628 /* 30170 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11629 /* 30172 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11630 /* 30174 */ GIR_RootConstrainSelectedInstOperands,
11631 /* 30175 */ // GIR_Coverage, 1355,
11632 /* 30175 */ GIR_EraseRootFromParent_Done,
11633 /* 30176 */ // Label 950: @30176
11634 /* 30176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 951*/ GIMT_Encode4(30220), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1356 //
11635 /* 30183 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
11636 /* 30188 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11637 /* 30191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11638 /* 30194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11639 /* 30197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11640 /* 30201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11641 /* 30205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11642 /* 30209 */ // (intrinsic_wo_chain:{ *:[i32] } 8594:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11643 /* 30209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
11644 /* 30212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11645 /* 30214 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11646 /* 30216 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11647 /* 30218 */ GIR_RootConstrainSelectedInstOperands,
11648 /* 30219 */ // GIR_Coverage, 1356,
11649 /* 30219 */ GIR_EraseRootFromParent_Done,
11650 /* 30220 */ // Label 951: @30220
11651 /* 30220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 952*/ GIMT_Encode4(30264), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1357 //
11652 /* 30227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
11653 /* 30232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11654 /* 30235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11655 /* 30238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11656 /* 30241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11657 /* 30245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11658 /* 30249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11659 /* 30253 */ // (intrinsic_wo_chain:{ *:[i32] } 8593:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
11660 /* 30253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
11661 /* 30256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11662 /* 30258 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11663 /* 30260 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11664 /* 30262 */ GIR_RootConstrainSelectedInstOperands,
11665 /* 30263 */ // GIR_Coverage, 1357,
11666 /* 30263 */ GIR_EraseRootFromParent_Done,
11667 /* 30264 */ // Label 952: @30264
11668 /* 30264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(30308), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1360 //
11669 /* 30271 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
11670 /* 30276 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11671 /* 30279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11672 /* 30282 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11673 /* 30285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11674 /* 30289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11675 /* 30293 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11676 /* 30297 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8615:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11677 /* 30297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
11678 /* 30300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11679 /* 30302 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11680 /* 30304 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11681 /* 30306 */ GIR_RootConstrainSelectedInstOperands,
11682 /* 30307 */ // GIR_Coverage, 1360,
11683 /* 30307 */ GIR_EraseRootFromParent_Done,
11684 /* 30308 */ // Label 953: @30308
11685 /* 30308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(30352), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1361 //
11686 /* 30315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
11687 /* 30320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11688 /* 30323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11689 /* 30326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11690 /* 30329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11691 /* 30333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11692 /* 30337 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11693 /* 30341 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8616:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
11694 /* 30341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
11695 /* 30344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11696 /* 30346 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
11697 /* 30348 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
11698 /* 30350 */ GIR_RootConstrainSelectedInstOperands,
11699 /* 30351 */ // GIR_Coverage, 1361,
11700 /* 30351 */ GIR_EraseRootFromParent_Done,
11701 /* 30352 */ // Label 954: @30352
11702 /* 30352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(30391), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2055 //
11703 /* 30359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
11704 /* 30364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11705 /* 30367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11706 /* 30370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11707 /* 30373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11708 /* 30377 */ // (intrinsic_wo_chain:{ *:[v2i16] } 7968:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11709 /* 30377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
11710 /* 30380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11711 /* 30382 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11712 /* 30384 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11713 /* 30386 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11714 /* 30389 */ GIR_RootConstrainSelectedInstOperands,
11715 /* 30390 */ // GIR_Coverage, 2055,
11716 /* 30390 */ GIR_EraseRootFromParent_Done,
11717 /* 30391 */ // Label 955: @30391
11718 /* 30391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(30430), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2057 //
11719 /* 30398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
11720 /* 30403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11721 /* 30406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
11722 /* 30409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
11723 /* 30412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11724 /* 30416 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8588:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
11725 /* 30416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
11726 /* 30419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11727 /* 30421 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11728 /* 30423 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11729 /* 30425 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11730 /* 30428 */ GIR_RootConstrainSelectedInstOperands,
11731 /* 30429 */ // GIR_Coverage, 2057,
11732 /* 30429 */ GIR_EraseRootFromParent_Done,
11733 /* 30430 */ // Label 956: @30430
11734 /* 30430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(30469), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2061 //
11735 /* 30437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
11736 /* 30442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11737 /* 30445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11738 /* 30448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11739 /* 30451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11740 /* 30455 */ // (intrinsic_wo_chain:{ *:[v4i8] } 7989:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11741 /* 30455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
11742 /* 30458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11743 /* 30460 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11744 /* 30462 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11745 /* 30464 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11746 /* 30467 */ GIR_RootConstrainSelectedInstOperands,
11747 /* 30468 */ // GIR_Coverage, 2061,
11748 /* 30468 */ GIR_EraseRootFromParent_Done,
11749 /* 30469 */ // Label 957: @30469
11750 /* 30469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(30508), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2063 //
11751 /* 30476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
11752 /* 30481 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11753 /* 30484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11754 /* 30487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11755 /* 30490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11756 /* 30494 */ // (intrinsic_wo_chain:{ *:[v4i8] } 8612:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11757 /* 30494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
11758 /* 30497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11759 /* 30499 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
11760 /* 30501 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
11761 /* 30503 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11762 /* 30506 */ GIR_RootConstrainSelectedInstOperands,
11763 /* 30507 */ // GIR_Coverage, 2063,
11764 /* 30507 */ GIR_EraseRootFromParent_Done,
11765 /* 30508 */ // Label 958: @30508
11766 /* 30508 */ GIM_Reject,
11767 /* 30509 */ // Label 744: @30509
11768 /* 30509 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(32977),
11769 /* 30514 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
11770 /* 30517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 960*/ GIMT_Encode4(30571), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 505 //
11771 /* 30524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11772 /* 30529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11773 /* 30532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11774 /* 30535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11775 /* 30538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11776 /* 30542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11777 /* 30546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11778 /* 30550 */ // MIs[0] sa
11779 /* 30550 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11780 /* 30553 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11781 /* 30558 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11782 /* 30558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
11783 /* 30561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11784 /* 30563 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11785 /* 30565 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11786 /* 30567 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11787 /* 30569 */ GIR_RootConstrainSelectedInstOperands,
11788 /* 30570 */ // GIR_Coverage, 505,
11789 /* 30570 */ GIR_EraseRootFromParent_Done,
11790 /* 30571 */ // Label 960: @30571
11791 /* 30571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 961*/ GIMT_Encode4(30625), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 506 //
11792 /* 30578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11793 /* 30583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11794 /* 30586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11795 /* 30589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11796 /* 30592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11797 /* 30596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11798 /* 30600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11799 /* 30604 */ // MIs[0] sa
11800 /* 30604 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11801 /* 30607 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11802 /* 30612 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8493:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11803 /* 30612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
11804 /* 30615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11805 /* 30617 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11806 /* 30619 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11807 /* 30621 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11808 /* 30623 */ GIR_RootConstrainSelectedInstOperands,
11809 /* 30624 */ // GIR_Coverage, 506,
11810 /* 30624 */ GIR_EraseRootFromParent_Done,
11811 /* 30625 */ // Label 961: @30625
11812 /* 30625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(30679), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 511 //
11813 /* 30632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
11814 /* 30637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11815 /* 30640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11816 /* 30643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11817 /* 30646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11818 /* 30650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11819 /* 30654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11820 /* 30658 */ // MIs[0] sa
11821 /* 30658 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11822 /* 30661 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11823 /* 30666 */ // (intrinsic_wo_chain:{ *:[i32] } 8005:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11824 /* 30666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
11825 /* 30669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11826 /* 30671 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11827 /* 30673 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11828 /* 30675 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11829 /* 30677 */ GIR_RootConstrainSelectedInstOperands,
11830 /* 30678 */ // GIR_Coverage, 511,
11831 /* 30678 */ GIR_EraseRootFromParent_Done,
11832 /* 30679 */ // Label 962: @30679
11833 /* 30679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(30733), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 512 //
11834 /* 30686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
11835 /* 30691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11836 /* 30694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11837 /* 30697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11838 /* 30700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11839 /* 30704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11840 /* 30708 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11841 /* 30712 */ // MIs[0] sa
11842 /* 30712 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11843 /* 30715 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11844 /* 30720 */ // (intrinsic_wo_chain:{ *:[i32] } 8030:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11845 /* 30720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
11846 /* 30723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11847 /* 30725 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11848 /* 30727 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11849 /* 30729 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11850 /* 30731 */ GIR_RootConstrainSelectedInstOperands,
11851 /* 30732 */ // GIR_Coverage, 512,
11852 /* 30732 */ GIR_EraseRootFromParent_Done,
11853 /* 30733 */ // Label 963: @30733
11854 /* 30733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(30787), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 513 //
11855 /* 30740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
11856 /* 30745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11857 /* 30748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11858 /* 30751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11859 /* 30754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11860 /* 30758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11861 /* 30762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11862 /* 30766 */ // MIs[0] sa
11863 /* 30766 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11864 /* 30769 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11865 /* 30774 */ // (intrinsic_wo_chain:{ *:[i32] } 8498:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11866 /* 30774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
11867 /* 30777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11868 /* 30779 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11869 /* 30781 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11870 /* 30783 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11871 /* 30785 */ GIR_RootConstrainSelectedInstOperands,
11872 /* 30786 */ // GIR_Coverage, 513,
11873 /* 30786 */ GIR_EraseRootFromParent_Done,
11874 /* 30787 */ // Label 964: @30787
11875 /* 30787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(30841), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 981 //
11876 /* 30794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
11877 /* 30799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11878 /* 30802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11879 /* 30805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11880 /* 30808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11881 /* 30812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11882 /* 30816 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11883 /* 30820 */ // MIs[0] n
11884 /* 30820 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11885 /* 30823 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
11886 /* 30828 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8530:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
11887 /* 30828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
11888 /* 30831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11889 /* 30833 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11890 /* 30835 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
11891 /* 30837 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
11892 /* 30839 */ GIR_RootConstrainSelectedInstOperands,
11893 /* 30840 */ // GIR_Coverage, 981,
11894 /* 30840 */ GIR_EraseRootFromParent_Done,
11895 /* 30841 */ // Label 965: @30841
11896 /* 30841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(30895), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 982 //
11897 /* 30848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
11898 /* 30853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11899 /* 30856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11900 /* 30859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11901 /* 30862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11902 /* 30866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11903 /* 30870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11904 /* 30874 */ // MIs[0] n
11905 /* 30874 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11906 /* 30877 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
11907 /* 30882 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8532:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
11908 /* 30882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
11909 /* 30885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11910 /* 30887 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11911 /* 30889 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
11912 /* 30891 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
11913 /* 30893 */ GIR_RootConstrainSelectedInstOperands,
11914 /* 30894 */ // GIR_Coverage, 982,
11915 /* 30894 */ GIR_EraseRootFromParent_Done,
11916 /* 30895 */ // Label 966: @30895
11917 /* 30895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(30949), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 983 //
11918 /* 30902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
11919 /* 30907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11920 /* 30910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11921 /* 30913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11922 /* 30916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11923 /* 30920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11924 /* 30924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11925 /* 30928 */ // MIs[0] n
11926 /* 30928 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11927 /* 30931 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11928 /* 30936 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8533:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
11929 /* 30936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
11930 /* 30939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11931 /* 30941 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11932 /* 30943 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
11933 /* 30945 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
11934 /* 30947 */ GIR_RootConstrainSelectedInstOperands,
11935 /* 30948 */ // GIR_Coverage, 983,
11936 /* 30948 */ GIR_EraseRootFromParent_Done,
11937 /* 30949 */ // Label 967: @30949
11938 /* 30949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(31003), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 984 //
11939 /* 30956 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
11940 /* 30961 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11941 /* 30964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11942 /* 30967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11943 /* 30970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11944 /* 30974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11945 /* 30978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11946 /* 30982 */ // MIs[0] n
11947 /* 30982 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11948 /* 30985 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
11949 /* 30990 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8531:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
11950 /* 30990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
11951 /* 30993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11952 /* 30995 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11953 /* 30997 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
11954 /* 30999 */ GIR_RootToRootCopy, /*OpIdx*/4, // n
11955 /* 31001 */ GIR_RootConstrainSelectedInstOperands,
11956 /* 31002 */ // GIR_Coverage, 984,
11957 /* 31002 */ GIR_EraseRootFromParent_Done,
11958 /* 31003 */ // Label 968: @31003
11959 /* 31003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 969*/ GIMT_Encode4(31057), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1371 //
11960 /* 31010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11961 /* 31015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11962 /* 31018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11963 /* 31021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11964 /* 31024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11965 /* 31028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11966 /* 31032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11967 /* 31036 */ // MIs[0] sa
11968 /* 31036 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11969 /* 31039 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11970 /* 31044 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11971 /* 31044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
11972 /* 31047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11973 /* 31049 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11974 /* 31051 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11975 /* 31053 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11976 /* 31055 */ GIR_RootConstrainSelectedInstOperands,
11977 /* 31056 */ // GIR_Coverage, 1371,
11978 /* 31056 */ GIR_EraseRootFromParent_Done,
11979 /* 31057 */ // Label 969: @31057
11980 /* 31057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 970*/ GIMT_Encode4(31111), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1372 //
11981 /* 31064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11982 /* 31069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11983 /* 31072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11984 /* 31075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11985 /* 31078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11986 /* 31082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11987 /* 31086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11988 /* 31090 */ // MIs[0] sa
11989 /* 31090 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11990 /* 31093 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11991 /* 31098 */ // (intrinsic_wo_chain:{ *:[v2i16] } 8493:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11992 /* 31098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
11993 /* 31101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11994 /* 31103 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
11995 /* 31105 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
11996 /* 31107 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
11997 /* 31109 */ GIR_RootConstrainSelectedInstOperands,
11998 /* 31110 */ // GIR_Coverage, 1372,
11999 /* 31110 */ GIR_EraseRootFromParent_Done,
12000 /* 31111 */ // Label 970: @31111
12001 /* 31111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(31165), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1373 //
12002 /* 31118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
12003 /* 31123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12004 /* 31126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12005 /* 31129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12006 /* 31132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12007 /* 31136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12008 /* 31140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12009 /* 31144 */ // MIs[0] sa
12010 /* 31144 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12011 /* 31147 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12012 /* 31152 */ // (intrinsic_wo_chain:{ *:[i32] } 8498:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12013 /* 31152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
12014 /* 31155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12015 /* 31157 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12016 /* 31159 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12017 /* 31161 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12018 /* 31163 */ GIR_RootConstrainSelectedInstOperands,
12019 /* 31164 */ // GIR_Coverage, 1373,
12020 /* 31164 */ GIR_EraseRootFromParent_Done,
12021 /* 31165 */ // Label 971: @31165
12022 /* 31165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 972*/ GIMT_Encode4(31219), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1374 //
12023 /* 31172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
12024 /* 31177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12025 /* 31180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12026 /* 31183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12027 /* 31186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12028 /* 31190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12029 /* 31194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12030 /* 31198 */ // MIs[0] sa
12031 /* 31198 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
12032 /* 31201 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
12033 /* 31206 */ // (intrinsic_wo_chain:{ *:[i32] } 8005:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
12034 /* 31206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
12035 /* 31209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12036 /* 31211 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12037 /* 31213 */ GIR_RootToRootCopy, /*OpIdx*/4, // sa
12038 /* 31215 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12039 /* 31217 */ GIR_RootConstrainSelectedInstOperands,
12040 /* 31218 */ // GIR_Coverage, 1374,
12041 /* 31218 */ GIR_EraseRootFromParent_Done,
12042 /* 31219 */ // Label 972: @31219
12043 /* 31219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 973*/ GIMT_Encode4(31280), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1349 //
12044 /* 31226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
12045 /* 31231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12046 /* 31234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12047 /* 31237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12048 /* 31240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12049 /* 31244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12050 /* 31248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12051 /* 31252 */ // MIs[0] bp
12052 /* 31252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
12053 /* 31256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12054 /* 31260 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
12055 /* 31264 */ // MIs[1] Operand 1
12056 /* 31264 */ // No operand predicates
12057 /* 31264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
12058 /* 31266 */ // (intrinsic_wo_chain:{ *:[i32] } 8030:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
12059 /* 31266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
12060 /* 31269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12061 /* 31271 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
12062 /* 31273 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
12063 /* 31276 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
12064 /* 31278 */ GIR_RootConstrainSelectedInstOperands,
12065 /* 31279 */ // GIR_Coverage, 1349,
12066 /* 31279 */ GIR_EraseRootFromParent_Done,
12067 /* 31280 */ // Label 973: @31280
12068 /* 31280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(31333), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 580 //
12069 /* 31287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
12070 /* 31292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12071 /* 31295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12072 /* 31298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12073 /* 31301 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12074 /* 31304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12075 /* 31308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12076 /* 31312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12077 /* 31316 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12078 /* 31320 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8039:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12079 /* 31320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
12080 /* 31323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12081 /* 31325 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12082 /* 31327 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12083 /* 31329 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12084 /* 31331 */ GIR_RootConstrainSelectedInstOperands,
12085 /* 31332 */ // GIR_Coverage, 580,
12086 /* 31332 */ GIR_EraseRootFromParent_Done,
12087 /* 31333 */ // Label 974: @31333
12088 /* 31333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 975*/ GIMT_Encode4(31386), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 581 //
12089 /* 31340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
12090 /* 31345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12091 /* 31348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12092 /* 31351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12093 /* 31354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12094 /* 31357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12095 /* 31361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12096 /* 31365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12097 /* 31369 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12098 /* 31373 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8041:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12099 /* 31373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
12100 /* 31376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12101 /* 31378 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12102 /* 31380 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12103 /* 31382 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12104 /* 31384 */ GIR_RootConstrainSelectedInstOperands,
12105 /* 31385 */ // GIR_Coverage, 581,
12106 /* 31385 */ GIR_EraseRootFromParent_Done,
12107 /* 31386 */ // Label 975: @31386
12108 /* 31386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 976*/ GIMT_Encode4(31439), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 582 //
12109 /* 31393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
12110 /* 31398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12111 /* 31401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12112 /* 31404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12113 /* 31407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12114 /* 31410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12115 /* 31414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12116 /* 31418 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12117 /* 31422 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12118 /* 31426 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8042:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12119 /* 31426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
12120 /* 31429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12121 /* 31431 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12122 /* 31433 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12123 /* 31435 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12124 /* 31437 */ GIR_RootConstrainSelectedInstOperands,
12125 /* 31438 */ // GIR_Coverage, 582,
12126 /* 31438 */ GIR_EraseRootFromParent_Done,
12127 /* 31439 */ // Label 976: @31439
12128 /* 31439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(31492), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 583 //
12129 /* 31446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
12130 /* 31451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12131 /* 31454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12132 /* 31457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12133 /* 31460 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12134 /* 31463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12135 /* 31467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12136 /* 31471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12137 /* 31475 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12138 /* 31479 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8040:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12139 /* 31479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
12140 /* 31482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12141 /* 31484 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12142 /* 31486 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12143 /* 31488 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12144 /* 31490 */ GIR_RootConstrainSelectedInstOperands,
12145 /* 31491 */ // GIR_Coverage, 583,
12146 /* 31491 */ GIR_EraseRootFromParent_Done,
12147 /* 31492 */ // Label 977: @31492
12148 /* 31492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(31545), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 588 //
12149 /* 31499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
12150 /* 31504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12151 /* 31507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12152 /* 31510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12153 /* 31513 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12154 /* 31516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12155 /* 31520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12156 /* 31524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12157 /* 31528 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12158 /* 31532 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8047:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12159 /* 31532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
12160 /* 31535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12161 /* 31537 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12162 /* 31539 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12163 /* 31541 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12164 /* 31543 */ GIR_RootConstrainSelectedInstOperands,
12165 /* 31544 */ // GIR_Coverage, 588,
12166 /* 31544 */ GIR_EraseRootFromParent_Done,
12167 /* 31545 */ // Label 978: @31545
12168 /* 31545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(31598), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 589 //
12169 /* 31552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
12170 /* 31557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12171 /* 31560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12172 /* 31563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12173 /* 31566 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12174 /* 31569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12175 /* 31573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12176 /* 31577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12177 /* 31581 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12178 /* 31585 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8049:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12179 /* 31585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
12180 /* 31588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12181 /* 31590 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12182 /* 31592 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12183 /* 31594 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12184 /* 31596 */ GIR_RootConstrainSelectedInstOperands,
12185 /* 31597 */ // GIR_Coverage, 589,
12186 /* 31597 */ GIR_EraseRootFromParent_Done,
12187 /* 31598 */ // Label 979: @31598
12188 /* 31598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(31651), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 590 //
12189 /* 31605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
12190 /* 31610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12191 /* 31613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12192 /* 31616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12193 /* 31619 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12194 /* 31622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12195 /* 31626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12196 /* 31630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12197 /* 31634 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12198 /* 31638 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8050:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12199 /* 31638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
12200 /* 31641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12201 /* 31643 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12202 /* 31645 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12203 /* 31647 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12204 /* 31649 */ GIR_RootConstrainSelectedInstOperands,
12205 /* 31650 */ // GIR_Coverage, 590,
12206 /* 31650 */ GIR_EraseRootFromParent_Done,
12207 /* 31651 */ // Label 980: @31651
12208 /* 31651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(31704), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 591 //
12209 /* 31658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
12210 /* 31663 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12211 /* 31666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12212 /* 31669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12213 /* 31672 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
12214 /* 31675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12215 /* 31679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12216 /* 31683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12217 /* 31687 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12218 /* 31691 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8048:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
12219 /* 31691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
12220 /* 31694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12221 /* 31696 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12222 /* 31698 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12223 /* 31700 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12224 /* 31702 */ GIR_RootConstrainSelectedInstOperands,
12225 /* 31703 */ // GIR_Coverage, 591,
12226 /* 31703 */ GIR_EraseRootFromParent_Done,
12227 /* 31704 */ // Label 981: @31704
12228 /* 31704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 982*/ GIMT_Encode4(31757), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 686 //
12229 /* 31711 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
12230 /* 31716 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12231 /* 31719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12232 /* 31722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12233 /* 31725 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12234 /* 31728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12235 /* 31732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12236 /* 31736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12237 /* 31740 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12238 /* 31744 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8168:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12239 /* 31744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
12240 /* 31747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12241 /* 31749 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12242 /* 31751 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12243 /* 31753 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12244 /* 31755 */ GIR_RootConstrainSelectedInstOperands,
12245 /* 31756 */ // GIR_Coverage, 686,
12246 /* 31756 */ GIR_EraseRootFromParent_Done,
12247 /* 31757 */ // Label 982: @31757
12248 /* 31757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(31810), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 687 //
12249 /* 31764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
12250 /* 31769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12251 /* 31772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12252 /* 31775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12253 /* 31778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12254 /* 31781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12255 /* 31785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12256 /* 31789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12257 /* 31793 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12258 /* 31797 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8169:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12259 /* 31797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
12260 /* 31800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12261 /* 31802 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12262 /* 31804 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12263 /* 31806 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12264 /* 31808 */ GIR_RootConstrainSelectedInstOperands,
12265 /* 31809 */ // GIR_Coverage, 687,
12266 /* 31809 */ GIR_EraseRootFromParent_Done,
12267 /* 31810 */ // Label 983: @31810
12268 /* 31810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 984*/ GIMT_Encode4(31863), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 688 //
12269 /* 31817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
12270 /* 31822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12271 /* 31825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12272 /* 31828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12273 /* 31831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12274 /* 31834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12275 /* 31838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12276 /* 31842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12277 /* 31846 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12278 /* 31850 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8167:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12279 /* 31850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
12280 /* 31853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12281 /* 31855 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12282 /* 31857 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12283 /* 31859 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12284 /* 31861 */ GIR_RootConstrainSelectedInstOperands,
12285 /* 31862 */ // GIR_Coverage, 688,
12286 /* 31862 */ GIR_EraseRootFromParent_Done,
12287 /* 31863 */ // Label 984: @31863
12288 /* 31863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 985*/ GIMT_Encode4(31916), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 689 //
12289 /* 31870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
12290 /* 31875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12291 /* 31878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12292 /* 31881 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12293 /* 31884 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12294 /* 31887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12295 /* 31891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12296 /* 31895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12297 /* 31899 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12298 /* 31903 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8171:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12299 /* 31903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
12300 /* 31906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12301 /* 31908 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12302 /* 31910 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12303 /* 31912 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12304 /* 31914 */ GIR_RootConstrainSelectedInstOperands,
12305 /* 31915 */ // GIR_Coverage, 689,
12306 /* 31915 */ GIR_EraseRootFromParent_Done,
12307 /* 31916 */ // Label 985: @31916
12308 /* 31916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(31969), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 690 //
12309 /* 31923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
12310 /* 31928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12311 /* 31931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12312 /* 31934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12313 /* 31937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12314 /* 31940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12315 /* 31944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12316 /* 31948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12317 /* 31952 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12318 /* 31956 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8172:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12319 /* 31956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
12320 /* 31959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12321 /* 31961 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12322 /* 31963 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12323 /* 31965 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12324 /* 31967 */ GIR_RootConstrainSelectedInstOperands,
12325 /* 31968 */ // GIR_Coverage, 690,
12326 /* 31968 */ GIR_EraseRootFromParent_Done,
12327 /* 31969 */ // Label 986: @31969
12328 /* 31969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(32022), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 691 //
12329 /* 31976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
12330 /* 31981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12331 /* 31984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12332 /* 31987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12333 /* 31990 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12334 /* 31993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12335 /* 31997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12336 /* 32001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12337 /* 32005 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12338 /* 32009 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8170:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12339 /* 32009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
12340 /* 32012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12341 /* 32014 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12342 /* 32016 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12343 /* 32018 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12344 /* 32020 */ GIR_RootConstrainSelectedInstOperands,
12345 /* 32021 */ // GIR_Coverage, 691,
12346 /* 32021 */ GIR_EraseRootFromParent_Done,
12347 /* 32022 */ // Label 987: @32022
12348 /* 32022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(32075), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 692 //
12349 /* 32029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
12350 /* 32034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12351 /* 32037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12352 /* 32040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12353 /* 32043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12354 /* 32046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12355 /* 32050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12356 /* 32054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12357 /* 32058 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12358 /* 32062 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8188:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12359 /* 32062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
12360 /* 32065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12361 /* 32067 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12362 /* 32069 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12363 /* 32071 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12364 /* 32073 */ GIR_RootConstrainSelectedInstOperands,
12365 /* 32074 */ // GIR_Coverage, 692,
12366 /* 32074 */ GIR_EraseRootFromParent_Done,
12367 /* 32075 */ // Label 988: @32075
12368 /* 32075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(32128), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 693 //
12369 /* 32082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
12370 /* 32087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12371 /* 32090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12372 /* 32093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12373 /* 32096 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12374 /* 32099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12375 /* 32103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12376 /* 32107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12377 /* 32111 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12378 /* 32115 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8189:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12379 /* 32115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
12380 /* 32118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12381 /* 32120 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12382 /* 32122 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12383 /* 32124 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12384 /* 32126 */ GIR_RootConstrainSelectedInstOperands,
12385 /* 32127 */ // GIR_Coverage, 693,
12386 /* 32127 */ GIR_EraseRootFromParent_Done,
12387 /* 32128 */ // Label 989: @32128
12388 /* 32128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(32181), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 694 //
12389 /* 32135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
12390 /* 32140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12391 /* 32143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12392 /* 32146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12393 /* 32149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12394 /* 32152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12395 /* 32156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12396 /* 32160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12397 /* 32164 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12398 /* 32168 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8187:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12399 /* 32168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
12400 /* 32171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12401 /* 32173 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12402 /* 32175 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12403 /* 32177 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12404 /* 32179 */ GIR_RootConstrainSelectedInstOperands,
12405 /* 32180 */ // GIR_Coverage, 694,
12406 /* 32180 */ GIR_EraseRootFromParent_Done,
12407 /* 32181 */ // Label 990: @32181
12408 /* 32181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(32234), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 695 //
12409 /* 32188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
12410 /* 32193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12411 /* 32196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12412 /* 32199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12413 /* 32202 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
12414 /* 32205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12415 /* 32209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12416 /* 32213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12417 /* 32217 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12418 /* 32221 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8191:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
12419 /* 32221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
12420 /* 32224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12421 /* 32226 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12422 /* 32228 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12423 /* 32230 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12424 /* 32232 */ GIR_RootConstrainSelectedInstOperands,
12425 /* 32233 */ // GIR_Coverage, 695,
12426 /* 32233 */ GIR_EraseRootFromParent_Done,
12427 /* 32234 */ // Label 991: @32234
12428 /* 32234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(32287), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 696 //
12429 /* 32241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
12430 /* 32246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12431 /* 32249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12432 /* 32252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12433 /* 32255 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12434 /* 32258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12435 /* 32262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12436 /* 32266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12437 /* 32270 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12438 /* 32274 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8192:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12439 /* 32274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
12440 /* 32277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12441 /* 32279 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12442 /* 32281 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12443 /* 32283 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12444 /* 32285 */ GIR_RootConstrainSelectedInstOperands,
12445 /* 32286 */ // GIR_Coverage, 696,
12446 /* 32286 */ GIR_EraseRootFromParent_Done,
12447 /* 32287 */ // Label 992: @32287
12448 /* 32287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 993*/ GIMT_Encode4(32340), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 697 //
12449 /* 32294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
12450 /* 32299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12451 /* 32302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12452 /* 32305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12453 /* 32308 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12454 /* 32311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12455 /* 32315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12456 /* 32319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12457 /* 32323 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12458 /* 32327 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8190:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12459 /* 32327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
12460 /* 32330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12461 /* 32332 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12462 /* 32334 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12463 /* 32336 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12464 /* 32338 */ GIR_RootConstrainSelectedInstOperands,
12465 /* 32339 */ // GIR_Coverage, 697,
12466 /* 32339 */ GIR_EraseRootFromParent_Done,
12467 /* 32340 */ // Label 993: @32340
12468 /* 32340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 994*/ GIMT_Encode4(32393), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 864 //
12469 /* 32347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
12470 /* 32352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12471 /* 32355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12472 /* 32358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12473 /* 32361 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12474 /* 32364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12475 /* 32368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12476 /* 32372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12477 /* 32376 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12478 /* 32380 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8358:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12479 /* 32380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
12480 /* 32383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12481 /* 32385 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12482 /* 32387 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12483 /* 32389 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12484 /* 32391 */ GIR_RootConstrainSelectedInstOperands,
12485 /* 32392 */ // GIR_Coverage, 864,
12486 /* 32392 */ GIR_EraseRootFromParent_Done,
12487 /* 32393 */ // Label 994: @32393
12488 /* 32393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 995*/ GIMT_Encode4(32446), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 865 //
12489 /* 32400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
12490 /* 32405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12491 /* 32408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12492 /* 32411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12493 /* 32414 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12494 /* 32417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12495 /* 32421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12496 /* 32425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12497 /* 32429 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12498 /* 32433 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8359:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12499 /* 32433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
12500 /* 32436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12501 /* 32438 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12502 /* 32440 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12503 /* 32442 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12504 /* 32444 */ GIR_RootConstrainSelectedInstOperands,
12505 /* 32445 */ // GIR_Coverage, 865,
12506 /* 32445 */ GIR_EraseRootFromParent_Done,
12507 /* 32446 */ // Label 995: @32446
12508 /* 32446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 996*/ GIMT_Encode4(32499), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 866 //
12509 /* 32453 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
12510 /* 32458 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12511 /* 32461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12512 /* 32464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12513 /* 32467 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12514 /* 32470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12515 /* 32474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12516 /* 32478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12517 /* 32482 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12518 /* 32486 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8360:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12519 /* 32486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
12520 /* 32489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12521 /* 32491 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12522 /* 32493 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12523 /* 32495 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12524 /* 32497 */ GIR_RootConstrainSelectedInstOperands,
12525 /* 32498 */ // GIR_Coverage, 866,
12526 /* 32498 */ GIR_EraseRootFromParent_Done,
12527 /* 32499 */ // Label 996: @32499
12528 /* 32499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 997*/ GIMT_Encode4(32552), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 867 //
12529 /* 32506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
12530 /* 32511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12531 /* 32514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12532 /* 32517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12533 /* 32520 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12534 /* 32523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12535 /* 32527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12536 /* 32531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12537 /* 32535 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12538 /* 32539 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8361:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12539 /* 32539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
12540 /* 32542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12541 /* 32544 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12542 /* 32546 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12543 /* 32548 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12544 /* 32550 */ GIR_RootConstrainSelectedInstOperands,
12545 /* 32551 */ // GIR_Coverage, 867,
12546 /* 32551 */ GIR_EraseRootFromParent_Done,
12547 /* 32552 */ // Label 997: @32552
12548 /* 32552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 998*/ GIMT_Encode4(32605), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 920 //
12549 /* 32559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
12550 /* 32564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12551 /* 32567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12552 /* 32570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12553 /* 32573 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12554 /* 32576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12555 /* 32580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12556 /* 32584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12557 /* 32588 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12558 /* 32592 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8422:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12559 /* 32592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
12560 /* 32595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12561 /* 32597 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12562 /* 32599 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12563 /* 32601 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12564 /* 32603 */ GIR_RootConstrainSelectedInstOperands,
12565 /* 32604 */ // GIR_Coverage, 920,
12566 /* 32604 */ GIR_EraseRootFromParent_Done,
12567 /* 32605 */ // Label 998: @32605
12568 /* 32605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 999*/ GIMT_Encode4(32658), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 921 //
12569 /* 32612 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
12570 /* 32617 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12571 /* 32620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12572 /* 32623 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12573 /* 32626 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12574 /* 32629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12575 /* 32633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12576 /* 32637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12577 /* 32641 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12578 /* 32645 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8423:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12579 /* 32645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
12580 /* 32648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12581 /* 32650 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12582 /* 32652 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12583 /* 32654 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12584 /* 32656 */ GIR_RootConstrainSelectedInstOperands,
12585 /* 32657 */ // GIR_Coverage, 921,
12586 /* 32657 */ GIR_EraseRootFromParent_Done,
12587 /* 32658 */ // Label 999: @32658
12588 /* 32658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(32711), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 922 //
12589 /* 32665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
12590 /* 32670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12591 /* 32673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12592 /* 32676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12593 /* 32679 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
12594 /* 32682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12595 /* 32686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12596 /* 32690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12597 /* 32694 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12598 /* 32698 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8424:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
12599 /* 32698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
12600 /* 32701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12601 /* 32703 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12602 /* 32705 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12603 /* 32707 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12604 /* 32709 */ GIR_RootConstrainSelectedInstOperands,
12605 /* 32710 */ // GIR_Coverage, 922,
12606 /* 32710 */ GIR_EraseRootFromParent_Done,
12607 /* 32711 */ // Label 1000: @32711
12608 /* 32711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(32764), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 923 //
12609 /* 32718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
12610 /* 32723 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12611 /* 32726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12612 /* 32729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12613 /* 32732 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
12614 /* 32735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12615 /* 32739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12616 /* 32743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12617 /* 32747 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12618 /* 32751 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8425:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
12619 /* 32751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
12620 /* 32754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12621 /* 32756 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12622 /* 32758 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12623 /* 32760 */ GIR_RootToRootCopy, /*OpIdx*/4, // wt
12624 /* 32762 */ GIR_RootConstrainSelectedInstOperands,
12625 /* 32763 */ // GIR_Coverage, 923,
12626 /* 32763 */ GIR_EraseRootFromParent_Done,
12627 /* 32764 */ // Label 1001: @32764
12628 /* 32764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(32817), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 977 //
12629 /* 32771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
12630 /* 32776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
12631 /* 32779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
12632 /* 32782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
12633 /* 32785 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12634 /* 32788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12635 /* 32792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12636 /* 32796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
12637 /* 32800 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12638 /* 32804 */ // (intrinsic_wo_chain:{ *:[v16i8] } 8526:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12639 /* 32804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
12640 /* 32807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12641 /* 32809 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12642 /* 32811 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12643 /* 32813 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12644 /* 32815 */ GIR_RootConstrainSelectedInstOperands,
12645 /* 32816 */ // GIR_Coverage, 977,
12646 /* 32816 */ GIR_EraseRootFromParent_Done,
12647 /* 32817 */ // Label 1002: @32817
12648 /* 32817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1003*/ GIMT_Encode4(32870), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 978 //
12649 /* 32824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
12650 /* 32829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
12651 /* 32832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
12652 /* 32835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
12653 /* 32838 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12654 /* 32841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12655 /* 32845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12656 /* 32849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
12657 /* 32853 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12658 /* 32857 */ // (intrinsic_wo_chain:{ *:[v8i16] } 8528:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12659 /* 32857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
12660 /* 32860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12661 /* 32862 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12662 /* 32864 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12663 /* 32866 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12664 /* 32868 */ GIR_RootConstrainSelectedInstOperands,
12665 /* 32869 */ // GIR_Coverage, 978,
12666 /* 32869 */ GIR_EraseRootFromParent_Done,
12667 /* 32870 */ // Label 1003: @32870
12668 /* 32870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1004*/ GIMT_Encode4(32923), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 979 //
12669 /* 32877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
12670 /* 32882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
12671 /* 32885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
12672 /* 32888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
12673 /* 32891 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12674 /* 32894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12675 /* 32898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12676 /* 32902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
12677 /* 32906 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12678 /* 32910 */ // (intrinsic_wo_chain:{ *:[v4i32] } 8529:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12679 /* 32910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
12680 /* 32913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12681 /* 32915 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12682 /* 32917 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12683 /* 32919 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12684 /* 32921 */ GIR_RootConstrainSelectedInstOperands,
12685 /* 32922 */ // GIR_Coverage, 979,
12686 /* 32922 */ GIR_EraseRootFromParent_Done,
12687 /* 32923 */ // Label 1004: @32923
12688 /* 32923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(32976), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 980 //
12689 /* 32930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
12690 /* 32935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
12691 /* 32938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
12692 /* 32941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
12693 /* 32944 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
12694 /* 32947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12695 /* 32951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12696 /* 32955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12697 /* 32959 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12698 /* 32963 */ // (intrinsic_wo_chain:{ *:[v2i64] } 8527:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12699 /* 32963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
12700 /* 32966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12701 /* 32968 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12702 /* 32970 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
12703 /* 32972 */ GIR_RootToRootCopy, /*OpIdx*/4, // rt
12704 /* 32974 */ GIR_RootConstrainSelectedInstOperands,
12705 /* 32975 */ // GIR_Coverage, 980,
12706 /* 32975 */ GIR_EraseRootFromParent_Done,
12707 /* 32976 */ // Label 1005: @32976
12708 /* 32976 */ GIM_Reject,
12709 /* 32977 */ // Label 959: @32977
12710 /* 32977 */ GIM_Reject,
12711 /* 32978 */ // Label 30: @32978
12712 /* 32978 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(33009), // Rule ID 382 //
12713 /* 32983 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
12714 /* 32986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
12715 /* 32991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12716 /* 32994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12717 /* 32998 */ // (intrinsic_w_chain:{ *:[i32] } 8073:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
12718 /* 32998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
12719 /* 33001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12720 /* 33003 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12721 /* 33007 */ GIR_RootConstrainSelectedInstOperands,
12722 /* 33008 */ // GIR_Coverage, 382,
12723 /* 33008 */ GIR_EraseRootFromParent_Done,
12724 /* 33009 */ // Label 1006: @33009
12725 /* 33009 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(33906),
12726 /* 33014 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
12727 /* 33017 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(33083),
12728 /* 33022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12729 /* 33027 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12730 /* 33030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12731 /* 33034 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12732 /* 33037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1009*/ GIMT_Encode4(33062), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 469 //
12733 /* 33044 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12734 /* 33049 */ // (intrinsic_w_chain:{ *:[i32] } 8500:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12735 /* 33049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
12736 /* 33052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12737 /* 33054 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12738 /* 33056 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12739 /* 33060 */ GIR_RootConstrainSelectedInstOperands,
12740 /* 33061 */ // GIR_Coverage, 469,
12741 /* 33061 */ GIR_EraseRootFromParent_Done,
12742 /* 33062 */ // Label 1009: @33062
12743 /* 33062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(33082), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1309 //
12744 /* 33069 */ // (intrinsic_w_chain:{ *:[i32] } 8500:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12745 /* 33069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
12746 /* 33072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12747 /* 33074 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12748 /* 33076 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12749 /* 33080 */ GIR_RootConstrainSelectedInstOperands,
12750 /* 33081 */ // GIR_Coverage, 1309,
12751 /* 33081 */ GIR_EraseRootFromParent_Done,
12752 /* 33082 */ // Label 1010: @33082
12753 /* 33082 */ GIM_Reject,
12754 /* 33083 */ // Label 1008: @33083
12755 /* 33083 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(33149),
12756 /* 33088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12757 /* 33093 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12758 /* 33096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12759 /* 33100 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12760 /* 33103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(33128), GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips), // Rule ID 470 //
12761 /* 33110 */ GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12762 /* 33115 */ // (intrinsic_void 8629:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
12763 /* 33115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
12764 /* 33118 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12765 /* 33120 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12766 /* 33122 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12767 /* 33126 */ GIR_RootConstrainSelectedInstOperands,
12768 /* 33127 */ // GIR_Coverage, 470,
12769 /* 33127 */ GIR_EraseRootFromParent_Done,
12770 /* 33128 */ // Label 1012: @33128
12771 /* 33128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(33148), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1320 //
12772 /* 33135 */ // (intrinsic_void 8629:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
12773 /* 33135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
12774 /* 33138 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
12775 /* 33140 */ GIR_RootToRootCopy, /*OpIdx*/2, // mask
12776 /* 33142 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12777 /* 33146 */ GIR_RootConstrainSelectedInstOperands,
12778 /* 33147 */ // GIR_Coverage, 1320,
12779 /* 33147 */ GIR_EraseRootFromParent_Done,
12780 /* 33148 */ // Label 1013: @33148
12781 /* 33148 */ GIM_Reject,
12782 /* 33149 */ // Label 1011: @33149
12783 /* 33149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(33191), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 391 //
12784 /* 33156 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12785 /* 33161 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12786 /* 33164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12787 /* 33167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12788 /* 33171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12789 /* 33175 */ // (intrinsic_w_chain:{ *:[v2i16] } 7961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
12790 /* 33175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
12791 /* 33178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12792 /* 33180 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12793 /* 33182 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12794 /* 33185 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12795 /* 33189 */ GIR_RootConstrainSelectedInstOperands,
12796 /* 33190 */ // GIR_Coverage, 391,
12797 /* 33190 */ GIR_EraseRootFromParent_Done,
12798 /* 33191 */ // Label 1014: @33191
12799 /* 33191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(33233), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 392 //
12800 /* 33198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12801 /* 33203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12802 /* 33206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12803 /* 33209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12804 /* 33213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12805 /* 33217 */ // (intrinsic_w_chain:{ *:[i32] } 7963:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
12806 /* 33217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
12807 /* 33220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12808 /* 33222 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12809 /* 33224 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12810 /* 33227 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12811 /* 33231 */ GIR_RootConstrainSelectedInstOperands,
12812 /* 33232 */ // GIR_Coverage, 392,
12813 /* 33232 */ GIR_EraseRootFromParent_Done,
12814 /* 33233 */ // Label 1015: @33233
12815 /* 33233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(33275), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 478 //
12816 /* 33240 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12817 /* 33245 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12818 /* 33248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12819 /* 33251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12820 /* 33255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12821 /* 33259 */ // (intrinsic_w_chain:{ *:[v4i8] } 7962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
12822 /* 33259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
12823 /* 33262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12824 /* 33264 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12825 /* 33266 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12826 /* 33269 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12827 /* 33273 */ GIR_RootConstrainSelectedInstOperands,
12828 /* 33274 */ // GIR_Coverage, 478,
12829 /* 33274 */ GIR_EraseRootFromParent_Done,
12830 /* 33275 */ // Label 1016: @33275
12831 /* 33275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1017*/ GIMT_Encode4(33317), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1252 //
12832 /* 33282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12833 /* 33287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12834 /* 33290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12835 /* 33293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12836 /* 33297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12837 /* 33301 */ // (intrinsic_w_chain:{ *:[v2i16] } 7961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
12838 /* 33301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
12839 /* 33304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12840 /* 33306 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12841 /* 33308 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12842 /* 33311 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12843 /* 33315 */ GIR_RootConstrainSelectedInstOperands,
12844 /* 33316 */ // GIR_Coverage, 1252,
12845 /* 33316 */ GIR_EraseRootFromParent_Done,
12846 /* 33317 */ // Label 1017: @33317
12847 /* 33317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1018*/ GIMT_Encode4(33359), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1253 //
12848 /* 33324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12849 /* 33329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12850 /* 33332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12851 /* 33335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12852 /* 33339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12853 /* 33343 */ // (intrinsic_w_chain:{ *:[i32] } 7963:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
12854 /* 33343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
12855 /* 33346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12856 /* 33348 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12857 /* 33350 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12858 /* 33353 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12859 /* 33357 */ GIR_RootConstrainSelectedInstOperands,
12860 /* 33358 */ // GIR_Coverage, 1253,
12861 /* 33358 */ GIR_EraseRootFromParent_Done,
12862 /* 33359 */ // Label 1018: @33359
12863 /* 33359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(33401), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1333 //
12864 /* 33366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12865 /* 33371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12866 /* 33374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12867 /* 33377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12868 /* 33381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12869 /* 33385 */ // (intrinsic_w_chain:{ *:[v4i8] } 7962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
12870 /* 33385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
12871 /* 33388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12872 /* 33390 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
12873 /* 33392 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12874 /* 33395 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12875 /* 33399 */ GIR_RootConstrainSelectedInstOperands,
12876 /* 33400 */ // GIR_Coverage, 1333,
12877 /* 33400 */ GIR_EraseRootFromParent_Done,
12878 /* 33401 */ // Label 1019: @33401
12879 /* 33401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(33443), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 445 //
12880 /* 33408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
12881 /* 33413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12882 /* 33416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12883 /* 33419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12884 /* 33423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12885 /* 33427 */ // (intrinsic_void 8139:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12886 /* 33427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
12887 /* 33430 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12888 /* 33432 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12889 /* 33434 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12890 /* 33437 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12891 /* 33441 */ GIR_RootConstrainSelectedInstOperands,
12892 /* 33442 */ // GIR_Coverage, 445,
12893 /* 33442 */ GIR_EraseRootFromParent_Done,
12894 /* 33443 */ // Label 1020: @33443
12895 /* 33443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(33485), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 446 //
12896 /* 33450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
12897 /* 33455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12898 /* 33458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12899 /* 33461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12900 /* 33465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12901 /* 33469 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12902 /* 33469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
12903 /* 33472 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12904 /* 33474 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12905 /* 33476 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12906 /* 33479 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12907 /* 33483 */ GIR_RootConstrainSelectedInstOperands,
12908 /* 33484 */ // GIR_Coverage, 446,
12909 /* 33484 */ GIR_EraseRootFromParent_Done,
12910 /* 33485 */ // Label 1021: @33485
12911 /* 33485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(33527), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 447 //
12912 /* 33492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
12913 /* 33497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12914 /* 33500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12915 /* 33503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12916 /* 33507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12917 /* 33511 */ // (intrinsic_void 8140:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12918 /* 33511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
12919 /* 33514 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12920 /* 33516 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12921 /* 33518 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12922 /* 33521 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12923 /* 33525 */ GIR_RootConstrainSelectedInstOperands,
12924 /* 33526 */ // GIR_Coverage, 447,
12925 /* 33526 */ GIR_EraseRootFromParent_Done,
12926 /* 33527 */ // Label 1022: @33527
12927 /* 33527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(33569), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 451 //
12928 /* 33534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12929 /* 33539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12930 /* 33542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12931 /* 33545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12932 /* 33549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12933 /* 33553 */ // (intrinsic_void 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12934 /* 33553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
12935 /* 33556 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12936 /* 33558 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12937 /* 33560 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12938 /* 33563 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12939 /* 33567 */ GIR_RootConstrainSelectedInstOperands,
12940 /* 33568 */ // GIR_Coverage, 451,
12941 /* 33568 */ GIR_EraseRootFromParent_Done,
12942 /* 33569 */ // Label 1023: @33569
12943 /* 33569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(33611), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 452 //
12944 /* 33576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12945 /* 33581 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12946 /* 33584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12947 /* 33587 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12948 /* 33591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12949 /* 33595 */ // (intrinsic_void 8132:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12950 /* 33595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
12951 /* 33598 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12952 /* 33600 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12953 /* 33602 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12954 /* 33605 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12955 /* 33609 */ GIR_RootConstrainSelectedInstOperands,
12956 /* 33610 */ // GIR_Coverage, 452,
12957 /* 33610 */ GIR_EraseRootFromParent_Done,
12958 /* 33611 */ // Label 1024: @33611
12959 /* 33611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(33653), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 453 //
12960 /* 33618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
12961 /* 33623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12962 /* 33626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12963 /* 33629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12964 /* 33633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12965 /* 33637 */ // (intrinsic_void 8131:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12966 /* 33637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
12967 /* 33640 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12968 /* 33642 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12969 /* 33644 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12970 /* 33647 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12971 /* 33651 */ GIR_RootConstrainSelectedInstOperands,
12972 /* 33652 */ // GIR_Coverage, 453,
12973 /* 33652 */ GIR_EraseRootFromParent_Done,
12974 /* 33653 */ // Label 1025: @33653
12975 /* 33653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1026*/ GIMT_Encode4(33695), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1324 //
12976 /* 33660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12977 /* 33665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12978 /* 33668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12979 /* 33671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12980 /* 33675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12981 /* 33679 */ // (intrinsic_void 8130:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12982 /* 33679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
12983 /* 33682 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
12984 /* 33684 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
12985 /* 33686 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12986 /* 33689 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12987 /* 33693 */ GIR_RootConstrainSelectedInstOperands,
12988 /* 33694 */ // GIR_Coverage, 1324,
12989 /* 33694 */ GIR_EraseRootFromParent_Done,
12990 /* 33695 */ // Label 1026: @33695
12991 /* 33695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1027*/ GIMT_Encode4(33737), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1325 //
12992 /* 33702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12993 /* 33707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12994 /* 33710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12995 /* 33713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12996 /* 33717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12997 /* 33721 */ // (intrinsic_void 8132:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12998 /* 33721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
12999 /* 33724 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13000 /* 33726 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13001 /* 33728 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13002 /* 33731 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13003 /* 33735 */ GIR_RootConstrainSelectedInstOperands,
13004 /* 33736 */ // GIR_Coverage, 1325,
13005 /* 33736 */ GIR_EraseRootFromParent_Done,
13006 /* 33737 */ // Label 1027: @33737
13007 /* 33737 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(33779), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1326 //
13008 /* 33744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
13009 /* 33749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
13010 /* 33752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13011 /* 33755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13012 /* 33759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13013 /* 33763 */ // (intrinsic_void 8131:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13014 /* 33763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
13015 /* 33766 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13016 /* 33768 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13017 /* 33770 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13018 /* 33773 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13019 /* 33777 */ GIR_RootConstrainSelectedInstOperands,
13020 /* 33778 */ // GIR_Coverage, 1326,
13021 /* 33778 */ GIR_EraseRootFromParent_Done,
13022 /* 33779 */ // Label 1028: @33779
13023 /* 33779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1029*/ GIMT_Encode4(33821), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1330 //
13024 /* 33786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
13025 /* 33791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13026 /* 33794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13027 /* 33797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13028 /* 33801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13029 /* 33805 */ // (intrinsic_void 8139:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13030 /* 33805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
13031 /* 33808 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13032 /* 33810 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13033 /* 33812 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13034 /* 33815 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13035 /* 33819 */ GIR_RootConstrainSelectedInstOperands,
13036 /* 33820 */ // GIR_Coverage, 1330,
13037 /* 33820 */ GIR_EraseRootFromParent_Done,
13038 /* 33821 */ // Label 1029: @33821
13039 /* 33821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1030*/ GIMT_Encode4(33863), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1331 //
13040 /* 33828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
13041 /* 33833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13042 /* 33836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13043 /* 33839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13044 /* 33843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13045 /* 33847 */ // (intrinsic_void 8141:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13046 /* 33847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
13047 /* 33850 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13048 /* 33852 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13049 /* 33854 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13050 /* 33857 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13051 /* 33861 */ GIR_RootConstrainSelectedInstOperands,
13052 /* 33862 */ // GIR_Coverage, 1331,
13053 /* 33862 */ GIR_EraseRootFromParent_Done,
13054 /* 33863 */ // Label 1030: @33863
13055 /* 33863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1031*/ GIMT_Encode4(33905), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1332 //
13056 /* 33870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
13057 /* 33875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
13058 /* 33878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13059 /* 33881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13060 /* 33885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13061 /* 33889 */ // (intrinsic_void 8140:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13062 /* 33889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
13063 /* 33892 */ GIR_RootToRootCopy, /*OpIdx*/1, // rs
13064 /* 33894 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13065 /* 33896 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13066 /* 33899 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13067 /* 33903 */ GIR_RootConstrainSelectedInstOperands,
13068 /* 33904 */ // GIR_Coverage, 1332,
13069 /* 33904 */ GIR_EraseRootFromParent_Done,
13070 /* 33905 */ // Label 1031: @33905
13071 /* 33905 */ GIM_Reject,
13072 /* 33906 */ // Label 1007: @33906
13073 /* 33906 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(37937),
13074 /* 33911 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
13075 /* 33914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(33977), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 410 //
13076 /* 33921 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13077 /* 33926 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13078 /* 33929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13079 /* 33932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13080 /* 33935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13081 /* 33939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13082 /* 33943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13083 /* 33947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13084 /* 33951 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13085 /* 33955 */ // MIs[1] Operand 1
13086 /* 33955 */ // No operand predicates
13087 /* 33955 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13088 /* 33957 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13089 /* 33957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
13090 /* 33960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13091 /* 33962 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13092 /* 33964 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13093 /* 33967 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13094 /* 33970 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13095 /* 33975 */ GIR_RootConstrainSelectedInstOperands,
13096 /* 33976 */ // GIR_Coverage, 410,
13097 /* 33976 */ GIR_EraseRootFromParent_Done,
13098 /* 33977 */ // Label 1033: @33977
13099 /* 33977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1034*/ GIMT_Encode4(34040), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 415 //
13100 /* 33984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13101 /* 33989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13102 /* 33992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13103 /* 33995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13104 /* 33998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13105 /* 34002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13106 /* 34006 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13107 /* 34010 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13108 /* 34014 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13109 /* 34018 */ // MIs[1] Operand 1
13110 /* 34018 */ // No operand predicates
13111 /* 34018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13112 /* 34020 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
13113 /* 34020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
13114 /* 34023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13115 /* 34025 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13116 /* 34027 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
13117 /* 34030 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13118 /* 34033 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13119 /* 34038 */ GIR_RootConstrainSelectedInstOperands,
13120 /* 34039 */ // GIR_Coverage, 415,
13121 /* 34039 */ GIR_EraseRootFromParent_Done,
13122 /* 34040 */ // Label 1034: @34040
13123 /* 34040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1035*/ GIMT_Encode4(34103), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1261 //
13124 /* 34047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13125 /* 34052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13126 /* 34055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13127 /* 34058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13128 /* 34061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13129 /* 34065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13130 /* 34069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13131 /* 34073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13132 /* 34077 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13133 /* 34081 */ // MIs[1] Operand 1
13134 /* 34081 */ // No operand predicates
13135 /* 34081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13136 /* 34083 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
13137 /* 34083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
13138 /* 34086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13139 /* 34088 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13140 /* 34090 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13141 /* 34093 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13142 /* 34096 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13143 /* 34101 */ GIR_RootConstrainSelectedInstOperands,
13144 /* 34102 */ // GIR_Coverage, 1261,
13145 /* 34102 */ GIR_EraseRootFromParent_Done,
13146 /* 34103 */ // Label 1035: @34103
13147 /* 34103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1036*/ GIMT_Encode4(34166), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1266 //
13148 /* 34110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13149 /* 34115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13150 /* 34118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13151 /* 34121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13152 /* 34124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13153 /* 34128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13154 /* 34132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13155 /* 34136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13156 /* 34140 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13157 /* 34144 */ // MIs[1] Operand 1
13158 /* 34144 */ // No operand predicates
13159 /* 34144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13160 /* 34146 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
13161 /* 34146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
13162 /* 34149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13163 /* 34151 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13164 /* 34153 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
13165 /* 34156 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13166 /* 34159 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
13167 /* 34164 */ GIR_RootConstrainSelectedInstOperands,
13168 /* 34165 */ // GIR_Coverage, 1266,
13169 /* 34165 */ GIR_EraseRootFromParent_Done,
13170 /* 34166 */ // Label 1036: @34166
13171 /* 34166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(34220), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2072 //
13172 /* 34173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13173 /* 34178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13174 /* 34181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13175 /* 34184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13176 /* 34187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13177 /* 34191 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13178 /* 34195 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13179 /* 34199 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
13180 /* 34203 */ // MIs[1] Operand 1
13181 /* 34203 */ // No operand predicates
13182 /* 34203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13183 /* 34205 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
13184 /* 34205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
13185 /* 34208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13186 /* 34210 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13187 /* 34212 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13188 /* 34215 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13189 /* 34218 */ GIR_RootConstrainSelectedInstOperands,
13190 /* 34219 */ // GIR_Coverage, 2072,
13191 /* 34219 */ GIR_EraseRootFromParent_Done,
13192 /* 34220 */ // Label 1037: @34220
13193 /* 34220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(34274), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2078 //
13194 /* 34227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13195 /* 34232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13196 /* 34235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13197 /* 34238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13198 /* 34241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13199 /* 34245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
13200 /* 34249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13201 /* 34253 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
13202 /* 34257 */ // MIs[1] Operand 1
13203 /* 34257 */ // No operand predicates
13204 /* 34257 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
13205 /* 34259 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
13206 /* 34259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
13207 /* 34262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13208 /* 34264 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
13209 /* 34266 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
13210 /* 34269 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13211 /* 34272 */ GIR_RootConstrainSelectedInstOperands,
13212 /* 34273 */ // GIR_Coverage, 2078,
13213 /* 34273 */ GIR_EraseRootFromParent_Done,
13214 /* 34274 */ // Label 1038: @34274
13215 /* 34274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(34325), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 387 //
13216 /* 34281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13217 /* 34286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13218 /* 34289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13219 /* 34292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13220 /* 34295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13221 /* 34299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13222 /* 34303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13223 /* 34307 */ // (intrinsic_w_chain:{ *:[i32] } 7970:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13224 /* 34307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
13225 /* 34310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13226 /* 34312 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13227 /* 34314 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13228 /* 34316 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13229 /* 34319 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13230 /* 34323 */ GIR_RootConstrainSelectedInstOperands,
13231 /* 34324 */ // GIR_Coverage, 387,
13232 /* 34324 */ GIR_EraseRootFromParent_Done,
13233 /* 34325 */ // Label 1039: @34325
13234 /* 34325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(34376), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 388 //
13235 /* 34332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13236 /* 34337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13237 /* 34340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13238 /* 34343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13239 /* 34346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13240 /* 34350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13241 /* 34354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13242 /* 34358 */ // (intrinsic_w_chain:{ *:[i32] } 8590:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13243 /* 34358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
13244 /* 34361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13245 /* 34363 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13246 /* 34365 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13247 /* 34367 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13248 /* 34370 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13249 /* 34374 */ GIR_RootConstrainSelectedInstOperands,
13250 /* 34375 */ // GIR_Coverage, 388,
13251 /* 34375 */ GIR_EraseRootFromParent_Done,
13252 /* 34376 */ // Label 1040: @34376
13253 /* 34376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(34427), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 395 //
13254 /* 34383 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
13255 /* 34388 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13256 /* 34391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13257 /* 34394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13258 /* 34397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13259 /* 34401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13260 /* 34405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13261 /* 34409 */ // (intrinsic_w_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13262 /* 34409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
13263 /* 34412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13264 /* 34414 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13265 /* 34416 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13266 /* 34418 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13267 /* 34421 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13268 /* 34425 */ GIR_RootConstrainSelectedInstOperands,
13269 /* 34426 */ // GIR_Coverage, 395,
13270 /* 34426 */ GIR_EraseRootFromParent_Done,
13271 /* 34427 */ // Label 1041: @34427
13272 /* 34427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(34478), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 396 //
13273 /* 34434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13274 /* 34439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13275 /* 34442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13276 /* 34445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13277 /* 34448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13278 /* 34452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13279 /* 34456 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13280 /* 34460 */ // (intrinsic_w_chain:{ *:[v4i8] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13281 /* 34460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
13282 /* 34463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13283 /* 34465 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13284 /* 34467 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13285 /* 34469 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13286 /* 34472 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13287 /* 34476 */ GIR_RootConstrainSelectedInstOperands,
13288 /* 34477 */ // GIR_Coverage, 396,
13289 /* 34477 */ GIR_EraseRootFromParent_Done,
13290 /* 34478 */ // Label 1042: @34478
13291 /* 34478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(34529), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 407 //
13292 /* 34485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13293 /* 34490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13294 /* 34493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13295 /* 34496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13296 /* 34499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13297 /* 34503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13298 /* 34507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13299 /* 34511 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13300 /* 34511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
13301 /* 34514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13302 /* 34516 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13303 /* 34518 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13304 /* 34520 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13305 /* 34523 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13306 /* 34527 */ GIR_RootConstrainSelectedInstOperands,
13307 /* 34528 */ // GIR_Coverage, 407,
13308 /* 34528 */ GIR_EraseRootFromParent_Done,
13309 /* 34529 */ // Label 1043: @34529
13310 /* 34529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1044*/ GIMT_Encode4(34580), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 409 //
13311 /* 34536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13312 /* 34541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13313 /* 34544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13314 /* 34547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13315 /* 34550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13316 /* 34554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13317 /* 34558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13318 /* 34562 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13319 /* 34562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
13320 /* 34565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13321 /* 34567 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13322 /* 34569 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13323 /* 34571 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13324 /* 34574 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13325 /* 34578 */ GIR_RootConstrainSelectedInstOperands,
13326 /* 34579 */ // GIR_Coverage, 409,
13327 /* 34579 */ GIR_EraseRootFromParent_Done,
13328 /* 34580 */ // Label 1044: @34580
13329 /* 34580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1045*/ GIMT_Encode4(34631), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 411 //
13330 /* 34587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13331 /* 34592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13332 /* 34595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13333 /* 34598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13334 /* 34601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13335 /* 34605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13336 /* 34609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13337 /* 34613 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13338 /* 34613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
13339 /* 34616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13340 /* 34618 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13341 /* 34620 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13342 /* 34622 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13343 /* 34625 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13344 /* 34629 */ GIR_RootConstrainSelectedInstOperands,
13345 /* 34630 */ // GIR_Coverage, 411,
13346 /* 34630 */ GIR_EraseRootFromParent_Done,
13347 /* 34631 */ // Label 1045: @34631
13348 /* 34631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(34682), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 416 //
13349 /* 34638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13350 /* 34643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13351 /* 34646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13352 /* 34649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13353 /* 34652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13354 /* 34656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13355 /* 34660 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13356 /* 34664 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
13357 /* 34664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
13358 /* 34667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13359 /* 34669 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13360 /* 34671 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
13361 /* 34673 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13362 /* 34676 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13363 /* 34680 */ GIR_RootConstrainSelectedInstOperands,
13364 /* 34681 */ // GIR_Coverage, 416,
13365 /* 34681 */ GIR_EraseRootFromParent_Done,
13366 /* 34682 */ // Label 1046: @34682
13367 /* 34682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1047*/ GIMT_Encode4(34733), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 419 //
13368 /* 34689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13369 /* 34694 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13370 /* 34697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13371 /* 34700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13372 /* 34703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13373 /* 34707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13374 /* 34711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13375 /* 34715 */ // (intrinsic_w_chain:{ *:[v2i16] } 8438:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13376 /* 34715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
13377 /* 34718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13378 /* 34720 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13379 /* 34722 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13380 /* 34724 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13381 /* 34727 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13382 /* 34731 */ GIR_RootConstrainSelectedInstOperands,
13383 /* 34732 */ // GIR_Coverage, 419,
13384 /* 34732 */ GIR_EraseRootFromParent_Done,
13385 /* 34733 */ // Label 1047: @34733
13386 /* 34733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1048*/ GIMT_Encode4(34784), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 420 //
13387 /* 34740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13388 /* 34745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13389 /* 34748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13390 /* 34751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13391 /* 34754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13392 /* 34758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13393 /* 34762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13394 /* 34766 */ // (intrinsic_w_chain:{ *:[v2i16] } 8439:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13395 /* 34766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
13396 /* 34769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13397 /* 34771 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13398 /* 34773 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13399 /* 34775 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13400 /* 34778 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13401 /* 34782 */ GIR_RootConstrainSelectedInstOperands,
13402 /* 34783 */ // GIR_Coverage, 420,
13403 /* 34783 */ GIR_EraseRootFromParent_Done,
13404 /* 34784 */ // Label 1048: @34784
13405 /* 34784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(34835), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 421 //
13406 /* 34791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13407 /* 34796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13408 /* 34799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13409 /* 34802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13410 /* 34805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13411 /* 34809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13412 /* 34813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13413 /* 34817 */ // (intrinsic_w_chain:{ *:[i32] } 8436:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13414 /* 34817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
13415 /* 34820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13416 /* 34822 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13417 /* 34824 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13418 /* 34826 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13419 /* 34829 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13420 /* 34833 */ GIR_RootConstrainSelectedInstOperands,
13421 /* 34834 */ // GIR_Coverage, 421,
13422 /* 34834 */ GIR_EraseRootFromParent_Done,
13423 /* 34835 */ // Label 1049: @34835
13424 /* 34835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1050*/ GIMT_Encode4(34886), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 422 //
13425 /* 34842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13426 /* 34847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13427 /* 34850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13428 /* 34853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13429 /* 34856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13430 /* 34860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13431 /* 34864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13432 /* 34868 */ // (intrinsic_w_chain:{ *:[i32] } 8437:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13433 /* 34868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
13434 /* 34871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13435 /* 34873 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13436 /* 34875 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13437 /* 34877 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13438 /* 34880 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13439 /* 34884 */ GIR_RootConstrainSelectedInstOperands,
13440 /* 34885 */ // GIR_Coverage, 422,
13441 /* 34885 */ GIR_EraseRootFromParent_Done,
13442 /* 34886 */ // Label 1050: @34886
13443 /* 34886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1051*/ GIMT_Encode4(34937), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 423 //
13444 /* 34893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13445 /* 34898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13446 /* 34901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13447 /* 34904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13448 /* 34907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13449 /* 34911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13450 /* 34915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13451 /* 34919 */ // (intrinsic_w_chain:{ *:[v2i16] } 8440:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13452 /* 34919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
13453 /* 34922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13454 /* 34924 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13455 /* 34926 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13456 /* 34928 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13457 /* 34931 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13458 /* 34935 */ GIR_RootConstrainSelectedInstOperands,
13459 /* 34936 */ // GIR_Coverage, 423,
13460 /* 34936 */ GIR_EraseRootFromParent_Done,
13461 /* 34937 */ // Label 1051: @34937
13462 /* 34937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1052*/ GIMT_Encode4(34985), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 448 //
13463 /* 34944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
13464 /* 34949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13465 /* 34952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13466 /* 34955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13467 /* 34958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13468 /* 34962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13469 /* 34966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13470 /* 34970 */ // (intrinsic_w_chain:{ *:[i32] } 8136:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13471 /* 34970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
13472 /* 34973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13473 /* 34975 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13474 /* 34977 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13475 /* 34979 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13476 /* 34983 */ GIR_RootConstrainSelectedInstOperands,
13477 /* 34984 */ // GIR_Coverage, 448,
13478 /* 34984 */ GIR_EraseRootFromParent_Done,
13479 /* 34985 */ // Label 1052: @34985
13480 /* 34985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1053*/ GIMT_Encode4(35033), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 449 //
13481 /* 34992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
13482 /* 34997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13483 /* 35000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13484 /* 35003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13485 /* 35006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13486 /* 35010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13487 /* 35014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13488 /* 35018 */ // (intrinsic_w_chain:{ *:[i32] } 8138:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13489 /* 35018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
13490 /* 35021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13491 /* 35023 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13492 /* 35025 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13493 /* 35027 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13494 /* 35031 */ GIR_RootConstrainSelectedInstOperands,
13495 /* 35032 */ // GIR_Coverage, 449,
13496 /* 35032 */ GIR_EraseRootFromParent_Done,
13497 /* 35033 */ // Label 1053: @35033
13498 /* 35033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1054*/ GIMT_Encode4(35081), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 450 //
13499 /* 35040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
13500 /* 35045 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13501 /* 35048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13502 /* 35051 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13503 /* 35054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13504 /* 35058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13505 /* 35062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13506 /* 35066 */ // (intrinsic_w_chain:{ *:[i32] } 8137:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13507 /* 35066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
13508 /* 35069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13509 /* 35071 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13510 /* 35073 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13511 /* 35075 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13512 /* 35079 */ GIR_RootConstrainSelectedInstOperands,
13513 /* 35080 */ // GIR_Coverage, 450,
13514 /* 35080 */ GIR_EraseRootFromParent_Done,
13515 /* 35081 */ // Label 1054: @35081
13516 /* 35081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1055*/ GIMT_Encode4(35129), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 460 //
13517 /* 35088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
13518 /* 35093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13519 /* 35096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13520 /* 35099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13521 /* 35102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13522 /* 35106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13523 /* 35110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13524 /* 35114 */ // (intrinsic_w_chain:{ *:[v4i8] } 8480:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13525 /* 35114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
13526 /* 35117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13527 /* 35119 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13528 /* 35121 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13529 /* 35123 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13530 /* 35127 */ GIR_RootConstrainSelectedInstOperands,
13531 /* 35128 */ // GIR_Coverage, 460,
13532 /* 35128 */ GIR_EraseRootFromParent_Done,
13533 /* 35129 */ // Label 1055: @35129
13534 /* 35129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1056*/ GIMT_Encode4(35177), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 461 //
13535 /* 35136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
13536 /* 35141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13537 /* 35144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13538 /* 35147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13539 /* 35150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13540 /* 35154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13541 /* 35158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13542 /* 35162 */ // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13543 /* 35162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
13544 /* 35165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13545 /* 35167 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13546 /* 35169 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13547 /* 35171 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13548 /* 35175 */ GIR_RootConstrainSelectedInstOperands,
13549 /* 35176 */ // GIR_Coverage, 461,
13550 /* 35176 */ GIR_EraseRootFromParent_Done,
13551 /* 35177 */ // Label 1056: @35177
13552 /* 35177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1057*/ GIMT_Encode4(35225), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 465 //
13553 /* 35184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13554 /* 35189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13555 /* 35192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13556 /* 35195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13557 /* 35198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13558 /* 35202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13559 /* 35206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13560 /* 35210 */ // (intrinsic_w_chain:{ *:[i32] } 8338:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13561 /* 35210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
13562 /* 35213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13563 /* 35215 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
13564 /* 35217 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13565 /* 35219 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13566 /* 35223 */ GIR_RootConstrainSelectedInstOperands,
13567 /* 35224 */ // GIR_Coverage, 465,
13568 /* 35224 */ GIR_EraseRootFromParent_Done,
13569 /* 35225 */ // Label 1057: @35225
13570 /* 35225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1058*/ GIMT_Encode4(35276), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 471 //
13571 /* 35232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
13572 /* 35237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13573 /* 35240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13574 /* 35243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13575 /* 35246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13576 /* 35250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13577 /* 35254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13578 /* 35258 */ // (intrinsic_w_chain:{ *:[v2i16] } 7988:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13579 /* 35258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
13580 /* 35261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13581 /* 35263 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13582 /* 35265 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13583 /* 35267 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13584 /* 35270 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13585 /* 35274 */ GIR_RootConstrainSelectedInstOperands,
13586 /* 35275 */ // GIR_Coverage, 471,
13587 /* 35275 */ GIR_EraseRootFromParent_Done,
13588 /* 35276 */ // Label 1058: @35276
13589 /* 35276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(35327), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 472 //
13590 /* 35283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
13591 /* 35288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13592 /* 35291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13593 /* 35294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13594 /* 35297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13595 /* 35301 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13596 /* 35305 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13597 /* 35309 */ // (intrinsic_w_chain:{ *:[v2i16] } 7990:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13598 /* 35309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
13599 /* 35312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13600 /* 35314 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13601 /* 35316 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13602 /* 35318 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13603 /* 35321 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13604 /* 35325 */ GIR_RootConstrainSelectedInstOperands,
13605 /* 35326 */ // GIR_Coverage, 472,
13606 /* 35326 */ GIR_EraseRootFromParent_Done,
13607 /* 35327 */ // Label 1059: @35327
13608 /* 35327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(35378), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 473 //
13609 /* 35334 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
13610 /* 35339 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13611 /* 35342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13612 /* 35345 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13613 /* 35348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13614 /* 35352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13615 /* 35356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13616 /* 35360 */ // (intrinsic_w_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13617 /* 35360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
13618 /* 35363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13619 /* 35365 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13620 /* 35367 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13621 /* 35369 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13622 /* 35372 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13623 /* 35376 */ GIR_RootConstrainSelectedInstOperands,
13624 /* 35377 */ // GIR_Coverage, 473,
13625 /* 35377 */ GIR_EraseRootFromParent_Done,
13626 /* 35378 */ // Label 1060: @35378
13627 /* 35378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(35429), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 474 //
13628 /* 35385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
13629 /* 35390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13630 /* 35393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13631 /* 35396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13632 /* 35399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13633 /* 35403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13634 /* 35407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13635 /* 35411 */ // (intrinsic_w_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13636 /* 35411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
13637 /* 35414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13638 /* 35416 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13639 /* 35418 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13640 /* 35420 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13641 /* 35423 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13642 /* 35427 */ GIR_RootConstrainSelectedInstOperands,
13643 /* 35428 */ // GIR_Coverage, 474,
13644 /* 35428 */ GIR_EraseRootFromParent_Done,
13645 /* 35429 */ // Label 1061: @35429
13646 /* 35429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1062*/ GIMT_Encode4(35480), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 475 //
13647 /* 35436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13648 /* 35441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13649 /* 35444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13650 /* 35447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13651 /* 35450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13652 /* 35454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13653 /* 35458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13654 /* 35462 */ // (intrinsic_w_chain:{ *:[i32] } 8133:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13655 /* 35462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
13656 /* 35465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13657 /* 35467 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13658 /* 35469 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13659 /* 35471 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13660 /* 35474 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13661 /* 35478 */ GIR_RootConstrainSelectedInstOperands,
13662 /* 35479 */ // GIR_Coverage, 475,
13663 /* 35479 */ GIR_EraseRootFromParent_Done,
13664 /* 35480 */ // Label 1062: @35480
13665 /* 35480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1063*/ GIMT_Encode4(35531), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 476 //
13666 /* 35487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13667 /* 35492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13668 /* 35495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13669 /* 35498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13670 /* 35501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13671 /* 35505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13672 /* 35509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13673 /* 35513 */ // (intrinsic_w_chain:{ *:[i32] } 8135:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13674 /* 35513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
13675 /* 35516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13676 /* 35518 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13677 /* 35520 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13678 /* 35522 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13679 /* 35525 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13680 /* 35529 */ GIR_RootConstrainSelectedInstOperands,
13681 /* 35530 */ // GIR_Coverage, 476,
13682 /* 35530 */ GIR_EraseRootFromParent_Done,
13683 /* 35531 */ // Label 1063: @35531
13684 /* 35531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(35582), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 477 //
13685 /* 35538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13686 /* 35543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13687 /* 35546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13688 /* 35549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13689 /* 35552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13690 /* 35556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13691 /* 35560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13692 /* 35564 */ // (intrinsic_w_chain:{ *:[i32] } 8134:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13693 /* 35564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
13694 /* 35567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13695 /* 35569 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13696 /* 35571 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13697 /* 35573 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13698 /* 35576 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13699 /* 35580 */ GIR_RootConstrainSelectedInstOperands,
13700 /* 35581 */ // GIR_Coverage, 477,
13701 /* 35581 */ GIR_EraseRootFromParent_Done,
13702 /* 35582 */ // Label 1064: @35582
13703 /* 35582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(35633), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 491 //
13704 /* 35589 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13705 /* 35594 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13706 /* 35597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13707 /* 35600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13708 /* 35603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13709 /* 35607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13710 /* 35611 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13711 /* 35615 */ // (intrinsic_w_chain:{ *:[v2i16] } 8435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13712 /* 35615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
13713 /* 35618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13714 /* 35620 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13715 /* 35622 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13716 /* 35624 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13717 /* 35627 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13718 /* 35631 */ GIR_RootConstrainSelectedInstOperands,
13719 /* 35632 */ // GIR_Coverage, 491,
13720 /* 35632 */ GIR_EraseRootFromParent_Done,
13721 /* 35633 */ // Label 1065: @35633
13722 /* 35633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1066*/ GIMT_Encode4(35684), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 492 //
13723 /* 35640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13724 /* 35645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13725 /* 35648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13726 /* 35651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13727 /* 35654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13728 /* 35658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13729 /* 35662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13730 /* 35666 */ // (intrinsic_w_chain:{ *:[i32] } 8443:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13731 /* 35666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
13732 /* 35669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13733 /* 35671 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13734 /* 35673 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13735 /* 35675 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13736 /* 35678 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13737 /* 35682 */ GIR_RootConstrainSelectedInstOperands,
13738 /* 35683 */ // GIR_Coverage, 492,
13739 /* 35683 */ GIR_EraseRootFromParent_Done,
13740 /* 35684 */ // Label 1066: @35684
13741 /* 35684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1067*/ GIMT_Encode4(35735), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 493 //
13742 /* 35691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13743 /* 35696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13744 /* 35699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13745 /* 35702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13746 /* 35705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13747 /* 35709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13748 /* 35713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13749 /* 35717 */ // (intrinsic_w_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13750 /* 35717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
13751 /* 35720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13752 /* 35722 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13753 /* 35724 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13754 /* 35726 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13755 /* 35729 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13756 /* 35733 */ GIR_RootConstrainSelectedInstOperands,
13757 /* 35734 */ // GIR_Coverage, 493,
13758 /* 35734 */ GIR_EraseRootFromParent_Done,
13759 /* 35735 */ // Label 1067: @35735
13760 /* 35735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(35786), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 494 //
13761 /* 35742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13762 /* 35747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13763 /* 35750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13764 /* 35753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13765 /* 35756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13766 /* 35760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13767 /* 35764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13768 /* 35768 */ // (intrinsic_w_chain:{ *:[v2i16] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13769 /* 35768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
13770 /* 35771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13771 /* 35773 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13772 /* 35775 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13773 /* 35777 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13774 /* 35780 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13775 /* 35784 */ GIR_RootConstrainSelectedInstOperands,
13776 /* 35785 */ // GIR_Coverage, 494,
13777 /* 35785 */ GIR_EraseRootFromParent_Done,
13778 /* 35786 */ // Label 1068: @35786
13779 /* 35786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1069*/ GIMT_Encode4(35834), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 504 //
13780 /* 35793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13781 /* 35798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13782 /* 35801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13783 /* 35804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13784 /* 35807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13785 /* 35811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13786 /* 35815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13787 /* 35819 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13788 /* 35819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
13789 /* 35822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13790 /* 35824 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13791 /* 35826 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13792 /* 35828 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13793 /* 35832 */ GIR_RootConstrainSelectedInstOperands,
13794 /* 35833 */ // GIR_Coverage, 504,
13795 /* 35833 */ GIR_EraseRootFromParent_Done,
13796 /* 35834 */ // Label 1069: @35834
13797 /* 35834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1070*/ GIMT_Encode4(35885), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1246 //
13798 /* 35841 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13799 /* 35846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13800 /* 35849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13801 /* 35852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13802 /* 35855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13803 /* 35859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13804 /* 35863 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13805 /* 35867 */ // (intrinsic_w_chain:{ *:[i32] } 7970:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13806 /* 35867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
13807 /* 35870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13808 /* 35872 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13809 /* 35874 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13810 /* 35876 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13811 /* 35879 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13812 /* 35883 */ GIR_RootConstrainSelectedInstOperands,
13813 /* 35884 */ // GIR_Coverage, 1246,
13814 /* 35884 */ GIR_EraseRootFromParent_Done,
13815 /* 35885 */ // Label 1070: @35885
13816 /* 35885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1071*/ GIMT_Encode4(35933), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1254 //
13817 /* 35892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13818 /* 35897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13819 /* 35900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13820 /* 35903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13821 /* 35906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13822 /* 35910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13823 /* 35914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13824 /* 35918 */ // (intrinsic_w_chain:{ *:[i32] } 8338:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13825 /* 35918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
13826 /* 35921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13827 /* 35923 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
13828 /* 35925 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13829 /* 35927 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13830 /* 35931 */ GIR_RootConstrainSelectedInstOperands,
13831 /* 35932 */ // GIR_Coverage, 1254,
13832 /* 35932 */ GIR_EraseRootFromParent_Done,
13833 /* 35933 */ // Label 1071: @35933
13834 /* 35933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1072*/ GIMT_Encode4(35984), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1262 //
13835 /* 35940 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13836 /* 35945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13837 /* 35948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13838 /* 35951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13839 /* 35954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13840 /* 35958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13841 /* 35962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13842 /* 35966 */ // (intrinsic_w_chain:{ *:[v2i16] } 8515:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13843 /* 35966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
13844 /* 35969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13845 /* 35971 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13846 /* 35973 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13847 /* 35975 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13848 /* 35978 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13849 /* 35982 */ GIR_RootConstrainSelectedInstOperands,
13850 /* 35983 */ // GIR_Coverage, 1262,
13851 /* 35983 */ GIR_EraseRootFromParent_Done,
13852 /* 35984 */ // Label 1072: @35984
13853 /* 35984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1073*/ GIMT_Encode4(36035), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1263 //
13854 /* 35991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13855 /* 35996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13856 /* 35999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13857 /* 36002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13858 /* 36005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13859 /* 36009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13860 /* 36013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13861 /* 36017 */ // (intrinsic_w_chain:{ *:[v2i16] } 8517:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13862 /* 36017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
13863 /* 36020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13864 /* 36022 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13865 /* 36024 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13866 /* 36026 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13867 /* 36029 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13868 /* 36033 */ GIR_RootConstrainSelectedInstOperands,
13869 /* 36034 */ // GIR_Coverage, 1263,
13870 /* 36034 */ GIR_EraseRootFromParent_Done,
13871 /* 36035 */ // Label 1073: @36035
13872 /* 36035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1074*/ GIMT_Encode4(36086), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1264 //
13873 /* 36042 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13874 /* 36047 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13875 /* 36050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13876 /* 36053 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13877 /* 36056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13878 /* 36060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13879 /* 36064 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13880 /* 36068 */ // (intrinsic_w_chain:{ *:[v4i8] } 8516:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13881 /* 36068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
13882 /* 36071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13883 /* 36073 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13884 /* 36075 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13885 /* 36077 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13886 /* 36080 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13887 /* 36084 */ GIR_RootConstrainSelectedInstOperands,
13888 /* 36085 */ // GIR_Coverage, 1264,
13889 /* 36085 */ GIR_EraseRootFromParent_Done,
13890 /* 36086 */ // Label 1074: @36086
13891 /* 36086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1075*/ GIMT_Encode4(36137), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1265 //
13892 /* 36093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13893 /* 36098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13894 /* 36101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13895 /* 36104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13896 /* 36107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13897 /* 36111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13898 /* 36115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13899 /* 36119 */ // (intrinsic_w_chain:{ *:[i32] } 8518:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13900 /* 36119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
13901 /* 36122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13902 /* 36124 */ GIR_RootToRootCopy, /*OpIdx*/2, // rt
13903 /* 36126 */ GIR_RootToRootCopy, /*OpIdx*/3, // rs
13904 /* 36128 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13905 /* 36131 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13906 /* 36135 */ GIR_RootConstrainSelectedInstOperands,
13907 /* 36136 */ // GIR_Coverage, 1265,
13908 /* 36136 */ GIR_EraseRootFromParent_Done,
13909 /* 36137 */ // Label 1075: @36137
13910 /* 36137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1076*/ GIMT_Encode4(36188), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1284 //
13911 /* 36144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13912 /* 36149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13913 /* 36152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13914 /* 36155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13915 /* 36158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13916 /* 36162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13917 /* 36166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13918 /* 36170 */ // (intrinsic_w_chain:{ *:[i32] } 8590:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13919 /* 36170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
13920 /* 36173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13921 /* 36175 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13922 /* 36177 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13923 /* 36179 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13924 /* 36182 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13925 /* 36186 */ GIR_RootConstrainSelectedInstOperands,
13926 /* 36187 */ // GIR_Coverage, 1284,
13927 /* 36187 */ GIR_EraseRootFromParent_Done,
13928 /* 36188 */ // Label 1076: @36188
13929 /* 36188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1077*/ GIMT_Encode4(36239), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1290 //
13930 /* 36195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13931 /* 36200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13932 /* 36203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13933 /* 36206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13934 /* 36209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13935 /* 36213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13936 /* 36217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13937 /* 36221 */ // (intrinsic_w_chain:{ *:[i32] } 8436:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13938 /* 36221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
13939 /* 36224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13940 /* 36226 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13941 /* 36228 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13942 /* 36230 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13943 /* 36233 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13944 /* 36237 */ GIR_RootConstrainSelectedInstOperands,
13945 /* 36238 */ // GIR_Coverage, 1290,
13946 /* 36238 */ GIR_EraseRootFromParent_Done,
13947 /* 36239 */ // Label 1077: @36239
13948 /* 36239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(36290), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1291 //
13949 /* 36246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13950 /* 36251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13951 /* 36254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13952 /* 36257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13953 /* 36260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13954 /* 36264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13955 /* 36268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13956 /* 36272 */ // (intrinsic_w_chain:{ *:[i32] } 8437:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13957 /* 36272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
13958 /* 36275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13959 /* 36277 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13960 /* 36279 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13961 /* 36281 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13962 /* 36284 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13963 /* 36288 */ GIR_RootConstrainSelectedInstOperands,
13964 /* 36289 */ // GIR_Coverage, 1291,
13965 /* 36289 */ GIR_EraseRootFromParent_Done,
13966 /* 36290 */ // Label 1078: @36290
13967 /* 36290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(36341), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1292 //
13968 /* 36297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13969 /* 36302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13970 /* 36305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13971 /* 36308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13972 /* 36311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13973 /* 36315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13974 /* 36319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13975 /* 36323 */ // (intrinsic_w_chain:{ *:[v2i16] } 8438:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13976 /* 36323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
13977 /* 36326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13978 /* 36328 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13979 /* 36330 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13980 /* 36332 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13981 /* 36335 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13982 /* 36339 */ GIR_RootConstrainSelectedInstOperands,
13983 /* 36340 */ // GIR_Coverage, 1292,
13984 /* 36340 */ GIR_EraseRootFromParent_Done,
13985 /* 36341 */ // Label 1079: @36341
13986 /* 36341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(36392), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1293 //
13987 /* 36348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13988 /* 36353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13989 /* 36356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13990 /* 36359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13991 /* 36362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13992 /* 36366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13993 /* 36370 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13994 /* 36374 */ // (intrinsic_w_chain:{ *:[v2i16] } 8439:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13995 /* 36374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
13996 /* 36377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13997 /* 36379 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
13998 /* 36381 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
13999 /* 36383 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14000 /* 36386 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14001 /* 36390 */ GIR_RootConstrainSelectedInstOperands,
14002 /* 36391 */ // GIR_Coverage, 1293,
14003 /* 36391 */ GIR_EraseRootFromParent_Done,
14004 /* 36392 */ // Label 1080: @36392
14005 /* 36392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1081*/ GIMT_Encode4(36443), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1294 //
14006 /* 36399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
14007 /* 36404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14008 /* 36407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14009 /* 36410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14010 /* 36413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14011 /* 36417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14012 /* 36421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14013 /* 36425 */ // (intrinsic_w_chain:{ *:[v2i16] } 8440:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14014 /* 36425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
14015 /* 36428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14016 /* 36430 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14017 /* 36432 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14018 /* 36434 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14019 /* 36437 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14020 /* 36441 */ GIR_RootConstrainSelectedInstOperands,
14021 /* 36442 */ // GIR_Coverage, 1294,
14022 /* 36442 */ GIR_EraseRootFromParent_Done,
14023 /* 36443 */ // Label 1081: @36443
14024 /* 36443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1082*/ GIMT_Encode4(36494), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1297 //
14025 /* 36450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
14026 /* 36455 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14027 /* 36458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14028 /* 36461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14029 /* 36464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14030 /* 36468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14031 /* 36472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14032 /* 36476 */ // (intrinsic_w_chain:{ *:[v4i8] } 8497:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14033 /* 36476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
14034 /* 36479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14035 /* 36481 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14036 /* 36483 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14037 /* 36485 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14038 /* 36488 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14039 /* 36492 */ GIR_RootConstrainSelectedInstOperands,
14040 /* 36493 */ // GIR_Coverage, 1297,
14041 /* 36493 */ GIR_EraseRootFromParent_Done,
14042 /* 36494 */ // Label 1082: @36494
14043 /* 36494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(36545), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1298 //
14044 /* 36501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
14045 /* 36506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14046 /* 36509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14047 /* 36512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14048 /* 36515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14049 /* 36519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14050 /* 36523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14051 /* 36527 */ // (intrinsic_w_chain:{ *:[v2i16] } 8496:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14052 /* 36527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
14053 /* 36530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14054 /* 36532 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14055 /* 36534 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14056 /* 36536 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
14057 /* 36539 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14058 /* 36543 */ GIR_RootConstrainSelectedInstOperands,
14059 /* 36544 */ // GIR_Coverage, 1298,
14060 /* 36544 */ GIR_EraseRootFromParent_Done,
14061 /* 36545 */ // Label 1083: @36545
14062 /* 36545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(36593), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1316 //
14063 /* 36552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
14064 /* 36557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14065 /* 36560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14066 /* 36563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14067 /* 36566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14068 /* 36570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14069 /* 36574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14070 /* 36578 */ // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14071 /* 36578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
14072 /* 36581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14073 /* 36583 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14074 /* 36585 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14075 /* 36587 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14076 /* 36591 */ GIR_RootConstrainSelectedInstOperands,
14077 /* 36592 */ // GIR_Coverage, 1316,
14078 /* 36592 */ GIR_EraseRootFromParent_Done,
14079 /* 36593 */ // Label 1084: @36593
14080 /* 36593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1085*/ GIMT_Encode4(36641), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1317 //
14081 /* 36600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
14082 /* 36605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14083 /* 36608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14084 /* 36611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14085 /* 36614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14086 /* 36618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14087 /* 36622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14088 /* 36626 */ // (intrinsic_w_chain:{ *:[v4i8] } 8480:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14089 /* 36626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
14090 /* 36629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14091 /* 36631 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14092 /* 36633 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14093 /* 36635 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14094 /* 36639 */ GIR_RootConstrainSelectedInstOperands,
14095 /* 36640 */ // GIR_Coverage, 1317,
14096 /* 36640 */ GIR_EraseRootFromParent_Done,
14097 /* 36641 */ // Label 1085: @36641
14098 /* 36641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1086*/ GIMT_Encode4(36689), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1327 //
14099 /* 36648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
14100 /* 36653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14101 /* 36656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14102 /* 36659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14103 /* 36662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14104 /* 36666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14105 /* 36670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14106 /* 36674 */ // (intrinsic_w_chain:{ *:[i32] } 8136:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14107 /* 36674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
14108 /* 36677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14109 /* 36679 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14110 /* 36681 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14111 /* 36683 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14112 /* 36687 */ GIR_RootConstrainSelectedInstOperands,
14113 /* 36688 */ // GIR_Coverage, 1327,
14114 /* 36688 */ GIR_EraseRootFromParent_Done,
14115 /* 36689 */ // Label 1086: @36689
14116 /* 36689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(36737), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1328 //
14117 /* 36696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
14118 /* 36701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14119 /* 36704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14120 /* 36707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14121 /* 36710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14122 /* 36714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14123 /* 36718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14124 /* 36722 */ // (intrinsic_w_chain:{ *:[i32] } 8138:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14125 /* 36722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
14126 /* 36725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14127 /* 36727 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14128 /* 36729 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14129 /* 36731 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14130 /* 36735 */ GIR_RootConstrainSelectedInstOperands,
14131 /* 36736 */ // GIR_Coverage, 1328,
14132 /* 36736 */ GIR_EraseRootFromParent_Done,
14133 /* 36737 */ // Label 1087: @36737
14134 /* 36737 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1088*/ GIMT_Encode4(36785), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1329 //
14135 /* 36744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
14136 /* 36749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14137 /* 36752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14138 /* 36755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14139 /* 36758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14140 /* 36762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14141 /* 36766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14142 /* 36770 */ // (intrinsic_w_chain:{ *:[i32] } 8137:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14143 /* 36770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
14144 /* 36773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14145 /* 36775 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14146 /* 36777 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14147 /* 36779 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14148 /* 36783 */ GIR_RootConstrainSelectedInstOperands,
14149 /* 36784 */ // GIR_Coverage, 1329,
14150 /* 36784 */ GIR_EraseRootFromParent_Done,
14151 /* 36785 */ // Label 1088: @36785
14152 /* 36785 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1089*/ GIMT_Encode4(36836), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1338 //
14153 /* 36792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
14154 /* 36797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14155 /* 36800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14156 /* 36803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14157 /* 36806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14158 /* 36810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14159 /* 36814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14160 /* 36818 */ // (intrinsic_w_chain:{ *:[v2i16] } 7988:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14161 /* 36818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
14162 /* 36821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14163 /* 36823 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14164 /* 36825 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14165 /* 36827 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14166 /* 36830 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14167 /* 36834 */ GIR_RootConstrainSelectedInstOperands,
14168 /* 36835 */ // GIR_Coverage, 1338,
14169 /* 36835 */ GIR_EraseRootFromParent_Done,
14170 /* 36836 */ // Label 1089: @36836
14171 /* 36836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1090*/ GIMT_Encode4(36887), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1339 //
14172 /* 36843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
14173 /* 36848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14174 /* 36851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14175 /* 36854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14176 /* 36857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14177 /* 36861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14178 /* 36865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14179 /* 36869 */ // (intrinsic_w_chain:{ *:[v2i16] } 7990:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14180 /* 36869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
14181 /* 36872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14182 /* 36874 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14183 /* 36876 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14184 /* 36878 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14185 /* 36881 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14186 /* 36885 */ GIR_RootConstrainSelectedInstOperands,
14187 /* 36886 */ // GIR_Coverage, 1339,
14188 /* 36886 */ GIR_EraseRootFromParent_Done,
14189 /* 36887 */ // Label 1090: @36887
14190 /* 36887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1091*/ GIMT_Encode4(36938), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1350 //
14191 /* 36894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
14192 /* 36899 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14193 /* 36902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14194 /* 36905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14195 /* 36908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14196 /* 36912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14197 /* 36916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14198 /* 36920 */ // (intrinsic_w_chain:{ *:[i32] } 8133:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14199 /* 36920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
14200 /* 36923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14201 /* 36925 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14202 /* 36927 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14203 /* 36929 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14204 /* 36932 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14205 /* 36936 */ GIR_RootConstrainSelectedInstOperands,
14206 /* 36937 */ // GIR_Coverage, 1350,
14207 /* 36937 */ GIR_EraseRootFromParent_Done,
14208 /* 36938 */ // Label 1091: @36938
14209 /* 36938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1092*/ GIMT_Encode4(36989), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1351 //
14210 /* 36945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
14211 /* 36950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14212 /* 36953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14213 /* 36956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14214 /* 36959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14215 /* 36963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14216 /* 36967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14217 /* 36971 */ // (intrinsic_w_chain:{ *:[i32] } 8135:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14218 /* 36971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
14219 /* 36974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14220 /* 36976 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14221 /* 36978 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14222 /* 36980 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14223 /* 36983 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14224 /* 36987 */ GIR_RootConstrainSelectedInstOperands,
14225 /* 36988 */ // GIR_Coverage, 1351,
14226 /* 36988 */ GIR_EraseRootFromParent_Done,
14227 /* 36989 */ // Label 1092: @36989
14228 /* 36989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1093*/ GIMT_Encode4(37040), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1352 //
14229 /* 36996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
14230 /* 37001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14231 /* 37004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
14232 /* 37007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
14233 /* 37010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14234 /* 37014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14235 /* 37018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14236 /* 37022 */ // (intrinsic_w_chain:{ *:[i32] } 8134:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
14237 /* 37022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
14238 /* 37025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14239 /* 37027 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14240 /* 37029 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14241 /* 37031 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
14242 /* 37034 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14243 /* 37038 */ GIR_RootConstrainSelectedInstOperands,
14244 /* 37039 */ // GIR_Coverage, 1352,
14245 /* 37039 */ GIR_EraseRootFromParent_Done,
14246 /* 37040 */ // Label 1093: @37040
14247 /* 37040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1094*/ GIMT_Encode4(37091), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1358 //
14248 /* 37047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
14249 /* 37052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14250 /* 37055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14251 /* 37058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14252 /* 37061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14253 /* 37065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14254 /* 37069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14255 /* 37073 */ // (intrinsic_w_chain:{ *:[v2i16] } 8611:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14256 /* 37073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
14257 /* 37076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14258 /* 37078 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14259 /* 37080 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14260 /* 37082 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14261 /* 37085 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14262 /* 37089 */ GIR_RootConstrainSelectedInstOperands,
14263 /* 37090 */ // GIR_Coverage, 1358,
14264 /* 37090 */ GIR_EraseRootFromParent_Done,
14265 /* 37091 */ // Label 1094: @37091
14266 /* 37091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1095*/ GIMT_Encode4(37142), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1359 //
14267 /* 37098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
14268 /* 37103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14269 /* 37106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14270 /* 37109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14271 /* 37112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14272 /* 37116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14273 /* 37120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14274 /* 37124 */ // (intrinsic_w_chain:{ *:[v2i16] } 8613:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14275 /* 37124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
14276 /* 37127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14277 /* 37129 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14278 /* 37131 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14279 /* 37133 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14280 /* 37136 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14281 /* 37140 */ GIR_RootConstrainSelectedInstOperands,
14282 /* 37141 */ // GIR_Coverage, 1359,
14283 /* 37141 */ GIR_EraseRootFromParent_Done,
14284 /* 37142 */ // Label 1095: @37142
14285 /* 37142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1096*/ GIMT_Encode4(37193), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1366 //
14286 /* 37149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
14287 /* 37154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14288 /* 37157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14289 /* 37160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14290 /* 37163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14291 /* 37167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14292 /* 37171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14293 /* 37175 */ // (intrinsic_w_chain:{ *:[v2i16] } 8435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14294 /* 37175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
14295 /* 37178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14296 /* 37180 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14297 /* 37182 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14298 /* 37184 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14299 /* 37187 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14300 /* 37191 */ GIR_RootConstrainSelectedInstOperands,
14301 /* 37192 */ // GIR_Coverage, 1366,
14302 /* 37192 */ GIR_EraseRootFromParent_Done,
14303 /* 37193 */ // Label 1096: @37193
14304 /* 37193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(37244), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1367 //
14305 /* 37200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
14306 /* 37205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14307 /* 37208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14308 /* 37211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14309 /* 37214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14310 /* 37218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14311 /* 37222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14312 /* 37226 */ // (intrinsic_w_chain:{ *:[i32] } 8441:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14313 /* 37226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
14314 /* 37229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14315 /* 37231 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14316 /* 37233 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14317 /* 37235 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14318 /* 37238 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14319 /* 37242 */ GIR_RootConstrainSelectedInstOperands,
14320 /* 37243 */ // GIR_Coverage, 1367,
14321 /* 37243 */ GIR_EraseRootFromParent_Done,
14322 /* 37244 */ // Label 1097: @37244
14323 /* 37244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(37295), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1368 //
14324 /* 37251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
14325 /* 37256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14326 /* 37259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14327 /* 37262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14328 /* 37265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14329 /* 37269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14330 /* 37273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14331 /* 37277 */ // (intrinsic_w_chain:{ *:[v2i16] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14332 /* 37277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
14333 /* 37280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14334 /* 37282 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14335 /* 37284 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14336 /* 37286 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14337 /* 37289 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14338 /* 37293 */ GIR_RootConstrainSelectedInstOperands,
14339 /* 37294 */ // GIR_Coverage, 1368,
14340 /* 37294 */ GIR_EraseRootFromParent_Done,
14341 /* 37295 */ // Label 1098: @37295
14342 /* 37295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(37346), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1369 //
14343 /* 37302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
14344 /* 37307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14345 /* 37310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14346 /* 37313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14347 /* 37316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14348 /* 37320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14349 /* 37324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14350 /* 37328 */ // (intrinsic_w_chain:{ *:[i32] } 8443:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
14351 /* 37328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
14352 /* 37331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14353 /* 37333 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14354 /* 37335 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14355 /* 37337 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14356 /* 37340 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14357 /* 37344 */ GIR_RootConstrainSelectedInstOperands,
14358 /* 37345 */ // GIR_Coverage, 1369,
14359 /* 37345 */ GIR_EraseRootFromParent_Done,
14360 /* 37346 */ // Label 1099: @37346
14361 /* 37346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1100*/ GIMT_Encode4(37394), GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips), // Rule ID 1370 //
14362 /* 37353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
14363 /* 37358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
14364 /* 37361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14365 /* 37364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14366 /* 37367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14367 /* 37371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14368 /* 37375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14369 /* 37379 */ // (intrinsic_w_chain:{ *:[v4i8] } 8491:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
14370 /* 37379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
14371 /* 37382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14372 /* 37384 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
14373 /* 37386 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
14374 /* 37388 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14375 /* 37392 */ GIR_RootConstrainSelectedInstOperands,
14376 /* 37393 */ // GIR_Coverage, 1370,
14377 /* 37393 */ GIR_EraseRootFromParent_Done,
14378 /* 37394 */ // Label 1100: @37394
14379 /* 37394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1101*/ GIMT_Encode4(37437), GIMT_Encode2(GIFBS_HasDSPR2), // Rule ID 2059 //
14380 /* 37401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
14381 /* 37406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
14382 /* 37409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
14383 /* 37412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
14384 /* 37415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
14385 /* 37419 */ // (intrinsic_w_chain:{ *:[v2i16] } 8432:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
14386 /* 37419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
14387 /* 37422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14388 /* 37424 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14389 /* 37426 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14390 /* 37428 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
14391 /* 37431 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14392 /* 37435 */ GIR_RootConstrainSelectedInstOperands,
14393 /* 37436 */ // GIR_Coverage, 2059,
14394 /* 37436 */ GIR_EraseRootFromParent_Done,
14395 /* 37437 */ // Label 1101: @37437
14396 /* 37437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(37480), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2065 //
14397 /* 37444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
14398 /* 37449 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14399 /* 37452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14400 /* 37455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14401 /* 37458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14402 /* 37462 */ // (intrinsic_w_chain:{ *:[i32] } 7987:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14403 /* 37462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
14404 /* 37465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14405 /* 37467 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14406 /* 37469 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14407 /* 37471 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
14408 /* 37474 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14409 /* 37478 */ GIR_RootConstrainSelectedInstOperands,
14410 /* 37479 */ // GIR_Coverage, 2065,
14411 /* 37479 */ GIR_EraseRootFromParent_Done,
14412 /* 37480 */ // Label 1102: @37480
14413 /* 37480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(37523), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 2067 //
14414 /* 37487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
14415 /* 37492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14416 /* 37495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14417 /* 37498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14418 /* 37501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14419 /* 37505 */ // (intrinsic_w_chain:{ *:[i32] } 8002:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
14420 /* 37505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
14421 /* 37508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14422 /* 37510 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
14423 /* 37512 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
14424 /* 37514 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
14425 /* 37517 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14426 /* 37521 */ GIR_RootConstrainSelectedInstOperands,
14427 /* 37522 */ // GIR_Coverage, 2067,
14428 /* 37522 */ GIR_EraseRootFromParent_Done,
14429 /* 37523 */ // Label 1103: @37523
14430 /* 37523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1104*/ GIMT_Encode4(37568), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 515 //
14431 /* 37530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
14432 /* 37535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
14433 /* 37538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14434 /* 37541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14435 /* 37545 */ // MIs[0] ptr
14436 /* 37545 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14437 /* 37549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14438 /* 37553 */ // (intrinsic_w_chain:{ *:[v2i64] } 8352:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14439 /* 37553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
14440 /* 37556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14441 /* 37558 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14442 /* 37560 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14443 /* 37562 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14444 /* 37566 */ GIR_RootConstrainSelectedInstOperands,
14445 /* 37567 */ // GIR_Coverage, 515,
14446 /* 37567 */ GIR_EraseRootFromParent_Done,
14447 /* 37568 */ // Label 1104: @37568
14448 /* 37568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1105*/ GIMT_Encode4(37613), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 516 //
14449 /* 37575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
14450 /* 37580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
14451 /* 37583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14452 /* 37586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14453 /* 37590 */ // MIs[0] ptr
14454 /* 37590 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14455 /* 37594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14456 /* 37598 */ // (intrinsic_w_chain:{ *:[v4i32] } 8353:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14457 /* 37598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
14458 /* 37601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14459 /* 37603 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14460 /* 37605 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14461 /* 37607 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14462 /* 37611 */ GIR_RootConstrainSelectedInstOperands,
14463 /* 37612 */ // GIR_Coverage, 516,
14464 /* 37612 */ GIR_EraseRootFromParent_Done,
14465 /* 37613 */ // Label 1105: @37613
14466 /* 37613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(37654), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 462 //
14467 /* 37620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14468 /* 37625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14469 /* 37628 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14470 /* 37631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14471 /* 37635 */ // MIs[0] base
14472 /* 37635 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14473 /* 37639 */ // (intrinsic_w_chain:{ *:[i32] } 8356:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14474 /* 37639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
14475 /* 37642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14476 /* 37644 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14477 /* 37646 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14478 /* 37648 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14479 /* 37652 */ GIR_RootConstrainSelectedInstOperands,
14480 /* 37653 */ // GIR_Coverage, 462,
14481 /* 37653 */ GIR_EraseRootFromParent_Done,
14482 /* 37654 */ // Label 1106: @37654
14483 /* 37654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1107*/ GIMT_Encode4(37695), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 463 //
14484 /* 37661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14485 /* 37666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14486 /* 37669 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14487 /* 37672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14488 /* 37676 */ // MIs[0] base
14489 /* 37676 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14490 /* 37680 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14491 /* 37680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
14492 /* 37683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14493 /* 37685 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14494 /* 37687 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14495 /* 37689 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14496 /* 37693 */ GIR_RootConstrainSelectedInstOperands,
14497 /* 37694 */ // GIR_Coverage, 463,
14498 /* 37694 */ GIR_EraseRootFromParent_Done,
14499 /* 37695 */ // Label 1107: @37695
14500 /* 37695 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(37764),
14501 /* 37700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
14502 /* 37705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14503 /* 37708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14504 /* 37711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14505 /* 37715 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14506 /* 37719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(37741), GIMT_Encode2(GIFBS_HasDSP), // Rule ID 464 //
14507 /* 37726 */ // (intrinsic_w_chain:{ *:[i32] } 8343:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14508 /* 37726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
14509 /* 37729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14510 /* 37731 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14511 /* 37733 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14512 /* 37735 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14513 /* 37739 */ GIR_RootConstrainSelectedInstOperands,
14514 /* 37740 */ // GIR_Coverage, 464,
14515 /* 37740 */ GIR_EraseRootFromParent_Done,
14516 /* 37741 */ // Label 1109: @37741
14517 /* 37741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1110*/ GIMT_Encode4(37763), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1299 //
14518 /* 37748 */ // (intrinsic_w_chain:{ *:[i32] } 8343:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14519 /* 37748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
14520 /* 37751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14521 /* 37753 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14522 /* 37755 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14523 /* 37757 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14524 /* 37761 */ GIR_RootConstrainSelectedInstOperands,
14525 /* 37762 */ // GIR_Coverage, 1299,
14526 /* 37762 */ GIR_EraseRootFromParent_Done,
14527 /* 37763 */ // Label 1110: @37763
14528 /* 37763 */ GIM_Reject,
14529 /* 37764 */ // Label 1108: @37764
14530 /* 37764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1111*/ GIMT_Encode4(37805), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1300 //
14531 /* 37771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
14532 /* 37776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14533 /* 37779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14534 /* 37782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14535 /* 37786 */ // MIs[0] base
14536 /* 37786 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14537 /* 37790 */ // (intrinsic_w_chain:{ *:[i32] } 8354:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14538 /* 37790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
14539 /* 37793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14540 /* 37795 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14541 /* 37797 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14542 /* 37799 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14543 /* 37803 */ GIR_RootConstrainSelectedInstOperands,
14544 /* 37804 */ // GIR_Coverage, 1300,
14545 /* 37804 */ GIR_EraseRootFromParent_Done,
14546 /* 37805 */ // Label 1111: @37805
14547 /* 37805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1112*/ GIMT_Encode4(37846), GIMT_Encode2(GIFBS_HasDSP_InMicroMips), // Rule ID 1301 //
14548 /* 37812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
14549 /* 37817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14550 /* 37820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14551 /* 37823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14552 /* 37827 */ // MIs[0] base
14553 /* 37827 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14554 /* 37831 */ // (intrinsic_w_chain:{ *:[i32] } 8356:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) => (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
14555 /* 37831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
14556 /* 37834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14557 /* 37836 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
14558 /* 37838 */ GIR_RootToRootCopy, /*OpIdx*/3, // index
14559 /* 37840 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14560 /* 37844 */ GIR_RootConstrainSelectedInstOperands,
14561 /* 37845 */ // GIR_Coverage, 1301,
14562 /* 37845 */ GIR_EraseRootFromParent_Done,
14563 /* 37846 */ // Label 1112: @37846
14564 /* 37846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(37891), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 517 //
14565 /* 37853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
14566 /* 37858 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14567 /* 37861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14568 /* 37864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14569 /* 37868 */ // MIs[0] ptr
14570 /* 37868 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14571 /* 37872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14572 /* 37876 */ // (intrinsic_void 8586:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14573 /* 37876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
14574 /* 37879 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14575 /* 37881 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14576 /* 37883 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14577 /* 37885 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14578 /* 37889 */ GIR_RootConstrainSelectedInstOperands,
14579 /* 37890 */ // GIR_Coverage, 517,
14580 /* 37890 */ GIR_EraseRootFromParent_Done,
14581 /* 37891 */ // Label 1113: @37891
14582 /* 37891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(37936), GIMT_Encode2(GIFBS_NotInMips16Mode), // Rule ID 518 //
14583 /* 37898 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
14584 /* 37903 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14585 /* 37906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
14586 /* 37909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14587 /* 37913 */ // MIs[0] ptr
14588 /* 37913 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
14589 /* 37917 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14590 /* 37921 */ // (intrinsic_void 8587:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm) => (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
14591 /* 37921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
14592 /* 37924 */ GIR_RootToRootCopy, /*OpIdx*/1, // dst
14593 /* 37926 */ GIR_RootToRootCopy, /*OpIdx*/2, // ptr
14594 /* 37928 */ GIR_RootToRootCopy, /*OpIdx*/3, // imm
14595 /* 37930 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14596 /* 37934 */ GIR_RootConstrainSelectedInstOperands,
14597 /* 37935 */ // GIR_Coverage, 518,
14598 /* 37935 */ GIR_EraseRootFromParent_Done,
14599 /* 37936 */ // Label 1114: @37936
14600 /* 37936 */ GIM_Reject,
14601 /* 37937 */ // Label 1032: @37937
14602 /* 37937 */ GIM_Reject,
14603 /* 37938 */ // Label 31: @37938
14604 /* 37938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1115*/ GIMT_Encode4(38002), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1688 //
14605 /* 37945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14606 /* 37948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14607 /* 37951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14608 /* 37955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14609 /* 37959 */ // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
14610 /* 37959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14611 /* 37962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14612 /* 37966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14613 /* 37971 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14614 /* 37973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14615 /* 37976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14616 /* 37978 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14617 /* 37981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14618 /* 37983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14619 /* 37986 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14620 /* 37991 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14621 /* 37996 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14622 /* 38001 */ // GIR_Coverage, 1688,
14623 /* 38001 */ GIR_EraseRootFromParent_Done,
14624 /* 38002 */ // Label 1115: @38002
14625 /* 38002 */ GIM_Reject,
14626 /* 38003 */ // Label 32: @38003
14627 /* 38003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1116*/ GIMT_Encode4(38065), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1681 //
14628 /* 38010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14629 /* 38013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14630 /* 38016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14631 /* 38020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14632 /* 38024 */ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
14633 /* 38024 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14634 /* 38027 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14635 /* 38031 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14636 /* 38036 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
14637 /* 38042 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
14638 /* 38047 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14639 /* 38052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
14640 /* 38055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14641 /* 38057 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14642 /* 38060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14643 /* 38063 */ GIR_RootConstrainSelectedInstOperands,
14644 /* 38064 */ // GIR_Coverage, 1681,
14645 /* 38064 */ GIR_EraseRootFromParent_Done,
14646 /* 38065 */ // Label 1116: @38065
14647 /* 38065 */ GIM_Reject,
14648 /* 38066 */ // Label 33: @38066
14649 /* 38066 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(38124),
14650 /* 38071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14651 /* 38074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1118*/ GIMT_Encode4(38099), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2290 //
14652 /* 38081 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
14653 /* 38085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
14654 /* 38089 */ // MIs[0] Operand 1
14655 /* 38089 */ // No operand predicates
14656 /* 38089 */ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
14657 /* 38089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
14658 /* 38092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14659 /* 38094 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14660 /* 38097 */ GIR_RootConstrainSelectedInstOperands,
14661 /* 38098 */ // GIR_Coverage, 2290,
14662 /* 38098 */ GIR_EraseRootFromParent_Done,
14663 /* 38099 */ // Label 1118: @38099
14664 /* 38099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(38123), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1983 //
14665 /* 38106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14666 /* 38110 */ // MIs[0] Operand 1
14667 /* 38110 */ // No operand predicates
14668 /* 38110 */ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
14669 /* 38110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
14670 /* 38113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
14671 /* 38115 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
14672 /* 38118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
14673 /* 38121 */ GIR_RootConstrainSelectedInstOperands,
14674 /* 38122 */ // GIR_Coverage, 1983,
14675 /* 38122 */ GIR_EraseRootFromParent_Done,
14676 /* 38123 */ // Label 1119: @38123
14677 /* 38123 */ GIM_Reject,
14678 /* 38124 */ // Label 1117: @38124
14679 /* 38124 */ GIM_Reject,
14680 /* 38125 */ // Label 34: @38125
14681 /* 38125 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(39581),
14682 /* 38130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14683 /* 38133 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14684 /* 38136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14685 /* 38140 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(38245), // Rule ID 1737 //
14686 /* 38145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14687 /* 38149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14688 /* 38153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14689 /* 38157 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14690 /* 38161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14691 /* 38166 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14692 /* 38170 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14693 /* 38174 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14694 /* 38178 */ // MIs[2] Operand 1
14695 /* 38178 */ // No operand predicates
14696 /* 38178 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14697 /* 38180 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14698 /* 38180 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14699 /* 38183 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
14700 /* 38187 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14701 /* 38192 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14702 /* 38196 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14703 /* 38199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14704 /* 38201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14705 /* 38204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14706 /* 38208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14707 /* 38213 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14708 /* 38215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14709 /* 38218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14710 /* 38220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14711 /* 38223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14712 /* 38226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14713 /* 38229 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14714 /* 38234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14715 /* 38239 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14716 /* 38244 */ // GIR_Coverage, 1737,
14717 /* 38244 */ GIR_EraseRootFromParent_Done,
14718 /* 38245 */ // Label 1121: @38245
14719 /* 38245 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(38350), // Rule ID 1733 //
14720 /* 38250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14721 /* 38254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
14722 /* 38258 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14723 /* 38262 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14724 /* 38266 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14725 /* 38271 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14726 /* 38275 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14727 /* 38279 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14728 /* 38283 */ // MIs[2] Operand 1
14729 /* 38283 */ // No operand predicates
14730 /* 38283 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14731 /* 38285 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14732 /* 38285 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14733 /* 38288 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
14734 /* 38292 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14735 /* 38297 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14736 /* 38301 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14737 /* 38304 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14738 /* 38306 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14739 /* 38309 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14740 /* 38313 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14741 /* 38318 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14742 /* 38320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14743 /* 38323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14744 /* 38325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14745 /* 38328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14746 /* 38331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14747 /* 38334 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14748 /* 38339 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14749 /* 38344 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14750 /* 38349 */ // GIR_Coverage, 1733,
14751 /* 38349 */ GIR_EraseRootFromParent_Done,
14752 /* 38350 */ // Label 1122: @38350
14753 /* 38350 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(38455), // Rule ID 1729 //
14754 /* 38355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14755 /* 38359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
14756 /* 38363 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14757 /* 38367 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14758 /* 38371 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14759 /* 38376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14760 /* 38380 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14761 /* 38384 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14762 /* 38388 */ // MIs[2] Operand 1
14763 /* 38388 */ // No operand predicates
14764 /* 38388 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
14765 /* 38390 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14766 /* 38390 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14767 /* 38393 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
14768 /* 38397 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14769 /* 38402 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14770 /* 38406 */ GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14771 /* 38409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14772 /* 38411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14773 /* 38414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14774 /* 38418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14775 /* 38423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14776 /* 38425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14777 /* 38428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14778 /* 38430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14779 /* 38433 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14780 /* 38436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14781 /* 38439 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14782 /* 38444 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14783 /* 38449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14784 /* 38454 */ // GIR_Coverage, 1729,
14785 /* 38454 */ GIR_EraseRootFromParent_Done,
14786 /* 38455 */ // Label 1123: @38455
14787 /* 38455 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(38554), // Rule ID 1719 //
14788 /* 38460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14789 /* 38464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
14790 /* 38468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14791 /* 38472 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14792 /* 38476 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14793 /* 38481 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14794 /* 38486 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14795 /* 38488 */ // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14796 /* 38488 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14797 /* 38491 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
14798 /* 38495 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14799 /* 38500 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14800 /* 38504 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14801 /* 38508 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14802 /* 38510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14803 /* 38513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14804 /* 38517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14805 /* 38522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14806 /* 38524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14807 /* 38527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14808 /* 38529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14809 /* 38532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14810 /* 38535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14811 /* 38538 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14812 /* 38543 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14813 /* 38548 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14814 /* 38553 */ // GIR_Coverage, 1719,
14815 /* 38553 */ GIR_EraseRootFromParent_Done,
14816 /* 38554 */ // Label 1124: @38554
14817 /* 38554 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(38653), // Rule ID 1739 //
14818 /* 38559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14819 /* 38563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14820 /* 38567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14821 /* 38571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14822 /* 38575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14823 /* 38580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14824 /* 38585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14825 /* 38587 */ // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14826 /* 38587 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14827 /* 38590 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
14828 /* 38594 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14829 /* 38599 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14830 /* 38603 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14831 /* 38607 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14832 /* 38609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14833 /* 38612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14834 /* 38616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14835 /* 38621 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14836 /* 38623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14837 /* 38626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14838 /* 38628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14839 /* 38631 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14840 /* 38634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14841 /* 38637 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14842 /* 38642 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14843 /* 38647 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14844 /* 38652 */ // GIR_Coverage, 1739,
14845 /* 38652 */ GIR_EraseRootFromParent_Done,
14846 /* 38653 */ // Label 1125: @38653
14847 /* 38653 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(38752), // Rule ID 1735 //
14848 /* 38658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14849 /* 38662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
14850 /* 38666 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14851 /* 38670 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14852 /* 38674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14853 /* 38679 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14854 /* 38684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14855 /* 38686 */ // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14856 /* 38686 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14857 /* 38689 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
14858 /* 38693 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14859 /* 38698 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14860 /* 38702 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14861 /* 38706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14862 /* 38708 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14863 /* 38711 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14864 /* 38715 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14865 /* 38720 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14866 /* 38722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14867 /* 38725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14868 /* 38727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14869 /* 38730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14870 /* 38733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14871 /* 38736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14872 /* 38741 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14873 /* 38746 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14874 /* 38751 */ // GIR_Coverage, 1735,
14875 /* 38751 */ GIR_EraseRootFromParent_Done,
14876 /* 38752 */ // Label 1126: @38752
14877 /* 38752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1127*/ GIMT_Encode4(38859), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 1723 //
14878 /* 38759 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14879 /* 38763 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
14880 /* 38767 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14881 /* 38771 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14882 /* 38775 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14883 /* 38780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14884 /* 38785 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14885 /* 38787 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14886 /* 38787 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14887 /* 38790 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
14888 /* 38794 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14889 /* 38799 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14890 /* 38803 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14891 /* 38807 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
14892 /* 38810 */ GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
14893 /* 38813 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14894 /* 38815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14895 /* 38818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14896 /* 38822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14897 /* 38827 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14898 /* 38829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14899 /* 38832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14900 /* 38834 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14901 /* 38837 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14902 /* 38840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14903 /* 38843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14904 /* 38848 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14905 /* 38853 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14906 /* 38858 */ // GIR_Coverage, 1723,
14907 /* 38858 */ GIR_EraseRootFromParent_Done,
14908 /* 38859 */ // Label 1127: @38859
14909 /* 38859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1128*/ GIMT_Encode4(38960), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1934 //
14910 /* 38866 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14911 /* 38870 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
14912 /* 38874 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14913 /* 38878 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14914 /* 38882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14915 /* 38887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14916 /* 38892 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14917 /* 38894 */ // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14918 /* 38894 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14919 /* 38897 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
14920 /* 38901 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14921 /* 38906 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14922 /* 38910 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14923 /* 38914 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14924 /* 38916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14925 /* 38919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14926 /* 38923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14927 /* 38928 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14928 /* 38930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14929 /* 38933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14930 /* 38935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14931 /* 38938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14932 /* 38941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14933 /* 38944 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14934 /* 38949 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14935 /* 38954 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14936 /* 38959 */ // GIR_Coverage, 1934,
14937 /* 38959 */ GIR_EraseRootFromParent_Done,
14938 /* 38960 */ // Label 1128: @38960
14939 /* 38960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1129*/ GIMT_Encode4(39061), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1935 //
14940 /* 38967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14941 /* 38971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
14942 /* 38975 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14943 /* 38979 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14944 /* 38983 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14945 /* 38988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14946 /* 38993 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14947 /* 38995 */ // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14948 /* 38995 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14949 /* 38998 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
14950 /* 39002 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14951 /* 39007 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14952 /* 39011 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14953 /* 39015 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14954 /* 39017 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14955 /* 39020 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14956 /* 39024 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14957 /* 39029 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14958 /* 39031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14959 /* 39034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14960 /* 39036 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14961 /* 39039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14962 /* 39042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14963 /* 39045 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14964 /* 39050 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14965 /* 39055 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14966 /* 39060 */ // GIR_Coverage, 1935,
14967 /* 39060 */ GIR_EraseRootFromParent_Done,
14968 /* 39061 */ // Label 1129: @39061
14969 /* 39061 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(39160), // Rule ID 1731 //
14970 /* 39066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14971 /* 39070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
14972 /* 39074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14973 /* 39078 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14974 /* 39082 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14975 /* 39087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14976 /* 39092 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
14977 /* 39094 */ // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14978 /* 39094 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14979 /* 39097 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
14980 /* 39101 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14981 /* 39106 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14982 /* 39110 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14983 /* 39114 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14984 /* 39116 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14985 /* 39119 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14986 /* 39123 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14987 /* 39128 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14988 /* 39130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14989 /* 39133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14990 /* 39135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14991 /* 39138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14992 /* 39141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14993 /* 39144 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14994 /* 39149 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14995 /* 39154 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14996 /* 39159 */ // GIR_Coverage, 1731,
14997 /* 39159 */ GIR_EraseRootFromParent_Done,
14998 /* 39160 */ // Label 1130: @39160
14999 /* 39160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1131*/ GIMT_Encode4(39261), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1937 //
15000 /* 39167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15001 /* 39171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
15002 /* 39175 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15003 /* 39179 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15004 /* 39183 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15005 /* 39188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15006 /* 39193 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15007 /* 39195 */ // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15008 /* 39195 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15009 /* 39198 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
15010 /* 39202 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15011 /* 39207 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15012 /* 39211 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15013 /* 39215 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15014 /* 39217 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15015 /* 39220 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15016 /* 39224 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15017 /* 39229 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15018 /* 39231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15019 /* 39234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15020 /* 39236 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15021 /* 39239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15022 /* 39242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15023 /* 39245 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15024 /* 39250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15025 /* 39255 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15026 /* 39260 */ // GIR_Coverage, 1937,
15027 /* 39260 */ GIR_EraseRootFromParent_Done,
15028 /* 39261 */ // Label 1131: @39261
15029 /* 39261 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(39360), // Rule ID 1721 //
15030 /* 39266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15031 /* 39270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
15032 /* 39274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15033 /* 39278 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15034 /* 39282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15035 /* 39287 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15036 /* 39292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15037 /* 39294 */ // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15038 /* 39294 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15039 /* 39297 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
15040 /* 39301 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15041 /* 39306 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15042 /* 39310 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15043 /* 39314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15044 /* 39316 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15045 /* 39319 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15046 /* 39323 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15047 /* 39328 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15048 /* 39330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15049 /* 39333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15050 /* 39335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15051 /* 39338 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15052 /* 39341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15053 /* 39344 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15054 /* 39349 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15055 /* 39354 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15056 /* 39359 */ // GIR_Coverage, 1721,
15057 /* 39359 */ GIR_EraseRootFromParent_Done,
15058 /* 39360 */ // Label 1132: @39360
15059 /* 39360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1133*/ GIMT_Encode4(39461), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1936 //
15060 /* 39367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15061 /* 39371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
15062 /* 39375 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15063 /* 39379 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15064 /* 39383 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15065 /* 39388 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15066 /* 39393 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15067 /* 39395 */ // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15068 /* 39395 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15069 /* 39398 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
15070 /* 39402 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15071 /* 39407 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15072 /* 39411 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15073 /* 39415 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15074 /* 39417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15075 /* 39420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15076 /* 39424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15077 /* 39429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15078 /* 39431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15079 /* 39434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15080 /* 39436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15081 /* 39439 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15082 /* 39442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15083 /* 39445 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15084 /* 39450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15085 /* 39455 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15086 /* 39460 */ // GIR_Coverage, 1936,
15087 /* 39460 */ GIR_EraseRootFromParent_Done,
15088 /* 39461 */ // Label 1133: @39461
15089 /* 39461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1134*/ GIMT_Encode4(39562), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1938 //
15090 /* 39468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15091 /* 39472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
15092 /* 39476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
15093 /* 39480 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
15094 /* 39484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15095 /* 39489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15096 /* 39494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15097 /* 39496 */ // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
15098 /* 39496 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
15099 /* 39499 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
15100 /* 39503 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15101 /* 39508 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
15102 /* 39512 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
15103 /* 39516 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
15104 /* 39518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15105 /* 39521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15106 /* 39525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15107 /* 39530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15108 /* 39532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
15109 /* 39535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
15110 /* 39537 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15111 /* 39540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
15112 /* 39543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
15113 /* 39546 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
15114 /* 39551 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15115 /* 39556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
15116 /* 39561 */ // GIR_Coverage, 1938,
15117 /* 39561 */ GIR_EraseRootFromParent_Done,
15118 /* 39562 */ // Label 1134: @39562
15119 /* 39562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1135*/ GIMT_Encode4(39580), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1691 //
15120 /* 39569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15121 /* 39573 */ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
15122 /* 39573 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
15123 /* 39578 */ GIR_RootConstrainSelectedInstOperands,
15124 /* 39579 */ // GIR_Coverage, 1691,
15125 /* 39579 */ GIR_Done,
15126 /* 39580 */ // Label 1135: @39580
15127 /* 39580 */ GIM_Reject,
15128 /* 39581 */ // Label 1120: @39581
15129 /* 39581 */ GIM_Reject,
15130 /* 39582 */ // Label 35: @39582
15131 /* 39582 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1138*/ GIMT_Encode4(39900),
15132 /* 39593 */ /*GILLT_s32*//*Label 1136*/ GIMT_Encode4(39601),
15133 /* 39597 */ /*GILLT_s64*//*Label 1137*/ GIMT_Encode4(39801),
15134 /* 39601 */ // Label 1136: @39601
15135 /* 39601 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(39800),
15136 /* 39606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15137 /* 39609 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(39731),
15138 /* 39614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15139 /* 39618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15140 /* 39622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1141*/ GIMT_Encode4(39649), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 106 //
15141 /* 39629 */ // MIs[0] Operand 2
15142 /* 39629 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15143 /* 39640 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15144 /* 39640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
15145 /* 39643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15146 /* 39645 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15147 /* 39647 */ GIR_RootConstrainSelectedInstOperands,
15148 /* 39648 */ // GIR_Coverage, 106,
15149 /* 39648 */ GIR_EraseRootFromParent_Done,
15150 /* 39649 */ // Label 1141: @39649
15151 /* 39649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1142*/ GIMT_Encode4(39676), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 107 //
15152 /* 39656 */ // MIs[0] Operand 2
15153 /* 39656 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15154 /* 39667 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15155 /* 39667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
15156 /* 39670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15157 /* 39672 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15158 /* 39674 */ GIR_RootConstrainSelectedInstOperands,
15159 /* 39675 */ // GIR_Coverage, 107,
15160 /* 39675 */ GIR_EraseRootFromParent_Done,
15161 /* 39676 */ // Label 1142: @39676
15162 /* 39676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1143*/ GIMT_Encode4(39703), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1123 //
15163 /* 39683 */ // MIs[0] Operand 2
15164 /* 39683 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15165 /* 39694 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) => (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15166 /* 39694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
15167 /* 39697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15168 /* 39699 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15169 /* 39701 */ GIR_RootConstrainSelectedInstOperands,
15170 /* 39702 */ // GIR_Coverage, 1123,
15171 /* 39702 */ GIR_EraseRootFromParent_Done,
15172 /* 39703 */ // Label 1143: @39703
15173 /* 39703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1144*/ GIMT_Encode4(39730), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1124 //
15174 /* 39710 */ // MIs[0] Operand 2
15175 /* 39710 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15176 /* 39721 */ // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) => (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
15177 /* 39721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
15178 /* 39724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15179 /* 39726 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15180 /* 39728 */ GIR_RootConstrainSelectedInstOperands,
15181 /* 39729 */ // GIR_Coverage, 1124,
15182 /* 39729 */ GIR_EraseRootFromParent_Done,
15183 /* 39730 */ // Label 1144: @39730
15184 /* 39730 */ GIM_Reject,
15185 /* 39731 */ // Label 1140: @39731
15186 /* 39731 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(39799),
15187 /* 39736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15188 /* 39740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15189 /* 39744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1146*/ GIMT_Encode4(39771), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2041 //
15190 /* 39751 */ // MIs[0] Operand 2
15191 /* 39751 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15192 /* 39762 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) => (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15193 /* 39762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
15194 /* 39765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15195 /* 39767 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15196 /* 39769 */ GIR_RootConstrainSelectedInstOperands,
15197 /* 39770 */ // GIR_Coverage, 2041,
15198 /* 39770 */ GIR_EraseRootFromParent_Done,
15199 /* 39771 */ // Label 1146: @39771
15200 /* 39771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1147*/ GIMT_Encode4(39798), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2042 //
15201 /* 39778 */ // MIs[0] Operand 2
15202 /* 39778 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15203 /* 39789 */ // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) => (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
15204 /* 39789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
15205 /* 39792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15206 /* 39794 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15207 /* 39796 */ GIR_RootConstrainSelectedInstOperands,
15208 /* 39797 */ // GIR_Coverage, 2042,
15209 /* 39797 */ GIR_EraseRootFromParent_Done,
15210 /* 39798 */ // Label 1147: @39798
15211 /* 39798 */ GIM_Reject,
15212 /* 39799 */ // Label 1145: @39799
15213 /* 39799 */ GIM_Reject,
15214 /* 39800 */ // Label 1139: @39800
15215 /* 39800 */ GIM_Reject,
15216 /* 39801 */ // Label 1137: @39801
15217 /* 39801 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(39899),
15218 /* 39806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15219 /* 39809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15220 /* 39813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15221 /* 39817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1149*/ GIMT_Encode4(39844), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 289 //
15222 /* 39824 */ // MIs[0] Operand 2
15223 /* 39824 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
15224 /* 39835 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) => (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15225 /* 39835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
15226 /* 39838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15227 /* 39840 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15228 /* 39842 */ GIR_RootConstrainSelectedInstOperands,
15229 /* 39843 */ // GIR_Coverage, 289,
15230 /* 39843 */ GIR_EraseRootFromParent_Done,
15231 /* 39844 */ // Label 1149: @39844
15232 /* 39844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1150*/ GIMT_Encode4(39871), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit), // Rule ID 290 //
15233 /* 39851 */ // MIs[0] Operand 2
15234 /* 39851 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
15235 /* 39862 */ // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) => (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
15236 /* 39862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
15237 /* 39865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15238 /* 39867 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15239 /* 39869 */ GIR_RootConstrainSelectedInstOperands,
15240 /* 39870 */ // GIR_Coverage, 290,
15241 /* 39870 */ GIR_EraseRootFromParent_Done,
15242 /* 39871 */ // Label 1150: @39871
15243 /* 39871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1151*/ GIMT_Encode4(39898), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1694 //
15244 /* 39878 */ // MIs[0] Operand 2
15245 /* 39878 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
15246 /* 39889 */ // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) => (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
15247 /* 39889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
15248 /* 39892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15249 /* 39894 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15250 /* 39896 */ GIR_RootConstrainSelectedInstOperands,
15251 /* 39897 */ // GIR_Coverage, 1694,
15252 /* 39897 */ GIR_EraseRootFromParent_Done,
15253 /* 39898 */ // Label 1151: @39898
15254 /* 39898 */ GIM_Reject,
15255 /* 39899 */ // Label 1148: @39899
15256 /* 39899 */ GIM_Reject,
15257 /* 39900 */ // Label 1138: @39900
15258 /* 39900 */ GIM_Reject,
15259 /* 39901 */ // Label 36: @39901
15260 /* 39901 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(40097),
15261 /* 39906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15262 /* 39909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15263 /* 39912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15264 /* 39916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1153*/ GIMT_Encode4(39971), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 308 //
15265 /* 39923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15266 /* 39927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15267 /* 39931 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15268 /* 39935 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15269 /* 39939 */ // MIs[1] Operand 1
15270 /* 39939 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
15271 /* 39944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15272 /* 39949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15273 /* 39954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15274 /* 39956 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15275 /* 39956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
15276 /* 39959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15277 /* 39961 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15278 /* 39965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15279 /* 39969 */ GIR_RootConstrainSelectedInstOperands,
15280 /* 39970 */ // GIR_Coverage, 308,
15281 /* 39970 */ GIR_EraseRootFromParent_Done,
15282 /* 39971 */ // Label 1153: @39971
15283 /* 39971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(40026), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 310 //
15284 /* 39978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
15285 /* 39982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
15286 /* 39986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
15287 /* 39990 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
15288 /* 39994 */ // MIs[1] Operand 1
15289 /* 39994 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
15290 /* 39999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15291 /* 40004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15292 /* 40009 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15293 /* 40011 */ // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
15294 /* 40011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
15295 /* 40014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15296 /* 40016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
15297 /* 40020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
15298 /* 40024 */ GIR_RootConstrainSelectedInstOperands,
15299 /* 40025 */ // GIR_Coverage, 310,
15300 /* 40025 */ GIR_EraseRootFromParent_Done,
15301 /* 40026 */ // Label 1154: @40026
15302 /* 40026 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(40096),
15303 /* 40031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15304 /* 40035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1156*/ GIMT_Encode4(40073), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1689 //
15305 /* 40042 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
15306 /* 40042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
15307 /* 40045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
15308 /* 40049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15309 /* 40054 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
15310 /* 40058 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15311 /* 40060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
15312 /* 40063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15313 /* 40065 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15314 /* 40068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15315 /* 40071 */ GIR_RootConstrainSelectedInstOperands,
15316 /* 40072 */ // GIR_Coverage, 1689,
15317 /* 40072 */ GIR_EraseRootFromParent_Done,
15318 /* 40073 */ // Label 1156: @40073
15319 /* 40073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1157*/ GIMT_Encode4(40095), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1692 //
15320 /* 40080 */ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
15321 /* 40080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
15322 /* 40083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
15323 /* 40085 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15324 /* 40087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15325 /* 40090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
15326 /* 40093 */ GIR_RootConstrainSelectedInstOperands,
15327 /* 40094 */ // GIR_Coverage, 1692,
15328 /* 40094 */ GIR_EraseRootFromParent_Done,
15329 /* 40095 */ // Label 1157: @40095
15330 /* 40095 */ GIM_Reject,
15331 /* 40096 */ // Label 1155: @40096
15332 /* 40096 */ GIM_Reject,
15333 /* 40097 */ // Label 1152: @40097
15334 /* 40097 */ GIM_Reject,
15335 /* 40098 */ // Label 37: @40098
15336 /* 40098 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1164*/ GIMT_Encode4(41872),
15337 /* 40109 */ /*GILLT_s32*//*Label 1158*/ GIMT_Encode4(40141),
15338 /* 40113 */ /*GILLT_s64*//*Label 1159*/ GIMT_Encode4(40394), GIMT_Encode4(0),
15339 /* 40121 */ /*GILLT_v16s8*//*Label 1160*/ GIMT_Encode4(40532), GIMT_Encode4(0),
15340 /* 40129 */ /*GILLT_v8s16*//*Label 1161*/ GIMT_Encode4(41181),
15341 /* 40133 */ /*GILLT_v4s32*//*Label 1162*/ GIMT_Encode4(41574),
15342 /* 40137 */ /*GILLT_v2s64*//*Label 1163*/ GIMT_Encode4(41839),
15343 /* 40141 */ // Label 1158: @40141
15344 /* 40141 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(40393),
15345 /* 40146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15346 /* 40149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15347 /* 40152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40193), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 55 //
15348 /* 40159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15349 /* 40163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15350 /* 40167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15351 /* 40171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15352 /* 40175 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15353 /* 40179 */ // MIs[1] Operand 1
15354 /* 40179 */ // No operand predicates
15355 /* 40179 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15356 /* 40181 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15357 /* 40181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
15358 /* 40184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15359 /* 40186 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15360 /* 40188 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15361 /* 40191 */ GIR_RootConstrainSelectedInstOperands,
15362 /* 40192 */ // GIR_Coverage, 55,
15363 /* 40192 */ GIR_EraseRootFromParent_Done,
15364 /* 40193 */ // Label 1166: @40193
15365 /* 40193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40234), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1965 //
15366 /* 40200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15367 /* 40204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15368 /* 40208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15369 /* 40212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15370 /* 40216 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15371 /* 40220 */ // MIs[1] Operand 1
15372 /* 40220 */ // No operand predicates
15373 /* 40220 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15374 /* 40222 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15375 /* 40222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
15376 /* 40225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15377 /* 40227 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
15378 /* 40229 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15379 /* 40232 */ GIR_RootConstrainSelectedInstOperands,
15380 /* 40233 */ // GIR_Coverage, 1965,
15381 /* 40233 */ GIR_EraseRootFromParent_Done,
15382 /* 40234 */ // Label 1167: @40234
15383 /* 40234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40275), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2302 //
15384 /* 40241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15385 /* 40245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15386 /* 40249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15387 /* 40253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15388 /* 40257 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
15389 /* 40261 */ // MIs[1] Operand 1
15390 /* 40261 */ // No operand predicates
15391 /* 40261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15392 /* 40263 */ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
15393 /* 40263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
15394 /* 40266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15395 /* 40268 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15396 /* 40270 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15397 /* 40273 */ GIR_RootConstrainSelectedInstOperands,
15398 /* 40274 */ // GIR_Coverage, 2302,
15399 /* 40274 */ GIR_EraseRootFromParent_Done,
15400 /* 40275 */ // Label 1168: @40275
15401 /* 40275 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40340),
15402 /* 40280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15403 /* 40284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15404 /* 40288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1170*/ GIMT_Encode4(40321), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2303 //
15405 /* 40295 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15406 /* 40299 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15407 /* 40303 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15408 /* 40307 */ // MIs[1] Operand 1
15409 /* 40307 */ // No operand predicates
15410 /* 40307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15411 /* 40309 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15412 /* 40309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
15413 /* 40312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15414 /* 40314 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
15415 /* 40316 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15416 /* 40319 */ GIR_RootConstrainSelectedInstOperands,
15417 /* 40320 */ // GIR_Coverage, 2303,
15418 /* 40320 */ GIR_EraseRootFromParent_Done,
15419 /* 40321 */ // Label 1170: @40321
15420 /* 40321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1171*/ GIMT_Encode4(40339), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 61 //
15421 /* 40328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15422 /* 40332 */ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15423 /* 40332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
15424 /* 40337 */ GIR_RootConstrainSelectedInstOperands,
15425 /* 40338 */ // GIR_Coverage, 61,
15426 /* 40338 */ GIR_Done,
15427 /* 40339 */ // Label 1171: @40339
15428 /* 40339 */ GIM_Reject,
15429 /* 40340 */ // Label 1169: @40340
15430 /* 40340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1172*/ GIMT_Encode4(40366), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1968 //
15431 /* 40347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15432 /* 40351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15433 /* 40355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15434 /* 40359 */ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
15435 /* 40359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
15436 /* 40364 */ GIR_RootConstrainSelectedInstOperands,
15437 /* 40365 */ // GIR_Coverage, 1968,
15438 /* 40365 */ GIR_Done,
15439 /* 40366 */ // Label 1172: @40366
15440 /* 40366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1173*/ GIMT_Encode4(40392), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2304 //
15441 /* 40373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15442 /* 40377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15443 /* 40381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15444 /* 40385 */ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
15445 /* 40385 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
15446 /* 40390 */ GIR_RootConstrainSelectedInstOperands,
15447 /* 40391 */ // GIR_Coverage, 2304,
15448 /* 40391 */ GIR_Done,
15449 /* 40392 */ // Label 1173: @40392
15450 /* 40392 */ GIM_Reject,
15451 /* 40393 */ // Label 1165: @40393
15452 /* 40393 */ GIM_Reject,
15453 /* 40394 */ // Label 1159: @40394
15454 /* 40394 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(40531),
15455 /* 40399 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15456 /* 40402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15457 /* 40405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15458 /* 40409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15459 /* 40413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1175*/ GIMT_Encode4(40446), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 238 //
15460 /* 40420 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15461 /* 40424 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15462 /* 40428 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15463 /* 40432 */ // MIs[1] Operand 1
15464 /* 40432 */ // No operand predicates
15465 /* 40432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15466 /* 40434 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15467 /* 40434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
15468 /* 40437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15469 /* 40439 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15470 /* 40441 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15471 /* 40444 */ GIR_RootConstrainSelectedInstOperands,
15472 /* 40445 */ // GIR_Coverage, 238,
15473 /* 40445 */ GIR_EraseRootFromParent_Done,
15474 /* 40446 */ // Label 1175: @40446
15475 /* 40446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1176*/ GIMT_Encode4(40512), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1682 //
15476 /* 40453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15477 /* 40457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
15478 /* 40461 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15479 /* 40465 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15480 /* 40470 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
15481 /* 40472 */ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15482 /* 40472 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15483 /* 40475 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15484 /* 40479 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15485 /* 40484 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
15486 /* 40490 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15487 /* 40495 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15488 /* 40500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15489 /* 40503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15490 /* 40505 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
15491 /* 40507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15492 /* 40510 */ GIR_RootConstrainSelectedInstOperands,
15493 /* 40511 */ // GIR_Coverage, 1682,
15494 /* 40511 */ GIR_EraseRootFromParent_Done,
15495 /* 40512 */ // Label 1176: @40512
15496 /* 40512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1177*/ GIMT_Encode4(40530), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 244 //
15497 /* 40519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15498 /* 40523 */ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15499 /* 40523 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
15500 /* 40528 */ GIR_RootConstrainSelectedInstOperands,
15501 /* 40529 */ // GIR_Coverage, 244,
15502 /* 40529 */ GIR_Done,
15503 /* 40530 */ // Label 1177: @40530
15504 /* 40530 */ GIM_Reject,
15505 /* 40531 */ // Label 1174: @40531
15506 /* 40531 */ GIM_Reject,
15507 /* 40532 */ // Label 1160: @40532
15508 /* 40532 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(41180),
15509 /* 40537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
15510 /* 40540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15511 /* 40543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15512 /* 40547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1179*/ GIMT_Encode4(40852), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2636 //
15513 /* 40554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15514 /* 40558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15515 /* 40562 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15516 /* 40566 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15517 /* 40570 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15518 /* 40574 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15519 /* 40578 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15520 /* 40581 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15521 /* 40585 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15522 /* 40589 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15523 /* 40593 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15524 /* 40597 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15525 /* 40601 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15526 /* 40605 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15527 /* 40609 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15528 /* 40613 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15529 /* 40617 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15530 /* 40621 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15531 /* 40625 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15532 /* 40629 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15533 /* 40633 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15534 /* 40637 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15535 /* 40641 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15536 /* 40645 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15537 /* 40649 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15538 /* 40653 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15539 /* 40657 */ // MIs[3] Operand 1
15540 /* 40657 */ // No operand predicates
15541 /* 40657 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15542 /* 40661 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15543 /* 40665 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15544 /* 40669 */ // MIs[4] Operand 1
15545 /* 40669 */ // No operand predicates
15546 /* 40669 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15547 /* 40673 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15548 /* 40677 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15549 /* 40681 */ // MIs[5] Operand 1
15550 /* 40681 */ // No operand predicates
15551 /* 40681 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15552 /* 40685 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15553 /* 40689 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15554 /* 40693 */ // MIs[6] Operand 1
15555 /* 40693 */ // No operand predicates
15556 /* 40693 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15557 /* 40697 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15558 /* 40701 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15559 /* 40705 */ // MIs[7] Operand 1
15560 /* 40705 */ // No operand predicates
15561 /* 40705 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15562 /* 40709 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15563 /* 40713 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15564 /* 40717 */ // MIs[8] Operand 1
15565 /* 40717 */ // No operand predicates
15566 /* 40717 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15567 /* 40721 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15568 /* 40725 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15569 /* 40729 */ // MIs[9] Operand 1
15570 /* 40729 */ // No operand predicates
15571 /* 40729 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15572 /* 40733 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15573 /* 40737 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15574 /* 40741 */ // MIs[10] Operand 1
15575 /* 40741 */ // No operand predicates
15576 /* 40741 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15577 /* 40745 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15578 /* 40749 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15579 /* 40753 */ // MIs[11] Operand 1
15580 /* 40753 */ // No operand predicates
15581 /* 40753 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15582 /* 40757 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15583 /* 40761 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15584 /* 40765 */ // MIs[12] Operand 1
15585 /* 40765 */ // No operand predicates
15586 /* 40765 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15587 /* 40769 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15588 /* 40773 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15589 /* 40777 */ // MIs[13] Operand 1
15590 /* 40777 */ // No operand predicates
15591 /* 40777 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15592 /* 40781 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15593 /* 40785 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15594 /* 40789 */ // MIs[14] Operand 1
15595 /* 40789 */ // No operand predicates
15596 /* 40789 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15597 /* 40793 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15598 /* 40797 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15599 /* 40801 */ // MIs[15] Operand 1
15600 /* 40801 */ // No operand predicates
15601 /* 40801 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15602 /* 40805 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15603 /* 40809 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15604 /* 40813 */ // MIs[16] Operand 1
15605 /* 40813 */ // No operand predicates
15606 /* 40813 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15607 /* 40817 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15608 /* 40821 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15609 /* 40825 */ // MIs[17] Operand 1
15610 /* 40825 */ // No operand predicates
15611 /* 40825 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15612 /* 40829 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15613 /* 40833 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15614 /* 40837 */ // MIs[18] Operand 1
15615 /* 40837 */ // No operand predicates
15616 /* 40837 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
15617 /* 40839 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15618 /* 40839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15619 /* 40842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15620 /* 40844 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15621 /* 40846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15622 /* 40850 */ GIR_RootConstrainSelectedInstOperands,
15623 /* 40851 */ // GIR_Coverage, 2636,
15624 /* 40851 */ GIR_EraseRootFromParent_Done,
15625 /* 40852 */ // Label 1179: @40852
15626 /* 40852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1180*/ GIMT_Encode4(41157), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2201 //
15627 /* 40859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15628 /* 40863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15629 /* 40867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15630 /* 40871 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15631 /* 40875 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15632 /* 40879 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15633 /* 40883 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15634 /* 40886 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15635 /* 40890 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15636 /* 40894 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15637 /* 40898 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15638 /* 40902 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15639 /* 40906 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15640 /* 40910 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15641 /* 40914 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15642 /* 40918 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15643 /* 40922 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15644 /* 40926 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15645 /* 40930 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15646 /* 40934 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15647 /* 40938 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15648 /* 40942 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15649 /* 40946 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15650 /* 40950 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15651 /* 40954 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15652 /* 40958 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15653 /* 40962 */ // MIs[3] Operand 1
15654 /* 40962 */ // No operand predicates
15655 /* 40962 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15656 /* 40966 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15657 /* 40970 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15658 /* 40974 */ // MIs[4] Operand 1
15659 /* 40974 */ // No operand predicates
15660 /* 40974 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15661 /* 40978 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15662 /* 40982 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15663 /* 40986 */ // MIs[5] Operand 1
15664 /* 40986 */ // No operand predicates
15665 /* 40986 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15666 /* 40990 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15667 /* 40994 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15668 /* 40998 */ // MIs[6] Operand 1
15669 /* 40998 */ // No operand predicates
15670 /* 40998 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15671 /* 41002 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15672 /* 41006 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15673 /* 41010 */ // MIs[7] Operand 1
15674 /* 41010 */ // No operand predicates
15675 /* 41010 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15676 /* 41014 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15677 /* 41018 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15678 /* 41022 */ // MIs[8] Operand 1
15679 /* 41022 */ // No operand predicates
15680 /* 41022 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15681 /* 41026 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15682 /* 41030 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15683 /* 41034 */ // MIs[9] Operand 1
15684 /* 41034 */ // No operand predicates
15685 /* 41034 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15686 /* 41038 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15687 /* 41042 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15688 /* 41046 */ // MIs[10] Operand 1
15689 /* 41046 */ // No operand predicates
15690 /* 41046 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15691 /* 41050 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15692 /* 41054 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15693 /* 41058 */ // MIs[11] Operand 1
15694 /* 41058 */ // No operand predicates
15695 /* 41058 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15696 /* 41062 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15697 /* 41066 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15698 /* 41070 */ // MIs[12] Operand 1
15699 /* 41070 */ // No operand predicates
15700 /* 41070 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15701 /* 41074 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15702 /* 41078 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15703 /* 41082 */ // MIs[13] Operand 1
15704 /* 41082 */ // No operand predicates
15705 /* 41082 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15706 /* 41086 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15707 /* 41090 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15708 /* 41094 */ // MIs[14] Operand 1
15709 /* 41094 */ // No operand predicates
15710 /* 41094 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15711 /* 41098 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15712 /* 41102 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15713 /* 41106 */ // MIs[15] Operand 1
15714 /* 41106 */ // No operand predicates
15715 /* 41106 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15716 /* 41110 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15717 /* 41114 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15718 /* 41118 */ // MIs[16] Operand 1
15719 /* 41118 */ // No operand predicates
15720 /* 41118 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15721 /* 41122 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15722 /* 41126 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15723 /* 41130 */ // MIs[17] Operand 1
15724 /* 41130 */ // No operand predicates
15725 /* 41130 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15726 /* 41134 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15727 /* 41138 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15728 /* 41142 */ // MIs[18] Operand 1
15729 /* 41142 */ // No operand predicates
15730 /* 41142 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
15731 /* 41144 */ // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15732 /* 41144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15733 /* 41147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15734 /* 41149 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15735 /* 41151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15736 /* 41155 */ GIR_RootConstrainSelectedInstOperands,
15737 /* 41156 */ // GIR_Coverage, 2201,
15738 /* 41156 */ GIR_EraseRootFromParent_Done,
15739 /* 41157 */ // Label 1180: @41157
15740 /* 41157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1181*/ GIMT_Encode4(41179), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 985 //
15741 /* 41164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15742 /* 41168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15743 /* 41172 */ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15744 /* 41172 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15745 /* 41177 */ GIR_RootConstrainSelectedInstOperands,
15746 /* 41178 */ // GIR_Coverage, 985,
15747 /* 41178 */ GIR_Done,
15748 /* 41179 */ // Label 1181: @41179
15749 /* 41179 */ GIM_Reject,
15750 /* 41180 */ // Label 1178: @41180
15751 /* 41180 */ GIM_Reject,
15752 /* 41181 */ // Label 1161: @41181
15753 /* 41181 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(41573),
15754 /* 41186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
15755 /* 41189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15756 /* 41192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15757 /* 41196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1183*/ GIMT_Encode4(41373), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2637 //
15758 /* 41203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15759 /* 41207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15760 /* 41211 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15761 /* 41215 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15762 /* 41219 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15763 /* 41223 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15764 /* 41227 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15765 /* 41230 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15766 /* 41234 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15767 /* 41238 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15768 /* 41242 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15769 /* 41246 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15770 /* 41250 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15771 /* 41254 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15772 /* 41258 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15773 /* 41262 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15774 /* 41266 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15775 /* 41270 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15776 /* 41274 */ // MIs[3] Operand 1
15777 /* 41274 */ // No operand predicates
15778 /* 41274 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15779 /* 41278 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15780 /* 41282 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15781 /* 41286 */ // MIs[4] Operand 1
15782 /* 41286 */ // No operand predicates
15783 /* 41286 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15784 /* 41290 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15785 /* 41294 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15786 /* 41298 */ // MIs[5] Operand 1
15787 /* 41298 */ // No operand predicates
15788 /* 41298 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15789 /* 41302 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15790 /* 41306 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15791 /* 41310 */ // MIs[6] Operand 1
15792 /* 41310 */ // No operand predicates
15793 /* 41310 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15794 /* 41314 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15795 /* 41318 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15796 /* 41322 */ // MIs[7] Operand 1
15797 /* 41322 */ // No operand predicates
15798 /* 41322 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15799 /* 41326 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15800 /* 41330 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15801 /* 41334 */ // MIs[8] Operand 1
15802 /* 41334 */ // No operand predicates
15803 /* 41334 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15804 /* 41338 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15805 /* 41342 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15806 /* 41346 */ // MIs[9] Operand 1
15807 /* 41346 */ // No operand predicates
15808 /* 41346 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15809 /* 41350 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15810 /* 41354 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15811 /* 41358 */ // MIs[10] Operand 1
15812 /* 41358 */ // No operand predicates
15813 /* 41358 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
15814 /* 41360 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15815 /* 41360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
15816 /* 41363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15817 /* 41365 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15818 /* 41367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15819 /* 41371 */ GIR_RootConstrainSelectedInstOperands,
15820 /* 41372 */ // GIR_Coverage, 2637,
15821 /* 41372 */ GIR_EraseRootFromParent_Done,
15822 /* 41373 */ // Label 1183: @41373
15823 /* 41373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1184*/ GIMT_Encode4(41550), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2202 //
15824 /* 41380 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15825 /* 41384 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15826 /* 41388 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15827 /* 41392 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15828 /* 41396 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15829 /* 41400 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15830 /* 41404 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15831 /* 41407 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15832 /* 41411 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15833 /* 41415 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15834 /* 41419 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15835 /* 41423 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15836 /* 41427 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15837 /* 41431 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15838 /* 41435 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15839 /* 41439 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15840 /* 41443 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15841 /* 41447 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15842 /* 41451 */ // MIs[3] Operand 1
15843 /* 41451 */ // No operand predicates
15844 /* 41451 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15845 /* 41455 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15846 /* 41459 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15847 /* 41463 */ // MIs[4] Operand 1
15848 /* 41463 */ // No operand predicates
15849 /* 41463 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15850 /* 41467 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15851 /* 41471 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15852 /* 41475 */ // MIs[5] Operand 1
15853 /* 41475 */ // No operand predicates
15854 /* 41475 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15855 /* 41479 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15856 /* 41483 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15857 /* 41487 */ // MIs[6] Operand 1
15858 /* 41487 */ // No operand predicates
15859 /* 41487 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15860 /* 41491 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15861 /* 41495 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15862 /* 41499 */ // MIs[7] Operand 1
15863 /* 41499 */ // No operand predicates
15864 /* 41499 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15865 /* 41503 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15866 /* 41507 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15867 /* 41511 */ // MIs[8] Operand 1
15868 /* 41511 */ // No operand predicates
15869 /* 41511 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15870 /* 41515 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15871 /* 41519 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15872 /* 41523 */ // MIs[9] Operand 1
15873 /* 41523 */ // No operand predicates
15874 /* 41523 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15875 /* 41527 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15876 /* 41531 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15877 /* 41535 */ // MIs[10] Operand 1
15878 /* 41535 */ // No operand predicates
15879 /* 41535 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
15880 /* 41537 */ // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15881 /* 41537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
15882 /* 41540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15883 /* 41542 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15884 /* 41544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15885 /* 41548 */ GIR_RootConstrainSelectedInstOperands,
15886 /* 41549 */ // GIR_Coverage, 2202,
15887 /* 41549 */ GIR_EraseRootFromParent_Done,
15888 /* 41550 */ // Label 1184: @41550
15889 /* 41550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1185*/ GIMT_Encode4(41572), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 986 //
15890 /* 41557 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15891 /* 41561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15892 /* 41565 */ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
15893 /* 41565 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
15894 /* 41570 */ GIR_RootConstrainSelectedInstOperands,
15895 /* 41571 */ // GIR_Coverage, 986,
15896 /* 41571 */ GIR_Done,
15897 /* 41572 */ // Label 1185: @41572
15898 /* 41572 */ GIM_Reject,
15899 /* 41573 */ // Label 1182: @41573
15900 /* 41573 */ GIM_Reject,
15901 /* 41574 */ // Label 1162: @41574
15902 /* 41574 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(41838),
15903 /* 41579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
15904 /* 41582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15905 /* 41585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15906 /* 41589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1187*/ GIMT_Encode4(41702), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2638 //
15907 /* 41596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15908 /* 41600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15909 /* 41604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15910 /* 41608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15911 /* 41612 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15912 /* 41616 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15913 /* 41620 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15914 /* 41623 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15915 /* 41627 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15916 /* 41631 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15917 /* 41635 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15918 /* 41639 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15919 /* 41643 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15920 /* 41647 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15921 /* 41651 */ // MIs[3] Operand 1
15922 /* 41651 */ // No operand predicates
15923 /* 41651 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15924 /* 41655 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15925 /* 41659 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15926 /* 41663 */ // MIs[4] Operand 1
15927 /* 41663 */ // No operand predicates
15928 /* 41663 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15929 /* 41667 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15930 /* 41671 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15931 /* 41675 */ // MIs[5] Operand 1
15932 /* 41675 */ // No operand predicates
15933 /* 41675 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15934 /* 41679 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15935 /* 41683 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15936 /* 41687 */ // MIs[6] Operand 1
15937 /* 41687 */ // No operand predicates
15938 /* 41687 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
15939 /* 41689 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15940 /* 41689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15941 /* 41692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15942 /* 41694 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15943 /* 41696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15944 /* 41700 */ GIR_RootConstrainSelectedInstOperands,
15945 /* 41701 */ // GIR_Coverage, 2638,
15946 /* 41701 */ GIR_EraseRootFromParent_Done,
15947 /* 41702 */ // Label 1187: @41702
15948 /* 41702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1188*/ GIMT_Encode4(41815), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2203 //
15949 /* 41709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15950 /* 41713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15951 /* 41717 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15952 /* 41721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15953 /* 41725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15954 /* 41729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15955 /* 41733 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15956 /* 41736 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15957 /* 41740 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15958 /* 41744 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15959 /* 41748 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15960 /* 41752 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15961 /* 41756 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15962 /* 41760 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15963 /* 41764 */ // MIs[3] Operand 1
15964 /* 41764 */ // No operand predicates
15965 /* 41764 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15966 /* 41768 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15967 /* 41772 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15968 /* 41776 */ // MIs[4] Operand 1
15969 /* 41776 */ // No operand predicates
15970 /* 41776 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15971 /* 41780 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15972 /* 41784 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15973 /* 41788 */ // MIs[5] Operand 1
15974 /* 41788 */ // No operand predicates
15975 /* 41788 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15976 /* 41792 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15977 /* 41796 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15978 /* 41800 */ // MIs[6] Operand 1
15979 /* 41800 */ // No operand predicates
15980 /* 41800 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
15981 /* 41802 */ // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15982 /* 41802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15983 /* 41805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15984 /* 41807 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
15985 /* 41809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15986 /* 41813 */ GIR_RootConstrainSelectedInstOperands,
15987 /* 41814 */ // GIR_Coverage, 2203,
15988 /* 41814 */ GIR_EraseRootFromParent_Done,
15989 /* 41815 */ // Label 1188: @41815
15990 /* 41815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1189*/ GIMT_Encode4(41837), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 987 //
15991 /* 41822 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15992 /* 41826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15993 /* 41830 */ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
15994 /* 41830 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
15995 /* 41835 */ GIR_RootConstrainSelectedInstOperands,
15996 /* 41836 */ // GIR_Coverage, 987,
15997 /* 41836 */ GIR_Done,
15998 /* 41837 */ // Label 1189: @41837
15999 /* 41837 */ GIM_Reject,
16000 /* 41838 */ // Label 1186: @41838
16001 /* 41838 */ GIM_Reject,
16002 /* 41839 */ // Label 1163: @41839
16003 /* 41839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1190*/ GIMT_Encode4(41871), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 988 //
16004 /* 41846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16005 /* 41849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16006 /* 41852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16007 /* 41856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16008 /* 41860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16009 /* 41864 */ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16010 /* 41864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
16011 /* 41869 */ GIR_RootConstrainSelectedInstOperands,
16012 /* 41870 */ // GIR_Coverage, 988,
16013 /* 41870 */ GIR_Done,
16014 /* 41871 */ // Label 1190: @41871
16015 /* 41871 */ GIM_Reject,
16016 /* 41872 */ // Label 1164: @41872
16017 /* 41872 */ GIM_Reject,
16018 /* 41873 */ // Label 38: @41873
16019 /* 41873 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1197*/ GIMT_Encode4(43647),
16020 /* 41884 */ /*GILLT_s32*//*Label 1191*/ GIMT_Encode4(41916),
16021 /* 41888 */ /*GILLT_s64*//*Label 1192*/ GIMT_Encode4(42169), GIMT_Encode4(0),
16022 /* 41896 */ /*GILLT_v16s8*//*Label 1193*/ GIMT_Encode4(42307), GIMT_Encode4(0),
16023 /* 41904 */ /*GILLT_v8s16*//*Label 1194*/ GIMT_Encode4(42956),
16024 /* 41908 */ /*GILLT_v4s32*//*Label 1195*/ GIMT_Encode4(43349),
16025 /* 41912 */ /*GILLT_v2s64*//*Label 1196*/ GIMT_Encode4(43614),
16026 /* 41916 */ // Label 1191: @41916
16027 /* 41916 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(42168),
16028 /* 41921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16029 /* 41924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16030 /* 41927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1199*/ GIMT_Encode4(41968), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 57 //
16031 /* 41934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16032 /* 41938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16033 /* 41942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16034 /* 41946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16035 /* 41950 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16036 /* 41954 */ // MIs[1] Operand 1
16037 /* 41954 */ // No operand predicates
16038 /* 41954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16039 /* 41956 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16040 /* 41956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
16041 /* 41959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16042 /* 41961 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16043 /* 41963 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16044 /* 41966 */ GIR_RootConstrainSelectedInstOperands,
16045 /* 41967 */ // GIR_Coverage, 57,
16046 /* 41967 */ GIR_EraseRootFromParent_Done,
16047 /* 41968 */ // Label 1199: @41968
16048 /* 41968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1200*/ GIMT_Encode4(42009), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1966 //
16049 /* 41975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16050 /* 41979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16051 /* 41983 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16052 /* 41987 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16053 /* 41991 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16054 /* 41995 */ // MIs[1] Operand 1
16055 /* 41995 */ // No operand predicates
16056 /* 41995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16057 /* 41997 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16058 /* 41997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
16059 /* 42000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16060 /* 42002 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16061 /* 42004 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16062 /* 42007 */ GIR_RootConstrainSelectedInstOperands,
16063 /* 42008 */ // GIR_Coverage, 1966,
16064 /* 42008 */ GIR_EraseRootFromParent_Done,
16065 /* 42009 */ // Label 1200: @42009
16066 /* 42009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1201*/ GIMT_Encode4(42050), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2305 //
16067 /* 42016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16068 /* 42020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
16069 /* 42024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16070 /* 42028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16071 /* 42032 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
16072 /* 42036 */ // MIs[1] Operand 1
16073 /* 42036 */ // No operand predicates
16074 /* 42036 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16075 /* 42038 */ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
16076 /* 42038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
16077 /* 42041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16078 /* 42043 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16079 /* 42045 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16080 /* 42048 */ GIR_RootConstrainSelectedInstOperands,
16081 /* 42049 */ // GIR_Coverage, 2305,
16082 /* 42049 */ GIR_EraseRootFromParent_Done,
16083 /* 42050 */ // Label 1201: @42050
16084 /* 42050 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(42115),
16085 /* 42055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16086 /* 42059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16087 /* 42063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1203*/ GIMT_Encode4(42096), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2306 //
16088 /* 42070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16089 /* 42074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16090 /* 42078 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16091 /* 42082 */ // MIs[1] Operand 1
16092 /* 42082 */ // No operand predicates
16093 /* 42082 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16094 /* 42084 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16095 /* 42084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
16096 /* 42087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16097 /* 42089 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16098 /* 42091 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16099 /* 42094 */ GIR_RootConstrainSelectedInstOperands,
16100 /* 42095 */ // GIR_Coverage, 2306,
16101 /* 42095 */ GIR_EraseRootFromParent_Done,
16102 /* 42096 */ // Label 1203: @42096
16103 /* 42096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1204*/ GIMT_Encode4(42114), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 63 //
16104 /* 42103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16105 /* 42107 */ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16106 /* 42107 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
16107 /* 42112 */ GIR_RootConstrainSelectedInstOperands,
16108 /* 42113 */ // GIR_Coverage, 63,
16109 /* 42113 */ GIR_Done,
16110 /* 42114 */ // Label 1204: @42114
16111 /* 42114 */ GIM_Reject,
16112 /* 42115 */ // Label 1202: @42115
16113 /* 42115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1205*/ GIMT_Encode4(42141), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1970 //
16114 /* 42122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16115 /* 42126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16116 /* 42130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16117 /* 42134 */ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16118 /* 42134 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
16119 /* 42139 */ GIR_RootConstrainSelectedInstOperands,
16120 /* 42140 */ // GIR_Coverage, 1970,
16121 /* 42140 */ GIR_Done,
16122 /* 42141 */ // Label 1205: @42141
16123 /* 42141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1206*/ GIMT_Encode4(42167), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2307 //
16124 /* 42148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16125 /* 42152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16126 /* 42156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16127 /* 42160 */ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16128 /* 42160 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
16129 /* 42165 */ GIR_RootConstrainSelectedInstOperands,
16130 /* 42166 */ // GIR_Coverage, 2307,
16131 /* 42166 */ GIR_Done,
16132 /* 42167 */ // Label 1206: @42167
16133 /* 42167 */ GIM_Reject,
16134 /* 42168 */ // Label 1198: @42168
16135 /* 42168 */ GIM_Reject,
16136 /* 42169 */ // Label 1192: @42169
16137 /* 42169 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(42306),
16138 /* 42174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16139 /* 42177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16140 /* 42180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16141 /* 42184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16142 /* 42188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1208*/ GIMT_Encode4(42221), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 240 //
16143 /* 42195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16144 /* 42199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16145 /* 42203 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16146 /* 42207 */ // MIs[1] Operand 1
16147 /* 42207 */ // No operand predicates
16148 /* 42207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16149 /* 42209 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16150 /* 42209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
16151 /* 42212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16152 /* 42214 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16153 /* 42216 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16154 /* 42219 */ GIR_RootConstrainSelectedInstOperands,
16155 /* 42220 */ // GIR_Coverage, 240,
16156 /* 42220 */ GIR_EraseRootFromParent_Done,
16157 /* 42221 */ // Label 1208: @42221
16158 /* 42221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1209*/ GIMT_Encode4(42287), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1683 //
16159 /* 42228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16160 /* 42232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16161 /* 42236 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16162 /* 42240 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16163 /* 42245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16164 /* 42247 */ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16165 /* 42247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16166 /* 42250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16167 /* 42254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16168 /* 42259 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16169 /* 42265 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16170 /* 42270 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16171 /* 42275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16172 /* 42278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16173 /* 42280 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16174 /* 42282 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16175 /* 42285 */ GIR_RootConstrainSelectedInstOperands,
16176 /* 42286 */ // GIR_Coverage, 1683,
16177 /* 42286 */ GIR_EraseRootFromParent_Done,
16178 /* 42287 */ // Label 1209: @42287
16179 /* 42287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(42305), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 248 //
16180 /* 42294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16181 /* 42298 */ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16182 /* 42298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
16183 /* 42303 */ GIR_RootConstrainSelectedInstOperands,
16184 /* 42304 */ // GIR_Coverage, 248,
16185 /* 42304 */ GIR_Done,
16186 /* 42305 */ // Label 1210: @42305
16187 /* 42305 */ GIM_Reject,
16188 /* 42306 */ // Label 1207: @42306
16189 /* 42306 */ GIM_Reject,
16190 /* 42307 */ // Label 1193: @42307
16191 /* 42307 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(42955),
16192 /* 42312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16193 /* 42315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16194 /* 42318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16195 /* 42322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1212*/ GIMT_Encode4(42627), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2652 //
16196 /* 42329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16197 /* 42333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16198 /* 42337 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16199 /* 42341 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16200 /* 42345 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16201 /* 42349 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16202 /* 42353 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16203 /* 42356 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16204 /* 42360 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16205 /* 42364 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16206 /* 42368 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16207 /* 42372 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16208 /* 42376 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16209 /* 42380 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16210 /* 42384 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16211 /* 42388 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16212 /* 42392 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16213 /* 42396 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16214 /* 42400 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16215 /* 42404 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16216 /* 42408 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16217 /* 42412 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16218 /* 42416 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16219 /* 42420 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16220 /* 42424 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16221 /* 42428 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16222 /* 42432 */ // MIs[3] Operand 1
16223 /* 42432 */ // No operand predicates
16224 /* 42432 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16225 /* 42436 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16226 /* 42440 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16227 /* 42444 */ // MIs[4] Operand 1
16228 /* 42444 */ // No operand predicates
16229 /* 42444 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16230 /* 42448 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16231 /* 42452 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16232 /* 42456 */ // MIs[5] Operand 1
16233 /* 42456 */ // No operand predicates
16234 /* 42456 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16235 /* 42460 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16236 /* 42464 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16237 /* 42468 */ // MIs[6] Operand 1
16238 /* 42468 */ // No operand predicates
16239 /* 42468 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16240 /* 42472 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16241 /* 42476 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16242 /* 42480 */ // MIs[7] Operand 1
16243 /* 42480 */ // No operand predicates
16244 /* 42480 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16245 /* 42484 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16246 /* 42488 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16247 /* 42492 */ // MIs[8] Operand 1
16248 /* 42492 */ // No operand predicates
16249 /* 42492 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16250 /* 42496 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16251 /* 42500 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16252 /* 42504 */ // MIs[9] Operand 1
16253 /* 42504 */ // No operand predicates
16254 /* 42504 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16255 /* 42508 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16256 /* 42512 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16257 /* 42516 */ // MIs[10] Operand 1
16258 /* 42516 */ // No operand predicates
16259 /* 42516 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16260 /* 42520 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16261 /* 42524 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16262 /* 42528 */ // MIs[11] Operand 1
16263 /* 42528 */ // No operand predicates
16264 /* 42528 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16265 /* 42532 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16266 /* 42536 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16267 /* 42540 */ // MIs[12] Operand 1
16268 /* 42540 */ // No operand predicates
16269 /* 42540 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16270 /* 42544 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16271 /* 42548 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16272 /* 42552 */ // MIs[13] Operand 1
16273 /* 42552 */ // No operand predicates
16274 /* 42552 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16275 /* 42556 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16276 /* 42560 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16277 /* 42564 */ // MIs[14] Operand 1
16278 /* 42564 */ // No operand predicates
16279 /* 42564 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16280 /* 42568 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16281 /* 42572 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16282 /* 42576 */ // MIs[15] Operand 1
16283 /* 42576 */ // No operand predicates
16284 /* 42576 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16285 /* 42580 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16286 /* 42584 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16287 /* 42588 */ // MIs[16] Operand 1
16288 /* 42588 */ // No operand predicates
16289 /* 42588 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16290 /* 42592 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16291 /* 42596 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16292 /* 42600 */ // MIs[17] Operand 1
16293 /* 42600 */ // No operand predicates
16294 /* 42600 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16295 /* 42604 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16296 /* 42608 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16297 /* 42612 */ // MIs[18] Operand 1
16298 /* 42612 */ // No operand predicates
16299 /* 42612 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16300 /* 42614 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16301 /* 42614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16302 /* 42617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16303 /* 42619 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16304 /* 42621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16305 /* 42625 */ GIR_RootConstrainSelectedInstOperands,
16306 /* 42626 */ // GIR_Coverage, 2652,
16307 /* 42626 */ GIR_EraseRootFromParent_Done,
16308 /* 42627 */ // Label 1212: @42627
16309 /* 42627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1213*/ GIMT_Encode4(42932), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2209 //
16310 /* 42634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16311 /* 42638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16312 /* 42642 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16313 /* 42646 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16314 /* 42650 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16315 /* 42654 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16316 /* 42658 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16317 /* 42661 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16318 /* 42665 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16319 /* 42669 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16320 /* 42673 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16321 /* 42677 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16322 /* 42681 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16323 /* 42685 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16324 /* 42689 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16325 /* 42693 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16326 /* 42697 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16327 /* 42701 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16328 /* 42705 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16329 /* 42709 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16330 /* 42713 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16331 /* 42717 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16332 /* 42721 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16333 /* 42725 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16334 /* 42729 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16335 /* 42733 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16336 /* 42737 */ // MIs[3] Operand 1
16337 /* 42737 */ // No operand predicates
16338 /* 42737 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16339 /* 42741 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16340 /* 42745 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16341 /* 42749 */ // MIs[4] Operand 1
16342 /* 42749 */ // No operand predicates
16343 /* 42749 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16344 /* 42753 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16345 /* 42757 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16346 /* 42761 */ // MIs[5] Operand 1
16347 /* 42761 */ // No operand predicates
16348 /* 42761 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16349 /* 42765 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16350 /* 42769 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16351 /* 42773 */ // MIs[6] Operand 1
16352 /* 42773 */ // No operand predicates
16353 /* 42773 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16354 /* 42777 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16355 /* 42781 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16356 /* 42785 */ // MIs[7] Operand 1
16357 /* 42785 */ // No operand predicates
16358 /* 42785 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16359 /* 42789 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16360 /* 42793 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16361 /* 42797 */ // MIs[8] Operand 1
16362 /* 42797 */ // No operand predicates
16363 /* 42797 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16364 /* 42801 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16365 /* 42805 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16366 /* 42809 */ // MIs[9] Operand 1
16367 /* 42809 */ // No operand predicates
16368 /* 42809 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16369 /* 42813 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16370 /* 42817 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16371 /* 42821 */ // MIs[10] Operand 1
16372 /* 42821 */ // No operand predicates
16373 /* 42821 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16374 /* 42825 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16375 /* 42829 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16376 /* 42833 */ // MIs[11] Operand 1
16377 /* 42833 */ // No operand predicates
16378 /* 42833 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16379 /* 42837 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16380 /* 42841 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16381 /* 42845 */ // MIs[12] Operand 1
16382 /* 42845 */ // No operand predicates
16383 /* 42845 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16384 /* 42849 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16385 /* 42853 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16386 /* 42857 */ // MIs[13] Operand 1
16387 /* 42857 */ // No operand predicates
16388 /* 42857 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16389 /* 42861 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16390 /* 42865 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16391 /* 42869 */ // MIs[14] Operand 1
16392 /* 42869 */ // No operand predicates
16393 /* 42869 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16394 /* 42873 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16395 /* 42877 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16396 /* 42881 */ // MIs[15] Operand 1
16397 /* 42881 */ // No operand predicates
16398 /* 42881 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16399 /* 42885 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16400 /* 42889 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16401 /* 42893 */ // MIs[16] Operand 1
16402 /* 42893 */ // No operand predicates
16403 /* 42893 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16404 /* 42897 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16405 /* 42901 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16406 /* 42905 */ // MIs[17] Operand 1
16407 /* 42905 */ // No operand predicates
16408 /* 42905 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16409 /* 42909 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16410 /* 42913 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16411 /* 42917 */ // MIs[18] Operand 1
16412 /* 42917 */ // No operand predicates
16413 /* 42917 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16414 /* 42919 */ // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16415 /* 42919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16416 /* 42922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16417 /* 42924 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16418 /* 42926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16419 /* 42930 */ GIR_RootConstrainSelectedInstOperands,
16420 /* 42931 */ // GIR_Coverage, 2209,
16421 /* 42931 */ GIR_EraseRootFromParent_Done,
16422 /* 42932 */ // Label 1213: @42932
16423 /* 42932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1214*/ GIMT_Encode4(42954), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1017 //
16424 /* 42939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16425 /* 42943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16426 /* 42947 */ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
16427 /* 42947 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
16428 /* 42952 */ GIR_RootConstrainSelectedInstOperands,
16429 /* 42953 */ // GIR_Coverage, 1017,
16430 /* 42953 */ GIR_Done,
16431 /* 42954 */ // Label 1214: @42954
16432 /* 42954 */ GIM_Reject,
16433 /* 42955 */ // Label 1211: @42955
16434 /* 42955 */ GIM_Reject,
16435 /* 42956 */ // Label 1194: @42956
16436 /* 42956 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(43348),
16437 /* 42961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16438 /* 42964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16439 /* 42967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16440 /* 42971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1216*/ GIMT_Encode4(43148), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2653 //
16441 /* 42978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16442 /* 42982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16443 /* 42986 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16444 /* 42990 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16445 /* 42994 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16446 /* 42998 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16447 /* 43002 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16448 /* 43005 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16449 /* 43009 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16450 /* 43013 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16451 /* 43017 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16452 /* 43021 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16453 /* 43025 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16454 /* 43029 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16455 /* 43033 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16456 /* 43037 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16457 /* 43041 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16458 /* 43045 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16459 /* 43049 */ // MIs[3] Operand 1
16460 /* 43049 */ // No operand predicates
16461 /* 43049 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16462 /* 43053 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16463 /* 43057 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16464 /* 43061 */ // MIs[4] Operand 1
16465 /* 43061 */ // No operand predicates
16466 /* 43061 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16467 /* 43065 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16468 /* 43069 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16469 /* 43073 */ // MIs[5] Operand 1
16470 /* 43073 */ // No operand predicates
16471 /* 43073 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16472 /* 43077 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16473 /* 43081 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16474 /* 43085 */ // MIs[6] Operand 1
16475 /* 43085 */ // No operand predicates
16476 /* 43085 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16477 /* 43089 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16478 /* 43093 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16479 /* 43097 */ // MIs[7] Operand 1
16480 /* 43097 */ // No operand predicates
16481 /* 43097 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16482 /* 43101 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16483 /* 43105 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16484 /* 43109 */ // MIs[8] Operand 1
16485 /* 43109 */ // No operand predicates
16486 /* 43109 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16487 /* 43113 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16488 /* 43117 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16489 /* 43121 */ // MIs[9] Operand 1
16490 /* 43121 */ // No operand predicates
16491 /* 43121 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16492 /* 43125 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16493 /* 43129 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16494 /* 43133 */ // MIs[10] Operand 1
16495 /* 43133 */ // No operand predicates
16496 /* 43133 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16497 /* 43135 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16498 /* 43135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16499 /* 43138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16500 /* 43140 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16501 /* 43142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16502 /* 43146 */ GIR_RootConstrainSelectedInstOperands,
16503 /* 43147 */ // GIR_Coverage, 2653,
16504 /* 43147 */ GIR_EraseRootFromParent_Done,
16505 /* 43148 */ // Label 1216: @43148
16506 /* 43148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1217*/ GIMT_Encode4(43325), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2210 //
16507 /* 43155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16508 /* 43159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16509 /* 43163 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16510 /* 43167 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16511 /* 43171 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16512 /* 43175 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16513 /* 43179 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16514 /* 43182 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16515 /* 43186 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16516 /* 43190 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16517 /* 43194 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16518 /* 43198 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16519 /* 43202 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16520 /* 43206 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16521 /* 43210 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16522 /* 43214 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16523 /* 43218 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16524 /* 43222 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16525 /* 43226 */ // MIs[3] Operand 1
16526 /* 43226 */ // No operand predicates
16527 /* 43226 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16528 /* 43230 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16529 /* 43234 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16530 /* 43238 */ // MIs[4] Operand 1
16531 /* 43238 */ // No operand predicates
16532 /* 43238 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16533 /* 43242 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16534 /* 43246 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16535 /* 43250 */ // MIs[5] Operand 1
16536 /* 43250 */ // No operand predicates
16537 /* 43250 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16538 /* 43254 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16539 /* 43258 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16540 /* 43262 */ // MIs[6] Operand 1
16541 /* 43262 */ // No operand predicates
16542 /* 43262 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16543 /* 43266 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16544 /* 43270 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16545 /* 43274 */ // MIs[7] Operand 1
16546 /* 43274 */ // No operand predicates
16547 /* 43274 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16548 /* 43278 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16549 /* 43282 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16550 /* 43286 */ // MIs[8] Operand 1
16551 /* 43286 */ // No operand predicates
16552 /* 43286 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16553 /* 43290 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16554 /* 43294 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16555 /* 43298 */ // MIs[9] Operand 1
16556 /* 43298 */ // No operand predicates
16557 /* 43298 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16558 /* 43302 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16559 /* 43306 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16560 /* 43310 */ // MIs[10] Operand 1
16561 /* 43310 */ // No operand predicates
16562 /* 43310 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
16563 /* 43312 */ // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16564 /* 43312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16565 /* 43315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16566 /* 43317 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16567 /* 43319 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16568 /* 43323 */ GIR_RootConstrainSelectedInstOperands,
16569 /* 43324 */ // GIR_Coverage, 2210,
16570 /* 43324 */ GIR_EraseRootFromParent_Done,
16571 /* 43325 */ // Label 1217: @43325
16572 /* 43325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1218*/ GIMT_Encode4(43347), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1018 //
16573 /* 43332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16574 /* 43336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16575 /* 43340 */ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16576 /* 43340 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
16577 /* 43345 */ GIR_RootConstrainSelectedInstOperands,
16578 /* 43346 */ // GIR_Coverage, 1018,
16579 /* 43346 */ GIR_Done,
16580 /* 43347 */ // Label 1218: @43347
16581 /* 43347 */ GIM_Reject,
16582 /* 43348 */ // Label 1215: @43348
16583 /* 43348 */ GIM_Reject,
16584 /* 43349 */ // Label 1195: @43349
16585 /* 43349 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(43613),
16586 /* 43354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16587 /* 43357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16588 /* 43360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16589 /* 43364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1220*/ GIMT_Encode4(43477), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2654 //
16590 /* 43371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16591 /* 43375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16592 /* 43379 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16593 /* 43383 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16594 /* 43387 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16595 /* 43391 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16596 /* 43395 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16597 /* 43398 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16598 /* 43402 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16599 /* 43406 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16600 /* 43410 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16601 /* 43414 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16602 /* 43418 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16603 /* 43422 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16604 /* 43426 */ // MIs[3] Operand 1
16605 /* 43426 */ // No operand predicates
16606 /* 43426 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16607 /* 43430 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16608 /* 43434 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16609 /* 43438 */ // MIs[4] Operand 1
16610 /* 43438 */ // No operand predicates
16611 /* 43438 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16612 /* 43442 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16613 /* 43446 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16614 /* 43450 */ // MIs[5] Operand 1
16615 /* 43450 */ // No operand predicates
16616 /* 43450 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16617 /* 43454 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16618 /* 43458 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16619 /* 43462 */ // MIs[6] Operand 1
16620 /* 43462 */ // No operand predicates
16621 /* 43462 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16622 /* 43464 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16623 /* 43464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16624 /* 43467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16625 /* 43469 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16626 /* 43471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16627 /* 43475 */ GIR_RootConstrainSelectedInstOperands,
16628 /* 43476 */ // GIR_Coverage, 2654,
16629 /* 43476 */ GIR_EraseRootFromParent_Done,
16630 /* 43477 */ // Label 1220: @43477
16631 /* 43477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1221*/ GIMT_Encode4(43590), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2211 //
16632 /* 43484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16633 /* 43488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16634 /* 43492 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16635 /* 43496 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16636 /* 43500 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16637 /* 43504 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16638 /* 43508 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16639 /* 43511 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16640 /* 43515 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16641 /* 43519 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16642 /* 43523 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16643 /* 43527 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16644 /* 43531 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16645 /* 43535 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16646 /* 43539 */ // MIs[3] Operand 1
16647 /* 43539 */ // No operand predicates
16648 /* 43539 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16649 /* 43543 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16650 /* 43547 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16651 /* 43551 */ // MIs[4] Operand 1
16652 /* 43551 */ // No operand predicates
16653 /* 43551 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16654 /* 43555 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16655 /* 43559 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16656 /* 43563 */ // MIs[5] Operand 1
16657 /* 43563 */ // No operand predicates
16658 /* 43563 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16659 /* 43567 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16660 /* 43571 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16661 /* 43575 */ // MIs[6] Operand 1
16662 /* 43575 */ // No operand predicates
16663 /* 43575 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
16664 /* 43577 */ // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16665 /* 43577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16666 /* 43580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16667 /* 43582 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16668 /* 43584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16669 /* 43588 */ GIR_RootConstrainSelectedInstOperands,
16670 /* 43589 */ // GIR_Coverage, 2211,
16671 /* 43589 */ GIR_EraseRootFromParent_Done,
16672 /* 43590 */ // Label 1221: @43590
16673 /* 43590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1222*/ GIMT_Encode4(43612), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1019 //
16674 /* 43597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16675 /* 43601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16676 /* 43605 */ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16677 /* 43605 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
16678 /* 43610 */ GIR_RootConstrainSelectedInstOperands,
16679 /* 43611 */ // GIR_Coverage, 1019,
16680 /* 43611 */ GIR_Done,
16681 /* 43612 */ // Label 1222: @43612
16682 /* 43612 */ GIM_Reject,
16683 /* 43613 */ // Label 1219: @43613
16684 /* 43613 */ GIM_Reject,
16685 /* 43614 */ // Label 1196: @43614
16686 /* 43614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1223*/ GIMT_Encode4(43646), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1020 //
16687 /* 43621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16688 /* 43624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16689 /* 43627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16690 /* 43631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16691 /* 43635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16692 /* 43639 */ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16693 /* 43639 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
16694 /* 43644 */ GIR_RootConstrainSelectedInstOperands,
16695 /* 43645 */ // GIR_Coverage, 1020,
16696 /* 43645 */ GIR_Done,
16697 /* 43646 */ // Label 1223: @43646
16698 /* 43646 */ GIM_Reject,
16699 /* 43647 */ // Label 1197: @43647
16700 /* 43647 */ GIM_Reject,
16701 /* 43648 */ // Label 39: @43648
16702 /* 43648 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1230*/ GIMT_Encode4(45381),
16703 /* 43659 */ /*GILLT_s32*//*Label 1224*/ GIMT_Encode4(43691),
16704 /* 43663 */ /*GILLT_s64*//*Label 1225*/ GIMT_Encode4(43903), GIMT_Encode4(0),
16705 /* 43671 */ /*GILLT_v16s8*//*Label 1226*/ GIMT_Encode4(44041), GIMT_Encode4(0),
16706 /* 43679 */ /*GILLT_v8s16*//*Label 1227*/ GIMT_Encode4(44690),
16707 /* 43683 */ /*GILLT_v4s32*//*Label 1228*/ GIMT_Encode4(45083),
16708 /* 43687 */ /*GILLT_v2s64*//*Label 1229*/ GIMT_Encode4(45348),
16709 /* 43691 */ // Label 1224: @43691
16710 /* 43691 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(43902),
16711 /* 43696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16712 /* 43699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16713 /* 43702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1232*/ GIMT_Encode4(43743), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 59 //
16714 /* 43709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16715 /* 43713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16716 /* 43717 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16717 /* 43721 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16718 /* 43725 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16719 /* 43729 */ // MIs[1] Operand 1
16720 /* 43729 */ // No operand predicates
16721 /* 43729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16722 /* 43731 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16723 /* 43731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
16724 /* 43734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16725 /* 43736 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16726 /* 43738 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16727 /* 43741 */ GIR_RootConstrainSelectedInstOperands,
16728 /* 43742 */ // GIR_Coverage, 59,
16729 /* 43742 */ GIR_EraseRootFromParent_Done,
16730 /* 43743 */ // Label 1232: @43743
16731 /* 43743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1233*/ GIMT_Encode4(43784), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1967 //
16732 /* 43750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16733 /* 43754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16734 /* 43758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16735 /* 43762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16736 /* 43766 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16737 /* 43770 */ // MIs[1] Operand 1
16738 /* 43770 */ // No operand predicates
16739 /* 43770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16740 /* 43772 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16741 /* 43772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
16742 /* 43775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
16743 /* 43777 */ GIR_RootToRootCopy, /*OpIdx*/1, // in
16744 /* 43779 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16745 /* 43782 */ GIR_RootConstrainSelectedInstOperands,
16746 /* 43783 */ // GIR_Coverage, 1967,
16747 /* 43783 */ GIR_EraseRootFromParent_Done,
16748 /* 43784 */ // Label 1233: @43784
16749 /* 43784 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(43849),
16750 /* 43789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16751 /* 43793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16752 /* 43797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1235*/ GIMT_Encode4(43830), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2308 //
16753 /* 43804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16754 /* 43808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16755 /* 43812 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16756 /* 43816 */ // MIs[1] Operand 1
16757 /* 43816 */ // No operand predicates
16758 /* 43816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16759 /* 43818 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
16760 /* 43818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
16761 /* 43821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16762 /* 43823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
16763 /* 43825 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
16764 /* 43828 */ GIR_RootConstrainSelectedInstOperands,
16765 /* 43829 */ // GIR_Coverage, 2308,
16766 /* 43829 */ GIR_EraseRootFromParent_Done,
16767 /* 43830 */ // Label 1235: @43830
16768 /* 43830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1236*/ GIMT_Encode4(43848), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 65 //
16769 /* 43837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16770 /* 43841 */ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16771 /* 43841 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
16772 /* 43846 */ GIR_RootConstrainSelectedInstOperands,
16773 /* 43847 */ // GIR_Coverage, 65,
16774 /* 43847 */ GIR_Done,
16775 /* 43848 */ // Label 1236: @43848
16776 /* 43848 */ GIM_Reject,
16777 /* 43849 */ // Label 1234: @43849
16778 /* 43849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1237*/ GIMT_Encode4(43875), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1969 //
16779 /* 43856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16780 /* 43860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16781 /* 43864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16782 /* 43868 */ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
16783 /* 43868 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
16784 /* 43873 */ GIR_RootConstrainSelectedInstOperands,
16785 /* 43874 */ // GIR_Coverage, 1969,
16786 /* 43874 */ GIR_Done,
16787 /* 43875 */ // Label 1237: @43875
16788 /* 43875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1238*/ GIMT_Encode4(43901), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2309 //
16789 /* 43882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16790 /* 43886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16791 /* 43890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16792 /* 43894 */ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
16793 /* 43894 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
16794 /* 43899 */ GIR_RootConstrainSelectedInstOperands,
16795 /* 43900 */ // GIR_Coverage, 2309,
16796 /* 43900 */ GIR_Done,
16797 /* 43901 */ // Label 1238: @43901
16798 /* 43901 */ GIM_Reject,
16799 /* 43902 */ // Label 1231: @43902
16800 /* 43902 */ GIM_Reject,
16801 /* 43903 */ // Label 1225: @43903
16802 /* 43903 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(44040),
16803 /* 43908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16804 /* 43911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16805 /* 43914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16806 /* 43918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16807 /* 43922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1240*/ GIMT_Encode4(43955), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 242 //
16808 /* 43929 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16809 /* 43933 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16810 /* 43937 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16811 /* 43941 */ // MIs[1] Operand 1
16812 /* 43941 */ // No operand predicates
16813 /* 43941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16814 /* 43943 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16815 /* 43943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
16816 /* 43946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16817 /* 43948 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16818 /* 43950 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16819 /* 43953 */ GIR_RootConstrainSelectedInstOperands,
16820 /* 43954 */ // GIR_Coverage, 242,
16821 /* 43954 */ GIR_EraseRootFromParent_Done,
16822 /* 43955 */ // Label 1240: @43955
16823 /* 43955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1241*/ GIMT_Encode4(44021), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1684 //
16824 /* 43962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16825 /* 43966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16826 /* 43970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16827 /* 43974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16828 /* 43979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16829 /* 43981 */ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16830 /* 43981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16831 /* 43984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16832 /* 43988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16833 /* 43993 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16834 /* 43999 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16835 /* 44004 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16836 /* 44009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
16837 /* 44012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16838 /* 44014 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
16839 /* 44016 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16840 /* 44019 */ GIR_RootConstrainSelectedInstOperands,
16841 /* 44020 */ // GIR_Coverage, 1684,
16842 /* 44020 */ GIR_EraseRootFromParent_Done,
16843 /* 44021 */ // Label 1241: @44021
16844 /* 44021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1242*/ GIMT_Encode4(44039), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips), // Rule ID 246 //
16845 /* 44028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16846 /* 44032 */ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16847 /* 44032 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
16848 /* 44037 */ GIR_RootConstrainSelectedInstOperands,
16849 /* 44038 */ // GIR_Coverage, 246,
16850 /* 44038 */ GIR_Done,
16851 /* 44039 */ // Label 1242: @44039
16852 /* 44039 */ GIM_Reject,
16853 /* 44040 */ // Label 1239: @44040
16854 /* 44040 */ GIM_Reject,
16855 /* 44041 */ // Label 1226: @44041
16856 /* 44041 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(44689),
16857 /* 44046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16858 /* 44049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16859 /* 44052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16860 /* 44056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1244*/ GIMT_Encode4(44361), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2656 //
16861 /* 44063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16862 /* 44067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16863 /* 44071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16864 /* 44075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16865 /* 44079 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16866 /* 44083 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16867 /* 44087 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16868 /* 44090 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16869 /* 44094 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16870 /* 44098 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16871 /* 44102 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16872 /* 44106 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16873 /* 44110 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16874 /* 44114 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16875 /* 44118 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16876 /* 44122 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16877 /* 44126 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16878 /* 44130 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16879 /* 44134 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16880 /* 44138 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16881 /* 44142 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16882 /* 44146 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16883 /* 44150 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16884 /* 44154 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16885 /* 44158 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16886 /* 44162 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16887 /* 44166 */ // MIs[3] Operand 1
16888 /* 44166 */ // No operand predicates
16889 /* 44166 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16890 /* 44170 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16891 /* 44174 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16892 /* 44178 */ // MIs[4] Operand 1
16893 /* 44178 */ // No operand predicates
16894 /* 44178 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16895 /* 44182 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16896 /* 44186 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16897 /* 44190 */ // MIs[5] Operand 1
16898 /* 44190 */ // No operand predicates
16899 /* 44190 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16900 /* 44194 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16901 /* 44198 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16902 /* 44202 */ // MIs[6] Operand 1
16903 /* 44202 */ // No operand predicates
16904 /* 44202 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16905 /* 44206 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16906 /* 44210 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16907 /* 44214 */ // MIs[7] Operand 1
16908 /* 44214 */ // No operand predicates
16909 /* 44214 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16910 /* 44218 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16911 /* 44222 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16912 /* 44226 */ // MIs[8] Operand 1
16913 /* 44226 */ // No operand predicates
16914 /* 44226 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16915 /* 44230 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16916 /* 44234 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16917 /* 44238 */ // MIs[9] Operand 1
16918 /* 44238 */ // No operand predicates
16919 /* 44238 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16920 /* 44242 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16921 /* 44246 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16922 /* 44250 */ // MIs[10] Operand 1
16923 /* 44250 */ // No operand predicates
16924 /* 44250 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16925 /* 44254 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16926 /* 44258 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16927 /* 44262 */ // MIs[11] Operand 1
16928 /* 44262 */ // No operand predicates
16929 /* 44262 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16930 /* 44266 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16931 /* 44270 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16932 /* 44274 */ // MIs[12] Operand 1
16933 /* 44274 */ // No operand predicates
16934 /* 44274 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16935 /* 44278 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16936 /* 44282 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16937 /* 44286 */ // MIs[13] Operand 1
16938 /* 44286 */ // No operand predicates
16939 /* 44286 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16940 /* 44290 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16941 /* 44294 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16942 /* 44298 */ // MIs[14] Operand 1
16943 /* 44298 */ // No operand predicates
16944 /* 44298 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16945 /* 44302 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16946 /* 44306 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16947 /* 44310 */ // MIs[15] Operand 1
16948 /* 44310 */ // No operand predicates
16949 /* 44310 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16950 /* 44314 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16951 /* 44318 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16952 /* 44322 */ // MIs[16] Operand 1
16953 /* 44322 */ // No operand predicates
16954 /* 44322 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16955 /* 44326 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16956 /* 44330 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16957 /* 44334 */ // MIs[17] Operand 1
16958 /* 44334 */ // No operand predicates
16959 /* 44334 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16960 /* 44338 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16961 /* 44342 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16962 /* 44346 */ // MIs[18] Operand 1
16963 /* 44346 */ // No operand predicates
16964 /* 44346 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
16965 /* 44348 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16966 /* 44348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
16967 /* 44351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16968 /* 44353 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
16969 /* 44355 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16970 /* 44359 */ GIR_RootConstrainSelectedInstOperands,
16971 /* 44360 */ // GIR_Coverage, 2656,
16972 /* 44360 */ GIR_EraseRootFromParent_Done,
16973 /* 44361 */ // Label 1244: @44361
16974 /* 44361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(44666), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2213 //
16975 /* 44368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16976 /* 44372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16977 /* 44376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16978 /* 44380 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16979 /* 44384 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16980 /* 44388 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16981 /* 44392 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16982 /* 44395 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16983 /* 44399 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16984 /* 44403 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16985 /* 44407 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16986 /* 44411 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16987 /* 44415 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16988 /* 44419 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16989 /* 44423 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16990 /* 44427 */ GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16991 /* 44431 */ GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16992 /* 44435 */ GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16993 /* 44439 */ GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16994 /* 44443 */ GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16995 /* 44447 */ GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16996 /* 44451 */ GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16997 /* 44455 */ GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16998 /* 44459 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16999 /* 44463 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17000 /* 44467 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17001 /* 44471 */ // MIs[3] Operand 1
17002 /* 44471 */ // No operand predicates
17003 /* 44471 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17004 /* 44475 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17005 /* 44479 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17006 /* 44483 */ // MIs[4] Operand 1
17007 /* 44483 */ // No operand predicates
17008 /* 44483 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17009 /* 44487 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17010 /* 44491 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17011 /* 44495 */ // MIs[5] Operand 1
17012 /* 44495 */ // No operand predicates
17013 /* 44495 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17014 /* 44499 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17015 /* 44503 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17016 /* 44507 */ // MIs[6] Operand 1
17017 /* 44507 */ // No operand predicates
17018 /* 44507 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17019 /* 44511 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17020 /* 44515 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17021 /* 44519 */ // MIs[7] Operand 1
17022 /* 44519 */ // No operand predicates
17023 /* 44519 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17024 /* 44523 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17025 /* 44527 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17026 /* 44531 */ // MIs[8] Operand 1
17027 /* 44531 */ // No operand predicates
17028 /* 44531 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17029 /* 44535 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17030 /* 44539 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17031 /* 44543 */ // MIs[9] Operand 1
17032 /* 44543 */ // No operand predicates
17033 /* 44543 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17034 /* 44547 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17035 /* 44551 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17036 /* 44555 */ // MIs[10] Operand 1
17037 /* 44555 */ // No operand predicates
17038 /* 44555 */ GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
17039 /* 44559 */ GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17040 /* 44563 */ GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17041 /* 44567 */ // MIs[11] Operand 1
17042 /* 44567 */ // No operand predicates
17043 /* 44567 */ GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
17044 /* 44571 */ GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17045 /* 44575 */ GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17046 /* 44579 */ // MIs[12] Operand 1
17047 /* 44579 */ // No operand predicates
17048 /* 44579 */ GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
17049 /* 44583 */ GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17050 /* 44587 */ GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17051 /* 44591 */ // MIs[13] Operand 1
17052 /* 44591 */ // No operand predicates
17053 /* 44591 */ GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
17054 /* 44595 */ GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17055 /* 44599 */ GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17056 /* 44603 */ // MIs[14] Operand 1
17057 /* 44603 */ // No operand predicates
17058 /* 44603 */ GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
17059 /* 44607 */ GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17060 /* 44611 */ GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17061 /* 44615 */ // MIs[15] Operand 1
17062 /* 44615 */ // No operand predicates
17063 /* 44615 */ GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
17064 /* 44619 */ GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17065 /* 44623 */ GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17066 /* 44627 */ // MIs[16] Operand 1
17067 /* 44627 */ // No operand predicates
17068 /* 44627 */ GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
17069 /* 44631 */ GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17070 /* 44635 */ GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17071 /* 44639 */ // MIs[17] Operand 1
17072 /* 44639 */ // No operand predicates
17073 /* 44639 */ GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
17074 /* 44643 */ GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17075 /* 44647 */ GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
17076 /* 44651 */ // MIs[18] Operand 1
17077 /* 44651 */ // No operand predicates
17078 /* 44651 */ GIM_CheckIsSafeToFold, /*NumInsns*/18,
17079 /* 44653 */ // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
17080 /* 44653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17081 /* 44656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17082 /* 44658 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17083 /* 44660 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17084 /* 44664 */ GIR_RootConstrainSelectedInstOperands,
17085 /* 44665 */ // GIR_Coverage, 2213,
17086 /* 44665 */ GIR_EraseRootFromParent_Done,
17087 /* 44666 */ // Label 1245: @44666
17088 /* 44666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1246*/ GIMT_Encode4(44688), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1001 //
17089 /* 44673 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17090 /* 44677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
17091 /* 44681 */ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
17092 /* 44681 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
17093 /* 44686 */ GIR_RootConstrainSelectedInstOperands,
17094 /* 44687 */ // GIR_Coverage, 1001,
17095 /* 44687 */ GIR_Done,
17096 /* 44688 */ // Label 1246: @44688
17097 /* 44688 */ GIM_Reject,
17098 /* 44689 */ // Label 1243: @44689
17099 /* 44689 */ GIM_Reject,
17100 /* 44690 */ // Label 1227: @44690
17101 /* 44690 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(45082),
17102 /* 44695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
17103 /* 44698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17104 /* 44701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17105 /* 44705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1248*/ GIMT_Encode4(44882), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2657 //
17106 /* 44712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17107 /* 44716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17108 /* 44720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17109 /* 44724 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17110 /* 44728 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17111 /* 44732 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17112 /* 44736 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17113 /* 44739 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17114 /* 44743 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17115 /* 44747 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17116 /* 44751 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17117 /* 44755 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17118 /* 44759 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17119 /* 44763 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17120 /* 44767 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17121 /* 44771 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17122 /* 44775 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17123 /* 44779 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17124 /* 44783 */ // MIs[3] Operand 1
17125 /* 44783 */ // No operand predicates
17126 /* 44783 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17127 /* 44787 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17128 /* 44791 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17129 /* 44795 */ // MIs[4] Operand 1
17130 /* 44795 */ // No operand predicates
17131 /* 44795 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17132 /* 44799 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17133 /* 44803 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17134 /* 44807 */ // MIs[5] Operand 1
17135 /* 44807 */ // No operand predicates
17136 /* 44807 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17137 /* 44811 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17138 /* 44815 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17139 /* 44819 */ // MIs[6] Operand 1
17140 /* 44819 */ // No operand predicates
17141 /* 44819 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17142 /* 44823 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17143 /* 44827 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17144 /* 44831 */ // MIs[7] Operand 1
17145 /* 44831 */ // No operand predicates
17146 /* 44831 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17147 /* 44835 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17148 /* 44839 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17149 /* 44843 */ // MIs[8] Operand 1
17150 /* 44843 */ // No operand predicates
17151 /* 44843 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17152 /* 44847 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17153 /* 44851 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17154 /* 44855 */ // MIs[9] Operand 1
17155 /* 44855 */ // No operand predicates
17156 /* 44855 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17157 /* 44859 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17158 /* 44863 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17159 /* 44867 */ // MIs[10] Operand 1
17160 /* 44867 */ // No operand predicates
17161 /* 44867 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17162 /* 44869 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17163 /* 44869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17164 /* 44872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17165 /* 44874 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17166 /* 44876 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17167 /* 44880 */ GIR_RootConstrainSelectedInstOperands,
17168 /* 44881 */ // GIR_Coverage, 2657,
17169 /* 44881 */ GIR_EraseRootFromParent_Done,
17170 /* 44882 */ // Label 1248: @44882
17171 /* 44882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1249*/ GIMT_Encode4(45059), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2214 //
17172 /* 44889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17173 /* 44893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17174 /* 44897 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17175 /* 44901 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
17176 /* 44905 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17177 /* 44909 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17178 /* 44913 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
17179 /* 44916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17180 /* 44920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17181 /* 44924 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17182 /* 44928 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17183 /* 44932 */ GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
17184 /* 44936 */ GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
17185 /* 44940 */ GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
17186 /* 44944 */ GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
17187 /* 44948 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17188 /* 44952 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17189 /* 44956 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17190 /* 44960 */ // MIs[3] Operand 1
17191 /* 44960 */ // No operand predicates
17192 /* 44960 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17193 /* 44964 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17194 /* 44968 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17195 /* 44972 */ // MIs[4] Operand 1
17196 /* 44972 */ // No operand predicates
17197 /* 44972 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17198 /* 44976 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17199 /* 44980 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17200 /* 44984 */ // MIs[5] Operand 1
17201 /* 44984 */ // No operand predicates
17202 /* 44984 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17203 /* 44988 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17204 /* 44992 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17205 /* 44996 */ // MIs[6] Operand 1
17206 /* 44996 */ // No operand predicates
17207 /* 44996 */ GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
17208 /* 45000 */ GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17209 /* 45004 */ GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17210 /* 45008 */ // MIs[7] Operand 1
17211 /* 45008 */ // No operand predicates
17212 /* 45008 */ GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
17213 /* 45012 */ GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17214 /* 45016 */ GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17215 /* 45020 */ // MIs[8] Operand 1
17216 /* 45020 */ // No operand predicates
17217 /* 45020 */ GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
17218 /* 45024 */ GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17219 /* 45028 */ GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17220 /* 45032 */ // MIs[9] Operand 1
17221 /* 45032 */ // No operand predicates
17222 /* 45032 */ GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
17223 /* 45036 */ GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17224 /* 45040 */ GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
17225 /* 45044 */ // MIs[10] Operand 1
17226 /* 45044 */ // No operand predicates
17227 /* 45044 */ GIM_CheckIsSafeToFold, /*NumInsns*/10,
17228 /* 45046 */ // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
17229 /* 45046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17230 /* 45049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17231 /* 45051 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17232 /* 45053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17233 /* 45057 */ GIR_RootConstrainSelectedInstOperands,
17234 /* 45058 */ // GIR_Coverage, 2214,
17235 /* 45058 */ GIR_EraseRootFromParent_Done,
17236 /* 45059 */ // Label 1249: @45059
17237 /* 45059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1250*/ GIMT_Encode4(45081), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1002 //
17238 /* 45066 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17239 /* 45070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
17240 /* 45074 */ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
17241 /* 45074 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
17242 /* 45079 */ GIR_RootConstrainSelectedInstOperands,
17243 /* 45080 */ // GIR_Coverage, 1002,
17244 /* 45080 */ GIR_Done,
17245 /* 45081 */ // Label 1250: @45081
17246 /* 45081 */ GIM_Reject,
17247 /* 45082 */ // Label 1247: @45082
17248 /* 45082 */ GIM_Reject,
17249 /* 45083 */ // Label 1228: @45083
17250 /* 45083 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(45347),
17251 /* 45088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
17252 /* 45091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17253 /* 45094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17254 /* 45098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1252*/ GIMT_Encode4(45211), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2658 //
17255 /* 45105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17256 /* 45109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17257 /* 45113 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17258 /* 45117 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17259 /* 45121 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17260 /* 45125 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17261 /* 45129 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17262 /* 45132 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17263 /* 45136 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17264 /* 45140 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17265 /* 45144 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17266 /* 45148 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17267 /* 45152 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17268 /* 45156 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17269 /* 45160 */ // MIs[3] Operand 1
17270 /* 45160 */ // No operand predicates
17271 /* 45160 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17272 /* 45164 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17273 /* 45168 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17274 /* 45172 */ // MIs[4] Operand 1
17275 /* 45172 */ // No operand predicates
17276 /* 45172 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17277 /* 45176 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17278 /* 45180 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17279 /* 45184 */ // MIs[5] Operand 1
17280 /* 45184 */ // No operand predicates
17281 /* 45184 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17282 /* 45188 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17283 /* 45192 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17284 /* 45196 */ // MIs[6] Operand 1
17285 /* 45196 */ // No operand predicates
17286 /* 45196 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17287 /* 45198 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17288 /* 45198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17289 /* 45201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17290 /* 45203 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17291 /* 45205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
17292 /* 45209 */ GIR_RootConstrainSelectedInstOperands,
17293 /* 45210 */ // GIR_Coverage, 2658,
17294 /* 45210 */ GIR_EraseRootFromParent_Done,
17295 /* 45211 */ // Label 1252: @45211
17296 /* 45211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1253*/ GIMT_Encode4(45324), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2215 //
17297 /* 45218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17298 /* 45222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
17299 /* 45226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17300 /* 45230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
17301 /* 45234 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17302 /* 45238 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
17303 /* 45242 */ GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
17304 /* 45245 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
17305 /* 45249 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
17306 /* 45253 */ GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
17307 /* 45257 */ GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
17308 /* 45261 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
17309 /* 45265 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17310 /* 45269 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17311 /* 45273 */ // MIs[3] Operand 1
17312 /* 45273 */ // No operand predicates
17313 /* 45273 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
17314 /* 45277 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17315 /* 45281 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17316 /* 45285 */ // MIs[4] Operand 1
17317 /* 45285 */ // No operand predicates
17318 /* 45285 */ GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
17319 /* 45289 */ GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17320 /* 45293 */ GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17321 /* 45297 */ // MIs[5] Operand 1
17322 /* 45297 */ // No operand predicates
17323 /* 45297 */ GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
17324 /* 45301 */ GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17325 /* 45305 */ GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
17326 /* 45309 */ // MIs[6] Operand 1
17327 /* 45309 */ // No operand predicates
17328 /* 45309 */ GIM_CheckIsSafeToFold, /*NumInsns*/6,
17329 /* 45311 */ // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
17330 /* 45311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17331 /* 45314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
17332 /* 45316 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
17333 /* 45318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
17334 /* 45322 */ GIR_RootConstrainSelectedInstOperands,
17335 /* 45323 */ // GIR_Coverage, 2215,
17336 /* 45323 */ GIR_EraseRootFromParent_Done,
17337 /* 45324 */ // Label 1253: @45324
17338 /* 45324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1254*/ GIMT_Encode4(45346), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1003 //
17339 /* 45331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17340 /* 45335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
17341 /* 45339 */ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
17342 /* 45339 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
17343 /* 45344 */ GIR_RootConstrainSelectedInstOperands,
17344 /* 45345 */ // GIR_Coverage, 1003,
17345 /* 45345 */ GIR_Done,
17346 /* 45346 */ // Label 1254: @45346
17347 /* 45346 */ GIM_Reject,
17348 /* 45347 */ // Label 1251: @45347
17349 /* 45347 */ GIM_Reject,
17350 /* 45348 */ // Label 1229: @45348
17351 /* 45348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1255*/ GIMT_Encode4(45380), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1004 //
17352 /* 45355 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
17353 /* 45358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
17354 /* 45361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17355 /* 45365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17356 /* 45369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
17357 /* 45373 */ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
17358 /* 45373 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
17359 /* 45378 */ GIR_RootConstrainSelectedInstOperands,
17360 /* 45379 */ // GIR_Coverage, 1004,
17361 /* 45379 */ GIR_Done,
17362 /* 45380 */ // Label 1255: @45380
17363 /* 45380 */ GIM_Reject,
17364 /* 45381 */ // Label 1230: @45381
17365 /* 45381 */ GIM_Reject,
17366 /* 45382 */ // Label 40: @45382
17367 /* 45382 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1258*/ GIMT_Encode4(45664),
17368 /* 45393 */ /*GILLT_s32*//*Label 1256*/ GIMT_Encode4(45401),
17369 /* 45397 */ /*GILLT_s64*//*Label 1257*/ GIMT_Encode4(45526),
17370 /* 45401 */ // Label 1256: @45401
17371 /* 45401 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(45525),
17372 /* 45406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
17373 /* 45409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17374 /* 45412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17375 /* 45416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17376 /* 45420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1260*/ GIMT_Encode4(45453), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 67 //
17377 /* 45427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17378 /* 45431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17379 /* 45435 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17380 /* 45439 */ // MIs[1] Operand 1
17381 /* 45439 */ // No operand predicates
17382 /* 45439 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17383 /* 45441 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17384 /* 45441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
17385 /* 45444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17386 /* 45446 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17387 /* 45448 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17388 /* 45451 */ GIR_RootConstrainSelectedInstOperands,
17389 /* 45452 */ // GIR_Coverage, 67,
17390 /* 45452 */ GIR_EraseRootFromParent_Done,
17391 /* 45453 */ // Label 1260: @45453
17392 /* 45453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1261*/ GIMT_Encode4(45486), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1103 //
17393 /* 45460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17394 /* 45464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17395 /* 45468 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
17396 /* 45472 */ // MIs[1] Operand 1
17397 /* 45472 */ // No operand predicates
17398 /* 45472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17399 /* 45474 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
17400 /* 45474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
17401 /* 45477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17402 /* 45479 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17403 /* 45481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17404 /* 45484 */ GIR_RootConstrainSelectedInstOperands,
17405 /* 45485 */ // GIR_Coverage, 1103,
17406 /* 45485 */ GIR_EraseRootFromParent_Done,
17407 /* 45486 */ // Label 1261: @45486
17408 /* 45486 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(45524),
17409 /* 45491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17410 /* 45495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(45509), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 68 //
17411 /* 45502 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17412 /* 45502 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
17413 /* 45507 */ GIR_RootConstrainSelectedInstOperands,
17414 /* 45508 */ // GIR_Coverage, 68,
17415 /* 45508 */ GIR_Done,
17416 /* 45509 */ // Label 1263: @45509
17417 /* 45509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1264*/ GIMT_Encode4(45523), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1104 //
17418 /* 45516 */ // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17419 /* 45516 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
17420 /* 45521 */ GIR_RootConstrainSelectedInstOperands,
17421 /* 45522 */ // GIR_Coverage, 1104,
17422 /* 45522 */ GIR_Done,
17423 /* 45523 */ // Label 1264: @45523
17424 /* 45523 */ GIM_Reject,
17425 /* 45524 */ // Label 1262: @45524
17426 /* 45524 */ GIM_Reject,
17427 /* 45525 */ // Label 1259: @45525
17428 /* 45525 */ GIM_Reject,
17429 /* 45526 */ // Label 1257: @45526
17430 /* 45526 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(45663),
17431 /* 45531 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
17432 /* 45534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17433 /* 45537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17434 /* 45541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17435 /* 45545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1266*/ GIMT_Encode4(45578), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 250 //
17436 /* 45552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17437 /* 45556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17438 /* 45560 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
17439 /* 45564 */ // MIs[1] Operand 1
17440 /* 45564 */ // No operand predicates
17441 /* 45564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17442 /* 45566 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
17443 /* 45566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
17444 /* 45569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17445 /* 45571 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17446 /* 45573 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
17447 /* 45576 */ GIR_RootConstrainSelectedInstOperands,
17448 /* 45577 */ // GIR_Coverage, 250,
17449 /* 45577 */ GIR_EraseRootFromParent_Done,
17450 /* 45578 */ // Label 1266: @45578
17451 /* 45578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1267*/ GIMT_Encode4(45644), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit), // Rule ID 1685 //
17452 /* 45585 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17453 /* 45589 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
17454 /* 45593 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
17455 /* 45597 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17456 /* 45602 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17457 /* 45604 */ // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
17458 /* 45604 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17459 /* 45607 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17460 /* 45611 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17461 /* 45616 */ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
17462 /* 45622 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
17463 /* 45627 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
17464 /* 45632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17465 /* 45635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17466 /* 45637 */ GIR_RootToRootCopy, /*OpIdx*/1, // rt
17467 /* 45639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17468 /* 45642 */ GIR_RootConstrainSelectedInstOperands,
17469 /* 45643 */ // GIR_Coverage, 1685,
17470 /* 45643 */ GIR_EraseRootFromParent_Done,
17471 /* 45644 */ // Label 1267: @45644
17472 /* 45644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1268*/ GIMT_Encode4(45662), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips), // Rule ID 251 //
17473 /* 45651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17474 /* 45655 */ // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
17475 /* 45655 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
17476 /* 45660 */ GIR_RootConstrainSelectedInstOperands,
17477 /* 45661 */ // GIR_Coverage, 251,
17478 /* 45661 */ GIR_Done,
17479 /* 45662 */ // Label 1268: @45662
17480 /* 45662 */ GIM_Reject,
17481 /* 45663 */ // Label 1265: @45663
17482 /* 45663 */ GIM_Reject,
17483 /* 45664 */ // Label 1258: @45664
17484 /* 45664 */ GIM_Reject,
17485 /* 45665 */ // Label 41: @45665
17486 /* 45665 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(48158),
17487 /* 45670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17488 /* 45673 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1272*/ GIMT_Encode4(48157),
17489 /* 45684 */ /*GILLT_s32*//*Label 1270*/ GIMT_Encode4(45692),
17490 /* 45688 */ /*GILLT_s64*//*Label 1271*/ GIMT_Encode4(47619),
17491 /* 45692 */ // Label 1270: @45692
17492 /* 45692 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(47618),
17493 /* 45697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17494 /* 45700 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(45930),
17495 /* 45705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17496 /* 45709 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(45862),
17497 /* 45714 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17498 /* 45719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17499 /* 45723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1276*/ GIMT_Encode4(45792), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsNotSingleFloat_NotFP64bit), // Rule ID 1521 //
17500 /* 45730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17501 /* 45734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
17502 /* 45738 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17503 /* 45742 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17504 /* 45746 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17505 /* 45750 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
17506 /* 45754 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
17507 /* 45759 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17508 /* 45761 */ // (setcc:{ *:[i32] } (bitconvert:{ *:[i32] } (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)), 0:{ *:[i32] }, SETLT:{ *:[Other] }) => (SLTi:{ *:[i32] } (MFHC1_D32:{ *:[i32] } AFGR64Opnd:{ *:[f64] }:$src), 0:{ *:[i32] })
17509 /* 45761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17510 /* 45764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::MFHC1_D32),
17511 /* 45768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17512 /* 45773 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src
17513 /* 45777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17514 /* 45779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTi),
17515 /* 45782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17516 /* 45784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17517 /* 45787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17518 /* 45790 */ GIR_RootConstrainSelectedInstOperands,
17519 /* 45791 */ // GIR_Coverage, 1521,
17520 /* 45791 */ GIR_EraseRootFromParent_Done,
17521 /* 45792 */ // Label 1276: @45792
17522 /* 45792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1277*/ GIMT_Encode4(45861), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat), // Rule ID 1522 //
17523 /* 45799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17524 /* 45803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
17525 /* 45807 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17526 /* 45811 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
17527 /* 45815 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
17528 /* 45819 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
17529 /* 45823 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17530 /* 45828 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17531 /* 45830 */ // (setcc:{ *:[i32] } (bitconvert:{ *:[i32] } (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)), 0:{ *:[i32] }, SETLT:{ *:[Other] }) => (SLTi:{ *:[i32] } (MFHC1_D64:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$src), 0:{ *:[i32] })
17532 /* 45830 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17533 /* 45833 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::MFHC1_D64),
17534 /* 45837 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17535 /* 45842 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // src
17536 /* 45846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17537 /* 45848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTi),
17538 /* 45851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17539 /* 45853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17540 /* 45856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17541 /* 45859 */ GIR_RootConstrainSelectedInstOperands,
17542 /* 45860 */ // GIR_Coverage, 1522,
17543 /* 45860 */ GIR_EraseRootFromParent_Done,
17544 /* 45861 */ // Label 1277: @45861
17545 /* 45861 */ GIM_Reject,
17546 /* 45862 */ // Label 1275: @45862
17547 /* 45862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1278*/ GIMT_Encode4(45894), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1437 //
17548 /* 45869 */ // MIs[0] Operand 1
17549 /* 45869 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17550 /* 45874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17551 /* 45878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17552 /* 45882 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17553 /* 45882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
17554 /* 45885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17555 /* 45887 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17556 /* 45889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17557 /* 45892 */ GIR_RootConstrainSelectedInstOperands,
17558 /* 45893 */ // GIR_Coverage, 1437,
17559 /* 45893 */ GIR_EraseRootFromParent_Done,
17560 /* 45894 */ // Label 1278: @45894
17561 /* 45894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1279*/ GIMT_Encode4(45929), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1438 //
17562 /* 45901 */ // MIs[0] Operand 1
17563 /* 45901 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17564 /* 45906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17565 /* 45910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17566 /* 45914 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17567 /* 45914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17568 /* 45917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17569 /* 45919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17570 /* 45925 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17571 /* 45927 */ GIR_RootConstrainSelectedInstOperands,
17572 /* 45928 */ // GIR_Coverage, 1438,
17573 /* 45928 */ GIR_EraseRootFromParent_Done,
17574 /* 45929 */ // Label 1279: @45929
17575 /* 45929 */ GIM_Reject,
17576 /* 45930 */ // Label 1274: @45930
17577 /* 45930 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(46057),
17578 /* 45935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17579 /* 45939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1281*/ GIMT_Encode4(45971), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2017 //
17580 /* 45946 */ // MIs[0] Operand 1
17581 /* 45946 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17582 /* 45951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17583 /* 45955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17584 /* 45959 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17585 /* 45959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17586 /* 45962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17587 /* 45964 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17588 /* 45966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17589 /* 45969 */ GIR_RootConstrainSelectedInstOperands,
17590 /* 45970 */ // GIR_Coverage, 2017,
17591 /* 45970 */ GIR_EraseRootFromParent_Done,
17592 /* 45971 */ // Label 1281: @45971
17593 /* 45971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1282*/ GIMT_Encode4(46056), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2019 //
17594 /* 45978 */ // MIs[0] Operand 1
17595 /* 45978 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17596 /* 45983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17597 /* 45987 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709518847u),
17598 /* 45998 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17599 /* 45998 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17600 /* 46001 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17601 /* 46005 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17602 /* 46010 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17603 /* 46013 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17604 /* 46015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17605 /* 46018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
17606 /* 46022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17607 /* 46027 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17608 /* 46031 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
17609 /* 46041 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17610 /* 46043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17611 /* 46046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17612 /* 46048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17613 /* 46051 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17614 /* 46054 */ GIR_RootConstrainSelectedInstOperands,
17615 /* 46055 */ // GIR_Coverage, 2019,
17616 /* 46055 */ GIR_EraseRootFromParent_Done,
17617 /* 46056 */ // Label 1282: @46056
17618 /* 46056 */ GIM_Reject,
17619 /* 46057 */ // Label 1280: @46057
17620 /* 46057 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(46196),
17621 /* 46062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17622 /* 46066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1284*/ GIMT_Encode4(46098), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2336 //
17623 /* 46073 */ // MIs[0] Operand 1
17624 /* 46073 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17625 /* 46078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17626 /* 46082 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17627 /* 46086 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
17628 /* 46086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
17629 /* 46089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17630 /* 46091 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17631 /* 46093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17632 /* 46096 */ GIR_RootConstrainSelectedInstOperands,
17633 /* 46097 */ // GIR_Coverage, 2336,
17634 /* 46097 */ GIR_EraseRootFromParent_Done,
17635 /* 46098 */ // Label 1284: @46098
17636 /* 46098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1285*/ GIMT_Encode4(46133), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2337 //
17637 /* 46105 */ // MIs[0] Operand 1
17638 /* 46105 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17639 /* 46110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17640 /* 46114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17641 /* 46118 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
17642 /* 46118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17643 /* 46121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17644 /* 46123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17645 /* 46129 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17646 /* 46131 */ GIR_RootConstrainSelectedInstOperands,
17647 /* 46132 */ // GIR_Coverage, 2337,
17648 /* 46132 */ GIR_EraseRootFromParent_Done,
17649 /* 46133 */ // Label 1285: @46133
17650 /* 46133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1286*/ GIMT_Encode4(46164), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 49 //
17651 /* 46140 */ // MIs[0] Operand 1
17652 /* 46140 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17653 /* 46145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17654 /* 46149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17655 /* 46153 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17656 /* 46153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17657 /* 46156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17658 /* 46158 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17659 /* 46160 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17660 /* 46162 */ GIR_RootConstrainSelectedInstOperands,
17661 /* 46163 */ // GIR_Coverage, 49,
17662 /* 46163 */ GIR_EraseRootFromParent_Done,
17663 /* 46164 */ // Label 1286: @46164
17664 /* 46164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(46195), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 50 //
17665 /* 46171 */ // MIs[0] Operand 1
17666 /* 46171 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
17667 /* 46176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17668 /* 46180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17669 /* 46184 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17670 /* 46184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17671 /* 46187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17672 /* 46189 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17673 /* 46191 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17674 /* 46193 */ GIR_RootConstrainSelectedInstOperands,
17675 /* 46194 */ // GIR_Coverage, 50,
17676 /* 46194 */ GIR_EraseRootFromParent_Done,
17677 /* 46195 */ // Label 1287: @46195
17678 /* 46195 */ GIM_Reject,
17679 /* 46196 */ // Label 1283: @46196
17680 /* 46196 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(46663),
17681 /* 46201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17682 /* 46205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1289*/ GIMT_Encode4(46236), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1097 //
17683 /* 46212 */ // MIs[0] Operand 1
17684 /* 46212 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17685 /* 46217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17686 /* 46221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17687 /* 46225 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17688 /* 46225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
17689 /* 46228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17690 /* 46230 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17691 /* 46232 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17692 /* 46234 */ GIR_RootConstrainSelectedInstOperands,
17693 /* 46235 */ // GIR_Coverage, 1097,
17694 /* 46235 */ GIR_EraseRootFromParent_Done,
17695 /* 46236 */ // Label 1289: @46236
17696 /* 46236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1290*/ GIMT_Encode4(46267), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1098 //
17697 /* 46243 */ // MIs[0] Operand 1
17698 /* 46243 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
17699 /* 46248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17700 /* 46252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17701 /* 46256 */ // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
17702 /* 46256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17703 /* 46259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17704 /* 46261 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
17705 /* 46263 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
17706 /* 46265 */ GIR_RootConstrainSelectedInstOperands,
17707 /* 46266 */ // GIR_Coverage, 1098,
17708 /* 46266 */ GIR_EraseRootFromParent_Done,
17709 /* 46267 */ // Label 1290: @46267
17710 /* 46267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1291*/ GIMT_Encode4(46322), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1439 //
17711 /* 46274 */ // MIs[0] Operand 1
17712 /* 46274 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17713 /* 46279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17714 /* 46283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17715 /* 46287 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17716 /* 46287 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17717 /* 46290 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
17718 /* 46294 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17719 /* 46299 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17720 /* 46303 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17721 /* 46307 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17722 /* 46309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
17723 /* 46312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17724 /* 46314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17725 /* 46317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17726 /* 46320 */ GIR_RootConstrainSelectedInstOperands,
17727 /* 46321 */ // GIR_Coverage, 1439,
17728 /* 46321 */ GIR_EraseRootFromParent_Done,
17729 /* 46322 */ // Label 1291: @46322
17730 /* 46322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1292*/ GIMT_Encode4(46380), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1440 //
17731 /* 46329 */ // MIs[0] Operand 1
17732 /* 46329 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17733 /* 46334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17734 /* 46338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17735 /* 46342 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
17736 /* 46342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17737 /* 46345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
17738 /* 46349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17739 /* 46354 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17740 /* 46358 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17741 /* 46362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17742 /* 46364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17743 /* 46367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17744 /* 46369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17745 /* 46375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17746 /* 46378 */ GIR_RootConstrainSelectedInstOperands,
17747 /* 46379 */ // GIR_Coverage, 1440,
17748 /* 46379 */ GIR_EraseRootFromParent_Done,
17749 /* 46380 */ // Label 1292: @46380
17750 /* 46380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1293*/ GIMT_Encode4(46435), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1441 //
17751 /* 46387 */ // MIs[0] Operand 1
17752 /* 46387 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17753 /* 46392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17754 /* 46396 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17755 /* 46400 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17756 /* 46400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17757 /* 46403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
17758 /* 46407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17759 /* 46412 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17760 /* 46416 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17761 /* 46420 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17762 /* 46422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17763 /* 46425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17764 /* 46427 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17765 /* 46430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17766 /* 46433 */ GIR_RootConstrainSelectedInstOperands,
17767 /* 46434 */ // GIR_Coverage, 1441,
17768 /* 46434 */ GIR_EraseRootFromParent_Done,
17769 /* 46435 */ // Label 1293: @46435
17770 /* 46435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1294*/ GIMT_Encode4(46490), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1442 //
17771 /* 46442 */ // MIs[0] Operand 1
17772 /* 46442 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17773 /* 46447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17774 /* 46451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17775 /* 46455 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17776 /* 46455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17777 /* 46458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17778 /* 46462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17779 /* 46467 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17780 /* 46471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17781 /* 46475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17782 /* 46477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17783 /* 46480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17784 /* 46482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17785 /* 46485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17786 /* 46488 */ GIR_RootConstrainSelectedInstOperands,
17787 /* 46489 */ // GIR_Coverage, 1442,
17788 /* 46489 */ GIR_EraseRootFromParent_Done,
17789 /* 46490 */ // Label 1294: @46490
17790 /* 46490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1295*/ GIMT_Encode4(46521), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1443 //
17791 /* 46497 */ // MIs[0] Operand 1
17792 /* 46497 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17793 /* 46502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17794 /* 46506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17795 /* 46510 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17796 /* 46510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17797 /* 46513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17798 /* 46515 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17799 /* 46517 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17800 /* 46519 */ GIR_RootConstrainSelectedInstOperands,
17801 /* 46520 */ // GIR_Coverage, 1443,
17802 /* 46520 */ GIR_EraseRootFromParent_Done,
17803 /* 46521 */ // Label 1295: @46521
17804 /* 46521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1296*/ GIMT_Encode4(46552), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1444 //
17805 /* 46528 */ // MIs[0] Operand 1
17806 /* 46528 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17807 /* 46533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17808 /* 46537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17809 /* 46541 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17810 /* 46541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17811 /* 46544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17812 /* 46546 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17813 /* 46548 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17814 /* 46550 */ GIR_RootConstrainSelectedInstOperands,
17815 /* 46551 */ // GIR_Coverage, 1444,
17816 /* 46551 */ GIR_EraseRootFromParent_Done,
17817 /* 46552 */ // Label 1296: @46552
17818 /* 46552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1297*/ GIMT_Encode4(46607), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1445 //
17819 /* 46559 */ // MIs[0] Operand 1
17820 /* 46559 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17821 /* 46564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17822 /* 46568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17823 /* 46572 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17824 /* 46572 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17825 /* 46575 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
17826 /* 46579 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17827 /* 46584 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17828 /* 46588 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17829 /* 46592 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17830 /* 46594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17831 /* 46597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17832 /* 46599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17833 /* 46602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17834 /* 46605 */ GIR_RootConstrainSelectedInstOperands,
17835 /* 46606 */ // GIR_Coverage, 1445,
17836 /* 46606 */ GIR_EraseRootFromParent_Done,
17837 /* 46607 */ // Label 1297: @46607
17838 /* 46607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1298*/ GIMT_Encode4(46662), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 1446 //
17839 /* 46614 */ // MIs[0] Operand 1
17840 /* 46614 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17841 /* 46619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17842 /* 46623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17843 /* 46627 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17844 /* 46627 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17845 /* 46630 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17846 /* 46634 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17847 /* 46639 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17848 /* 46643 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17849 /* 46647 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17850 /* 46649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17851 /* 46652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17852 /* 46654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17853 /* 46657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17854 /* 46660 */ GIR_RootConstrainSelectedInstOperands,
17855 /* 46661 */ // GIR_Coverage, 1446,
17856 /* 46661 */ GIR_EraseRootFromParent_Done,
17857 /* 46662 */ // Label 1298: @46662
17858 /* 46662 */ GIM_Reject,
17859 /* 46663 */ // Label 1288: @46663
17860 /* 46663 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(47212),
17861 /* 46668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17862 /* 46672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1300*/ GIMT_Encode4(46727), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2016 //
17863 /* 46679 */ // MIs[0] Operand 1
17864 /* 46679 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17865 /* 46684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17866 /* 46688 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17867 /* 46692 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17868 /* 46692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17869 /* 46695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17870 /* 46699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17871 /* 46704 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17872 /* 46708 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17873 /* 46712 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17874 /* 46714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17875 /* 46717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17876 /* 46719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17877 /* 46722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17878 /* 46725 */ GIR_RootConstrainSelectedInstOperands,
17879 /* 46726 */ // GIR_Coverage, 2016,
17880 /* 46726 */ GIR_EraseRootFromParent_Done,
17881 /* 46727 */ // Label 1300: @46727
17882 /* 46727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1301*/ GIMT_Encode4(46799), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2018 //
17883 /* 46734 */ // MIs[0] Operand 1
17884 /* 46734 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17885 /* 46739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17886 /* 46743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17887 /* 46747 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17888 /* 46747 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17889 /* 46750 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17890 /* 46754 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17891 /* 46759 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17892 /* 46762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17893 /* 46764 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17894 /* 46767 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17895 /* 46771 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17896 /* 46776 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17897 /* 46780 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17898 /* 46784 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17899 /* 46786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17900 /* 46789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17901 /* 46791 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17902 /* 46794 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17903 /* 46797 */ GIR_RootConstrainSelectedInstOperands,
17904 /* 46798 */ // GIR_Coverage, 2018,
17905 /* 46798 */ GIR_EraseRootFromParent_Done,
17906 /* 46799 */ // Label 1301: @46799
17907 /* 46799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1302*/ GIMT_Encode4(46830), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2020 //
17908 /* 46806 */ // MIs[0] Operand 1
17909 /* 46806 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17910 /* 46811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17911 /* 46815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17912 /* 46819 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
17913 /* 46819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17914 /* 46822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17915 /* 46824 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17916 /* 46826 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17917 /* 46828 */ GIR_RootConstrainSelectedInstOperands,
17918 /* 46829 */ // GIR_Coverage, 2020,
17919 /* 46829 */ GIR_EraseRootFromParent_Done,
17920 /* 46830 */ // Label 1302: @46830
17921 /* 46830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1303*/ GIMT_Encode4(46902), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2021 //
17922 /* 46837 */ // MIs[0] Operand 1
17923 /* 46837 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17924 /* 46842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17925 /* 46846 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17926 /* 46850 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
17927 /* 46850 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17928 /* 46853 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
17929 /* 46857 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17930 /* 46862 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17931 /* 46865 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17932 /* 46867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17933 /* 46870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17934 /* 46874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17935 /* 46879 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17936 /* 46883 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17937 /* 46887 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17938 /* 46889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17939 /* 46892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17940 /* 46894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17941 /* 46897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17942 /* 46900 */ GIR_RootConstrainSelectedInstOperands,
17943 /* 46901 */ // GIR_Coverage, 2021,
17944 /* 46901 */ GIR_EraseRootFromParent_Done,
17945 /* 46902 */ // Label 1303: @46902
17946 /* 46902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1304*/ GIMT_Encode4(46933), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2022 //
17947 /* 46909 */ // MIs[0] Operand 1
17948 /* 46909 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17949 /* 46914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17950 /* 46918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17951 /* 46922 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
17952 /* 46922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17953 /* 46925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17954 /* 46927 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
17955 /* 46929 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
17956 /* 46931 */ GIR_RootConstrainSelectedInstOperands,
17957 /* 46932 */ // GIR_Coverage, 2022,
17958 /* 46932 */ GIR_EraseRootFromParent_Done,
17959 /* 46933 */ // Label 1304: @46933
17960 /* 46933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(47005), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2024 //
17961 /* 46940 */ // MIs[0] Operand 1
17962 /* 46940 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17963 /* 46945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17964 /* 46949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17965 /* 46953 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
17966 /* 46953 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17967 /* 46956 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17968 /* 46960 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17969 /* 46965 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17970 /* 46969 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17971 /* 46973 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17972 /* 46975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17973 /* 46978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17974 /* 46982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17975 /* 46987 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
17976 /* 46990 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17977 /* 46992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17978 /* 46995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17979 /* 46997 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17980 /* 47000 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17981 /* 47003 */ GIR_RootConstrainSelectedInstOperands,
17982 /* 47004 */ // GIR_Coverage, 2024,
17983 /* 47004 */ GIR_EraseRootFromParent_Done,
17984 /* 47005 */ // Label 1305: @47005
17985 /* 47005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1306*/ GIMT_Encode4(47077), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2025 //
17986 /* 47012 */ // MIs[0] Operand 1
17987 /* 47012 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17988 /* 47017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17989 /* 47021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17990 /* 47025 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17991 /* 47025 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17992 /* 47028 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17993 /* 47032 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17994 /* 47037 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17995 /* 47040 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17996 /* 47042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17997 /* 47045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17998 /* 47049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17999 /* 47054 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18000 /* 47058 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18001 /* 47062 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18002 /* 47064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18003 /* 47067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18004 /* 47069 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18005 /* 47072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18006 /* 47075 */ GIR_RootConstrainSelectedInstOperands,
18007 /* 47076 */ // GIR_Coverage, 2025,
18008 /* 47076 */ GIR_EraseRootFromParent_Done,
18009 /* 47077 */ // Label 1306: @47077
18010 /* 47077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1307*/ GIMT_Encode4(47108), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2026 //
18011 /* 47084 */ // MIs[0] Operand 1
18012 /* 47084 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18013 /* 47089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18014 /* 47093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18015 /* 47097 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
18016 /* 47097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18017 /* 47100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18018 /* 47102 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18019 /* 47104 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18020 /* 47106 */ GIR_RootConstrainSelectedInstOperands,
18021 /* 47107 */ // GIR_Coverage, 2026,
18022 /* 47107 */ GIR_EraseRootFromParent_Done,
18023 /* 47108 */ // Label 1307: @47108
18024 /* 47108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1308*/ GIMT_Encode4(47180), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2027 //
18025 /* 47115 */ // MIs[0] Operand 1
18026 /* 47115 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18027 /* 47120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18028 /* 47124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18029 /* 47128 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
18030 /* 47128 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
18031 /* 47131 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
18032 /* 47135 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18033 /* 47140 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
18034 /* 47143 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
18035 /* 47145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18036 /* 47148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18037 /* 47152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18038 /* 47157 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18039 /* 47161 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18040 /* 47165 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18041 /* 47167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
18042 /* 47170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
18043 /* 47172 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18044 /* 47175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
18045 /* 47178 */ GIR_RootConstrainSelectedInstOperands,
18046 /* 47179 */ // GIR_Coverage, 2027,
18047 /* 47179 */ GIR_EraseRootFromParent_Done,
18048 /* 47180 */ // Label 1308: @47180
18049 /* 47180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1309*/ GIMT_Encode4(47211), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2028 //
18050 /* 47187 */ // MIs[0] Operand 1
18051 /* 47187 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18052 /* 47192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18053 /* 47196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18054 /* 47200 */ // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
18055 /* 47200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
18056 /* 47203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
18057 /* 47205 */ GIR_RootToRootCopy, /*OpIdx*/2, // rx
18058 /* 47207 */ GIR_RootToRootCopy, /*OpIdx*/3, // ry
18059 /* 47209 */ GIR_RootConstrainSelectedInstOperands,
18060 /* 47210 */ // GIR_Coverage, 2028,
18061 /* 47210 */ GIR_EraseRootFromParent_Done,
18062 /* 47211 */ // Label 1309: @47211
18063 /* 47211 */ GIM_Reject,
18064 /* 47212 */ // Label 1299: @47212
18065 /* 47212 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(47617),
18066 /* 47217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18067 /* 47221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1311*/ GIMT_Encode4(47276), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2338 //
18068 /* 47228 */ // MIs[0] Operand 1
18069 /* 47228 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18070 /* 47233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18071 /* 47237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18072 /* 47241 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18073 /* 47241 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18074 /* 47244 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18075 /* 47248 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18076 /* 47253 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18077 /* 47257 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18078 /* 47261 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18079 /* 47263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
18080 /* 47266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18081 /* 47268 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18082 /* 47271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18083 /* 47274 */ GIR_RootConstrainSelectedInstOperands,
18084 /* 47275 */ // GIR_Coverage, 2338,
18085 /* 47275 */ GIR_EraseRootFromParent_Done,
18086 /* 47276 */ // Label 1311: @47276
18087 /* 47276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1312*/ GIMT_Encode4(47334), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2339 //
18088 /* 47283 */ // MIs[0] Operand 1
18089 /* 47283 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18090 /* 47288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18091 /* 47292 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18092 /* 47296 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
18093 /* 47296 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18094 /* 47299 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
18095 /* 47303 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18096 /* 47308 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18097 /* 47312 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18098 /* 47316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18099 /* 47318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18100 /* 47321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18101 /* 47323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18102 /* 47329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18103 /* 47332 */ GIR_RootConstrainSelectedInstOperands,
18104 /* 47333 */ // GIR_Coverage, 2339,
18105 /* 47333 */ GIR_EraseRootFromParent_Done,
18106 /* 47334 */ // Label 1312: @47334
18107 /* 47334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1313*/ GIMT_Encode4(47389), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2340 //
18108 /* 47341 */ // MIs[0] Operand 1
18109 /* 47341 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18110 /* 47346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18111 /* 47350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18112 /* 47354 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18113 /* 47354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18114 /* 47357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18115 /* 47361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18116 /* 47366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18117 /* 47370 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18118 /* 47374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18119 /* 47376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18120 /* 47379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18121 /* 47381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18122 /* 47384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18123 /* 47387 */ GIR_RootConstrainSelectedInstOperands,
18124 /* 47388 */ // GIR_Coverage, 2340,
18125 /* 47388 */ GIR_EraseRootFromParent_Done,
18126 /* 47389 */ // Label 1313: @47389
18127 /* 47389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1314*/ GIMT_Encode4(47444), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2341 //
18128 /* 47396 */ // MIs[0] Operand 1
18129 /* 47396 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18130 /* 47401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18131 /* 47405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18132 /* 47409 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
18133 /* 47409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18134 /* 47412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18135 /* 47416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18136 /* 47421 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18137 /* 47425 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18138 /* 47429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18139 /* 47431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18140 /* 47434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18141 /* 47436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18142 /* 47439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18143 /* 47442 */ GIR_RootConstrainSelectedInstOperands,
18144 /* 47443 */ // GIR_Coverage, 2341,
18145 /* 47443 */ GIR_EraseRootFromParent_Done,
18146 /* 47444 */ // Label 1314: @47444
18147 /* 47444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1315*/ GIMT_Encode4(47475), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2342 //
18148 /* 47451 */ // MIs[0] Operand 1
18149 /* 47451 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18150 /* 47456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18151 /* 47460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18152 /* 47464 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18153 /* 47464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18154 /* 47467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18155 /* 47469 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18156 /* 47471 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18157 /* 47473 */ GIR_RootConstrainSelectedInstOperands,
18158 /* 47474 */ // GIR_Coverage, 2342,
18159 /* 47474 */ GIR_EraseRootFromParent_Done,
18160 /* 47475 */ // Label 1315: @47475
18161 /* 47475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1316*/ GIMT_Encode4(47506), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2343 //
18162 /* 47482 */ // MIs[0] Operand 1
18163 /* 47482 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18164 /* 47487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18165 /* 47491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18166 /* 47495 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
18167 /* 47495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18168 /* 47498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18169 /* 47500 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18170 /* 47502 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18171 /* 47504 */ GIR_RootConstrainSelectedInstOperands,
18172 /* 47505 */ // GIR_Coverage, 2343,
18173 /* 47505 */ GIR_EraseRootFromParent_Done,
18174 /* 47506 */ // Label 1316: @47506
18175 /* 47506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(47561), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2344 //
18176 /* 47513 */ // MIs[0] Operand 1
18177 /* 47513 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18178 /* 47518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18179 /* 47522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18180 /* 47526 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18181 /* 47526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18182 /* 47529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
18183 /* 47533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18184 /* 47538 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18185 /* 47542 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18186 /* 47546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18187 /* 47548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18188 /* 47551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18189 /* 47553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18190 /* 47556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18191 /* 47559 */ GIR_RootConstrainSelectedInstOperands,
18192 /* 47560 */ // GIR_Coverage, 2344,
18193 /* 47560 */ GIR_EraseRootFromParent_Done,
18194 /* 47561 */ // Label 1317: @47561
18195 /* 47561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1318*/ GIMT_Encode4(47616), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2345 //
18196 /* 47568 */ // MIs[0] Operand 1
18197 /* 47568 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18198 /* 47573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18199 /* 47577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18200 /* 47581 */ // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
18201 /* 47581 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18202 /* 47584 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
18203 /* 47588 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18204 /* 47593 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18205 /* 47597 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18206 /* 47601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18207 /* 47603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
18208 /* 47606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18209 /* 47608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18210 /* 47611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18211 /* 47614 */ GIR_RootConstrainSelectedInstOperands,
18212 /* 47615 */ // GIR_Coverage, 2345,
18213 /* 47615 */ GIR_EraseRootFromParent_Done,
18214 /* 47616 */ // Label 1318: @47616
18215 /* 47616 */ GIM_Reject,
18216 /* 47617 */ // Label 1310: @47617
18217 /* 47617 */ GIM_Reject,
18218 /* 47618 */ // Label 1273: @47618
18219 /* 47618 */ GIM_Reject,
18220 /* 47619 */ // Label 1271: @47619
18221 /* 47619 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(48156),
18222 /* 47624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18223 /* 47627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18224 /* 47631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1320*/ GIMT_Encode4(47663), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1667 //
18225 /* 47638 */ // MIs[0] Operand 1
18226 /* 47638 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18227 /* 47643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18228 /* 47647 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18229 /* 47651 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
18230 /* 47651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18231 /* 47654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18232 /* 47656 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18233 /* 47658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18234 /* 47661 */ GIR_RootConstrainSelectedInstOperands,
18235 /* 47662 */ // GIR_Coverage, 1667,
18236 /* 47662 */ GIR_EraseRootFromParent_Done,
18237 /* 47663 */ // Label 1320: @47663
18238 /* 47663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1321*/ GIMT_Encode4(47698), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1668 //
18239 /* 47670 */ // MIs[0] Operand 1
18240 /* 47670 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18241 /* 47675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18242 /* 47679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18243 /* 47683 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
18244 /* 47683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18245 /* 47686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18246 /* 47688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18247 /* 47694 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18248 /* 47696 */ GIR_RootConstrainSelectedInstOperands,
18249 /* 47697 */ // GIR_Coverage, 1668,
18250 /* 47697 */ GIR_EraseRootFromParent_Done,
18251 /* 47698 */ // Label 1321: @47698
18252 /* 47698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1322*/ GIMT_Encode4(47729), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 232 //
18253 /* 47705 */ // MIs[0] Operand 1
18254 /* 47705 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
18255 /* 47710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18256 /* 47714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18257 /* 47718 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18258 /* 47718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18259 /* 47721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18260 /* 47723 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18261 /* 47725 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18262 /* 47727 */ GIR_RootConstrainSelectedInstOperands,
18263 /* 47728 */ // GIR_Coverage, 232,
18264 /* 47728 */ GIR_EraseRootFromParent_Done,
18265 /* 47729 */ // Label 1322: @47729
18266 /* 47729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(47760), GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode), // Rule ID 233 //
18267 /* 47736 */ // MIs[0] Operand 1
18268 /* 47736 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
18269 /* 47741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18270 /* 47745 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18271 /* 47749 */ // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
18272 /* 47749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18273 /* 47752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18274 /* 47754 */ GIR_RootToRootCopy, /*OpIdx*/2, // rs
18275 /* 47756 */ GIR_RootToRootCopy, /*OpIdx*/3, // rt
18276 /* 47758 */ GIR_RootConstrainSelectedInstOperands,
18277 /* 47759 */ // GIR_Coverage, 233,
18278 /* 47759 */ GIR_EraseRootFromParent_Done,
18279 /* 47760 */ // Label 1323: @47760
18280 /* 47760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1324*/ GIMT_Encode4(47815), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1669 //
18281 /* 47767 */ // MIs[0] Operand 1
18282 /* 47767 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18283 /* 47772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18284 /* 47776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18285 /* 47780 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
18286 /* 47780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18287 /* 47783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18288 /* 47787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18289 /* 47792 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18290 /* 47796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18291 /* 47800 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18292 /* 47802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
18293 /* 47805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18294 /* 47807 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18295 /* 47810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18296 /* 47813 */ GIR_RootConstrainSelectedInstOperands,
18297 /* 47814 */ // GIR_Coverage, 1669,
18298 /* 47814 */ GIR_EraseRootFromParent_Done,
18299 /* 47815 */ // Label 1324: @47815
18300 /* 47815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1325*/ GIMT_Encode4(47873), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1670 //
18301 /* 47822 */ // MIs[0] Operand 1
18302 /* 47822 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18303 /* 47827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18304 /* 47831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18305 /* 47835 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
18306 /* 47835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
18307 /* 47838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
18308 /* 47842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18309 /* 47847 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18310 /* 47851 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18311 /* 47855 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18312 /* 47857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18313 /* 47860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18314 /* 47862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18315 /* 47868 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18316 /* 47871 */ GIR_RootConstrainSelectedInstOperands,
18317 /* 47872 */ // GIR_Coverage, 1670,
18318 /* 47872 */ GIR_EraseRootFromParent_Done,
18319 /* 47873 */ // Label 1325: @47873
18320 /* 47873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1326*/ GIMT_Encode4(47928), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1671 //
18321 /* 47880 */ // MIs[0] Operand 1
18322 /* 47880 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18323 /* 47885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18324 /* 47889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18325 /* 47893 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18326 /* 47893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18327 /* 47896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18328 /* 47900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18329 /* 47905 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18330 /* 47909 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18331 /* 47913 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18332 /* 47915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18333 /* 47918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18334 /* 47920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18335 /* 47923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18336 /* 47926 */ GIR_RootConstrainSelectedInstOperands,
18337 /* 47927 */ // GIR_Coverage, 1671,
18338 /* 47927 */ GIR_EraseRootFromParent_Done,
18339 /* 47928 */ // Label 1326: @47928
18340 /* 47928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1327*/ GIMT_Encode4(47983), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1672 //
18341 /* 47935 */ // MIs[0] Operand 1
18342 /* 47935 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18343 /* 47940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18344 /* 47944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18345 /* 47948 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
18346 /* 47948 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18347 /* 47951 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18348 /* 47955 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18349 /* 47960 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18350 /* 47964 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18351 /* 47968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18352 /* 47970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18353 /* 47973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18354 /* 47975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18355 /* 47978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18356 /* 47981 */ GIR_RootConstrainSelectedInstOperands,
18357 /* 47982 */ // GIR_Coverage, 1672,
18358 /* 47982 */ GIR_EraseRootFromParent_Done,
18359 /* 47983 */ // Label 1327: @47983
18360 /* 47983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1328*/ GIMT_Encode4(48014), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1673 //
18361 /* 47990 */ // MIs[0] Operand 1
18362 /* 47990 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
18363 /* 47995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18364 /* 47999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18365 /* 48003 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18366 /* 48003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18367 /* 48006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18368 /* 48008 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18369 /* 48010 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18370 /* 48012 */ GIR_RootConstrainSelectedInstOperands,
18371 /* 48013 */ // GIR_Coverage, 1673,
18372 /* 48013 */ GIR_EraseRootFromParent_Done,
18373 /* 48014 */ // Label 1328: @48014
18374 /* 48014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(48045), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1674 //
18375 /* 48021 */ // MIs[0] Operand 1
18376 /* 48021 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
18377 /* 48026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18378 /* 48030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18379 /* 48034 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
18380 /* 48034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18381 /* 48037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18382 /* 48039 */ GIR_RootToRootCopy, /*OpIdx*/3, // rhs
18383 /* 48041 */ GIR_RootToRootCopy, /*OpIdx*/2, // lhs
18384 /* 48043 */ GIR_RootConstrainSelectedInstOperands,
18385 /* 48044 */ // GIR_Coverage, 1674,
18386 /* 48044 */ GIR_EraseRootFromParent_Done,
18387 /* 48045 */ // Label 1329: @48045
18388 /* 48045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1330*/ GIMT_Encode4(48100), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1675 //
18389 /* 48052 */ // MIs[0] Operand 1
18390 /* 48052 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18391 /* 48057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18392 /* 48061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18393 /* 48065 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18394 /* 48065 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18395 /* 48068 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
18396 /* 48072 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18397 /* 48077 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18398 /* 48081 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18399 /* 48085 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18400 /* 48087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18401 /* 48090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18402 /* 48092 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18403 /* 48095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18404 /* 48098 */ GIR_RootConstrainSelectedInstOperands,
18405 /* 48099 */ // GIR_Coverage, 1675,
18406 /* 48099 */ GIR_EraseRootFromParent_Done,
18407 /* 48100 */ // Label 1330: @48100
18408 /* 48100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1331*/ GIMT_Encode4(48155), GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips), // Rule ID 1676 //
18409 /* 48107 */ // MIs[0] Operand 1
18410 /* 48107 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18411 /* 48112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18412 /* 48116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18413 /* 48120 */ // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
18414 /* 48120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18415 /* 48123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
18416 /* 48127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18417 /* 48132 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18418 /* 48136 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18419 /* 48140 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18420 /* 48142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
18421 /* 48145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
18422 /* 48147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18423 /* 48150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
18424 /* 48153 */ GIR_RootConstrainSelectedInstOperands,
18425 /* 48154 */ // GIR_Coverage, 1676,
18426 /* 48154 */ GIR_EraseRootFromParent_Done,
18427 /* 48155 */ // Label 1331: @48155
18428 /* 48155 */ GIM_Reject,
18429 /* 48156 */ // Label 1319: @48156
18430 /* 48156 */ GIM_Reject,
18431 /* 48157 */ // Label 1272: @48157
18432 /* 48157 */ GIM_Reject,
18433 /* 48158 */ // Label 1269: @48158
18434 /* 48158 */ GIM_Reject,
18435 /* 48159 */ // Label 42: @48159
18436 /* 48159 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(49083),
18437 /* 48164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18438 /* 48167 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1335*/ GIMT_Encode4(49082),
18439 /* 48178 */ /*GILLT_s32*//*Label 1333*/ GIMT_Encode4(48186),
18440 /* 48182 */ /*GILLT_s64*//*Label 1334*/ GIMT_Encode4(48634),
18441 /* 48186 */ // Label 1333: @48186
18442 /* 48186 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(48633),
18443 /* 48191 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18444 /* 48194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
18445 /* 48198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(48229), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 340 //
18446 /* 48205 */ // MIs[0] Operand 1
18447 /* 48205 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18448 /* 48210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18449 /* 48214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18450 /* 48218 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18451 /* 48218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
18452 /* 48221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18453 /* 48223 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18454 /* 48225 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18455 /* 48227 */ GIR_RootConstrainSelectedInstOperands,
18456 /* 48228 */ // GIR_Coverage, 340,
18457 /* 48228 */ GIR_EraseRootFromParent_Done,
18458 /* 48229 */ // Label 1337: @48229
18459 /* 48229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(48260), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 341 //
18460 /* 48236 */ // MIs[0] Operand 1
18461 /* 48236 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18462 /* 48241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18463 /* 48245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18464 /* 48249 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18465 /* 48249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
18466 /* 48252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18467 /* 48254 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18468 /* 48256 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18469 /* 48258 */ GIR_RootConstrainSelectedInstOperands,
18470 /* 48259 */ // GIR_Coverage, 341,
18471 /* 48259 */ GIR_EraseRootFromParent_Done,
18472 /* 48260 */ // Label 1338: @48260
18473 /* 48260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(48291), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 342 //
18474 /* 48267 */ // MIs[0] Operand 1
18475 /* 48267 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18476 /* 48272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18477 /* 48276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18478 /* 48280 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18479 /* 48280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
18480 /* 48283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18481 /* 48285 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18482 /* 48287 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18483 /* 48289 */ GIR_RootConstrainSelectedInstOperands,
18484 /* 48290 */ // GIR_Coverage, 342,
18485 /* 48290 */ GIR_EraseRootFromParent_Done,
18486 /* 48291 */ // Label 1339: @48291
18487 /* 48291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1340*/ GIMT_Encode4(48322), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 343 //
18488 /* 48298 */ // MIs[0] Operand 1
18489 /* 48298 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18490 /* 48303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18491 /* 48307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18492 /* 48311 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18493 /* 48311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
18494 /* 48314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18495 /* 48316 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18496 /* 48318 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18497 /* 48320 */ GIR_RootConstrainSelectedInstOperands,
18498 /* 48321 */ // GIR_Coverage, 343,
18499 /* 48321 */ GIR_EraseRootFromParent_Done,
18500 /* 48322 */ // Label 1340: @48322
18501 /* 48322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(48353), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 344 //
18502 /* 48329 */ // MIs[0] Operand 1
18503 /* 48329 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18504 /* 48334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18505 /* 48338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18506 /* 48342 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18507 /* 48342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
18508 /* 48345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18509 /* 48347 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18510 /* 48349 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18511 /* 48351 */ GIR_RootConstrainSelectedInstOperands,
18512 /* 48352 */ // GIR_Coverage, 344,
18513 /* 48352 */ GIR_EraseRootFromParent_Done,
18514 /* 48353 */ // Label 1341: @48353
18515 /* 48353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1342*/ GIMT_Encode4(48384), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 345 //
18516 /* 48360 */ // MIs[0] Operand 1
18517 /* 48360 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18518 /* 48365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18519 /* 48369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18520 /* 48373 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18521 /* 48373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
18522 /* 48376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18523 /* 48378 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18524 /* 48380 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18525 /* 48382 */ GIR_RootConstrainSelectedInstOperands,
18526 /* 48383 */ // GIR_Coverage, 345,
18527 /* 48383 */ GIR_EraseRootFromParent_Done,
18528 /* 48384 */ // Label 1342: @48384
18529 /* 48384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(48415), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 346 //
18530 /* 48391 */ // MIs[0] Operand 1
18531 /* 48391 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18532 /* 48396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18533 /* 48400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18534 /* 48404 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18535 /* 48404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
18536 /* 48407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18537 /* 48409 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18538 /* 48411 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18539 /* 48413 */ GIR_RootConstrainSelectedInstOperands,
18540 /* 48414 */ // GIR_Coverage, 346,
18541 /* 48414 */ GIR_EraseRootFromParent_Done,
18542 /* 48415 */ // Label 1343: @48415
18543 /* 48415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(48446), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1215 //
18544 /* 48422 */ // MIs[0] Operand 1
18545 /* 48422 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18546 /* 48427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18547 /* 48431 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18548 /* 48435 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18549 /* 48435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
18550 /* 48438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18551 /* 48440 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18552 /* 48442 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18553 /* 48444 */ GIR_RootConstrainSelectedInstOperands,
18554 /* 48445 */ // GIR_Coverage, 1215,
18555 /* 48445 */ GIR_EraseRootFromParent_Done,
18556 /* 48446 */ // Label 1344: @48446
18557 /* 48446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(48477), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1216 //
18558 /* 48453 */ // MIs[0] Operand 1
18559 /* 48453 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18560 /* 48458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18561 /* 48462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18562 /* 48466 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18563 /* 48466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
18564 /* 48469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18565 /* 48471 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18566 /* 48473 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18567 /* 48475 */ GIR_RootConstrainSelectedInstOperands,
18568 /* 48476 */ // GIR_Coverage, 1216,
18569 /* 48476 */ GIR_EraseRootFromParent_Done,
18570 /* 48477 */ // Label 1345: @48477
18571 /* 48477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(48508), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1217 //
18572 /* 48484 */ // MIs[0] Operand 1
18573 /* 48484 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18574 /* 48489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18575 /* 48493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18576 /* 48497 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18577 /* 48497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
18578 /* 48500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18579 /* 48502 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18580 /* 48504 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18581 /* 48506 */ GIR_RootConstrainSelectedInstOperands,
18582 /* 48507 */ // GIR_Coverage, 1217,
18583 /* 48507 */ GIR_EraseRootFromParent_Done,
18584 /* 48508 */ // Label 1346: @48508
18585 /* 48508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(48539), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1218 //
18586 /* 48515 */ // MIs[0] Operand 1
18587 /* 48515 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18588 /* 48520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18589 /* 48524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18590 /* 48528 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18591 /* 48528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
18592 /* 48531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18593 /* 48533 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18594 /* 48535 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18595 /* 48537 */ GIR_RootConstrainSelectedInstOperands,
18596 /* 48538 */ // GIR_Coverage, 1218,
18597 /* 48538 */ GIR_EraseRootFromParent_Done,
18598 /* 48539 */ // Label 1347: @48539
18599 /* 48539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(48570), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1219 //
18600 /* 48546 */ // MIs[0] Operand 1
18601 /* 48546 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18602 /* 48551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18603 /* 48555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18604 /* 48559 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18605 /* 48559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
18606 /* 48562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18607 /* 48564 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18608 /* 48566 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18609 /* 48568 */ GIR_RootConstrainSelectedInstOperands,
18610 /* 48569 */ // GIR_Coverage, 1219,
18611 /* 48569 */ GIR_EraseRootFromParent_Done,
18612 /* 48570 */ // Label 1348: @48570
18613 /* 48570 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(48601), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1220 //
18614 /* 48577 */ // MIs[0] Operand 1
18615 /* 48577 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18616 /* 48582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18617 /* 48586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18618 /* 48590 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18619 /* 48590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
18620 /* 48593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18621 /* 48595 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18622 /* 48597 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18623 /* 48599 */ GIR_RootConstrainSelectedInstOperands,
18624 /* 48600 */ // GIR_Coverage, 1220,
18625 /* 48600 */ GIR_EraseRootFromParent_Done,
18626 /* 48601 */ // Label 1349: @48601
18627 /* 48601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(48632), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1221 //
18628 /* 48608 */ // MIs[0] Operand 1
18629 /* 48608 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18630 /* 48613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18631 /* 48617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18632 /* 48621 */ // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
18633 /* 48621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
18634 /* 48624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18635 /* 48626 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18636 /* 48628 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18637 /* 48630 */ GIR_RootConstrainSelectedInstOperands,
18638 /* 48631 */ // GIR_Coverage, 1221,
18639 /* 48631 */ GIR_EraseRootFromParent_Done,
18640 /* 48632 */ // Label 1350: @48632
18641 /* 48632 */ GIM_Reject,
18642 /* 48633 */ // Label 1336: @48633
18643 /* 48633 */ GIM_Reject,
18644 /* 48634 */ // Label 1334: @48634
18645 /* 48634 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(49081),
18646 /* 48639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18647 /* 48642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
18648 /* 48646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(48677), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 347 //
18649 /* 48653 */ // MIs[0] Operand 1
18650 /* 48653 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18651 /* 48658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18652 /* 48662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18653 /* 48666 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18654 /* 48666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
18655 /* 48669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18656 /* 48671 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18657 /* 48673 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18658 /* 48675 */ GIR_RootConstrainSelectedInstOperands,
18659 /* 48676 */ // GIR_Coverage, 347,
18660 /* 48676 */ GIR_EraseRootFromParent_Done,
18661 /* 48677 */ // Label 1352: @48677
18662 /* 48677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(48708), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 348 //
18663 /* 48684 */ // MIs[0] Operand 1
18664 /* 48684 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18665 /* 48689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18666 /* 48693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18667 /* 48697 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18668 /* 48697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
18669 /* 48700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18670 /* 48702 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18671 /* 48704 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18672 /* 48706 */ GIR_RootConstrainSelectedInstOperands,
18673 /* 48707 */ // GIR_Coverage, 348,
18674 /* 48707 */ GIR_EraseRootFromParent_Done,
18675 /* 48708 */ // Label 1353: @48708
18676 /* 48708 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(48739), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 349 //
18677 /* 48715 */ // MIs[0] Operand 1
18678 /* 48715 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18679 /* 48720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18680 /* 48724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18681 /* 48728 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18682 /* 48728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
18683 /* 48731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18684 /* 48733 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18685 /* 48735 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18686 /* 48737 */ GIR_RootConstrainSelectedInstOperands,
18687 /* 48738 */ // GIR_Coverage, 349,
18688 /* 48738 */ GIR_EraseRootFromParent_Done,
18689 /* 48739 */ // Label 1354: @48739
18690 /* 48739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1355*/ GIMT_Encode4(48770), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 350 //
18691 /* 48746 */ // MIs[0] Operand 1
18692 /* 48746 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18693 /* 48751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18694 /* 48755 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18695 /* 48759 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18696 /* 48759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
18697 /* 48762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18698 /* 48764 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18699 /* 48766 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18700 /* 48768 */ GIR_RootConstrainSelectedInstOperands,
18701 /* 48769 */ // GIR_Coverage, 350,
18702 /* 48769 */ GIR_EraseRootFromParent_Done,
18703 /* 48770 */ // Label 1355: @48770
18704 /* 48770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1356*/ GIMT_Encode4(48801), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 351 //
18705 /* 48777 */ // MIs[0] Operand 1
18706 /* 48777 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18707 /* 48782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18708 /* 48786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18709 /* 48790 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18710 /* 48790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
18711 /* 48793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18712 /* 48795 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18713 /* 48797 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18714 /* 48799 */ GIR_RootConstrainSelectedInstOperands,
18715 /* 48800 */ // GIR_Coverage, 351,
18716 /* 48800 */ GIR_EraseRootFromParent_Done,
18717 /* 48801 */ // Label 1356: @48801
18718 /* 48801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1357*/ GIMT_Encode4(48832), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 352 //
18719 /* 48808 */ // MIs[0] Operand 1
18720 /* 48808 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18721 /* 48813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18722 /* 48817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18723 /* 48821 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18724 /* 48821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
18725 /* 48824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18726 /* 48826 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18727 /* 48828 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18728 /* 48830 */ GIR_RootConstrainSelectedInstOperands,
18729 /* 48831 */ // GIR_Coverage, 352,
18730 /* 48831 */ GIR_EraseRootFromParent_Done,
18731 /* 48832 */ // Label 1357: @48832
18732 /* 48832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1358*/ GIMT_Encode4(48863), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 353 //
18733 /* 48839 */ // MIs[0] Operand 1
18734 /* 48839 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18735 /* 48844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18736 /* 48848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18737 /* 48852 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18738 /* 48852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
18739 /* 48855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18740 /* 48857 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18741 /* 48859 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18742 /* 48861 */ GIR_RootConstrainSelectedInstOperands,
18743 /* 48862 */ // GIR_Coverage, 353,
18744 /* 48862 */ GIR_EraseRootFromParent_Done,
18745 /* 48863 */ // Label 1358: @48863
18746 /* 48863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1359*/ GIMT_Encode4(48894), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1222 //
18747 /* 48870 */ // MIs[0] Operand 1
18748 /* 48870 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18749 /* 48875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18750 /* 48879 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18751 /* 48883 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18752 /* 48883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
18753 /* 48886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18754 /* 48888 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18755 /* 48890 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18756 /* 48892 */ GIR_RootConstrainSelectedInstOperands,
18757 /* 48893 */ // GIR_Coverage, 1222,
18758 /* 48893 */ GIR_EraseRootFromParent_Done,
18759 /* 48894 */ // Label 1359: @48894
18760 /* 48894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(48925), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1223 //
18761 /* 48901 */ // MIs[0] Operand 1
18762 /* 48901 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18763 /* 48906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18764 /* 48910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18765 /* 48914 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18766 /* 48914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
18767 /* 48917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18768 /* 48919 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18769 /* 48921 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18770 /* 48923 */ GIR_RootConstrainSelectedInstOperands,
18771 /* 48924 */ // GIR_Coverage, 1223,
18772 /* 48924 */ GIR_EraseRootFromParent_Done,
18773 /* 48925 */ // Label 1360: @48925
18774 /* 48925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1361*/ GIMT_Encode4(48956), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1224 //
18775 /* 48932 */ // MIs[0] Operand 1
18776 /* 48932 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18777 /* 48937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18778 /* 48941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18779 /* 48945 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18780 /* 48945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
18781 /* 48948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18782 /* 48950 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18783 /* 48952 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18784 /* 48954 */ GIR_RootConstrainSelectedInstOperands,
18785 /* 48955 */ // GIR_Coverage, 1224,
18786 /* 48955 */ GIR_EraseRootFromParent_Done,
18787 /* 48956 */ // Label 1361: @48956
18788 /* 48956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(48987), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1225 //
18789 /* 48963 */ // MIs[0] Operand 1
18790 /* 48963 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18791 /* 48968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18792 /* 48972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18793 /* 48976 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18794 /* 48976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
18795 /* 48979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18796 /* 48981 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18797 /* 48983 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18798 /* 48985 */ GIR_RootConstrainSelectedInstOperands,
18799 /* 48986 */ // GIR_Coverage, 1225,
18800 /* 48986 */ GIR_EraseRootFromParent_Done,
18801 /* 48987 */ // Label 1362: @48987
18802 /* 48987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(49018), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1226 //
18803 /* 48994 */ // MIs[0] Operand 1
18804 /* 48994 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18805 /* 48999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18806 /* 49003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18807 /* 49007 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18808 /* 49007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
18809 /* 49010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18810 /* 49012 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18811 /* 49014 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18812 /* 49016 */ GIR_RootConstrainSelectedInstOperands,
18813 /* 49017 */ // GIR_Coverage, 1226,
18814 /* 49017 */ GIR_EraseRootFromParent_Done,
18815 /* 49018 */ // Label 1363: @49018
18816 /* 49018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1364*/ GIMT_Encode4(49049), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1227 //
18817 /* 49025 */ // MIs[0] Operand 1
18818 /* 49025 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18819 /* 49030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18820 /* 49034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18821 /* 49038 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18822 /* 49038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
18823 /* 49041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18824 /* 49043 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18825 /* 49045 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18826 /* 49047 */ GIR_RootConstrainSelectedInstOperands,
18827 /* 49048 */ // GIR_Coverage, 1227,
18828 /* 49048 */ GIR_EraseRootFromParent_Done,
18829 /* 49049 */ // Label 1364: @49049
18830 /* 49049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(49080), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1228 //
18831 /* 49056 */ // MIs[0] Operand 1
18832 /* 49056 */ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18833 /* 49061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18834 /* 49065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18835 /* 49069 */ // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18836 /* 49069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
18837 /* 49072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18838 /* 49074 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
18839 /* 49076 */ GIR_RootToRootCopy, /*OpIdx*/3, // ft
18840 /* 49078 */ GIR_RootConstrainSelectedInstOperands,
18841 /* 49079 */ // GIR_Coverage, 1228,
18842 /* 49079 */ GIR_EraseRootFromParent_Done,
18843 /* 49080 */ // Label 1365: @49080
18844 /* 49080 */ GIM_Reject,
18845 /* 49081 */ // Label 1351: @49081
18846 /* 49081 */ GIM_Reject,
18847 /* 49082 */ // Label 1335: @49082
18848 /* 49082 */ GIM_Reject,
18849 /* 49083 */ // Label 1332: @49083
18850 /* 49083 */ GIM_Reject,
18851 /* 49084 */ // Label 43: @49084
18852 /* 49084 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1372*/ GIMT_Encode4(58817),
18853 /* 49095 */ /*GILLT_s32*//*Label 1366*/ GIMT_Encode4(49127),
18854 /* 49099 */ /*GILLT_s64*//*Label 1367*/ GIMT_Encode4(54421), GIMT_Encode4(0),
18855 /* 49107 */ /*GILLT_v16s8*//*Label 1368*/ GIMT_Encode4(58535), GIMT_Encode4(0),
18856 /* 49115 */ /*GILLT_v8s16*//*Label 1369*/ GIMT_Encode4(58627),
18857 /* 49119 */ /*GILLT_v4s32*//*Label 1370*/ GIMT_Encode4(58673),
18858 /* 49123 */ /*GILLT_v2s64*//*Label 1371*/ GIMT_Encode4(58745),
18859 /* 49127 */ // Label 1366: @49127
18860 /* 49127 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1375*/ GIMT_Encode4(54420),
18861 /* 49138 */ /*GILLT_s32*//*Label 1373*/ GIMT_Encode4(49146),
18862 /* 49142 */ /*GILLT_s64*//*Label 1374*/ GIMT_Encode4(54335),
18863 /* 49146 */ // Label 1373: @49146
18864 /* 49146 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(54334),
18865 /* 49151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18866 /* 49154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18867 /* 49157 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(49391),
18868 /* 49162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18869 /* 49166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18870 /* 49170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18871 /* 49174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1378*/ GIMT_Encode4(49228), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1749 //
18872 /* 49181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18873 /* 49185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18874 /* 49189 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18875 /* 49193 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18876 /* 49197 */ // MIs[1] Operand 1
18877 /* 49197 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18878 /* 49202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18879 /* 49207 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18880 /* 49211 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18881 /* 49213 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18882 /* 49213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18883 /* 49216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18884 /* 49218 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18885 /* 49220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18886 /* 49224 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18887 /* 49226 */ GIR_RootConstrainSelectedInstOperands,
18888 /* 49227 */ // GIR_Coverage, 1749,
18889 /* 49227 */ GIR_EraseRootFromParent_Done,
18890 /* 49228 */ // Label 1378: @49228
18891 /* 49228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1379*/ GIMT_Encode4(49282), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1753 //
18892 /* 49235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18893 /* 49239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18894 /* 49243 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18895 /* 49247 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18896 /* 49251 */ // MIs[1] Operand 1
18897 /* 49251 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18898 /* 49256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18899 /* 49261 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18900 /* 49265 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18901 /* 49267 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18902 /* 49267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
18903 /* 49270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18904 /* 49272 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18905 /* 49274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18906 /* 49278 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18907 /* 49280 */ GIR_RootConstrainSelectedInstOperands,
18908 /* 49281 */ // GIR_Coverage, 1753,
18909 /* 49281 */ GIR_EraseRootFromParent_Done,
18910 /* 49282 */ // Label 1379: @49282
18911 /* 49282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1380*/ GIMT_Encode4(49336), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1781 //
18912 /* 49289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18913 /* 49293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18914 /* 49297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18915 /* 49301 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18916 /* 49305 */ // MIs[1] Operand 1
18917 /* 49305 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18918 /* 49310 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18919 /* 49315 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18920 /* 49319 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18921 /* 49321 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
18922 /* 49321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
18923 /* 49324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18924 /* 49326 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18925 /* 49328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18926 /* 49332 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18927 /* 49334 */ GIR_RootConstrainSelectedInstOperands,
18928 /* 49335 */ // GIR_Coverage, 1781,
18929 /* 49335 */ GIR_EraseRootFromParent_Done,
18930 /* 49336 */ // Label 1380: @49336
18931 /* 49336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(49390), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1792 //
18932 /* 49343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18933 /* 49347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18934 /* 49351 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18935 /* 49355 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18936 /* 49359 */ // MIs[1] Operand 1
18937 /* 49359 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18938 /* 49364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18939 /* 49369 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18940 /* 49373 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18941 /* 49375 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
18942 /* 49375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
18943 /* 49378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18944 /* 49380 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18945 /* 49382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18946 /* 49386 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18947 /* 49388 */ GIR_RootConstrainSelectedInstOperands,
18948 /* 49389 */ // GIR_Coverage, 1792,
18949 /* 49389 */ GIR_EraseRootFromParent_Done,
18950 /* 49390 */ // Label 1381: @49390
18951 /* 49390 */ GIM_Reject,
18952 /* 49391 */ // Label 1377: @49391
18953 /* 49391 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(49625),
18954 /* 49396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18955 /* 49400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18956 /* 49404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18957 /* 49408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1383*/ GIMT_Encode4(49462), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1805 //
18958 /* 49415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18959 /* 49419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18960 /* 49423 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18961 /* 49427 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18962 /* 49431 */ // MIs[1] Operand 1
18963 /* 49431 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18964 /* 49436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18965 /* 49441 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18966 /* 49445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18967 /* 49447 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18968 /* 49447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
18969 /* 49450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18970 /* 49452 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18971 /* 49454 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18972 /* 49458 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18973 /* 49460 */ GIR_RootConstrainSelectedInstOperands,
18974 /* 49461 */ // GIR_Coverage, 1805,
18975 /* 49461 */ GIR_EraseRootFromParent_Done,
18976 /* 49462 */ // Label 1383: @49462
18977 /* 49462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1384*/ GIMT_Encode4(49516), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1808 //
18978 /* 49469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18979 /* 49473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18980 /* 49477 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18981 /* 49481 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18982 /* 49485 */ // MIs[1] Operand 1
18983 /* 49485 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18984 /* 49490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18985 /* 49495 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18986 /* 49499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18987 /* 49501 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18988 /* 49501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
18989 /* 49504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18990 /* 49506 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
18991 /* 49508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18992 /* 49512 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
18993 /* 49514 */ GIR_RootConstrainSelectedInstOperands,
18994 /* 49515 */ // GIR_Coverage, 1808,
18995 /* 49515 */ GIR_EraseRootFromParent_Done,
18996 /* 49516 */ // Label 1384: @49516
18997 /* 49516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1385*/ GIMT_Encode4(49570), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1818 //
18998 /* 49523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18999 /* 49527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19000 /* 49531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19001 /* 49535 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19002 /* 49539 */ // MIs[1] Operand 1
19003 /* 49539 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19004 /* 49544 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19005 /* 49549 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19006 /* 49553 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19007 /* 49555 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19008 /* 49555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
19009 /* 49558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19010 /* 49560 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19011 /* 49562 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19012 /* 49566 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19013 /* 49568 */ GIR_RootConstrainSelectedInstOperands,
19014 /* 49569 */ // GIR_Coverage, 1818,
19015 /* 49569 */ GIR_EraseRootFromParent_Done,
19016 /* 49570 */ // Label 1385: @49570
19017 /* 49570 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(49624), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1821 //
19018 /* 49577 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19019 /* 49581 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19020 /* 49585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19021 /* 49589 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19022 /* 49593 */ // MIs[1] Operand 1
19023 /* 49593 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19024 /* 49598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19025 /* 49603 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19026 /* 49607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19027 /* 49609 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
19028 /* 49609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
19029 /* 49612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19030 /* 49614 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19031 /* 49616 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19032 /* 49620 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19033 /* 49622 */ GIR_RootConstrainSelectedInstOperands,
19034 /* 49623 */ // GIR_Coverage, 1821,
19035 /* 49623 */ GIR_EraseRootFromParent_Done,
19036 /* 49624 */ // Label 1386: @49624
19037 /* 49624 */ GIM_Reject,
19038 /* 49625 */ // Label 1382: @49625
19039 /* 49625 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(49751),
19040 /* 49630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19041 /* 49634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19042 /* 49638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19043 /* 49642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(49696), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2010 //
19044 /* 49649 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19045 /* 49653 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19046 /* 49657 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19047 /* 49661 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19048 /* 49665 */ // MIs[1] Operand 1
19049 /* 49665 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19050 /* 49670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19051 /* 49675 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19052 /* 49679 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19053 /* 49681 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19054 /* 49681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
19055 /* 49684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19056 /* 49686 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19057 /* 49688 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19058 /* 49690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19059 /* 49694 */ GIR_RootConstrainSelectedInstOperands,
19060 /* 49695 */ // GIR_Coverage, 2010,
19061 /* 49695 */ GIR_EraseRootFromParent_Done,
19062 /* 49696 */ // Label 1388: @49696
19063 /* 49696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1389*/ GIMT_Encode4(49750), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2013 //
19064 /* 49703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19065 /* 49707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19066 /* 49711 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19067 /* 49715 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19068 /* 49719 */ // MIs[1] Operand 1
19069 /* 49719 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19070 /* 49724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19071 /* 49729 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19072 /* 49733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19073 /* 49735 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
19074 /* 49735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
19075 /* 49738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19076 /* 49740 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19077 /* 49742 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19078 /* 49744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19079 /* 49748 */ GIR_RootConstrainSelectedInstOperands,
19080 /* 49749 */ // GIR_Coverage, 2013,
19081 /* 49749 */ GIR_EraseRootFromParent_Done,
19082 /* 49750 */ // Label 1389: @49750
19083 /* 49750 */ GIM_Reject,
19084 /* 49751 */ // Label 1387: @49751
19085 /* 49751 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(49985),
19086 /* 49756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19087 /* 49760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19088 /* 49764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19089 /* 49768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1391*/ GIMT_Encode4(49822), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2357 //
19090 /* 49775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19091 /* 49779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19092 /* 49783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19093 /* 49787 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19094 /* 49791 */ // MIs[1] Operand 1
19095 /* 49791 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19096 /* 49796 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19097 /* 49801 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19098 /* 49805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19099 /* 49807 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19100 /* 49807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19101 /* 49810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19102 /* 49812 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19103 /* 49814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19104 /* 49818 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19105 /* 49820 */ GIR_RootConstrainSelectedInstOperands,
19106 /* 49821 */ // GIR_Coverage, 2357,
19107 /* 49821 */ GIR_EraseRootFromParent_Done,
19108 /* 49822 */ // Label 1391: @49822
19109 /* 49822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1392*/ GIMT_Encode4(49876), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2361 //
19110 /* 49829 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19111 /* 49833 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19112 /* 49837 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19113 /* 49841 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19114 /* 49845 */ // MIs[1] Operand 1
19115 /* 49845 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19116 /* 49850 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19117 /* 49855 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19118 /* 49859 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19119 /* 49861 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19120 /* 49861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19121 /* 49864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19122 /* 49866 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19123 /* 49868 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19124 /* 49872 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19125 /* 49874 */ GIR_RootConstrainSelectedInstOperands,
19126 /* 49875 */ // GIR_Coverage, 2361,
19127 /* 49875 */ GIR_EraseRootFromParent_Done,
19128 /* 49876 */ // Label 1392: @49876
19129 /* 49876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1393*/ GIMT_Encode4(49930), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2371 //
19130 /* 49883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19131 /* 49887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19132 /* 49891 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19133 /* 49895 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19134 /* 49899 */ // MIs[1] Operand 1
19135 /* 49899 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19136 /* 49904 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19137 /* 49909 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19138 /* 49913 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19139 /* 49915 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19140 /* 49915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19141 /* 49918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19142 /* 49920 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19143 /* 49922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19144 /* 49926 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19145 /* 49928 */ GIR_RootConstrainSelectedInstOperands,
19146 /* 49929 */ // GIR_Coverage, 2371,
19147 /* 49929 */ GIR_EraseRootFromParent_Done,
19148 /* 49930 */ // Label 1393: @49930
19149 /* 49930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1394*/ GIMT_Encode4(49984), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2375 //
19150 /* 49937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19151 /* 49941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19152 /* 49945 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19153 /* 49949 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19154 /* 49953 */ // MIs[1] Operand 1
19155 /* 49953 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19156 /* 49958 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19157 /* 49963 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19158 /* 49967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19159 /* 49969 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
19160 /* 49969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
19161 /* 49972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19162 /* 49974 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19163 /* 49976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19164 /* 49980 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19165 /* 49982 */ GIR_RootConstrainSelectedInstOperands,
19166 /* 49983 */ // GIR_Coverage, 2375,
19167 /* 49983 */ GIR_EraseRootFromParent_Done,
19168 /* 49984 */ // Label 1394: @49984
19169 /* 49984 */ GIM_Reject,
19170 /* 49985 */ // Label 1390: @49985
19171 /* 49985 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(50111),
19172 /* 49990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19173 /* 49994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19174 /* 49998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19175 /* 50002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1396*/ GIMT_Encode4(50056), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2418 //
19176 /* 50009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19177 /* 50013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19178 /* 50017 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19179 /* 50021 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19180 /* 50025 */ // MIs[1] Operand 1
19181 /* 50025 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19182 /* 50030 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19183 /* 50035 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19184 /* 50039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19185 /* 50041 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19186 /* 50041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
19187 /* 50044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19188 /* 50046 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19189 /* 50048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19190 /* 50052 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19191 /* 50054 */ GIR_RootConstrainSelectedInstOperands,
19192 /* 50055 */ // GIR_Coverage, 2418,
19193 /* 50055 */ GIR_EraseRootFromParent_Done,
19194 /* 50056 */ // Label 1396: @50056
19195 /* 50056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1397*/ GIMT_Encode4(50110), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2421 //
19196 /* 50063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19197 /* 50067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19198 /* 50071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19199 /* 50075 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19200 /* 50079 */ // MIs[1] Operand 1
19201 /* 50079 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19202 /* 50084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19203 /* 50089 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
19204 /* 50093 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19205 /* 50095 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
19206 /* 50095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
19207 /* 50098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19208 /* 50100 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19209 /* 50102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19210 /* 50106 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19211 /* 50108 */ GIR_RootConstrainSelectedInstOperands,
19212 /* 50109 */ // GIR_Coverage, 2421,
19213 /* 50109 */ GIR_EraseRootFromParent_Done,
19214 /* 50110 */ // Label 1397: @50110
19215 /* 50110 */ GIM_Reject,
19216 /* 50111 */ // Label 1395: @50111
19217 /* 50111 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(51041),
19218 /* 50116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19219 /* 50120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19220 /* 50124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19221 /* 50128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1399*/ GIMT_Encode4(50204), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1740 //
19222 /* 50135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19223 /* 50139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19224 /* 50143 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19225 /* 50147 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19226 /* 50151 */ // MIs[1] Operand 1
19227 /* 50151 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19228 /* 50156 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19229 /* 50161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19230 /* 50166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19231 /* 50168 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19232 /* 50168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19233 /* 50171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19234 /* 50175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19235 /* 50180 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19236 /* 50184 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19237 /* 50188 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19238 /* 50190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19239 /* 50193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19240 /* 50195 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19241 /* 50197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19242 /* 50200 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19243 /* 50202 */ GIR_RootConstrainSelectedInstOperands,
19244 /* 50203 */ // GIR_Coverage, 1740,
19245 /* 50203 */ GIR_EraseRootFromParent_Done,
19246 /* 50204 */ // Label 1399: @50204
19247 /* 50204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1400*/ GIMT_Encode4(50280), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1741 //
19248 /* 50211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19249 /* 50215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19250 /* 50219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19251 /* 50223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19252 /* 50227 */ // MIs[1] Operand 1
19253 /* 50227 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19254 /* 50232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19255 /* 50237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19256 /* 50242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19257 /* 50244 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19258 /* 50244 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19259 /* 50247 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19260 /* 50251 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19261 /* 50256 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19262 /* 50260 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19263 /* 50264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19264 /* 50266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19265 /* 50269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19266 /* 50271 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19267 /* 50273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19268 /* 50276 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19269 /* 50278 */ GIR_RootConstrainSelectedInstOperands,
19270 /* 50279 */ // GIR_Coverage, 1741,
19271 /* 50279 */ GIR_EraseRootFromParent_Done,
19272 /* 50280 */ // Label 1400: @50280
19273 /* 50280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1401*/ GIMT_Encode4(50356), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1744 //
19274 /* 50287 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19275 /* 50291 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19276 /* 50295 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19277 /* 50299 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19278 /* 50303 */ // MIs[1] Operand 1
19279 /* 50303 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19280 /* 50308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19281 /* 50313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19282 /* 50318 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19283 /* 50320 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19284 /* 50320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19285 /* 50323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19286 /* 50327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19287 /* 50332 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19288 /* 50336 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19289 /* 50340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19290 /* 50342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19291 /* 50345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19292 /* 50347 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19293 /* 50349 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19294 /* 50352 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19295 /* 50354 */ GIR_RootConstrainSelectedInstOperands,
19296 /* 50355 */ // GIR_Coverage, 1744,
19297 /* 50355 */ GIR_EraseRootFromParent_Done,
19298 /* 50356 */ // Label 1401: @50356
19299 /* 50356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1402*/ GIMT_Encode4(50432), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1745 //
19300 /* 50363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19301 /* 50367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19302 /* 50371 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19303 /* 50375 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19304 /* 50379 */ // MIs[1] Operand 1
19305 /* 50379 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19306 /* 50384 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19307 /* 50389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19308 /* 50394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19309 /* 50396 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19310 /* 50396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19311 /* 50399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19312 /* 50403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19313 /* 50408 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19314 /* 50412 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19315 /* 50416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19316 /* 50418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19317 /* 50421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19318 /* 50423 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19319 /* 50425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19320 /* 50428 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19321 /* 50430 */ GIR_RootConstrainSelectedInstOperands,
19322 /* 50431 */ // GIR_Coverage, 1745,
19323 /* 50431 */ GIR_EraseRootFromParent_Done,
19324 /* 50432 */ // Label 1402: @50432
19325 /* 50432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1403*/ GIMT_Encode4(50508), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1748 //
19326 /* 50439 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19327 /* 50443 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19328 /* 50447 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19329 /* 50451 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19330 /* 50455 */ // MIs[1] Operand 1
19331 /* 50455 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19332 /* 50460 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19333 /* 50465 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19334 /* 50470 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19335 /* 50472 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19336 /* 50472 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19337 /* 50475 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19338 /* 50479 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19339 /* 50484 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19340 /* 50488 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19341 /* 50492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19342 /* 50494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19343 /* 50497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19344 /* 50499 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19345 /* 50501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19346 /* 50504 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19347 /* 50506 */ GIR_RootConstrainSelectedInstOperands,
19348 /* 50507 */ // GIR_Coverage, 1748,
19349 /* 50507 */ GIR_EraseRootFromParent_Done,
19350 /* 50508 */ // Label 1403: @50508
19351 /* 50508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1404*/ GIMT_Encode4(50584), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1751 //
19352 /* 50515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19353 /* 50519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19354 /* 50523 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19355 /* 50527 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19356 /* 50531 */ // MIs[1] Operand 1
19357 /* 50531 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19358 /* 50536 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19359 /* 50541 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19360 /* 50546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19361 /* 50548 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19362 /* 50548 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19363 /* 50551 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19364 /* 50555 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19365 /* 50560 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19366 /* 50564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19367 /* 50568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19368 /* 50570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
19369 /* 50573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19370 /* 50575 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19371 /* 50577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19372 /* 50580 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19373 /* 50582 */ GIR_RootConstrainSelectedInstOperands,
19374 /* 50583 */ // GIR_Coverage, 1751,
19375 /* 50583 */ GIR_EraseRootFromParent_Done,
19376 /* 50584 */ // Label 1404: @50584
19377 /* 50584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1405*/ GIMT_Encode4(50660), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1762 //
19378 /* 50591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19379 /* 50595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19380 /* 50599 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19381 /* 50603 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19382 /* 50607 */ // MIs[1] Operand 1
19383 /* 50607 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19384 /* 50612 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19385 /* 50617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19386 /* 50622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19387 /* 50624 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19388 /* 50624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19389 /* 50627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19390 /* 50631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19391 /* 50636 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19392 /* 50640 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19393 /* 50644 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19394 /* 50646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19395 /* 50649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19396 /* 50651 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19397 /* 50653 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19398 /* 50656 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19399 /* 50658 */ GIR_RootConstrainSelectedInstOperands,
19400 /* 50659 */ // GIR_Coverage, 1762,
19401 /* 50659 */ GIR_EraseRootFromParent_Done,
19402 /* 50660 */ // Label 1405: @50660
19403 /* 50660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1406*/ GIMT_Encode4(50736), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1763 //
19404 /* 50667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19405 /* 50671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19406 /* 50675 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19407 /* 50679 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19408 /* 50683 */ // MIs[1] Operand 1
19409 /* 50683 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19410 /* 50688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19411 /* 50693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19412 /* 50698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19413 /* 50700 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19414 /* 50700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19415 /* 50703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19416 /* 50707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19417 /* 50712 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19418 /* 50716 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19419 /* 50720 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19420 /* 50722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19421 /* 50725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19422 /* 50727 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19423 /* 50729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19424 /* 50732 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19425 /* 50734 */ GIR_RootConstrainSelectedInstOperands,
19426 /* 50735 */ // GIR_Coverage, 1763,
19427 /* 50735 */ GIR_EraseRootFromParent_Done,
19428 /* 50736 */ // Label 1406: @50736
19429 /* 50736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1407*/ GIMT_Encode4(50812), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1766 //
19430 /* 50743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19431 /* 50747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19432 /* 50751 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19433 /* 50755 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19434 /* 50759 */ // MIs[1] Operand 1
19435 /* 50759 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19436 /* 50764 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19437 /* 50769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19438 /* 50774 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19439 /* 50776 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19440 /* 50776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19441 /* 50779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19442 /* 50783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19443 /* 50788 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19444 /* 50792 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19445 /* 50796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19446 /* 50798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19447 /* 50801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19448 /* 50803 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19449 /* 50805 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19450 /* 50808 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19451 /* 50810 */ GIR_RootConstrainSelectedInstOperands,
19452 /* 50811 */ // GIR_Coverage, 1766,
19453 /* 50811 */ GIR_EraseRootFromParent_Done,
19454 /* 50812 */ // Label 1407: @50812
19455 /* 50812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1408*/ GIMT_Encode4(50888), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1767 //
19456 /* 50819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19457 /* 50823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19458 /* 50827 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19459 /* 50831 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19460 /* 50835 */ // MIs[1] Operand 1
19461 /* 50835 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19462 /* 50840 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19463 /* 50845 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19464 /* 50850 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19465 /* 50852 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19466 /* 50852 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19467 /* 50855 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19468 /* 50859 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19469 /* 50864 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19470 /* 50868 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19471 /* 50872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19472 /* 50874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19473 /* 50877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19474 /* 50879 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19475 /* 50881 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19476 /* 50884 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19477 /* 50886 */ GIR_RootConstrainSelectedInstOperands,
19478 /* 50887 */ // GIR_Coverage, 1767,
19479 /* 50887 */ GIR_EraseRootFromParent_Done,
19480 /* 50888 */ // Label 1408: @50888
19481 /* 50888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1409*/ GIMT_Encode4(50964), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1780 //
19482 /* 50895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19483 /* 50899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19484 /* 50903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19485 /* 50907 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19486 /* 50911 */ // MIs[1] Operand 1
19487 /* 50911 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19488 /* 50916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19489 /* 50921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19490 /* 50926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19491 /* 50928 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19492 /* 50928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19493 /* 50931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19494 /* 50935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19495 /* 50940 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19496 /* 50944 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19497 /* 50948 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19498 /* 50950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
19499 /* 50953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19500 /* 50955 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19501 /* 50957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19502 /* 50960 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19503 /* 50962 */ GIR_RootConstrainSelectedInstOperands,
19504 /* 50963 */ // GIR_Coverage, 1780,
19505 /* 50963 */ GIR_EraseRootFromParent_Done,
19506 /* 50964 */ // Label 1409: @50964
19507 /* 50964 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1410*/ GIMT_Encode4(51040), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1790 //
19508 /* 50971 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19509 /* 50975 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19510 /* 50979 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19511 /* 50983 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19512 /* 50987 */ // MIs[1] Operand 1
19513 /* 50987 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19514 /* 50992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19515 /* 50997 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19516 /* 51002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19517 /* 51004 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19518 /* 51004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19519 /* 51007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19520 /* 51011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19521 /* 51016 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19522 /* 51020 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19523 /* 51024 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19524 /* 51026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
19525 /* 51029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19526 /* 51031 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19527 /* 51033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19528 /* 51036 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19529 /* 51038 */ GIR_RootConstrainSelectedInstOperands,
19530 /* 51039 */ // GIR_Coverage, 1790,
19531 /* 51039 */ GIR_EraseRootFromParent_Done,
19532 /* 51040 */ // Label 1410: @51040
19533 /* 51040 */ GIM_Reject,
19534 /* 51041 */ // Label 1398: @51041
19535 /* 51041 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(51971),
19536 /* 51046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19537 /* 51050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19538 /* 51054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19539 /* 51058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1412*/ GIMT_Encode4(51134), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1796 //
19540 /* 51065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19541 /* 51069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19542 /* 51073 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19543 /* 51077 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19544 /* 51081 */ // MIs[1] Operand 1
19545 /* 51081 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19546 /* 51086 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19547 /* 51091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19548 /* 51096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19549 /* 51098 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19550 /* 51098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19551 /* 51101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19552 /* 51105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19553 /* 51110 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19554 /* 51114 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19555 /* 51118 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19556 /* 51120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19557 /* 51123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19558 /* 51125 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19559 /* 51127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19560 /* 51130 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19561 /* 51132 */ GIR_RootConstrainSelectedInstOperands,
19562 /* 51133 */ // GIR_Coverage, 1796,
19563 /* 51133 */ GIR_EraseRootFromParent_Done,
19564 /* 51134 */ // Label 1412: @51134
19565 /* 51134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1413*/ GIMT_Encode4(51210), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1797 //
19566 /* 51141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19567 /* 51145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19568 /* 51149 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19569 /* 51153 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19570 /* 51157 */ // MIs[1] Operand 1
19571 /* 51157 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19572 /* 51162 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19573 /* 51167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19574 /* 51172 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19575 /* 51174 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19576 /* 51174 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19577 /* 51177 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19578 /* 51181 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19579 /* 51186 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19580 /* 51190 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19581 /* 51194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19582 /* 51196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19583 /* 51199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19584 /* 51201 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19585 /* 51203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19586 /* 51206 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19587 /* 51208 */ GIR_RootConstrainSelectedInstOperands,
19588 /* 51209 */ // GIR_Coverage, 1797,
19589 /* 51209 */ GIR_EraseRootFromParent_Done,
19590 /* 51210 */ // Label 1413: @51210
19591 /* 51210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1414*/ GIMT_Encode4(51286), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1800 //
19592 /* 51217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19593 /* 51221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19594 /* 51225 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19595 /* 51229 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19596 /* 51233 */ // MIs[1] Operand 1
19597 /* 51233 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19598 /* 51238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19599 /* 51243 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19600 /* 51248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19601 /* 51250 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19602 /* 51250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19603 /* 51253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19604 /* 51257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19605 /* 51262 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19606 /* 51266 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19607 /* 51270 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19608 /* 51272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19609 /* 51275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19610 /* 51277 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19611 /* 51279 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19612 /* 51282 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19613 /* 51284 */ GIR_RootConstrainSelectedInstOperands,
19614 /* 51285 */ // GIR_Coverage, 1800,
19615 /* 51285 */ GIR_EraseRootFromParent_Done,
19616 /* 51286 */ // Label 1414: @51286
19617 /* 51286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1415*/ GIMT_Encode4(51362), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1801 //
19618 /* 51293 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19619 /* 51297 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19620 /* 51301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19621 /* 51305 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19622 /* 51309 */ // MIs[1] Operand 1
19623 /* 51309 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19624 /* 51314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19625 /* 51319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19626 /* 51324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19627 /* 51326 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19628 /* 51326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19629 /* 51329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19630 /* 51333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19631 /* 51338 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19632 /* 51342 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19633 /* 51346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19634 /* 51348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19635 /* 51351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19636 /* 51353 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19637 /* 51355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19638 /* 51358 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19639 /* 51360 */ GIR_RootConstrainSelectedInstOperands,
19640 /* 51361 */ // GIR_Coverage, 1801,
19641 /* 51361 */ GIR_EraseRootFromParent_Done,
19642 /* 51362 */ // Label 1415: @51362
19643 /* 51362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1416*/ GIMT_Encode4(51438), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1804 //
19644 /* 51369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19645 /* 51373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19646 /* 51377 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19647 /* 51381 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19648 /* 51385 */ // MIs[1] Operand 1
19649 /* 51385 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19650 /* 51390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19651 /* 51395 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19652 /* 51400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19653 /* 51402 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19654 /* 51402 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19655 /* 51405 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19656 /* 51409 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19657 /* 51414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19658 /* 51418 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19659 /* 51422 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19660 /* 51424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19661 /* 51427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19662 /* 51429 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19663 /* 51431 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19664 /* 51434 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19665 /* 51436 */ GIR_RootConstrainSelectedInstOperands,
19666 /* 51437 */ // GIR_Coverage, 1804,
19667 /* 51437 */ GIR_EraseRootFromParent_Done,
19668 /* 51438 */ // Label 1416: @51438
19669 /* 51438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1417*/ GIMT_Encode4(51514), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1806 //
19670 /* 51445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19671 /* 51449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19672 /* 51453 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19673 /* 51457 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19674 /* 51461 */ // MIs[1] Operand 1
19675 /* 51461 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19676 /* 51466 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19677 /* 51471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19678 /* 51476 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19679 /* 51478 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19680 /* 51478 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19681 /* 51481 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19682 /* 51485 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19683 /* 51490 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19684 /* 51494 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19685 /* 51498 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19686 /* 51500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
19687 /* 51503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19688 /* 51505 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19689 /* 51507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19690 /* 51510 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19691 /* 51512 */ GIR_RootConstrainSelectedInstOperands,
19692 /* 51513 */ // GIR_Coverage, 1806,
19693 /* 51513 */ GIR_EraseRootFromParent_Done,
19694 /* 51514 */ // Label 1417: @51514
19695 /* 51514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1418*/ GIMT_Encode4(51590), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1809 //
19696 /* 51521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19697 /* 51525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19698 /* 51529 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19699 /* 51533 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19700 /* 51537 */ // MIs[1] Operand 1
19701 /* 51537 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19702 /* 51542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19703 /* 51547 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19704 /* 51552 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19705 /* 51554 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19706 /* 51554 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19707 /* 51557 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19708 /* 51561 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19709 /* 51566 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19710 /* 51570 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19711 /* 51574 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19712 /* 51576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19713 /* 51579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19714 /* 51581 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19715 /* 51583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19716 /* 51586 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19717 /* 51588 */ GIR_RootConstrainSelectedInstOperands,
19718 /* 51589 */ // GIR_Coverage, 1809,
19719 /* 51589 */ GIR_EraseRootFromParent_Done,
19720 /* 51590 */ // Label 1418: @51590
19721 /* 51590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1419*/ GIMT_Encode4(51666), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1810 //
19722 /* 51597 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19723 /* 51601 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19724 /* 51605 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19725 /* 51609 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19726 /* 51613 */ // MIs[1] Operand 1
19727 /* 51613 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19728 /* 51618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19729 /* 51623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19730 /* 51628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19731 /* 51630 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19732 /* 51630 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19733 /* 51633 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19734 /* 51637 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19735 /* 51642 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19736 /* 51646 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19737 /* 51650 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19738 /* 51652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19739 /* 51655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19740 /* 51657 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19741 /* 51659 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19742 /* 51662 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19743 /* 51664 */ GIR_RootConstrainSelectedInstOperands,
19744 /* 51665 */ // GIR_Coverage, 1810,
19745 /* 51665 */ GIR_EraseRootFromParent_Done,
19746 /* 51666 */ // Label 1419: @51666
19747 /* 51666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(51742), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1813 //
19748 /* 51673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19749 /* 51677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19750 /* 51681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19751 /* 51685 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19752 /* 51689 */ // MIs[1] Operand 1
19753 /* 51689 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19754 /* 51694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19755 /* 51699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19756 /* 51704 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19757 /* 51706 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
19758 /* 51706 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19759 /* 51709 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19760 /* 51713 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19761 /* 51718 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19762 /* 51722 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19763 /* 51726 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19764 /* 51728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19765 /* 51731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19766 /* 51733 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19767 /* 51735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19768 /* 51738 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19769 /* 51740 */ GIR_RootConstrainSelectedInstOperands,
19770 /* 51741 */ // GIR_Coverage, 1813,
19771 /* 51741 */ GIR_EraseRootFromParent_Done,
19772 /* 51742 */ // Label 1420: @51742
19773 /* 51742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1421*/ GIMT_Encode4(51818), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1814 //
19774 /* 51749 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19775 /* 51753 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19776 /* 51757 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19777 /* 51761 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19778 /* 51765 */ // MIs[1] Operand 1
19779 /* 51765 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19780 /* 51770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19781 /* 51775 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19782 /* 51780 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19783 /* 51782 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
19784 /* 51782 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19785 /* 51785 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19786 /* 51789 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19787 /* 51794 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19788 /* 51798 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19789 /* 51802 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19790 /* 51804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19791 /* 51807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19792 /* 51809 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19793 /* 51811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19794 /* 51814 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19795 /* 51816 */ GIR_RootConstrainSelectedInstOperands,
19796 /* 51817 */ // GIR_Coverage, 1814,
19797 /* 51817 */ GIR_EraseRootFromParent_Done,
19798 /* 51818 */ // Label 1421: @51818
19799 /* 51818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(51894), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1817 //
19800 /* 51825 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19801 /* 51829 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19802 /* 51833 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19803 /* 51837 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19804 /* 51841 */ // MIs[1] Operand 1
19805 /* 51841 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19806 /* 51846 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19807 /* 51851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19808 /* 51856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19809 /* 51858 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19810 /* 51858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19811 /* 51861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19812 /* 51865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19813 /* 51870 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19814 /* 51874 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19815 /* 51878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19816 /* 51880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
19817 /* 51883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19818 /* 51885 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19819 /* 51887 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19820 /* 51890 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19821 /* 51892 */ GIR_RootConstrainSelectedInstOperands,
19822 /* 51893 */ // GIR_Coverage, 1817,
19823 /* 51893 */ GIR_EraseRootFromParent_Done,
19824 /* 51894 */ // Label 1422: @51894
19825 /* 51894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(51970), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1819 //
19826 /* 51901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19827 /* 51905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19828 /* 51909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19829 /* 51913 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19830 /* 51917 */ // MIs[1] Operand 1
19831 /* 51917 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19832 /* 51922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19833 /* 51927 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19834 /* 51932 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19835 /* 51934 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19836 /* 51934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19837 /* 51937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19838 /* 51941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
19839 /* 51946 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19840 /* 51950 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19841 /* 51954 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19842 /* 51956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
19843 /* 51959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19844 /* 51961 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
19845 /* 51963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19846 /* 51966 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
19847 /* 51968 */ GIR_RootConstrainSelectedInstOperands,
19848 /* 51969 */ // GIR_Coverage, 1819,
19849 /* 51969 */ GIR_EraseRootFromParent_Done,
19850 /* 51970 */ // Label 1423: @51970
19851 /* 51970 */ GIM_Reject,
19852 /* 51971 */ // Label 1411: @51971
19853 /* 51971 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(52461),
19854 /* 51976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19855 /* 51980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19856 /* 51984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19857 /* 51988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(52047), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2002 //
19858 /* 51995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19859 /* 51999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19860 /* 52003 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19861 /* 52007 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19862 /* 52011 */ // MIs[1] Operand 1
19863 /* 52011 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19864 /* 52016 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19865 /* 52021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19866 /* 52026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19867 /* 52028 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19868 /* 52028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
19869 /* 52031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19870 /* 52033 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19871 /* 52035 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19872 /* 52037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19873 /* 52041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19874 /* 52045 */ GIR_RootConstrainSelectedInstOperands,
19875 /* 52046 */ // GIR_Coverage, 2002,
19876 /* 52046 */ GIR_EraseRootFromParent_Done,
19877 /* 52047 */ // Label 1425: @52047
19878 /* 52047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1426*/ GIMT_Encode4(52106), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2003 //
19879 /* 52054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19880 /* 52058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19881 /* 52062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19882 /* 52066 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19883 /* 52070 */ // MIs[1] Operand 1
19884 /* 52070 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19885 /* 52075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19886 /* 52080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19887 /* 52085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19888 /* 52087 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19889 /* 52087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
19890 /* 52090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19891 /* 52092 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19892 /* 52094 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19893 /* 52096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19894 /* 52100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19895 /* 52104 */ GIR_RootConstrainSelectedInstOperands,
19896 /* 52105 */ // GIR_Coverage, 2003,
19897 /* 52105 */ GIR_EraseRootFromParent_Done,
19898 /* 52106 */ // Label 1426: @52106
19899 /* 52106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1427*/ GIMT_Encode4(52165), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2004 //
19900 /* 52113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19901 /* 52117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19902 /* 52121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19903 /* 52125 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19904 /* 52129 */ // MIs[1] Operand 1
19905 /* 52129 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19906 /* 52134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19907 /* 52139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19908 /* 52144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19909 /* 52146 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19910 /* 52146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
19911 /* 52149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19912 /* 52151 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19913 /* 52153 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19914 /* 52155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19915 /* 52159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19916 /* 52163 */ GIR_RootConstrainSelectedInstOperands,
19917 /* 52164 */ // GIR_Coverage, 2004,
19918 /* 52164 */ GIR_EraseRootFromParent_Done,
19919 /* 52165 */ // Label 1427: @52165
19920 /* 52165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1428*/ GIMT_Encode4(52224), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2005 //
19921 /* 52172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19922 /* 52176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19923 /* 52180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19924 /* 52184 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19925 /* 52188 */ // MIs[1] Operand 1
19926 /* 52188 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19927 /* 52193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19928 /* 52198 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19929 /* 52203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19930 /* 52205 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19931 /* 52205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
19932 /* 52208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19933 /* 52210 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19934 /* 52212 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19935 /* 52214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19936 /* 52218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19937 /* 52222 */ GIR_RootConstrainSelectedInstOperands,
19938 /* 52223 */ // GIR_Coverage, 2005,
19939 /* 52223 */ GIR_EraseRootFromParent_Done,
19940 /* 52224 */ // Label 1428: @52224
19941 /* 52224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1429*/ GIMT_Encode4(52283), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2007 //
19942 /* 52231 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19943 /* 52235 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19944 /* 52239 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19945 /* 52243 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19946 /* 52247 */ // MIs[1] Operand 1
19947 /* 52247 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19948 /* 52252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19949 /* 52257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19950 /* 52262 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19951 /* 52264 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19952 /* 52264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
19953 /* 52267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19954 /* 52269 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19955 /* 52271 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19956 /* 52273 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19957 /* 52277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19958 /* 52281 */ GIR_RootConstrainSelectedInstOperands,
19959 /* 52282 */ // GIR_Coverage, 2007,
19960 /* 52282 */ GIR_EraseRootFromParent_Done,
19961 /* 52283 */ // Label 1429: @52283
19962 /* 52283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1430*/ GIMT_Encode4(52342), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2008 //
19963 /* 52290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19964 /* 52294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19965 /* 52298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19966 /* 52302 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19967 /* 52306 */ // MIs[1] Operand 1
19968 /* 52306 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19969 /* 52311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19970 /* 52316 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19971 /* 52321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19972 /* 52323 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19973 /* 52323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
19974 /* 52326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19975 /* 52328 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19976 /* 52330 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19977 /* 52332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19978 /* 52336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19979 /* 52340 */ GIR_RootConstrainSelectedInstOperands,
19980 /* 52341 */ // GIR_Coverage, 2008,
19981 /* 52341 */ GIR_EraseRootFromParent_Done,
19982 /* 52342 */ // Label 1430: @52342
19983 /* 52342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1431*/ GIMT_Encode4(52401), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2009 //
19984 /* 52349 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19985 /* 52353 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19986 /* 52357 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19987 /* 52361 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19988 /* 52365 */ // MIs[1] Operand 1
19989 /* 52365 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19990 /* 52370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19991 /* 52375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19992 /* 52380 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
19993 /* 52382 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19994 /* 52382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
19995 /* 52385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19996 /* 52387 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
19997 /* 52389 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
19998 /* 52391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19999 /* 52395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20000 /* 52399 */ GIR_RootConstrainSelectedInstOperands,
20001 /* 52400 */ // GIR_Coverage, 2009,
20002 /* 52400 */ GIR_EraseRootFromParent_Done,
20003 /* 52401 */ // Label 1431: @52401
20004 /* 52401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1432*/ GIMT_Encode4(52460), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2012 //
20005 /* 52408 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20006 /* 52412 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20007 /* 52416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20008 /* 52420 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20009 /* 52424 */ // MIs[1] Operand 1
20010 /* 52424 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20011 /* 52429 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20012 /* 52434 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20013 /* 52439 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20014 /* 52441 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
20015 /* 52441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
20016 /* 52444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20017 /* 52446 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20018 /* 52448 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20019 /* 52450 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
20020 /* 52454 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
20021 /* 52458 */ GIR_RootConstrainSelectedInstOperands,
20022 /* 52459 */ // GIR_Coverage, 2012,
20023 /* 52459 */ GIR_EraseRootFromParent_Done,
20024 /* 52460 */ // Label 1432: @52460
20025 /* 52460 */ GIM_Reject,
20026 /* 52461 */ // Label 1424: @52461
20027 /* 52461 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(53391),
20028 /* 52466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20029 /* 52470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20030 /* 52474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20031 /* 52478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1434*/ GIMT_Encode4(52554), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2348 //
20032 /* 52485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20033 /* 52489 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20034 /* 52493 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20035 /* 52497 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20036 /* 52501 */ // MIs[1] Operand 1
20037 /* 52501 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20038 /* 52506 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20039 /* 52511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20040 /* 52516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20041 /* 52518 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20042 /* 52518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20043 /* 52521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20044 /* 52525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20045 /* 52530 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20046 /* 52534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20047 /* 52538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20048 /* 52540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20049 /* 52543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20050 /* 52545 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20051 /* 52547 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20052 /* 52550 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20053 /* 52552 */ GIR_RootConstrainSelectedInstOperands,
20054 /* 52553 */ // GIR_Coverage, 2348,
20055 /* 52553 */ GIR_EraseRootFromParent_Done,
20056 /* 52554 */ // Label 1434: @52554
20057 /* 52554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1435*/ GIMT_Encode4(52630), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2349 //
20058 /* 52561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20059 /* 52565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20060 /* 52569 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20061 /* 52573 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20062 /* 52577 */ // MIs[1] Operand 1
20063 /* 52577 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20064 /* 52582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20065 /* 52587 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20066 /* 52592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20067 /* 52594 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20068 /* 52594 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20069 /* 52597 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20070 /* 52601 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20071 /* 52606 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20072 /* 52610 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20073 /* 52614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20074 /* 52616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20075 /* 52619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20076 /* 52621 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20077 /* 52623 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20078 /* 52626 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20079 /* 52628 */ GIR_RootConstrainSelectedInstOperands,
20080 /* 52629 */ // GIR_Coverage, 2349,
20081 /* 52629 */ GIR_EraseRootFromParent_Done,
20082 /* 52630 */ // Label 1435: @52630
20083 /* 52630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1436*/ GIMT_Encode4(52706), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2352 //
20084 /* 52637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20085 /* 52641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20086 /* 52645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20087 /* 52649 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20088 /* 52653 */ // MIs[1] Operand 1
20089 /* 52653 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20090 /* 52658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20091 /* 52663 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20092 /* 52668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20093 /* 52670 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20094 /* 52670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20095 /* 52673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20096 /* 52677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20097 /* 52682 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20098 /* 52686 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20099 /* 52690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20100 /* 52692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20101 /* 52695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20102 /* 52697 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20103 /* 52699 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20104 /* 52702 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20105 /* 52704 */ GIR_RootConstrainSelectedInstOperands,
20106 /* 52705 */ // GIR_Coverage, 2352,
20107 /* 52705 */ GIR_EraseRootFromParent_Done,
20108 /* 52706 */ // Label 1436: @52706
20109 /* 52706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1437*/ GIMT_Encode4(52782), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2353 //
20110 /* 52713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20111 /* 52717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20112 /* 52721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20113 /* 52725 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20114 /* 52729 */ // MIs[1] Operand 1
20115 /* 52729 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20116 /* 52734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20117 /* 52739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20118 /* 52744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20119 /* 52746 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20120 /* 52746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20121 /* 52749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20122 /* 52753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20123 /* 52758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20124 /* 52762 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20125 /* 52766 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20126 /* 52768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20127 /* 52771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20128 /* 52773 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20129 /* 52775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20130 /* 52778 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20131 /* 52780 */ GIR_RootConstrainSelectedInstOperands,
20132 /* 52781 */ // GIR_Coverage, 2353,
20133 /* 52781 */ GIR_EraseRootFromParent_Done,
20134 /* 52782 */ // Label 1437: @52782
20135 /* 52782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1438*/ GIMT_Encode4(52858), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2356 //
20136 /* 52789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20137 /* 52793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20138 /* 52797 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20139 /* 52801 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20140 /* 52805 */ // MIs[1] Operand 1
20141 /* 52805 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20142 /* 52810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20143 /* 52815 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20144 /* 52820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20145 /* 52822 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20146 /* 52822 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20147 /* 52825 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20148 /* 52829 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20149 /* 52834 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20150 /* 52838 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20151 /* 52842 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20152 /* 52844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20153 /* 52847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20154 /* 52849 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20155 /* 52851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20156 /* 52854 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20157 /* 52856 */ GIR_RootConstrainSelectedInstOperands,
20158 /* 52857 */ // GIR_Coverage, 2356,
20159 /* 52857 */ GIR_EraseRootFromParent_Done,
20160 /* 52858 */ // Label 1438: @52858
20161 /* 52858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(52934), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2359 //
20162 /* 52865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20163 /* 52869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20164 /* 52873 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20165 /* 52877 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20166 /* 52881 */ // MIs[1] Operand 1
20167 /* 52881 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20168 /* 52886 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20169 /* 52891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20170 /* 52896 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20171 /* 52898 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20172 /* 52898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20173 /* 52901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20174 /* 52905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20175 /* 52910 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20176 /* 52914 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20177 /* 52918 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20178 /* 52920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20179 /* 52923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20180 /* 52925 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20181 /* 52927 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20182 /* 52930 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20183 /* 52932 */ GIR_RootConstrainSelectedInstOperands,
20184 /* 52933 */ // GIR_Coverage, 2359,
20185 /* 52933 */ GIR_EraseRootFromParent_Done,
20186 /* 52934 */ // Label 1439: @52934
20187 /* 52934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(53010), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2362 //
20188 /* 52941 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20189 /* 52945 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20190 /* 52949 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20191 /* 52953 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20192 /* 52957 */ // MIs[1] Operand 1
20193 /* 52957 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20194 /* 52962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20195 /* 52967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20196 /* 52972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20197 /* 52974 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20198 /* 52974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20199 /* 52977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20200 /* 52981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20201 /* 52986 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20202 /* 52990 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20203 /* 52994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20204 /* 52996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20205 /* 52999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20206 /* 53001 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20207 /* 53003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20208 /* 53006 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20209 /* 53008 */ GIR_RootConstrainSelectedInstOperands,
20210 /* 53009 */ // GIR_Coverage, 2362,
20211 /* 53009 */ GIR_EraseRootFromParent_Done,
20212 /* 53010 */ // Label 1440: @53010
20213 /* 53010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(53086), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2363 //
20214 /* 53017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20215 /* 53021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20216 /* 53025 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20217 /* 53029 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20218 /* 53033 */ // MIs[1] Operand 1
20219 /* 53033 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20220 /* 53038 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20221 /* 53043 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20222 /* 53048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20223 /* 53050 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20224 /* 53050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20225 /* 53053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20226 /* 53057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20227 /* 53062 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20228 /* 53066 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20229 /* 53070 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20230 /* 53072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20231 /* 53075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20232 /* 53077 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20233 /* 53079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20234 /* 53082 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20235 /* 53084 */ GIR_RootConstrainSelectedInstOperands,
20236 /* 53085 */ // GIR_Coverage, 2363,
20237 /* 53085 */ GIR_EraseRootFromParent_Done,
20238 /* 53086 */ // Label 1441: @53086
20239 /* 53086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(53162), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2366 //
20240 /* 53093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20241 /* 53097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20242 /* 53101 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20243 /* 53105 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20244 /* 53109 */ // MIs[1] Operand 1
20245 /* 53109 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20246 /* 53114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20247 /* 53119 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20248 /* 53124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20249 /* 53126 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20250 /* 53126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20251 /* 53129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20252 /* 53133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20253 /* 53138 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20254 /* 53142 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20255 /* 53146 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20256 /* 53148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20257 /* 53151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20258 /* 53153 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20259 /* 53155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20260 /* 53158 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20261 /* 53160 */ GIR_RootConstrainSelectedInstOperands,
20262 /* 53161 */ // GIR_Coverage, 2366,
20263 /* 53161 */ GIR_EraseRootFromParent_Done,
20264 /* 53162 */ // Label 1442: @53162
20265 /* 53162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(53238), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2367 //
20266 /* 53169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20267 /* 53173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20268 /* 53177 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20269 /* 53181 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20270 /* 53185 */ // MIs[1] Operand 1
20271 /* 53185 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20272 /* 53190 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20273 /* 53195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20274 /* 53200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20275 /* 53202 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20276 /* 53202 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20277 /* 53205 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20278 /* 53209 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20279 /* 53214 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20280 /* 53218 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20281 /* 53222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20282 /* 53224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20283 /* 53227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20284 /* 53229 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20285 /* 53231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20286 /* 53234 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20287 /* 53236 */ GIR_RootConstrainSelectedInstOperands,
20288 /* 53237 */ // GIR_Coverage, 2367,
20289 /* 53237 */ GIR_EraseRootFromParent_Done,
20290 /* 53238 */ // Label 1443: @53238
20291 /* 53238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(53314), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2370 //
20292 /* 53245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20293 /* 53249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20294 /* 53253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20295 /* 53257 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20296 /* 53261 */ // MIs[1] Operand 1
20297 /* 53261 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20298 /* 53266 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20299 /* 53271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20300 /* 53276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20301 /* 53278 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20302 /* 53278 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20303 /* 53281 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20304 /* 53285 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20305 /* 53290 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20306 /* 53294 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20307 /* 53298 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20308 /* 53300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20309 /* 53303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20310 /* 53305 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20311 /* 53307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20312 /* 53310 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20313 /* 53312 */ GIR_RootConstrainSelectedInstOperands,
20314 /* 53313 */ // GIR_Coverage, 2370,
20315 /* 53313 */ GIR_EraseRootFromParent_Done,
20316 /* 53314 */ // Label 1444: @53314
20317 /* 53314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(53390), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2373 //
20318 /* 53321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20319 /* 53325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20320 /* 53329 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20321 /* 53333 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20322 /* 53337 */ // MIs[1] Operand 1
20323 /* 53337 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20324 /* 53342 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20325 /* 53347 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20326 /* 53352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20327 /* 53354 */ // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20328 /* 53354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20329 /* 53357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20330 /* 53361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20331 /* 53366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20332 /* 53370 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20333 /* 53374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20334 /* 53376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20335 /* 53379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20336 /* 53381 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20337 /* 53383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20338 /* 53386 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20339 /* 53388 */ GIR_RootConstrainSelectedInstOperands,
20340 /* 53389 */ // GIR_Coverage, 2373,
20341 /* 53389 */ GIR_EraseRootFromParent_Done,
20342 /* 53390 */ // Label 1445: @53390
20343 /* 53390 */ GIM_Reject,
20344 /* 53391 */ // Label 1433: @53391
20345 /* 53391 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(53865),
20346 /* 53396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20347 /* 53400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20348 /* 53404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20349 /* 53408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1447*/ GIMT_Encode4(53484), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2409 //
20350 /* 53415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20351 /* 53419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20352 /* 53423 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20353 /* 53427 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20354 /* 53431 */ // MIs[1] Operand 1
20355 /* 53431 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20356 /* 53436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20357 /* 53441 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20358 /* 53446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20359 /* 53448 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20360 /* 53448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20361 /* 53451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20362 /* 53455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20363 /* 53460 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20364 /* 53464 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20365 /* 53468 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20366 /* 53470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20367 /* 53473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20368 /* 53475 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20369 /* 53477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20370 /* 53480 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20371 /* 53482 */ GIR_RootConstrainSelectedInstOperands,
20372 /* 53483 */ // GIR_Coverage, 2409,
20373 /* 53483 */ GIR_EraseRootFromParent_Done,
20374 /* 53484 */ // Label 1447: @53484
20375 /* 53484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(53560), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2410 //
20376 /* 53491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20377 /* 53495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20378 /* 53499 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20379 /* 53503 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20380 /* 53507 */ // MIs[1] Operand 1
20381 /* 53507 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20382 /* 53512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20383 /* 53517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20384 /* 53522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20385 /* 53524 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20386 /* 53524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20387 /* 53527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20388 /* 53531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20389 /* 53536 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20390 /* 53540 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20391 /* 53544 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20392 /* 53546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20393 /* 53549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20394 /* 53551 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20395 /* 53553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20396 /* 53556 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20397 /* 53558 */ GIR_RootConstrainSelectedInstOperands,
20398 /* 53559 */ // GIR_Coverage, 2410,
20399 /* 53559 */ GIR_EraseRootFromParent_Done,
20400 /* 53560 */ // Label 1448: @53560
20401 /* 53560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(53636), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2413 //
20402 /* 53567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20403 /* 53571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20404 /* 53575 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20405 /* 53579 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20406 /* 53583 */ // MIs[1] Operand 1
20407 /* 53583 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20408 /* 53588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20409 /* 53593 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20410 /* 53598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20411 /* 53600 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20412 /* 53600 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20413 /* 53603 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20414 /* 53607 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20415 /* 53612 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20416 /* 53616 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20417 /* 53620 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20418 /* 53622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20419 /* 53625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20420 /* 53627 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20421 /* 53629 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20422 /* 53632 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20423 /* 53634 */ GIR_RootConstrainSelectedInstOperands,
20424 /* 53635 */ // GIR_Coverage, 2413,
20425 /* 53635 */ GIR_EraseRootFromParent_Done,
20426 /* 53636 */ // Label 1449: @53636
20427 /* 53636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(53712), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2414 //
20428 /* 53643 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20429 /* 53647 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20430 /* 53651 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20431 /* 53655 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20432 /* 53659 */ // MIs[1] Operand 1
20433 /* 53659 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20434 /* 53664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20435 /* 53669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20436 /* 53674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20437 /* 53676 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20438 /* 53676 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20439 /* 53679 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20440 /* 53683 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20441 /* 53688 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20442 /* 53692 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20443 /* 53696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20444 /* 53698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20445 /* 53701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20446 /* 53703 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20447 /* 53705 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20448 /* 53708 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20449 /* 53710 */ GIR_RootConstrainSelectedInstOperands,
20450 /* 53711 */ // GIR_Coverage, 2414,
20451 /* 53711 */ GIR_EraseRootFromParent_Done,
20452 /* 53712 */ // Label 1450: @53712
20453 /* 53712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(53788), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2417 //
20454 /* 53719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20455 /* 53723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20456 /* 53727 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20457 /* 53731 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20458 /* 53735 */ // MIs[1] Operand 1
20459 /* 53735 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20460 /* 53740 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20461 /* 53745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20462 /* 53750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20463 /* 53752 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20464 /* 53752 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20465 /* 53755 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20466 /* 53759 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20467 /* 53764 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20468 /* 53768 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20469 /* 53772 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20470 /* 53774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20471 /* 53777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20472 /* 53779 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20473 /* 53781 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20474 /* 53784 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20475 /* 53786 */ GIR_RootConstrainSelectedInstOperands,
20476 /* 53787 */ // GIR_Coverage, 2417,
20477 /* 53787 */ GIR_EraseRootFromParent_Done,
20478 /* 53788 */ // Label 1451: @53788
20479 /* 53788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(53864), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2419 //
20480 /* 53795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20481 /* 53799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20482 /* 53803 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20483 /* 53807 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20484 /* 53811 */ // MIs[1] Operand 1
20485 /* 53811 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20486 /* 53816 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20487 /* 53821 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20488 /* 53826 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20489 /* 53828 */ // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20490 /* 53828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20491 /* 53831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20492 /* 53835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20493 /* 53840 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20494 /* 53844 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20495 /* 53848 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20496 /* 53850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20497 /* 53853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20498 /* 53855 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20499 /* 53857 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20500 /* 53860 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20501 /* 53862 */ GIR_RootConstrainSelectedInstOperands,
20502 /* 53863 */ // GIR_Coverage, 2419,
20503 /* 53863 */ GIR_EraseRootFromParent_Done,
20504 /* 53864 */ // Label 1452: @53864
20505 /* 53864 */ GIM_Reject,
20506 /* 53865 */ // Label 1446: @53865
20507 /* 53865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(53895), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 323 //
20508 /* 53872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20509 /* 53876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20510 /* 53880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20511 /* 53884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20512 /* 53888 */ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
20513 /* 53888 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
20514 /* 53893 */ GIR_RootConstrainSelectedInstOperands,
20515 /* 53894 */ // GIR_Coverage, 323,
20516 /* 53894 */ GIR_Done,
20517 /* 53895 */ // Label 1453: @53895
20518 /* 53895 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(53989),
20519 /* 53900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20520 /* 53904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(53930), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 325 //
20521 /* 53911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20522 /* 53915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20523 /* 53919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20524 /* 53923 */ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
20525 /* 53923 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
20526 /* 53928 */ GIR_RootConstrainSelectedInstOperands,
20527 /* 53929 */ // GIR_Coverage, 325,
20528 /* 53929 */ GIR_Done,
20529 /* 53930 */ // Label 1455: @53930
20530 /* 53930 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(53988),
20531 /* 53935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
20532 /* 53939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20533 /* 53943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20534 /* 53947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(53967), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 362 //
20535 /* 53954 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20536 /* 53954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
20537 /* 53957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20538 /* 53959 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
20539 /* 53961 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
20540 /* 53963 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
20541 /* 53965 */ GIR_RootConstrainSelectedInstOperands,
20542 /* 53966 */ // GIR_Coverage, 362,
20543 /* 53966 */ GIR_EraseRootFromParent_Done,
20544 /* 53967 */ // Label 1457: @53967
20545 /* 53967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(53987), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1235 //
20546 /* 53974 */ // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20547 /* 53974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
20548 /* 53977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20549 /* 53979 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
20550 /* 53981 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
20551 /* 53983 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
20552 /* 53985 */ GIR_RootConstrainSelectedInstOperands,
20553 /* 53986 */ // GIR_Coverage, 1235,
20554 /* 53986 */ GIR_EraseRootFromParent_Done,
20555 /* 53987 */ // Label 1458: @53987
20556 /* 53987 */ GIM_Reject,
20557 /* 53988 */ // Label 1456: @53988
20558 /* 53988 */ GIM_Reject,
20559 /* 53989 */ // Label 1454: @53989
20560 /* 53989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(54025), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1752 //
20561 /* 53996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20562 /* 54000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20563 /* 54004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20564 /* 54008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20565 /* 54012 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20566 /* 54012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20567 /* 54015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20568 /* 54017 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20569 /* 54019 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20570 /* 54021 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20571 /* 54023 */ GIR_RootConstrainSelectedInstOperands,
20572 /* 54024 */ // GIR_Coverage, 1752,
20573 /* 54024 */ GIR_EraseRootFromParent_Done,
20574 /* 54025 */ // Label 1459: @54025
20575 /* 54025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(54061), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1807 //
20576 /* 54032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20577 /* 54036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20578 /* 54040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20579 /* 54044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20580 /* 54048 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20581 /* 54048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20582 /* 54051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20583 /* 54053 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20584 /* 54055 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20585 /* 54057 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20586 /* 54059 */ GIR_RootConstrainSelectedInstOperands,
20587 /* 54060 */ // GIR_Coverage, 1807,
20588 /* 54060 */ GIR_EraseRootFromParent_Done,
20589 /* 54061 */ // Label 1460: @54061
20590 /* 54061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(54097), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2014 //
20591 /* 54068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20592 /* 54072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20593 /* 54076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20594 /* 54080 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20595 /* 54084 */ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20596 /* 54084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
20597 /* 54087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20598 /* 54089 */ GIR_RootToRootCopy, /*OpIdx*/2, // x
20599 /* 54091 */ GIR_RootToRootCopy, /*OpIdx*/3, // y
20600 /* 54093 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
20601 /* 54095 */ GIR_RootConstrainSelectedInstOperands,
20602 /* 54096 */ // GIR_Coverage, 2014,
20603 /* 54096 */ GIR_EraseRootFromParent_Done,
20604 /* 54097 */ // Label 1461: @54097
20605 /* 54097 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(54159),
20606 /* 54102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20607 /* 54106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20608 /* 54110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20609 /* 54114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20610 /* 54118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(54138), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6), // Rule ID 2360 //
20611 /* 54125 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20612 /* 54125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20613 /* 54128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20614 /* 54130 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20615 /* 54132 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20616 /* 54134 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20617 /* 54136 */ GIR_RootConstrainSelectedInstOperands,
20618 /* 54137 */ // GIR_Coverage, 2360,
20619 /* 54137 */ GIR_EraseRootFromParent_Done,
20620 /* 54138 */ // Label 1463: @54138
20621 /* 54138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(54158), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2374 //
20622 /* 54145 */ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20623 /* 54145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20624 /* 54148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20625 /* 54150 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20626 /* 54152 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20627 /* 54154 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20628 /* 54156 */ GIR_RootConstrainSelectedInstOperands,
20629 /* 54157 */ // GIR_Coverage, 2374,
20630 /* 54157 */ GIR_EraseRootFromParent_Done,
20631 /* 54158 */ // Label 1464: @54158
20632 /* 54158 */ GIM_Reject,
20633 /* 54159 */ // Label 1462: @54159
20634 /* 54159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(54195), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6), // Rule ID 2420 //
20635 /* 54166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20636 /* 54170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20637 /* 54174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20638 /* 54178 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20639 /* 54182 */ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20640 /* 54182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20641 /* 54185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20642 /* 54187 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20643 /* 54189 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20644 /* 54191 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20645 /* 54193 */ GIR_RootConstrainSelectedInstOperands,
20646 /* 54194 */ // GIR_Coverage, 2420,
20647 /* 54194 */ GIR_EraseRootFromParent_Done,
20648 /* 54195 */ // Label 1465: @54195
20649 /* 54195 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(54333),
20650 /* 54200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20651 /* 54204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(54268), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1881 //
20652 /* 54211 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20653 /* 54211 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20654 /* 54214 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
20655 /* 54218 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20656 /* 54223 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20657 /* 54227 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20658 /* 54231 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20659 /* 54233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20660 /* 54236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
20661 /* 54240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20662 /* 54245 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20663 /* 54249 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20664 /* 54253 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20665 /* 54255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
20666 /* 54258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20667 /* 54260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20668 /* 54263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20669 /* 54266 */ GIR_RootConstrainSelectedInstOperands,
20670 /* 54267 */ // GIR_Coverage, 1881,
20671 /* 54267 */ GIR_EraseRootFromParent_Done,
20672 /* 54268 */ // Label 1467: @54268
20673 /* 54268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(54332), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 2437 //
20674 /* 54275 */ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20675 /* 54275 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20676 /* 54278 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
20677 /* 54282 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20678 /* 54287 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20679 /* 54291 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20680 /* 54295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20681 /* 54297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20682 /* 54300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
20683 /* 54304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
20684 /* 54309 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20685 /* 54313 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20686 /* 54317 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20687 /* 54319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
20688 /* 54322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20689 /* 54324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20690 /* 54327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20691 /* 54330 */ GIR_RootConstrainSelectedInstOperands,
20692 /* 54331 */ // GIR_Coverage, 2437,
20693 /* 54331 */ GIR_EraseRootFromParent_Done,
20694 /* 54332 */ // Label 1468: @54332
20695 /* 54332 */ GIM_Reject,
20696 /* 54333 */ // Label 1466: @54333
20697 /* 54333 */ GIM_Reject,
20698 /* 54334 */ // Label 1376: @54334
20699 /* 54334 */ GIM_Reject,
20700 /* 54335 */ // Label 1374: @54335
20701 /* 54335 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(54419),
20702 /* 54340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20703 /* 54343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20704 /* 54346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(54382), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1791 //
20705 /* 54353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20706 /* 54357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20707 /* 54361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20708 /* 54365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20709 /* 54369 */ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
20710 /* 54369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20711 /* 54372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20712 /* 54374 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20713 /* 54376 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20714 /* 54378 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20715 /* 54380 */ GIR_RootConstrainSelectedInstOperands,
20716 /* 54381 */ // GIR_Coverage, 1791,
20717 /* 54381 */ GIR_EraseRootFromParent_Done,
20718 /* 54382 */ // Label 1470: @54382
20719 /* 54382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(54418), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1820 //
20720 /* 54389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20721 /* 54393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20722 /* 54397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20723 /* 54401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20724 /* 54405 */ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
20725 /* 54405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20726 /* 54408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20727 /* 54410 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20728 /* 54412 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
20729 /* 54414 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20730 /* 54416 */ GIR_RootConstrainSelectedInstOperands,
20731 /* 54417 */ // GIR_Coverage, 1820,
20732 /* 54417 */ GIR_EraseRootFromParent_Done,
20733 /* 54418 */ // Label 1471: @54418
20734 /* 54418 */ GIM_Reject,
20735 /* 54419 */ // Label 1469: @54419
20736 /* 54419 */ GIM_Reject,
20737 /* 54420 */ // Label 1375: @54420
20738 /* 54420 */ GIM_Reject,
20739 /* 54421 */ // Label 1367: @54421
20740 /* 54421 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1474*/ GIMT_Encode4(58534),
20741 /* 54432 */ /*GILLT_s32*//*Label 1472*/ GIMT_Encode4(54440),
20742 /* 54436 */ /*GILLT_s64*//*Label 1473*/ GIMT_Encode4(58381),
20743 /* 54440 */ // Label 1472: @54440
20744 /* 54440 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(58380),
20745 /* 54445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20746 /* 54448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20747 /* 54451 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(54685),
20748 /* 54456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20749 /* 54460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20750 /* 54464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20751 /* 54468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(54522), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1779 //
20752 /* 54475 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20753 /* 54479 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20754 /* 54483 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20755 /* 54487 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20756 /* 54491 */ // MIs[1] Operand 1
20757 /* 54491 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20758 /* 54496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20759 /* 54501 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20760 /* 54505 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20761 /* 54507 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
20762 /* 54507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
20763 /* 54510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20764 /* 54512 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20765 /* 54514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20766 /* 54518 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20767 /* 54520 */ GIR_RootConstrainSelectedInstOperands,
20768 /* 54521 */ // GIR_Coverage, 1779,
20769 /* 54521 */ GIR_EraseRootFromParent_Done,
20770 /* 54522 */ // Label 1477: @54522
20771 /* 54522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(54576), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1783 //
20772 /* 54529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20773 /* 54533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20774 /* 54537 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20775 /* 54541 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20776 /* 54545 */ // MIs[1] Operand 1
20777 /* 54545 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20778 /* 54550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20779 /* 54555 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20780 /* 54559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20781 /* 54561 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
20782 /* 54561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
20783 /* 54564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20784 /* 54566 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20785 /* 54568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20786 /* 54572 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20787 /* 54574 */ GIR_RootConstrainSelectedInstOperands,
20788 /* 54575 */ // GIR_Coverage, 1783,
20789 /* 54575 */ GIR_EraseRootFromParent_Done,
20790 /* 54576 */ // Label 1478: @54576
20791 /* 54576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(54630), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1789 //
20792 /* 54583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20793 /* 54587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20794 /* 54591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20795 /* 54595 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20796 /* 54599 */ // MIs[1] Operand 1
20797 /* 54599 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20798 /* 54604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20799 /* 54609 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20800 /* 54613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20801 /* 54615 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
20802 /* 54615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
20803 /* 54618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20804 /* 54620 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20805 /* 54622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20806 /* 54626 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20807 /* 54628 */ GIR_RootConstrainSelectedInstOperands,
20808 /* 54629 */ // GIR_Coverage, 1789,
20809 /* 54629 */ GIR_EraseRootFromParent_Done,
20810 /* 54630 */ // Label 1479: @54630
20811 /* 54630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(54684), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1795 //
20812 /* 54637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20813 /* 54641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20814 /* 54645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20815 /* 54649 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20816 /* 54653 */ // MIs[1] Operand 1
20817 /* 54653 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20818 /* 54658 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20819 /* 54663 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20820 /* 54667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20821 /* 54669 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
20822 /* 54669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
20823 /* 54672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20824 /* 54674 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20825 /* 54676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20826 /* 54680 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20827 /* 54682 */ GIR_RootConstrainSelectedInstOperands,
20828 /* 54683 */ // GIR_Coverage, 1795,
20829 /* 54683 */ GIR_EraseRootFromParent_Done,
20830 /* 54684 */ // Label 1480: @54684
20831 /* 54684 */ GIM_Reject,
20832 /* 54685 */ // Label 1476: @54685
20833 /* 54685 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(54811),
20834 /* 54690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20835 /* 54694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20836 /* 54698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20837 /* 54702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(54756), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1831 //
20838 /* 54709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20839 /* 54713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20840 /* 54717 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20841 /* 54721 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20842 /* 54725 */ // MIs[1] Operand 1
20843 /* 54725 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20844 /* 54730 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20845 /* 54735 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20846 /* 54739 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20847 /* 54741 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20848 /* 54741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
20849 /* 54744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20850 /* 54746 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20851 /* 54748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20852 /* 54752 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20853 /* 54754 */ GIR_RootConstrainSelectedInstOperands,
20854 /* 54755 */ // GIR_Coverage, 1831,
20855 /* 54755 */ GIR_EraseRootFromParent_Done,
20856 /* 54756 */ // Label 1482: @54756
20857 /* 54756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(54810), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1834 //
20858 /* 54763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20859 /* 54767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20860 /* 54771 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20861 /* 54775 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20862 /* 54779 */ // MIs[1] Operand 1
20863 /* 54779 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20864 /* 54784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20865 /* 54789 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20866 /* 54793 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20867 /* 54795 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20868 /* 54795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
20869 /* 54798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20870 /* 54800 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20871 /* 54802 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20872 /* 54806 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20873 /* 54808 */ GIR_RootConstrainSelectedInstOperands,
20874 /* 54809 */ // GIR_Coverage, 1834,
20875 /* 54809 */ GIR_EraseRootFromParent_Done,
20876 /* 54810 */ // Label 1483: @54810
20877 /* 54810 */ GIM_Reject,
20878 /* 54811 */ // Label 1481: @54811
20879 /* 54811 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(55045),
20880 /* 54816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20881 /* 54820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20882 /* 54824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20883 /* 54828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(54882), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1852 //
20884 /* 54835 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20885 /* 54839 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20886 /* 54843 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20887 /* 54847 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20888 /* 54851 */ // MIs[1] Operand 1
20889 /* 54851 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20890 /* 54856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20891 /* 54861 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20892 /* 54865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20893 /* 54867 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20894 /* 54867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
20895 /* 54870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20896 /* 54872 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20897 /* 54874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20898 /* 54878 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20899 /* 54880 */ GIR_RootConstrainSelectedInstOperands,
20900 /* 54881 */ // GIR_Coverage, 1852,
20901 /* 54881 */ GIR_EraseRootFromParent_Done,
20902 /* 54882 */ // Label 1485: @54882
20903 /* 54882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1486*/ GIMT_Encode4(54936), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1854 //
20904 /* 54889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20905 /* 54893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20906 /* 54897 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20907 /* 54901 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20908 /* 54905 */ // MIs[1] Operand 1
20909 /* 54905 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20910 /* 54910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20911 /* 54915 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20912 /* 54919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20913 /* 54921 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20914 /* 54921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
20915 /* 54924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20916 /* 54926 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20917 /* 54928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20918 /* 54932 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20919 /* 54934 */ GIR_RootConstrainSelectedInstOperands,
20920 /* 54935 */ // GIR_Coverage, 1854,
20921 /* 54935 */ GIR_EraseRootFromParent_Done,
20922 /* 54936 */ // Label 1486: @54936
20923 /* 54936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(54990), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1857 //
20924 /* 54943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20925 /* 54947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20926 /* 54951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20927 /* 54955 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20928 /* 54959 */ // MIs[1] Operand 1
20929 /* 54959 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20930 /* 54964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20931 /* 54969 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20932 /* 54973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20933 /* 54975 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20934 /* 54975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
20935 /* 54978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20936 /* 54980 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20937 /* 54982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20938 /* 54986 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20939 /* 54988 */ GIR_RootConstrainSelectedInstOperands,
20940 /* 54989 */ // GIR_Coverage, 1857,
20941 /* 54989 */ GIR_EraseRootFromParent_Done,
20942 /* 54990 */ // Label 1487: @54990
20943 /* 54990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(55044), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1860 //
20944 /* 54997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20945 /* 55001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20946 /* 55005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20947 /* 55009 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20948 /* 55013 */ // MIs[1] Operand 1
20949 /* 55013 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20950 /* 55018 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20951 /* 55023 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20952 /* 55027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20953 /* 55029 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20954 /* 55029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
20955 /* 55032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20956 /* 55034 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20957 /* 55036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20958 /* 55040 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20959 /* 55042 */ GIR_RootConstrainSelectedInstOperands,
20960 /* 55043 */ // GIR_Coverage, 1860,
20961 /* 55043 */ GIR_EraseRootFromParent_Done,
20962 /* 55044 */ // Label 1488: @55044
20963 /* 55044 */ GIM_Reject,
20964 /* 55045 */ // Label 1484: @55045
20965 /* 55045 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(55171),
20966 /* 55050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20967 /* 55054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20968 /* 55058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20969 /* 55062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(55116), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2431 //
20970 /* 55069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20971 /* 55073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20972 /* 55077 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20973 /* 55081 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20974 /* 55085 */ // MIs[1] Operand 1
20975 /* 55085 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20976 /* 55090 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20977 /* 55095 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20978 /* 55099 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20979 /* 55101 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20980 /* 55101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
20981 /* 55104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20982 /* 55106 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
20983 /* 55108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20984 /* 55112 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
20985 /* 55114 */ GIR_RootConstrainSelectedInstOperands,
20986 /* 55115 */ // GIR_Coverage, 2431,
20987 /* 55115 */ GIR_EraseRootFromParent_Done,
20988 /* 55116 */ // Label 1490: @55116
20989 /* 55116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(55170), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2434 //
20990 /* 55123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20991 /* 55127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20992 /* 55131 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20993 /* 55135 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20994 /* 55139 */ // MIs[1] Operand 1
20995 /* 55139 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20996 /* 55144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20997 /* 55149 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20998 /* 55153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
20999 /* 55155 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21000 /* 55155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
21001 /* 55158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21002 /* 55160 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21003 /* 55162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21004 /* 55166 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21005 /* 55168 */ GIR_RootConstrainSelectedInstOperands,
21006 /* 55169 */ // GIR_Coverage, 2434,
21007 /* 55169 */ GIR_EraseRootFromParent_Done,
21008 /* 55170 */ // Label 1491: @55170
21009 /* 55170 */ GIM_Reject,
21010 /* 55171 */ // Label 1489: @55171
21011 /* 55171 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(56101),
21012 /* 55176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21013 /* 55180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21014 /* 55184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21015 /* 55188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(55264), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1754 //
21016 /* 55195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21017 /* 55199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21018 /* 55203 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21019 /* 55207 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21020 /* 55211 */ // MIs[1] Operand 1
21021 /* 55211 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21022 /* 55216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21023 /* 55221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21024 /* 55226 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21025 /* 55228 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21026 /* 55228 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21027 /* 55231 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21028 /* 55235 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21029 /* 55240 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21030 /* 55244 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21031 /* 55248 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21032 /* 55250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21033 /* 55253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21034 /* 55255 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21035 /* 55257 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21036 /* 55260 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21037 /* 55262 */ GIR_RootConstrainSelectedInstOperands,
21038 /* 55263 */ // GIR_Coverage, 1754,
21039 /* 55263 */ GIR_EraseRootFromParent_Done,
21040 /* 55264 */ // Label 1493: @55264
21041 /* 55264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(55340), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1755 //
21042 /* 55271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21043 /* 55275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21044 /* 55279 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21045 /* 55283 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21046 /* 55287 */ // MIs[1] Operand 1
21047 /* 55287 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21048 /* 55292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21049 /* 55297 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21050 /* 55302 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21051 /* 55304 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21052 /* 55304 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21053 /* 55307 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21054 /* 55311 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21055 /* 55316 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21056 /* 55320 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21057 /* 55324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21058 /* 55326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21059 /* 55329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21060 /* 55331 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21061 /* 55333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21062 /* 55336 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21063 /* 55338 */ GIR_RootConstrainSelectedInstOperands,
21064 /* 55339 */ // GIR_Coverage, 1755,
21065 /* 55339 */ GIR_EraseRootFromParent_Done,
21066 /* 55340 */ // Label 1494: @55340
21067 /* 55340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1495*/ GIMT_Encode4(55416), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1758 //
21068 /* 55347 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21069 /* 55351 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21070 /* 55355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21071 /* 55359 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21072 /* 55363 */ // MIs[1] Operand 1
21073 /* 55363 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21074 /* 55368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21075 /* 55373 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21076 /* 55378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21077 /* 55380 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21078 /* 55380 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21079 /* 55383 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21080 /* 55387 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21081 /* 55392 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21082 /* 55396 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21083 /* 55400 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21084 /* 55402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21085 /* 55405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21086 /* 55407 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21087 /* 55409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21088 /* 55412 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21089 /* 55414 */ GIR_RootConstrainSelectedInstOperands,
21090 /* 55415 */ // GIR_Coverage, 1758,
21091 /* 55415 */ GIR_EraseRootFromParent_Done,
21092 /* 55416 */ // Label 1495: @55416
21093 /* 55416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1496*/ GIMT_Encode4(55492), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1759 //
21094 /* 55423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21095 /* 55427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21096 /* 55431 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21097 /* 55435 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21098 /* 55439 */ // MIs[1] Operand 1
21099 /* 55439 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21100 /* 55444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21101 /* 55449 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21102 /* 55454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21103 /* 55456 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21104 /* 55456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21105 /* 55459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21106 /* 55463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21107 /* 55468 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21108 /* 55472 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21109 /* 55476 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21110 /* 55478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21111 /* 55481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21112 /* 55483 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21113 /* 55485 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21114 /* 55488 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21115 /* 55490 */ GIR_RootConstrainSelectedInstOperands,
21116 /* 55491 */ // GIR_Coverage, 1759,
21117 /* 55491 */ GIR_EraseRootFromParent_Done,
21118 /* 55492 */ // Label 1496: @55492
21119 /* 55492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1497*/ GIMT_Encode4(55568), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1770 //
21120 /* 55499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21121 /* 55503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21122 /* 55507 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21123 /* 55511 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21124 /* 55515 */ // MIs[1] Operand 1
21125 /* 55515 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21126 /* 55520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21127 /* 55525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21128 /* 55530 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21129 /* 55532 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21130 /* 55532 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21131 /* 55535 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21132 /* 55539 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21133 /* 55544 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21134 /* 55548 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21135 /* 55552 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21136 /* 55554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21137 /* 55557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21138 /* 55559 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21139 /* 55561 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21140 /* 55564 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21141 /* 55566 */ GIR_RootConstrainSelectedInstOperands,
21142 /* 55567 */ // GIR_Coverage, 1770,
21143 /* 55567 */ GIR_EraseRootFromParent_Done,
21144 /* 55568 */ // Label 1497: @55568
21145 /* 55568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1498*/ GIMT_Encode4(55644), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1771 //
21146 /* 55575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21147 /* 55579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21148 /* 55583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21149 /* 55587 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21150 /* 55591 */ // MIs[1] Operand 1
21151 /* 55591 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21152 /* 55596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21153 /* 55601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21154 /* 55606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21155 /* 55608 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21156 /* 55608 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21157 /* 55611 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21158 /* 55615 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21159 /* 55620 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21160 /* 55624 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21161 /* 55628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21162 /* 55630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21163 /* 55633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21164 /* 55635 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21165 /* 55637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21166 /* 55640 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21167 /* 55642 */ GIR_RootConstrainSelectedInstOperands,
21168 /* 55643 */ // GIR_Coverage, 1771,
21169 /* 55643 */ GIR_EraseRootFromParent_Done,
21170 /* 55644 */ // Label 1498: @55644
21171 /* 55644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1499*/ GIMT_Encode4(55720), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1774 //
21172 /* 55651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21173 /* 55655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21174 /* 55659 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21175 /* 55663 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21176 /* 55667 */ // MIs[1] Operand 1
21177 /* 55667 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21178 /* 55672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21179 /* 55677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21180 /* 55682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21181 /* 55684 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21182 /* 55684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21183 /* 55687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21184 /* 55691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21185 /* 55696 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21186 /* 55700 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21187 /* 55704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21188 /* 55706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21189 /* 55709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21190 /* 55711 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21191 /* 55713 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21192 /* 55716 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21193 /* 55718 */ GIR_RootConstrainSelectedInstOperands,
21194 /* 55719 */ // GIR_Coverage, 1774,
21195 /* 55719 */ GIR_EraseRootFromParent_Done,
21196 /* 55720 */ // Label 1499: @55720
21197 /* 55720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(55796), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1775 //
21198 /* 55727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21199 /* 55731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21200 /* 55735 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21201 /* 55739 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21202 /* 55743 */ // MIs[1] Operand 1
21203 /* 55743 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21204 /* 55748 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21205 /* 55753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21206 /* 55758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21207 /* 55760 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21208 /* 55760 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21209 /* 55763 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21210 /* 55767 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21211 /* 55772 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21212 /* 55776 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21213 /* 55780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21214 /* 55782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21215 /* 55785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21216 /* 55787 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21217 /* 55789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21218 /* 55792 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21219 /* 55794 */ GIR_RootConstrainSelectedInstOperands,
21220 /* 55795 */ // GIR_Coverage, 1775,
21221 /* 55795 */ GIR_EraseRootFromParent_Done,
21222 /* 55796 */ // Label 1500: @55796
21223 /* 55796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(55872), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1778 //
21224 /* 55803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21225 /* 55807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21226 /* 55811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21227 /* 55815 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21228 /* 55819 */ // MIs[1] Operand 1
21229 /* 55819 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21230 /* 55824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21231 /* 55829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21232 /* 55834 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21233 /* 55836 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21234 /* 55836 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21235 /* 55839 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21236 /* 55843 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21237 /* 55848 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21238 /* 55852 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21239 /* 55856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21240 /* 55858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21241 /* 55861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21242 /* 55863 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21243 /* 55865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21244 /* 55868 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21245 /* 55870 */ GIR_RootConstrainSelectedInstOperands,
21246 /* 55871 */ // GIR_Coverage, 1778,
21247 /* 55871 */ GIR_EraseRootFromParent_Done,
21248 /* 55872 */ // Label 1501: @55872
21249 /* 55872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(55948), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1782 //
21250 /* 55879 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21251 /* 55883 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21252 /* 55887 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21253 /* 55891 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21254 /* 55895 */ // MIs[1] Operand 1
21255 /* 55895 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21256 /* 55900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21257 /* 55905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21258 /* 55910 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21259 /* 55912 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21260 /* 55912 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21261 /* 55915 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21262 /* 55919 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21263 /* 55924 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21264 /* 55928 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21265 /* 55932 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21266 /* 55934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
21267 /* 55937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21268 /* 55939 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21269 /* 55941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21270 /* 55944 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21271 /* 55946 */ GIR_RootConstrainSelectedInstOperands,
21272 /* 55947 */ // GIR_Coverage, 1782,
21273 /* 55947 */ GIR_EraseRootFromParent_Done,
21274 /* 55948 */ // Label 1502: @55948
21275 /* 55948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(56024), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1787 //
21276 /* 55955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21277 /* 55959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21278 /* 55963 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21279 /* 55967 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21280 /* 55971 */ // MIs[1] Operand 1
21281 /* 55971 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21282 /* 55976 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21283 /* 55981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21284 /* 55986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21285 /* 55988 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21286 /* 55988 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21287 /* 55991 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21288 /* 55995 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21289 /* 56000 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21290 /* 56004 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21291 /* 56008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21292 /* 56010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
21293 /* 56013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21294 /* 56015 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21295 /* 56017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21296 /* 56020 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21297 /* 56022 */ GIR_RootConstrainSelectedInstOperands,
21298 /* 56023 */ // GIR_Coverage, 1787,
21299 /* 56023 */ GIR_EraseRootFromParent_Done,
21300 /* 56024 */ // Label 1503: @56024
21301 /* 56024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1504*/ GIMT_Encode4(56100), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1793 //
21302 /* 56031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21303 /* 56035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21304 /* 56039 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21305 /* 56043 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21306 /* 56047 */ // MIs[1] Operand 1
21307 /* 56047 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21308 /* 56052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21309 /* 56057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21310 /* 56062 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21311 /* 56064 */ // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21312 /* 56064 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21313 /* 56067 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21314 /* 56071 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21315 /* 56076 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21316 /* 56080 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21317 /* 56084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21318 /* 56086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
21319 /* 56089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21320 /* 56091 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21321 /* 56093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21322 /* 56096 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21323 /* 56098 */ GIR_RootConstrainSelectedInstOperands,
21324 /* 56099 */ // GIR_Coverage, 1793,
21325 /* 56099 */ GIR_EraseRootFromParent_Done,
21326 /* 56100 */ // Label 1504: @56100
21327 /* 56100 */ GIM_Reject,
21328 /* 56101 */ // Label 1492: @56101
21329 /* 56101 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(56575),
21330 /* 56106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21331 /* 56110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21332 /* 56114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21333 /* 56118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(56194), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1822 //
21334 /* 56125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21335 /* 56129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21336 /* 56133 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21337 /* 56137 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21338 /* 56141 */ // MIs[1] Operand 1
21339 /* 56141 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21340 /* 56146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21341 /* 56151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21342 /* 56156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21343 /* 56158 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21344 /* 56158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21345 /* 56161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21346 /* 56165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21347 /* 56170 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21348 /* 56174 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21349 /* 56178 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21350 /* 56180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21351 /* 56183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21352 /* 56185 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21353 /* 56187 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21354 /* 56190 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21355 /* 56192 */ GIR_RootConstrainSelectedInstOperands,
21356 /* 56193 */ // GIR_Coverage, 1822,
21357 /* 56193 */ GIR_EraseRootFromParent_Done,
21358 /* 56194 */ // Label 1506: @56194
21359 /* 56194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1507*/ GIMT_Encode4(56270), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1823 //
21360 /* 56201 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21361 /* 56205 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21362 /* 56209 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21363 /* 56213 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21364 /* 56217 */ // MIs[1] Operand 1
21365 /* 56217 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21366 /* 56222 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21367 /* 56227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21368 /* 56232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21369 /* 56234 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21370 /* 56234 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21371 /* 56237 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21372 /* 56241 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21373 /* 56246 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21374 /* 56250 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21375 /* 56254 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21376 /* 56256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21377 /* 56259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21378 /* 56261 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21379 /* 56263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21380 /* 56266 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21381 /* 56268 */ GIR_RootConstrainSelectedInstOperands,
21382 /* 56269 */ // GIR_Coverage, 1823,
21383 /* 56269 */ GIR_EraseRootFromParent_Done,
21384 /* 56270 */ // Label 1507: @56270
21385 /* 56270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(56346), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1826 //
21386 /* 56277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21387 /* 56281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21388 /* 56285 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21389 /* 56289 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21390 /* 56293 */ // MIs[1] Operand 1
21391 /* 56293 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21392 /* 56298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21393 /* 56303 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21394 /* 56308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21395 /* 56310 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21396 /* 56310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21397 /* 56313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21398 /* 56317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21399 /* 56322 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21400 /* 56326 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21401 /* 56330 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21402 /* 56332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21403 /* 56335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21404 /* 56337 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21405 /* 56339 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21406 /* 56342 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21407 /* 56344 */ GIR_RootConstrainSelectedInstOperands,
21408 /* 56345 */ // GIR_Coverage, 1826,
21409 /* 56345 */ GIR_EraseRootFromParent_Done,
21410 /* 56346 */ // Label 1508: @56346
21411 /* 56346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(56422), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1827 //
21412 /* 56353 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21413 /* 56357 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21414 /* 56361 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21415 /* 56365 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21416 /* 56369 */ // MIs[1] Operand 1
21417 /* 56369 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21418 /* 56374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21419 /* 56379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21420 /* 56384 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21421 /* 56386 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21422 /* 56386 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21423 /* 56389 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21424 /* 56393 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21425 /* 56398 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21426 /* 56402 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21427 /* 56406 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21428 /* 56408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21429 /* 56411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21430 /* 56413 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21431 /* 56415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21432 /* 56418 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21433 /* 56420 */ GIR_RootConstrainSelectedInstOperands,
21434 /* 56421 */ // GIR_Coverage, 1827,
21435 /* 56421 */ GIR_EraseRootFromParent_Done,
21436 /* 56422 */ // Label 1509: @56422
21437 /* 56422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(56498), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1830 //
21438 /* 56429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21439 /* 56433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21440 /* 56437 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21441 /* 56441 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21442 /* 56445 */ // MIs[1] Operand 1
21443 /* 56445 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21444 /* 56450 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21445 /* 56455 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21446 /* 56460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21447 /* 56462 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21448 /* 56462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21449 /* 56465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21450 /* 56469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21451 /* 56474 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21452 /* 56478 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21453 /* 56482 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21454 /* 56484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21455 /* 56487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21456 /* 56489 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21457 /* 56491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21458 /* 56494 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21459 /* 56496 */ GIR_RootConstrainSelectedInstOperands,
21460 /* 56497 */ // GIR_Coverage, 1830,
21461 /* 56497 */ GIR_EraseRootFromParent_Done,
21462 /* 56498 */ // Label 1510: @56498
21463 /* 56498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(56574), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1832 //
21464 /* 56505 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21465 /* 56509 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21466 /* 56513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21467 /* 56517 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21468 /* 56521 */ // MIs[1] Operand 1
21469 /* 56521 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21470 /* 56526 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21471 /* 56531 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21472 /* 56536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21473 /* 56538 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21474 /* 56538 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21475 /* 56541 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21476 /* 56545 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21477 /* 56550 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21478 /* 56554 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21479 /* 56558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21480 /* 56560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
21481 /* 56563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21482 /* 56565 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21483 /* 56567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21484 /* 56570 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21485 /* 56572 */ GIR_RootConstrainSelectedInstOperands,
21486 /* 56573 */ // GIR_Coverage, 1832,
21487 /* 56573 */ GIR_EraseRootFromParent_Done,
21488 /* 56574 */ // Label 1511: @56574
21489 /* 56574 */ GIM_Reject,
21490 /* 56575 */ // Label 1505: @56575
21491 /* 56575 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(57505),
21492 /* 56580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21493 /* 56584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21494 /* 56588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21495 /* 56592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(56668), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1835 //
21496 /* 56599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21497 /* 56603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21498 /* 56607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21499 /* 56611 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21500 /* 56615 */ // MIs[1] Operand 1
21501 /* 56615 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21502 /* 56620 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21503 /* 56625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21504 /* 56630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21505 /* 56632 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21506 /* 56632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21507 /* 56635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21508 /* 56639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21509 /* 56644 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21510 /* 56648 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21511 /* 56652 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21512 /* 56654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21513 /* 56657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21514 /* 56659 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21515 /* 56661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21516 /* 56664 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21517 /* 56666 */ GIR_RootConstrainSelectedInstOperands,
21518 /* 56667 */ // GIR_Coverage, 1835,
21519 /* 56667 */ GIR_EraseRootFromParent_Done,
21520 /* 56668 */ // Label 1513: @56668
21521 /* 56668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(56744), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1836 //
21522 /* 56675 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21523 /* 56679 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21524 /* 56683 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21525 /* 56687 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21526 /* 56691 */ // MIs[1] Operand 1
21527 /* 56691 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21528 /* 56696 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21529 /* 56701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21530 /* 56706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21531 /* 56708 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21532 /* 56708 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21533 /* 56711 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21534 /* 56715 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21535 /* 56720 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21536 /* 56724 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21537 /* 56728 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21538 /* 56730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21539 /* 56733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21540 /* 56735 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21541 /* 56737 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21542 /* 56740 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21543 /* 56742 */ GIR_RootConstrainSelectedInstOperands,
21544 /* 56743 */ // GIR_Coverage, 1836,
21545 /* 56743 */ GIR_EraseRootFromParent_Done,
21546 /* 56744 */ // Label 1514: @56744
21547 /* 56744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1515*/ GIMT_Encode4(56820), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1839 //
21548 /* 56751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21549 /* 56755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21550 /* 56759 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21551 /* 56763 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21552 /* 56767 */ // MIs[1] Operand 1
21553 /* 56767 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21554 /* 56772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21555 /* 56777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21556 /* 56782 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21557 /* 56784 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21558 /* 56784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21559 /* 56787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21560 /* 56791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21561 /* 56796 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21562 /* 56800 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21563 /* 56804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21564 /* 56806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21565 /* 56809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21566 /* 56811 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21567 /* 56813 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21568 /* 56816 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21569 /* 56818 */ GIR_RootConstrainSelectedInstOperands,
21570 /* 56819 */ // GIR_Coverage, 1839,
21571 /* 56819 */ GIR_EraseRootFromParent_Done,
21572 /* 56820 */ // Label 1515: @56820
21573 /* 56820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(56896), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1840 //
21574 /* 56827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21575 /* 56831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21576 /* 56835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21577 /* 56839 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21578 /* 56843 */ // MIs[1] Operand 1
21579 /* 56843 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21580 /* 56848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21581 /* 56853 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21582 /* 56858 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21583 /* 56860 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21584 /* 56860 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21585 /* 56863 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21586 /* 56867 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21587 /* 56872 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21588 /* 56876 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21589 /* 56880 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21590 /* 56882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21591 /* 56885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21592 /* 56887 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21593 /* 56889 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21594 /* 56892 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21595 /* 56894 */ GIR_RootConstrainSelectedInstOperands,
21596 /* 56895 */ // GIR_Coverage, 1840,
21597 /* 56895 */ GIR_EraseRootFromParent_Done,
21598 /* 56896 */ // Label 1516: @56896
21599 /* 56896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(56972), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1843 //
21600 /* 56903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21601 /* 56907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21602 /* 56911 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21603 /* 56915 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21604 /* 56919 */ // MIs[1] Operand 1
21605 /* 56919 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21606 /* 56924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21607 /* 56929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21608 /* 56934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21609 /* 56936 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21610 /* 56936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21611 /* 56939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21612 /* 56943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21613 /* 56948 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21614 /* 56952 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21615 /* 56956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21616 /* 56958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21617 /* 56961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21618 /* 56963 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21619 /* 56965 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21620 /* 56968 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21621 /* 56970 */ GIR_RootConstrainSelectedInstOperands,
21622 /* 56971 */ // GIR_Coverage, 1843,
21623 /* 56971 */ GIR_EraseRootFromParent_Done,
21624 /* 56972 */ // Label 1517: @56972
21625 /* 56972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(57048), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1844 //
21626 /* 56979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21627 /* 56983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21628 /* 56987 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21629 /* 56991 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21630 /* 56995 */ // MIs[1] Operand 1
21631 /* 56995 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21632 /* 57000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21633 /* 57005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21634 /* 57010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21635 /* 57012 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21636 /* 57012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21637 /* 57015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21638 /* 57019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21639 /* 57024 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21640 /* 57028 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21641 /* 57032 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21642 /* 57034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21643 /* 57037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21644 /* 57039 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21645 /* 57041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21646 /* 57044 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21647 /* 57046 */ GIR_RootConstrainSelectedInstOperands,
21648 /* 57047 */ // GIR_Coverage, 1844,
21649 /* 57047 */ GIR_EraseRootFromParent_Done,
21650 /* 57048 */ // Label 1518: @57048
21651 /* 57048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(57124), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1847 //
21652 /* 57055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21653 /* 57059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21654 /* 57063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21655 /* 57067 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21656 /* 57071 */ // MIs[1] Operand 1
21657 /* 57071 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21658 /* 57076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21659 /* 57081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21660 /* 57086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21661 /* 57088 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21662 /* 57088 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21663 /* 57091 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21664 /* 57095 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21665 /* 57100 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21666 /* 57104 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21667 /* 57108 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21668 /* 57110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21669 /* 57113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21670 /* 57115 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21671 /* 57117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21672 /* 57120 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21673 /* 57122 */ GIR_RootConstrainSelectedInstOperands,
21674 /* 57123 */ // GIR_Coverage, 1847,
21675 /* 57123 */ GIR_EraseRootFromParent_Done,
21676 /* 57124 */ // Label 1519: @57124
21677 /* 57124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(57200), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1848 //
21678 /* 57131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21679 /* 57135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21680 /* 57139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21681 /* 57143 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21682 /* 57147 */ // MIs[1] Operand 1
21683 /* 57147 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21684 /* 57152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21685 /* 57157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21686 /* 57162 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21687 /* 57164 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21688 /* 57164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21689 /* 57167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21690 /* 57171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21691 /* 57176 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21692 /* 57180 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21693 /* 57184 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21694 /* 57186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21695 /* 57189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21696 /* 57191 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21697 /* 57193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21698 /* 57196 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21699 /* 57198 */ GIR_RootConstrainSelectedInstOperands,
21700 /* 57199 */ // GIR_Coverage, 1848,
21701 /* 57199 */ GIR_EraseRootFromParent_Done,
21702 /* 57200 */ // Label 1520: @57200
21703 /* 57200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(57276), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1851 //
21704 /* 57207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21705 /* 57211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21706 /* 57215 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21707 /* 57219 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21708 /* 57223 */ // MIs[1] Operand 1
21709 /* 57223 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21710 /* 57228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21711 /* 57233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21712 /* 57238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21713 /* 57240 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21714 /* 57240 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21715 /* 57243 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21716 /* 57247 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21717 /* 57252 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21718 /* 57256 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21719 /* 57260 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21720 /* 57262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21721 /* 57265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21722 /* 57267 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21723 /* 57269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21724 /* 57272 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21725 /* 57274 */ GIR_RootConstrainSelectedInstOperands,
21726 /* 57275 */ // GIR_Coverage, 1851,
21727 /* 57275 */ GIR_EraseRootFromParent_Done,
21728 /* 57276 */ // Label 1521: @57276
21729 /* 57276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1522*/ GIMT_Encode4(57352), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1853 //
21730 /* 57283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21731 /* 57287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21732 /* 57291 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21733 /* 57295 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21734 /* 57299 */ // MIs[1] Operand 1
21735 /* 57299 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21736 /* 57304 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21737 /* 57309 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21738 /* 57314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21739 /* 57316 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21740 /* 57316 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21741 /* 57319 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21742 /* 57323 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21743 /* 57328 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21744 /* 57332 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21745 /* 57336 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21746 /* 57338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
21747 /* 57341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21748 /* 57343 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21749 /* 57345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21750 /* 57348 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21751 /* 57350 */ GIR_RootConstrainSelectedInstOperands,
21752 /* 57351 */ // GIR_Coverage, 1853,
21753 /* 57351 */ GIR_EraseRootFromParent_Done,
21754 /* 57352 */ // Label 1522: @57352
21755 /* 57352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1523*/ GIMT_Encode4(57428), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1855 //
21756 /* 57359 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21757 /* 57363 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21758 /* 57367 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21759 /* 57371 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21760 /* 57375 */ // MIs[1] Operand 1
21761 /* 57375 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21762 /* 57380 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21763 /* 57385 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21764 /* 57390 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21765 /* 57392 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21766 /* 57392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21767 /* 57395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21768 /* 57399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21769 /* 57404 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21770 /* 57408 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21771 /* 57412 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21772 /* 57414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
21773 /* 57417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21774 /* 57419 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21775 /* 57421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21776 /* 57424 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21777 /* 57426 */ GIR_RootConstrainSelectedInstOperands,
21778 /* 57427 */ // GIR_Coverage, 1855,
21779 /* 57427 */ GIR_EraseRootFromParent_Done,
21780 /* 57428 */ // Label 1523: @57428
21781 /* 57428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1524*/ GIMT_Encode4(57504), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1858 //
21782 /* 57435 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21783 /* 57439 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21784 /* 57443 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21785 /* 57447 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21786 /* 57451 */ // MIs[1] Operand 1
21787 /* 57451 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21788 /* 57456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21789 /* 57461 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21790 /* 57466 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21791 /* 57468 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21792 /* 57468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21793 /* 57471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21794 /* 57475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21795 /* 57480 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21796 /* 57484 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21797 /* 57488 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21798 /* 57490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
21799 /* 57493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21800 /* 57495 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21801 /* 57497 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21802 /* 57500 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21803 /* 57502 */ GIR_RootConstrainSelectedInstOperands,
21804 /* 57503 */ // GIR_Coverage, 1858,
21805 /* 57503 */ GIR_EraseRootFromParent_Done,
21806 /* 57504 */ // Label 1524: @57504
21807 /* 57504 */ GIM_Reject,
21808 /* 57505 */ // Label 1512: @57505
21809 /* 57505 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(57979),
21810 /* 57510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21811 /* 57514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21812 /* 57518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21813 /* 57522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1526*/ GIMT_Encode4(57598), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2422 //
21814 /* 57529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21815 /* 57533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21816 /* 57537 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21817 /* 57541 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21818 /* 57545 */ // MIs[1] Operand 1
21819 /* 57545 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21820 /* 57550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21821 /* 57555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21822 /* 57560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21823 /* 57562 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21824 /* 57562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21825 /* 57565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21826 /* 57569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21827 /* 57574 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21828 /* 57578 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21829 /* 57582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21830 /* 57584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21831 /* 57587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21832 /* 57589 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21833 /* 57591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21834 /* 57594 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21835 /* 57596 */ GIR_RootConstrainSelectedInstOperands,
21836 /* 57597 */ // GIR_Coverage, 2422,
21837 /* 57597 */ GIR_EraseRootFromParent_Done,
21838 /* 57598 */ // Label 1526: @57598
21839 /* 57598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1527*/ GIMT_Encode4(57674), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2423 //
21840 /* 57605 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21841 /* 57609 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21842 /* 57613 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21843 /* 57617 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21844 /* 57621 */ // MIs[1] Operand 1
21845 /* 57621 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21846 /* 57626 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21847 /* 57631 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21848 /* 57636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21849 /* 57638 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21850 /* 57638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21851 /* 57641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21852 /* 57645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21853 /* 57650 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21854 /* 57654 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21855 /* 57658 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21856 /* 57660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21857 /* 57663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21858 /* 57665 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21859 /* 57667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21860 /* 57670 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21861 /* 57672 */ GIR_RootConstrainSelectedInstOperands,
21862 /* 57673 */ // GIR_Coverage, 2423,
21863 /* 57673 */ GIR_EraseRootFromParent_Done,
21864 /* 57674 */ // Label 1527: @57674
21865 /* 57674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1528*/ GIMT_Encode4(57750), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2426 //
21866 /* 57681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21867 /* 57685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21868 /* 57689 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21869 /* 57693 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21870 /* 57697 */ // MIs[1] Operand 1
21871 /* 57697 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21872 /* 57702 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21873 /* 57707 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21874 /* 57712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21875 /* 57714 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21876 /* 57714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21877 /* 57717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
21878 /* 57721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21879 /* 57726 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21880 /* 57730 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21881 /* 57734 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21882 /* 57736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21883 /* 57739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21884 /* 57741 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21885 /* 57743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21886 /* 57746 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21887 /* 57748 */ GIR_RootConstrainSelectedInstOperands,
21888 /* 57749 */ // GIR_Coverage, 2426,
21889 /* 57749 */ GIR_EraseRootFromParent_Done,
21890 /* 57750 */ // Label 1528: @57750
21891 /* 57750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1529*/ GIMT_Encode4(57826), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2427 //
21892 /* 57757 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21893 /* 57761 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21894 /* 57765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21895 /* 57769 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21896 /* 57773 */ // MIs[1] Operand 1
21897 /* 57773 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21898 /* 57778 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21899 /* 57783 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21900 /* 57788 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21901 /* 57790 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21902 /* 57790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21903 /* 57793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
21904 /* 57797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21905 /* 57802 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21906 /* 57806 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21907 /* 57810 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21908 /* 57812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21909 /* 57815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21910 /* 57817 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21911 /* 57819 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21912 /* 57822 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21913 /* 57824 */ GIR_RootConstrainSelectedInstOperands,
21914 /* 57825 */ // GIR_Coverage, 2427,
21915 /* 57825 */ GIR_EraseRootFromParent_Done,
21916 /* 57826 */ // Label 1529: @57826
21917 /* 57826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1530*/ GIMT_Encode4(57902), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2430 //
21918 /* 57833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21919 /* 57837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21920 /* 57841 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21921 /* 57845 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21922 /* 57849 */ // MIs[1] Operand 1
21923 /* 57849 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21924 /* 57854 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21925 /* 57859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21926 /* 57864 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21927 /* 57866 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21928 /* 57866 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21929 /* 57869 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21930 /* 57873 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21931 /* 57878 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21932 /* 57882 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21933 /* 57886 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21934 /* 57888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
21935 /* 57891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21936 /* 57893 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21937 /* 57895 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21938 /* 57898 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21939 /* 57900 */ GIR_RootConstrainSelectedInstOperands,
21940 /* 57901 */ // GIR_Coverage, 2430,
21941 /* 57901 */ GIR_EraseRootFromParent_Done,
21942 /* 57902 */ // Label 1530: @57902
21943 /* 57902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1531*/ GIMT_Encode4(57978), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2432 //
21944 /* 57909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21945 /* 57913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21946 /* 57917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21947 /* 57921 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21948 /* 57925 */ // MIs[1] Operand 1
21949 /* 57925 */ GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21950 /* 57930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21951 /* 57935 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21952 /* 57940 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
21953 /* 57942 */ // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21954 /* 57942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21955 /* 57945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
21956 /* 57949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
21957 /* 57954 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21958 /* 57958 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21959 /* 57962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21960 /* 57964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
21961 /* 57967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21962 /* 57969 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
21963 /* 57971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21964 /* 57974 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
21965 /* 57976 */ GIR_RootConstrainSelectedInstOperands,
21966 /* 57977 */ // GIR_Coverage, 2432,
21967 /* 57977 */ GIR_EraseRootFromParent_Done,
21968 /* 57978 */ // Label 1531: @57978
21969 /* 57978 */ GIM_Reject,
21970 /* 57979 */ // Label 1525: @57979
21971 /* 57979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1532*/ GIMT_Encode4(58009), GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32), // Rule ID 324 //
21972 /* 57986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21973 /* 57990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21974 /* 57994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21975 /* 57998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21976 /* 58002 */ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
21977 /* 58002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
21978 /* 58007 */ GIR_RootConstrainSelectedInstOperands,
21979 /* 58008 */ // GIR_Coverage, 324,
21980 /* 58008 */ GIR_Done,
21981 /* 58009 */ // Label 1532: @58009
21982 /* 58009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1533*/ GIMT_Encode4(58039), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotMips4_32), // Rule ID 326 //
21983 /* 58016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21984 /* 58020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21985 /* 58024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21986 /* 58028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21987 /* 58032 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
21988 /* 58032 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
21989 /* 58037 */ GIR_RootConstrainSelectedInstOperands,
21990 /* 58038 */ // GIR_Coverage, 326,
21991 /* 58038 */ GIR_Done,
21992 /* 58039 */ // Label 1533: @58039
21993 /* 58039 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(58133),
21994 /* 58044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21995 /* 58048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1535*/ GIMT_Encode4(58074), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotMips4_32), // Rule ID 327 //
21996 /* 58055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21997 /* 58059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21998 /* 58063 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21999 /* 58067 */ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
22000 /* 58067 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
22001 /* 58072 */ GIR_RootConstrainSelectedInstOperands,
22002 /* 58073 */ // GIR_Coverage, 327,
22003 /* 58073 */ GIR_Done,
22004 /* 58074 */ // Label 1535: @58074
22005 /* 58074 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(58132),
22006 /* 58079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
22007 /* 58083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22008 /* 58087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22009 /* 58091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1537*/ GIMT_Encode4(58111), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 361 //
22010 /* 58098 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22011 /* 58098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D),
22012 /* 58101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22013 /* 58103 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22014 /* 58105 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22015 /* 58107 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22016 /* 58109 */ GIR_RootConstrainSelectedInstOperands,
22017 /* 58110 */ // GIR_Coverage, 361,
22018 /* 58110 */ GIR_EraseRootFromParent_Done,
22019 /* 58111 */ // Label 1537: @58111
22020 /* 58111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1538*/ GIMT_Encode4(58131), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1236 //
22021 /* 58118 */ // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) => (SEL_D_MMR6:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22022 /* 58118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D_MMR6),
22023 /* 58121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22024 /* 58123 */ GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
22025 /* 58125 */ GIR_RootToRootCopy, /*OpIdx*/3, // fs
22026 /* 58127 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22027 /* 58129 */ GIR_RootConstrainSelectedInstOperands,
22028 /* 58130 */ // GIR_Coverage, 1236,
22029 /* 58130 */ GIR_EraseRootFromParent_Done,
22030 /* 58131 */ // Label 1538: @58131
22031 /* 58131 */ GIM_Reject,
22032 /* 58132 */ // Label 1536: @58132
22033 /* 58132 */ GIM_Reject,
22034 /* 58133 */ // Label 1534: @58133
22035 /* 58133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1539*/ GIMT_Encode4(58169), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1788 //
22036 /* 58140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22037 /* 58144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22038 /* 58148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22039 /* 58152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22040 /* 58156 */ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
22041 /* 58156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22042 /* 58159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22043 /* 58161 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22044 /* 58163 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22045 /* 58165 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22046 /* 58167 */ GIR_RootConstrainSelectedInstOperands,
22047 /* 58168 */ // GIR_Coverage, 1788,
22048 /* 58168 */ GIR_EraseRootFromParent_Done,
22049 /* 58169 */ // Label 1539: @58169
22050 /* 58169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1540*/ GIMT_Encode4(58205), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1833 //
22051 /* 58176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22052 /* 58180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22053 /* 58184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22054 /* 58188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22055 /* 58192 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22056 /* 58192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22057 /* 58195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22058 /* 58197 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22059 /* 58199 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22060 /* 58201 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22061 /* 58203 */ GIR_RootConstrainSelectedInstOperands,
22062 /* 58204 */ // GIR_Coverage, 1833,
22063 /* 58204 */ GIR_EraseRootFromParent_Done,
22064 /* 58205 */ // Label 1540: @58205
22065 /* 58205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1541*/ GIMT_Encode4(58241), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1856 //
22066 /* 58212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22067 /* 58216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22068 /* 58220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22069 /* 58224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22070 /* 58228 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
22071 /* 58228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22072 /* 58231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22073 /* 58233 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22074 /* 58235 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22075 /* 58237 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22076 /* 58239 */ GIR_RootConstrainSelectedInstOperands,
22077 /* 58240 */ // GIR_Coverage, 1856,
22078 /* 58240 */ GIR_EraseRootFromParent_Done,
22079 /* 58241 */ // Label 1541: @58241
22080 /* 58241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1542*/ GIMT_Encode4(58277), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit_NotMips32r6), // Rule ID 2433 //
22081 /* 58248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22082 /* 58252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22083 /* 58256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22084 /* 58260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22085 /* 58264 */ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22086 /* 58264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22087 /* 58267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22088 /* 58269 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22089 /* 58271 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22090 /* 58273 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22091 /* 58275 */ GIR_RootConstrainSelectedInstOperands,
22092 /* 58276 */ // GIR_Coverage, 2433,
22093 /* 58276 */ GIR_EraseRootFromParent_Done,
22094 /* 58277 */ // Label 1542: @58277
22095 /* 58277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1543*/ GIMT_Encode4(58379), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1923 //
22096 /* 58284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22097 /* 58288 */ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
22098 /* 58288 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
22099 /* 58291 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22100 /* 58295 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22101 /* 58300 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
22102 /* 58304 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
22103 /* 58306 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
22104 /* 58309 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22105 /* 58313 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22106 /* 58318 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
22107 /* 58322 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
22108 /* 58325 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
22109 /* 58327 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22110 /* 58330 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22111 /* 58334 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22112 /* 58339 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22113 /* 58343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22114 /* 58345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22115 /* 58348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22116 /* 58352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22117 /* 58357 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22118 /* 58361 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
22119 /* 58364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22120 /* 58366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22121 /* 58369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22122 /* 58371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22123 /* 58374 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
22124 /* 58377 */ GIR_RootConstrainSelectedInstOperands,
22125 /* 58378 */ // GIR_Coverage, 1923,
22126 /* 58378 */ GIR_EraseRootFromParent_Done,
22127 /* 58379 */ // Label 1543: @58379
22128 /* 58379 */ GIM_Reject,
22129 /* 58380 */ // Label 1475: @58380
22130 /* 58380 */ GIM_Reject,
22131 /* 58381 */ // Label 1473: @58381
22132 /* 58381 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(58533),
22133 /* 58386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22134 /* 58389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22135 /* 58392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1545*/ GIMT_Encode4(58428), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1794 //
22136 /* 58399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22137 /* 58403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22138 /* 58407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22139 /* 58411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22140 /* 58415 */ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
22141 /* 58415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22142 /* 58418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22143 /* 58420 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22144 /* 58422 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22145 /* 58424 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22146 /* 58426 */ GIR_RootConstrainSelectedInstOperands,
22147 /* 58427 */ // GIR_Coverage, 1794,
22148 /* 58427 */ GIR_EraseRootFromParent_Done,
22149 /* 58428 */ // Label 1545: @58428
22150 /* 58428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1546*/ GIMT_Encode4(58464), GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 1859 //
22151 /* 58435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22152 /* 58439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22153 /* 58443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22154 /* 58447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22155 /* 58451 */ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
22156 /* 58451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22157 /* 58454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22158 /* 58456 */ GIR_RootToRootCopy, /*OpIdx*/2, // T
22159 /* 58458 */ GIR_RootToRootCopy, /*OpIdx*/1, // cond
22160 /* 58460 */ GIR_RootToRootCopy, /*OpIdx*/3, // F
22161 /* 58462 */ GIR_RootConstrainSelectedInstOperands,
22162 /* 58463 */ // GIR_Coverage, 1859,
22163 /* 58463 */ GIR_EraseRootFromParent_Done,
22164 /* 58464 */ // Label 1546: @58464
22165 /* 58464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1547*/ GIMT_Encode4(58532), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc), // Rule ID 1912 //
22166 /* 58471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22167 /* 58475 */ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
22168 /* 58475 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22169 /* 58478 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22170 /* 58482 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22171 /* 58487 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22172 /* 58491 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22173 /* 58495 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22174 /* 58497 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22175 /* 58500 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22176 /* 58504 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
22177 /* 58509 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22178 /* 58513 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22179 /* 58517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22180 /* 58519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22181 /* 58522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22182 /* 58524 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22183 /* 58527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22184 /* 58530 */ GIR_RootConstrainSelectedInstOperands,
22185 /* 58531 */ // GIR_Coverage, 1912,
22186 /* 58531 */ GIR_EraseRootFromParent_Done,
22187 /* 58532 */ // Label 1547: @58532
22188 /* 58532 */ GIM_Reject,
22189 /* 58533 */ // Label 1544: @58533
22190 /* 58533 */ GIM_Reject,
22191 /* 58534 */ // Label 1474: @58534
22192 /* 58534 */ GIM_Reject,
22193 /* 58535 */ // Label 1368: @58535
22194 /* 58535 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(58626),
22195 /* 58540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
22196 /* 58543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22197 /* 58546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22198 /* 58549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22199 /* 58553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22200 /* 58557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22201 /* 58561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22202 /* 58565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(58585), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 596 //
22203 /* 58572 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22204 /* 58572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
22205 /* 58575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22206 /* 58577 */ GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
22207 /* 58579 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
22208 /* 58581 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
22209 /* 58583 */ GIR_RootConstrainSelectedInstOperands,
22210 /* 58584 */ // GIR_Coverage, 596,
22211 /* 58584 */ GIR_EraseRootFromParent_Done,
22212 /* 58585 */ // Label 1549: @58585
22213 /* 58585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1550*/ GIMT_Encode4(58605), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 598 //
22214 /* 58592 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22215 /* 58592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
22216 /* 58595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22217 /* 58597 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
22218 /* 58599 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22219 /* 58601 */ GIR_RootToRootCopy, /*OpIdx*/1, // wt
22220 /* 58603 */ GIR_RootConstrainSelectedInstOperands,
22221 /* 58604 */ // GIR_Coverage, 598,
22222 /* 58604 */ GIR_EraseRootFromParent_Done,
22223 /* 58605 */ // Label 1550: @58605
22224 /* 58605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1551*/ GIMT_Encode4(58625), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 608 //
22225 /* 58612 */ // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22226 /* 58612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
22227 /* 58615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22228 /* 58617 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22229 /* 58619 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22230 /* 58621 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22231 /* 58623 */ GIR_RootConstrainSelectedInstOperands,
22232 /* 58624 */ // GIR_Coverage, 608,
22233 /* 58624 */ GIR_EraseRootFromParent_Done,
22234 /* 58625 */ // Label 1551: @58625
22235 /* 58625 */ GIM_Reject,
22236 /* 58626 */ // Label 1548: @58626
22237 /* 58626 */ GIM_Reject,
22238 /* 58627 */ // Label 1369: @58627
22239 /* 58627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1552*/ GIMT_Encode4(58672), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 609 //
22240 /* 58634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22241 /* 58637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22242 /* 58640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22243 /* 58643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22244 /* 58647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22245 /* 58651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22246 /* 58655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22247 /* 58659 */ // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
22248 /* 58659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
22249 /* 58662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22250 /* 58664 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22251 /* 58666 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22252 /* 58668 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22253 /* 58670 */ GIR_RootConstrainSelectedInstOperands,
22254 /* 58671 */ // GIR_Coverage, 609,
22255 /* 58671 */ GIR_EraseRootFromParent_Done,
22256 /* 58672 */ // Label 1552: @58672
22257 /* 58672 */ GIM_Reject,
22258 /* 58673 */ // Label 1370: @58673
22259 /* 58673 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(58744),
22260 /* 58678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22261 /* 58681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22262 /* 58684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22263 /* 58687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22264 /* 58691 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22265 /* 58695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22266 /* 58699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22267 /* 58703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1554*/ GIMT_Encode4(58723), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 610 //
22268 /* 58710 */ // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
22269 /* 58710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
22270 /* 58713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22271 /* 58715 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22272 /* 58717 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22273 /* 58719 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22274 /* 58721 */ GIR_RootConstrainSelectedInstOperands,
22275 /* 58722 */ // GIR_Coverage, 610,
22276 /* 58722 */ GIR_EraseRootFromParent_Done,
22277 /* 58723 */ // Label 1554: @58723
22278 /* 58723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1555*/ GIMT_Encode4(58743), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 612 //
22279 /* 58730 */ // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22280 /* 58730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
22281 /* 58733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22282 /* 58735 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22283 /* 58737 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22284 /* 58739 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22285 /* 58741 */ GIR_RootConstrainSelectedInstOperands,
22286 /* 58742 */ // GIR_Coverage, 612,
22287 /* 58742 */ GIR_EraseRootFromParent_Done,
22288 /* 58743 */ // Label 1555: @58743
22289 /* 58743 */ GIM_Reject,
22290 /* 58744 */ // Label 1553: @58744
22291 /* 58744 */ GIM_Reject,
22292 /* 58745 */ // Label 1371: @58745
22293 /* 58745 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(58816),
22294 /* 58750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22295 /* 58753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22296 /* 58756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22297 /* 58759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22298 /* 58763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22299 /* 58767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22300 /* 58771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22301 /* 58775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1557*/ GIMT_Encode4(58795), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 611 //
22302 /* 58782 */ // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
22303 /* 58782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
22304 /* 58785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22305 /* 58787 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22306 /* 58789 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22307 /* 58791 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22308 /* 58793 */ GIR_RootConstrainSelectedInstOperands,
22309 /* 58794 */ // GIR_Coverage, 611,
22310 /* 58794 */ GIR_EraseRootFromParent_Done,
22311 /* 58795 */ // Label 1557: @58795
22312 /* 58795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1558*/ GIMT_Encode4(58815), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 613 //
22313 /* 58802 */ // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22314 /* 58802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
22315 /* 58805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22316 /* 58807 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22317 /* 58809 */ GIR_RootToRootCopy, /*OpIdx*/3, // ws
22318 /* 58811 */ GIR_RootToRootCopy, /*OpIdx*/2, // wt
22319 /* 58813 */ GIR_RootConstrainSelectedInstOperands,
22320 /* 58814 */ // GIR_Coverage, 613,
22321 /* 58814 */ GIR_EraseRootFromParent_Done,
22322 /* 58815 */ // Label 1558: @58815
22323 /* 58815 */ GIM_Reject,
22324 /* 58816 */ // Label 1556: @58816
22325 /* 58816 */ GIM_Reject,
22326 /* 58817 */ // Label 1372: @58817
22327 /* 58817 */ GIM_Reject,
22328 /* 58818 */ // Label 44: @58818
22329 /* 58818 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1561*/ GIMT_Encode4(58923),
22330 /* 58829 */ /*GILLT_s32*//*Label 1559*/ GIMT_Encode4(58837),
22331 /* 58833 */ /*GILLT_s64*//*Label 1560*/ GIMT_Encode4(58890),
22332 /* 58837 */ // Label 1559: @58837
22333 /* 58837 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(58889),
22334 /* 58842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22335 /* 58845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22336 /* 58848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22337 /* 58852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22338 /* 58856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22339 /* 58860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1563*/ GIMT_Encode4(58874), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 359 //
22340 /* 58867 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22341 /* 58867 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
22342 /* 58872 */ GIR_RootConstrainSelectedInstOperands,
22343 /* 58873 */ // GIR_Coverage, 359,
22344 /* 58873 */ GIR_Done,
22345 /* 58874 */ // Label 1563: @58874
22346 /* 58874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1564*/ GIMT_Encode4(58888), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1203 //
22347 /* 58881 */ // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22348 /* 58881 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
22349 /* 58886 */ GIR_RootConstrainSelectedInstOperands,
22350 /* 58887 */ // GIR_Coverage, 1203,
22351 /* 58887 */ GIR_Done,
22352 /* 58888 */ // Label 1564: @58888
22353 /* 58888 */ GIM_Reject,
22354 /* 58889 */ // Label 1562: @58889
22355 /* 58889 */ GIM_Reject,
22356 /* 58890 */ // Label 1560: @58890
22357 /* 58890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1565*/ GIMT_Encode4(58922), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 374 //
22358 /* 58897 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22359 /* 58900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22360 /* 58903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22361 /* 58907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22362 /* 58911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22363 /* 58915 */ // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22364 /* 58915 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
22365 /* 58920 */ GIR_RootConstrainSelectedInstOperands,
22366 /* 58921 */ // GIR_Coverage, 374,
22367 /* 58921 */ GIR_Done,
22368 /* 58922 */ // Label 1565: @58922
22369 /* 58922 */ GIM_Reject,
22370 /* 58923 */ // Label 1561: @58923
22371 /* 58923 */ GIM_Reject,
22372 /* 58924 */ // Label 45: @58924
22373 /* 58924 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1568*/ GIMT_Encode4(59029),
22374 /* 58935 */ /*GILLT_s32*//*Label 1566*/ GIMT_Encode4(58943),
22375 /* 58939 */ /*GILLT_s64*//*Label 1567*/ GIMT_Encode4(58996),
22376 /* 58943 */ // Label 1566: @58943
22377 /* 58943 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(58995),
22378 /* 58948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22379 /* 58951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22380 /* 58954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22381 /* 58958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22382 /* 58962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22383 /* 58966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1570*/ GIMT_Encode4(58980), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 358 //
22384 /* 58973 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22385 /* 58973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
22386 /* 58978 */ GIR_RootConstrainSelectedInstOperands,
22387 /* 58979 */ // GIR_Coverage, 358,
22388 /* 58979 */ GIR_Done,
22389 /* 58980 */ // Label 1570: @58980
22390 /* 58980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1571*/ GIMT_Encode4(58994), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1202 //
22391 /* 58987 */ // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22392 /* 58987 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
22393 /* 58992 */ GIR_RootConstrainSelectedInstOperands,
22394 /* 58993 */ // GIR_Coverage, 1202,
22395 /* 58993 */ GIR_Done,
22396 /* 58994 */ // Label 1571: @58994
22397 /* 58994 */ GIM_Reject,
22398 /* 58995 */ // Label 1569: @58995
22399 /* 58995 */ GIM_Reject,
22400 /* 58996 */ // Label 1567: @58996
22401 /* 58996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1572*/ GIMT_Encode4(59028), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 373 //
22402 /* 59003 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22403 /* 59006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22404 /* 59009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22405 /* 59013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22406 /* 59017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22407 /* 59021 */ // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22408 /* 59021 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
22409 /* 59026 */ GIR_RootConstrainSelectedInstOperands,
22410 /* 59027 */ // GIR_Coverage, 373,
22411 /* 59027 */ GIR_Done,
22412 /* 59028 */ // Label 1572: @59028
22413 /* 59028 */ GIM_Reject,
22414 /* 59029 */ // Label 1568: @59029
22415 /* 59029 */ GIM_Reject,
22416 /* 59030 */ // Label 46: @59030
22417 /* 59030 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1577*/ GIMT_Encode4(60341),
22418 /* 59041 */ /*GILLT_s32*//*Label 1573*/ GIMT_Encode4(59073),
22419 /* 59045 */ /*GILLT_s64*//*Label 1574*/ GIMT_Encode4(59382), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22420 /* 59065 */ /*GILLT_v4s32*//*Label 1575*/ GIMT_Encode4(59995),
22421 /* 59069 */ /*GILLT_v2s64*//*Label 1576*/ GIMT_Encode4(60168),
22422 /* 59073 */ // Label 1573: @59073
22423 /* 59073 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(59381),
22424 /* 59078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22425 /* 59081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22426 /* 59084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22427 /* 59088 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(59202),
22428 /* 59093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22429 /* 59097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1580*/ GIMT_Encode4(59149), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 181 //
22430 /* 59104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22431 /* 59108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22432 /* 59112 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22433 /* 59116 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22434 /* 59120 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22435 /* 59125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22436 /* 59130 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22437 /* 59132 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22438 /* 59132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22439 /* 59135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22440 /* 59137 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22441 /* 59139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22442 /* 59143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22443 /* 59147 */ GIR_RootConstrainSelectedInstOperands,
22444 /* 59148 */ // GIR_Coverage, 181,
22445 /* 59148 */ GIR_EraseRootFromParent_Done,
22446 /* 59149 */ // Label 1580: @59149
22447 /* 59149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1581*/ GIMT_Encode4(59201), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 180 //
22448 /* 59156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22449 /* 59160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22450 /* 59164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22451 /* 59168 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22452 /* 59172 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22453 /* 59177 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22454 /* 59182 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22455 /* 59184 */ // (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22456 /* 59184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22457 /* 59187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22458 /* 59189 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22459 /* 59191 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22460 /* 59195 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22461 /* 59199 */ GIR_RootConstrainSelectedInstOperands,
22462 /* 59200 */ // GIR_Coverage, 180,
22463 /* 59200 */ GIR_EraseRootFromParent_Done,
22464 /* 59201 */ // Label 1581: @59201
22465 /* 59201 */ GIM_Reject,
22466 /* 59202 */ // Label 1579: @59202
22467 /* 59202 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(59380),
22468 /* 59207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22469 /* 59211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1583*/ GIMT_Encode4(59263), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2492 //
22470 /* 59218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22471 /* 59222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22472 /* 59226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22473 /* 59230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22474 /* 59234 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22475 /* 59239 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22476 /* 59244 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22477 /* 59246 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22478 /* 59246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22479 /* 59249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22480 /* 59251 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22481 /* 59253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22482 /* 59257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22483 /* 59261 */ GIR_RootConstrainSelectedInstOperands,
22484 /* 59262 */ // GIR_Coverage, 2492,
22485 /* 59262 */ GIR_EraseRootFromParent_Done,
22486 /* 59263 */ // Label 1583: @59263
22487 /* 59263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1584*/ GIMT_Encode4(59315), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2491 //
22488 /* 59270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22489 /* 59274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22490 /* 59278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22491 /* 59282 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22492 /* 59286 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22493 /* 59291 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22494 /* 59296 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22495 /* 59298 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22496 /* 59298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22497 /* 59301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22498 /* 59303 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22499 /* 59305 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22500 /* 59309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22501 /* 59313 */ GIR_RootConstrainSelectedInstOperands,
22502 /* 59314 */ // GIR_Coverage, 2491,
22503 /* 59314 */ GIR_EraseRootFromParent_Done,
22504 /* 59315 */ // Label 1584: @59315
22505 /* 59315 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(59379),
22506 /* 59320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22507 /* 59324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1586*/ GIMT_Encode4(59342), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 155 //
22508 /* 59331 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22509 /* 59331 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
22510 /* 59336 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22511 /* 59340 */ GIR_RootConstrainSelectedInstOperands,
22512 /* 59341 */ // GIR_Coverage, 155,
22513 /* 59341 */ GIR_Done,
22514 /* 59342 */ // Label 1586: @59342
22515 /* 59342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1587*/ GIMT_Encode4(59360), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1152 //
22516 /* 59349 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22517 /* 59349 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
22518 /* 59354 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22519 /* 59358 */ GIR_RootConstrainSelectedInstOperands,
22520 /* 59359 */ // GIR_Coverage, 1152,
22521 /* 59359 */ GIR_Done,
22522 /* 59360 */ // Label 1587: @59360
22523 /* 59360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1588*/ GIMT_Encode4(59378), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1210 //
22524 /* 59367 */ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22525 /* 59367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
22526 /* 59370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22527 /* 59372 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22528 /* 59374 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
22529 /* 59376 */ GIR_RootConstrainSelectedInstOperands,
22530 /* 59377 */ // GIR_Coverage, 1210,
22531 /* 59377 */ GIR_EraseRootFromParent_Done,
22532 /* 59378 */ // Label 1588: @59378
22533 /* 59378 */ GIM_Reject,
22534 /* 59379 */ // Label 1585: @59379
22535 /* 59379 */ GIM_Reject,
22536 /* 59380 */ // Label 1582: @59380
22537 /* 59380 */ GIM_Reject,
22538 /* 59381 */ // Label 1578: @59381
22539 /* 59381 */ GIM_Reject,
22540 /* 59382 */ // Label 1574: @59382
22541 /* 59382 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(59994),
22542 /* 59387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22543 /* 59390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22544 /* 59393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(59453), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 189 //
22545 /* 59400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22546 /* 59404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22547 /* 59408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22548 /* 59412 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22549 /* 59416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22550 /* 59420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22551 /* 59425 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22552 /* 59430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22553 /* 59434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22554 /* 59436 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22555 /* 59436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22556 /* 59439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22557 /* 59441 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22558 /* 59443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22559 /* 59447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22560 /* 59451 */ GIR_RootConstrainSelectedInstOperands,
22561 /* 59452 */ // GIR_Coverage, 189,
22562 /* 59452 */ GIR_EraseRootFromParent_Done,
22563 /* 59453 */ // Label 1590: @59453
22564 /* 59453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1591*/ GIMT_Encode4(59513), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 197 //
22565 /* 59460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22566 /* 59464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22567 /* 59468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22568 /* 59472 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22569 /* 59476 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22570 /* 59480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22571 /* 59485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22572 /* 59490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22573 /* 59494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22574 /* 59496 */ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22575 /* 59496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22576 /* 59499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22577 /* 59501 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22578 /* 59503 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22579 /* 59507 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22580 /* 59511 */ GIR_RootConstrainSelectedInstOperands,
22581 /* 59512 */ // GIR_Coverage, 197,
22582 /* 59512 */ GIR_EraseRootFromParent_Done,
22583 /* 59513 */ // Label 1591: @59513
22584 /* 59513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1592*/ GIMT_Encode4(59573), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 188 //
22585 /* 59520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22586 /* 59524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22587 /* 59528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22588 /* 59532 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22589 /* 59536 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22590 /* 59540 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22591 /* 59545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22592 /* 59550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22593 /* 59554 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22594 /* 59556 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22595 /* 59556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22596 /* 59559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22597 /* 59561 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22598 /* 59563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22599 /* 59567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22600 /* 59571 */ GIR_RootConstrainSelectedInstOperands,
22601 /* 59572 */ // GIR_Coverage, 188,
22602 /* 59572 */ GIR_EraseRootFromParent_Done,
22603 /* 59573 */ // Label 1592: @59573
22604 /* 59573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1593*/ GIMT_Encode4(59633), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 196 //
22605 /* 59580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22606 /* 59584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22607 /* 59588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22608 /* 59592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22609 /* 59596 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22610 /* 59600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22611 /* 59605 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22612 /* 59610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22613 /* 59614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22614 /* 59616 */ // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22615 /* 59616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22616 /* 59619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22617 /* 59621 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22618 /* 59623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22619 /* 59627 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22620 /* 59631 */ GIR_RootConstrainSelectedInstOperands,
22621 /* 59632 */ // GIR_Coverage, 196,
22622 /* 59632 */ GIR_EraseRootFromParent_Done,
22623 /* 59633 */ // Label 1593: @59633
22624 /* 59633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1594*/ GIMT_Encode4(59693), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2496 //
22625 /* 59640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22626 /* 59644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22627 /* 59648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22628 /* 59652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22629 /* 59656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22630 /* 59660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22631 /* 59664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22632 /* 59669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22633 /* 59674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22634 /* 59676 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22635 /* 59676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22636 /* 59679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22637 /* 59681 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22638 /* 59683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22639 /* 59687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22640 /* 59691 */ GIR_RootConstrainSelectedInstOperands,
22641 /* 59692 */ // GIR_Coverage, 2496,
22642 /* 59692 */ GIR_EraseRootFromParent_Done,
22643 /* 59693 */ // Label 1594: @59693
22644 /* 59693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1595*/ GIMT_Encode4(59753), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2500 //
22645 /* 59700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22646 /* 59704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22647 /* 59708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22648 /* 59712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22649 /* 59716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22650 /* 59720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22651 /* 59724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22652 /* 59729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22653 /* 59734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22654 /* 59736 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22655 /* 59736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22656 /* 59739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22657 /* 59741 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22658 /* 59743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22659 /* 59747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22660 /* 59751 */ GIR_RootConstrainSelectedInstOperands,
22661 /* 59752 */ // GIR_Coverage, 2500,
22662 /* 59752 */ GIR_EraseRootFromParent_Done,
22663 /* 59753 */ // Label 1595: @59753
22664 /* 59753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1596*/ GIMT_Encode4(59813), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2495 //
22665 /* 59760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22666 /* 59764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22667 /* 59768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22668 /* 59772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22669 /* 59776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22670 /* 59780 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22671 /* 59784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22672 /* 59789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22673 /* 59794 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22674 /* 59796 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22675 /* 59796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22676 /* 59799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22677 /* 59801 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22678 /* 59803 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22679 /* 59807 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22680 /* 59811 */ GIR_RootConstrainSelectedInstOperands,
22681 /* 59812 */ // GIR_Coverage, 2495,
22682 /* 59812 */ GIR_EraseRootFromParent_Done,
22683 /* 59813 */ // Label 1596: @59813
22684 /* 59813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1597*/ GIMT_Encode4(59873), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2499 //
22685 /* 59820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22686 /* 59824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22687 /* 59828 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22688 /* 59832 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22689 /* 59836 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22690 /* 59840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22691 /* 59844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22692 /* 59849 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22693 /* 59854 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22694 /* 59856 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22695 /* 59856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22696 /* 59859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22697 /* 59861 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
22698 /* 59863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22699 /* 59867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22700 /* 59871 */ GIR_RootConstrainSelectedInstOperands,
22701 /* 59872 */ // GIR_Coverage, 2499,
22702 /* 59872 */ GIR_EraseRootFromParent_Done,
22703 /* 59873 */ // Label 1597: @59873
22704 /* 59873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1598*/ GIMT_Encode4(59903), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 157 //
22705 /* 59880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22706 /* 59884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22707 /* 59888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22708 /* 59892 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22709 /* 59892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
22710 /* 59897 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22711 /* 59901 */ GIR_RootConstrainSelectedInstOperands,
22712 /* 59902 */ // GIR_Coverage, 157,
22713 /* 59902 */ GIR_Done,
22714 /* 59903 */ // Label 1598: @59903
22715 /* 59903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1599*/ GIMT_Encode4(59933), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 159 //
22716 /* 59910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22717 /* 59914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22718 /* 59918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22719 /* 59922 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22720 /* 59922 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
22721 /* 59927 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22722 /* 59931 */ GIR_RootConstrainSelectedInstOperands,
22723 /* 59932 */ // GIR_Coverage, 159,
22724 /* 59932 */ GIR_Done,
22725 /* 59933 */ // Label 1599: @59933
22726 /* 59933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1600*/ GIMT_Encode4(59963), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1156 //
22727 /* 59940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22728 /* 59944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22729 /* 59948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22730 /* 59952 */ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22731 /* 59952 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
22732 /* 59957 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22733 /* 59961 */ GIR_RootConstrainSelectedInstOperands,
22734 /* 59962 */ // GIR_Coverage, 1156,
22735 /* 59962 */ GIR_Done,
22736 /* 59963 */ // Label 1600: @59963
22737 /* 59963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1601*/ GIMT_Encode4(59993), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1157 //
22738 /* 59970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22739 /* 59974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22740 /* 59978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22741 /* 59982 */ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22742 /* 59982 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
22743 /* 59987 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22744 /* 59991 */ GIR_RootConstrainSelectedInstOperands,
22745 /* 59992 */ // GIR_Coverage, 1157,
22746 /* 59992 */ GIR_Done,
22747 /* 59993 */ // Label 1601: @59993
22748 /* 59993 */ GIM_Reject,
22749 /* 59994 */ // Label 1589: @59994
22750 /* 59994 */ GIM_Reject,
22751 /* 59995 */ // Label 1575: @59995
22752 /* 59995 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(60167),
22753 /* 60000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22754 /* 60003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22755 /* 60006 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(60140),
22756 /* 60011 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
22757 /* 60015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22758 /* 60019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1604*/ GIMT_Encode4(60079), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2634 //
22759 /* 60026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22760 /* 60030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22761 /* 60034 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22762 /* 60038 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22763 /* 60042 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22764 /* 60047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22765 /* 60052 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
22766 /* 60056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22767 /* 60060 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22768 /* 60062 */ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>, MSA128WOpnd:{ *:[v4f32] }:$wd)<<P:Predicate_fadd_contract>> => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22769 /* 60062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
22770 /* 60065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22771 /* 60067 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
22772 /* 60069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22773 /* 60073 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22774 /* 60077 */ GIR_RootConstrainSelectedInstOperands,
22775 /* 60078 */ // GIR_Coverage, 2634,
22776 /* 60078 */ GIR_EraseRootFromParent_Done,
22777 /* 60079 */ // Label 1604: @60079
22778 /* 60079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1605*/ GIMT_Encode4(60139), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2122 //
22779 /* 60086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22780 /* 60090 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22781 /* 60094 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22782 /* 60098 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22783 /* 60102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22784 /* 60106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22785 /* 60111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22786 /* 60116 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
22787 /* 60120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22788 /* 60122 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22789 /* 60122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
22790 /* 60125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22791 /* 60127 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
22792 /* 60129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22793 /* 60133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22794 /* 60137 */ GIR_RootConstrainSelectedInstOperands,
22795 /* 60138 */ // GIR_Coverage, 2122,
22796 /* 60138 */ GIR_EraseRootFromParent_Done,
22797 /* 60139 */ // Label 1605: @60139
22798 /* 60139 */ GIM_Reject,
22799 /* 60140 */ // Label 1603: @60140
22800 /* 60140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1606*/ GIMT_Encode4(60166), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 698 //
22801 /* 60147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22802 /* 60151 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22803 /* 60155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22804 /* 60159 */ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22805 /* 60159 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
22806 /* 60164 */ GIR_RootConstrainSelectedInstOperands,
22807 /* 60165 */ // GIR_Coverage, 698,
22808 /* 60165 */ GIR_Done,
22809 /* 60166 */ // Label 1606: @60166
22810 /* 60166 */ GIM_Reject,
22811 /* 60167 */ // Label 1602: @60167
22812 /* 60167 */ GIM_Reject,
22813 /* 60168 */ // Label 1576: @60168
22814 /* 60168 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(60340),
22815 /* 60173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22816 /* 60176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22817 /* 60179 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(60313),
22818 /* 60184 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract),
22819 /* 60188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22820 /* 60192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1609*/ GIMT_Encode4(60252), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2635 //
22821 /* 60199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22822 /* 60203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22823 /* 60207 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22824 /* 60211 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22825 /* 60215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22826 /* 60220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22827 /* 60225 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
22828 /* 60229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22829 /* 60233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22830 /* 60235 */ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>, MSA128DOpnd:{ *:[v2f64] }:$wd)<<P:Predicate_fadd_contract>> => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22831 /* 60235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
22832 /* 60238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22833 /* 60240 */ GIR_RootToRootCopy, /*OpIdx*/2, // wd
22834 /* 60242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22835 /* 60246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22836 /* 60250 */ GIR_RootConstrainSelectedInstOperands,
22837 /* 60251 */ // GIR_Coverage, 2635,
22838 /* 60251 */ GIR_EraseRootFromParent_Done,
22839 /* 60252 */ // Label 1609: @60252
22840 /* 60252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1610*/ GIMT_Encode4(60312), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2123 //
22841 /* 60259 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22842 /* 60263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22843 /* 60267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22844 /* 60271 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22845 /* 60275 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22846 /* 60279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22847 /* 60284 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22848 /* 60289 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
22849 /* 60293 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22850 /* 60295 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22851 /* 60295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
22852 /* 60298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22853 /* 60300 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
22854 /* 60302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22855 /* 60306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22856 /* 60310 */ GIR_RootConstrainSelectedInstOperands,
22857 /* 60311 */ // GIR_Coverage, 2123,
22858 /* 60311 */ GIR_EraseRootFromParent_Done,
22859 /* 60312 */ // Label 1610: @60312
22860 /* 60312 */ GIM_Reject,
22861 /* 60313 */ // Label 1608: @60313
22862 /* 60313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1611*/ GIMT_Encode4(60339), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 699 //
22863 /* 60320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22864 /* 60324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22865 /* 60328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22866 /* 60332 */ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22867 /* 60332 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
22868 /* 60337 */ GIR_RootConstrainSelectedInstOperands,
22869 /* 60338 */ // GIR_Coverage, 699,
22870 /* 60338 */ GIR_Done,
22871 /* 60339 */ // Label 1611: @60339
22872 /* 60339 */ GIM_Reject,
22873 /* 60340 */ // Label 1607: @60340
22874 /* 60340 */ GIM_Reject,
22875 /* 60341 */ // Label 1577: @60341
22876 /* 60341 */ GIM_Reject,
22877 /* 60342 */ // Label 47: @60342
22878 /* 60342 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1616*/ GIMT_Encode4(61171),
22879 /* 60353 */ /*GILLT_s32*//*Label 1612*/ GIMT_Encode4(60385),
22880 /* 60357 */ /*GILLT_s64*//*Label 1613*/ GIMT_Encode4(60584), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22881 /* 60377 */ /*GILLT_v4s32*//*Label 1614*/ GIMT_Encode4(60957),
22882 /* 60381 */ /*GILLT_v2s64*//*Label 1615*/ GIMT_Encode4(61064),
22883 /* 60385 */ // Label 1612: @60385
22884 /* 60385 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(60583),
22885 /* 60390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22886 /* 60393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22887 /* 60396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22888 /* 60400 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(60514),
22889 /* 60405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22890 /* 60409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1619*/ GIMT_Encode4(60461), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 185 //
22891 /* 60416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22892 /* 60420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22893 /* 60424 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22894 /* 60428 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22895 /* 60432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22896 /* 60437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22897 /* 60442 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22898 /* 60444 */ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22899 /* 60444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
22900 /* 60447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22901 /* 60449 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22902 /* 60451 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22903 /* 60455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22904 /* 60459 */ GIR_RootConstrainSelectedInstOperands,
22905 /* 60460 */ // GIR_Coverage, 185,
22906 /* 60460 */ GIR_EraseRootFromParent_Done,
22907 /* 60461 */ // Label 1619: @60461
22908 /* 60461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1620*/ GIMT_Encode4(60513), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 184 //
22909 /* 60468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22910 /* 60472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
22911 /* 60476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22912 /* 60480 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22913 /* 60484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22914 /* 60489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22915 /* 60494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22916 /* 60496 */ // (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22917 /* 60496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
22918 /* 60499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22919 /* 60501 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22920 /* 60503 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22921 /* 60507 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22922 /* 60511 */ GIR_RootConstrainSelectedInstOperands,
22923 /* 60512 */ // GIR_Coverage, 184,
22924 /* 60512 */ GIR_EraseRootFromParent_Done,
22925 /* 60513 */ // Label 1620: @60513
22926 /* 60513 */ GIM_Reject,
22927 /* 60514 */ // Label 1618: @60514
22928 /* 60514 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(60582),
22929 /* 60519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22930 /* 60523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22931 /* 60527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1622*/ GIMT_Encode4(60545), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 173 //
22932 /* 60534 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22933 /* 60534 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
22934 /* 60539 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22935 /* 60543 */ GIR_RootConstrainSelectedInstOperands,
22936 /* 60544 */ // GIR_Coverage, 173,
22937 /* 60544 */ GIR_Done,
22938 /* 60545 */ // Label 1622: @60545
22939 /* 60545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1623*/ GIMT_Encode4(60563), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1155 //
22940 /* 60552 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22941 /* 60552 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
22942 /* 60557 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
22943 /* 60561 */ GIR_RootConstrainSelectedInstOperands,
22944 /* 60562 */ // GIR_Coverage, 1155,
22945 /* 60562 */ GIR_Done,
22946 /* 60563 */ // Label 1623: @60563
22947 /* 60563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1624*/ GIMT_Encode4(60581), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1211 //
22948 /* 60570 */ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22949 /* 60570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
22950 /* 60573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22951 /* 60575 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
22952 /* 60577 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
22953 /* 60579 */ GIR_RootConstrainSelectedInstOperands,
22954 /* 60580 */ // GIR_Coverage, 1211,
22955 /* 60580 */ GIR_EraseRootFromParent_Done,
22956 /* 60581 */ // Label 1624: @60581
22957 /* 60581 */ GIM_Reject,
22958 /* 60582 */ // Label 1621: @60582
22959 /* 60582 */ GIM_Reject,
22960 /* 60583 */ // Label 1617: @60583
22961 /* 60583 */ GIM_Reject,
22962 /* 60584 */ // Label 1613: @60584
22963 /* 60584 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(60956),
22964 /* 60589 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22965 /* 60592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22966 /* 60595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1626*/ GIMT_Encode4(60655), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 193 //
22967 /* 60602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22968 /* 60606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22969 /* 60610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22970 /* 60614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22971 /* 60618 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22972 /* 60622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22973 /* 60627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22974 /* 60632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22975 /* 60636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22976 /* 60638 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22977 /* 60638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
22978 /* 60641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22979 /* 60643 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
22980 /* 60645 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22981 /* 60649 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22982 /* 60653 */ GIR_RootConstrainSelectedInstOperands,
22983 /* 60654 */ // GIR_Coverage, 193,
22984 /* 60654 */ GIR_EraseRootFromParent_Done,
22985 /* 60655 */ // Label 1626: @60655
22986 /* 60655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1627*/ GIMT_Encode4(60715), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 201 //
22987 /* 60662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22988 /* 60666 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22989 /* 60670 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22990 /* 60674 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22991 /* 60678 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22992 /* 60682 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22993 /* 60687 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22994 /* 60692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22995 /* 60696 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
22996 /* 60698 */ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22997 /* 60698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
22998 /* 60701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22999 /* 60703 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23000 /* 60705 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23001 /* 60709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23002 /* 60713 */ GIR_RootConstrainSelectedInstOperands,
23003 /* 60714 */ // GIR_Coverage, 201,
23004 /* 60714 */ GIR_EraseRootFromParent_Done,
23005 /* 60715 */ // Label 1627: @60715
23006 /* 60715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1628*/ GIMT_Encode4(60775), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 192 //
23007 /* 60722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23008 /* 60726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23009 /* 60730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
23010 /* 60734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23011 /* 60738 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23012 /* 60742 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23013 /* 60747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23014 /* 60752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23015 /* 60756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23016 /* 60758 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23017 /* 60758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
23018 /* 60761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23019 /* 60763 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23020 /* 60765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23021 /* 60769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23022 /* 60773 */ GIR_RootConstrainSelectedInstOperands,
23023 /* 60774 */ // GIR_Coverage, 192,
23024 /* 60774 */ GIR_EraseRootFromParent_Done,
23025 /* 60775 */ // Label 1628: @60775
23026 /* 60775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1629*/ GIMT_Encode4(60835), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 200 //
23027 /* 60782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23028 /* 60786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23029 /* 60790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
23030 /* 60794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23031 /* 60798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23032 /* 60802 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23033 /* 60807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23034 /* 60812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23035 /* 60816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23036 /* 60818 */ // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23037 /* 60818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
23038 /* 60821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23039 /* 60823 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
23040 /* 60825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23041 /* 60829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23042 /* 60833 */ GIR_RootConstrainSelectedInstOperands,
23043 /* 60834 */ // GIR_Coverage, 200,
23044 /* 60834 */ GIR_EraseRootFromParent_Done,
23045 /* 60835 */ // Label 1629: @60835
23046 /* 60835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1630*/ GIMT_Encode4(60865), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 175 //
23047 /* 60842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23048 /* 60846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23049 /* 60850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23050 /* 60854 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23051 /* 60854 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
23052 /* 60859 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23053 /* 60863 */ GIR_RootConstrainSelectedInstOperands,
23054 /* 60864 */ // GIR_Coverage, 175,
23055 /* 60864 */ GIR_Done,
23056 /* 60865 */ // Label 1630: @60865
23057 /* 60865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1631*/ GIMT_Encode4(60895), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 177 //
23058 /* 60872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23059 /* 60876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23060 /* 60880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23061 /* 60884 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23062 /* 60884 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
23063 /* 60889 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23064 /* 60893 */ GIR_RootConstrainSelectedInstOperands,
23065 /* 60894 */ // GIR_Coverage, 177,
23066 /* 60894 */ GIR_Done,
23067 /* 60895 */ // Label 1631: @60895
23068 /* 60895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1632*/ GIMT_Encode4(60925), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1162 //
23069 /* 60902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23070 /* 60906 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23071 /* 60910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23072 /* 60914 */ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23073 /* 60914 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
23074 /* 60919 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23075 /* 60923 */ GIR_RootConstrainSelectedInstOperands,
23076 /* 60924 */ // GIR_Coverage, 1162,
23077 /* 60924 */ GIR_Done,
23078 /* 60925 */ // Label 1632: @60925
23079 /* 60925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1633*/ GIMT_Encode4(60955), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1163 //
23080 /* 60932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23081 /* 60936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23082 /* 60940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23083 /* 60944 */ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23084 /* 60944 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
23085 /* 60949 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23086 /* 60953 */ GIR_RootConstrainSelectedInstOperands,
23087 /* 60954 */ // GIR_Coverage, 1163,
23088 /* 60954 */ GIR_Done,
23089 /* 60955 */ // Label 1633: @60955
23090 /* 60955 */ GIM_Reject,
23091 /* 60956 */ // Label 1625: @60956
23092 /* 60956 */ GIM_Reject,
23093 /* 60957 */ // Label 1614: @60957
23094 /* 60957 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(61063),
23095 /* 60962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23096 /* 60965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23097 /* 60968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1635*/ GIMT_Encode4(61036), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2120 //
23098 /* 60975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23099 /* 60979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23100 /* 60983 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23101 /* 60987 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23102 /* 60991 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23103 /* 60995 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
23104 /* 60999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23105 /* 61004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23106 /* 61009 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23107 /* 61013 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
23108 /* 61017 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23109 /* 61019 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23110 /* 61019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
23111 /* 61022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23112 /* 61024 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23113 /* 61026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23114 /* 61030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23115 /* 61034 */ GIR_RootConstrainSelectedInstOperands,
23116 /* 61035 */ // GIR_Coverage, 2120,
23117 /* 61035 */ GIR_EraseRootFromParent_Done,
23118 /* 61036 */ // Label 1635: @61036
23119 /* 61036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1636*/ GIMT_Encode4(61062), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 786 //
23120 /* 61043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23121 /* 61047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23122 /* 61051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23123 /* 61055 */ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23124 /* 61055 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
23125 /* 61060 */ GIR_RootConstrainSelectedInstOperands,
23126 /* 61061 */ // GIR_Coverage, 786,
23127 /* 61061 */ GIR_Done,
23128 /* 61062 */ // Label 1636: @61062
23129 /* 61062 */ GIM_Reject,
23130 /* 61063 */ // Label 1634: @61063
23131 /* 61063 */ GIM_Reject,
23132 /* 61064 */ // Label 1615: @61064
23133 /* 61064 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(61170),
23134 /* 61069 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23135 /* 61072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23136 /* 61075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1638*/ GIMT_Encode4(61143), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2121 //
23137 /* 61082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23138 /* 61086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23139 /* 61090 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23140 /* 61094 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23141 /* 61098 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23142 /* 61102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
23143 /* 61106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23144 /* 61111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23145 /* 61116 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract),
23146 /* 61120 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract),
23147 /* 61124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23148 /* 61126 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23149 /* 61126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
23150 /* 61129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23151 /* 61131 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd
23152 /* 61133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23153 /* 61137 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23154 /* 61141 */ GIR_RootConstrainSelectedInstOperands,
23155 /* 61142 */ // GIR_Coverage, 2121,
23156 /* 61142 */ GIR_EraseRootFromParent_Done,
23157 /* 61143 */ // Label 1638: @61143
23158 /* 61143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1639*/ GIMT_Encode4(61169), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 787 //
23159 /* 61150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23160 /* 61154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23161 /* 61158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23162 /* 61162 */ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23163 /* 61162 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
23164 /* 61167 */ GIR_RootConstrainSelectedInstOperands,
23165 /* 61168 */ // GIR_Coverage, 787,
23166 /* 61168 */ GIR_Done,
23167 /* 61169 */ // Label 1639: @61169
23168 /* 61169 */ GIM_Reject,
23169 /* 61170 */ // Label 1637: @61170
23170 /* 61170 */ GIM_Reject,
23171 /* 61171 */ // Label 1616: @61171
23172 /* 61171 */ GIM_Reject,
23173 /* 61172 */ // Label 48: @61172
23174 /* 61172 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1644*/ GIMT_Encode4(61681),
23175 /* 61183 */ /*GILLT_s32*//*Label 1640*/ GIMT_Encode4(61215),
23176 /* 61187 */ /*GILLT_s64*//*Label 1641*/ GIMT_Encode4(61294), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23177 /* 61207 */ /*GILLT_v4s32*//*Label 1642*/ GIMT_Encode4(61427),
23178 /* 61211 */ /*GILLT_v2s64*//*Label 1643*/ GIMT_Encode4(61554),
23179 /* 61215 */ // Label 1640: @61215
23180 /* 61215 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(61293),
23181 /* 61220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23182 /* 61223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23183 /* 61226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23184 /* 61230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23185 /* 61234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23186 /* 61238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1646*/ GIMT_Encode4(61256), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 167 //
23187 /* 61245 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23188 /* 61245 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
23189 /* 61250 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23190 /* 61254 */ GIR_RootConstrainSelectedInstOperands,
23191 /* 61255 */ // GIR_Coverage, 167,
23192 /* 61255 */ GIR_Done,
23193 /* 61256 */ // Label 1646: @61256
23194 /* 61256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1647*/ GIMT_Encode4(61274), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1154 //
23195 /* 61263 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23196 /* 61263 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
23197 /* 61268 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23198 /* 61272 */ GIR_RootConstrainSelectedInstOperands,
23199 /* 61273 */ // GIR_Coverage, 1154,
23200 /* 61273 */ GIR_Done,
23201 /* 61274 */ // Label 1647: @61274
23202 /* 61274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1648*/ GIMT_Encode4(61292), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1212 //
23203 /* 61281 */ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23204 /* 61281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
23205 /* 61284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23206 /* 61286 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23207 /* 61288 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23208 /* 61290 */ GIR_RootConstrainSelectedInstOperands,
23209 /* 61291 */ // GIR_Coverage, 1212,
23210 /* 61291 */ GIR_EraseRootFromParent_Done,
23211 /* 61292 */ // Label 1648: @61292
23212 /* 61292 */ GIM_Reject,
23213 /* 61293 */ // Label 1645: @61293
23214 /* 61293 */ GIM_Reject,
23215 /* 61294 */ // Label 1641: @61294
23216 /* 61294 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(61426),
23217 /* 61299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23218 /* 61302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23219 /* 61305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1650*/ GIMT_Encode4(61335), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 169 //
23220 /* 61312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23221 /* 61316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23222 /* 61320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23223 /* 61324 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23224 /* 61324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
23225 /* 61329 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23226 /* 61333 */ GIR_RootConstrainSelectedInstOperands,
23227 /* 61334 */ // GIR_Coverage, 169,
23228 /* 61334 */ GIR_Done,
23229 /* 61335 */ // Label 1650: @61335
23230 /* 61335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(61365), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 171 //
23231 /* 61342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23232 /* 61346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23233 /* 61350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23234 /* 61354 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23235 /* 61354 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
23236 /* 61359 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23237 /* 61363 */ GIR_RootConstrainSelectedInstOperands,
23238 /* 61364 */ // GIR_Coverage, 171,
23239 /* 61364 */ GIR_Done,
23240 /* 61365 */ // Label 1651: @61365
23241 /* 61365 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1652*/ GIMT_Encode4(61395), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1160 //
23242 /* 61372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23243 /* 61376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23244 /* 61380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23245 /* 61384 */ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23246 /* 61384 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
23247 /* 61389 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23248 /* 61393 */ GIR_RootConstrainSelectedInstOperands,
23249 /* 61394 */ // GIR_Coverage, 1160,
23250 /* 61394 */ GIR_Done,
23251 /* 61395 */ // Label 1652: @61395
23252 /* 61395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1653*/ GIMT_Encode4(61425), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1161 //
23253 /* 61402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23254 /* 61406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23255 /* 61410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23256 /* 61414 */ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23257 /* 61414 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
23258 /* 61419 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23259 /* 61423 */ GIR_RootConstrainSelectedInstOperands,
23260 /* 61424 */ // GIR_Coverage, 1161,
23261 /* 61424 */ GIR_Done,
23262 /* 61425 */ // Label 1653: @61425
23263 /* 61425 */ GIM_Reject,
23264 /* 61426 */ // Label 1649: @61426
23265 /* 61426 */ GIM_Reject,
23266 /* 61427 */ // Label 1642: @61427
23267 /* 61427 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(61553),
23268 /* 61432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23269 /* 61435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23270 /* 61438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23271 /* 61442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1655*/ GIMT_Encode4(61485), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2537 //
23272 /* 61449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23273 /* 61453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23274 /* 61457 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23275 /* 61461 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23276 /* 61466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23277 /* 61470 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23278 /* 61472 */ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23279 /* 61472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23280 /* 61475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23281 /* 61477 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
23282 /* 61479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23283 /* 61483 */ GIR_RootConstrainSelectedInstOperands,
23284 /* 61484 */ // GIR_Coverage, 2537,
23285 /* 61484 */ GIR_EraseRootFromParent_Done,
23286 /* 61485 */ // Label 1655: @61485
23287 /* 61485 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(61552),
23288 /* 61490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23289 /* 61494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1657*/ GIMT_Encode4(61533), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 728 //
23290 /* 61501 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23291 /* 61505 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23292 /* 61509 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23293 /* 61513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23294 /* 61518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23295 /* 61520 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23296 /* 61520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23297 /* 61523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23298 /* 61525 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
23299 /* 61527 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23300 /* 61531 */ GIR_RootConstrainSelectedInstOperands,
23301 /* 61532 */ // GIR_Coverage, 728,
23302 /* 61532 */ GIR_EraseRootFromParent_Done,
23303 /* 61533 */ // Label 1657: @61533
23304 /* 61533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1658*/ GIMT_Encode4(61551), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 764 //
23305 /* 61540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23306 /* 61544 */ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23307 /* 61544 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
23308 /* 61549 */ GIR_RootConstrainSelectedInstOperands,
23309 /* 61550 */ // GIR_Coverage, 764,
23310 /* 61550 */ GIR_Done,
23311 /* 61551 */ // Label 1658: @61551
23312 /* 61551 */ GIM_Reject,
23313 /* 61552 */ // Label 1656: @61552
23314 /* 61552 */ GIM_Reject,
23315 /* 61553 */ // Label 1654: @61553
23316 /* 61553 */ GIM_Reject,
23317 /* 61554 */ // Label 1643: @61554
23318 /* 61554 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(61680),
23319 /* 61559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23320 /* 61562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23321 /* 61565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23322 /* 61569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1660*/ GIMT_Encode4(61612), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 2538 //
23323 /* 61576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23324 /* 61580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23325 /* 61584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23326 /* 61588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23327 /* 61593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23328 /* 61597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23329 /* 61599 */ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23330 /* 61599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23331 /* 61602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23332 /* 61604 */ GIR_RootToRootCopy, /*OpIdx*/2, // ws
23333 /* 61606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23334 /* 61610 */ GIR_RootConstrainSelectedInstOperands,
23335 /* 61611 */ // GIR_Coverage, 2538,
23336 /* 61611 */ GIR_EraseRootFromParent_Done,
23337 /* 61612 */ // Label 1660: @61612
23338 /* 61612 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(61679),
23339 /* 61617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23340 /* 61621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1662*/ GIMT_Encode4(61660), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 729 //
23341 /* 61628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23342 /* 61632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23343 /* 61636 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23344 /* 61640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23345 /* 61645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
23346 /* 61647 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23347 /* 61647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23348 /* 61650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23349 /* 61652 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
23350 /* 61654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23351 /* 61658 */ GIR_RootConstrainSelectedInstOperands,
23352 /* 61659 */ // GIR_Coverage, 729,
23353 /* 61659 */ GIR_EraseRootFromParent_Done,
23354 /* 61660 */ // Label 1662: @61660
23355 /* 61660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1663*/ GIMT_Encode4(61678), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 765 //
23356 /* 61667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23357 /* 61671 */ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23358 /* 61671 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
23359 /* 61676 */ GIR_RootConstrainSelectedInstOperands,
23360 /* 61677 */ // GIR_Coverage, 765,
23361 /* 61677 */ GIR_Done,
23362 /* 61678 */ // Label 1663: @61678
23363 /* 61678 */ GIM_Reject,
23364 /* 61679 */ // Label 1661: @61679
23365 /* 61679 */ GIM_Reject,
23366 /* 61680 */ // Label 1659: @61680
23367 /* 61680 */ GIM_Reject,
23368 /* 61681 */ // Label 1644: @61681
23369 /* 61681 */ GIM_Reject,
23370 /* 61682 */ // Label 49: @61682
23371 /* 61682 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1666*/ GIMT_Encode4(61781),
23372 /* 61693 */ /*GILLT_v4s32*//*Label 1664*/ GIMT_Encode4(61701),
23373 /* 61697 */ /*GILLT_v2s64*//*Label 1665*/ GIMT_Encode4(61741),
23374 /* 61701 */ // Label 1664: @61701
23375 /* 61701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1667*/ GIMT_Encode4(61740), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 752 //
23376 /* 61708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23377 /* 61711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23378 /* 61714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23379 /* 61717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23380 /* 61721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23381 /* 61725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23382 /* 61729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23383 /* 61733 */ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23384 /* 61733 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
23385 /* 61738 */ GIR_RootConstrainSelectedInstOperands,
23386 /* 61739 */ // GIR_Coverage, 752,
23387 /* 61739 */ GIR_Done,
23388 /* 61740 */ // Label 1667: @61740
23389 /* 61740 */ GIM_Reject,
23390 /* 61741 */ // Label 1665: @61741
23391 /* 61741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1668*/ GIMT_Encode4(61780), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 753 //
23392 /* 61748 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23393 /* 61751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23394 /* 61754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23395 /* 61757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23396 /* 61761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23397 /* 61765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23398 /* 61769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23399 /* 61773 */ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23400 /* 61773 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
23401 /* 61778 */ GIR_RootConstrainSelectedInstOperands,
23402 /* 61779 */ // GIR_Coverage, 753,
23403 /* 61779 */ GIR_Done,
23404 /* 61780 */ // Label 1668: @61780
23405 /* 61780 */ GIM_Reject,
23406 /* 61781 */ // Label 1666: @61781
23407 /* 61781 */ GIM_Reject,
23408 /* 61782 */ // Label 50: @61782
23409 /* 61782 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1673*/ GIMT_Encode4(62103),
23410 /* 61793 */ /*GILLT_s32*//*Label 1669*/ GIMT_Encode4(61825),
23411 /* 61797 */ /*GILLT_s64*//*Label 1670*/ GIMT_Encode4(61904), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23412 /* 61817 */ /*GILLT_v4s32*//*Label 1671*/ GIMT_Encode4(62037),
23413 /* 61821 */ /*GILLT_v2s64*//*Label 1672*/ GIMT_Encode4(62070),
23414 /* 61825 */ // Label 1669: @61825
23415 /* 61825 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(61903),
23416 /* 61830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23417 /* 61833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23418 /* 61836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23419 /* 61840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23420 /* 61844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23421 /* 61848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1675*/ GIMT_Encode4(61866), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 161 //
23422 /* 61855 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23423 /* 61855 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
23424 /* 61860 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23425 /* 61864 */ GIR_RootConstrainSelectedInstOperands,
23426 /* 61865 */ // GIR_Coverage, 161,
23427 /* 61865 */ GIR_Done,
23428 /* 61866 */ // Label 1675: @61866
23429 /* 61866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1676*/ GIMT_Encode4(61884), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1153 //
23430 /* 61873 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23431 /* 61873 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
23432 /* 61878 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23433 /* 61882 */ GIR_RootConstrainSelectedInstOperands,
23434 /* 61883 */ // GIR_Coverage, 1153,
23435 /* 61883 */ GIR_Done,
23436 /* 61884 */ // Label 1676: @61884
23437 /* 61884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1677*/ GIMT_Encode4(61902), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1213 //
23438 /* 61891 */ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23439 /* 61891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
23440 /* 61894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23441 /* 61896 */ GIR_RootToRootCopy, /*OpIdx*/2, // ft
23442 /* 61898 */ GIR_RootToRootCopy, /*OpIdx*/1, // fs
23443 /* 61900 */ GIR_RootConstrainSelectedInstOperands,
23444 /* 61901 */ // GIR_Coverage, 1213,
23445 /* 61901 */ GIR_EraseRootFromParent_Done,
23446 /* 61902 */ // Label 1677: @61902
23447 /* 61902 */ GIM_Reject,
23448 /* 61903 */ // Label 1674: @61903
23449 /* 61903 */ GIM_Reject,
23450 /* 61904 */ // Label 1670: @61904
23451 /* 61904 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(62036),
23452 /* 61909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23453 /* 61912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23454 /* 61915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1679*/ GIMT_Encode4(61945), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 163 //
23455 /* 61922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23456 /* 61926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23457 /* 61930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23458 /* 61934 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23459 /* 61934 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
23460 /* 61939 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23461 /* 61943 */ GIR_RootConstrainSelectedInstOperands,
23462 /* 61944 */ // GIR_Coverage, 163,
23463 /* 61944 */ GIR_Done,
23464 /* 61945 */ // Label 1679: @61945
23465 /* 61945 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1680*/ GIMT_Encode4(61975), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 165 //
23466 /* 61952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23467 /* 61956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23468 /* 61960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23469 /* 61964 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23470 /* 61964 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
23471 /* 61969 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23472 /* 61973 */ GIR_RootConstrainSelectedInstOperands,
23473 /* 61974 */ // GIR_Coverage, 165,
23474 /* 61974 */ GIR_Done,
23475 /* 61975 */ // Label 1680: @61975
23476 /* 61975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1681*/ GIMT_Encode4(62005), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1158 //
23477 /* 61982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23478 /* 61986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23479 /* 61990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23480 /* 61994 */ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23481 /* 61994 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
23482 /* 61999 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23483 /* 62003 */ GIR_RootConstrainSelectedInstOperands,
23484 /* 62004 */ // GIR_Coverage, 1158,
23485 /* 62004 */ GIR_Done,
23486 /* 62005 */ // Label 1681: @62005
23487 /* 62005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1682*/ GIMT_Encode4(62035), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1159 //
23488 /* 62012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23489 /* 62016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23490 /* 62020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23491 /* 62024 */ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23492 /* 62024 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
23493 /* 62029 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23494 /* 62033 */ GIR_RootConstrainSelectedInstOperands,
23495 /* 62034 */ // GIR_Coverage, 1159,
23496 /* 62034 */ GIR_Done,
23497 /* 62035 */ // Label 1682: @62035
23498 /* 62035 */ GIM_Reject,
23499 /* 62036 */ // Label 1678: @62036
23500 /* 62036 */ GIM_Reject,
23501 /* 62037 */ // Label 1671: @62037
23502 /* 62037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1683*/ GIMT_Encode4(62069), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 724 //
23503 /* 62044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23504 /* 62047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23505 /* 62050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23506 /* 62054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23507 /* 62058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23508 /* 62062 */ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23509 /* 62062 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
23510 /* 62067 */ GIR_RootConstrainSelectedInstOperands,
23511 /* 62068 */ // GIR_Coverage, 724,
23512 /* 62068 */ GIR_Done,
23513 /* 62069 */ // Label 1683: @62069
23514 /* 62069 */ GIM_Reject,
23515 /* 62070 */ // Label 1672: @62070
23516 /* 62070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1684*/ GIMT_Encode4(62102), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 725 //
23517 /* 62077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23518 /* 62080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23519 /* 62083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23520 /* 62087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23521 /* 62091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23522 /* 62095 */ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23523 /* 62095 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
23524 /* 62100 */ GIR_RootConstrainSelectedInstOperands,
23525 /* 62101 */ // GIR_Coverage, 725,
23526 /* 62101 */ GIR_Done,
23527 /* 62102 */ // Label 1684: @62102
23528 /* 62102 */ GIM_Reject,
23529 /* 62103 */ // Label 1673: @62103
23530 /* 62103 */ GIM_Reject,
23531 /* 62104 */ // Label 51: @62104
23532 /* 62104 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1687*/ GIMT_Encode4(62175),
23533 /* 62115 */ /*GILLT_v4s32*//*Label 1685*/ GIMT_Encode4(62123),
23534 /* 62119 */ /*GILLT_v2s64*//*Label 1686*/ GIMT_Encode4(62149),
23535 /* 62123 */ // Label 1685: @62123
23536 /* 62123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1688*/ GIMT_Encode4(62148), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 730 //
23537 /* 62130 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23538 /* 62133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23539 /* 62137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23540 /* 62141 */ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
23541 /* 62141 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
23542 /* 62146 */ GIR_RootConstrainSelectedInstOperands,
23543 /* 62147 */ // GIR_Coverage, 730,
23544 /* 62147 */ GIR_Done,
23545 /* 62148 */ // Label 1688: @62148
23546 /* 62148 */ GIM_Reject,
23547 /* 62149 */ // Label 1686: @62149
23548 /* 62149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1689*/ GIMT_Encode4(62174), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 731 //
23549 /* 62156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23550 /* 62159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23551 /* 62163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23552 /* 62167 */ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
23553 /* 62167 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
23554 /* 62172 */ GIR_RootConstrainSelectedInstOperands,
23555 /* 62173 */ // GIR_Coverage, 731,
23556 /* 62173 */ GIR_Done,
23557 /* 62174 */ // Label 1689: @62174
23558 /* 62174 */ GIM_Reject,
23559 /* 62175 */ // Label 1687: @62175
23560 /* 62175 */ GIM_Reject,
23561 /* 62176 */ // Label 52: @62176
23562 /* 62176 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1692*/ GIMT_Encode4(62247),
23563 /* 62187 */ /*GILLT_v4s32*//*Label 1690*/ GIMT_Encode4(62195),
23564 /* 62191 */ /*GILLT_v2s64*//*Label 1691*/ GIMT_Encode4(62221),
23565 /* 62195 */ // Label 1690: @62195
23566 /* 62195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1693*/ GIMT_Encode4(62220), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 750 //
23567 /* 62202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23568 /* 62205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23569 /* 62209 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23570 /* 62213 */ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23571 /* 62213 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
23572 /* 62218 */ GIR_RootConstrainSelectedInstOperands,
23573 /* 62219 */ // GIR_Coverage, 750,
23574 /* 62219 */ GIR_Done,
23575 /* 62220 */ // Label 1693: @62220
23576 /* 62220 */ GIM_Reject,
23577 /* 62221 */ // Label 1691: @62221
23578 /* 62221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1694*/ GIMT_Encode4(62246), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 751 //
23579 /* 62228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23580 /* 62231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23581 /* 62235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23582 /* 62239 */ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23583 /* 62239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
23584 /* 62244 */ GIR_RootConstrainSelectedInstOperands,
23585 /* 62245 */ // GIR_Coverage, 751,
23586 /* 62245 */ GIR_Done,
23587 /* 62246 */ // Label 1694: @62246
23588 /* 62246 */ GIM_Reject,
23589 /* 62247 */ // Label 1692: @62247
23590 /* 62247 */ GIM_Reject,
23591 /* 62248 */ // Label 53: @62248
23592 /* 62248 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1697*/ GIMT_Encode4(62425),
23593 /* 62259 */ /*GILLT_s32*//*Label 1695*/ GIMT_Encode4(62267),
23594 /* 62263 */ /*GILLT_s64*//*Label 1696*/ GIMT_Encode4(62327),
23595 /* 62267 */ // Label 1695: @62267
23596 /* 62267 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(62326),
23597 /* 62272 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23598 /* 62275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23599 /* 62279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23600 /* 62283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1699*/ GIMT_Encode4(62297), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat), // Rule ID 129 //
23601 /* 62290 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23602 /* 62290 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
23603 /* 62295 */ GIR_RootConstrainSelectedInstOperands,
23604 /* 62296 */ // GIR_Coverage, 129,
23605 /* 62296 */ GIR_Done,
23606 /* 62297 */ // Label 1699: @62297
23607 /* 62297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(62311), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1175 //
23608 /* 62304 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23609 /* 62304 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
23610 /* 62309 */ GIR_RootConstrainSelectedInstOperands,
23611 /* 62310 */ // GIR_Coverage, 1175,
23612 /* 62310 */ GIR_Done,
23613 /* 62311 */ // Label 1700: @62311
23614 /* 62311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1701*/ GIMT_Encode4(62325), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat), // Rule ID 1214 //
23615 /* 62318 */ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23616 /* 62318 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
23617 /* 62323 */ GIR_RootConstrainSelectedInstOperands,
23618 /* 62324 */ // GIR_Coverage, 1214,
23619 /* 62324 */ GIR_Done,
23620 /* 62325 */ // Label 1701: @62325
23621 /* 62325 */ GIM_Reject,
23622 /* 62326 */ // Label 1698: @62326
23623 /* 62326 */ GIM_Reject,
23624 /* 62327 */ // Label 1696: @62327
23625 /* 62327 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(62424),
23626 /* 62332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23627 /* 62335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1703*/ GIMT_Encode4(62357), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 130 //
23628 /* 62342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23629 /* 62346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23630 /* 62350 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23631 /* 62350 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
23632 /* 62355 */ GIR_RootConstrainSelectedInstOperands,
23633 /* 62356 */ // GIR_Coverage, 130,
23634 /* 62356 */ GIR_Done,
23635 /* 62357 */ // Label 1703: @62357
23636 /* 62357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1704*/ GIMT_Encode4(62379), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 131 //
23637 /* 62364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23638 /* 62368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23639 /* 62372 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23640 /* 62372 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
23641 /* 62377 */ GIR_RootConstrainSelectedInstOperands,
23642 /* 62378 */ // GIR_Coverage, 131,
23643 /* 62378 */ GIR_Done,
23644 /* 62379 */ // Label 1704: @62379
23645 /* 62379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1705*/ GIMT_Encode4(62401), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1176 //
23646 /* 62386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23647 /* 62390 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23648 /* 62394 */ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23649 /* 62394 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
23650 /* 62399 */ GIR_RootConstrainSelectedInstOperands,
23651 /* 62400 */ // GIR_Coverage, 1176,
23652 /* 62400 */ GIR_Done,
23653 /* 62401 */ // Label 1705: @62401
23654 /* 62401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1706*/ GIMT_Encode4(62423), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1177 //
23655 /* 62408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23656 /* 62412 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23657 /* 62416 */ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
23658 /* 62416 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
23659 /* 62421 */ GIR_RootConstrainSelectedInstOperands,
23660 /* 62422 */ // GIR_Coverage, 1177,
23661 /* 62422 */ GIR_Done,
23662 /* 62423 */ // Label 1706: @62423
23663 /* 62423 */ GIM_Reject,
23664 /* 62424 */ // Label 1702: @62424
23665 /* 62424 */ GIM_Reject,
23666 /* 62425 */ // Label 1697: @62425
23667 /* 62425 */ GIM_Reject,
23668 /* 62426 */ // Label 54: @62426
23669 /* 62426 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(62540),
23670 /* 62431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23671 /* 62434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23672 /* 62437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1708*/ GIMT_Encode4(62463), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1529 //
23673 /* 62444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23674 /* 62448 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23675 /* 62452 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23676 /* 62452 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
23677 /* 62457 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23678 /* 62461 */ GIR_RootConstrainSelectedInstOperands,
23679 /* 62462 */ // GIR_Coverage, 1529,
23680 /* 62462 */ GIR_Done,
23681 /* 62463 */ // Label 1708: @62463
23682 /* 62463 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(62513),
23683 /* 62468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23684 /* 62472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23685 /* 62476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1710*/ GIMT_Encode4(62494), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1546 //
23686 /* 62483 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23687 /* 62483 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
23688 /* 62488 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23689 /* 62492 */ GIR_RootConstrainSelectedInstOperands,
23690 /* 62493 */ // GIR_Coverage, 1546,
23691 /* 62493 */ GIR_Done,
23692 /* 62494 */ // Label 1710: @62494
23693 /* 62494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1711*/ GIMT_Encode4(62512), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2403 //
23694 /* 62501 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23695 /* 62501 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
23696 /* 62506 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23697 /* 62510 */ GIR_RootConstrainSelectedInstOperands,
23698 /* 62511 */ // GIR_Coverage, 2403,
23699 /* 62511 */ GIR_Done,
23700 /* 62512 */ // Label 1711: @62512
23701 /* 62512 */ GIM_Reject,
23702 /* 62513 */ // Label 1709: @62513
23703 /* 62513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1712*/ GIMT_Encode4(62539), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2405 //
23704 /* 62520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23705 /* 62524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23706 /* 62528 */ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
23707 /* 62528 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
23708 /* 62533 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23709 /* 62537 */ GIR_RootConstrainSelectedInstOperands,
23710 /* 62538 */ // GIR_Coverage, 2405,
23711 /* 62538 */ GIR_Done,
23712 /* 62539 */ // Label 1712: @62539
23713 /* 62539 */ GIM_Reject,
23714 /* 62540 */ // Label 1707: @62540
23715 /* 62540 */ GIM_Reject,
23716 /* 62541 */ // Label 55: @62541
23717 /* 62541 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(62647),
23718 /* 62546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23719 /* 62549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23720 /* 62552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23721 /* 62556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1714*/ GIMT_Encode4(62578), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_NotFP64bit_NotInMicroMips), // Rule ID 1527 //
23722 /* 62563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23723 /* 62567 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23724 /* 62567 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
23725 /* 62572 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23726 /* 62576 */ GIR_RootConstrainSelectedInstOperands,
23727 /* 62577 */ // GIR_Coverage, 1527,
23728 /* 62577 */ GIR_Done,
23729 /* 62578 */ // Label 1714: @62578
23730 /* 62578 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(62624),
23731 /* 62583 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23732 /* 62587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1716*/ GIMT_Encode4(62605), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_NotInMicroMips), // Rule ID 1544 //
23733 /* 62594 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23734 /* 62594 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
23735 /* 62599 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23736 /* 62603 */ GIR_RootConstrainSelectedInstOperands,
23737 /* 62604 */ // GIR_Coverage, 1544,
23738 /* 62604 */ GIR_Done,
23739 /* 62605 */ // Label 1716: @62605
23740 /* 62605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1717*/ GIMT_Encode4(62623), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat), // Rule ID 2402 //
23741 /* 62612 */ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
23742 /* 62612 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
23743 /* 62617 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23744 /* 62621 */ GIR_RootConstrainSelectedInstOperands,
23745 /* 62622 */ // GIR_Coverage, 2402,
23746 /* 62622 */ GIR_Done,
23747 /* 62623 */ // Label 1717: @62623
23748 /* 62623 */ GIM_Reject,
23749 /* 62624 */ // Label 1715: @62624
23750 /* 62624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1718*/ GIMT_Encode4(62646), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_NotFP64bit), // Rule ID 2404 //
23751 /* 62631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23752 /* 62635 */ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
23753 /* 62635 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
23754 /* 62640 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
23755 /* 62644 */ GIR_RootConstrainSelectedInstOperands,
23756 /* 62645 */ // GIR_Coverage, 2404,
23757 /* 62645 */ GIR_Done,
23758 /* 62646 */ // Label 1718: @62646
23759 /* 62646 */ GIM_Reject,
23760 /* 62647 */ // Label 1713: @62647
23761 /* 62647 */ GIM_Reject,
23762 /* 62648 */ // Label 56: @62648
23763 /* 62648 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1721*/ GIMT_Encode4(62719),
23764 /* 62659 */ /*GILLT_v4s32*//*Label 1719*/ GIMT_Encode4(62667),
23765 /* 62663 */ /*GILLT_v2s64*//*Label 1720*/ GIMT_Encode4(62693),
23766 /* 62667 */ // Label 1719: @62667
23767 /* 62667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1722*/ GIMT_Encode4(62692), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 804 //
23768 /* 62674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23769 /* 62677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23770 /* 62681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23771 /* 62685 */ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23772 /* 62685 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
23773 /* 62690 */ GIR_RootConstrainSelectedInstOperands,
23774 /* 62691 */ // GIR_Coverage, 804,
23775 /* 62691 */ GIR_Done,
23776 /* 62692 */ // Label 1722: @62692
23777 /* 62692 */ GIM_Reject,
23778 /* 62693 */ // Label 1720: @62693
23779 /* 62693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1723*/ GIMT_Encode4(62718), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 805 //
23780 /* 62700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23781 /* 62703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23782 /* 62707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23783 /* 62711 */ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23784 /* 62711 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
23785 /* 62716 */ GIR_RootConstrainSelectedInstOperands,
23786 /* 62717 */ // GIR_Coverage, 805,
23787 /* 62717 */ GIR_Done,
23788 /* 62718 */ // Label 1723: @62718
23789 /* 62718 */ GIM_Reject,
23790 /* 62719 */ // Label 1721: @62719
23791 /* 62719 */ GIM_Reject,
23792 /* 62720 */ // Label 57: @62720
23793 /* 62720 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1726*/ GIMT_Encode4(62791),
23794 /* 62731 */ /*GILLT_v4s32*//*Label 1724*/ GIMT_Encode4(62739),
23795 /* 62735 */ /*GILLT_v2s64*//*Label 1725*/ GIMT_Encode4(62765),
23796 /* 62739 */ // Label 1724: @62739
23797 /* 62739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1727*/ GIMT_Encode4(62764), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 806 //
23798 /* 62746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23799 /* 62749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23800 /* 62753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23801 /* 62757 */ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23802 /* 62757 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
23803 /* 62762 */ GIR_RootConstrainSelectedInstOperands,
23804 /* 62763 */ // GIR_Coverage, 806,
23805 /* 62763 */ GIR_Done,
23806 /* 62764 */ // Label 1727: @62764
23807 /* 62764 */ GIM_Reject,
23808 /* 62765 */ // Label 1725: @62765
23809 /* 62765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1728*/ GIMT_Encode4(62790), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 807 //
23810 /* 62772 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23811 /* 62775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23812 /* 62779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23813 /* 62783 */ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23814 /* 62783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
23815 /* 62788 */ GIR_RootConstrainSelectedInstOperands,
23816 /* 62789 */ // GIR_Coverage, 807,
23817 /* 62789 */ GIR_Done,
23818 /* 62790 */ // Label 1728: @62790
23819 /* 62790 */ GIM_Reject,
23820 /* 62791 */ // Label 1726: @62791
23821 /* 62791 */ GIM_Reject,
23822 /* 62792 */ // Label 58: @62792
23823 /* 62792 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1733*/ GIMT_Encode4(63073),
23824 /* 62803 */ /*GILLT_s32*//*Label 1729*/ GIMT_Encode4(62835),
23825 /* 62807 */ /*GILLT_s64*//*Label 1730*/ GIMT_Encode4(62933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23826 /* 62827 */ /*GILLT_v4s32*//*Label 1731*/ GIMT_Encode4(63021),
23827 /* 62831 */ /*GILLT_v2s64*//*Label 1732*/ GIMT_Encode4(63047),
23828 /* 62835 */ // Label 1729: @62835
23829 /* 62835 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1736*/ GIMT_Encode4(62932),
23830 /* 62846 */ /*GILLT_s32*//*Label 1734*/ GIMT_Encode4(62854),
23831 /* 62850 */ /*GILLT_s64*//*Label 1735*/ GIMT_Encode4(62875),
23832 /* 62854 */ // Label 1734: @62854
23833 /* 62854 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(62874), // Rule ID 1517 //
23834 /* 62859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23835 /* 62863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23836 /* 62867 */ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
23837 /* 62867 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
23838 /* 62872 */ GIR_RootConstrainSelectedInstOperands,
23839 /* 62873 */ // GIR_Coverage, 1517,
23840 /* 62873 */ GIR_Done,
23841 /* 62874 */ // Label 1737: @62874
23842 /* 62874 */ GIM_Reject,
23843 /* 62875 */ // Label 1735: @62875
23844 /* 62875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1738*/ GIMT_Encode4(62931), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1537 //
23845 /* 62882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23846 /* 62886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23847 /* 62890 */ // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
23848 /* 62890 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
23849 /* 62893 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
23850 /* 62897 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23851 /* 62902 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
23852 /* 62906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23853 /* 62908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23854 /* 62911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23855 /* 62913 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
23856 /* 62920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
23857 /* 62925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
23858 /* 62930 */ // GIR_Coverage, 1537,
23859 /* 62930 */ GIR_EraseRootFromParent_Done,
23860 /* 62931 */ // Label 1738: @62931
23861 /* 62931 */ GIM_Reject,
23862 /* 62932 */ // Label 1736: @62932
23863 /* 62932 */ GIM_Reject,
23864 /* 62933 */ // Label 1730: @62933
23865 /* 62933 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1741*/ GIMT_Encode4(63020),
23866 /* 62944 */ /*GILLT_s32*//*Label 1739*/ GIMT_Encode4(62952),
23867 /* 62948 */ /*GILLT_s64*//*Label 1740*/ GIMT_Encode4(62997),
23868 /* 62952 */ // Label 1739: @62952
23869 /* 62952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1742*/ GIMT_Encode4(62974), GIMT_Encode2(GIFBS_IsNotSingleFloat_NotFP64bit), // Rule ID 1524 //
23870 /* 62959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23871 /* 62963 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23872 /* 62967 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23873 /* 62967 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
23874 /* 62972 */ GIR_RootConstrainSelectedInstOperands,
23875 /* 62973 */ // GIR_Coverage, 1524,
23876 /* 62973 */ GIR_Done,
23877 /* 62974 */ // Label 1742: @62974
23878 /* 62974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1743*/ GIMT_Encode4(62996), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1535 //
23879 /* 62981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23880 /* 62985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
23881 /* 62989 */ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
23882 /* 62989 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
23883 /* 62994 */ GIR_RootConstrainSelectedInstOperands,
23884 /* 62995 */ // GIR_Coverage, 1535,
23885 /* 62995 */ GIR_Done,
23886 /* 62996 */ // Label 1743: @62996
23887 /* 62996 */ GIM_Reject,
23888 /* 62997 */ // Label 1740: @62997
23889 /* 62997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1744*/ GIMT_Encode4(63019), GIMT_Encode2(GIFBS_IsFP64bit_IsNotSingleFloat), // Rule ID 1539 //
23890 /* 63004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23891 /* 63008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
23892 /* 63012 */ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
23893 /* 63012 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
23894 /* 63017 */ GIR_RootConstrainSelectedInstOperands,
23895 /* 63018 */ // GIR_Coverage, 1539,
23896 /* 63018 */ GIR_Done,
23897 /* 63019 */ // Label 1744: @63019
23898 /* 63019 */ GIM_Reject,
23899 /* 63020 */ // Label 1741: @63020
23900 /* 63020 */ GIM_Reject,
23901 /* 63021 */ // Label 1731: @63021
23902 /* 63021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1745*/ GIMT_Encode4(63046), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 736 //
23903 /* 63028 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23904 /* 63031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23905 /* 63035 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23906 /* 63039 */ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23907 /* 63039 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
23908 /* 63044 */ GIR_RootConstrainSelectedInstOperands,
23909 /* 63045 */ // GIR_Coverage, 736,
23910 /* 63045 */ GIR_Done,
23911 /* 63046 */ // Label 1745: @63046
23912 /* 63046 */ GIM_Reject,
23913 /* 63047 */ // Label 1732: @63047
23914 /* 63047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1746*/ GIMT_Encode4(63072), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 737 //
23915 /* 63054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23916 /* 63057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23917 /* 63061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23918 /* 63065 */ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23919 /* 63065 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
23920 /* 63070 */ GIR_RootConstrainSelectedInstOperands,
23921 /* 63071 */ // GIR_Coverage, 737,
23922 /* 63071 */ GIR_Done,
23923 /* 63072 */ // Label 1746: @63072
23924 /* 63072 */ GIM_Reject,
23925 /* 63073 */ // Label 1733: @63073
23926 /* 63073 */ GIM_Reject,
23927 /* 63074 */ // Label 59: @63074
23928 /* 63074 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1749*/ GIMT_Encode4(63145),
23929 /* 63085 */ /*GILLT_v4s32*//*Label 1747*/ GIMT_Encode4(63093),
23930 /* 63089 */ /*GILLT_v2s64*//*Label 1748*/ GIMT_Encode4(63119),
23931 /* 63093 */ // Label 1747: @63093
23932 /* 63093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1750*/ GIMT_Encode4(63118), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 738 //
23933 /* 63100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23934 /* 63103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23935 /* 63107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23936 /* 63111 */ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
23937 /* 63111 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
23938 /* 63116 */ GIR_RootConstrainSelectedInstOperands,
23939 /* 63117 */ // GIR_Coverage, 738,
23940 /* 63117 */ GIR_Done,
23941 /* 63118 */ // Label 1750: @63118
23942 /* 63118 */ GIM_Reject,
23943 /* 63119 */ // Label 1748: @63119
23944 /* 63119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1751*/ GIMT_Encode4(63144), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 739 //
23945 /* 63126 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23946 /* 63129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23947 /* 63133 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23948 /* 63137 */ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
23949 /* 63137 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
23950 /* 63142 */ GIR_RootConstrainSelectedInstOperands,
23951 /* 63143 */ // GIR_Coverage, 739,
23952 /* 63143 */ GIR_Done,
23953 /* 63144 */ // Label 1751: @63144
23954 /* 63144 */ GIM_Reject,
23955 /* 63145 */ // Label 1749: @63145
23956 /* 63145 */ GIM_Reject,
23957 /* 63146 */ // Label 60: @63146
23958 /* 63146 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1756*/ GIMT_Encode4(63385),
23959 /* 63157 */ /*GILLT_s32*//*Label 1752*/ GIMT_Encode4(63189),
23960 /* 63161 */ /*GILLT_s64*//*Label 1753*/ GIMT_Encode4(63235), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
23961 /* 63181 */ /*GILLT_v4s32*//*Label 1754*/ GIMT_Encode4(63333),
23962 /* 63185 */ /*GILLT_v2s64*//*Label 1755*/ GIMT_Encode4(63359),
23963 /* 63189 */ // Label 1752: @63189
23964 /* 63189 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(63234),
23965 /* 63194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23966 /* 63197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23967 /* 63201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23968 /* 63205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1758*/ GIMT_Encode4(63219), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 126 //
23969 /* 63212 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23970 /* 63212 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S),
23971 /* 63217 */ GIR_RootConstrainSelectedInstOperands,
23972 /* 63218 */ // GIR_Coverage, 126,
23973 /* 63218 */ GIR_Done,
23974 /* 63219 */ // Label 1758: @63219
23975 /* 63219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1759*/ GIMT_Encode4(63233), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1174 //
23976 /* 63226 */ // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23977 /* 63226 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S_MM),
23978 /* 63231 */ GIR_RootConstrainSelectedInstOperands,
23979 /* 63232 */ // GIR_Coverage, 1174,
23980 /* 63232 */ GIR_Done,
23981 /* 63233 */ // Label 1759: @63233
23982 /* 63233 */ GIM_Reject,
23983 /* 63234 */ // Label 1757: @63234
23984 /* 63234 */ GIM_Reject,
23985 /* 63235 */ // Label 1753: @63235
23986 /* 63235 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(63332),
23987 /* 63240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23988 /* 63243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1761*/ GIMT_Encode4(63265), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 127 //
23989 /* 63250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23990 /* 63254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23991 /* 63258 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
23992 /* 63258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32),
23993 /* 63263 */ GIR_RootConstrainSelectedInstOperands,
23994 /* 63264 */ // GIR_Coverage, 127,
23995 /* 63264 */ GIR_Done,
23996 /* 63265 */ // Label 1761: @63265
23997 /* 63265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1762*/ GIMT_Encode4(63287), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 128 //
23998 /* 63272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23999 /* 63276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24000 /* 63280 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24001 /* 63280 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64),
24002 /* 63285 */ GIR_RootConstrainSelectedInstOperands,
24003 /* 63286 */ // GIR_Coverage, 128,
24004 /* 63286 */ GIR_Done,
24005 /* 63287 */ // Label 1762: @63287
24006 /* 63287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1763*/ GIMT_Encode4(63309), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1172 //
24007 /* 63294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24008 /* 63298 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24009 /* 63302 */ // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24010 /* 63302 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
24011 /* 63307 */ GIR_RootConstrainSelectedInstOperands,
24012 /* 63308 */ // GIR_Coverage, 1172,
24013 /* 63308 */ GIR_Done,
24014 /* 63309 */ // Label 1763: @63309
24015 /* 63309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1764*/ GIMT_Encode4(63331), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1173 //
24016 /* 63316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24017 /* 63320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24018 /* 63324 */ // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24019 /* 63324 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
24020 /* 63329 */ GIR_RootConstrainSelectedInstOperands,
24021 /* 63330 */ // GIR_Coverage, 1173,
24022 /* 63330 */ GIR_Done,
24023 /* 63331 */ // Label 1764: @63331
24024 /* 63331 */ GIM_Reject,
24025 /* 63332 */ // Label 1760: @63332
24026 /* 63332 */ GIM_Reject,
24027 /* 63333 */ // Label 1754: @63333
24028 /* 63333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1765*/ GIMT_Encode4(63358), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1070 //
24029 /* 63340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24030 /* 63343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24031 /* 63347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24032 /* 63351 */ // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24033 /* 63351 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
24034 /* 63356 */ GIR_RootConstrainSelectedInstOperands,
24035 /* 63357 */ // GIR_Coverage, 1070,
24036 /* 63357 */ GIR_Done,
24037 /* 63358 */ // Label 1765: @63358
24038 /* 63358 */ GIM_Reject,
24039 /* 63359 */ // Label 1755: @63359
24040 /* 63359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1766*/ GIMT_Encode4(63384), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 1071 //
24041 /* 63366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24042 /* 63369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24043 /* 63373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24044 /* 63377 */ // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24045 /* 63377 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
24046 /* 63382 */ GIR_RootConstrainSelectedInstOperands,
24047 /* 63383 */ // GIR_Coverage, 1071,
24048 /* 63383 */ GIR_Done,
24049 /* 63384 */ // Label 1766: @63384
24050 /* 63384 */ GIM_Reject,
24051 /* 63385 */ // Label 1756: @63385
24052 /* 63385 */ GIM_Reject,
24053 /* 63386 */ // Label 61: @63386
24054 /* 63386 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1769*/ GIMT_Encode4(63457),
24055 /* 63397 */ /*GILLT_s32*//*Label 1767*/ GIMT_Encode4(63405),
24056 /* 63401 */ /*GILLT_s64*//*Label 1768*/ GIMT_Encode4(63431),
24057 /* 63405 */ // Label 1767: @63405
24058 /* 63405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1770*/ GIMT_Encode4(63430), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1892 //
24059 /* 63412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24060 /* 63415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24061 /* 63419 */ // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
24062 /* 63419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24063 /* 63422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24064 /* 63424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24065 /* 63426 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24066 /* 63428 */ GIR_RootConstrainSelectedInstOperands,
24067 /* 63429 */ // GIR_Coverage, 1892,
24068 /* 63429 */ GIR_EraseRootFromParent_Done,
24069 /* 63430 */ // Label 1770: @63430
24070 /* 63430 */ GIM_Reject,
24071 /* 63431 */ // Label 1768: @63431
24072 /* 63431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1771*/ GIMT_Encode4(63456), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1893 //
24073 /* 63438 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24074 /* 63441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24075 /* 63445 */ // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
24076 /* 63445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24077 /* 63448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24078 /* 63450 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24079 /* 63452 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
24080 /* 63454 */ GIR_RootConstrainSelectedInstOperands,
24081 /* 63455 */ // GIR_Coverage, 1893,
24082 /* 63455 */ GIR_EraseRootFromParent_Done,
24083 /* 63456 */ // Label 1771: @63456
24084 /* 63456 */ GIM_Reject,
24085 /* 63457 */ // Label 1769: @63457
24086 /* 63457 */ GIM_Reject,
24087 /* 63458 */ // Label 62: @63458
24088 /* 63458 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1774*/ GIMT_Encode4(63527),
24089 /* 63469 */ /*GILLT_s32*//*Label 1772*/ GIMT_Encode4(63477),
24090 /* 63473 */ /*GILLT_s64*//*Label 1773*/ GIMT_Encode4(63502),
24091 /* 63477 */ // Label 1772: @63477
24092 /* 63477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1775*/ GIMT_Encode4(63501), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1889 //
24093 /* 63484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24094 /* 63487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24095 /* 63490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24096 /* 63494 */ // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24097 /* 63494 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24098 /* 63499 */ GIR_RootConstrainSelectedInstOperands,
24099 /* 63500 */ // GIR_Coverage, 1889,
24100 /* 63500 */ GIR_Done,
24101 /* 63501 */ // Label 1775: @63501
24102 /* 63501 */ GIM_Reject,
24103 /* 63502 */ // Label 1773: @63502
24104 /* 63502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1776*/ GIMT_Encode4(63526), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1891 //
24105 /* 63509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24106 /* 63512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24107 /* 63515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24108 /* 63519 */ // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24109 /* 63519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24110 /* 63524 */ GIR_RootConstrainSelectedInstOperands,
24111 /* 63525 */ // GIR_Coverage, 1891,
24112 /* 63525 */ GIR_Done,
24113 /* 63526 */ // Label 1776: @63526
24114 /* 63526 */ GIM_Reject,
24115 /* 63527 */ // Label 1774: @63527
24116 /* 63527 */ GIM_Reject,
24117 /* 63528 */ // Label 63: @63528
24118 /* 63528 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1779*/ GIMT_Encode4(63597),
24119 /* 63539 */ /*GILLT_s32*//*Label 1777*/ GIMT_Encode4(63547),
24120 /* 63543 */ /*GILLT_s64*//*Label 1778*/ GIMT_Encode4(63572),
24121 /* 63547 */ // Label 1777: @63547
24122 /* 63547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1780*/ GIMT_Encode4(63571), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1885 //
24123 /* 63554 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24124 /* 63557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24125 /* 63560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24126 /* 63564 */ // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24127 /* 63564 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
24128 /* 63569 */ GIR_RootConstrainSelectedInstOperands,
24129 /* 63570 */ // GIR_Coverage, 1885,
24130 /* 63570 */ GIR_Done,
24131 /* 63571 */ // Label 1780: @63571
24132 /* 63571 */ GIM_Reject,
24133 /* 63572 */ // Label 1778: @63572
24134 /* 63572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1781*/ GIMT_Encode4(63596), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1887 //
24135 /* 63579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24136 /* 63582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24137 /* 63585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24138 /* 63589 */ // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24139 /* 63589 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
24140 /* 63594 */ GIR_RootConstrainSelectedInstOperands,
24141 /* 63595 */ // GIR_Coverage, 1887,
24142 /* 63595 */ GIR_Done,
24143 /* 63596 */ // Label 1781: @63596
24144 /* 63596 */ GIM_Reject,
24145 /* 63597 */ // Label 1779: @63597
24146 /* 63597 */ GIM_Reject,
24147 /* 63598 */ // Label 64: @63598
24148 /* 63598 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1784*/ GIMT_Encode4(63667),
24149 /* 63609 */ /*GILLT_s32*//*Label 1782*/ GIMT_Encode4(63617),
24150 /* 63613 */ /*GILLT_s64*//*Label 1783*/ GIMT_Encode4(63642),
24151 /* 63617 */ // Label 1782: @63617
24152 /* 63617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1785*/ GIMT_Encode4(63641), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1888 //
24153 /* 63624 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24154 /* 63627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24155 /* 63630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24156 /* 63634 */ // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24157 /* 63634 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24158 /* 63639 */ GIR_RootConstrainSelectedInstOperands,
24159 /* 63640 */ // GIR_Coverage, 1888,
24160 /* 63640 */ GIR_Done,
24161 /* 63641 */ // Label 1785: @63641
24162 /* 63641 */ GIM_Reject,
24163 /* 63642 */ // Label 1783: @63642
24164 /* 63642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1786*/ GIMT_Encode4(63666), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1890 //
24165 /* 63649 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24166 /* 63652 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24167 /* 63655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24168 /* 63659 */ // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24169 /* 63659 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24170 /* 63664 */ GIR_RootConstrainSelectedInstOperands,
24171 /* 63665 */ // GIR_Coverage, 1890,
24172 /* 63665 */ GIR_Done,
24173 /* 63666 */ // Label 1786: @63666
24174 /* 63666 */ GIM_Reject,
24175 /* 63667 */ // Label 1784: @63667
24176 /* 63667 */ GIM_Reject,
24177 /* 63668 */ // Label 65: @63668
24178 /* 63668 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1789*/ GIMT_Encode4(63737),
24179 /* 63679 */ /*GILLT_s32*//*Label 1787*/ GIMT_Encode4(63687),
24180 /* 63683 */ /*GILLT_s64*//*Label 1788*/ GIMT_Encode4(63712),
24181 /* 63687 */ // Label 1787: @63687
24182 /* 63687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1790*/ GIMT_Encode4(63711), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1884 //
24183 /* 63694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24184 /* 63697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24185 /* 63700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24186 /* 63704 */ // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24187 /* 63704 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
24188 /* 63709 */ GIR_RootConstrainSelectedInstOperands,
24189 /* 63710 */ // GIR_Coverage, 1884,
24190 /* 63710 */ GIR_Done,
24191 /* 63711 */ // Label 1790: @63711
24192 /* 63711 */ GIM_Reject,
24193 /* 63712 */ // Label 1788: @63712
24194 /* 63712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1791*/ GIMT_Encode4(63736), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips), // Rule ID 1886 //
24195 /* 63719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24196 /* 63722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24197 /* 63725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24198 /* 63729 */ // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24199 /* 63729 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
24200 /* 63734 */ GIR_RootConstrainSelectedInstOperands,
24201 /* 63735 */ // GIR_Coverage, 1886,
24202 /* 63735 */ GIR_Done,
24203 /* 63736 */ // Label 1791: @63736
24204 /* 63736 */ GIM_Reject,
24205 /* 63737 */ // Label 1789: @63737
24206 /* 63737 */ GIM_Reject,
24207 /* 63738 */ // Label 66: @63738
24208 /* 63738 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1796*/ GIMT_Encode4(63901),
24209 /* 63749 */ /*GILLT_v16s8*//*Label 1792*/ GIMT_Encode4(63769), GIMT_Encode4(0),
24210 /* 63757 */ /*GILLT_v8s16*//*Label 1793*/ GIMT_Encode4(63802),
24211 /* 63761 */ /*GILLT_v4s32*//*Label 1794*/ GIMT_Encode4(63835),
24212 /* 63765 */ /*GILLT_v2s64*//*Label 1795*/ GIMT_Encode4(63868),
24213 /* 63769 */ // Label 1792: @63769
24214 /* 63769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1797*/ GIMT_Encode4(63801), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 896 //
24215 /* 63776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24216 /* 63779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24217 /* 63782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24218 /* 63786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24219 /* 63790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24220 /* 63794 */ // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24221 /* 63794 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
24222 /* 63799 */ GIR_RootConstrainSelectedInstOperands,
24223 /* 63800 */ // GIR_Coverage, 896,
24224 /* 63800 */ GIR_Done,
24225 /* 63801 */ // Label 1797: @63801
24226 /* 63801 */ GIM_Reject,
24227 /* 63802 */ // Label 1793: @63802
24228 /* 63802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1798*/ GIMT_Encode4(63834), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 897 //
24229 /* 63809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24230 /* 63812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24231 /* 63815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24232 /* 63819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24233 /* 63823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24234 /* 63827 */ // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24235 /* 63827 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
24236 /* 63832 */ GIR_RootConstrainSelectedInstOperands,
24237 /* 63833 */ // GIR_Coverage, 897,
24238 /* 63833 */ GIR_Done,
24239 /* 63834 */ // Label 1798: @63834
24240 /* 63834 */ GIM_Reject,
24241 /* 63835 */ // Label 1794: @63835
24242 /* 63835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1799*/ GIMT_Encode4(63867), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 898 //
24243 /* 63842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24244 /* 63845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24245 /* 63848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24246 /* 63852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24247 /* 63856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24248 /* 63860 */ // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24249 /* 63860 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
24250 /* 63865 */ GIR_RootConstrainSelectedInstOperands,
24251 /* 63866 */ // GIR_Coverage, 898,
24252 /* 63866 */ GIR_Done,
24253 /* 63867 */ // Label 1799: @63867
24254 /* 63867 */ GIM_Reject,
24255 /* 63868 */ // Label 1795: @63868
24256 /* 63868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1800*/ GIMT_Encode4(63900), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 899 //
24257 /* 63875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24258 /* 63878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24259 /* 63881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24260 /* 63885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24261 /* 63889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24262 /* 63893 */ // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24263 /* 63893 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
24264 /* 63898 */ GIR_RootConstrainSelectedInstOperands,
24265 /* 63899 */ // GIR_Coverage, 899,
24266 /* 63899 */ GIR_Done,
24267 /* 63900 */ // Label 1800: @63900
24268 /* 63900 */ GIM_Reject,
24269 /* 63901 */ // Label 1796: @63901
24270 /* 63901 */ GIM_Reject,
24271 /* 63902 */ // Label 67: @63902
24272 /* 63902 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1805*/ GIMT_Encode4(64065),
24273 /* 63913 */ /*GILLT_v16s8*//*Label 1801*/ GIMT_Encode4(63933), GIMT_Encode4(0),
24274 /* 63921 */ /*GILLT_v8s16*//*Label 1802*/ GIMT_Encode4(63966),
24275 /* 63925 */ /*GILLT_v4s32*//*Label 1803*/ GIMT_Encode4(63999),
24276 /* 63929 */ /*GILLT_v2s64*//*Label 1804*/ GIMT_Encode4(64032),
24277 /* 63933 */ // Label 1801: @63933
24278 /* 63933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1806*/ GIMT_Encode4(63965), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 876 //
24279 /* 63940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24280 /* 63943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24281 /* 63946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24282 /* 63950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24283 /* 63954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24284 /* 63958 */ // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24285 /* 63958 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
24286 /* 63963 */ GIR_RootConstrainSelectedInstOperands,
24287 /* 63964 */ // GIR_Coverage, 876,
24288 /* 63964 */ GIR_Done,
24289 /* 63965 */ // Label 1806: @63965
24290 /* 63965 */ GIM_Reject,
24291 /* 63966 */ // Label 1802: @63966
24292 /* 63966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1807*/ GIMT_Encode4(63998), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 877 //
24293 /* 63973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24294 /* 63976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24295 /* 63979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24296 /* 63983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24297 /* 63987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24298 /* 63991 */ // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24299 /* 63991 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
24300 /* 63996 */ GIR_RootConstrainSelectedInstOperands,
24301 /* 63997 */ // GIR_Coverage, 877,
24302 /* 63997 */ GIR_Done,
24303 /* 63998 */ // Label 1807: @63998
24304 /* 63998 */ GIM_Reject,
24305 /* 63999 */ // Label 1803: @63999
24306 /* 63999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1808*/ GIMT_Encode4(64031), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 878 //
24307 /* 64006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24308 /* 64009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24309 /* 64012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24310 /* 64016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24311 /* 64020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24312 /* 64024 */ // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24313 /* 64024 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
24314 /* 64029 */ GIR_RootConstrainSelectedInstOperands,
24315 /* 64030 */ // GIR_Coverage, 878,
24316 /* 64030 */ GIR_Done,
24317 /* 64031 */ // Label 1808: @64031
24318 /* 64031 */ GIM_Reject,
24319 /* 64032 */ // Label 1804: @64032
24320 /* 64032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(64064), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 879 //
24321 /* 64039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24322 /* 64042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24323 /* 64045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24324 /* 64049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24325 /* 64053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24326 /* 64057 */ // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24327 /* 64057 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
24328 /* 64062 */ GIR_RootConstrainSelectedInstOperands,
24329 /* 64063 */ // GIR_Coverage, 879,
24330 /* 64063 */ GIR_Done,
24331 /* 64064 */ // Label 1809: @64064
24332 /* 64064 */ GIM_Reject,
24333 /* 64065 */ // Label 1805: @64065
24334 /* 64065 */ GIM_Reject,
24335 /* 64066 */ // Label 68: @64066
24336 /* 64066 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1814*/ GIMT_Encode4(64229),
24337 /* 64077 */ /*GILLT_v16s8*//*Label 1810*/ GIMT_Encode4(64097), GIMT_Encode4(0),
24338 /* 64085 */ /*GILLT_v8s16*//*Label 1811*/ GIMT_Encode4(64130),
24339 /* 64089 */ /*GILLT_v4s32*//*Label 1812*/ GIMT_Encode4(64163),
24340 /* 64093 */ /*GILLT_v2s64*//*Label 1813*/ GIMT_Encode4(64196),
24341 /* 64097 */ // Label 1810: @64097
24342 /* 64097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1815*/ GIMT_Encode4(64129), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 900 //
24343 /* 64104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24344 /* 64107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24345 /* 64110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24346 /* 64114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24347 /* 64118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24348 /* 64122 */ // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24349 /* 64122 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
24350 /* 64127 */ GIR_RootConstrainSelectedInstOperands,
24351 /* 64128 */ // GIR_Coverage, 900,
24352 /* 64128 */ GIR_Done,
24353 /* 64129 */ // Label 1815: @64129
24354 /* 64129 */ GIM_Reject,
24355 /* 64130 */ // Label 1811: @64130
24356 /* 64130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1816*/ GIMT_Encode4(64162), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 901 //
24357 /* 64137 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24358 /* 64140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24359 /* 64143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24360 /* 64147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24361 /* 64151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24362 /* 64155 */ // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24363 /* 64155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
24364 /* 64160 */ GIR_RootConstrainSelectedInstOperands,
24365 /* 64161 */ // GIR_Coverage, 901,
24366 /* 64161 */ GIR_Done,
24367 /* 64162 */ // Label 1816: @64162
24368 /* 64162 */ GIM_Reject,
24369 /* 64163 */ // Label 1812: @64163
24370 /* 64163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1817*/ GIMT_Encode4(64195), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 902 //
24371 /* 64170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24372 /* 64173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24373 /* 64176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24374 /* 64180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24375 /* 64184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24376 /* 64188 */ // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24377 /* 64188 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
24378 /* 64193 */ GIR_RootConstrainSelectedInstOperands,
24379 /* 64194 */ // GIR_Coverage, 902,
24380 /* 64194 */ GIR_Done,
24381 /* 64195 */ // Label 1817: @64195
24382 /* 64195 */ GIM_Reject,
24383 /* 64196 */ // Label 1813: @64196
24384 /* 64196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1818*/ GIMT_Encode4(64228), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 903 //
24385 /* 64203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24386 /* 64206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24387 /* 64209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24388 /* 64213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24389 /* 64217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24390 /* 64221 */ // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24391 /* 64221 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
24392 /* 64226 */ GIR_RootConstrainSelectedInstOperands,
24393 /* 64227 */ // GIR_Coverage, 903,
24394 /* 64227 */ GIR_Done,
24395 /* 64228 */ // Label 1818: @64228
24396 /* 64228 */ GIM_Reject,
24397 /* 64229 */ // Label 1814: @64229
24398 /* 64229 */ GIM_Reject,
24399 /* 64230 */ // Label 69: @64230
24400 /* 64230 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1823*/ GIMT_Encode4(64393),
24401 /* 64241 */ /*GILLT_v16s8*//*Label 1819*/ GIMT_Encode4(64261), GIMT_Encode4(0),
24402 /* 64249 */ /*GILLT_v8s16*//*Label 1820*/ GIMT_Encode4(64294),
24403 /* 64253 */ /*GILLT_v4s32*//*Label 1821*/ GIMT_Encode4(64327),
24404 /* 64257 */ /*GILLT_v2s64*//*Label 1822*/ GIMT_Encode4(64360),
24405 /* 64261 */ // Label 1819: @64261
24406 /* 64261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1824*/ GIMT_Encode4(64293), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 880 //
24407 /* 64268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24408 /* 64271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24409 /* 64274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24410 /* 64278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24411 /* 64282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24412 /* 64286 */ // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24413 /* 64286 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
24414 /* 64291 */ GIR_RootConstrainSelectedInstOperands,
24415 /* 64292 */ // GIR_Coverage, 880,
24416 /* 64292 */ GIR_Done,
24417 /* 64293 */ // Label 1824: @64293
24418 /* 64293 */ GIM_Reject,
24419 /* 64294 */ // Label 1820: @64294
24420 /* 64294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1825*/ GIMT_Encode4(64326), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 881 //
24421 /* 64301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24422 /* 64304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24423 /* 64307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24424 /* 64311 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24425 /* 64315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24426 /* 64319 */ // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24427 /* 64319 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
24428 /* 64324 */ GIR_RootConstrainSelectedInstOperands,
24429 /* 64325 */ // GIR_Coverage, 881,
24430 /* 64325 */ GIR_Done,
24431 /* 64326 */ // Label 1825: @64326
24432 /* 64326 */ GIM_Reject,
24433 /* 64327 */ // Label 1821: @64327
24434 /* 64327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1826*/ GIMT_Encode4(64359), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 882 //
24435 /* 64334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24436 /* 64337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24437 /* 64340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24438 /* 64344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24439 /* 64348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24440 /* 64352 */ // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24441 /* 64352 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
24442 /* 64357 */ GIR_RootConstrainSelectedInstOperands,
24443 /* 64358 */ // GIR_Coverage, 882,
24444 /* 64358 */ GIR_Done,
24445 /* 64359 */ // Label 1826: @64359
24446 /* 64359 */ GIM_Reject,
24447 /* 64360 */ // Label 1822: @64360
24448 /* 64360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(64392), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 883 //
24449 /* 64367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24450 /* 64370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24451 /* 64373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24452 /* 64377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24453 /* 64381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24454 /* 64385 */ // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24455 /* 64385 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
24456 /* 64390 */ GIR_RootConstrainSelectedInstOperands,
24457 /* 64391 */ // GIR_Coverage, 883,
24458 /* 64391 */ GIR_Done,
24459 /* 64392 */ // Label 1827: @64392
24460 /* 64392 */ GIM_Reject,
24461 /* 64393 */ // Label 1823: @64393
24462 /* 64393 */ GIM_Reject,
24463 /* 64394 */ // Label 70: @64394
24464 /* 64394 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(64511),
24465 /* 64399 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
24466 /* 64402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1829*/ GIMT_Encode4(64422), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC), // Rule ID 91 //
24467 /* 64409 */ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
24468 /* 64409 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
24469 /* 64414 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24470 /* 64420 */ GIR_RootConstrainSelectedInstOperands,
24471 /* 64421 */ // GIR_Coverage, 91,
24472 /* 64421 */ GIR_Done,
24473 /* 64422 */ // Label 1829: @64422
24474 /* 64422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1830*/ GIMT_Encode4(64442), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 98 //
24475 /* 64429 */ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
24476 /* 64429 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
24477 /* 64434 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24478 /* 64440 */ GIR_RootConstrainSelectedInstOperands,
24479 /* 64441 */ // GIR_Coverage, 98,
24480 /* 64441 */ GIR_Done,
24481 /* 64442 */ // Label 1830: @64442
24482 /* 64442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1831*/ GIMT_Encode4(64462), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC), // Rule ID 1126 //
24483 /* 64449 */ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
24484 /* 64449 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
24485 /* 64454 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24486 /* 64460 */ GIR_RootConstrainSelectedInstOperands,
24487 /* 64461 */ // GIR_Coverage, 1126,
24488 /* 64461 */ GIR_Done,
24489 /* 64462 */ // Label 1831: @64462
24490 /* 64462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1832*/ GIMT_Encode4(64482), GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC), // Rule ID 1135 //
24491 /* 64469 */ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
24492 /* 64469 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
24493 /* 64474 */ GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
24494 /* 64480 */ GIR_RootConstrainSelectedInstOperands,
24495 /* 64481 */ // GIR_Coverage, 1135,
24496 /* 64481 */ GIR_Done,
24497 /* 64482 */ // Label 1832: @64482
24498 /* 64482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1833*/ GIMT_Encode4(64496), GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips), // Rule ID 1193 //
24499 /* 64489 */ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
24500 /* 64489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
24501 /* 64494 */ GIR_RootConstrainSelectedInstOperands,
24502 /* 64495 */ // GIR_Coverage, 1193,
24503 /* 64495 */ GIR_Done,
24504 /* 64496 */ // Label 1833: @64496
24505 /* 64496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1834*/ GIMT_Encode4(64510), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 1997 //
24506 /* 64503 */ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
24507 /* 64503 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
24508 /* 64508 */ GIR_RootConstrainSelectedInstOperands,
24509 /* 64509 */ // GIR_Coverage, 1997,
24510 /* 64509 */ GIR_Done,
24511 /* 64510 */ // Label 1834: @64510
24512 /* 64510 */ GIM_Reject,
24513 /* 64511 */ // Label 1828: @64511
24514 /* 64511 */ GIM_Reject,
24515 /* 64512 */ // Label 71: @64512
24516 /* 64512 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(8), /*)*//*default:*//*Label 1839*/ GIMT_Encode4(65103),
24517 /* 64523 */ /*GILLT_v16s8*//*Label 1835*/ GIMT_Encode4(64543), GIMT_Encode4(0),
24518 /* 64531 */ /*GILLT_v8s16*//*Label 1836*/ GIMT_Encode4(64649),
24519 /* 64535 */ /*GILLT_v4s32*//*Label 1837*/ GIMT_Encode4(64755),
24520 /* 64539 */ /*GILLT_v2s64*//*Label 1838*/ GIMT_Encode4(64929),
24521 /* 64543 */ // Label 1835: @64543
24522 /* 64543 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(64648),
24523 /* 64548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24524 /* 64551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24525 /* 64554 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1843*/ GIMT_Encode4(64647),
24526 /* 64565 */ /*GILLT_s32*//*Label 1841*/ GIMT_Encode4(64573),
24527 /* 64569 */ /*GILLT_s64*//*Label 1842*/ GIMT_Encode4(64610),
24528 /* 64573 */ // Label 1841: @64573
24529 /* 64573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1844*/ GIMT_Encode4(64609), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 846 //
24530 /* 64580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24531 /* 64584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24532 /* 64588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24533 /* 64592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24534 /* 64596 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24535 /* 64596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
24536 /* 64599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24537 /* 64601 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24538 /* 64603 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24539 /* 64605 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24540 /* 64607 */ GIR_RootConstrainSelectedInstOperands,
24541 /* 64608 */ // GIR_Coverage, 846,
24542 /* 64608 */ GIR_EraseRootFromParent_Done,
24543 /* 64609 */ // Label 1844: @64609
24544 /* 64609 */ GIM_Reject,
24545 /* 64610 */ // Label 1842: @64610
24546 /* 64610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(64646), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 852 //
24547 /* 64617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24548 /* 64621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24549 /* 64625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24550 /* 64629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24551 /* 64633 */ // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24552 /* 64633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
24553 /* 64636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24554 /* 64638 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24555 /* 64640 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24556 /* 64642 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24557 /* 64644 */ GIR_RootConstrainSelectedInstOperands,
24558 /* 64645 */ // GIR_Coverage, 852,
24559 /* 64645 */ GIR_EraseRootFromParent_Done,
24560 /* 64646 */ // Label 1845: @64646
24561 /* 64646 */ GIM_Reject,
24562 /* 64647 */ // Label 1843: @64647
24563 /* 64647 */ GIM_Reject,
24564 /* 64648 */ // Label 1840: @64648
24565 /* 64648 */ GIM_Reject,
24566 /* 64649 */ // Label 1836: @64649
24567 /* 64649 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(64754),
24568 /* 64654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24569 /* 64657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24570 /* 64660 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1849*/ GIMT_Encode4(64753),
24571 /* 64671 */ /*GILLT_s32*//*Label 1847*/ GIMT_Encode4(64679),
24572 /* 64675 */ /*GILLT_s64*//*Label 1848*/ GIMT_Encode4(64716),
24573 /* 64679 */ // Label 1847: @64679
24574 /* 64679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1850*/ GIMT_Encode4(64715), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 847 //
24575 /* 64686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24576 /* 64690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24577 /* 64694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24578 /* 64698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24579 /* 64702 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24580 /* 64702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
24581 /* 64705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24582 /* 64707 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24583 /* 64709 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24584 /* 64711 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24585 /* 64713 */ GIR_RootConstrainSelectedInstOperands,
24586 /* 64714 */ // GIR_Coverage, 847,
24587 /* 64714 */ GIR_EraseRootFromParent_Done,
24588 /* 64715 */ // Label 1850: @64715
24589 /* 64715 */ GIM_Reject,
24590 /* 64716 */ // Label 1848: @64716
24591 /* 64716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1851*/ GIMT_Encode4(64752), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 853 //
24592 /* 64723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24593 /* 64727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24594 /* 64731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24595 /* 64735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24596 /* 64739 */ // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24597 /* 64739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
24598 /* 64742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24599 /* 64744 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24600 /* 64746 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24601 /* 64748 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24602 /* 64750 */ GIR_RootConstrainSelectedInstOperands,
24603 /* 64751 */ // GIR_Coverage, 853,
24604 /* 64751 */ GIR_EraseRootFromParent_Done,
24605 /* 64752 */ // Label 1851: @64752
24606 /* 64752 */ GIM_Reject,
24607 /* 64753 */ // Label 1849: @64753
24608 /* 64753 */ GIM_Reject,
24609 /* 64754 */ // Label 1846: @64754
24610 /* 64754 */ GIM_Reject,
24611 /* 64755 */ // Label 1837: @64755
24612 /* 64755 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(64928),
24613 /* 64760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24614 /* 64763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24615 /* 64766 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1855*/ GIMT_Encode4(64927),
24616 /* 64777 */ /*GILLT_s32*//*Label 1853*/ GIMT_Encode4(64785),
24617 /* 64781 */ /*GILLT_s64*//*Label 1854*/ GIMT_Encode4(64856),
24618 /* 64785 */ // Label 1853: @64785
24619 /* 64785 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(64855),
24620 /* 64790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24621 /* 64794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24622 /* 64798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1857*/ GIMT_Encode4(64826), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 848 //
24623 /* 64805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24624 /* 64809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24625 /* 64813 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24626 /* 64813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
24627 /* 64816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24628 /* 64818 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24629 /* 64820 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24630 /* 64822 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24631 /* 64824 */ GIR_RootConstrainSelectedInstOperands,
24632 /* 64825 */ // GIR_Coverage, 848,
24633 /* 64825 */ GIR_EraseRootFromParent_Done,
24634 /* 64826 */ // Label 1857: @64826
24635 /* 64826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1858*/ GIMT_Encode4(64854), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 850 //
24636 /* 64833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24637 /* 64837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24638 /* 64841 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24639 /* 64841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
24640 /* 64844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24641 /* 64846 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24642 /* 64848 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24643 /* 64850 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24644 /* 64852 */ GIR_RootConstrainSelectedInstOperands,
24645 /* 64853 */ // GIR_Coverage, 850,
24646 /* 64853 */ GIR_EraseRootFromParent_Done,
24647 /* 64854 */ // Label 1858: @64854
24648 /* 64854 */ GIM_Reject,
24649 /* 64855 */ // Label 1856: @64855
24650 /* 64855 */ GIM_Reject,
24651 /* 64856 */ // Label 1854: @64856
24652 /* 64856 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(64926),
24653 /* 64861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24654 /* 64865 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24655 /* 64869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1860*/ GIMT_Encode4(64897), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 854 //
24656 /* 64876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24657 /* 64880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24658 /* 64884 */ // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
24659 /* 64884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
24660 /* 64887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24661 /* 64889 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24662 /* 64891 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24663 /* 64893 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24664 /* 64895 */ GIR_RootConstrainSelectedInstOperands,
24665 /* 64896 */ // GIR_Coverage, 854,
24666 /* 64896 */ GIR_EraseRootFromParent_Done,
24667 /* 64897 */ // Label 1860: @64897
24668 /* 64897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1861*/ GIMT_Encode4(64925), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 856 //
24669 /* 64904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24670 /* 64908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24671 /* 64912 */ // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
24672 /* 64912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
24673 /* 64915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24674 /* 64917 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24675 /* 64919 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24676 /* 64921 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24677 /* 64923 */ GIR_RootConstrainSelectedInstOperands,
24678 /* 64924 */ // GIR_Coverage, 856,
24679 /* 64924 */ GIR_EraseRootFromParent_Done,
24680 /* 64925 */ // Label 1861: @64925
24681 /* 64925 */ GIM_Reject,
24682 /* 64926 */ // Label 1859: @64926
24683 /* 64926 */ GIM_Reject,
24684 /* 64927 */ // Label 1855: @64927
24685 /* 64927 */ GIM_Reject,
24686 /* 64928 */ // Label 1852: @64928
24687 /* 64928 */ GIM_Reject,
24688 /* 64929 */ // Label 1838: @64929
24689 /* 64929 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(65102),
24690 /* 64934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24691 /* 64937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24692 /* 64940 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1865*/ GIMT_Encode4(65101),
24693 /* 64951 */ /*GILLT_s32*//*Label 1863*/ GIMT_Encode4(64959),
24694 /* 64955 */ /*GILLT_s64*//*Label 1864*/ GIMT_Encode4(65030),
24695 /* 64959 */ // Label 1863: @64959
24696 /* 64959 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(65029),
24697 /* 64964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24698 /* 64968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24699 /* 64972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1867*/ GIMT_Encode4(65000), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 849 //
24700 /* 64979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24701 /* 64983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24702 /* 64987 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24703 /* 64987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
24704 /* 64990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24705 /* 64992 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24706 /* 64994 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24707 /* 64996 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24708 /* 64998 */ GIR_RootConstrainSelectedInstOperands,
24709 /* 64999 */ // GIR_Coverage, 849,
24710 /* 64999 */ GIR_EraseRootFromParent_Done,
24711 /* 65000 */ // Label 1867: @65000
24712 /* 65000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1868*/ GIMT_Encode4(65028), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 851 //
24713 /* 65007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24714 /* 65011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24715 /* 65015 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24716 /* 65015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
24717 /* 65018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24718 /* 65020 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24719 /* 65022 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24720 /* 65024 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24721 /* 65026 */ GIR_RootConstrainSelectedInstOperands,
24722 /* 65027 */ // GIR_Coverage, 851,
24723 /* 65027 */ GIR_EraseRootFromParent_Done,
24724 /* 65028 */ // Label 1868: @65028
24725 /* 65028 */ GIM_Reject,
24726 /* 65029 */ // Label 1866: @65029
24727 /* 65029 */ GIM_Reject,
24728 /* 65030 */ // Label 1864: @65030
24729 /* 65030 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(65100),
24730 /* 65035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24731 /* 65039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24732 /* 65043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1870*/ GIMT_Encode4(65071), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 855 //
24733 /* 65050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24734 /* 65054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24735 /* 65058 */ // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
24736 /* 65058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
24737 /* 65061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24738 /* 65063 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24739 /* 65065 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24740 /* 65067 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24741 /* 65069 */ GIR_RootConstrainSelectedInstOperands,
24742 /* 65070 */ // GIR_Coverage, 855,
24743 /* 65070 */ GIR_EraseRootFromParent_Done,
24744 /* 65071 */ // Label 1870: @65071
24745 /* 65071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1871*/ GIMT_Encode4(65099), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 857 //
24746 /* 65078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24747 /* 65082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24748 /* 65086 */ // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
24749 /* 65086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
24750 /* 65089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
24751 /* 65091 */ GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
24752 /* 65093 */ GIR_RootToRootCopy, /*OpIdx*/3, // n
24753 /* 65095 */ GIR_RootToRootCopy, /*OpIdx*/2, // fs
24754 /* 65097 */ GIR_RootConstrainSelectedInstOperands,
24755 /* 65098 */ // GIR_Coverage, 857,
24756 /* 65098 */ GIR_EraseRootFromParent_Done,
24757 /* 65099 */ // Label 1871: @65099
24758 /* 65099 */ GIM_Reject,
24759 /* 65100 */ // Label 1869: @65100
24760 /* 65100 */ GIM_Reject,
24761 /* 65101 */ // Label 1865: @65101
24762 /* 65101 */ GIM_Reject,
24763 /* 65102 */ // Label 1862: @65102
24764 /* 65102 */ GIM_Reject,
24765 /* 65103 */ // Label 1839: @65103
24766 /* 65103 */ GIM_Reject,
24767 /* 65104 */ // Label 72: @65104
24768 /* 65104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1872*/ GIMT_Encode4(65154), GIMT_Encode2(GIFBS_HasMSA), // Rule ID 2124 //
24769 /* 65111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24770 /* 65114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24771 /* 65117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24772 /* 65120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24773 /* 65124 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24774 /* 65128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
24775 /* 65132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24776 /* 65136 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
24777 /* 65140 */ // MIs[1] Operand 1
24778 /* 65140 */ // No operand predicates
24779 /* 65140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24780 /* 65142 */ // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
24781 /* 65142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
24782 /* 65145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24783 /* 65147 */ GIR_RootToRootCopy, /*OpIdx*/1, // ws
24784 /* 65149 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
24785 /* 65152 */ GIR_RootConstrainSelectedInstOperands,
24786 /* 65153 */ // GIR_Coverage, 2124,
24787 /* 65153 */ GIR_EraseRootFromParent_Done,
24788 /* 65154 */ // Label 1872: @65154
24789 /* 65154 */ GIM_Reject,
24790 /* 65155 */ // Label 73: @65155
24791 /* 65155 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1879*/ GIMT_Encode4(65645),
24792 /* 65166 */ /*GILLT_s32*//*Label 1873*/ GIMT_Encode4(65198),
24793 /* 65170 */ /*GILLT_s64*//*Label 1874*/ GIMT_Encode4(65399), GIMT_Encode4(0),
24794 /* 65178 */ /*GILLT_v16s8*//*Label 1875*/ GIMT_Encode4(65541), GIMT_Encode4(0),
24795 /* 65186 */ /*GILLT_v8s16*//*Label 1876*/ GIMT_Encode4(65567),
24796 /* 65190 */ /*GILLT_v4s32*//*Label 1877*/ GIMT_Encode4(65593),
24797 /* 65194 */ /*GILLT_v2s64*//*Label 1878*/ GIMT_Encode4(65619),
24798 /* 65198 */ // Label 1873: @65198
24799 /* 65198 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(65398),
24800 /* 65203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24801 /* 65206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24802 /* 65210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1881*/ GIMT_Encode4(65255), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 109 //
24803 /* 65217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24804 /* 65221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
24805 /* 65225 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24806 /* 65229 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24807 /* 65233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24808 /* 65238 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
24809 /* 65242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24810 /* 65244 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24811 /* 65244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
24812 /* 65247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24813 /* 65249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24814 /* 65253 */ GIR_RootConstrainSelectedInstOperands,
24815 /* 65254 */ // GIR_Coverage, 109,
24816 /* 65254 */ GIR_EraseRootFromParent_Done,
24817 /* 65255 */ // Label 1881: @65255
24818 /* 65255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1882*/ GIMT_Encode4(65300), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 338 //
24819 /* 65262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24820 /* 65266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
24821 /* 65270 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24822 /* 65274 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24823 /* 65278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24824 /* 65283 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
24825 /* 65287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24826 /* 65289 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24827 /* 65289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
24828 /* 65292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24829 /* 65294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24830 /* 65298 */ GIR_RootConstrainSelectedInstOperands,
24831 /* 65299 */ // GIR_Coverage, 338,
24832 /* 65299 */ GIR_EraseRootFromParent_Done,
24833 /* 65300 */ // Label 1882: @65300
24834 /* 65300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1883*/ GIMT_Encode4(65345), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1122 //
24835 /* 65307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24836 /* 65311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
24837 /* 65315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
24838 /* 65319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
24839 /* 65323 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24840 /* 65328 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
24841 /* 65332 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24842 /* 65334 */ // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24843 /* 65334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
24844 /* 65337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24845 /* 65339 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24846 /* 65343 */ GIR_RootConstrainSelectedInstOperands,
24847 /* 65344 */ // GIR_Coverage, 1122,
24848 /* 65344 */ GIR_EraseRootFromParent_Done,
24849 /* 65345 */ // Label 1883: @65345
24850 /* 65345 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(65397),
24851 /* 65350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24852 /* 65354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1885*/ GIMT_Encode4(65368), GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 108 //
24853 /* 65361 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24854 /* 65361 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
24855 /* 65366 */ GIR_RootConstrainSelectedInstOperands,
24856 /* 65367 */ // GIR_Coverage, 108,
24857 /* 65367 */ GIR_Done,
24858 /* 65368 */ // Label 1885: @65368
24859 /* 65368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1886*/ GIMT_Encode4(65382), GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc), // Rule ID 339 //
24860 /* 65375 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24861 /* 65375 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
24862 /* 65380 */ GIR_RootConstrainSelectedInstOperands,
24863 /* 65381 */ // GIR_Coverage, 339,
24864 /* 65381 */ GIR_Done,
24865 /* 65382 */ // Label 1886: @65382
24866 /* 65382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1887*/ GIMT_Encode4(65396), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1121 //
24867 /* 65389 */ // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24868 /* 65389 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
24869 /* 65394 */ GIR_RootConstrainSelectedInstOperands,
24870 /* 65395 */ // GIR_Coverage, 1121,
24871 /* 65395 */ GIR_Done,
24872 /* 65396 */ // Label 1887: @65396
24873 /* 65396 */ GIM_Reject,
24874 /* 65397 */ // Label 1884: @65397
24875 /* 65397 */ GIM_Reject,
24876 /* 65398 */ // Label 1880: @65398
24877 /* 65398 */ GIM_Reject,
24878 /* 65399 */ // Label 1874: @65399
24879 /* 65399 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(65540),
24880 /* 65404 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24881 /* 65407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24882 /* 65411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1889*/ GIMT_Encode4(65456), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 292 //
24883 /* 65418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24884 /* 65422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
24885 /* 65426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24886 /* 65430 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24887 /* 65434 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24888 /* 65439 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
24889 /* 65443 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24890 /* 65445 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24891 /* 65445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
24892 /* 65448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24893 /* 65450 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24894 /* 65454 */ GIR_RootConstrainSelectedInstOperands,
24895 /* 65455 */ // GIR_Coverage, 292,
24896 /* 65455 */ GIR_EraseRootFromParent_Done,
24897 /* 65456 */ // Label 1889: @65456
24898 /* 65456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1890*/ GIMT_Encode4(65501), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 367 //
24899 /* 65463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24900 /* 65467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
24901 /* 65471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24902 /* 65475 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24903 /* 65479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24904 /* 65484 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
24905 /* 65488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24906 /* 65490 */ // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24907 /* 65490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
24908 /* 65493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
24909 /* 65495 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
24910 /* 65499 */ GIR_RootConstrainSelectedInstOperands,
24911 /* 65500 */ // GIR_Coverage, 367,
24912 /* 65500 */ GIR_EraseRootFromParent_Done,
24913 /* 65501 */ // Label 1890: @65501
24914 /* 65501 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(65539),
24915 /* 65506 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24916 /* 65510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1892*/ GIMT_Encode4(65524), GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6), // Rule ID 291 //
24917 /* 65517 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24918 /* 65517 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
24919 /* 65522 */ GIR_RootConstrainSelectedInstOperands,
24920 /* 65523 */ // GIR_Coverage, 291,
24921 /* 65523 */ GIR_Done,
24922 /* 65524 */ // Label 1892: @65524
24923 /* 65524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1893*/ GIMT_Encode4(65538), GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips), // Rule ID 368 //
24924 /* 65531 */ // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
24925 /* 65531 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
24926 /* 65536 */ GIR_RootConstrainSelectedInstOperands,
24927 /* 65537 */ // GIR_Coverage, 368,
24928 /* 65537 */ GIR_Done,
24929 /* 65538 */ // Label 1893: @65538
24930 /* 65538 */ GIM_Reject,
24931 /* 65539 */ // Label 1891: @65539
24932 /* 65539 */ GIM_Reject,
24933 /* 65540 */ // Label 1888: @65540
24934 /* 65540 */ GIM_Reject,
24935 /* 65541 */ // Label 1875: @65541
24936 /* 65541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1894*/ GIMT_Encode4(65566), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 940 //
24937 /* 65548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24938 /* 65551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24939 /* 65555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24940 /* 65559 */ // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
24941 /* 65559 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
24942 /* 65564 */ GIR_RootConstrainSelectedInstOperands,
24943 /* 65565 */ // GIR_Coverage, 940,
24944 /* 65565 */ GIR_Done,
24945 /* 65566 */ // Label 1894: @65566
24946 /* 65566 */ GIM_Reject,
24947 /* 65567 */ // Label 1876: @65567
24948 /* 65567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1895*/ GIMT_Encode4(65592), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 941 //
24949 /* 65574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24950 /* 65577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24951 /* 65581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24952 /* 65585 */ // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
24953 /* 65585 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
24954 /* 65590 */ GIR_RootConstrainSelectedInstOperands,
24955 /* 65591 */ // GIR_Coverage, 941,
24956 /* 65591 */ GIR_Done,
24957 /* 65592 */ // Label 1895: @65592
24958 /* 65592 */ GIM_Reject,
24959 /* 65593 */ // Label 1877: @65593
24960 /* 65593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1896*/ GIMT_Encode4(65618), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 942 //
24961 /* 65600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24962 /* 65603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24963 /* 65607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24964 /* 65611 */ // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24965 /* 65611 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
24966 /* 65616 */ GIR_RootConstrainSelectedInstOperands,
24967 /* 65617 */ // GIR_Coverage, 942,
24968 /* 65617 */ GIR_Done,
24969 /* 65618 */ // Label 1896: @65618
24970 /* 65618 */ GIM_Reject,
24971 /* 65619 */ // Label 1878: @65619
24972 /* 65619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1897*/ GIMT_Encode4(65644), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 943 //
24973 /* 65626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24974 /* 65629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24975 /* 65633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24976 /* 65637 */ // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24977 /* 65637 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
24978 /* 65642 */ GIR_RootConstrainSelectedInstOperands,
24979 /* 65643 */ // GIR_Coverage, 943,
24980 /* 65643 */ GIR_Done,
24981 /* 65644 */ // Label 1897: @65644
24982 /* 65644 */ GIM_Reject,
24983 /* 65645 */ // Label 1879: @65645
24984 /* 65645 */ GIM_Reject,
24985 /* 65646 */ // Label 74: @65646
24986 /* 65646 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1904*/ GIMT_Encode4(65845),
24987 /* 65657 */ /*GILLT_s32*//*Label 1898*/ GIMT_Encode4(65689),
24988 /* 65661 */ /*GILLT_s64*//*Label 1899*/ GIMT_Encode4(65715), GIMT_Encode4(0),
24989 /* 65669 */ /*GILLT_v16s8*//*Label 1900*/ GIMT_Encode4(65741), GIMT_Encode4(0),
24990 /* 65677 */ /*GILLT_v8s16*//*Label 1901*/ GIMT_Encode4(65767),
24991 /* 65681 */ /*GILLT_v4s32*//*Label 1902*/ GIMT_Encode4(65793),
24992 /* 65685 */ /*GILLT_v2s64*//*Label 1903*/ GIMT_Encode4(65819),
24993 /* 65689 */ // Label 1898: @65689
24994 /* 65689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1905*/ GIMT_Encode4(65714), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 306 //
24995 /* 65696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24996 /* 65699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24997 /* 65703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24998 /* 65707 */ // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
24999 /* 65707 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
25000 /* 65712 */ GIR_RootConstrainSelectedInstOperands,
25001 /* 65713 */ // GIR_Coverage, 306,
25002 /* 65713 */ GIR_Done,
25003 /* 65714 */ // Label 1905: @65714
25004 /* 65714 */ GIM_Reject,
25005 /* 65715 */ // Label 1899: @65715
25006 /* 65715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1906*/ GIMT_Encode4(65740), GIMT_Encode2(GIFBS_HasCnMips), // Rule ID 307 //
25007 /* 65722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25008 /* 65725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25009 /* 65729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25010 /* 65733 */ // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25011 /* 65733 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
25012 /* 65738 */ GIR_RootConstrainSelectedInstOperands,
25013 /* 65739 */ // GIR_Coverage, 307,
25014 /* 65739 */ GIR_Done,
25015 /* 65740 */ // Label 1906: @65740
25016 /* 65740 */ GIM_Reject,
25017 /* 65741 */ // Label 1900: @65741
25018 /* 65741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1907*/ GIMT_Encode4(65766), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 962 //
25019 /* 65748 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25020 /* 65751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25021 /* 65755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25022 /* 65759 */ // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
25023 /* 65759 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
25024 /* 65764 */ GIR_RootConstrainSelectedInstOperands,
25025 /* 65765 */ // GIR_Coverage, 962,
25026 /* 65765 */ GIR_Done,
25027 /* 65766 */ // Label 1907: @65766
25028 /* 65766 */ GIM_Reject,
25029 /* 65767 */ // Label 1901: @65767
25030 /* 65767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1908*/ GIMT_Encode4(65792), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 963 //
25031 /* 65774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25032 /* 65777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25033 /* 65781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25034 /* 65785 */ // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
25035 /* 65785 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
25036 /* 65790 */ GIR_RootConstrainSelectedInstOperands,
25037 /* 65791 */ // GIR_Coverage, 963,
25038 /* 65791 */ GIR_Done,
25039 /* 65792 */ // Label 1908: @65792
25040 /* 65792 */ GIM_Reject,
25041 /* 65793 */ // Label 1902: @65793
25042 /* 65793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1909*/ GIMT_Encode4(65818), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 964 //
25043 /* 65800 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25044 /* 65803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25045 /* 65807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25046 /* 65811 */ // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25047 /* 65811 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
25048 /* 65816 */ GIR_RootConstrainSelectedInstOperands,
25049 /* 65817 */ // GIR_Coverage, 964,
25050 /* 65817 */ GIR_Done,
25051 /* 65818 */ // Label 1909: @65818
25052 /* 65818 */ GIM_Reject,
25053 /* 65819 */ // Label 1903: @65819
25054 /* 65819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1910*/ GIMT_Encode4(65844), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 965 //
25055 /* 65826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25056 /* 65829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25057 /* 65833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25058 /* 65837 */ // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25059 /* 65837 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
25060 /* 65842 */ GIR_RootConstrainSelectedInstOperands,
25061 /* 65843 */ // GIR_Coverage, 965,
25062 /* 65843 */ GIR_Done,
25063 /* 65844 */ // Label 1910: @65844
25064 /* 65844 */ GIM_Reject,
25065 /* 65845 */ // Label 1904: @65845
25066 /* 65845 */ GIM_Reject,
25067 /* 65846 */ // Label 75: @65846
25068 /* 65846 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1913*/ GIMT_Encode4(66006),
25069 /* 65857 */ /*GILLT_s32*//*Label 1911*/ GIMT_Encode4(65865),
25070 /* 65861 */ /*GILLT_s64*//*Label 1912*/ GIMT_Encode4(65959),
25071 /* 65865 */ // Label 1911: @65865
25072 /* 65865 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(65958),
25073 /* 65870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25074 /* 65873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25075 /* 65877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25076 /* 65881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1915*/ GIMT_Encode4(65919), GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips), // Rule ID 1449 //
25077 /* 65888 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25078 /* 65888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25079 /* 65891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
25080 /* 65895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25081 /* 65900 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25082 /* 65904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25083 /* 65906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
25084 /* 65909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25085 /* 65911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25086 /* 65914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25087 /* 65917 */ GIR_RootConstrainSelectedInstOperands,
25088 /* 65918 */ // GIR_Coverage, 1449,
25089 /* 65918 */ GIR_EraseRootFromParent_Done,
25090 /* 65919 */ // Label 1915: @65919
25091 /* 65919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1916*/ GIMT_Encode4(65957), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 2319 //
25092 /* 65926 */ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25093 /* 65926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25094 /* 65929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
25095 /* 65933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25096 /* 65938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25097 /* 65942 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25098 /* 65944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
25099 /* 65947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25100 /* 65949 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25101 /* 65952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25102 /* 65955 */ GIR_RootConstrainSelectedInstOperands,
25103 /* 65956 */ // GIR_Coverage, 2319,
25104 /* 65956 */ GIR_EraseRootFromParent_Done,
25105 /* 65957 */ // Label 1916: @65957
25106 /* 65957 */ GIM_Reject,
25107 /* 65958 */ // Label 1914: @65958
25108 /* 65958 */ GIM_Reject,
25109 /* 65959 */ // Label 1912: @65959
25110 /* 65959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1917*/ GIMT_Encode4(66005), GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc), // Rule ID 1695 //
25111 /* 65966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25112 /* 65969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25113 /* 65973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25114 /* 65977 */ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
25115 /* 65977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25116 /* 65980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
25117 /* 65984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25118 /* 65989 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25119 /* 65993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25120 /* 65995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
25121 /* 65998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25122 /* 66000 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25123 /* 66003 */ GIR_RootConstrainSelectedInstOperands,
25124 /* 66004 */ // GIR_Coverage, 1695,
25125 /* 66004 */ GIR_EraseRootFromParent_Done,
25126 /* 66005 */ // Label 1917: @66005
25127 /* 66005 */ GIM_Reject,
25128 /* 66006 */ // Label 1913: @66006
25129 /* 66006 */ GIM_Reject,
25130 /* 66007 */ // Label 76: @66007
25131 /* 66007 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1922*/ GIMT_Encode4(66270),
25132 /* 66018 */ /*GILLT_s32*//*Label 1918*/ GIMT_Encode4(66050),
25133 /* 66022 */ /*GILLT_s64*//*Label 1919*/ GIMT_Encode4(66104), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
25134 /* 66042 */ /*GILLT_v4s32*//*Label 1920*/ GIMT_Encode4(66218),
25135 /* 66046 */ /*GILLT_v2s64*//*Label 1921*/ GIMT_Encode4(66244),
25136 /* 66050 */ // Label 1918: @66050
25137 /* 66050 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(66103),
25138 /* 66055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25139 /* 66058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25140 /* 66062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25141 /* 66066 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1924*/ GIMT_Encode4(66084), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 133 //
25142 /* 66073 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25143 /* 66073 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
25144 /* 66078 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25145 /* 66082 */ GIR_RootConstrainSelectedInstOperands,
25146 /* 66083 */ // GIR_Coverage, 133,
25147 /* 66083 */ GIR_Done,
25148 /* 66084 */ // Label 1924: @66084
25149 /* 66084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1925*/ GIMT_Encode4(66102), GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat), // Rule ID 1184 //
25150 /* 66091 */ // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25151 /* 66091 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
25152 /* 66096 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25153 /* 66100 */ GIR_RootConstrainSelectedInstOperands,
25154 /* 66101 */ // GIR_Coverage, 1184,
25155 /* 66101 */ GIR_Done,
25156 /* 66102 */ // Label 1925: @66102
25157 /* 66102 */ GIM_Reject,
25158 /* 66103 */ // Label 1923: @66103
25159 /* 66103 */ GIM_Reject,
25160 /* 66104 */ // Label 1919: @66104
25161 /* 66104 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(66217),
25162 /* 66109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25163 /* 66112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1927*/ GIMT_Encode4(66138), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 135 //
25164 /* 66119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25165 /* 66123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25166 /* 66127 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25167 /* 66127 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
25168 /* 66132 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25169 /* 66136 */ GIR_RootConstrainSelectedInstOperands,
25170 /* 66137 */ // GIR_Coverage, 135,
25171 /* 66137 */ GIR_Done,
25172 /* 66138 */ // Label 1927: @66138
25173 /* 66138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1928*/ GIMT_Encode4(66164), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 137 //
25174 /* 66145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25175 /* 66149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25176 /* 66153 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25177 /* 66153 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
25178 /* 66158 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25179 /* 66162 */ GIR_RootConstrainSelectedInstOperands,
25180 /* 66163 */ // GIR_Coverage, 137,
25181 /* 66163 */ GIR_Done,
25182 /* 66164 */ // Label 1928: @66164
25183 /* 66164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1929*/ GIMT_Encode4(66190), GIMT_Encode2(GIFBS_InMicroMips_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit), // Rule ID 1170 //
25184 /* 66171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25185 /* 66175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25186 /* 66179 */ // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25187 /* 66179 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
25188 /* 66184 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25189 /* 66188 */ GIR_RootConstrainSelectedInstOperands,
25190 /* 66189 */ // GIR_Coverage, 1170,
25191 /* 66189 */ GIR_Done,
25192 /* 66190 */ // Label 1929: @66190
25193 /* 66190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1930*/ GIMT_Encode4(66216), GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat), // Rule ID 1171 //
25194 /* 66197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25195 /* 66201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25196 /* 66205 */ // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25197 /* 66205 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
25198 /* 66210 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25199 /* 66214 */ GIR_RootConstrainSelectedInstOperands,
25200 /* 66215 */ // GIR_Coverage, 1171,
25201 /* 66215 */ GIR_Done,
25202 /* 66216 */ // Label 1930: @66216
25203 /* 66216 */ GIM_Reject,
25204 /* 66217 */ // Label 1926: @66217
25205 /* 66217 */ GIM_Reject,
25206 /* 66218 */ // Label 1920: @66218
25207 /* 66218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1931*/ GIMT_Encode4(66243), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 784 //
25208 /* 66225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25209 /* 66228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25210 /* 66232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25211 /* 66236 */ // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25212 /* 66236 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
25213 /* 66241 */ GIR_RootConstrainSelectedInstOperands,
25214 /* 66242 */ // GIR_Coverage, 784,
25215 /* 66242 */ GIR_Done,
25216 /* 66243 */ // Label 1931: @66243
25217 /* 66243 */ GIM_Reject,
25218 /* 66244 */ // Label 1921: @66244
25219 /* 66244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1932*/ GIMT_Encode4(66269), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 785 //
25220 /* 66251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25221 /* 66254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25222 /* 66258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25223 /* 66262 */ // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25224 /* 66262 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
25225 /* 66267 */ GIR_RootConstrainSelectedInstOperands,
25226 /* 66268 */ // GIR_Coverage, 785,
25227 /* 66268 */ GIR_Done,
25228 /* 66269 */ // Label 1932: @66269
25229 /* 66269 */ GIM_Reject,
25230 /* 66270 */ // Label 1922: @66270
25231 /* 66270 */ GIM_Reject,
25232 /* 66271 */ // Label 77: @66271
25233 /* 66271 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1935*/ GIMT_Encode4(66342),
25234 /* 66282 */ /*GILLT_v4s32*//*Label 1933*/ GIMT_Encode4(66290),
25235 /* 66286 */ /*GILLT_v2s64*//*Label 1934*/ GIMT_Encode4(66316),
25236 /* 66290 */ // Label 1933: @66290
25237 /* 66290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(66315), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 766 //
25238 /* 66297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25239 /* 66300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25240 /* 66304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25241 /* 66308 */ // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25242 /* 66308 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
25243 /* 66313 */ GIR_RootConstrainSelectedInstOperands,
25244 /* 66314 */ // GIR_Coverage, 766,
25245 /* 66314 */ GIR_Done,
25246 /* 66315 */ // Label 1936: @66315
25247 /* 66315 */ GIM_Reject,
25248 /* 66316 */ // Label 1934: @66316
25249 /* 66316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1937*/ GIMT_Encode4(66341), GIMT_Encode2(GIFBS_HasMSA_HasStdEnc), // Rule ID 767 //
25250 /* 66323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25251 /* 66326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25252 /* 66330 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25253 /* 66334 */ // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25254 /* 66334 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
25255 /* 66339 */ GIR_RootConstrainSelectedInstOperands,
25256 /* 66340 */ // GIR_Coverage, 767,
25257 /* 66340 */ GIR_Done,
25258 /* 66341 */ // Label 1937: @66341
25259 /* 66341 */ GIM_Reject,
25260 /* 66342 */ // Label 1935: @66342
25261 /* 66342 */ GIM_Reject,
25262 /* 66343 */ // Label 78: @66343
25263 /* 66343 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1940*/ GIMT_Encode4(67182),
25264 /* 66354 */ /*GILLT_s32*//*Label 1938*/ GIMT_Encode4(66362),
25265 /* 66358 */ /*GILLT_s64*//*Label 1939*/ GIMT_Encode4(66629),
25266 /* 66362 */ // Label 1938: @66362
25267 /* 66362 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(66628),
25268 /* 66367 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25269 /* 66370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25270 /* 66373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25271 /* 66377 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(66491),
25272 /* 66382 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25273 /* 66386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(66438), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 179 //
25274 /* 66393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25275 /* 66397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25276 /* 66401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25277 /* 66405 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25278 /* 66409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25279 /* 66414 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25280 /* 66419 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25281 /* 66421 */ // (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25282 /* 66421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25283 /* 66424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25284 /* 66426 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25285 /* 66428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25286 /* 66432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25287 /* 66436 */ GIR_RootConstrainSelectedInstOperands,
25288 /* 66437 */ // GIR_Coverage, 179,
25289 /* 66437 */ GIR_EraseRootFromParent_Done,
25290 /* 66438 */ // Label 1943: @66438
25291 /* 66438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(66490), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 178 //
25292 /* 66445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25293 /* 66449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25294 /* 66453 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25295 /* 66457 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25296 /* 66461 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25297 /* 66466 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25298 /* 66471 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25299 /* 66473 */ // (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25300 /* 66473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25301 /* 66476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25302 /* 66478 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25303 /* 66480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25304 /* 66484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25305 /* 66488 */ GIR_RootConstrainSelectedInstOperands,
25306 /* 66489 */ // GIR_Coverage, 178,
25307 /* 66489 */ GIR_EraseRootFromParent_Done,
25308 /* 66490 */ // Label 1944: @66490
25309 /* 66490 */ GIM_Reject,
25310 /* 66491 */ // Label 1942: @66491
25311 /* 66491 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(66627),
25312 /* 66496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25313 /* 66500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(66552), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2490 //
25314 /* 66507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25315 /* 66511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25316 /* 66515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25317 /* 66519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25318 /* 66523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25319 /* 66528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25320 /* 66533 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25321 /* 66535 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25322 /* 66535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25323 /* 66538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25324 /* 66540 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25325 /* 66542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25326 /* 66546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25327 /* 66550 */ GIR_RootConstrainSelectedInstOperands,
25328 /* 66551 */ // GIR_Coverage, 2490,
25329 /* 66551 */ GIR_EraseRootFromParent_Done,
25330 /* 66552 */ // Label 1946: @66552
25331 /* 66552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(66604), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2489 //
25332 /* 66559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25333 /* 66563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25334 /* 66567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25335 /* 66571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25336 /* 66575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25337 /* 66580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25338 /* 66585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25339 /* 66587 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25340 /* 66587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
25341 /* 66590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25342 /* 66592 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25343 /* 66594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25344 /* 66598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25345 /* 66602 */ GIR_RootConstrainSelectedInstOperands,
25346 /* 66603 */ // GIR_Coverage, 2489,
25347 /* 66603 */ GIR_EraseRootFromParent_Done,
25348 /* 66604 */ // Label 1947: @66604
25349 /* 66604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(66626), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 154 //
25350 /* 66611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25351 /* 66615 */ // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25352 /* 66615 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
25353 /* 66620 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25354 /* 66624 */ GIR_RootConstrainSelectedInstOperands,
25355 /* 66625 */ // GIR_Coverage, 154,
25356 /* 66625 */ GIR_Done,
25357 /* 66626 */ // Label 1948: @66626
25358 /* 66626 */ GIM_Reject,
25359 /* 66627 */ // Label 1945: @66627
25360 /* 66627 */ GIM_Reject,
25361 /* 66628 */ // Label 1941: @66628
25362 /* 66628 */ GIM_Reject,
25363 /* 66629 */ // Label 1939: @66629
25364 /* 66629 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(67181),
25365 /* 66634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25366 /* 66637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25367 /* 66640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(66700), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 187 //
25368 /* 66647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25369 /* 66651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25370 /* 66655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25371 /* 66659 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25372 /* 66663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25373 /* 66667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25374 /* 66672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25375 /* 66677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25376 /* 66681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25377 /* 66683 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25378 /* 66683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25379 /* 66686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25380 /* 66688 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25381 /* 66690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25382 /* 66694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25383 /* 66698 */ GIR_RootConstrainSelectedInstOperands,
25384 /* 66699 */ // GIR_Coverage, 187,
25385 /* 66699 */ GIR_EraseRootFromParent_Done,
25386 /* 66700 */ // Label 1950: @66700
25387 /* 66700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(66760), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 195 //
25388 /* 66707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25389 /* 66711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25390 /* 66715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25391 /* 66719 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25392 /* 66723 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25393 /* 66727 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25394 /* 66732 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25395 /* 66737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25396 /* 66741 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25397 /* 66743 */ // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25398 /* 66743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25399 /* 66746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25400 /* 66748 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25401 /* 66750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25402 /* 66754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25403 /* 66758 */ GIR_RootConstrainSelectedInstOperands,
25404 /* 66759 */ // GIR_Coverage, 195,
25405 /* 66759 */ GIR_EraseRootFromParent_Done,
25406 /* 66760 */ // Label 1951: @66760
25407 /* 66760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1952*/ GIMT_Encode4(66820), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 186 //
25408 /* 66767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25409 /* 66771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25410 /* 66775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25411 /* 66779 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25412 /* 66783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25413 /* 66787 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25414 /* 66792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25415 /* 66797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25416 /* 66801 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25417 /* 66803 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25418 /* 66803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25419 /* 66806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25420 /* 66808 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25421 /* 66810 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25422 /* 66814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25423 /* 66818 */ GIR_RootConstrainSelectedInstOperands,
25424 /* 66819 */ // GIR_Coverage, 186,
25425 /* 66819 */ GIR_EraseRootFromParent_Done,
25426 /* 66820 */ // Label 1952: @66820
25427 /* 66820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1953*/ GIMT_Encode4(66880), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 194 //
25428 /* 66827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25429 /* 66831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25430 /* 66835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25431 /* 66839 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25432 /* 66843 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25433 /* 66847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25434 /* 66852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25435 /* 66857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25436 /* 66861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25437 /* 66863 */ // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25438 /* 66863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25439 /* 66866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25440 /* 66868 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25441 /* 66870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25442 /* 66874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25443 /* 66878 */ GIR_RootConstrainSelectedInstOperands,
25444 /* 66879 */ // GIR_Coverage, 194,
25445 /* 66879 */ GIR_EraseRootFromParent_Done,
25446 /* 66880 */ // Label 1953: @66880
25447 /* 66880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1954*/ GIMT_Encode4(66940), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2494 //
25448 /* 66887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25449 /* 66891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25450 /* 66895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25451 /* 66899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25452 /* 66903 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25453 /* 66907 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25454 /* 66911 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25455 /* 66916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25456 /* 66921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25457 /* 66923 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25458 /* 66923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25459 /* 66926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25460 /* 66928 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25461 /* 66930 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25462 /* 66934 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25463 /* 66938 */ GIR_RootConstrainSelectedInstOperands,
25464 /* 66939 */ // GIR_Coverage, 2494,
25465 /* 66939 */ GIR_EraseRootFromParent_Done,
25466 /* 66940 */ // Label 1954: @66940
25467 /* 66940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1955*/ GIMT_Encode4(67000), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2498 //
25468 /* 66947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25469 /* 66951 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25470 /* 66955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25471 /* 66959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25472 /* 66963 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25473 /* 66967 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25474 /* 66971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25475 /* 66976 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25476 /* 66981 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25477 /* 66983 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25478 /* 66983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25479 /* 66986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25480 /* 66988 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25481 /* 66990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25482 /* 66994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25483 /* 66998 */ GIR_RootConstrainSelectedInstOperands,
25484 /* 66999 */ // GIR_Coverage, 2498,
25485 /* 66999 */ GIR_EraseRootFromParent_Done,
25486 /* 67000 */ // Label 1955: @67000
25487 /* 67000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1956*/ GIMT_Encode4(67060), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2493 //
25488 /* 67007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25489 /* 67011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25490 /* 67015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25491 /* 67019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25492 /* 67023 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25493 /* 67027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25494 /* 67031 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25495 /* 67036 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25496 /* 67041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25497 /* 67043 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25498 /* 67043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
25499 /* 67046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25500 /* 67048 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25501 /* 67050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25502 /* 67054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25503 /* 67058 */ GIR_RootConstrainSelectedInstOperands,
25504 /* 67059 */ // GIR_Coverage, 2493,
25505 /* 67059 */ GIR_EraseRootFromParent_Done,
25506 /* 67060 */ // Label 1956: @67060
25507 /* 67060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(67120), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 2497 //
25508 /* 67067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25509 /* 67071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25510 /* 67075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25511 /* 67079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25512 /* 67083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25513 /* 67087 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25514 /* 67091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25515 /* 67096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25516 /* 67101 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25517 /* 67103 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25518 /* 67103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
25519 /* 67106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25520 /* 67108 */ GIR_RootToRootCopy, /*OpIdx*/1, // fr
25521 /* 67110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25522 /* 67114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25523 /* 67118 */ GIR_RootConstrainSelectedInstOperands,
25524 /* 67119 */ // GIR_Coverage, 2497,
25525 /* 67119 */ GIR_EraseRootFromParent_Done,
25526 /* 67120 */ // Label 1957: @67120
25527 /* 67120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(67150), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 156 //
25528 /* 67127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25529 /* 67131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25530 /* 67135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25531 /* 67139 */ // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25532 /* 67139 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
25533 /* 67144 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25534 /* 67148 */ GIR_RootConstrainSelectedInstOperands,
25535 /* 67149 */ // GIR_Coverage, 156,
25536 /* 67149 */ GIR_Done,
25537 /* 67150 */ // Label 1958: @67150
25538 /* 67150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(67180), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 158 //
25539 /* 67157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25540 /* 67161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25541 /* 67165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25542 /* 67169 */ // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25543 /* 67169 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
25544 /* 67174 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25545 /* 67178 */ GIR_RootConstrainSelectedInstOperands,
25546 /* 67179 */ // GIR_Coverage, 158,
25547 /* 67179 */ GIR_Done,
25548 /* 67180 */ // Label 1959: @67180
25549 /* 67180 */ GIM_Reject,
25550 /* 67181 */ // Label 1949: @67181
25551 /* 67181 */ GIM_Reject,
25552 /* 67182 */ // Label 1940: @67182
25553 /* 67182 */ GIM_Reject,
25554 /* 67183 */ // Label 79: @67183
25555 /* 67183 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1962*/ GIMT_Encode4(67672),
25556 /* 67194 */ /*GILLT_s32*//*Label 1960*/ GIMT_Encode4(67202),
25557 /* 67198 */ /*GILLT_s64*//*Label 1961*/ GIMT_Encode4(67359),
25558 /* 67202 */ // Label 1960: @67202
25559 /* 67202 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(67358),
25560 /* 67207 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25561 /* 67210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25562 /* 67213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25563 /* 67217 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(67331),
25564 /* 67222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25565 /* 67226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1965*/ GIMT_Encode4(67278), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 183 //
25566 /* 67233 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25567 /* 67237 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25568 /* 67241 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25569 /* 67245 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25570 /* 67249 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25571 /* 67254 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25572 /* 67259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25573 /* 67261 */ // (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25574 /* 67261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
25575 /* 67264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25576 /* 67266 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25577 /* 67268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25578 /* 67272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25579 /* 67276 */ GIR_RootConstrainSelectedInstOperands,
25580 /* 67277 */ // GIR_Coverage, 183,
25581 /* 67277 */ GIR_EraseRootFromParent_Done,
25582 /* 67278 */ // Label 1965: @67278
25583 /* 67278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(67330), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 182 //
25584 /* 67285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25585 /* 67289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25586 /* 67293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25587 /* 67297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25588 /* 67301 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25589 /* 67306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25590 /* 67311 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25591 /* 67313 */ // (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25592 /* 67313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
25593 /* 67316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25594 /* 67318 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25595 /* 67320 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25596 /* 67324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25597 /* 67328 */ GIR_RootConstrainSelectedInstOperands,
25598 /* 67329 */ // GIR_Coverage, 182,
25599 /* 67329 */ GIR_EraseRootFromParent_Done,
25600 /* 67330 */ // Label 1966: @67330
25601 /* 67330 */ GIM_Reject,
25602 /* 67331 */ // Label 1964: @67331
25603 /* 67331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(67357), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 172 //
25604 /* 67338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25605 /* 67342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25606 /* 67346 */ // (strict_fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25607 /* 67346 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
25608 /* 67351 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25609 /* 67355 */ GIR_RootConstrainSelectedInstOperands,
25610 /* 67356 */ // GIR_Coverage, 172,
25611 /* 67356 */ GIR_Done,
25612 /* 67357 */ // Label 1967: @67357
25613 /* 67357 */ GIM_Reject,
25614 /* 67358 */ // Label 1963: @67358
25615 /* 67358 */ GIM_Reject,
25616 /* 67359 */ // Label 1961: @67359
25617 /* 67359 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(67671),
25618 /* 67364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25619 /* 67367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25620 /* 67370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(67430), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 191 //
25621 /* 67377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25622 /* 67381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25623 /* 67385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25624 /* 67389 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25625 /* 67393 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25626 /* 67397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25627 /* 67402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25628 /* 67407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25629 /* 67411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25630 /* 67413 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25631 /* 67413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
25632 /* 67416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25633 /* 67418 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25634 /* 67420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25635 /* 67424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25636 /* 67428 */ GIR_RootConstrainSelectedInstOperands,
25637 /* 67429 */ // GIR_Coverage, 191,
25638 /* 67429 */ GIR_EraseRootFromParent_Done,
25639 /* 67430 */ // Label 1969: @67430
25640 /* 67430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(67490), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 199 //
25641 /* 67437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25642 /* 67441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25643 /* 67445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
25644 /* 67449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25645 /* 67453 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25646 /* 67457 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25647 /* 67462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25648 /* 67467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25649 /* 67471 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25650 /* 67473 */ // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25651 /* 67473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
25652 /* 67476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25653 /* 67478 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25654 /* 67480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25655 /* 67484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25656 /* 67488 */ GIR_RootConstrainSelectedInstOperands,
25657 /* 67489 */ // GIR_Coverage, 199,
25658 /* 67489 */ GIR_EraseRootFromParent_Done,
25659 /* 67490 */ // Label 1970: @67490
25660 /* 67490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(67550), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 190 //
25661 /* 67497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25662 /* 67501 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25663 /* 67505 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25664 /* 67509 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25665 /* 67513 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25666 /* 67517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25667 /* 67522 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25668 /* 67527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25669 /* 67531 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25670 /* 67533 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25671 /* 67533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
25672 /* 67536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25673 /* 67538 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25674 /* 67540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25675 /* 67544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25676 /* 67548 */ GIR_RootConstrainSelectedInstOperands,
25677 /* 67549 */ // GIR_Coverage, 190,
25678 /* 67549 */ GIR_EraseRootFromParent_Done,
25679 /* 67550 */ // Label 1971: @67550
25680 /* 67550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1972*/ GIMT_Encode4(67610), GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6), // Rule ID 198 //
25681 /* 67557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25682 /* 67561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25683 /* 67565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
25684 /* 67569 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25685 /* 67573 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25686 /* 67577 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25687 /* 67582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25688 /* 67587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25689 /* 67591 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25690 /* 67593 */ // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25691 /* 67593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
25692 /* 67596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
25693 /* 67598 */ GIR_RootToRootCopy, /*OpIdx*/2, // fr
25694 /* 67600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
25695 /* 67604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
25696 /* 67608 */ GIR_RootConstrainSelectedInstOperands,
25697 /* 67609 */ // GIR_Coverage, 198,
25698 /* 67609 */ GIR_EraseRootFromParent_Done,
25699 /* 67610 */ // Label 1972: @67610
25700 /* 67610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(67640), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 174 //
25701 /* 67617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25702 /* 67621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25703 /* 67625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25704 /* 67629 */ // (strict_fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25705 /* 67629 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
25706 /* 67634 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25707 /* 67638 */ GIR_RootConstrainSelectedInstOperands,
25708 /* 67639 */ // GIR_Coverage, 174,
25709 /* 67639 */ GIR_Done,
25710 /* 67640 */ // Label 1973: @67640
25711 /* 67640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1974*/ GIMT_Encode4(67670), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 176 //
25712 /* 67647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25713 /* 67651 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25714 /* 67655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25715 /* 67659 */ // (strict_fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25716 /* 67659 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
25717 /* 67664 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25718 /* 67668 */ GIR_RootConstrainSelectedInstOperands,
25719 /* 67669 */ // GIR_Coverage, 176,
25720 /* 67669 */ GIR_Done,
25721 /* 67670 */ // Label 1974: @67670
25722 /* 67670 */ GIM_Reject,
25723 /* 67671 */ // Label 1968: @67671
25724 /* 67671 */ GIM_Reject,
25725 /* 67672 */ // Label 1962: @67672
25726 /* 67672 */ GIM_Reject,
25727 /* 67673 */ // Label 80: @67673
25728 /* 67673 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1977*/ GIMT_Encode4(67802),
25729 /* 67684 */ /*GILLT_s32*//*Label 1975*/ GIMT_Encode4(67692),
25730 /* 67688 */ /*GILLT_s64*//*Label 1976*/ GIMT_Encode4(67729),
25731 /* 67692 */ // Label 1975: @67692
25732 /* 67692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(67728), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 166 //
25733 /* 67699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25734 /* 67702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25735 /* 67705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25736 /* 67709 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25737 /* 67713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25738 /* 67717 */ // (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25739 /* 67717 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
25740 /* 67722 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25741 /* 67726 */ GIR_RootConstrainSelectedInstOperands,
25742 /* 67727 */ // GIR_Coverage, 166,
25743 /* 67727 */ GIR_Done,
25744 /* 67728 */ // Label 1978: @67728
25745 /* 67728 */ GIM_Reject,
25746 /* 67729 */ // Label 1976: @67729
25747 /* 67729 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(67801),
25748 /* 67734 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25749 /* 67737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25750 /* 67740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1980*/ GIMT_Encode4(67770), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 168 //
25751 /* 67747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25752 /* 67751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25753 /* 67755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25754 /* 67759 */ // (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25755 /* 67759 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
25756 /* 67764 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25757 /* 67768 */ GIR_RootConstrainSelectedInstOperands,
25758 /* 67769 */ // GIR_Coverage, 168,
25759 /* 67769 */ GIR_Done,
25760 /* 67770 */ // Label 1980: @67770
25761 /* 67770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1981*/ GIMT_Encode4(67800), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 170 //
25762 /* 67777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25763 /* 67781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25764 /* 67785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25765 /* 67789 */ // (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25766 /* 67789 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
25767 /* 67794 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25768 /* 67798 */ GIR_RootConstrainSelectedInstOperands,
25769 /* 67799 */ // GIR_Coverage, 170,
25770 /* 67799 */ GIR_Done,
25771 /* 67800 */ // Label 1981: @67800
25772 /* 67800 */ GIM_Reject,
25773 /* 67801 */ // Label 1979: @67801
25774 /* 67801 */ GIM_Reject,
25775 /* 67802 */ // Label 1977: @67802
25776 /* 67802 */ GIM_Reject,
25777 /* 67803 */ // Label 81: @67803
25778 /* 67803 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1984*/ GIMT_Encode4(67932),
25779 /* 67814 */ /*GILLT_s32*//*Label 1982*/ GIMT_Encode4(67822),
25780 /* 67818 */ /*GILLT_s64*//*Label 1983*/ GIMT_Encode4(67859),
25781 /* 67822 */ // Label 1982: @67822
25782 /* 67822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1985*/ GIMT_Encode4(67858), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 160 //
25783 /* 67829 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25784 /* 67832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25785 /* 67835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25786 /* 67839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25787 /* 67843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25788 /* 67847 */ // (strict_fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
25789 /* 67847 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
25790 /* 67852 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25791 /* 67856 */ GIR_RootConstrainSelectedInstOperands,
25792 /* 67857 */ // GIR_Coverage, 160,
25793 /* 67857 */ GIR_Done,
25794 /* 67858 */ // Label 1985: @67858
25795 /* 67858 */ GIM_Reject,
25796 /* 67859 */ // Label 1983: @67859
25797 /* 67859 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(67931),
25798 /* 67864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25799 /* 67867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25800 /* 67870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1987*/ GIMT_Encode4(67900), GIMT_Encode2(GIFBS_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 162 //
25801 /* 67877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25802 /* 67881 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25803 /* 67885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25804 /* 67889 */ // (strict_fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
25805 /* 67889 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
25806 /* 67894 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25807 /* 67898 */ GIR_RootConstrainSelectedInstOperands,
25808 /* 67899 */ // GIR_Coverage, 162,
25809 /* 67899 */ GIR_Done,
25810 /* 67900 */ // Label 1987: @67900
25811 /* 67900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1988*/ GIMT_Encode4(67930), GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 164 //
25812 /* 67907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25813 /* 67911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25814 /* 67915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25815 /* 67919 */ // (strict_fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
25816 /* 67919 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
25817 /* 67924 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25818 /* 67928 */ GIR_RootConstrainSelectedInstOperands,
25819 /* 67929 */ // GIR_Coverage, 164,
25820 /* 67929 */ GIR_Done,
25821 /* 67930 */ // Label 1988: @67930
25822 /* 67930 */ GIM_Reject,
25823 /* 67931 */ // Label 1986: @67931
25824 /* 67931 */ GIM_Reject,
25825 /* 67932 */ // Label 1984: @67932
25826 /* 67932 */ GIM_Reject,
25827 /* 67933 */ // Label 82: @67933
25828 /* 67933 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1991*/ GIMT_Encode4(68044),
25829 /* 67944 */ /*GILLT_s32*//*Label 1989*/ GIMT_Encode4(67952),
25830 /* 67948 */ /*GILLT_s64*//*Label 1990*/ GIMT_Encode4(67982),
25831 /* 67952 */ // Label 1989: @67952
25832 /* 67952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1992*/ GIMT_Encode4(67981), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips), // Rule ID 132 //
25833 /* 67959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25834 /* 67962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25835 /* 67966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25836 /* 67970 */ // (strict_fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25837 /* 67970 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
25838 /* 67975 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25839 /* 67979 */ GIR_RootConstrainSelectedInstOperands,
25840 /* 67980 */ // GIR_Coverage, 132,
25841 /* 67980 */ GIR_Done,
25842 /* 67981 */ // Label 1992: @67981
25843 /* 67981 */ GIM_Reject,
25844 /* 67982 */ // Label 1990: @67982
25845 /* 67982 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(68043),
25846 /* 67987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25847 /* 67990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1994*/ GIMT_Encode4(68016), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSingleFloat_IsNotSoftFloat_NotFP64bit_NotInMicroMips), // Rule ID 134 //
25848 /* 67997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25849 /* 68001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25850 /* 68005 */ // (strict_fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25851 /* 68005 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
25852 /* 68010 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25853 /* 68014 */ GIR_RootConstrainSelectedInstOperands,
25854 /* 68015 */ // GIR_Coverage, 134,
25855 /* 68015 */ GIR_Done,
25856 /* 68016 */ // Label 1994: @68016
25857 /* 68016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1995*/ GIMT_Encode4(68042), GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSingleFloat_IsNotSoftFloat_NotInMicroMips), // Rule ID 136 //
25858 /* 68023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25859 /* 68027 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25860 /* 68031 */ // (strict_fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25861 /* 68031 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
25862 /* 68036 */ GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
25863 /* 68040 */ GIR_RootConstrainSelectedInstOperands,
25864 /* 68041 */ // GIR_Coverage, 136,
25865 /* 68041 */ GIR_Done,
25866 /* 68042 */ // Label 1995: @68042
25867 /* 68042 */ GIM_Reject,
25868 /* 68043 */ // Label 1993: @68043
25869 /* 68043 */ GIM_Reject,
25870 /* 68044 */ // Label 1991: @68044
25871 /* 68044 */ GIM_Reject,
25872 /* 68045 */ // Label 83: @68045
25873 /* 68045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(68059), GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips), // Rule ID 90 //
25874 /* 68052 */ // (trap) => (TRAP)
25875 /* 68052 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
25876 /* 68057 */ GIR_RootConstrainSelectedInstOperands,
25877 /* 68058 */ // GIR_Coverage, 90,
25878 /* 68058 */ GIR_Done,
25879 /* 68059 */ // Label 1996: @68059
25880 /* 68059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1997*/ GIMT_Encode4(68073), GIMT_Encode2(GIFBS_InMicroMips), // Rule ID 1137 //
25881 /* 68066 */ // (trap) => (TRAP_MM)
25882 /* 68066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
25883 /* 68071 */ GIR_RootConstrainSelectedInstOperands,
25884 /* 68072 */ // GIR_Coverage, 1137,
25885 /* 68072 */ GIR_Done,
25886 /* 68073 */ // Label 1997: @68073
25887 /* 68073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1998*/ GIMT_Encode4(68087), GIMT_Encode2(GIFBS_InMips16Mode), // Rule ID 2040 //
25888 /* 68080 */ // (trap) => (Break16)
25889 /* 68080 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
25890 /* 68085 */ GIR_RootConstrainSelectedInstOperands,
25891 /* 68086 */ // GIR_Coverage, 2040,
25892 /* 68086 */ GIR_Done,
25893 /* 68087 */ // Label 1998: @68087
25894 /* 68087 */ GIM_Reject,
25895 /* 68088 */ // Label 84: @68088
25896 /* 68088 */ GIM_Reject,
25897 /* 68089 */ }; // Size: 68089 bytes
25898 return MatchTable0;
25899}
25900#undef GIMT_Encode2
25901#undef GIMT_Encode4
25902#undef GIMT_Encode8
25903
25904
25905#endif // GET_GLOBALISEL_IMPL
25906
25907#ifdef GET_GLOBALISEL_PREDICATES_DECL
25908
25909PredicateBitset AvailableModuleFeatures;
25910mutable PredicateBitset AvailableFunctionFeatures;
25911PredicateBitset getAvailableFeatures() const {
25912 return AvailableModuleFeatures | AvailableFunctionFeatures;
25913}
25914PredicateBitset
25915computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
25916PredicateBitset
25917computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
25918 const MachineFunction *MF) const;
25919void setupGeneratedPerFunctionState(MachineFunction &MF) override;
25920
25921#endif // GET_GLOBALISEL_PREDICATES_DECL
25922
25923#ifdef GET_GLOBALISEL_PREDICATES_INIT
25924
25925AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
25926AvailableFunctionFeatures()
25927
25928#endif // GET_GLOBALISEL_PREDICATES_INIT
25929
25930